drivers/net/ethernet/broadcom/bnxt/bnxt.h

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  * Copyright (c) 2016-2018 Broadcom Limited
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  */
  10
  11 #ifndef BNXT_H
  12 #define BNXT_H
  13
  14 #define DRV_MODULE_NAME         "bnxt_en"
  15 #define DRV_MODULE_VERSION      "1.10.0"
  16
  17 #define DRV_VER_MAJ     1
  18 #define DRV_VER_MIN     10
  19 #define DRV_VER_UPD     0
  20
  21 #include <linux/interrupt.h>
  22 #include <linux/rhashtable.h>
  23 #include <linux/crash_dump.h>
  24 #include <net/devlink.h>
  25 #include <net/dst_metadata.h>
  26 #include <net/xdp.h>
  27 #include <linux/dim.h>
  28
  29 struct page_pool;
  30
  31 struct tx_bd {
  32         __le32 tx_bd_len_flags_type;
  33         #define TX_BD_TYPE                                      (0x3f << 0)
  34          #define TX_BD_TYPE_SHORT_TX_BD                          (0x00 << 0)
  35          #define TX_BD_TYPE_LONG_TX_BD                           (0x10 << 0)
  36         #define TX_BD_FLAGS_PACKET_END                          (1 << 6)
  37         #define TX_BD_FLAGS_NO_CMPL                             (1 << 7)
  38         #define TX_BD_FLAGS_BD_CNT                              (0x1f << 8)
  39          #define TX_BD_FLAGS_BD_CNT_SHIFT                        8
  40         #define TX_BD_FLAGS_LHINT                               (3 << 13)
  41          #define TX_BD_FLAGS_LHINT_SHIFT                         13
  42          #define TX_BD_FLAGS_LHINT_512_AND_SMALLER               (0 << 13)
  43          #define TX_BD_FLAGS_LHINT_512_TO_1023                   (1 << 13)
  44          #define TX_BD_FLAGS_LHINT_1024_TO_2047                  (2 << 13)
  45          #define TX_BD_FLAGS_LHINT_2048_AND_LARGER               (3 << 13)
  46         #define TX_BD_FLAGS_COAL_NOW                            (1 << 15)
  47         #define TX_BD_LEN                                       (0xffff << 16)
  48          #define TX_BD_LEN_SHIFT                                 16
  49
  50         u32 tx_bd_opaque;
  51         __le64 tx_bd_haddr;
  52 } __packed;
  53
  54 struct tx_bd_ext {
  55         __le32 tx_bd_hsize_lflags;
  56         #define TX_BD_FLAGS_TCP_UDP_CHKSUM                      (1 << 0)
  57         #define TX_BD_FLAGS_IP_CKSUM                            (1 << 1)
  58         #define TX_BD_FLAGS_NO_CRC                              (1 << 2)
  59         #define TX_BD_FLAGS_STAMP                               (1 << 3)
  60         #define TX_BD_FLAGS_T_IP_CHKSUM                         (1 << 4)
  61         #define TX_BD_FLAGS_LSO                                 (1 << 5)
  62         #define TX_BD_FLAGS_IPID_FMT                            (1 << 6)
  63         #define TX_BD_FLAGS_T_IPID                              (1 << 7)
  64         #define TX_BD_HSIZE                                     (0xff << 16)
  65          #define TX_BD_HSIZE_SHIFT                               16
  66
  67         __le32 tx_bd_mss;
  68         __le32 tx_bd_cfa_action;
  69         #define TX_BD_CFA_ACTION                                (0xffff << 16)
  70          #define TX_BD_CFA_ACTION_SHIFT                          16
  71
  72         __le32 tx_bd_cfa_meta;
  73         #define TX_BD_CFA_META_MASK                             0xfffffff
  74         #define TX_BD_CFA_META_VID_MASK                         0xfff
  75         #define TX_BD_CFA_META_PRI_MASK                         (0xf << 12)
  76          #define TX_BD_CFA_META_PRI_SHIFT                        12
  77         #define TX_BD_CFA_META_TPID_MASK                        (3 << 16)
  78          #define TX_BD_CFA_META_TPID_SHIFT                       16
  79         #define TX_BD_CFA_META_KEY                              (0xf << 28)
  80          #define TX_BD_CFA_META_KEY_SHIFT                        28
  81         #define TX_BD_CFA_META_KEY_VLAN                         (1 << 28)
  82 };
  83
  84 struct rx_bd {
  85         __le32 rx_bd_len_flags_type;
  86         #define RX_BD_TYPE                                      (0x3f << 0)
  87          #define RX_BD_TYPE_RX_PACKET_BD                         0x4
  88          #define RX_BD_TYPE_RX_BUFFER_BD                         0x5
  89          #define RX_BD_TYPE_RX_AGG_BD                            0x6
  90          #define RX_BD_TYPE_16B_BD_SIZE                          (0 << 4)
  91          #define RX_BD_TYPE_32B_BD_SIZE                          (1 << 4)
  92          #define RX_BD_TYPE_48B_BD_SIZE                          (2 << 4)
  93          #define RX_BD_TYPE_64B_BD_SIZE                          (3 << 4)
  94         #define RX_BD_FLAGS_SOP                                 (1 << 6)
  95         #define RX_BD_FLAGS_EOP                                 (1 << 7)
  96         #define RX_BD_FLAGS_BUFFERS                             (3 << 8)
  97          #define RX_BD_FLAGS_1_BUFFER_PACKET                     (0 << 8)
  98          #define RX_BD_FLAGS_2_BUFFER_PACKET                     (1 << 8)
  99          #define RX_BD_FLAGS_3_BUFFER_PACKET                     (2 << 8)
 100          #define RX_BD_FLAGS_4_BUFFER_PACKET                     (3 << 8)
 101         #define RX_BD_LEN                                       (0xffff << 16)
 102          #define RX_BD_LEN_SHIFT                                 16
 103
 104         u32 rx_bd_opaque;
 105         __le64 rx_bd_haddr;
 106 };
 107
 108 struct tx_cmp {
 109         __le32 tx_cmp_flags_type;
 110         #define CMP_TYPE                                        (0x3f << 0)
 111          #define CMP_TYPE_TX_L2_CMP                              0
 112          #define CMP_TYPE_RX_L2_CMP                              17
 113          #define CMP_TYPE_RX_AGG_CMP                             18
 114          #define CMP_TYPE_RX_L2_TPA_START_CMP                    19
 115          #define CMP_TYPE_RX_L2_TPA_END_CMP                      21
 116          #define CMP_TYPE_STATUS_CMP                             32
 117          #define CMP_TYPE_REMOTE_DRIVER_REQ                      34
 118          #define CMP_TYPE_REMOTE_DRIVER_RESP                     36
 119          #define CMP_TYPE_ERROR_STATUS                           48
 120          #define CMPL_BASE_TYPE_STAT_EJECT                       0x1aUL
 121          #define CMPL_BASE_TYPE_HWRM_DONE                        0x20UL
 122          #define CMPL_BASE_TYPE_HWRM_FWD_REQ                     0x22UL
 123          #define CMPL_BASE_TYPE_HWRM_FWD_RESP                    0x24UL
 124          #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT                 0x2eUL
 125
 126         #define TX_CMP_FLAGS_ERROR                              (1 << 6)
 127         #define TX_CMP_FLAGS_PUSH                               (1 << 7)
 128
 129         u32 tx_cmp_opaque;
 130         __le32 tx_cmp_errors_v;
 131         #define TX_CMP_V                                        (1 << 0)
 132         #define TX_CMP_ERRORS_BUFFER_ERROR                      (7 << 1)
 133          #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR             0
 134          #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT           2
 135          #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG         4
 136          #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS          5
 137          #define TX_CMP_ERRORS_ZERO_LENGTH_PKT                   (1 << 4)
 138          #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN                  (1 << 5)
 139          #define TX_CMP_ERRORS_DMA_ERROR                         (1 << 6)
 140          #define TX_CMP_ERRORS_HINT_TOO_SHORT                    (1 << 7)
 141
 142         __le32 tx_cmp_unsed_3;
 143 };
 144
 145 struct rx_cmp {
 146         __le32 rx_cmp_len_flags_type;
 147         #define RX_CMP_CMP_TYPE                                 (0x3f << 0)
 148         #define RX_CMP_FLAGS_ERROR                              (1 << 6)
 149         #define RX_CMP_FLAGS_PLACEMENT                          (7 << 7)
 150         #define RX_CMP_FLAGS_RSS_VALID                          (1 << 10)
 151         #define RX_CMP_FLAGS_UNUSED                             (1 << 11)
 152          #define RX_CMP_FLAGS_ITYPES_SHIFT                       12
 153          #define RX_CMP_FLAGS_ITYPE_UNKNOWN                      (0 << 12)
 154          #define RX_CMP_FLAGS_ITYPE_IP                           (1 << 12)
 155          #define RX_CMP_FLAGS_ITYPE_TCP                          (2 << 12)
 156          #define RX_CMP_FLAGS_ITYPE_UDP                          (3 << 12)
 157          #define RX_CMP_FLAGS_ITYPE_FCOE                         (4 << 12)
 158          #define RX_CMP_FLAGS_ITYPE_ROCE                         (5 << 12)
 159          #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS                    (8 << 12)
 160          #define RX_CMP_FLAGS_ITYPE_PTP_W_TS                     (9 << 12)
 161         #define RX_CMP_LEN                                      (0xffff << 16)
 162          #define RX_CMP_LEN_SHIFT                                16
 163
 164         u32 rx_cmp_opaque;
 165         __le32 rx_cmp_misc_v1;
 166         #define RX_CMP_V1                                       (1 << 0)
 167         #define RX_CMP_AGG_BUFS                                 (0x1f << 1)
 168          #define RX_CMP_AGG_BUFS_SHIFT                           1
 169         #define RX_CMP_RSS_HASH_TYPE                            (0x7f << 9)
 170          #define RX_CMP_RSS_HASH_TYPE_SHIFT                      9
 171         #define RX_CMP_PAYLOAD_OFFSET                           (0xff << 16)
 172          #define RX_CMP_PAYLOAD_OFFSET_SHIFT                     16
 173
 174         __le32 rx_cmp_rss_hash;
 175 };
 176
 177 #define RX_CMP_HASH_VALID(rxcmp)                                \
 178         ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
 179
 180 #define RSS_PROFILE_ID_MASK     0x1f
 181
 182 #define RX_CMP_HASH_TYPE(rxcmp)                                 \
 183         (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
 184           RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
 185
 186 struct rx_cmp_ext {
 187         __le32 rx_cmp_flags2;
 188         #define RX_CMP_FLAGS2_IP_CS_CALC                        0x1
 189         #define RX_CMP_FLAGS2_L4_CS_CALC                        (0x1 << 1)
 190         #define RX_CMP_FLAGS2_T_IP_CS_CALC                      (0x1 << 2)
 191         #define RX_CMP_FLAGS2_T_L4_CS_CALC                      (0x1 << 3)
 192         #define RX_CMP_FLAGS2_META_FORMAT_VLAN                  (0x1 << 4)
 193         __le32 rx_cmp_meta_data;
 194         #define RX_CMP_FLAGS2_METADATA_TCI_MASK                 0xffff
 195         #define RX_CMP_FLAGS2_METADATA_VID_MASK                 0xfff
 196         #define RX_CMP_FLAGS2_METADATA_TPID_MASK                0xffff0000
 197          #define RX_CMP_FLAGS2_METADATA_TPID_SFT                 16
 198         __le32 rx_cmp_cfa_code_errors_v2;
 199         #define RX_CMP_V                                        (1 << 0)
 200         #define RX_CMPL_ERRORS_MASK                             (0x7fff << 1)
 201          #define RX_CMPL_ERRORS_SFT                              1
 202         #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK                (0x7 << 1)
 203          #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER           (0x0 << 1)
 204          #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT         (0x1 << 1)
 205          #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP         (0x2 << 1)
 206          #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT          (0x3 << 1)
 207         #define RX_CMPL_ERRORS_IP_CS_ERROR                      (0x1 << 4)
 208         #define RX_CMPL_ERRORS_L4_CS_ERROR                      (0x1 << 5)
 209         #define RX_CMPL_ERRORS_T_IP_CS_ERROR                    (0x1 << 6)
 210         #define RX_CMPL_ERRORS_T_L4_CS_ERROR                    (0x1 << 7)
 211         #define RX_CMPL_ERRORS_CRC_ERROR                        (0x1 << 8)
 212         #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK                 (0x7 << 9)
 213          #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR             (0x0 << 9)
 214          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION     (0x1 << 9)
 215          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN     (0x2 << 9)
 216          #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR   (0x3 << 9)
 217          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR     (0x4 << 9)
 218          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR    (0x5 << 9)
 219          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL         (0x6 << 9)
 220         #define RX_CMPL_ERRORS_PKT_ERROR_MASK                   (0xf << 12)
 221          #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR               (0x0 << 12)
 222          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION         (0x1 << 12)
 223          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN         (0x2 << 12)
 224          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL             (0x3 << 12)
 225          #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR         (0x4 << 12)
 226          #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR        (0x5 << 12)
 227          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN         (0x6 << 12)
 228          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
 229          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN         (0x8 << 12)
 230
 231         #define RX_CMPL_CFA_CODE_MASK                           (0xffff << 16)
 232          #define RX_CMPL_CFA_CODE_SFT                            16
 233
 234         __le32 rx_cmp_unused3;
 235 };
 236
 237 #define RX_CMP_L2_ERRORS                                                \
 238         cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
 239
 240 #define RX_CMP_L4_CS_BITS                                               \
 241         (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
 242
 243 #define RX_CMP_L4_CS_ERR_BITS                                           \
 244         (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
 245
 246 #define RX_CMP_L4_CS_OK(rxcmp1)                                         \
 247             (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) &&           \
 248              !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
 249
 250 #define RX_CMP_ENCAP(rxcmp1)                                            \
 251             ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &                    \
 252              RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
 253
 254 #define RX_CMP_CFA_CODE(rxcmpl1)                                        \
 255         ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) &           \
 256           RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
 257
 258 struct rx_agg_cmp {
 259         __le32 rx_agg_cmp_len_flags_type;
 260         #define RX_AGG_CMP_TYPE                                 (0x3f << 0)
 261         #define RX_AGG_CMP_LEN                                  (0xffff << 16)
 262          #define RX_AGG_CMP_LEN_SHIFT                            16
 263         u32 rx_agg_cmp_opaque;
 264         __le32 rx_agg_cmp_v;
 265         #define RX_AGG_CMP_V                                    (1 << 0)
 266         __le32 rx_agg_cmp_unused;
 267 };
 268
 269 struct rx_tpa_start_cmp {
 270         __le32 rx_tpa_start_cmp_len_flags_type;
 271         #define RX_TPA_START_CMP_TYPE                           (0x3f << 0)
 272         #define RX_TPA_START_CMP_FLAGS                          (0x3ff << 6)
 273          #define RX_TPA_START_CMP_FLAGS_SHIFT                    6
 274         #define RX_TPA_START_CMP_FLAGS_PLACEMENT                (0x7 << 7)
 275          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT          7
 276          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO          (0x1 << 7)
 277          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS            (0x2 << 7)
 278          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO      (0x5 << 7)
 279          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS        (0x6 << 7)
 280         #define RX_TPA_START_CMP_FLAGS_RSS_VALID                (0x1 << 10)
 281         #define RX_TPA_START_CMP_FLAGS_ITYPES                   (0xf << 12)
 282          #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT             12
 283          #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP                (0x2 << 12)
 284         #define RX_TPA_START_CMP_LEN                            (0xffff << 16)
 285          #define RX_TPA_START_CMP_LEN_SHIFT                      16
 286
 287         u32 rx_tpa_start_cmp_opaque;
 288         __le32 rx_tpa_start_cmp_misc_v1;
 289         #define RX_TPA_START_CMP_V1                             (0x1 << 0)
 290         #define RX_TPA_START_CMP_RSS_HASH_TYPE                  (0x7f << 9)
 291          #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT            9
 292         #define RX_TPA_START_CMP_AGG_ID                         (0x7f << 25)
 293          #define RX_TPA_START_CMP_AGG_ID_SHIFT                   25
 294
 295         __le32 rx_tpa_start_cmp_rss_hash;
 296 };
 297
 298 #define TPA_START_HASH_VALID(rx_tpa_start)                              \
 299         ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &              \
 300          cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
 301
 302 #define TPA_START_HASH_TYPE(rx_tpa_start)                               \
 303         (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &      \
 304            RX_TPA_START_CMP_RSS_HASH_TYPE) >>                           \
 305           RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
 306
 307 #define TPA_START_AGG_ID(rx_tpa_start)                                  \
 308         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &       \
 309          RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
 310
 311 struct rx_tpa_start_cmp_ext {
 312         __le32 rx_tpa_start_cmp_flags2;
 313         #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC              (0x1 << 0)
 314         #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC              (0x1 << 1)
 315         #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC            (0x1 << 2)
 316         #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC            (0x1 << 3)
 317         #define RX_TPA_START_CMP_FLAGS2_IP_TYPE                 (0x1 << 8)
 318
 319         __le32 rx_tpa_start_cmp_metadata;
 320         __le32 rx_tpa_start_cmp_cfa_code_v2;
 321         #define RX_TPA_START_CMP_V2                             (0x1 << 0)
 322         #define RX_TPA_START_CMP_CFA_CODE                       (0xffff << 16)
 323          #define RX_TPA_START_CMPL_CFA_CODE_SHIFT                16
 324         __le32 rx_tpa_start_cmp_hdr_info;
 325 };
 326
 327 #define TPA_START_CFA_CODE(rx_tpa_start)                                \
 328         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) &   \
 329          RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
 330
 331 #define TPA_START_IS_IPV6(rx_tpa_start)                         \
 332         (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 &           \
 333             cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
 334
 335 struct rx_tpa_end_cmp {
 336         __le32 rx_tpa_end_cmp_len_flags_type;
 337         #define RX_TPA_END_CMP_TYPE                             (0x3f << 0)
 338         #define RX_TPA_END_CMP_FLAGS                            (0x3ff << 6)
 339          #define RX_TPA_END_CMP_FLAGS_SHIFT                      6
 340         #define RX_TPA_END_CMP_FLAGS_PLACEMENT                  (0x7 << 7)
 341          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT            7
 342          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO            (0x1 << 7)
 343          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS              (0x2 << 7)
 344          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO        (0x5 << 7)
 345          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS          (0x6 << 7)
 346         #define RX_TPA_END_CMP_FLAGS_RSS_VALID                  (0x1 << 10)
 347         #define RX_TPA_END_CMP_FLAGS_ITYPES                     (0xf << 12)
 348          #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT               12
 349          #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP                  (0x2 << 12)
 350         #define RX_TPA_END_CMP_LEN                              (0xffff << 16)
 351          #define RX_TPA_END_CMP_LEN_SHIFT                        16
 352
 353         u32 rx_tpa_end_cmp_opaque;
 354         __le32 rx_tpa_end_cmp_misc_v1;
 355         #define RX_TPA_END_CMP_V1                               (0x1 << 0)
 356         #define RX_TPA_END_CMP_AGG_BUFS                         (0x3f << 1)
 357          #define RX_TPA_END_CMP_AGG_BUFS_SHIFT                   1
 358         #define RX_TPA_END_CMP_TPA_SEGS                         (0xff << 8)
 359          #define RX_TPA_END_CMP_TPA_SEGS_SHIFT                   8
 360         #define RX_TPA_END_CMP_PAYLOAD_OFFSET                   (0xff << 16)
 361          #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT             16
 362         #define RX_TPA_END_CMP_AGG_ID                           (0x7f << 25)
 363          #define RX_TPA_END_CMP_AGG_ID_SHIFT                     25
 364
 365         __le32 rx_tpa_end_cmp_tsdelta;
 366         #define RX_TPA_END_GRO_TS                               (0x1 << 31)
 367 };
 368
 369 #define TPA_END_AGG_ID(rx_tpa_end)                                      \
 370         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 371          RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
 372
 373 #define TPA_END_TPA_SEGS(rx_tpa_end)                                    \
 374         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
 375          RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
 376
 377 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO                          \
 378         cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO &          \
 379                     RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
 380
 381 #define TPA_END_GRO(rx_tpa_end)                                         \
 382         ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &                  \
 383          RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
 384
 385 #define TPA_END_GRO_TS(rx_tpa_end)                                      \
 386         (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta &                      \
 387             cpu_to_le32(RX_TPA_END_GRO_TS)))
 388
 389 struct rx_tpa_end_cmp_ext {
 390         __le32 rx_tpa_end_cmp_dup_acks;
 391         #define RX_TPA_END_CMP_TPA_DUP_ACKS                     (0xf << 0)
 392
 393         __le32 rx_tpa_end_cmp_seg_len;
 394         #define RX_TPA_END_CMP_TPA_SEG_LEN                      (0xffff << 0)
 395
 396         __le32 rx_tpa_end_cmp_errors_v2;
 397         #define RX_TPA_END_CMP_V2                               (0x1 << 0)
 398         #define RX_TPA_END_CMP_ERRORS                           (0x3 << 1)
 399         #define RX_TPA_END_CMPL_ERRORS_SHIFT                     1
 400
 401         u32 rx_tpa_end_cmp_start_opaque;
 402 };
 403
 404 #define TPA_END_ERRORS(rx_tpa_end_ext)                                  \
 405         ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 &                   \
 406          cpu_to_le32(RX_TPA_END_CMP_ERRORS))
 407
 408 struct nqe_cn {
 409         __le16  type;
 410         #define NQ_CN_TYPE_MASK           0x3fUL
 411         #define NQ_CN_TYPE_SFT            0
 412         #define NQ_CN_TYPE_CQ_NOTIFICATION  0x30UL
 413         #define NQ_CN_TYPE_LAST            NQ_CN_TYPE_CQ_NOTIFICATION
 414         __le16  reserved16;
 415         __le32  cq_handle_low;
 416         __le32  v;
 417         #define NQ_CN_V     0x1UL
 418         __le32  cq_handle_high;
 419 };
 420
 421 #define DB_IDX_MASK                                             0xffffff
 422 #define DB_IDX_VALID                                            (0x1 << 26)
 423 #define DB_IRQ_DIS                                              (0x1 << 27)
 424 #define DB_KEY_TX                                               (0x0 << 28)
 425 #define DB_KEY_RX                                               (0x1 << 28)
 426 #define DB_KEY_CP                                               (0x2 << 28)
 427 #define DB_KEY_ST                                               (0x3 << 28)
 428 #define DB_KEY_TX_PUSH                                          (0x4 << 28)
 429 #define DB_LONG_TX_PUSH                                         (0x2 << 24)
 430
 431 #define BNXT_MIN_ROCE_CP_RINGS  2
 432 #define BNXT_MIN_ROCE_STAT_CTXS 1
 433
 434 /* 64-bit doorbell */
 435 #define DBR_INDEX_MASK                                  0x0000000000ffffffULL
 436 #define DBR_XID_MASK                                    0x000fffff00000000ULL
 437 #define DBR_XID_SFT                                     32
 438 #define DBR_PATH_L2                                     (0x1ULL << 56)
 439 #define DBR_TYPE_SQ                                     (0x0ULL << 60)
 440 #define DBR_TYPE_RQ                                     (0x1ULL << 60)
 441 #define DBR_TYPE_SRQ                                    (0x2ULL << 60)
 442 #define DBR_TYPE_SRQ_ARM                                (0x3ULL << 60)
 443 #define DBR_TYPE_CQ                                     (0x4ULL << 60)
 444 #define DBR_TYPE_CQ_ARMSE                               (0x5ULL << 60)
 445 #define DBR_TYPE_CQ_ARMALL                              (0x6ULL << 60)
 446 #define DBR_TYPE_CQ_ARMENA                              (0x7ULL << 60)
 447 #define DBR_TYPE_SRQ_ARMENA                             (0x8ULL << 60)
 448 #define DBR_TYPE_CQ_CUTOFF_ACK                          (0x9ULL << 60)
 449 #define DBR_TYPE_NQ                                     (0xaULL << 60)
 450 #define DBR_TYPE_NQ_ARM                                 (0xbULL << 60)
 451 #define DBR_TYPE_NULL                                   (0xfULL << 60)
 452
 453 #define INVALID_HW_RING_ID      ((u16)-1)
 454
 455 /* The hardware supports certain page sizes.  Use the supported page sizes
 456  * to allocate the rings.
 457  */
 458 #if (PAGE_SHIFT < 12)
 459 #define BNXT_PAGE_SHIFT 12
 460 #elif (PAGE_SHIFT <= 13)
 461 #define BNXT_PAGE_SHIFT PAGE_SHIFT
 462 #elif (PAGE_SHIFT < 16)
 463 #define BNXT_PAGE_SHIFT 13
 464 #else
 465 #define BNXT_PAGE_SHIFT 16
 466 #endif
 467
 468 #define BNXT_PAGE_SIZE  (1 << BNXT_PAGE_SHIFT)
 469
 470 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
 471 #if (PAGE_SHIFT > 15)
 472 #define BNXT_RX_PAGE_SHIFT 15
 473 #else
 474 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
 475 #endif
 476
 477 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
 478
 479 #define BNXT_MAX_MTU            9500
 480 #define BNXT_MAX_PAGE_MODE_MTU  \
 481         ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN -       \
 482          XDP_PACKET_HEADROOM)
 483
 484 #define BNXT_MIN_PKT_SIZE       52
 485
 486 #define BNXT_DEFAULT_RX_RING_SIZE       511
 487 #define BNXT_DEFAULT_TX_RING_SIZE       511
 488
 489 #define MAX_TPA         64
 490
 491 #if (BNXT_PAGE_SHIFT == 16)
 492 #define MAX_RX_PAGES    1
 493 #define MAX_RX_AGG_PAGES        4
 494 #define MAX_TX_PAGES    1
 495 #define MAX_CP_PAGES    8
 496 #else
 497 #define MAX_RX_PAGES    8
 498 #define MAX_RX_AGG_PAGES        32
 499 #define MAX_TX_PAGES    8
 500 #define MAX_CP_PAGES    64
 501 #endif
 502
 503 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
 504 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
 505 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
 506
 507 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
 508 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
 509
 510 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
 511
 512 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
 513 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
 514
 515 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
 516
 517 #define BNXT_MAX_RX_DESC_CNT            (RX_DESC_CNT * MAX_RX_PAGES - 1)
 518 #define BNXT_MAX_RX_JUM_DESC_CNT        (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
 519 #define BNXT_MAX_TX_DESC_CNT            (TX_DESC_CNT * MAX_TX_PAGES - 1)
 520
 521 #define RX_RING(x)      (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 522 #define RX_IDX(x)       ((x) & (RX_DESC_CNT - 1))
 523
 524 #define TX_RING(x)      (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 525 #define TX_IDX(x)       ((x) & (TX_DESC_CNT - 1))
 526
 527 #define CP_RING(x)      (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
 528 #define CP_IDX(x)       ((x) & (CP_DESC_CNT - 1))
 529
 530 #define TX_CMP_VALID(txcmp, raw_cons)                                   \
 531         (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==        \
 532          !((raw_cons) & bp->cp_bit))
 533
 534 #define RX_CMP_VALID(rxcmp1, raw_cons)                                  \
 535         (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
 536          !((raw_cons) & bp->cp_bit))
 537
 538 #define RX_AGG_CMP_VALID(agg, raw_cons)                         \
 539         (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
 540          !((raw_cons) & bp->cp_bit))
 541
 542 #define NQ_CMP_VALID(nqcmp, raw_cons)                           \
 543         (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
 544
 545 #define TX_CMP_TYPE(txcmp)                                      \
 546         (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
 547
 548 #define RX_CMP_TYPE(rxcmp)                                      \
 549         (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
 550
 551 #define NEXT_RX(idx)            (((idx) + 1) & bp->rx_ring_mask)
 552
 553 #define NEXT_RX_AGG(idx)        (((idx) + 1) & bp->rx_agg_ring_mask)
 554
 555 #define NEXT_TX(idx)            (((idx) + 1) & bp->tx_ring_mask)
 556
 557 #define ADV_RAW_CMP(idx, n)     ((idx) + (n))
 558 #define NEXT_RAW_CMP(idx)       ADV_RAW_CMP(idx, 1)
 559 #define RING_CMP(idx)           ((idx) & bp->cp_ring_mask)
 560 #define NEXT_CMP(idx)           RING_CMP(ADV_RAW_CMP(idx, 1))
 561
 562 #define BNXT_HWRM_MAX_REQ_LEN           (bp->hwrm_max_req_len)
 563 #define BNXT_HWRM_SHORT_REQ_LEN         sizeof(struct hwrm_short_input)
 564 #define DFLT_HWRM_CMD_TIMEOUT           500
 565 #define HWRM_CMD_TIMEOUT                (bp->hwrm_cmd_timeout)
 566 #define HWRM_RESET_TIMEOUT              ((HWRM_CMD_TIMEOUT) * 4)
 567 #define HWRM_RESP_ERR_CODE_MASK         0xffff
 568 #define HWRM_RESP_LEN_OFFSET            4
 569 #define HWRM_RESP_LEN_MASK              0xffff0000
 570 #define HWRM_RESP_LEN_SFT               16
 571 #define HWRM_RESP_VALID_MASK            0xff000000
 572 #define BNXT_HWRM_REQ_MAX_SIZE          128
 573 #define BNXT_HWRM_REQS_PER_PAGE         (BNXT_PAGE_SIZE /       \
 574                                          BNXT_HWRM_REQ_MAX_SIZE)
 575 #define HWRM_SHORT_MIN_TIMEOUT          3
 576 #define HWRM_SHORT_MAX_TIMEOUT          10
 577 #define HWRM_SHORT_TIMEOUT_COUNTER      5
 578
 579 #define HWRM_MIN_TIMEOUT                25
 580 #define HWRM_MAX_TIMEOUT                40
 581
 582 #define HWRM_TOTAL_TIMEOUT(n)   (((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ?  \
 583         ((n) * HWRM_SHORT_MIN_TIMEOUT) :                                \
 584         (HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT +          \
 585          ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT))
 586
 587 #define HWRM_VALID_BIT_DELAY_USEC       150
 588
 589 #define BNXT_HWRM_CHNL_CHIMP    0
 590 #define BNXT_HWRM_CHNL_KONG     1
 591
 592 #define BNXT_RX_EVENT           1
 593 #define BNXT_AGG_EVENT          2
 594 #define BNXT_TX_EVENT           4
 595 #define BNXT_REDIRECT_EVENT     8
 596
 597 struct bnxt_sw_tx_bd {
 598         union {
 599                 struct sk_buff          *skb;
 600                 struct xdp_frame        *xdpf;
 601         };
 602         DEFINE_DMA_UNMAP_ADDR(mapping);
 603         DEFINE_DMA_UNMAP_LEN(len);
 604         u8                      is_gso;
 605         u8                      is_push;
 606         u8                      action;
 607         union {
 608                 unsigned short          nr_frags;
 609                 u16                     rx_prod;
 610         };
 611 };
 612
 613 struct bnxt_sw_rx_bd {
 614         void                    *data;
 615         u8                      *data_ptr;
 616         dma_addr_t              mapping;
 617 };
 618
 619 struct bnxt_sw_rx_agg_bd {
 620         struct page             *page;
 621         unsigned int            offset;
 622         dma_addr_t              mapping;
 623 };
 624
 625 struct bnxt_ring_mem_info {
 626         int                     nr_pages;
 627         int                     page_size;
 628         u16                     flags;
 629 #define BNXT_RMEM_VALID_PTE_FLAG        1
 630 #define BNXT_RMEM_RING_PTE_FLAG         2
 631 #define BNXT_RMEM_USE_FULL_PAGE_FLAG    4
 632
 633         u16                     depth;
 634
 635         void                    **pg_arr;
 636         dma_addr_t              *dma_arr;
 637
 638         __le64                  *pg_tbl;
 639         dma_addr_t              pg_tbl_map;
 640
 641         int                     vmem_size;
 642         void                    **vmem;
 643 };
 644
 645 struct bnxt_ring_struct {
 646         struct bnxt_ring_mem_info       ring_mem;
 647
 648         u16                     fw_ring_id; /* Ring id filled by Chimp FW */
 649         union {
 650                 u16             grp_idx;
 651                 u16             map_idx; /* Used by cmpl rings */
 652         };
 653         u32                     handle;
 654         u8                      queue_id;
 655 };
 656
 657 struct tx_push_bd {
 658         __le32                  doorbell;
 659         __le32                  tx_bd_len_flags_type;
 660         u32                     tx_bd_opaque;
 661         struct tx_bd_ext        txbd2;
 662 };
 663
 664 struct tx_push_buffer {
 665         struct tx_push_bd       push_bd;
 666         u32                     data[25];
 667 };
 668
 669 struct bnxt_db_info {
 670         void __iomem            *doorbell;
 671         union {
 672                 u64             db_key64;
 673                 u32             db_key32;
 674         };
 675 };
 676
 677 struct bnxt_tx_ring_info {
 678         struct bnxt_napi        *bnapi;
 679         u16                     tx_prod;
 680         u16                     tx_cons;
 681         u16                     txq_index;
 682         struct bnxt_db_info     tx_db;
 683
 684         struct tx_bd            *tx_desc_ring[MAX_TX_PAGES];
 685         struct bnxt_sw_tx_bd    *tx_buf_ring;
 686
 687         dma_addr_t              tx_desc_mapping[MAX_TX_PAGES];
 688
 689         struct tx_push_buffer   *tx_push;
 690         dma_addr_t              tx_push_mapping;
 691         __le64                  data_mapping;
 692
 693 #define BNXT_DEV_STATE_CLOSING  0x1
 694         u32                     dev_state;
 695
 696         struct bnxt_ring_struct tx_ring_struct;
 697 };
 698
 699 #define BNXT_LEGACY_COAL_CMPL_PARAMS                                    \
 700         (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN |           \
 701          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX |           \
 702          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET |               \
 703          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE |                 \
 704          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR |         \
 705          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
 706          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR |         \
 707          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
 708          RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
 709
 710 #define BNXT_COAL_CMPL_ENABLES                                          \
 711         (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
 712          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
 713          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
 714          RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
 715
 716 #define BNXT_COAL_CMPL_MIN_TMR_ENABLE                                   \
 717         RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
 718
 719 #define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE                       \
 720         RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
 721
 722 struct bnxt_coal_cap {
 723         u32                     cmpl_params;
 724         u32                     nq_params;
 725         u16                     num_cmpl_dma_aggr_max;
 726         u16                     num_cmpl_dma_aggr_during_int_max;
 727         u16                     cmpl_aggr_dma_tmr_max;
 728         u16                     cmpl_aggr_dma_tmr_during_int_max;
 729         u16                     int_lat_tmr_min_max;
 730         u16                     int_lat_tmr_max_max;
 731         u16                     num_cmpl_aggr_int_max;
 732         u16                     timer_units;
 733 };
 734
 735 struct bnxt_coal {
 736         u16                     coal_ticks;
 737         u16                     coal_ticks_irq;
 738         u16                     coal_bufs;
 739         u16                     coal_bufs_irq;
 740                         /* RING_IDLE enabled when coal ticks < idle_thresh  */
 741         u16                     idle_thresh;
 742         u8                      bufs_per_record;
 743         u8                      budget;
 744 };
 745
 746 struct bnxt_tpa_info {
 747         void                    *data;
 748         u8                      *data_ptr;
 749         dma_addr_t              mapping;
 750         u16                     len;
 751         unsigned short          gso_type;
 752         u32                     flags2;
 753         u32                     metadata;
 754         enum pkt_hash_types     hash_type;
 755         u32                     rss_hash;
 756         u32                     hdr_info;
 757
 758 #define BNXT_TPA_L4_SIZE(hdr_info)      \
 759         (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
 760
 761 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
 762         (((hdr_info) >> 18) & 0x1ff)
 763
 764 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
 765         (((hdr_info) >> 9) & 0x1ff)
 766
 767 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
 768         ((hdr_info) & 0x1ff)
 769
 770         u16                     cfa_code; /* cfa_code in TPA start compl */
 771 };
 772
 773 struct bnxt_rx_ring_info {
 774         struct bnxt_napi        *bnapi;
 775         u16                     rx_prod;
 776         u16                     rx_agg_prod;
 777         u16                     rx_sw_agg_prod;
 778         u16                     rx_next_cons;
 779         struct bnxt_db_info     rx_db;
 780         struct bnxt_db_info     rx_agg_db;
 781
 782         struct bpf_prog         *xdp_prog;
 783
 784         struct rx_bd            *rx_desc_ring[MAX_RX_PAGES];
 785         struct bnxt_sw_rx_bd    *rx_buf_ring;
 786
 787         struct rx_bd            *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
 788         struct bnxt_sw_rx_agg_bd        *rx_agg_ring;
 789
 790         unsigned long           *rx_agg_bmap;
 791         u16                     rx_agg_bmap_size;
 792
 793         struct page             *rx_page;
 794         unsigned int            rx_page_offset;
 795
 796         dma_addr_t              rx_desc_mapping[MAX_RX_PAGES];
 797         dma_addr_t              rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
 798
 799         struct bnxt_tpa_info    *rx_tpa;
 800
 801         struct bnxt_ring_struct rx_ring_struct;
 802         struct bnxt_ring_struct rx_agg_ring_struct;
 803         struct xdp_rxq_info     xdp_rxq;
 804         struct page_pool        *page_pool;
 805 };
 806
 807 struct bnxt_cp_ring_info {
 808         struct bnxt_napi        *bnapi;
 809         u32                     cp_raw_cons;
 810         struct bnxt_db_info     cp_db;
 811
 812         u8                      had_work_done:1;
 813         u8                      has_more_work:1;
 814
 815         u32                     last_cp_raw_cons;
 816
 817         struct bnxt_coal        rx_ring_coal;
 818         u64                     rx_packets;
 819         u64                     rx_bytes;
 820         u64                     event_ctr;
 821
 822         struct dim              dim;
 823
 824         union {
 825                 struct tx_cmp   *cp_desc_ring[MAX_CP_PAGES];
 826                 struct nqe_cn   *nq_desc_ring[MAX_CP_PAGES];
 827         };
 828
 829         dma_addr_t              cp_desc_mapping[MAX_CP_PAGES];
 830
 831         struct ctx_hw_stats     *hw_stats;
 832         dma_addr_t              hw_stats_map;
 833         u32                     hw_stats_ctx_id;
 834         u64                     rx_l4_csum_errors;
 835         u64                     missed_irqs;
 836
 837         struct bnxt_ring_struct cp_ring_struct;
 838
 839         struct bnxt_cp_ring_info *cp_ring_arr[2];
 840 #define BNXT_RX_HDL     0
 841 #define BNXT_TX_HDL     1
 842 };
 843
 844 struct bnxt_napi {
 845         struct napi_struct      napi;
 846         struct bnxt             *bp;
 847
 848         int                     index;
 849         struct bnxt_cp_ring_info        cp_ring;
 850         struct bnxt_rx_ring_info        *rx_ring;
 851         struct bnxt_tx_ring_info        *tx_ring;
 852
 853         void                    (*tx_int)(struct bnxt *, struct bnxt_napi *,
 854                                           int);
 855         int                     tx_pkts;
 856         u8                      events;
 857
 858         u32                     flags;
 859 #define BNXT_NAPI_FLAG_XDP      0x1
 860
 861         bool                    in_reset;
 862 };
 863
 864 struct bnxt_irq {
 865         irq_handler_t   handler;
 866         unsigned int    vector;
 867         u8              requested:1;
 868         u8              have_cpumask:1;
 869         char            name[IFNAMSIZ + 2];
 870         cpumask_var_t   cpu_mask;
 871 };
 872
 873 #define HWRM_RING_ALLOC_TX      0x1
 874 #define HWRM_RING_ALLOC_RX      0x2
 875 #define HWRM_RING_ALLOC_AGG     0x4
 876 #define HWRM_RING_ALLOC_CMPL    0x8
 877 #define HWRM_RING_ALLOC_NQ      0x10
 878
 879 #define INVALID_STATS_CTX_ID    -1
 880
 881 struct bnxt_ring_grp_info {
 882         u16     fw_stats_ctx;
 883         u16     fw_grp_id;
 884         u16     rx_fw_ring_id;
 885         u16     agg_fw_ring_id;
 886         u16     cp_fw_ring_id;
 887 };
 888
 889 struct bnxt_vnic_info {
 890         u16             fw_vnic_id; /* returned by Chimp during alloc */
 891 #define BNXT_MAX_CTX_PER_VNIC   8
 892         u16             fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
 893         u16             fw_l2_ctx_id;
 894 #define BNXT_MAX_UC_ADDRS       4
 895         __le64          fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
 896                                 /* index 0 always dev_addr */
 897         u16             uc_filter_count;
 898         u8              *uc_list;
 899
 900         u16             *fw_grp_ids;
 901         dma_addr_t      rss_table_dma_addr;
 902         __le16          *rss_table;
 903         dma_addr_t      rss_hash_key_dma_addr;
 904         u64             *rss_hash_key;
 905         u32             rx_mask;
 906
 907         u8              *mc_list;
 908         int             mc_list_size;
 909         int             mc_list_count;
 910         dma_addr_t      mc_list_mapping;
 911 #define BNXT_MAX_MC_ADDRS       16
 912
 913         u32             flags;
 914 #define BNXT_VNIC_RSS_FLAG      1
 915 #define BNXT_VNIC_RFS_FLAG      2
 916 #define BNXT_VNIC_MCAST_FLAG    4
 917 #define BNXT_VNIC_UCAST_FLAG    8
 918 #define BNXT_VNIC_RFS_NEW_RSS_FLAG      0x10
 919 };
 920
 921 struct bnxt_hw_resc {
 922         u16     min_rsscos_ctxs;
 923         u16     max_rsscos_ctxs;
 924         u16     min_cp_rings;
 925         u16     max_cp_rings;
 926         u16     resv_cp_rings;
 927         u16     min_tx_rings;
 928         u16     max_tx_rings;
 929         u16     resv_tx_rings;
 930         u16     max_tx_sch_inputs;
 931         u16     min_rx_rings;
 932         u16     max_rx_rings;
 933         u16     resv_rx_rings;
 934         u16     min_hw_ring_grps;
 935         u16     max_hw_ring_grps;
 936         u16     resv_hw_ring_grps;
 937         u16     min_l2_ctxs;
 938         u16     max_l2_ctxs;
 939         u16     min_vnics;
 940         u16     max_vnics;
 941         u16     resv_vnics;
 942         u16     min_stat_ctxs;
 943         u16     max_stat_ctxs;
 944         u16     resv_stat_ctxs;
 945         u16     max_nqs;
 946         u16     max_irqs;
 947         u16     resv_irqs;
 948 };
 949
 950 #if defined(CONFIG_BNXT_SRIOV)
 951 struct bnxt_vf_info {
 952         u16     fw_fid;
 953         u8      mac_addr[ETH_ALEN];     /* PF assigned MAC Address */
 954         u8      vf_mac_addr[ETH_ALEN];  /* VF assigned MAC address, only
 955                                          * stored by PF.
 956                                          */
 957         u16     vlan;
 958         u16     func_qcfg_flags;
 959         u32     flags;
 960 #define BNXT_VF_QOS             0x1
 961 #define BNXT_VF_SPOOFCHK        0x2
 962 #define BNXT_VF_LINK_FORCED     0x4
 963 #define BNXT_VF_LINK_UP         0x8
 964 #define BNXT_VF_TRUST           0x10
 965         u32     func_flags; /* func cfg flags */
 966         u32     min_tx_rate;
 967         u32     max_tx_rate;
 968         void    *hwrm_cmd_req_addr;
 969         dma_addr_t      hwrm_cmd_req_dma_addr;
 970 };
 971 #endif
 972
 973 struct bnxt_pf_info {
 974 #define BNXT_FIRST_PF_FID       1
 975 #define BNXT_FIRST_VF_FID       128
 976         u16     fw_fid;
 977         u16     port_id;
 978         u8      mac_addr[ETH_ALEN];
 979         u32     first_vf_id;
 980         u16     active_vfs;
 981         u16     max_vfs;
 982         u32     max_encap_records;
 983         u32     max_decap_records;
 984         u32     max_tx_em_flows;
 985         u32     max_tx_wm_flows;
 986         u32     max_rx_em_flows;
 987         u32     max_rx_wm_flows;
 988         unsigned long   *vf_event_bmap;
 989         u16     hwrm_cmd_req_pages;
 990         u8      vf_resv_strategy;
 991 #define BNXT_VF_RESV_STRATEGY_MAXIMAL   0
 992 #define BNXT_VF_RESV_STRATEGY_MINIMAL   1
 993 #define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC    2
 994         void                    *hwrm_cmd_req_addr[4];
 995         dma_addr_t              hwrm_cmd_req_dma_addr[4];
 996         struct bnxt_vf_info     *vf;
 997 };
 998
 999 struct bnxt_ntuple_filter {
1000         struct hlist_node       hash;
1001         u8                      dst_mac_addr[ETH_ALEN];
1002         u8                      src_mac_addr[ETH_ALEN];
1003         struct flow_keys        fkeys;
1004         __le64                  filter_id;
1005         u16                     sw_id;
1006         u8                      l2_fltr_idx;
1007         u16                     rxq;
1008         u32                     flow_id;
1009         unsigned long           state;
1010 #define BNXT_FLTR_VALID         0
1011 #define BNXT_FLTR_UPDATE        1
1012 };
1013
1014 struct bnxt_link_info {
1015         u8                      phy_type;
1016         u8                      media_type;
1017         u8                      transceiver;
1018         u8                      phy_addr;
1019         u8                      phy_link_status;
1020 #define BNXT_LINK_NO_LINK       PORT_PHY_QCFG_RESP_LINK_NO_LINK
1021 #define BNXT_LINK_SIGNAL        PORT_PHY_QCFG_RESP_LINK_SIGNAL
1022 #define BNXT_LINK_LINK          PORT_PHY_QCFG_RESP_LINK_LINK
1023         u8                      wire_speed;
1024         u8                      loop_back;
1025         u8                      link_up;
1026         u8                      duplex;
1027 #define BNXT_LINK_DUPLEX_HALF   PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1028 #define BNXT_LINK_DUPLEX_FULL   PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1029         u8                      pause;
1030 #define BNXT_LINK_PAUSE_TX      PORT_PHY_QCFG_RESP_PAUSE_TX
1031 #define BNXT_LINK_PAUSE_RX      PORT_PHY_QCFG_RESP_PAUSE_RX
1032 #define BNXT_LINK_PAUSE_BOTH    (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1033                                  PORT_PHY_QCFG_RESP_PAUSE_TX)
1034         u8                      lp_pause;
1035         u8                      auto_pause_setting;
1036         u8                      force_pause_setting;
1037         u8                      duplex_setting;
1038         u8                      auto_mode;
1039 #define BNXT_AUTO_MODE(mode)    ((mode) > BNXT_LINK_AUTO_NONE && \
1040                                  (mode) <= BNXT_LINK_AUTO_MSK)
1041 #define BNXT_LINK_AUTO_NONE     PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1042 #define BNXT_LINK_AUTO_ALLSPDS  PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1043 #define BNXT_LINK_AUTO_ONESPD   PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1044 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1045 #define BNXT_LINK_AUTO_MSK      PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1046 #define PHY_VER_LEN             3
1047         u8                      phy_ver[PHY_VER_LEN];
1048         u16                     link_speed;
1049 #define BNXT_LINK_SPEED_100MB   PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1050 #define BNXT_LINK_SPEED_1GB     PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1051 #define BNXT_LINK_SPEED_2GB     PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1052 #define BNXT_LINK_SPEED_2_5GB   PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1053 #define BNXT_LINK_SPEED_10GB    PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1054 #define BNXT_LINK_SPEED_20GB    PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1055 #define BNXT_LINK_SPEED_25GB    PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1056 #define BNXT_LINK_SPEED_40GB    PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1057 #define BNXT_LINK_SPEED_50GB    PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1058 #define BNXT_LINK_SPEED_100GB   PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1059         u16                     support_speeds;
1060         u16                     auto_link_speeds;       /* fw adv setting */
1061 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1062 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1063 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1064 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1065 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1066 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1067 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1068 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1069 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1070 #define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1071         u16                     support_auto_speeds;
1072         u16                     lp_auto_link_speeds;
1073         u16                     force_link_speed;
1074         u32                     preemphasis;
1075         u8                      module_status;
1076         u16                     fec_cfg;
1077 #define BNXT_FEC_AUTONEG        PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1078 #define BNXT_FEC_ENC_BASE_R     PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1079 #define BNXT_FEC_ENC_RS         PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED
1080
1081         /* copy of requested setting from ethtool cmd */
1082         u8                      autoneg;
1083 #define BNXT_AUTONEG_SPEED              1
1084 #define BNXT_AUTONEG_FLOW_CTRL          2
1085         u8                      req_duplex;
1086         u8                      req_flow_ctrl;
1087         u16                     req_link_speed;
1088         u16                     advertising;    /* user adv setting */
1089         bool                    force_link_chng;
1090
1091         bool                    phy_retry;
1092         unsigned long           phy_retry_expires;
1093
1094         /* a copy of phy_qcfg output used to report link
1095          * info to VF
1096          */
1097         struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1098 };
1099
1100 #define BNXT_MAX_QUEUE  8
1101
1102 struct bnxt_queue_info {
1103         u8      queue_id;
1104         u8      queue_profile;
1105 };
1106
1107 #define BNXT_MAX_LED                    4
1108
1109 struct bnxt_led_info {
1110         u8      led_id;
1111         u8      led_type;
1112         u8      led_group_id;
1113         u8      unused;
1114         __le16  led_state_caps;
1115 #define BNXT_LED_ALT_BLINK_CAP(x)       ((x) &  \
1116         cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1117
1118         __le16  led_color_caps;
1119 };
1120
1121 #define BNXT_MAX_TEST   8
1122
1123 struct bnxt_test_info {
1124         u8 offline_mask;
1125         u8 flags;
1126 #define BNXT_TEST_FL_EXT_LPBK   0x1
1127         u16 timeout;
1128         char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1129 };
1130
1131 #define BNXT_GRCPF_REG_CHIMP_COMM               0x0
1132 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER       0x100
1133 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT          0x400
1134 #define BNXT_CAG_REG_LEGACY_INT_STATUS          0x4014
1135 #define BNXT_CAG_REG_BASE                       0x300000
1136
1137 #define BNXT_GRCPF_REG_KONG_COMM                0xA00
1138 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER        0xB00
1139
1140 struct bnxt_tc_flow_stats {
1141         u64             packets;
1142         u64             bytes;
1143 };
1144
1145 struct bnxt_tc_info {
1146         bool                            enabled;
1147
1148         /* hash table to store TC offloaded flows */
1149         struct rhashtable               flow_table;
1150         struct rhashtable_params        flow_ht_params;
1151
1152         /* hash table to store L2 keys of TC flows */
1153         struct rhashtable               l2_table;
1154         struct rhashtable_params        l2_ht_params;
1155         /* hash table to store L2 keys for TC tunnel decap */
1156         struct rhashtable               decap_l2_table;
1157         struct rhashtable_params        decap_l2_ht_params;
1158         /* hash table to store tunnel decap entries */
1159         struct rhashtable               decap_table;
1160         struct rhashtable_params        decap_ht_params;
1161         /* hash table to store tunnel encap entries */
1162         struct rhashtable               encap_table;
1163         struct rhashtable_params        encap_ht_params;
1164
1165         /* lock to atomically add/del an l2 node when a flow is
1166          * added or deleted.
1167          */
1168         struct mutex                    lock;
1169
1170         /* Fields used for batching stats query */
1171         struct rhashtable_iter          iter;
1172 #define BNXT_FLOW_STATS_BATCH_MAX       10
1173         struct bnxt_tc_stats_batch {
1174                 void                      *flow_node;
1175                 struct bnxt_tc_flow_stats hw_stats;
1176         } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1177
1178         /* Stat counter mask (width) */
1179         u64                             bytes_mask;
1180         u64                             packets_mask;
1181 };
1182
1183 struct bnxt_vf_rep_stats {
1184         u64                     packets;
1185         u64                     bytes;
1186         u64                     dropped;
1187 };
1188
1189 struct bnxt_vf_rep {
1190         struct bnxt                     *bp;
1191         struct net_device               *dev;
1192         struct metadata_dst             *dst;
1193         u16                             vf_idx;
1194         u16                             tx_cfa_action;
1195         u16                             rx_cfa_code;
1196
1197         struct bnxt_vf_rep_stats        rx_stats;
1198         struct bnxt_vf_rep_stats        tx_stats;
1199 };
1200
1201 #define PTU_PTE_VALID             0x1UL
1202 #define PTU_PTE_LAST              0x2UL
1203 #define PTU_PTE_NEXT_TO_LAST      0x4UL
1204
1205 #define MAX_CTX_PAGES   (BNXT_PAGE_SIZE / 8)
1206 #define MAX_CTX_TOTAL_PAGES     (MAX_CTX_PAGES * MAX_CTX_PAGES)
1207
1208 struct bnxt_ctx_pg_info {
1209         u32             entries;
1210         u32             nr_pages;
1211         void            *ctx_pg_arr[MAX_CTX_PAGES];
1212         dma_addr_t      ctx_dma_arr[MAX_CTX_PAGES];
1213         struct bnxt_ring_mem_info ring_mem;
1214         struct bnxt_ctx_pg_info **ctx_pg_tbl;
1215 };
1216
1217 struct bnxt_ctx_mem_info {
1218         u32     qp_max_entries;
1219         u16     qp_min_qp1_entries;
1220         u16     qp_max_l2_entries;
1221         u16     qp_entry_size;
1222         u16     srq_max_l2_entries;
1223         u32     srq_max_entries;
1224         u16     srq_entry_size;
1225         u16     cq_max_l2_entries;
1226         u32     cq_max_entries;
1227         u16     cq_entry_size;
1228         u16     vnic_max_vnic_entries;
1229         u16     vnic_max_ring_table_entries;
1230         u16     vnic_entry_size;
1231         u32     stat_max_entries;
1232         u16     stat_entry_size;
1233         u16     tqm_entry_size;
1234         u32     tqm_min_entries_per_ring;
1235         u32     tqm_max_entries_per_ring;
1236         u32     mrav_max_entries;
1237         u16     mrav_entry_size;
1238         u16     tim_entry_size;
1239         u32     tim_max_entries;
1240         u16     mrav_num_entries_units;
1241         u8      tqm_entries_multiple;
1242
1243         u32     flags;
1244         #define BNXT_CTX_FLAG_INITED    0x01
1245
1246         struct bnxt_ctx_pg_info qp_mem;
1247         struct bnxt_ctx_pg_info srq_mem;
1248         struct bnxt_ctx_pg_info cq_mem;
1249         struct bnxt_ctx_pg_info vnic_mem;
1250         struct bnxt_ctx_pg_info stat_mem;
1251         struct bnxt_ctx_pg_info mrav_mem;
1252         struct bnxt_ctx_pg_info tim_mem;
1253         struct bnxt_ctx_pg_info *tqm_mem[9];
1254 };
1255
1256 struct bnxt {
1257         void __iomem            *bar0;
1258         void __iomem            *bar1;
1259         void __iomem            *bar2;
1260
1261         u32                     reg_base;
1262         u16                     chip_num;
1263 #define CHIP_NUM_57301          0x16c8
1264 #define CHIP_NUM_57302          0x16c9
1265 #define CHIP_NUM_57304          0x16ca
1266 #define CHIP_NUM_58700          0x16cd
1267 #define CHIP_NUM_57402          0x16d0
1268 #define CHIP_NUM_57404          0x16d1
1269 #define CHIP_NUM_57406          0x16d2
1270 #define CHIP_NUM_57407          0x16d5
1271
1272 #define CHIP_NUM_57311          0x16ce
1273 #define CHIP_NUM_57312          0x16cf
1274 #define CHIP_NUM_57314          0x16df
1275 #define CHIP_NUM_57317          0x16e0
1276 #define CHIP_NUM_57412          0x16d6
1277 #define CHIP_NUM_57414          0x16d7
1278 #define CHIP_NUM_57416          0x16d8
1279 #define CHIP_NUM_57417          0x16d9
1280 #define CHIP_NUM_57412L         0x16da
1281 #define CHIP_NUM_57414L         0x16db
1282
1283 #define CHIP_NUM_5745X          0xd730
1284
1285 #define CHIP_NUM_57500          0x1750
1286
1287 #define CHIP_NUM_58802          0xd802
1288 #define CHIP_NUM_58804          0xd804
1289 #define CHIP_NUM_58808          0xd808
1290
1291 #define BNXT_CHIP_NUM_5730X(chip_num)           \
1292         ((chip_num) >= CHIP_NUM_57301 &&        \
1293          (chip_num) <= CHIP_NUM_57304)
1294
1295 #define BNXT_CHIP_NUM_5740X(chip_num)           \
1296         (((chip_num) >= CHIP_NUM_57402 &&       \
1297           (chip_num) <= CHIP_NUM_57406) ||      \
1298          (chip_num) == CHIP_NUM_57407)
1299
1300 #define BNXT_CHIP_NUM_5731X(chip_num)           \
1301         ((chip_num) == CHIP_NUM_57311 ||        \
1302          (chip_num) == CHIP_NUM_57312 ||        \
1303          (chip_num) == CHIP_NUM_57314 ||        \
1304          (chip_num) == CHIP_NUM_57317)
1305
1306 #define BNXT_CHIP_NUM_5741X(chip_num)           \
1307         ((chip_num) >= CHIP_NUM_57412 &&        \
1308          (chip_num) <= CHIP_NUM_57414L)
1309
1310 #define BNXT_CHIP_NUM_58700(chip_num)           \
1311          ((chip_num) == CHIP_NUM_58700)
1312
1313 #define BNXT_CHIP_NUM_5745X(chip_num)           \
1314          ((chip_num) == CHIP_NUM_5745X)
1315
1316 #define BNXT_CHIP_NUM_57X0X(chip_num)           \
1317         (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1318
1319 #define BNXT_CHIP_NUM_57X1X(chip_num)           \
1320         (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1321
1322 #define BNXT_CHIP_NUM_588XX(chip_num)           \
1323         ((chip_num) == CHIP_NUM_58802 ||        \
1324          (chip_num) == CHIP_NUM_58804 ||        \
1325          (chip_num) == CHIP_NUM_58808)
1326
1327         struct net_device       *dev;
1328         struct pci_dev          *pdev;
1329
1330         atomic_t                intr_sem;
1331
1332         u32                     flags;
1333         #define BNXT_FLAG_CHIP_P5       0x1
1334         #define BNXT_FLAG_VF            0x2
1335         #define BNXT_FLAG_LRO           0x4
1336 #ifdef CONFIG_INET
1337         #define BNXT_FLAG_GRO           0x8
1338 #else
1339         /* Cannot support hardware GRO if CONFIG_INET is not set */
1340         #define BNXT_FLAG_GRO           0x0
1341 #endif
1342         #define BNXT_FLAG_TPA           (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1343         #define BNXT_FLAG_JUMBO         0x10
1344         #define BNXT_FLAG_STRIP_VLAN    0x20
1345         #define BNXT_FLAG_AGG_RINGS     (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1346                                          BNXT_FLAG_LRO)
1347         #define BNXT_FLAG_USING_MSIX    0x40
1348         #define BNXT_FLAG_MSIX_CAP      0x80
1349         #define BNXT_FLAG_RFS           0x100
1350         #define BNXT_FLAG_SHARED_RINGS  0x200
1351         #define BNXT_FLAG_PORT_STATS    0x400
1352         #define BNXT_FLAG_UDP_RSS_CAP   0x800
1353         #define BNXT_FLAG_EEE_CAP       0x1000
1354         #define BNXT_FLAG_NEW_RSS_CAP   0x2000
1355         #define BNXT_FLAG_WOL_CAP       0x4000
1356         #define BNXT_FLAG_ROCEV1_CAP    0x8000
1357         #define BNXT_FLAG_ROCEV2_CAP    0x10000
1358         #define BNXT_FLAG_ROCE_CAP      (BNXT_FLAG_ROCEV1_CAP | \
1359                                          BNXT_FLAG_ROCEV2_CAP)
1360         #define BNXT_FLAG_NO_AGG_RINGS  0x20000
1361         #define BNXT_FLAG_RX_PAGE_MODE  0x40000
1362         #define BNXT_FLAG_MULTI_HOST    0x100000
1363         #define BNXT_FLAG_DOUBLE_DB     0x400000
1364         #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1365         #define BNXT_FLAG_DIM           0x2000000
1366         #define BNXT_FLAG_ROCE_MIRROR_CAP       0x4000000
1367         #define BNXT_FLAG_PORT_STATS_EXT        0x10000000
1368         #define BNXT_FLAG_PCIE_STATS    0x40000000
1369
1370         #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA |             \
1371                                             BNXT_FLAG_RFS |             \
1372                                             BNXT_FLAG_STRIP_VLAN)
1373
1374 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
1375 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
1376 #define BNXT_NPAR(bp)           ((bp)->port_partition_type)
1377 #define BNXT_MH(bp)             ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1378 #define BNXT_SINGLE_PF(bp)      (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1379 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1380 #define BNXT_RX_PAGE_MODE(bp)   ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1381 #define BNXT_SUPPORTS_TPA(bp)   (!BNXT_CHIP_TYPE_NITRO_A0(bp) &&        \
1382                                  !(bp->flags & BNXT_FLAG_CHIP_P5) &&    \
1383                                  !is_kdump_kernel())
1384
1385 /* Chip class phase 5 */
1386 #define BNXT_CHIP_P5(bp)                        \
1387         ((bp)->chip_num == CHIP_NUM_57500)
1388
1389 /* Chip class phase 4.x */
1390 #define BNXT_CHIP_P4(bp)                        \
1391         (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1392          BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1393          BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1394          (BNXT_CHIP_NUM_58700((bp)->chip_num) &&        \
1395           !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1396
1397 #define BNXT_CHIP_P4_PLUS(bp)                   \
1398         (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1399
1400         struct bnxt_en_dev      *edev;
1401         struct bnxt_en_dev *    (*ulp_probe)(struct net_device *);
1402
1403         struct bnxt_napi        **bnapi;
1404
1405         struct bnxt_rx_ring_info        *rx_ring;
1406         struct bnxt_tx_ring_info        *tx_ring;
1407         u16                     *tx_ring_map;
1408
1409         struct sk_buff *        (*gro_func)(struct bnxt_tpa_info *, int, int,
1410                                             struct sk_buff *);
1411
1412         struct sk_buff *        (*rx_skb_func)(struct bnxt *,
1413                                                struct bnxt_rx_ring_info *,
1414                                                u16, void *, u8 *, dma_addr_t,
1415                                                unsigned int);
1416
1417         u32                     rx_buf_size;
1418         u32                     rx_buf_use_size;        /* useable size */
1419         u16                     rx_offset;
1420         u16                     rx_dma_offset;
1421         enum dma_data_direction rx_dir;
1422         u32                     rx_ring_size;
1423         u32                     rx_agg_ring_size;
1424         u32                     rx_copy_thresh;
1425         u32                     rx_ring_mask;
1426         u32                     rx_agg_ring_mask;
1427         int                     rx_nr_pages;
1428         int                     rx_agg_nr_pages;
1429         int                     rx_nr_rings;
1430         int                     rsscos_nr_ctxs;
1431
1432         u32                     tx_ring_size;
1433         u32                     tx_ring_mask;
1434         int                     tx_nr_pages;
1435         int                     tx_nr_rings;
1436         int                     tx_nr_rings_per_tc;
1437         int                     tx_nr_rings_xdp;
1438
1439         int                     tx_wake_thresh;
1440         int                     tx_push_thresh;
1441         int                     tx_push_size;
1442
1443         u32                     cp_ring_size;
1444         u32                     cp_ring_mask;
1445         u32                     cp_bit;
1446         int                     cp_nr_pages;
1447         int                     cp_nr_rings;
1448
1449         /* grp_info indexed by completion ring index */
1450         struct bnxt_ring_grp_info       *grp_info;
1451         struct bnxt_vnic_info   *vnic_info;
1452         int                     nr_vnics;
1453         u32                     rss_hash_cfg;
1454
1455         u16                     max_mtu;
1456         u8                      max_tc;
1457         u8                      max_lltc;       /* lossless TCs */
1458         struct bnxt_queue_info  q_info[BNXT_MAX_QUEUE];
1459         u8                      tc_to_qidx[BNXT_MAX_QUEUE];
1460         u8                      q_ids[BNXT_MAX_QUEUE];
1461         u8                      max_q;
1462
1463         unsigned int            current_interval;
1464 #define BNXT_TIMER_INTERVAL     HZ
1465
1466         struct timer_list       timer;
1467
1468         unsigned long           state;
1469 #define BNXT_STATE_OPEN         0
1470 #define BNXT_STATE_IN_SP_TASK   1
1471 #define BNXT_STATE_READ_STATS   2
1472
1473         struct bnxt_irq *irq_tbl;
1474         int                     total_irqs;
1475         u8                      mac_addr[ETH_ALEN];
1476
1477 #ifdef CONFIG_BNXT_DCB
1478         struct ieee_pfc         *ieee_pfc;
1479         struct ieee_ets         *ieee_ets;
1480         u8                      dcbx_cap;
1481         u8                      default_pri;
1482         u8                      max_dscp_value;
1483 #endif /* CONFIG_BNXT_DCB */
1484
1485         u32                     msg_enable;
1486
1487         u32                     fw_cap;
1488         #define BNXT_FW_CAP_SHORT_CMD                   0x00000001
1489         #define BNXT_FW_CAP_LLDP_AGENT                  0x00000002
1490         #define BNXT_FW_CAP_DCBX_AGENT                  0x00000004
1491         #define BNXT_FW_CAP_NEW_RM                      0x00000008
1492         #define BNXT_FW_CAP_IF_CHANGE                   0x00000010
1493         #define BNXT_FW_CAP_KONG_MB_CHNL                0x00000080
1494         #define BNXT_FW_CAP_OVS_64BIT_HANDLE            0x00000400
1495         #define BNXT_FW_CAP_TRUSTED_VF                  0x00000800
1496         #define BNXT_FW_CAP_PKG_VER                     0x00004000
1497         #define BNXT_FW_CAP_CFA_ADV_FLOW                0x00008000
1498         #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX        0x00010000
1499         #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED        0x00020000
1500         #define BNXT_FW_CAP_EXT_STATS_SUPPORTED         0x00040000
1501
1502 #define BNXT_NEW_RM(bp)         ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1503         u32                     hwrm_spec_code;
1504         u16                     hwrm_cmd_seq;
1505         u16                     hwrm_cmd_kong_seq;
1506         u16                     hwrm_intr_seq_id;
1507         void                    *hwrm_short_cmd_req_addr;
1508         dma_addr_t              hwrm_short_cmd_req_dma_addr;
1509         void                    *hwrm_cmd_resp_addr;
1510         dma_addr_t              hwrm_cmd_resp_dma_addr;
1511         void                    *hwrm_cmd_kong_resp_addr;
1512         dma_addr_t              hwrm_cmd_kong_resp_dma_addr;
1513
1514         struct rtnl_link_stats64        net_stats_prev;
1515         struct rx_port_stats    *hw_rx_port_stats;
1516         struct tx_port_stats    *hw_tx_port_stats;
1517         struct rx_port_stats_ext        *hw_rx_port_stats_ext;
1518         struct tx_port_stats_ext        *hw_tx_port_stats_ext;
1519         struct pcie_ctx_hw_stats        *hw_pcie_stats;
1520         dma_addr_t              hw_rx_port_stats_map;
1521         dma_addr_t              hw_tx_port_stats_map;
1522         dma_addr_t              hw_rx_port_stats_ext_map;
1523         dma_addr_t              hw_tx_port_stats_ext_map;
1524         dma_addr_t              hw_pcie_stats_map;
1525         int                     hw_port_stats_size;
1526         u16                     fw_rx_stats_ext_size;
1527         u16                     fw_tx_stats_ext_size;
1528         u8                      pri2cos[8];
1529         u8                      pri2cos_valid;
1530
1531         u16                     hwrm_max_req_len;
1532         u16                     hwrm_max_ext_req_len;
1533         int                     hwrm_cmd_timeout;
1534         struct mutex            hwrm_cmd_lock;  /* serialize hwrm messages */
1535         struct hwrm_ver_get_output      ver_resp;
1536 #define FW_VER_STR_LEN          32
1537 #define BC_HWRM_STR_LEN         21
1538 #define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1539         char                    fw_ver_str[FW_VER_STR_LEN];
1540         __be16                  vxlan_port;
1541         u8                      vxlan_port_cnt;
1542         __le16                  vxlan_fw_dst_port_id;
1543         __be16                  nge_port;
1544         u8                      nge_port_cnt;
1545         __le16                  nge_fw_dst_port_id;
1546         u8                      port_partition_type;
1547         u8                      port_count;
1548         u16                     br_mode;
1549
1550         struct bnxt_coal_cap    coal_cap;
1551         struct bnxt_coal        rx_coal;
1552         struct bnxt_coal        tx_coal;
1553
1554         u32                     stats_coal_ticks;
1555 #define BNXT_DEF_STATS_COAL_TICKS        1000000
1556 #define BNXT_MIN_STATS_COAL_TICKS         250000
1557 #define BNXT_MAX_STATS_COAL_TICKS        1000000
1558
1559         struct work_struct      sp_task;
1560         unsigned long           sp_event;
1561 #define BNXT_RX_MASK_SP_EVENT           0
1562 #define BNXT_RX_NTP_FLTR_SP_EVENT       1
1563 #define BNXT_LINK_CHNG_SP_EVENT         2
1564 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1565 #define BNXT_VXLAN_ADD_PORT_SP_EVENT    4
1566 #define BNXT_VXLAN_DEL_PORT_SP_EVENT    5
1567 #define BNXT_RESET_TASK_SP_EVENT        6
1568 #define BNXT_RST_RING_SP_EVENT          7
1569 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT    8
1570 #define BNXT_PERIODIC_STATS_SP_EVENT    9
1571 #define BNXT_HWRM_PORT_MODULE_SP_EVENT  10
1572 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1573 #define BNXT_GENEVE_ADD_PORT_SP_EVENT   12
1574 #define BNXT_GENEVE_DEL_PORT_SP_EVENT   13
1575 #define BNXT_LINK_SPEED_CHNG_SP_EVENT   14
1576 #define BNXT_FLOW_STATS_SP_EVENT        15
1577 #define BNXT_UPDATE_PHY_SP_EVENT        16
1578 #define BNXT_RING_COAL_NOW_SP_EVENT     17
1579
1580         struct bnxt_hw_resc     hw_resc;
1581         struct bnxt_pf_info     pf;
1582         struct bnxt_ctx_mem_info        *ctx;
1583 #ifdef CONFIG_BNXT_SRIOV
1584         int                     nr_vfs;
1585         struct bnxt_vf_info     vf;
1586         wait_queue_head_t       sriov_cfg_wait;
1587         bool                    sriov_cfg;
1588 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1589
1590         /* lock to protect VF-rep creation/cleanup via
1591          * multiple paths such as ->sriov_configure() and
1592          * devlink ->eswitch_mode_set()
1593          */
1594         struct mutex            sriov_lock;
1595 #endif
1596
1597 #if BITS_PER_LONG == 32
1598         /* ensure atomic 64-bit doorbell writes on 32-bit systems. */
1599         spinlock_t              db_lock;
1600 #endif
1601
1602 #define BNXT_NTP_FLTR_MAX_FLTR  4096
1603 #define BNXT_NTP_FLTR_HASH_SIZE 512
1604 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1605         struct hlist_head       ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1606         spinlock_t              ntp_fltr_lock;  /* for hash table add, del */
1607
1608         unsigned long           *ntp_fltr_bmap;
1609         int                     ntp_fltr_count;
1610
1611         /* To protect link related settings during link changes and
1612          * ethtool settings changes.
1613          */
1614         struct mutex            link_lock;
1615         struct bnxt_link_info   link_info;
1616         struct ethtool_eee      eee;
1617         u32                     lpi_tmr_lo;
1618         u32                     lpi_tmr_hi;
1619
1620         u8                      num_tests;
1621         struct bnxt_test_info   *test_info;
1622
1623         u8                      wol_filter_id;
1624         u8                      wol;
1625
1626         u8                      num_leds;
1627         struct bnxt_led_info    leds[BNXT_MAX_LED];
1628
1629         struct bpf_prog         *xdp_prog;
1630
1631         /* devlink interface and vf-rep structs */
1632         struct devlink          *dl;
1633         struct devlink_port     dl_port;
1634         enum devlink_eswitch_mode eswitch_mode;
1635         struct bnxt_vf_rep      **vf_reps; /* array of vf-rep ptrs */
1636         u16                     *cfa_code_map; /* cfa_code -> vf_idx map */
1637         u8                      switch_id[8];
1638         struct bnxt_tc_info     *tc_info;
1639         struct dentry           *debugfs_pdev;
1640         struct dentry           *debugfs_dim;
1641         struct device           *hwmon_dev;
1642 };
1643
1644 #define BNXT_RX_STATS_OFFSET(counter)                   \
1645         (offsetof(struct rx_port_stats, counter) / 8)
1646
1647 #define BNXT_TX_STATS_OFFSET(counter)                   \
1648         ((offsetof(struct tx_port_stats, counter) +     \
1649           sizeof(struct rx_port_stats) + 512) / 8)
1650
1651 #define BNXT_RX_STATS_EXT_OFFSET(counter)               \
1652         (offsetof(struct rx_port_stats_ext, counter) / 8)
1653
1654 #define BNXT_TX_STATS_EXT_OFFSET(counter)               \
1655         (offsetof(struct tx_port_stats_ext, counter) / 8)
1656
1657 #define BNXT_PCIE_STATS_OFFSET(counter)                 \
1658         (offsetof(struct pcie_ctx_hw_stats, counter) / 8)
1659
1660 #define I2C_DEV_ADDR_A0                         0xa0
1661 #define I2C_DEV_ADDR_A2                         0xa2
1662 #define SFF_DIAG_SUPPORT_OFFSET                 0x5c
1663 #define SFF_MODULE_ID_SFP                       0x3
1664 #define SFF_MODULE_ID_QSFP                      0xc
1665 #define SFF_MODULE_ID_QSFP_PLUS                 0xd
1666 #define SFF_MODULE_ID_QSFP28                    0x11
1667 #define BNXT_MAX_PHY_I2C_RESP_SIZE              64
1668
1669 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
1670 {
1671         /* Tell compiler to fetch tx indices from memory. */
1672         barrier();
1673
1674         return bp->tx_ring_size -
1675                 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
1676 }
1677
1678 #if BITS_PER_LONG == 32
1679 #define writeq(val64, db)                       \
1680 do {                                            \
1681         spin_lock(&bp->db_lock);                \
1682         writel((val64) & 0xffffffff, db);       \
1683         writel((val64) >> 32, (db) + 4);        \
1684         spin_unlock(&bp->db_lock);              \
1685 } while (0)
1686
1687 #define writeq_relaxed writeq
1688 #endif
1689
1690 /* For TX and RX ring doorbells with no ordering guarantee*/
1691 static inline void bnxt_db_write_relaxed(struct bnxt *bp,
1692                                          struct bnxt_db_info *db, u32 idx)
1693 {
1694         if (bp->flags & BNXT_FLAG_CHIP_P5) {
1695                 writeq_relaxed(db->db_key64 | idx, db->doorbell);
1696         } else {
1697                 u32 db_val = db->db_key32 | idx;
1698
1699                 writel_relaxed(db_val, db->doorbell);
1700                 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1701                         writel_relaxed(db_val, db->doorbell);
1702         }
1703 }
1704
1705 /* For TX and RX ring doorbells */
1706 static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
1707                                  u32 idx)
1708 {
1709         if (bp->flags & BNXT_FLAG_CHIP_P5) {
1710                 writeq(db->db_key64 | idx, db->doorbell);
1711         } else {
1712                 u32 db_val = db->db_key32 | idx;
1713
1714                 writel(db_val, db->doorbell);
1715                 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1716                         writel(db_val, db->doorbell);
1717         }
1718 }
1719
1720 static inline bool bnxt_cfa_hwrm_message(u16 req_type)
1721 {
1722         switch (req_type) {
1723         case HWRM_CFA_ENCAP_RECORD_ALLOC:
1724         case HWRM_CFA_ENCAP_RECORD_FREE:
1725         case HWRM_CFA_DECAP_FILTER_ALLOC:
1726         case HWRM_CFA_DECAP_FILTER_FREE:
1727         case HWRM_CFA_NTUPLE_FILTER_ALLOC:
1728         case HWRM_CFA_NTUPLE_FILTER_FREE:
1729         case HWRM_CFA_NTUPLE_FILTER_CFG:
1730         case HWRM_CFA_EM_FLOW_ALLOC:
1731         case HWRM_CFA_EM_FLOW_FREE:
1732         case HWRM_CFA_EM_FLOW_CFG:
1733         case HWRM_CFA_FLOW_ALLOC:
1734         case HWRM_CFA_FLOW_FREE:
1735         case HWRM_CFA_FLOW_INFO:
1736         case HWRM_CFA_FLOW_FLUSH:
1737         case HWRM_CFA_FLOW_STATS:
1738         case HWRM_CFA_METER_PROFILE_ALLOC:
1739         case HWRM_CFA_METER_PROFILE_FREE:
1740         case HWRM_CFA_METER_PROFILE_CFG:
1741         case HWRM_CFA_METER_INSTANCE_ALLOC:
1742         case HWRM_CFA_METER_INSTANCE_FREE:
1743                 return true;
1744         default:
1745                 return false;
1746         }
1747 }
1748
1749 static inline bool bnxt_kong_hwrm_message(struct bnxt *bp, struct input *req)
1750 {
1751         return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
1752                 bnxt_cfa_hwrm_message(le16_to_cpu(req->req_type)));
1753 }
1754
1755 static inline bool bnxt_hwrm_kong_chnl(struct bnxt *bp, struct input *req)
1756 {
1757         return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
1758                 req->resp_addr == cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr));
1759 }
1760
1761 static inline void *bnxt_get_hwrm_resp_addr(struct bnxt *bp, void *req)
1762 {
1763         if (bnxt_hwrm_kong_chnl(bp, (struct input *)req))
1764                 return bp->hwrm_cmd_kong_resp_addr;
1765         else
1766                 return bp->hwrm_cmd_resp_addr;
1767 }
1768
1769 static inline u16 bnxt_get_hwrm_seq_id(struct bnxt *bp, u16 dst)
1770 {
1771         u16 seq_id;
1772
1773         if (dst == BNXT_HWRM_CHNL_CHIMP)
1774                 seq_id = bp->hwrm_cmd_seq++;
1775         else
1776                 seq_id = bp->hwrm_cmd_kong_seq++;
1777         return seq_id;
1778 }
1779
1780 extern const u16 bnxt_lhint_arr[];
1781
1782 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1783                        u16 prod, gfp_t gfp);
1784 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
1785 void bnxt_set_tpa_flags(struct bnxt *bp);
1786 void bnxt_set_ring_params(struct bnxt *);
1787 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
1788 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
1789 int _hwrm_send_message(struct bnxt *, void *, u32, int);
1790 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout);
1791 int hwrm_send_message(struct bnxt *, void *, u32, int);
1792 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
1793 int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
1794                                      int bmap_size);
1795 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
1796 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
1797 int bnxt_nq_rings_in_use(struct bnxt *bp);
1798 int bnxt_hwrm_set_coal(struct bnxt *);
1799 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
1800 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
1801 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
1802 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
1803 int bnxt_get_avail_msix(struct bnxt *bp, int num);
1804 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
1805 void bnxt_tx_disable(struct bnxt *bp);
1806 void bnxt_tx_enable(struct bnxt *bp);
1807 int bnxt_hwrm_set_pause(struct bnxt *);
1808 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
1809 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
1810 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
1811 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
1812 int bnxt_hwrm_fw_set_time(struct bnxt *);
1813 int bnxt_open_nic(struct bnxt *, bool, bool);
1814 int bnxt_half_open_nic(struct bnxt *bp);
1815 void bnxt_half_close_nic(struct bnxt *bp);
1816 int bnxt_close_nic(struct bnxt *, bool, bool);
1817 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
1818                      int tx_xdp);
1819 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
1820 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
1821 int bnxt_restore_pf_fw_resources(struct bnxt *bp);
1822 int bnxt_get_port_parent_id(struct net_device *dev,
1823                             struct netdev_phys_item_id *ppid);
1824 void bnxt_dim_work(struct work_struct *work);
1825 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
1826
1827 #endif