1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence MACB/GEM Ethernet Controller driver
5 * Copyright (C) 2004-2006 Atmel Corporation
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/clk-provider.h>
11 #include <linux/crc32.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/circ_buf.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_data/macb.h>
27 #include <linux/platform_device.h>
28 #include <linux/phylink.h>
30 #include <linux/of_device.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of_mdio.h>
33 #include <linux/of_net.h>
35 #include <linux/udp.h>
36 #include <linux/tcp.h>
37 #include <linux/iopoll.h>
38 #include <linux/pm_runtime.h>
41 /* This structure is only used for MACB on SiFive FU540 devices */
42 struct sifive_fu540_macb_mgmt {
48 #define MACB_RX_BUFFER_SIZE 128
49 #define RX_BUFFER_MULTIPLE 64 /* bytes */
51 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
52 #define MIN_RX_RING_SIZE 64
53 #define MAX_RX_RING_SIZE 8192
54 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
57 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
58 #define MIN_TX_RING_SIZE 64
59 #define MAX_TX_RING_SIZE 4096
60 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
63 /* level of occupied TX descriptors under which we wake up TX process */
64 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
66 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
67 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
70 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
73 /* Max length of transmit frame must be a multiple of 8 bytes */
74 #define MACB_TX_LEN_ALIGN 8
75 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
76 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
78 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
79 #define MACB_NETIF_LSO NETIF_F_TSO
81 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
82 #define MACB_WOL_ENABLED (0x1 << 1)
84 /* Graceful stop timeouts in us. We should allow up to
85 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
87 #define MACB_HALT_TIMEOUT 1230
89 #define MACB_PM_TIMEOUT 100 /* ms */
91 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
93 /* DMA buffer descriptor might be different size
94 * depends on hardware configuration:
96 * 1. dma address width 32 bits:
97 * word 1: 32 bit address of Data Buffer
100 * 2. dma address width 64 bits:
101 * word 1: 32 bit address of Data Buffer
103 * word 3: upper 32 bit address of Data Buffer
106 * 3. dma address width 32 bits with hardware timestamping:
107 * word 1: 32 bit address of Data Buffer
109 * word 3: timestamp word 1
110 * word 4: timestamp word 2
112 * 4. dma address width 64 bits with hardware timestamping:
113 * word 1: 32 bit address of Data Buffer
115 * word 3: upper 32 bit address of Data Buffer
117 * word 5: timestamp word 1
118 * word 6: timestamp word 2
120 static unsigned int macb_dma_desc_get_size(struct macb *bp)
123 unsigned int desc_size;
125 switch (bp->hw_dma_cap) {
127 desc_size = sizeof(struct macb_dma_desc)
128 + sizeof(struct macb_dma_desc_64);
131 desc_size = sizeof(struct macb_dma_desc)
132 + sizeof(struct macb_dma_desc_ptp);
134 case HW_DMA_CAP_64B_PTP:
135 desc_size = sizeof(struct macb_dma_desc)
136 + sizeof(struct macb_dma_desc_64)
137 + sizeof(struct macb_dma_desc_ptp);
140 desc_size = sizeof(struct macb_dma_desc);
144 return sizeof(struct macb_dma_desc);
147 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
150 switch (bp->hw_dma_cap) {
155 case HW_DMA_CAP_64B_PTP:
165 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
166 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
168 return (struct macb_dma_desc_64 *)((void *)desc
169 + sizeof(struct macb_dma_desc));
173 /* Ring buffer accessors */
174 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
176 return index & (bp->tx_ring_size - 1);
179 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
182 index = macb_tx_ring_wrap(queue->bp, index);
183 index = macb_adj_dma_desc_idx(queue->bp, index);
184 return &queue->tx_ring[index];
187 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
190 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
193 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
197 offset = macb_tx_ring_wrap(queue->bp, index) *
198 macb_dma_desc_get_size(queue->bp);
200 return queue->tx_ring_dma + offset;
203 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
205 return index & (bp->rx_ring_size - 1);
208 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
210 index = macb_rx_ring_wrap(queue->bp, index);
211 index = macb_adj_dma_desc_idx(queue->bp, index);
212 return &queue->rx_ring[index];
215 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
217 return queue->rx_buffers + queue->bp->rx_buffer_size *
218 macb_rx_ring_wrap(queue->bp, index);
222 static u32 hw_readl_native(struct macb *bp, int offset)
224 return __raw_readl(bp->regs + offset);
227 static void hw_writel_native(struct macb *bp, int offset, u32 value)
229 __raw_writel(value, bp->regs + offset);
232 static u32 hw_readl(struct macb *bp, int offset)
234 return readl_relaxed(bp->regs + offset);
237 static void hw_writel(struct macb *bp, int offset, u32 value)
239 writel_relaxed(value, bp->regs + offset);
242 /* Find the CPU endianness by using the loopback bit of NCR register. When the
243 * CPU is in big endian we need to program swapped mode for management
246 static bool hw_is_native_io(void __iomem *addr)
248 u32 value = MACB_BIT(LLB);
250 __raw_writel(value, addr + MACB_NCR);
251 value = __raw_readl(addr + MACB_NCR);
253 /* Write 0 back to disable everything */
254 __raw_writel(0, addr + MACB_NCR);
256 return value == MACB_BIT(LLB);
259 static bool hw_is_gem(void __iomem *addr, bool native_io)
264 id = __raw_readl(addr + MACB_MID);
266 id = readl_relaxed(addr + MACB_MID);
268 return MACB_BFEXT(IDNUM, id) >= 0x2;
271 static void macb_set_hwaddr(struct macb *bp)
276 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
277 macb_or_gem_writel(bp, SA1B, bottom);
278 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
279 macb_or_gem_writel(bp, SA1T, top);
281 /* Clear unused address register sets */
282 macb_or_gem_writel(bp, SA2B, 0);
283 macb_or_gem_writel(bp, SA2T, 0);
284 macb_or_gem_writel(bp, SA3B, 0);
285 macb_or_gem_writel(bp, SA3T, 0);
286 macb_or_gem_writel(bp, SA4B, 0);
287 macb_or_gem_writel(bp, SA4T, 0);
290 static void macb_get_hwaddr(struct macb *bp)
297 /* Check all 4 address register for valid address */
298 for (i = 0; i < 4; i++) {
299 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
300 top = macb_or_gem_readl(bp, SA1T + i * 8);
302 addr[0] = bottom & 0xff;
303 addr[1] = (bottom >> 8) & 0xff;
304 addr[2] = (bottom >> 16) & 0xff;
305 addr[3] = (bottom >> 24) & 0xff;
306 addr[4] = top & 0xff;
307 addr[5] = (top >> 8) & 0xff;
309 if (is_valid_ether_addr(addr)) {
310 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
315 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
316 eth_hw_addr_random(bp->dev);
319 static int macb_mdio_wait_for_idle(struct macb *bp)
323 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
324 1, MACB_MDIO_TIMEOUT);
327 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
329 struct macb *bp = bus->priv;
332 status = pm_runtime_get_sync(&bp->pdev->dev);
336 status = macb_mdio_wait_for_idle(bp);
340 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
341 | MACB_BF(RW, MACB_MAN_READ)
342 | MACB_BF(PHYA, mii_id)
343 | MACB_BF(REGA, regnum)
344 | MACB_BF(CODE, MACB_MAN_CODE)));
346 status = macb_mdio_wait_for_idle(bp);
350 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
353 pm_runtime_mark_last_busy(&bp->pdev->dev);
354 pm_runtime_put_autosuspend(&bp->pdev->dev);
359 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
362 struct macb *bp = bus->priv;
365 status = pm_runtime_get_sync(&bp->pdev->dev);
369 status = macb_mdio_wait_for_idle(bp);
371 goto mdio_write_exit;
373 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
374 | MACB_BF(RW, MACB_MAN_WRITE)
375 | MACB_BF(PHYA, mii_id)
376 | MACB_BF(REGA, regnum)
377 | MACB_BF(CODE, MACB_MAN_CODE)
378 | MACB_BF(DATA, value)));
380 status = macb_mdio_wait_for_idle(bp);
382 goto mdio_write_exit;
385 pm_runtime_mark_last_busy(&bp->pdev->dev);
386 pm_runtime_put_autosuspend(&bp->pdev->dev);
391 static void macb_init_buffers(struct macb *bp)
393 struct macb_queue *queue;
396 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
397 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
398 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
399 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
400 queue_writel(queue, RBQPH,
401 upper_32_bits(queue->rx_ring_dma));
403 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
404 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
405 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
406 queue_writel(queue, TBQPH,
407 upper_32_bits(queue->tx_ring_dma));
413 * macb_set_tx_clk() - Set a clock to a new frequency
414 * @clk Pointer to the clock to change
415 * @rate New frequency in Hz
416 * @dev Pointer to the struct net_device
418 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
420 long ferr, rate, rate_rounded;
439 rate_rounded = clk_round_rate(clk, rate);
440 if (rate_rounded < 0)
443 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
446 ferr = abs(rate_rounded - rate);
447 ferr = DIV_ROUND_UP(ferr, rate / 100000);
449 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
452 if (clk_set_rate(clk, rate_rounded))
453 netdev_err(dev, "adjusting tx_clk failed.\n");
456 static void macb_validate(struct phylink_config *config,
457 unsigned long *supported,
458 struct phylink_link_state *state)
460 struct net_device *ndev = to_net_dev(config->dev);
461 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
462 struct macb *bp = netdev_priv(ndev);
464 /* We only support MII, RMII, GMII, RGMII & SGMII. */
465 if (state->interface != PHY_INTERFACE_MODE_NA &&
466 state->interface != PHY_INTERFACE_MODE_MII &&
467 state->interface != PHY_INTERFACE_MODE_RMII &&
468 state->interface != PHY_INTERFACE_MODE_GMII &&
469 state->interface != PHY_INTERFACE_MODE_SGMII &&
470 !phy_interface_mode_is_rgmii(state->interface)) {
471 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
475 if (!macb_is_gem(bp) &&
476 (state->interface == PHY_INTERFACE_MODE_GMII ||
477 phy_interface_mode_is_rgmii(state->interface))) {
478 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
482 phylink_set_port_modes(mask);
483 phylink_set(mask, Autoneg);
484 phylink_set(mask, Asym_Pause);
486 phylink_set(mask, 10baseT_Half);
487 phylink_set(mask, 10baseT_Full);
488 phylink_set(mask, 100baseT_Half);
489 phylink_set(mask, 100baseT_Full);
491 if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE &&
492 (state->interface == PHY_INTERFACE_MODE_NA ||
493 state->interface == PHY_INTERFACE_MODE_GMII ||
494 state->interface == PHY_INTERFACE_MODE_SGMII ||
495 phy_interface_mode_is_rgmii(state->interface))) {
496 phylink_set(mask, 1000baseT_Full);
497 phylink_set(mask, 1000baseX_Full);
499 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
500 phylink_set(mask, 1000baseT_Half);
503 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
504 bitmap_and(state->advertising, state->advertising, mask,
505 __ETHTOOL_LINK_MODE_MASK_NBITS);
508 static void macb_mac_pcs_get_state(struct phylink_config *config,
509 struct phylink_link_state *state)
514 static void macb_mac_an_restart(struct phylink_config *config)
519 static void macb_mac_config(struct phylink_config *config, unsigned int mode,
520 const struct phylink_link_state *state)
522 struct net_device *ndev = to_net_dev(config->dev);
523 struct macb *bp = netdev_priv(ndev);
527 spin_lock_irqsave(&bp->lock, flags);
529 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
531 /* Clear all the bits we might set later */
532 ctrl &= ~(GEM_BIT(GBE) | MACB_BIT(SPD) | MACB_BIT(FD) | MACB_BIT(PAE) |
533 GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
535 if (state->speed == SPEED_1000)
536 ctrl |= GEM_BIT(GBE);
537 else if (state->speed == SPEED_100)
538 ctrl |= MACB_BIT(SPD);
541 ctrl |= MACB_BIT(FD);
543 /* We do not support MLO_PAUSE_RX yet */
544 if (state->pause & MLO_PAUSE_TX)
545 ctrl |= MACB_BIT(PAE);
547 if (state->interface == PHY_INTERFACE_MODE_SGMII)
548 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
550 /* Apply the new configuration, if any */
552 macb_or_gem_writel(bp, NCFGR, ctrl);
554 bp->speed = state->speed;
556 spin_unlock_irqrestore(&bp->lock, flags);
559 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
560 phy_interface_t interface)
562 struct net_device *ndev = to_net_dev(config->dev);
563 struct macb *bp = netdev_priv(ndev);
564 struct macb_queue *queue;
568 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
569 queue_writel(queue, IDR,
570 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
572 /* Disable Rx and Tx */
573 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
574 macb_writel(bp, NCR, ctrl);
576 netif_tx_stop_all_queues(ndev);
579 static void macb_mac_link_up(struct phylink_config *config, unsigned int mode,
580 phy_interface_t interface, struct phy_device *phy)
582 struct net_device *ndev = to_net_dev(config->dev);
583 struct macb *bp = netdev_priv(ndev);
584 struct macb_queue *queue;
587 macb_set_tx_clk(bp->tx_clk, bp->speed, ndev);
589 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
590 * cleared the pipeline and control registers.
592 bp->macbgem_ops.mog_init_rings(bp);
593 macb_init_buffers(bp);
595 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
596 queue_writel(queue, IER,
597 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
599 /* Enable Rx and Tx */
600 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
602 netif_tx_wake_all_queues(ndev);
605 static const struct phylink_mac_ops macb_phylink_ops = {
606 .validate = macb_validate,
607 .mac_pcs_get_state = macb_mac_pcs_get_state,
608 .mac_an_restart = macb_mac_an_restart,
609 .mac_config = macb_mac_config,
610 .mac_link_down = macb_mac_link_down,
611 .mac_link_up = macb_mac_link_up,
614 static bool macb_phy_handle_exists(struct device_node *dn)
616 dn = of_parse_phandle(dn, "phy-handle", 0);
621 static int macb_phylink_connect(struct macb *bp)
623 struct device_node *dn = bp->pdev->dev.of_node;
624 struct net_device *dev = bp->dev;
625 struct phy_device *phydev;
629 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
631 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
632 phydev = phy_find_first(bp->mii_bus);
634 netdev_err(dev, "no PHY found\n");
638 /* attach the mac to the phy */
639 ret = phylink_connect_phy(bp->phylink, phydev);
643 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
647 phylink_start(bp->phylink);
652 /* based on au1000_eth. c*/
653 static int macb_mii_probe(struct net_device *dev)
655 struct macb *bp = netdev_priv(dev);
657 bp->phylink_config.dev = &dev->dev;
658 bp->phylink_config.type = PHYLINK_NETDEV;
660 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
661 bp->phy_interface, &macb_phylink_ops);
662 if (IS_ERR(bp->phylink)) {
663 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
664 PTR_ERR(bp->phylink));
665 return PTR_ERR(bp->phylink);
671 static int macb_mdiobus_register(struct macb *bp)
673 struct device_node *child, *np = bp->pdev->dev.of_node;
675 /* Only create the PHY from the device tree if at least one PHY is
676 * described. Otherwise scan the entire MDIO bus. We do this to support
677 * old device tree that did not follow the best practices and did not
678 * describe their network PHYs.
680 for_each_available_child_of_node(np, child)
681 if (of_mdiobus_child_is_phy(child)) {
682 /* The loop increments the child refcount,
683 * decrement it before returning.
687 return of_mdiobus_register(bp->mii_bus, np);
690 return mdiobus_register(bp->mii_bus);
693 static int macb_mii_init(struct macb *bp)
697 /* Enable management port */
698 macb_writel(bp, NCR, MACB_BIT(MPE));
700 bp->mii_bus = mdiobus_alloc();
706 bp->mii_bus->name = "MACB_mii_bus";
707 bp->mii_bus->read = &macb_mdio_read;
708 bp->mii_bus->write = &macb_mdio_write;
709 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
710 bp->pdev->name, bp->pdev->id);
711 bp->mii_bus->priv = bp;
712 bp->mii_bus->parent = &bp->pdev->dev;
714 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
716 err = macb_mdiobus_register(bp);
718 goto err_out_free_mdiobus;
720 err = macb_mii_probe(bp->dev);
722 goto err_out_unregister_bus;
726 err_out_unregister_bus:
727 mdiobus_unregister(bp->mii_bus);
728 err_out_free_mdiobus:
729 mdiobus_free(bp->mii_bus);
734 static void macb_update_stats(struct macb *bp)
736 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
737 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
738 int offset = MACB_PFR;
740 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
742 for (; p < end; p++, offset += 4)
743 *p += bp->macb_reg_readl(bp, offset);
746 static int macb_halt_tx(struct macb *bp)
748 unsigned long halt_time, timeout;
751 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
753 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
756 status = macb_readl(bp, TSR);
757 if (!(status & MACB_BIT(TGO)))
761 } while (time_before(halt_time, timeout));
766 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
768 if (tx_skb->mapping) {
769 if (tx_skb->mapped_as_page)
770 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
771 tx_skb->size, DMA_TO_DEVICE);
773 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
774 tx_skb->size, DMA_TO_DEVICE);
779 dev_kfree_skb_any(tx_skb->skb);
784 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
786 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
787 struct macb_dma_desc_64 *desc_64;
789 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
790 desc_64 = macb_64b_desc(bp, desc);
791 desc_64->addrh = upper_32_bits(addr);
792 /* The low bits of RX address contain the RX_USED bit, clearing
793 * of which allows packet RX. Make sure the high bits are also
794 * visible to HW at that point.
799 desc->addr = lower_32_bits(addr);
802 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
805 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
806 struct macb_dma_desc_64 *desc_64;
808 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
809 desc_64 = macb_64b_desc(bp, desc);
810 addr = ((u64)(desc_64->addrh) << 32);
813 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
817 static void macb_tx_error_task(struct work_struct *work)
819 struct macb_queue *queue = container_of(work, struct macb_queue,
821 struct macb *bp = queue->bp;
822 struct macb_tx_skb *tx_skb;
823 struct macb_dma_desc *desc;
828 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
829 (unsigned int)(queue - bp->queues),
830 queue->tx_tail, queue->tx_head);
832 /* Prevent the queue IRQ handlers from running: each of them may call
833 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
834 * As explained below, we have to halt the transmission before updating
835 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
836 * network engine about the macb/gem being halted.
838 spin_lock_irqsave(&bp->lock, flags);
840 /* Make sure nobody is trying to queue up new packets */
841 netif_tx_stop_all_queues(bp->dev);
843 /* Stop transmission now
844 * (in case we have just queued new packets)
845 * macb/gem must be halted to write TBQP register
847 if (macb_halt_tx(bp))
848 /* Just complain for now, reinitializing TX path can be good */
849 netdev_err(bp->dev, "BUG: halt tx timed out\n");
851 /* Treat frames in TX queue including the ones that caused the error.
852 * Free transmit buffers in upper layer.
854 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
857 desc = macb_tx_desc(queue, tail);
859 tx_skb = macb_tx_skb(queue, tail);
862 if (ctrl & MACB_BIT(TX_USED)) {
863 /* skb is set for the last buffer of the frame */
865 macb_tx_unmap(bp, tx_skb);
867 tx_skb = macb_tx_skb(queue, tail);
871 /* ctrl still refers to the first buffer descriptor
872 * since it's the only one written back by the hardware
874 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
875 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
876 macb_tx_ring_wrap(bp, tail),
878 bp->dev->stats.tx_packets++;
879 queue->stats.tx_packets++;
880 bp->dev->stats.tx_bytes += skb->len;
881 queue->stats.tx_bytes += skb->len;
884 /* "Buffers exhausted mid-frame" errors may only happen
885 * if the driver is buggy, so complain loudly about
886 * those. Statistics are updated by hardware.
888 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
890 "BUG: TX buffers exhausted mid-frame\n");
892 desc->ctrl = ctrl | MACB_BIT(TX_USED);
895 macb_tx_unmap(bp, tx_skb);
898 /* Set end of TX queue */
899 desc = macb_tx_desc(queue, 0);
900 macb_set_addr(bp, desc, 0);
901 desc->ctrl = MACB_BIT(TX_USED);
903 /* Make descriptor updates visible to hardware */
906 /* Reinitialize the TX desc queue */
907 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
908 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
909 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
910 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
912 /* Make TX ring reflect state of hardware */
916 /* Housework before enabling TX IRQ */
917 macb_writel(bp, TSR, macb_readl(bp, TSR));
918 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
920 /* Now we are ready to start transmission again */
921 netif_tx_start_all_queues(bp->dev);
922 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
924 spin_unlock_irqrestore(&bp->lock, flags);
927 static void macb_tx_interrupt(struct macb_queue *queue)
932 struct macb *bp = queue->bp;
933 u16 queue_index = queue - bp->queues;
935 status = macb_readl(bp, TSR);
936 macb_writel(bp, TSR, status);
938 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
939 queue_writel(queue, ISR, MACB_BIT(TCOMP));
941 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
942 (unsigned long)status);
944 head = queue->tx_head;
945 for (tail = queue->tx_tail; tail != head; tail++) {
946 struct macb_tx_skb *tx_skb;
948 struct macb_dma_desc *desc;
951 desc = macb_tx_desc(queue, tail);
953 /* Make hw descriptor updates visible to CPU */
958 /* TX_USED bit is only set by hardware on the very first buffer
959 * descriptor of the transmitted frame.
961 if (!(ctrl & MACB_BIT(TX_USED)))
964 /* Process all buffers of the current transmitted frame */
966 tx_skb = macb_tx_skb(queue, tail);
969 /* First, update TX stats if needed */
971 if (unlikely(skb_shinfo(skb)->tx_flags &
973 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
974 /* skb now belongs to timestamp buffer
975 * and will be removed later
979 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
980 macb_tx_ring_wrap(bp, tail),
982 bp->dev->stats.tx_packets++;
983 queue->stats.tx_packets++;
984 bp->dev->stats.tx_bytes += skb->len;
985 queue->stats.tx_bytes += skb->len;
988 /* Now we can safely release resources */
989 macb_tx_unmap(bp, tx_skb);
991 /* skb is set only for the last buffer of the frame.
992 * WARNING: at this point skb has been freed by
1000 queue->tx_tail = tail;
1001 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1002 CIRC_CNT(queue->tx_head, queue->tx_tail,
1003 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1004 netif_wake_subqueue(bp->dev, queue_index);
1007 static void gem_rx_refill(struct macb_queue *queue)
1010 struct sk_buff *skb;
1012 struct macb *bp = queue->bp;
1013 struct macb_dma_desc *desc;
1015 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1016 bp->rx_ring_size) > 0) {
1017 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1019 /* Make hw descriptor updates visible to CPU */
1022 queue->rx_prepared_head++;
1023 desc = macb_rx_desc(queue, entry);
1025 if (!queue->rx_skbuff[entry]) {
1026 /* allocate sk_buff for this free entry in ring */
1027 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1028 if (unlikely(!skb)) {
1030 "Unable to allocate sk_buff\n");
1034 /* now fill corresponding descriptor entry */
1035 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1038 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1043 queue->rx_skbuff[entry] = skb;
1045 if (entry == bp->rx_ring_size - 1)
1046 paddr |= MACB_BIT(RX_WRAP);
1048 /* Setting addr clears RX_USED and allows reception,
1049 * make sure ctrl is cleared first to avoid a race.
1052 macb_set_addr(bp, desc, paddr);
1054 /* properly align Ethernet header */
1055 skb_reserve(skb, NET_IP_ALIGN);
1059 desc->addr &= ~MACB_BIT(RX_USED);
1063 /* Make descriptor updates visible to hardware */
1066 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1067 queue, queue->rx_prepared_head, queue->rx_tail);
1070 /* Mark DMA descriptors from begin up to and not including end as unused */
1071 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1076 for (frag = begin; frag != end; frag++) {
1077 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1079 desc->addr &= ~MACB_BIT(RX_USED);
1082 /* Make descriptor updates visible to hardware */
1085 /* When this happens, the hardware stats registers for
1086 * whatever caused this is updated, so we don't have to record
1091 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1094 struct macb *bp = queue->bp;
1097 struct sk_buff *skb;
1098 struct macb_dma_desc *desc;
1101 while (count < budget) {
1106 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1107 desc = macb_rx_desc(queue, entry);
1109 /* Make hw descriptor updates visible to CPU */
1112 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1113 addr = macb_get_addr(bp, desc);
1118 /* Ensure ctrl is at least as up-to-date as rxused */
1126 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1128 "not whole frame pointed by descriptor\n");
1129 bp->dev->stats.rx_dropped++;
1130 queue->stats.rx_dropped++;
1133 skb = queue->rx_skbuff[entry];
1134 if (unlikely(!skb)) {
1136 "inconsistent Rx descriptor chain\n");
1137 bp->dev->stats.rx_dropped++;
1138 queue->stats.rx_dropped++;
1141 /* now everything is ready for receiving packet */
1142 queue->rx_skbuff[entry] = NULL;
1143 len = ctrl & bp->rx_frm_len_mask;
1145 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1148 dma_unmap_single(&bp->pdev->dev, addr,
1149 bp->rx_buffer_size, DMA_FROM_DEVICE);
1151 skb->protocol = eth_type_trans(skb, bp->dev);
1152 skb_checksum_none_assert(skb);
1153 if (bp->dev->features & NETIF_F_RXCSUM &&
1154 !(bp->dev->flags & IFF_PROMISC) &&
1155 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1156 skb->ip_summed = CHECKSUM_UNNECESSARY;
1158 bp->dev->stats.rx_packets++;
1159 queue->stats.rx_packets++;
1160 bp->dev->stats.rx_bytes += skb->len;
1161 queue->stats.rx_bytes += skb->len;
1163 gem_ptp_do_rxstamp(bp, skb, desc);
1165 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1166 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1167 skb->len, skb->csum);
1168 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1169 skb_mac_header(skb), 16, true);
1170 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1171 skb->data, 32, true);
1174 napi_gro_receive(napi, skb);
1177 gem_rx_refill(queue);
1182 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1183 unsigned int first_frag, unsigned int last_frag)
1187 unsigned int offset;
1188 struct sk_buff *skb;
1189 struct macb_dma_desc *desc;
1190 struct macb *bp = queue->bp;
1192 desc = macb_rx_desc(queue, last_frag);
1193 len = desc->ctrl & bp->rx_frm_len_mask;
1195 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1196 macb_rx_ring_wrap(bp, first_frag),
1197 macb_rx_ring_wrap(bp, last_frag), len);
1199 /* The ethernet header starts NET_IP_ALIGN bytes into the
1200 * first buffer. Since the header is 14 bytes, this makes the
1201 * payload word-aligned.
1203 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1204 * the two padding bytes into the skb so that we avoid hitting
1205 * the slowpath in memcpy(), and pull them off afterwards.
1207 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1209 bp->dev->stats.rx_dropped++;
1210 for (frag = first_frag; ; frag++) {
1211 desc = macb_rx_desc(queue, frag);
1212 desc->addr &= ~MACB_BIT(RX_USED);
1213 if (frag == last_frag)
1217 /* Make descriptor updates visible to hardware */
1224 len += NET_IP_ALIGN;
1225 skb_checksum_none_assert(skb);
1228 for (frag = first_frag; ; frag++) {
1229 unsigned int frag_len = bp->rx_buffer_size;
1231 if (offset + frag_len > len) {
1232 if (unlikely(frag != last_frag)) {
1233 dev_kfree_skb_any(skb);
1236 frag_len = len - offset;
1238 skb_copy_to_linear_data_offset(skb, offset,
1239 macb_rx_buffer(queue, frag),
1241 offset += bp->rx_buffer_size;
1242 desc = macb_rx_desc(queue, frag);
1243 desc->addr &= ~MACB_BIT(RX_USED);
1245 if (frag == last_frag)
1249 /* Make descriptor updates visible to hardware */
1252 __skb_pull(skb, NET_IP_ALIGN);
1253 skb->protocol = eth_type_trans(skb, bp->dev);
1255 bp->dev->stats.rx_packets++;
1256 bp->dev->stats.rx_bytes += skb->len;
1257 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1258 skb->len, skb->csum);
1259 napi_gro_receive(napi, skb);
1264 static inline void macb_init_rx_ring(struct macb_queue *queue)
1266 struct macb *bp = queue->bp;
1268 struct macb_dma_desc *desc = NULL;
1271 addr = queue->rx_buffers_dma;
1272 for (i = 0; i < bp->rx_ring_size; i++) {
1273 desc = macb_rx_desc(queue, i);
1274 macb_set_addr(bp, desc, addr);
1276 addr += bp->rx_buffer_size;
1278 desc->addr |= MACB_BIT(RX_WRAP);
1282 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1285 struct macb *bp = queue->bp;
1286 bool reset_rx_queue = false;
1289 int first_frag = -1;
1291 for (tail = queue->rx_tail; budget > 0; tail++) {
1292 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1295 /* Make hw descriptor updates visible to CPU */
1298 if (!(desc->addr & MACB_BIT(RX_USED)))
1301 /* Ensure ctrl is at least as up-to-date as addr */
1306 if (ctrl & MACB_BIT(RX_SOF)) {
1307 if (first_frag != -1)
1308 discard_partial_frame(queue, first_frag, tail);
1312 if (ctrl & MACB_BIT(RX_EOF)) {
1315 if (unlikely(first_frag == -1)) {
1316 reset_rx_queue = true;
1320 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1322 if (unlikely(dropped < 0)) {
1323 reset_rx_queue = true;
1333 if (unlikely(reset_rx_queue)) {
1334 unsigned long flags;
1337 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1339 spin_lock_irqsave(&bp->lock, flags);
1341 ctrl = macb_readl(bp, NCR);
1342 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1344 macb_init_rx_ring(queue);
1345 queue_writel(queue, RBQP, queue->rx_ring_dma);
1347 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1349 spin_unlock_irqrestore(&bp->lock, flags);
1353 if (first_frag != -1)
1354 queue->rx_tail = first_frag;
1356 queue->rx_tail = tail;
1361 static int macb_poll(struct napi_struct *napi, int budget)
1363 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1364 struct macb *bp = queue->bp;
1368 status = macb_readl(bp, RSR);
1369 macb_writel(bp, RSR, status);
1371 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1372 (unsigned long)status, budget);
1374 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1375 if (work_done < budget) {
1376 napi_complete_done(napi, work_done);
1378 /* Packets received while interrupts were disabled */
1379 status = macb_readl(bp, RSR);
1381 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1382 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1383 napi_reschedule(napi);
1385 queue_writel(queue, IER, bp->rx_intr_mask);
1389 /* TODO: Handle errors */
1394 static void macb_hresp_error_task(unsigned long data)
1396 struct macb *bp = (struct macb *)data;
1397 struct net_device *dev = bp->dev;
1398 struct macb_queue *queue = bp->queues;
1402 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1403 queue_writel(queue, IDR, bp->rx_intr_mask |
1407 ctrl = macb_readl(bp, NCR);
1408 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1409 macb_writel(bp, NCR, ctrl);
1411 netif_tx_stop_all_queues(dev);
1412 netif_carrier_off(dev);
1414 bp->macbgem_ops.mog_init_rings(bp);
1416 /* Initialize TX and RX buffers */
1417 macb_init_buffers(bp);
1419 /* Enable interrupts */
1420 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1421 queue_writel(queue, IER,
1426 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1427 macb_writel(bp, NCR, ctrl);
1429 netif_carrier_on(dev);
1430 netif_tx_start_all_queues(dev);
1433 static void macb_tx_restart(struct macb_queue *queue)
1435 unsigned int head = queue->tx_head;
1436 unsigned int tail = queue->tx_tail;
1437 struct macb *bp = queue->bp;
1439 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1440 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1445 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1448 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1450 struct macb_queue *queue = dev_id;
1451 struct macb *bp = queue->bp;
1452 struct net_device *dev = bp->dev;
1455 status = queue_readl(queue, ISR);
1457 if (unlikely(!status))
1460 spin_lock(&bp->lock);
1463 /* close possible race with dev_close */
1464 if (unlikely(!netif_running(dev))) {
1465 queue_writel(queue, IDR, -1);
1466 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1467 queue_writel(queue, ISR, -1);
1471 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1472 (unsigned int)(queue - bp->queues),
1473 (unsigned long)status);
1475 if (status & bp->rx_intr_mask) {
1476 /* There's no point taking any more interrupts
1477 * until we have processed the buffers. The
1478 * scheduling call may fail if the poll routine
1479 * is already scheduled, so disable interrupts
1482 queue_writel(queue, IDR, bp->rx_intr_mask);
1483 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1484 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1486 if (napi_schedule_prep(&queue->napi)) {
1487 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1488 __napi_schedule(&queue->napi);
1492 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1493 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1494 schedule_work(&queue->tx_error_task);
1496 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1497 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1502 if (status & MACB_BIT(TCOMP))
1503 macb_tx_interrupt(queue);
1505 if (status & MACB_BIT(TXUBR))
1506 macb_tx_restart(queue);
1508 /* Link change detection isn't possible with RMII, so we'll
1509 * add that if/when we get our hands on a full-blown MII PHY.
1512 /* There is a hardware issue under heavy load where DMA can
1513 * stop, this causes endless "used buffer descriptor read"
1514 * interrupts but it can be cleared by re-enabling RX. See
1515 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1516 * section 16.7.4 for details. RXUBR is only enabled for
1517 * these two versions.
1519 if (status & MACB_BIT(RXUBR)) {
1520 ctrl = macb_readl(bp, NCR);
1521 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1523 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1525 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1526 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1529 if (status & MACB_BIT(ISR_ROVR)) {
1530 /* We missed at least one packet */
1531 if (macb_is_gem(bp))
1532 bp->hw_stats.gem.rx_overruns++;
1534 bp->hw_stats.macb.rx_overruns++;
1536 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1537 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1540 if (status & MACB_BIT(HRESP)) {
1541 tasklet_schedule(&bp->hresp_err_tasklet);
1542 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1544 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1545 queue_writel(queue, ISR, MACB_BIT(HRESP));
1547 status = queue_readl(queue, ISR);
1550 spin_unlock(&bp->lock);
1555 #ifdef CONFIG_NET_POLL_CONTROLLER
1556 /* Polling receive - used by netconsole and other diagnostic tools
1557 * to allow network i/o with interrupts disabled.
1559 static void macb_poll_controller(struct net_device *dev)
1561 struct macb *bp = netdev_priv(dev);
1562 struct macb_queue *queue;
1563 unsigned long flags;
1566 local_irq_save(flags);
1567 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1568 macb_interrupt(dev->irq, queue);
1569 local_irq_restore(flags);
1573 static unsigned int macb_tx_map(struct macb *bp,
1574 struct macb_queue *queue,
1575 struct sk_buff *skb,
1576 unsigned int hdrlen)
1579 unsigned int len, entry, i, tx_head = queue->tx_head;
1580 struct macb_tx_skb *tx_skb = NULL;
1581 struct macb_dma_desc *desc;
1582 unsigned int offset, size, count = 0;
1583 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1584 unsigned int eof = 1, mss_mfs = 0;
1585 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1588 if (skb_shinfo(skb)->gso_size != 0) {
1589 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1591 lso_ctrl = MACB_LSO_UFO_ENABLE;
1594 lso_ctrl = MACB_LSO_TSO_ENABLE;
1597 /* First, map non-paged data */
1598 len = skb_headlen(skb);
1600 /* first buffer length */
1605 entry = macb_tx_ring_wrap(bp, tx_head);
1606 tx_skb = &queue->tx_skb[entry];
1608 mapping = dma_map_single(&bp->pdev->dev,
1610 size, DMA_TO_DEVICE);
1611 if (dma_mapping_error(&bp->pdev->dev, mapping))
1614 /* Save info to properly release resources */
1616 tx_skb->mapping = mapping;
1617 tx_skb->size = size;
1618 tx_skb->mapped_as_page = false;
1625 size = min(len, bp->max_tx_length);
1628 /* Then, map paged data from fragments */
1629 for (f = 0; f < nr_frags; f++) {
1630 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1632 len = skb_frag_size(frag);
1635 size = min(len, bp->max_tx_length);
1636 entry = macb_tx_ring_wrap(bp, tx_head);
1637 tx_skb = &queue->tx_skb[entry];
1639 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1640 offset, size, DMA_TO_DEVICE);
1641 if (dma_mapping_error(&bp->pdev->dev, mapping))
1644 /* Save info to properly release resources */
1646 tx_skb->mapping = mapping;
1647 tx_skb->size = size;
1648 tx_skb->mapped_as_page = true;
1657 /* Should never happen */
1658 if (unlikely(!tx_skb)) {
1659 netdev_err(bp->dev, "BUG! empty skb!\n");
1663 /* This is the last buffer of the frame: save socket buffer */
1666 /* Update TX ring: update buffer descriptors in reverse order
1667 * to avoid race condition
1670 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1671 * to set the end of TX queue
1674 entry = macb_tx_ring_wrap(bp, i);
1675 ctrl = MACB_BIT(TX_USED);
1676 desc = macb_tx_desc(queue, entry);
1680 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1681 /* include header and FCS in value given to h/w */
1682 mss_mfs = skb_shinfo(skb)->gso_size +
1683 skb_transport_offset(skb) +
1686 mss_mfs = skb_shinfo(skb)->gso_size;
1687 /* TCP Sequence Number Source Select
1688 * can be set only for TSO
1696 entry = macb_tx_ring_wrap(bp, i);
1697 tx_skb = &queue->tx_skb[entry];
1698 desc = macb_tx_desc(queue, entry);
1700 ctrl = (u32)tx_skb->size;
1702 ctrl |= MACB_BIT(TX_LAST);
1705 if (unlikely(entry == (bp->tx_ring_size - 1)))
1706 ctrl |= MACB_BIT(TX_WRAP);
1708 /* First descriptor is header descriptor */
1709 if (i == queue->tx_head) {
1710 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1711 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1712 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
1713 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
1714 ctrl |= MACB_BIT(TX_NOCRC);
1716 /* Only set MSS/MFS on payload descriptors
1717 * (second or later descriptor)
1719 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1721 /* Set TX buffer descriptor */
1722 macb_set_addr(bp, desc, tx_skb->mapping);
1723 /* desc->addr must be visible to hardware before clearing
1724 * 'TX_USED' bit in desc->ctrl.
1728 } while (i != queue->tx_head);
1730 queue->tx_head = tx_head;
1735 netdev_err(bp->dev, "TX DMA map failed\n");
1737 for (i = queue->tx_head; i != tx_head; i++) {
1738 tx_skb = macb_tx_skb(queue, i);
1740 macb_tx_unmap(bp, tx_skb);
1746 static netdev_features_t macb_features_check(struct sk_buff *skb,
1747 struct net_device *dev,
1748 netdev_features_t features)
1750 unsigned int nr_frags, f;
1751 unsigned int hdrlen;
1753 /* Validate LSO compatibility */
1755 /* there is only one buffer */
1756 if (!skb_is_nonlinear(skb))
1759 /* length of header */
1760 hdrlen = skb_transport_offset(skb);
1761 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
1762 hdrlen += tcp_hdrlen(skb);
1765 * When software supplies two or more payload buffers all payload buffers
1766 * apart from the last must be a multiple of 8 bytes in size.
1768 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1769 return features & ~MACB_NETIF_LSO;
1771 nr_frags = skb_shinfo(skb)->nr_frags;
1772 /* No need to check last fragment */
1774 for (f = 0; f < nr_frags; f++) {
1775 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1777 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1778 return features & ~MACB_NETIF_LSO;
1783 static inline int macb_clear_csum(struct sk_buff *skb)
1785 /* no change for packets without checksum offloading */
1786 if (skb->ip_summed != CHECKSUM_PARTIAL)
1789 /* make sure we can modify the header */
1790 if (unlikely(skb_cow_head(skb, 0)))
1793 /* initialize checksum field
1794 * This is required - at least for Zynq, which otherwise calculates
1795 * wrong UDP header checksums for UDP packets with UDP data len <=2
1797 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1801 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
1803 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb);
1804 int padlen = ETH_ZLEN - (*skb)->len;
1805 int headroom = skb_headroom(*skb);
1806 int tailroom = skb_tailroom(*skb);
1807 struct sk_buff *nskb;
1810 if (!(ndev->features & NETIF_F_HW_CSUM) ||
1811 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
1812 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
1816 /* FCS could be appeded to tailroom. */
1817 if (tailroom >= ETH_FCS_LEN)
1819 /* FCS could be appeded by moving data to headroom. */
1820 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
1822 /* No room for FCS, need to reallocate skb. */
1824 padlen = ETH_FCS_LEN;
1826 /* Add room for FCS. */
1827 padlen += ETH_FCS_LEN;
1830 if (!cloned && headroom + tailroom >= padlen) {
1831 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
1832 skb_set_tail_pointer(*skb, (*skb)->len);
1834 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
1838 dev_consume_skb_any(*skb);
1842 if (padlen > ETH_FCS_LEN)
1843 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
1846 /* set FCS to packet */
1847 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
1850 skb_put_u8(*skb, fcs & 0xff);
1851 skb_put_u8(*skb, (fcs >> 8) & 0xff);
1852 skb_put_u8(*skb, (fcs >> 16) & 0xff);
1853 skb_put_u8(*skb, (fcs >> 24) & 0xff);
1858 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1860 u16 queue_index = skb_get_queue_mapping(skb);
1861 struct macb *bp = netdev_priv(dev);
1862 struct macb_queue *queue = &bp->queues[queue_index];
1863 unsigned long flags;
1864 unsigned int desc_cnt, nr_frags, frag_size, f;
1865 unsigned int hdrlen;
1866 bool is_lso, is_udp = 0;
1867 netdev_tx_t ret = NETDEV_TX_OK;
1869 if (macb_clear_csum(skb)) {
1870 dev_kfree_skb_any(skb);
1874 if (macb_pad_and_fcs(&skb, dev)) {
1875 dev_kfree_skb_any(skb);
1879 is_lso = (skb_shinfo(skb)->gso_size != 0);
1882 is_udp = !!(ip_hdr(skb)->protocol == IPPROTO_UDP);
1884 /* length of headers */
1886 /* only queue eth + ip headers separately for UDP */
1887 hdrlen = skb_transport_offset(skb);
1889 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
1890 if (skb_headlen(skb) < hdrlen) {
1891 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
1892 /* if this is required, would need to copy to single buffer */
1893 return NETDEV_TX_BUSY;
1896 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
1898 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1899 netdev_vdbg(bp->dev,
1900 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1901 queue_index, skb->len, skb->head, skb->data,
1902 skb_tail_pointer(skb), skb_end_pointer(skb));
1903 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1904 skb->data, 16, true);
1907 /* Count how many TX buffer descriptors are needed to send this
1908 * socket buffer: skb fragments of jumbo frames may need to be
1909 * split into many buffer descriptors.
1911 if (is_lso && (skb_headlen(skb) > hdrlen))
1912 /* extra header descriptor if also payload in first buffer */
1913 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
1915 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1916 nr_frags = skb_shinfo(skb)->nr_frags;
1917 for (f = 0; f < nr_frags; f++) {
1918 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1919 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1922 spin_lock_irqsave(&bp->lock, flags);
1924 /* This is a hard error, log it. */
1925 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
1926 bp->tx_ring_size) < desc_cnt) {
1927 netif_stop_subqueue(dev, queue_index);
1928 spin_unlock_irqrestore(&bp->lock, flags);
1929 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1930 queue->tx_head, queue->tx_tail);
1931 return NETDEV_TX_BUSY;
1934 /* Map socket buffer for DMA transfer */
1935 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
1936 dev_kfree_skb_any(skb);
1940 /* Make newly initialized descriptor visible to hardware */
1942 skb_tx_timestamp(skb);
1944 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1946 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
1947 netif_stop_subqueue(dev, queue_index);
1950 spin_unlock_irqrestore(&bp->lock, flags);
1955 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1957 if (!macb_is_gem(bp)) {
1958 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1960 bp->rx_buffer_size = size;
1962 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1964 "RX buffer must be multiple of %d bytes, expanding\n",
1965 RX_BUFFER_MULTIPLE);
1966 bp->rx_buffer_size =
1967 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1971 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
1972 bp->dev->mtu, bp->rx_buffer_size);
1975 static void gem_free_rx_buffers(struct macb *bp)
1977 struct sk_buff *skb;
1978 struct macb_dma_desc *desc;
1979 struct macb_queue *queue;
1984 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1985 if (!queue->rx_skbuff)
1988 for (i = 0; i < bp->rx_ring_size; i++) {
1989 skb = queue->rx_skbuff[i];
1994 desc = macb_rx_desc(queue, i);
1995 addr = macb_get_addr(bp, desc);
1997 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1999 dev_kfree_skb_any(skb);
2003 kfree(queue->rx_skbuff);
2004 queue->rx_skbuff = NULL;
2008 static void macb_free_rx_buffers(struct macb *bp)
2010 struct macb_queue *queue = &bp->queues[0];
2012 if (queue->rx_buffers) {
2013 dma_free_coherent(&bp->pdev->dev,
2014 bp->rx_ring_size * bp->rx_buffer_size,
2015 queue->rx_buffers, queue->rx_buffers_dma);
2016 queue->rx_buffers = NULL;
2020 static void macb_free_consistent(struct macb *bp)
2022 struct macb_queue *queue;
2026 bp->macbgem_ops.mog_free_rx_buffers(bp);
2028 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2029 kfree(queue->tx_skb);
2030 queue->tx_skb = NULL;
2031 if (queue->tx_ring) {
2032 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2033 dma_free_coherent(&bp->pdev->dev, size,
2034 queue->tx_ring, queue->tx_ring_dma);
2035 queue->tx_ring = NULL;
2037 if (queue->rx_ring) {
2038 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2039 dma_free_coherent(&bp->pdev->dev, size,
2040 queue->rx_ring, queue->rx_ring_dma);
2041 queue->rx_ring = NULL;
2046 static int gem_alloc_rx_buffers(struct macb *bp)
2048 struct macb_queue *queue;
2052 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2053 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2054 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2055 if (!queue->rx_skbuff)
2059 "Allocated %d RX struct sk_buff entries at %p\n",
2060 bp->rx_ring_size, queue->rx_skbuff);
2065 static int macb_alloc_rx_buffers(struct macb *bp)
2067 struct macb_queue *queue = &bp->queues[0];
2070 size = bp->rx_ring_size * bp->rx_buffer_size;
2071 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2072 &queue->rx_buffers_dma, GFP_KERNEL);
2073 if (!queue->rx_buffers)
2077 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2078 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2082 static int macb_alloc_consistent(struct macb *bp)
2084 struct macb_queue *queue;
2088 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2089 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2090 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2091 &queue->tx_ring_dma,
2093 if (!queue->tx_ring)
2096 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2097 q, size, (unsigned long)queue->tx_ring_dma,
2100 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2101 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2105 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2106 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2107 &queue->rx_ring_dma, GFP_KERNEL);
2108 if (!queue->rx_ring)
2111 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2112 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2114 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2120 macb_free_consistent(bp);
2124 static void gem_init_rings(struct macb *bp)
2126 struct macb_queue *queue;
2127 struct macb_dma_desc *desc = NULL;
2131 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2132 for (i = 0; i < bp->tx_ring_size; i++) {
2133 desc = macb_tx_desc(queue, i);
2134 macb_set_addr(bp, desc, 0);
2135 desc->ctrl = MACB_BIT(TX_USED);
2137 desc->ctrl |= MACB_BIT(TX_WRAP);
2142 queue->rx_prepared_head = 0;
2144 gem_rx_refill(queue);
2149 static void macb_init_rings(struct macb *bp)
2152 struct macb_dma_desc *desc = NULL;
2154 macb_init_rx_ring(&bp->queues[0]);
2156 for (i = 0; i < bp->tx_ring_size; i++) {
2157 desc = macb_tx_desc(&bp->queues[0], i);
2158 macb_set_addr(bp, desc, 0);
2159 desc->ctrl = MACB_BIT(TX_USED);
2161 bp->queues[0].tx_head = 0;
2162 bp->queues[0].tx_tail = 0;
2163 desc->ctrl |= MACB_BIT(TX_WRAP);
2166 static void macb_reset_hw(struct macb *bp)
2168 struct macb_queue *queue;
2170 u32 ctrl = macb_readl(bp, NCR);
2172 /* Disable RX and TX (XXX: Should we halt the transmission
2175 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2177 /* Clear the stats registers (XXX: Update stats first?) */
2178 ctrl |= MACB_BIT(CLRSTAT);
2180 macb_writel(bp, NCR, ctrl);
2182 /* Clear all status flags */
2183 macb_writel(bp, TSR, -1);
2184 macb_writel(bp, RSR, -1);
2186 /* Disable all interrupts */
2187 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2188 queue_writel(queue, IDR, -1);
2189 queue_readl(queue, ISR);
2190 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2191 queue_writel(queue, ISR, -1);
2195 static u32 gem_mdc_clk_div(struct macb *bp)
2198 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2200 if (pclk_hz <= 20000000)
2201 config = GEM_BF(CLK, GEM_CLK_DIV8);
2202 else if (pclk_hz <= 40000000)
2203 config = GEM_BF(CLK, GEM_CLK_DIV16);
2204 else if (pclk_hz <= 80000000)
2205 config = GEM_BF(CLK, GEM_CLK_DIV32);
2206 else if (pclk_hz <= 120000000)
2207 config = GEM_BF(CLK, GEM_CLK_DIV48);
2208 else if (pclk_hz <= 160000000)
2209 config = GEM_BF(CLK, GEM_CLK_DIV64);
2211 config = GEM_BF(CLK, GEM_CLK_DIV96);
2216 static u32 macb_mdc_clk_div(struct macb *bp)
2219 unsigned long pclk_hz;
2221 if (macb_is_gem(bp))
2222 return gem_mdc_clk_div(bp);
2224 pclk_hz = clk_get_rate(bp->pclk);
2225 if (pclk_hz <= 20000000)
2226 config = MACB_BF(CLK, MACB_CLK_DIV8);
2227 else if (pclk_hz <= 40000000)
2228 config = MACB_BF(CLK, MACB_CLK_DIV16);
2229 else if (pclk_hz <= 80000000)
2230 config = MACB_BF(CLK, MACB_CLK_DIV32);
2232 config = MACB_BF(CLK, MACB_CLK_DIV64);
2237 /* Get the DMA bus width field of the network configuration register that we
2238 * should program. We find the width from decoding the design configuration
2239 * register to find the maximum supported data bus width.
2241 static u32 macb_dbw(struct macb *bp)
2243 if (!macb_is_gem(bp))
2246 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2248 return GEM_BF(DBW, GEM_DBW128);
2250 return GEM_BF(DBW, GEM_DBW64);
2253 return GEM_BF(DBW, GEM_DBW32);
2257 /* Configure the receive DMA engine
2258 * - use the correct receive buffer size
2259 * - set best burst length for DMA operations
2260 * (if not supported by FIFO, it will fallback to default)
2261 * - set both rx/tx packet buffers to full memory size
2262 * These are configurable parameters for GEM.
2264 static void macb_configure_dma(struct macb *bp)
2266 struct macb_queue *queue;
2271 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2272 if (macb_is_gem(bp)) {
2273 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2274 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2276 queue_writel(queue, RBQS, buffer_size);
2278 dmacfg |= GEM_BF(RXBS, buffer_size);
2280 if (bp->dma_burst_length)
2281 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2282 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2283 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2286 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2288 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2290 if (bp->dev->features & NETIF_F_HW_CSUM)
2291 dmacfg |= GEM_BIT(TXCOEN);
2293 dmacfg &= ~GEM_BIT(TXCOEN);
2295 dmacfg &= ~GEM_BIT(ADDR64);
2296 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2297 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2298 dmacfg |= GEM_BIT(ADDR64);
2300 #ifdef CONFIG_MACB_USE_HWSTAMP
2301 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2302 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2304 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2306 gem_writel(bp, DMACFG, dmacfg);
2310 static void macb_init_hw(struct macb *bp)
2315 macb_set_hwaddr(bp);
2317 config = macb_mdc_clk_div(bp);
2318 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2319 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2320 if (bp->caps & MACB_CAPS_JUMBO)
2321 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2323 config |= MACB_BIT(BIG); /* Receive oversized frames */
2324 if (bp->dev->flags & IFF_PROMISC)
2325 config |= MACB_BIT(CAF); /* Copy All Frames */
2326 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2327 config |= GEM_BIT(RXCOEN);
2328 if (!(bp->dev->flags & IFF_BROADCAST))
2329 config |= MACB_BIT(NBC); /* No BroadCast */
2330 config |= macb_dbw(bp);
2331 macb_writel(bp, NCFGR, config);
2332 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2333 gem_writel(bp, JML, bp->jumbo_max_len);
2334 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2335 if (bp->caps & MACB_CAPS_JUMBO)
2336 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2338 macb_configure_dma(bp);
2341 /* The hash address register is 64 bits long and takes up two
2342 * locations in the memory map. The least significant bits are stored
2343 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2345 * The unicast hash enable and the multicast hash enable bits in the
2346 * network configuration register enable the reception of hash matched
2347 * frames. The destination address is reduced to a 6 bit index into
2348 * the 64 bit hash register using the following hash function. The
2349 * hash function is an exclusive or of every sixth bit of the
2350 * destination address.
2352 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2353 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2354 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2355 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2356 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2357 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2359 * da[0] represents the least significant bit of the first byte
2360 * received, that is, the multicast/unicast indicator, and da[47]
2361 * represents the most significant bit of the last byte received. If
2362 * the hash index, hi[n], points to a bit that is set in the hash
2363 * register then the frame will be matched according to whether the
2364 * frame is multicast or unicast. A multicast match will be signalled
2365 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2366 * index points to a bit set in the hash register. A unicast match
2367 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2368 * and the hash index points to a bit set in the hash register. To
2369 * receive all multicast frames, the hash register should be set with
2370 * all ones and the multicast hash enable bit should be set in the
2371 * network configuration register.
2374 static inline int hash_bit_value(int bitnr, __u8 *addr)
2376 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2381 /* Return the hash index value for the specified address. */
2382 static int hash_get_index(__u8 *addr)
2387 for (j = 0; j < 6; j++) {
2388 for (i = 0, bitval = 0; i < 8; i++)
2389 bitval ^= hash_bit_value(i * 6 + j, addr);
2391 hash_index |= (bitval << j);
2397 /* Add multicast addresses to the internal multicast-hash table. */
2398 static void macb_sethashtable(struct net_device *dev)
2400 struct netdev_hw_addr *ha;
2401 unsigned long mc_filter[2];
2403 struct macb *bp = netdev_priv(dev);
2408 netdev_for_each_mc_addr(ha, dev) {
2409 bitnr = hash_get_index(ha->addr);
2410 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2413 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2414 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2417 /* Enable/Disable promiscuous and multicast modes. */
2418 static void macb_set_rx_mode(struct net_device *dev)
2421 struct macb *bp = netdev_priv(dev);
2423 cfg = macb_readl(bp, NCFGR);
2425 if (dev->flags & IFF_PROMISC) {
2426 /* Enable promiscuous mode */
2427 cfg |= MACB_BIT(CAF);
2429 /* Disable RX checksum offload */
2430 if (macb_is_gem(bp))
2431 cfg &= ~GEM_BIT(RXCOEN);
2433 /* Disable promiscuous mode */
2434 cfg &= ~MACB_BIT(CAF);
2436 /* Enable RX checksum offload only if requested */
2437 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2438 cfg |= GEM_BIT(RXCOEN);
2441 if (dev->flags & IFF_ALLMULTI) {
2442 /* Enable all multicast mode */
2443 macb_or_gem_writel(bp, HRB, -1);
2444 macb_or_gem_writel(bp, HRT, -1);
2445 cfg |= MACB_BIT(NCFGR_MTI);
2446 } else if (!netdev_mc_empty(dev)) {
2447 /* Enable specific multicasts */
2448 macb_sethashtable(dev);
2449 cfg |= MACB_BIT(NCFGR_MTI);
2450 } else if (dev->flags & (~IFF_ALLMULTI)) {
2451 /* Disable all multicast mode */
2452 macb_or_gem_writel(bp, HRB, 0);
2453 macb_or_gem_writel(bp, HRT, 0);
2454 cfg &= ~MACB_BIT(NCFGR_MTI);
2457 macb_writel(bp, NCFGR, cfg);
2460 static int macb_open(struct net_device *dev)
2462 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2463 struct macb *bp = netdev_priv(dev);
2464 struct macb_queue *queue;
2468 netdev_dbg(bp->dev, "open\n");
2470 err = pm_runtime_get_sync(&bp->pdev->dev);
2474 /* RX buffers initialization */
2475 macb_init_rx_buffer_size(bp, bufsz);
2477 err = macb_alloc_consistent(bp);
2479 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2484 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2485 napi_enable(&queue->napi);
2489 err = macb_phylink_connect(bp);
2493 netif_tx_start_all_queues(dev);
2496 bp->ptp_info->ptp_init(dev);
2500 pm_runtime_put_sync(&bp->pdev->dev);
2506 static int macb_close(struct net_device *dev)
2508 struct macb *bp = netdev_priv(dev);
2509 struct macb_queue *queue;
2510 unsigned long flags;
2513 netif_tx_stop_all_queues(dev);
2515 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2516 napi_disable(&queue->napi);
2518 phylink_stop(bp->phylink);
2519 phylink_disconnect_phy(bp->phylink);
2521 spin_lock_irqsave(&bp->lock, flags);
2523 netif_carrier_off(dev);
2524 spin_unlock_irqrestore(&bp->lock, flags);
2526 macb_free_consistent(bp);
2529 bp->ptp_info->ptp_remove(dev);
2531 pm_runtime_put(&bp->pdev->dev);
2536 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2538 if (netif_running(dev))
2546 static void gem_update_stats(struct macb *bp)
2548 struct macb_queue *queue;
2549 unsigned int i, q, idx;
2550 unsigned long *stat;
2552 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2554 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2555 u32 offset = gem_statistics[i].offset;
2556 u64 val = bp->macb_reg_readl(bp, offset);
2558 bp->ethtool_stats[i] += val;
2561 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2562 /* Add GEM_OCTTXH, GEM_OCTRXH */
2563 val = bp->macb_reg_readl(bp, offset + 4);
2564 bp->ethtool_stats[i] += ((u64)val) << 32;
2569 idx = GEM_STATS_LEN;
2570 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2571 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2572 bp->ethtool_stats[idx++] = *stat;
2575 static struct net_device_stats *gem_get_stats(struct macb *bp)
2577 struct gem_stats *hwstat = &bp->hw_stats.gem;
2578 struct net_device_stats *nstat = &bp->dev->stats;
2580 gem_update_stats(bp);
2582 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2583 hwstat->rx_alignment_errors +
2584 hwstat->rx_resource_errors +
2585 hwstat->rx_overruns +
2586 hwstat->rx_oversize_frames +
2587 hwstat->rx_jabbers +
2588 hwstat->rx_undersized_frames +
2589 hwstat->rx_length_field_frame_errors);
2590 nstat->tx_errors = (hwstat->tx_late_collisions +
2591 hwstat->tx_excessive_collisions +
2592 hwstat->tx_underrun +
2593 hwstat->tx_carrier_sense_errors);
2594 nstat->multicast = hwstat->rx_multicast_frames;
2595 nstat->collisions = (hwstat->tx_single_collision_frames +
2596 hwstat->tx_multiple_collision_frames +
2597 hwstat->tx_excessive_collisions);
2598 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2599 hwstat->rx_jabbers +
2600 hwstat->rx_undersized_frames +
2601 hwstat->rx_length_field_frame_errors);
2602 nstat->rx_over_errors = hwstat->rx_resource_errors;
2603 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2604 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2605 nstat->rx_fifo_errors = hwstat->rx_overruns;
2606 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2607 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2608 nstat->tx_fifo_errors = hwstat->tx_underrun;
2613 static void gem_get_ethtool_stats(struct net_device *dev,
2614 struct ethtool_stats *stats, u64 *data)
2618 bp = netdev_priv(dev);
2619 gem_update_stats(bp);
2620 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2621 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2624 static int gem_get_sset_count(struct net_device *dev, int sset)
2626 struct macb *bp = netdev_priv(dev);
2630 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2636 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2638 char stat_string[ETH_GSTRING_LEN];
2639 struct macb *bp = netdev_priv(dev);
2640 struct macb_queue *queue;
2646 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2647 memcpy(p, gem_statistics[i].stat_string,
2650 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2651 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2652 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2653 q, queue_statistics[i].stat_string);
2654 memcpy(p, stat_string, ETH_GSTRING_LEN);
2661 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2663 struct macb *bp = netdev_priv(dev);
2664 struct net_device_stats *nstat = &bp->dev->stats;
2665 struct macb_stats *hwstat = &bp->hw_stats.macb;
2667 if (macb_is_gem(bp))
2668 return gem_get_stats(bp);
2670 /* read stats from hardware */
2671 macb_update_stats(bp);
2673 /* Convert HW stats into netdevice stats */
2674 nstat->rx_errors = (hwstat->rx_fcs_errors +
2675 hwstat->rx_align_errors +
2676 hwstat->rx_resource_errors +
2677 hwstat->rx_overruns +
2678 hwstat->rx_oversize_pkts +
2679 hwstat->rx_jabbers +
2680 hwstat->rx_undersize_pkts +
2681 hwstat->rx_length_mismatch);
2682 nstat->tx_errors = (hwstat->tx_late_cols +
2683 hwstat->tx_excessive_cols +
2684 hwstat->tx_underruns +
2685 hwstat->tx_carrier_errors +
2686 hwstat->sqe_test_errors);
2687 nstat->collisions = (hwstat->tx_single_cols +
2688 hwstat->tx_multiple_cols +
2689 hwstat->tx_excessive_cols);
2690 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2691 hwstat->rx_jabbers +
2692 hwstat->rx_undersize_pkts +
2693 hwstat->rx_length_mismatch);
2694 nstat->rx_over_errors = hwstat->rx_resource_errors +
2695 hwstat->rx_overruns;
2696 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2697 nstat->rx_frame_errors = hwstat->rx_align_errors;
2698 nstat->rx_fifo_errors = hwstat->rx_overruns;
2699 /* XXX: What does "missed" mean? */
2700 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2701 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2702 nstat->tx_fifo_errors = hwstat->tx_underruns;
2703 /* Don't know about heartbeat or window errors... */
2708 static int macb_get_regs_len(struct net_device *netdev)
2710 return MACB_GREGS_NBR * sizeof(u32);
2713 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2716 struct macb *bp = netdev_priv(dev);
2717 unsigned int tail, head;
2720 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2721 | MACB_GREGS_VERSION;
2723 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2724 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2726 regs_buff[0] = macb_readl(bp, NCR);
2727 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2728 regs_buff[2] = macb_readl(bp, NSR);
2729 regs_buff[3] = macb_readl(bp, TSR);
2730 regs_buff[4] = macb_readl(bp, RBQP);
2731 regs_buff[5] = macb_readl(bp, TBQP);
2732 regs_buff[6] = macb_readl(bp, RSR);
2733 regs_buff[7] = macb_readl(bp, IMR);
2735 regs_buff[8] = tail;
2736 regs_buff[9] = head;
2737 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2738 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2740 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2741 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2742 if (macb_is_gem(bp))
2743 regs_buff[13] = gem_readl(bp, DMACFG);
2746 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2748 struct macb *bp = netdev_priv(netdev);
2753 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET)
2754 phylink_ethtool_get_wol(bp->phylink, wol);
2757 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2759 struct macb *bp = netdev_priv(netdev);
2762 ret = phylink_ethtool_set_wol(bp->phylink, wol);
2766 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2767 (wol->wolopts & ~WAKE_MAGIC))
2770 if (wol->wolopts & WAKE_MAGIC)
2771 bp->wol |= MACB_WOL_ENABLED;
2773 bp->wol &= ~MACB_WOL_ENABLED;
2775 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2780 static int macb_get_link_ksettings(struct net_device *netdev,
2781 struct ethtool_link_ksettings *kset)
2783 struct macb *bp = netdev_priv(netdev);
2785 return phylink_ethtool_ksettings_get(bp->phylink, kset);
2788 static int macb_set_link_ksettings(struct net_device *netdev,
2789 const struct ethtool_link_ksettings *kset)
2791 struct macb *bp = netdev_priv(netdev);
2793 return phylink_ethtool_ksettings_set(bp->phylink, kset);
2796 static void macb_get_ringparam(struct net_device *netdev,
2797 struct ethtool_ringparam *ring)
2799 struct macb *bp = netdev_priv(netdev);
2801 ring->rx_max_pending = MAX_RX_RING_SIZE;
2802 ring->tx_max_pending = MAX_TX_RING_SIZE;
2804 ring->rx_pending = bp->rx_ring_size;
2805 ring->tx_pending = bp->tx_ring_size;
2808 static int macb_set_ringparam(struct net_device *netdev,
2809 struct ethtool_ringparam *ring)
2811 struct macb *bp = netdev_priv(netdev);
2812 u32 new_rx_size, new_tx_size;
2813 unsigned int reset = 0;
2815 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2818 new_rx_size = clamp_t(u32, ring->rx_pending,
2819 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2820 new_rx_size = roundup_pow_of_two(new_rx_size);
2822 new_tx_size = clamp_t(u32, ring->tx_pending,
2823 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2824 new_tx_size = roundup_pow_of_two(new_tx_size);
2826 if ((new_tx_size == bp->tx_ring_size) &&
2827 (new_rx_size == bp->rx_ring_size)) {
2832 if (netif_running(bp->dev)) {
2834 macb_close(bp->dev);
2837 bp->rx_ring_size = new_rx_size;
2838 bp->tx_ring_size = new_tx_size;
2846 #ifdef CONFIG_MACB_USE_HWSTAMP
2847 static unsigned int gem_get_tsu_rate(struct macb *bp)
2849 struct clk *tsu_clk;
2850 unsigned int tsu_rate;
2852 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
2853 if (!IS_ERR(tsu_clk))
2854 tsu_rate = clk_get_rate(tsu_clk);
2855 /* try pclk instead */
2856 else if (!IS_ERR(bp->pclk)) {
2858 tsu_rate = clk_get_rate(tsu_clk);
2864 static s32 gem_get_ptp_max_adj(void)
2869 static int gem_get_ts_info(struct net_device *dev,
2870 struct ethtool_ts_info *info)
2872 struct macb *bp = netdev_priv(dev);
2874 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
2875 ethtool_op_get_ts_info(dev, info);
2879 info->so_timestamping =
2880 SOF_TIMESTAMPING_TX_SOFTWARE |
2881 SOF_TIMESTAMPING_RX_SOFTWARE |
2882 SOF_TIMESTAMPING_SOFTWARE |
2883 SOF_TIMESTAMPING_TX_HARDWARE |
2884 SOF_TIMESTAMPING_RX_HARDWARE |
2885 SOF_TIMESTAMPING_RAW_HARDWARE;
2887 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
2888 (1 << HWTSTAMP_TX_OFF) |
2889 (1 << HWTSTAMP_TX_ON);
2891 (1 << HWTSTAMP_FILTER_NONE) |
2892 (1 << HWTSTAMP_FILTER_ALL);
2894 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
2899 static struct macb_ptp_info gem_ptp_info = {
2900 .ptp_init = gem_ptp_init,
2901 .ptp_remove = gem_ptp_remove,
2902 .get_ptp_max_adj = gem_get_ptp_max_adj,
2903 .get_tsu_rate = gem_get_tsu_rate,
2904 .get_ts_info = gem_get_ts_info,
2905 .get_hwtst = gem_get_hwtst,
2906 .set_hwtst = gem_set_hwtst,
2910 static int macb_get_ts_info(struct net_device *netdev,
2911 struct ethtool_ts_info *info)
2913 struct macb *bp = netdev_priv(netdev);
2916 return bp->ptp_info->get_ts_info(netdev, info);
2918 return ethtool_op_get_ts_info(netdev, info);
2921 static void gem_enable_flow_filters(struct macb *bp, bool enable)
2923 struct net_device *netdev = bp->dev;
2924 struct ethtool_rx_fs_item *item;
2928 if (!(netdev->features & NETIF_F_NTUPLE))
2931 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
2933 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2934 struct ethtool_rx_flow_spec *fs = &item->fs;
2935 struct ethtool_tcpip4_spec *tp4sp_m;
2937 if (fs->location >= num_t2_scr)
2940 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
2942 /* enable/disable screener regs for the flow entry */
2943 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
2945 /* only enable fields with no masking */
2946 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2948 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
2949 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
2951 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
2953 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
2954 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
2956 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
2958 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
2959 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
2961 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
2963 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
2967 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
2969 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
2970 uint16_t index = fs->location;
2976 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
2977 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2979 /* ignore field if any masking set */
2980 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
2981 /* 1st compare reg - IP source address */
2984 w0 = tp4sp_v->ip4src;
2985 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2986 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
2987 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
2988 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
2989 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
2993 /* ignore field if any masking set */
2994 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
2995 /* 2nd compare reg - IP destination address */
2998 w0 = tp4sp_v->ip4dst;
2999 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3000 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3001 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3002 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3003 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3007 /* ignore both port fields if masking set in both */
3008 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3009 /* 3rd compare reg - source port, destination port */
3012 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3013 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3014 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3015 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3016 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3017 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3019 /* only one port definition */
3020 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3021 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3022 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3023 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3024 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3025 } else { /* dst port */
3026 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3027 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3030 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3031 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3036 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3037 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3039 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3041 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3043 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3044 gem_writel_n(bp, SCRT2, index, t2_scr);
3047 static int gem_add_flow_filter(struct net_device *netdev,
3048 struct ethtool_rxnfc *cmd)
3050 struct macb *bp = netdev_priv(netdev);
3051 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3052 struct ethtool_rx_fs_item *item, *newfs;
3053 unsigned long flags;
3057 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3060 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3063 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3064 fs->flow_type, (int)fs->ring_cookie, fs->location,
3065 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3066 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3067 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
3069 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3071 /* find correct place to add in list */
3072 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3073 if (item->fs.location > newfs->fs.location) {
3074 list_add_tail(&newfs->list, &item->list);
3077 } else if (item->fs.location == fs->location) {
3078 netdev_err(netdev, "Rule not added: location %d not free!\n",
3085 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3087 gem_prog_cmp_regs(bp, fs);
3088 bp->rx_fs_list.count++;
3089 /* enable filtering if NTUPLE on */
3090 gem_enable_flow_filters(bp, 1);
3092 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3096 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3101 static int gem_del_flow_filter(struct net_device *netdev,
3102 struct ethtool_rxnfc *cmd)
3104 struct macb *bp = netdev_priv(netdev);
3105 struct ethtool_rx_fs_item *item;
3106 struct ethtool_rx_flow_spec *fs;
3107 unsigned long flags;
3109 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3111 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3112 if (item->fs.location == cmd->fs.location) {
3113 /* disable screener regs for the flow entry */
3116 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3117 fs->flow_type, (int)fs->ring_cookie, fs->location,
3118 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3119 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3120 htons(fs->h_u.tcp_ip4_spec.psrc),
3121 htons(fs->h_u.tcp_ip4_spec.pdst));
3123 gem_writel_n(bp, SCRT2, fs->location, 0);
3125 list_del(&item->list);
3126 bp->rx_fs_list.count--;
3127 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3133 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3137 static int gem_get_flow_entry(struct net_device *netdev,
3138 struct ethtool_rxnfc *cmd)
3140 struct macb *bp = netdev_priv(netdev);
3141 struct ethtool_rx_fs_item *item;
3143 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3144 if (item->fs.location == cmd->fs.location) {
3145 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3152 static int gem_get_all_flow_entries(struct net_device *netdev,
3153 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3155 struct macb *bp = netdev_priv(netdev);
3156 struct ethtool_rx_fs_item *item;
3159 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3160 if (cnt == cmd->rule_cnt)
3162 rule_locs[cnt] = item->fs.location;
3165 cmd->data = bp->max_tuples;
3166 cmd->rule_cnt = cnt;
3171 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3174 struct macb *bp = netdev_priv(netdev);
3178 case ETHTOOL_GRXRINGS:
3179 cmd->data = bp->num_queues;
3181 case ETHTOOL_GRXCLSRLCNT:
3182 cmd->rule_cnt = bp->rx_fs_list.count;
3184 case ETHTOOL_GRXCLSRULE:
3185 ret = gem_get_flow_entry(netdev, cmd);
3187 case ETHTOOL_GRXCLSRLALL:
3188 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3192 "Command parameter %d is not supported\n", cmd->cmd);
3199 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3201 struct macb *bp = netdev_priv(netdev);
3205 case ETHTOOL_SRXCLSRLINS:
3206 if ((cmd->fs.location >= bp->max_tuples)
3207 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3211 ret = gem_add_flow_filter(netdev, cmd);
3213 case ETHTOOL_SRXCLSRLDEL:
3214 ret = gem_del_flow_filter(netdev, cmd);
3218 "Command parameter %d is not supported\n", cmd->cmd);
3225 static const struct ethtool_ops macb_ethtool_ops = {
3226 .get_regs_len = macb_get_regs_len,
3227 .get_regs = macb_get_regs,
3228 .get_link = ethtool_op_get_link,
3229 .get_ts_info = ethtool_op_get_ts_info,
3230 .get_wol = macb_get_wol,
3231 .set_wol = macb_set_wol,
3232 .get_link_ksettings = macb_get_link_ksettings,
3233 .set_link_ksettings = macb_set_link_ksettings,
3234 .get_ringparam = macb_get_ringparam,
3235 .set_ringparam = macb_set_ringparam,
3238 static const struct ethtool_ops gem_ethtool_ops = {
3239 .get_regs_len = macb_get_regs_len,
3240 .get_regs = macb_get_regs,
3241 .get_link = ethtool_op_get_link,
3242 .get_ts_info = macb_get_ts_info,
3243 .get_ethtool_stats = gem_get_ethtool_stats,
3244 .get_strings = gem_get_ethtool_strings,
3245 .get_sset_count = gem_get_sset_count,
3246 .get_link_ksettings = macb_get_link_ksettings,
3247 .set_link_ksettings = macb_set_link_ksettings,
3248 .get_ringparam = macb_get_ringparam,
3249 .set_ringparam = macb_set_ringparam,
3250 .get_rxnfc = gem_get_rxnfc,
3251 .set_rxnfc = gem_set_rxnfc,
3254 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3256 struct macb *bp = netdev_priv(dev);
3258 if (!netif_running(dev))
3264 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3266 return bp->ptp_info->get_hwtst(dev, rq);
3270 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3273 static inline void macb_set_txcsum_feature(struct macb *bp,
3274 netdev_features_t features)
3278 if (!macb_is_gem(bp))
3281 val = gem_readl(bp, DMACFG);
3282 if (features & NETIF_F_HW_CSUM)
3283 val |= GEM_BIT(TXCOEN);
3285 val &= ~GEM_BIT(TXCOEN);
3287 gem_writel(bp, DMACFG, val);
3290 static inline void macb_set_rxcsum_feature(struct macb *bp,
3291 netdev_features_t features)
3293 struct net_device *netdev = bp->dev;
3296 if (!macb_is_gem(bp))
3299 val = gem_readl(bp, NCFGR);
3300 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3301 val |= GEM_BIT(RXCOEN);
3303 val &= ~GEM_BIT(RXCOEN);
3305 gem_writel(bp, NCFGR, val);
3308 static inline void macb_set_rxflow_feature(struct macb *bp,
3309 netdev_features_t features)
3311 if (!macb_is_gem(bp))
3314 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3317 static int macb_set_features(struct net_device *netdev,
3318 netdev_features_t features)
3320 struct macb *bp = netdev_priv(netdev);
3321 netdev_features_t changed = features ^ netdev->features;
3323 /* TX checksum offload */
3324 if (changed & NETIF_F_HW_CSUM)
3325 macb_set_txcsum_feature(bp, features);
3327 /* RX checksum offload */
3328 if (changed & NETIF_F_RXCSUM)
3329 macb_set_rxcsum_feature(bp, features);
3331 /* RX Flow Filters */
3332 if (changed & NETIF_F_NTUPLE)
3333 macb_set_rxflow_feature(bp, features);
3338 static void macb_restore_features(struct macb *bp)
3340 struct net_device *netdev = bp->dev;
3341 netdev_features_t features = netdev->features;
3343 /* TX checksum offload */
3344 macb_set_txcsum_feature(bp, features);
3346 /* RX checksum offload */
3347 macb_set_rxcsum_feature(bp, features);
3349 /* RX Flow Filters */
3350 macb_set_rxflow_feature(bp, features);
3353 static const struct net_device_ops macb_netdev_ops = {
3354 .ndo_open = macb_open,
3355 .ndo_stop = macb_close,
3356 .ndo_start_xmit = macb_start_xmit,
3357 .ndo_set_rx_mode = macb_set_rx_mode,
3358 .ndo_get_stats = macb_get_stats,
3359 .ndo_do_ioctl = macb_ioctl,
3360 .ndo_validate_addr = eth_validate_addr,
3361 .ndo_change_mtu = macb_change_mtu,
3362 .ndo_set_mac_address = eth_mac_addr,
3363 #ifdef CONFIG_NET_POLL_CONTROLLER
3364 .ndo_poll_controller = macb_poll_controller,
3366 .ndo_set_features = macb_set_features,
3367 .ndo_features_check = macb_features_check,
3370 /* Configure peripheral capabilities according to device tree
3371 * and integration options used
3373 static void macb_configure_caps(struct macb *bp,
3374 const struct macb_config *dt_conf)
3379 bp->caps = dt_conf->caps;
3381 if (hw_is_gem(bp->regs, bp->native_io)) {
3382 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3384 dcfg = gem_readl(bp, DCFG1);
3385 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3386 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3387 dcfg = gem_readl(bp, DCFG2);
3388 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3389 bp->caps |= MACB_CAPS_FIFO_MODE;
3390 #ifdef CONFIG_MACB_USE_HWSTAMP
3391 if (gem_has_ptp(bp)) {
3392 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3393 dev_err(&bp->pdev->dev,
3394 "GEM doesn't support hardware ptp.\n");
3396 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3397 bp->ptp_info = &gem_ptp_info;
3403 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3406 static void macb_probe_queues(void __iomem *mem,
3408 unsigned int *queue_mask,
3409 unsigned int *num_queues)
3416 /* is it macb or gem ?
3418 * We need to read directly from the hardware here because
3419 * we are early in the probe process and don't have the
3420 * MACB_CAPS_MACB_IS_GEM flag positioned
3422 if (!hw_is_gem(mem, native_io))
3425 /* bit 0 is never set but queue 0 always exists */
3426 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
3430 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
3431 if (*queue_mask & (1 << hw_q))
3435 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3436 struct clk **hclk, struct clk **tx_clk,
3437 struct clk **rx_clk, struct clk **tsu_clk)
3439 struct macb_platform_data *pdata;
3442 pdata = dev_get_platdata(&pdev->dev);
3444 *pclk = pdata->pclk;
3445 *hclk = pdata->hclk;
3447 *pclk = devm_clk_get(&pdev->dev, "pclk");
3448 *hclk = devm_clk_get(&pdev->dev, "hclk");
3451 if (IS_ERR_OR_NULL(*pclk)) {
3452 err = PTR_ERR(*pclk);
3456 dev_err(&pdev->dev, "failed to get macb_clk (%d)\n", err);
3460 if (IS_ERR_OR_NULL(*hclk)) {
3461 err = PTR_ERR(*hclk);
3465 dev_err(&pdev->dev, "failed to get hclk (%d)\n", err);
3469 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
3470 if (IS_ERR(*tx_clk))
3471 return PTR_ERR(*tx_clk);
3473 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
3474 if (IS_ERR(*rx_clk))
3475 return PTR_ERR(*rx_clk);
3477 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
3478 if (IS_ERR(*tsu_clk))
3479 return PTR_ERR(*tsu_clk);
3481 err = clk_prepare_enable(*pclk);
3483 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3487 err = clk_prepare_enable(*hclk);
3489 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3490 goto err_disable_pclk;
3493 err = clk_prepare_enable(*tx_clk);
3495 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3496 goto err_disable_hclk;
3499 err = clk_prepare_enable(*rx_clk);
3501 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3502 goto err_disable_txclk;
3505 err = clk_prepare_enable(*tsu_clk);
3507 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
3508 goto err_disable_rxclk;
3514 clk_disable_unprepare(*rx_clk);
3517 clk_disable_unprepare(*tx_clk);
3520 clk_disable_unprepare(*hclk);
3523 clk_disable_unprepare(*pclk);
3528 static int macb_init(struct platform_device *pdev)
3530 struct net_device *dev = platform_get_drvdata(pdev);
3531 unsigned int hw_q, q;
3532 struct macb *bp = netdev_priv(dev);
3533 struct macb_queue *queue;
3537 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3538 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3540 /* set the queue register mapping once for all: queue0 has a special
3541 * register mapping but we don't want to test the queue index then
3542 * compute the corresponding register offset at run time.
3544 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3545 if (!(bp->queue_mask & (1 << hw_q)))
3548 queue = &bp->queues[q];
3550 netif_napi_add(dev, &queue->napi, macb_poll, NAPI_POLL_WEIGHT);
3552 queue->ISR = GEM_ISR(hw_q - 1);
3553 queue->IER = GEM_IER(hw_q - 1);
3554 queue->IDR = GEM_IDR(hw_q - 1);
3555 queue->IMR = GEM_IMR(hw_q - 1);
3556 queue->TBQP = GEM_TBQP(hw_q - 1);
3557 queue->RBQP = GEM_RBQP(hw_q - 1);
3558 queue->RBQS = GEM_RBQS(hw_q - 1);
3559 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3560 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3561 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3562 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3566 /* queue0 uses legacy registers */
3567 queue->ISR = MACB_ISR;
3568 queue->IER = MACB_IER;
3569 queue->IDR = MACB_IDR;
3570 queue->IMR = MACB_IMR;
3571 queue->TBQP = MACB_TBQP;
3572 queue->RBQP = MACB_RBQP;
3573 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3574 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3575 queue->TBQPH = MACB_TBQPH;
3576 queue->RBQPH = MACB_RBQPH;
3581 /* get irq: here we use the linux queue index, not the hardware
3582 * queue index. the queue irq definitions in the device tree
3583 * must remove the optional gaps that could exist in the
3584 * hardware queue mask.
3586 queue->irq = platform_get_irq(pdev, q);
3587 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3588 IRQF_SHARED, dev->name, queue);
3591 "Unable to request IRQ %d (error %d)\n",
3596 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3600 dev->netdev_ops = &macb_netdev_ops;
3602 /* setup appropriated routines according to adapter type */
3603 if (macb_is_gem(bp)) {
3604 bp->max_tx_length = GEM_MAX_TX_LEN;
3605 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3606 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3607 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3608 bp->macbgem_ops.mog_rx = gem_rx;
3609 dev->ethtool_ops = &gem_ethtool_ops;
3611 bp->max_tx_length = MACB_MAX_TX_LEN;
3612 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3613 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3614 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3615 bp->macbgem_ops.mog_rx = macb_rx;
3616 dev->ethtool_ops = &macb_ethtool_ops;
3620 dev->hw_features = NETIF_F_SG;
3622 /* Check LSO capability */
3623 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3624 dev->hw_features |= MACB_NETIF_LSO;
3626 /* Checksum offload is only available on gem with packet buffer */
3627 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3628 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3629 if (bp->caps & MACB_CAPS_SG_DISABLED)
3630 dev->hw_features &= ~NETIF_F_SG;
3631 dev->features = dev->hw_features;
3633 /* Check RX Flow Filters support.
3634 * Max Rx flows set by availability of screeners & compare regs:
3635 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3637 reg = gem_readl(bp, DCFG8);
3638 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3639 GEM_BFEXT(T2SCR, reg));
3640 if (bp->max_tuples > 0) {
3641 /* also needs one ethtype match to check IPv4 */
3642 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3643 /* program this reg now */
3645 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3646 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3647 /* Filtering is supported in hw but don't enable it in kernel now */
3648 dev->hw_features |= NETIF_F_NTUPLE;
3649 /* init Rx flow definitions */
3650 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3651 bp->rx_fs_list.count = 0;
3652 spin_lock_init(&bp->rx_fs_lock);
3657 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3659 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
3660 val = GEM_BIT(RGMII);
3661 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3662 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3663 val = MACB_BIT(RMII);
3664 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3665 val = MACB_BIT(MII);
3667 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3668 val |= MACB_BIT(CLKEN);
3670 macb_or_gem_writel(bp, USRIO, val);
3673 /* Set MII management clock divider */
3674 val = macb_mdc_clk_div(bp);
3675 val |= macb_dbw(bp);
3676 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3677 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3678 macb_writel(bp, NCFGR, val);
3683 #if defined(CONFIG_OF)
3684 /* 1518 rounded up */
3685 #define AT91ETHER_MAX_RBUFF_SZ 0x600
3686 /* max number of receive buffers */
3687 #define AT91ETHER_MAX_RX_DESCR 9
3689 static struct sifive_fu540_macb_mgmt *mgmt;
3691 /* Initialize and start the Receiver and Transmit subsystems */
3692 static int at91ether_start(struct net_device *dev)
3694 struct macb *lp = netdev_priv(dev);
3695 struct macb_queue *q = &lp->queues[0];
3696 struct macb_dma_desc *desc;
3701 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3702 (AT91ETHER_MAX_RX_DESCR *
3703 macb_dma_desc_get_size(lp)),
3704 &q->rx_ring_dma, GFP_KERNEL);
3708 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3709 AT91ETHER_MAX_RX_DESCR *
3710 AT91ETHER_MAX_RBUFF_SZ,
3711 &q->rx_buffers_dma, GFP_KERNEL);
3712 if (!q->rx_buffers) {
3713 dma_free_coherent(&lp->pdev->dev,
3714 AT91ETHER_MAX_RX_DESCR *
3715 macb_dma_desc_get_size(lp),
3716 q->rx_ring, q->rx_ring_dma);
3721 addr = q->rx_buffers_dma;
3722 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3723 desc = macb_rx_desc(q, i);
3724 macb_set_addr(lp, desc, addr);
3726 addr += AT91ETHER_MAX_RBUFF_SZ;
3729 /* Set the Wrap bit on the last descriptor */
3730 desc->addr |= MACB_BIT(RX_WRAP);
3732 /* Reset buffer index */
3735 /* Program address of descriptor list in Rx Buffer Queue register */
3736 macb_writel(lp, RBQP, q->rx_ring_dma);
3738 /* Enable Receive and Transmit */
3739 ctl = macb_readl(lp, NCR);
3740 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3745 /* Open the ethernet interface */
3746 static int at91ether_open(struct net_device *dev)
3748 struct macb *lp = netdev_priv(dev);
3752 /* Clear internal statistics */
3753 ctl = macb_readl(lp, NCR);
3754 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3756 macb_set_hwaddr(lp);
3758 ret = at91ether_start(dev);
3762 /* Enable MAC interrupts */
3763 macb_writel(lp, IER, MACB_BIT(RCOMP) |
3765 MACB_BIT(ISR_TUND) |
3768 MACB_BIT(ISR_ROVR) |
3771 ret = macb_phylink_connect(lp);
3775 netif_start_queue(dev);
3780 /* Close the interface */
3781 static int at91ether_close(struct net_device *dev)
3783 struct macb *lp = netdev_priv(dev);
3784 struct macb_queue *q = &lp->queues[0];
3787 /* Disable Receiver and Transmitter */
3788 ctl = macb_readl(lp, NCR);
3789 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3791 /* Disable MAC interrupts */
3792 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
3794 MACB_BIT(ISR_TUND) |
3797 MACB_BIT(ISR_ROVR) |
3800 netif_stop_queue(dev);
3802 phylink_stop(lp->phylink);
3803 phylink_disconnect_phy(lp->phylink);
3805 dma_free_coherent(&lp->pdev->dev,
3806 AT91ETHER_MAX_RX_DESCR *
3807 macb_dma_desc_get_size(lp),
3808 q->rx_ring, q->rx_ring_dma);
3811 dma_free_coherent(&lp->pdev->dev,
3812 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
3813 q->rx_buffers, q->rx_buffers_dma);
3814 q->rx_buffers = NULL;
3819 /* Transmit packet */
3820 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
3821 struct net_device *dev)
3823 struct macb *lp = netdev_priv(dev);
3825 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
3826 netif_stop_queue(dev);
3828 /* Store packet information (to free when Tx completed) */
3830 lp->skb_length = skb->len;
3831 lp->skb_physaddr = dma_map_single(&lp->pdev->dev, skb->data,
3832 skb->len, DMA_TO_DEVICE);
3833 if (dma_mapping_error(&lp->pdev->dev, lp->skb_physaddr)) {
3834 dev_kfree_skb_any(skb);
3835 dev->stats.tx_dropped++;
3836 netdev_err(dev, "%s: DMA mapping error\n", __func__);
3837 return NETDEV_TX_OK;
3840 /* Set address of the data in the Transmit Address register */
3841 macb_writel(lp, TAR, lp->skb_physaddr);
3842 /* Set length of the packet in the Transmit Control register */
3843 macb_writel(lp, TCR, skb->len);
3846 netdev_err(dev, "%s called, but device is busy!\n", __func__);
3847 return NETDEV_TX_BUSY;
3850 return NETDEV_TX_OK;
3853 /* Extract received frame from buffer descriptors and sent to upper layers.
3854 * (Called from interrupt context)
3856 static void at91ether_rx(struct net_device *dev)
3858 struct macb *lp = netdev_priv(dev);
3859 struct macb_queue *q = &lp->queues[0];
3860 struct macb_dma_desc *desc;
3861 unsigned char *p_recv;
3862 struct sk_buff *skb;
3863 unsigned int pktlen;
3865 desc = macb_rx_desc(q, q->rx_tail);
3866 while (desc->addr & MACB_BIT(RX_USED)) {
3867 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
3868 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
3869 skb = netdev_alloc_skb(dev, pktlen + 2);
3871 skb_reserve(skb, 2);
3872 skb_put_data(skb, p_recv, pktlen);
3874 skb->protocol = eth_type_trans(skb, dev);
3875 dev->stats.rx_packets++;
3876 dev->stats.rx_bytes += pktlen;
3879 dev->stats.rx_dropped++;
3882 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
3883 dev->stats.multicast++;
3885 /* reset ownership bit */
3886 desc->addr &= ~MACB_BIT(RX_USED);
3888 /* wrap after last buffer */
3889 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
3894 desc = macb_rx_desc(q, q->rx_tail);
3898 /* MAC interrupt handler */
3899 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
3901 struct net_device *dev = dev_id;
3902 struct macb *lp = netdev_priv(dev);
3905 /* MAC Interrupt Status register indicates what interrupts are pending.
3906 * It is automatically cleared once read.
3908 intstatus = macb_readl(lp, ISR);
3910 /* Receive complete */
3911 if (intstatus & MACB_BIT(RCOMP))
3914 /* Transmit complete */
3915 if (intstatus & MACB_BIT(TCOMP)) {
3916 /* The TCOM bit is set even if the transmission failed */
3917 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
3918 dev->stats.tx_errors++;
3921 dev_consume_skb_irq(lp->skb);
3923 dma_unmap_single(&lp->pdev->dev, lp->skb_physaddr,
3924 lp->skb_length, DMA_TO_DEVICE);
3925 dev->stats.tx_packets++;
3926 dev->stats.tx_bytes += lp->skb_length;
3928 netif_wake_queue(dev);
3931 /* Work-around for EMAC Errata section 41.3.1 */
3932 if (intstatus & MACB_BIT(RXUBR)) {
3933 ctl = macb_readl(lp, NCR);
3934 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
3936 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
3939 if (intstatus & MACB_BIT(ISR_ROVR))
3940 netdev_err(dev, "ROVR error\n");
3945 #ifdef CONFIG_NET_POLL_CONTROLLER
3946 static void at91ether_poll_controller(struct net_device *dev)
3948 unsigned long flags;
3950 local_irq_save(flags);
3951 at91ether_interrupt(dev->irq, dev);
3952 local_irq_restore(flags);
3956 static const struct net_device_ops at91ether_netdev_ops = {
3957 .ndo_open = at91ether_open,
3958 .ndo_stop = at91ether_close,
3959 .ndo_start_xmit = at91ether_start_xmit,
3960 .ndo_get_stats = macb_get_stats,
3961 .ndo_set_rx_mode = macb_set_rx_mode,
3962 .ndo_set_mac_address = eth_mac_addr,
3963 .ndo_do_ioctl = macb_ioctl,
3964 .ndo_validate_addr = eth_validate_addr,
3965 #ifdef CONFIG_NET_POLL_CONTROLLER
3966 .ndo_poll_controller = at91ether_poll_controller,
3970 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
3971 struct clk **hclk, struct clk **tx_clk,
3972 struct clk **rx_clk, struct clk **tsu_clk)
3981 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
3983 return PTR_ERR(*pclk);
3985 err = clk_prepare_enable(*pclk);
3987 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3994 static int at91ether_init(struct platform_device *pdev)
3996 struct net_device *dev = platform_get_drvdata(pdev);
3997 struct macb *bp = netdev_priv(dev);
4001 bp->queues[0].bp = bp;
4003 dev->netdev_ops = &at91ether_netdev_ops;
4004 dev->ethtool_ops = &macb_ethtool_ops;
4006 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4011 macb_writel(bp, NCR, 0);
4013 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
4014 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
4015 reg |= MACB_BIT(RM9200_RMII);
4017 macb_writel(bp, NCFGR, reg);
4022 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4023 unsigned long parent_rate)
4028 static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4029 unsigned long *parent_rate)
4031 if (WARN_ON(rate < 2500000))
4033 else if (rate == 2500000)
4035 else if (WARN_ON(rate < 13750000))
4037 else if (WARN_ON(rate < 25000000))
4039 else if (rate == 25000000)
4041 else if (WARN_ON(rate < 75000000))
4043 else if (WARN_ON(rate < 125000000))
4045 else if (rate == 125000000)
4048 WARN_ON(rate > 125000000);
4053 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4054 unsigned long parent_rate)
4056 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4057 if (rate != 125000000)
4058 iowrite32(1, mgmt->reg);
4060 iowrite32(0, mgmt->reg);
4066 static const struct clk_ops fu540_c000_ops = {
4067 .recalc_rate = fu540_macb_tx_recalc_rate,
4068 .round_rate = fu540_macb_tx_round_rate,
4069 .set_rate = fu540_macb_tx_set_rate,
4072 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4073 struct clk **hclk, struct clk **tx_clk,
4074 struct clk **rx_clk, struct clk **tsu_clk)
4076 struct clk_init_data init;
4079 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4083 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4087 init.name = "sifive-gemgxl-mgmt";
4088 init.ops = &fu540_c000_ops;
4090 init.num_parents = 0;
4093 mgmt->hw.init = &init;
4095 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4096 if (IS_ERR(*tx_clk))
4097 return PTR_ERR(*tx_clk);
4099 err = clk_prepare_enable(*tx_clk);
4101 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4103 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4108 static int fu540_c000_init(struct platform_device *pdev)
4110 struct resource *res;
4112 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
4116 mgmt->reg = ioremap(res->start, resource_size(res));
4120 return macb_init(pdev);
4123 static const struct macb_config fu540_c000_config = {
4124 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4125 MACB_CAPS_GEM_HAS_PTP,
4126 .dma_burst_length = 16,
4127 .clk_init = fu540_c000_clk_init,
4128 .init = fu540_c000_init,
4129 .jumbo_max_len = 10240,
4132 static const struct macb_config at91sam9260_config = {
4133 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4134 .clk_init = macb_clk_init,
4138 static const struct macb_config sama5d3macb_config = {
4139 .caps = MACB_CAPS_SG_DISABLED
4140 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4141 .clk_init = macb_clk_init,
4145 static const struct macb_config pc302gem_config = {
4146 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4147 .dma_burst_length = 16,
4148 .clk_init = macb_clk_init,
4152 static const struct macb_config sama5d2_config = {
4153 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4154 .dma_burst_length = 16,
4155 .clk_init = macb_clk_init,
4159 static const struct macb_config sama5d3_config = {
4160 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
4161 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4162 .dma_burst_length = 16,
4163 .clk_init = macb_clk_init,
4165 .jumbo_max_len = 10240,
4168 static const struct macb_config sama5d4_config = {
4169 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4170 .dma_burst_length = 4,
4171 .clk_init = macb_clk_init,
4175 static const struct macb_config emac_config = {
4176 .caps = MACB_CAPS_NEEDS_RSTONUBR,
4177 .clk_init = at91ether_clk_init,
4178 .init = at91ether_init,
4181 static const struct macb_config np4_config = {
4182 .caps = MACB_CAPS_USRIO_DISABLED,
4183 .clk_init = macb_clk_init,
4187 static const struct macb_config zynqmp_config = {
4188 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4190 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4191 .dma_burst_length = 16,
4192 .clk_init = macb_clk_init,
4194 .jumbo_max_len = 10240,
4197 static const struct macb_config zynq_config = {
4198 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4199 MACB_CAPS_NEEDS_RSTONUBR,
4200 .dma_burst_length = 16,
4201 .clk_init = macb_clk_init,
4205 static const struct of_device_id macb_dt_ids[] = {
4206 { .compatible = "cdns,at32ap7000-macb" },
4207 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4208 { .compatible = "cdns,macb" },
4209 { .compatible = "cdns,np4-macb", .data = &np4_config },
4210 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4211 { .compatible = "cdns,gem", .data = &pc302gem_config },
4212 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4213 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4214 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4215 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4216 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4217 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4218 { .compatible = "cdns,emac", .data = &emac_config },
4219 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
4220 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
4221 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4224 MODULE_DEVICE_TABLE(of, macb_dt_ids);
4225 #endif /* CONFIG_OF */
4227 static const struct macb_config default_gem_config = {
4228 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4230 MACB_CAPS_GEM_HAS_PTP,
4231 .dma_burst_length = 16,
4232 .clk_init = macb_clk_init,
4234 .jumbo_max_len = 10240,
4237 static int macb_probe(struct platform_device *pdev)
4239 const struct macb_config *macb_config = &default_gem_config;
4240 int (*clk_init)(struct platform_device *, struct clk **,
4241 struct clk **, struct clk **, struct clk **,
4242 struct clk **) = macb_config->clk_init;
4243 int (*init)(struct platform_device *) = macb_config->init;
4244 struct device_node *np = pdev->dev.of_node;
4245 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4246 struct clk *tsu_clk = NULL;
4247 unsigned int queue_mask, num_queues;
4249 phy_interface_t interface;
4250 struct net_device *dev;
4251 struct resource *regs;
4257 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4258 mem = devm_ioremap_resource(&pdev->dev, regs);
4260 return PTR_ERR(mem);
4263 const struct of_device_id *match;
4265 match = of_match_node(macb_dt_ids, np);
4266 if (match && match->data) {
4267 macb_config = match->data;
4268 clk_init = macb_config->clk_init;
4269 init = macb_config->init;
4273 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
4277 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
4278 pm_runtime_use_autosuspend(&pdev->dev);
4279 pm_runtime_get_noresume(&pdev->dev);
4280 pm_runtime_set_active(&pdev->dev);
4281 pm_runtime_enable(&pdev->dev);
4282 native_io = hw_is_native_io(mem);
4284 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4285 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4288 goto err_disable_clocks;
4291 dev->base_addr = regs->start;
4293 SET_NETDEV_DEV(dev, &pdev->dev);
4295 bp = netdev_priv(dev);
4299 bp->native_io = native_io;
4301 bp->macb_reg_readl = hw_readl_native;
4302 bp->macb_reg_writel = hw_writel_native;
4304 bp->macb_reg_readl = hw_readl;
4305 bp->macb_reg_writel = hw_writel;
4307 bp->num_queues = num_queues;
4308 bp->queue_mask = queue_mask;
4310 bp->dma_burst_length = macb_config->dma_burst_length;
4313 bp->tx_clk = tx_clk;
4314 bp->rx_clk = rx_clk;
4315 bp->tsu_clk = tsu_clk;
4317 bp->jumbo_max_len = macb_config->jumbo_max_len;
4320 if (of_get_property(np, "magic-packet", NULL))
4321 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4322 device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4324 spin_lock_init(&bp->lock);
4326 /* setup capabilities */
4327 macb_configure_caps(bp, macb_config);
4329 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4330 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4331 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
4332 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4335 platform_set_drvdata(pdev, dev);
4337 dev->irq = platform_get_irq(pdev, 0);
4340 goto err_out_free_netdev;
4343 /* MTU range: 68 - 1500 or 10240 */
4344 dev->min_mtu = GEM_MTU_MIN_SIZE;
4345 if (bp->caps & MACB_CAPS_JUMBO)
4346 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4348 dev->max_mtu = ETH_DATA_LEN;
4350 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4351 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4353 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4354 macb_dma_desc_get_size(bp);
4356 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4358 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4359 macb_dma_desc_get_size(bp);
4362 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4363 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4364 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4366 mac = of_get_mac_address(np);
4367 if (PTR_ERR(mac) == -EPROBE_DEFER) {
4368 err = -EPROBE_DEFER;
4369 goto err_out_free_netdev;
4370 } else if (!IS_ERR_OR_NULL(mac)) {
4371 ether_addr_copy(bp->dev->dev_addr, mac);
4373 macb_get_hwaddr(bp);
4376 err = of_get_phy_mode(np, &interface);
4378 /* not found in DT, MII by default */
4379 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4381 bp->phy_interface = interface;
4383 bp->speed = SPEED_UNKNOWN;
4385 /* IP specific init */
4388 goto err_out_free_netdev;
4390 err = macb_mii_init(bp);
4392 goto err_out_free_netdev;
4394 netif_carrier_off(dev);
4396 err = register_netdev(dev);
4398 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4399 goto err_out_unregister_mdio;
4402 tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task,
4405 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4406 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4407 dev->base_addr, dev->irq, dev->dev_addr);
4409 pm_runtime_mark_last_busy(&bp->pdev->dev);
4410 pm_runtime_put_autosuspend(&bp->pdev->dev);
4414 err_out_unregister_mdio:
4415 mdiobus_unregister(bp->mii_bus);
4416 mdiobus_free(bp->mii_bus);
4418 err_out_free_netdev:
4422 clk_disable_unprepare(tx_clk);
4423 clk_disable_unprepare(hclk);
4424 clk_disable_unprepare(pclk);
4425 clk_disable_unprepare(rx_clk);
4426 clk_disable_unprepare(tsu_clk);
4427 pm_runtime_disable(&pdev->dev);
4428 pm_runtime_set_suspended(&pdev->dev);
4429 pm_runtime_dont_use_autosuspend(&pdev->dev);
4434 static int macb_remove(struct platform_device *pdev)
4436 struct net_device *dev;
4439 dev = platform_get_drvdata(pdev);
4442 bp = netdev_priv(dev);
4443 mdiobus_unregister(bp->mii_bus);
4444 mdiobus_free(bp->mii_bus);
4446 unregister_netdev(dev);
4447 tasklet_kill(&bp->hresp_err_tasklet);
4448 pm_runtime_disable(&pdev->dev);
4449 pm_runtime_dont_use_autosuspend(&pdev->dev);
4450 if (!pm_runtime_suspended(&pdev->dev)) {
4451 clk_disable_unprepare(bp->tx_clk);
4452 clk_disable_unprepare(bp->hclk);
4453 clk_disable_unprepare(bp->pclk);
4454 clk_disable_unprepare(bp->rx_clk);
4455 clk_disable_unprepare(bp->tsu_clk);
4456 pm_runtime_set_suspended(&pdev->dev);
4458 phylink_destroy(bp->phylink);
4465 static int __maybe_unused macb_suspend(struct device *dev)
4467 struct net_device *netdev = dev_get_drvdata(dev);
4468 struct macb *bp = netdev_priv(netdev);
4469 struct macb_queue *queue = bp->queues;
4470 unsigned long flags;
4473 if (!netif_running(netdev))
4476 if (bp->wol & MACB_WOL_ENABLED) {
4477 macb_writel(bp, IER, MACB_BIT(WOL));
4478 macb_writel(bp, WOL, MACB_BIT(MAG));
4479 enable_irq_wake(bp->queues[0].irq);
4480 netif_device_detach(netdev);
4482 netif_device_detach(netdev);
4483 for (q = 0, queue = bp->queues; q < bp->num_queues;
4485 napi_disable(&queue->napi);
4487 phylink_stop(bp->phylink);
4489 spin_lock_irqsave(&bp->lock, flags);
4491 spin_unlock_irqrestore(&bp->lock, flags);
4493 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4494 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
4496 if (netdev->hw_features & NETIF_F_NTUPLE)
4497 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
4500 netif_carrier_off(netdev);
4502 bp->ptp_info->ptp_remove(netdev);
4503 pm_runtime_force_suspend(dev);
4508 static int __maybe_unused macb_resume(struct device *dev)
4510 struct net_device *netdev = dev_get_drvdata(dev);
4511 struct macb *bp = netdev_priv(netdev);
4512 struct macb_queue *queue = bp->queues;
4515 if (!netif_running(netdev))
4518 pm_runtime_force_resume(dev);
4520 if (bp->wol & MACB_WOL_ENABLED) {
4521 macb_writel(bp, IDR, MACB_BIT(WOL));
4522 macb_writel(bp, WOL, 0);
4523 disable_irq_wake(bp->queues[0].irq);
4525 macb_writel(bp, NCR, MACB_BIT(MPE));
4527 if (netdev->hw_features & NETIF_F_NTUPLE)
4528 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
4530 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4531 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
4533 for (q = 0, queue = bp->queues; q < bp->num_queues;
4535 napi_enable(&queue->napi);
4537 phylink_start(bp->phylink);
4542 macb_set_rx_mode(netdev);
4543 macb_restore_features(bp);
4544 netif_device_attach(netdev);
4546 bp->ptp_info->ptp_init(netdev);
4551 static int __maybe_unused macb_runtime_suspend(struct device *dev)
4553 struct net_device *netdev = dev_get_drvdata(dev);
4554 struct macb *bp = netdev_priv(netdev);
4556 if (!(device_may_wakeup(&bp->dev->dev))) {
4557 clk_disable_unprepare(bp->tx_clk);
4558 clk_disable_unprepare(bp->hclk);
4559 clk_disable_unprepare(bp->pclk);
4560 clk_disable_unprepare(bp->rx_clk);
4562 clk_disable_unprepare(bp->tsu_clk);
4567 static int __maybe_unused macb_runtime_resume(struct device *dev)
4569 struct net_device *netdev = dev_get_drvdata(dev);
4570 struct macb *bp = netdev_priv(netdev);
4572 if (!(device_may_wakeup(&bp->dev->dev))) {
4573 clk_prepare_enable(bp->pclk);
4574 clk_prepare_enable(bp->hclk);
4575 clk_prepare_enable(bp->tx_clk);
4576 clk_prepare_enable(bp->rx_clk);
4578 clk_prepare_enable(bp->tsu_clk);
4583 static const struct dev_pm_ops macb_pm_ops = {
4584 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
4585 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
4588 static struct platform_driver macb_driver = {
4589 .probe = macb_probe,
4590 .remove = macb_remove,
4593 .of_match_table = of_match_ptr(macb_dt_ids),
4598 module_platform_driver(macb_driver);
4600 MODULE_LICENSE("GPL");
4601 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
4602 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4603 MODULE_ALIAS("platform:macb");