1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence MACB/GEM Ethernet Controller driver
5 * Copyright (C) 2004-2006 Atmel Corporation
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/clk-provider.h>
11 #include <linux/crc32.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/circ_buf.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_data/macb.h>
27 #include <linux/platform_device.h>
28 #include <linux/phylink.h>
30 #include <linux/of_device.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of_mdio.h>
33 #include <linux/of_net.h>
35 #include <linux/udp.h>
36 #include <linux/tcp.h>
37 #include <linux/iopoll.h>
38 #include <linux/pm_runtime.h>
41 /* This structure is only used for MACB on SiFive FU540 devices */
42 struct sifive_fu540_macb_mgmt {
48 #define MACB_RX_BUFFER_SIZE 128
49 #define RX_BUFFER_MULTIPLE 64 /* bytes */
51 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
52 #define MIN_RX_RING_SIZE 64
53 #define MAX_RX_RING_SIZE 8192
54 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
57 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
58 #define MIN_TX_RING_SIZE 64
59 #define MAX_TX_RING_SIZE 4096
60 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
63 /* level of occupied TX descriptors under which we wake up TX process */
64 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
66 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
67 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
70 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
73 /* Max length of transmit frame must be a multiple of 8 bytes */
74 #define MACB_TX_LEN_ALIGN 8
75 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
76 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
78 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
79 #define MACB_NETIF_LSO NETIF_F_TSO
81 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
82 #define MACB_WOL_ENABLED (0x1 << 1)
84 /* Graceful stop timeouts in us. We should allow up to
85 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
87 #define MACB_HALT_TIMEOUT 1230
89 #define MACB_PM_TIMEOUT 100 /* ms */
91 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
93 /* DMA buffer descriptor might be different size
94 * depends on hardware configuration:
96 * 1. dma address width 32 bits:
97 * word 1: 32 bit address of Data Buffer
100 * 2. dma address width 64 bits:
101 * word 1: 32 bit address of Data Buffer
103 * word 3: upper 32 bit address of Data Buffer
106 * 3. dma address width 32 bits with hardware timestamping:
107 * word 1: 32 bit address of Data Buffer
109 * word 3: timestamp word 1
110 * word 4: timestamp word 2
112 * 4. dma address width 64 bits with hardware timestamping:
113 * word 1: 32 bit address of Data Buffer
115 * word 3: upper 32 bit address of Data Buffer
117 * word 5: timestamp word 1
118 * word 6: timestamp word 2
120 static unsigned int macb_dma_desc_get_size(struct macb *bp)
123 unsigned int desc_size;
125 switch (bp->hw_dma_cap) {
127 desc_size = sizeof(struct macb_dma_desc)
128 + sizeof(struct macb_dma_desc_64);
131 desc_size = sizeof(struct macb_dma_desc)
132 + sizeof(struct macb_dma_desc_ptp);
134 case HW_DMA_CAP_64B_PTP:
135 desc_size = sizeof(struct macb_dma_desc)
136 + sizeof(struct macb_dma_desc_64)
137 + sizeof(struct macb_dma_desc_ptp);
140 desc_size = sizeof(struct macb_dma_desc);
144 return sizeof(struct macb_dma_desc);
147 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
150 switch (bp->hw_dma_cap) {
155 case HW_DMA_CAP_64B_PTP:
165 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
166 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
168 return (struct macb_dma_desc_64 *)((void *)desc
169 + sizeof(struct macb_dma_desc));
173 /* Ring buffer accessors */
174 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
176 return index & (bp->tx_ring_size - 1);
179 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
182 index = macb_tx_ring_wrap(queue->bp, index);
183 index = macb_adj_dma_desc_idx(queue->bp, index);
184 return &queue->tx_ring[index];
187 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
190 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
193 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
197 offset = macb_tx_ring_wrap(queue->bp, index) *
198 macb_dma_desc_get_size(queue->bp);
200 return queue->tx_ring_dma + offset;
203 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
205 return index & (bp->rx_ring_size - 1);
208 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
210 index = macb_rx_ring_wrap(queue->bp, index);
211 index = macb_adj_dma_desc_idx(queue->bp, index);
212 return &queue->rx_ring[index];
215 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
217 return queue->rx_buffers + queue->bp->rx_buffer_size *
218 macb_rx_ring_wrap(queue->bp, index);
222 static u32 hw_readl_native(struct macb *bp, int offset)
224 return __raw_readl(bp->regs + offset);
227 static void hw_writel_native(struct macb *bp, int offset, u32 value)
229 __raw_writel(value, bp->regs + offset);
232 static u32 hw_readl(struct macb *bp, int offset)
234 return readl_relaxed(bp->regs + offset);
237 static void hw_writel(struct macb *bp, int offset, u32 value)
239 writel_relaxed(value, bp->regs + offset);
242 /* Find the CPU endianness by using the loopback bit of NCR register. When the
243 * CPU is in big endian we need to program swapped mode for management
246 static bool hw_is_native_io(void __iomem *addr)
248 u32 value = MACB_BIT(LLB);
250 __raw_writel(value, addr + MACB_NCR);
251 value = __raw_readl(addr + MACB_NCR);
253 /* Write 0 back to disable everything */
254 __raw_writel(0, addr + MACB_NCR);
256 return value == MACB_BIT(LLB);
259 static bool hw_is_gem(void __iomem *addr, bool native_io)
264 id = __raw_readl(addr + MACB_MID);
266 id = readl_relaxed(addr + MACB_MID);
268 return MACB_BFEXT(IDNUM, id) >= 0x2;
271 static void macb_set_hwaddr(struct macb *bp)
276 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
277 macb_or_gem_writel(bp, SA1B, bottom);
278 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
279 macb_or_gem_writel(bp, SA1T, top);
281 /* Clear unused address register sets */
282 macb_or_gem_writel(bp, SA2B, 0);
283 macb_or_gem_writel(bp, SA2T, 0);
284 macb_or_gem_writel(bp, SA3B, 0);
285 macb_or_gem_writel(bp, SA3T, 0);
286 macb_or_gem_writel(bp, SA4B, 0);
287 macb_or_gem_writel(bp, SA4T, 0);
290 static void macb_get_hwaddr(struct macb *bp)
297 /* Check all 4 address register for valid address */
298 for (i = 0; i < 4; i++) {
299 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
300 top = macb_or_gem_readl(bp, SA1T + i * 8);
302 addr[0] = bottom & 0xff;
303 addr[1] = (bottom >> 8) & 0xff;
304 addr[2] = (bottom >> 16) & 0xff;
305 addr[3] = (bottom >> 24) & 0xff;
306 addr[4] = top & 0xff;
307 addr[5] = (top >> 8) & 0xff;
309 if (is_valid_ether_addr(addr)) {
310 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
315 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
316 eth_hw_addr_random(bp->dev);
319 static int macb_mdio_wait_for_idle(struct macb *bp)
323 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
324 1, MACB_MDIO_TIMEOUT);
327 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
329 struct macb *bp = bus->priv;
332 status = pm_runtime_get_sync(&bp->pdev->dev);
336 status = macb_mdio_wait_for_idle(bp);
340 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
341 | MACB_BF(RW, MACB_MAN_READ)
342 | MACB_BF(PHYA, mii_id)
343 | MACB_BF(REGA, regnum)
344 | MACB_BF(CODE, MACB_MAN_CODE)));
346 status = macb_mdio_wait_for_idle(bp);
350 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
353 pm_runtime_mark_last_busy(&bp->pdev->dev);
354 pm_runtime_put_autosuspend(&bp->pdev->dev);
359 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
362 struct macb *bp = bus->priv;
365 status = pm_runtime_get_sync(&bp->pdev->dev);
369 status = macb_mdio_wait_for_idle(bp);
371 goto mdio_write_exit;
373 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
374 | MACB_BF(RW, MACB_MAN_WRITE)
375 | MACB_BF(PHYA, mii_id)
376 | MACB_BF(REGA, regnum)
377 | MACB_BF(CODE, MACB_MAN_CODE)
378 | MACB_BF(DATA, value)));
380 status = macb_mdio_wait_for_idle(bp);
382 goto mdio_write_exit;
385 pm_runtime_mark_last_busy(&bp->pdev->dev);
386 pm_runtime_put_autosuspend(&bp->pdev->dev);
391 static void macb_init_buffers(struct macb *bp)
393 struct macb_queue *queue;
396 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
397 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
398 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
399 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
400 queue_writel(queue, RBQPH,
401 upper_32_bits(queue->rx_ring_dma));
403 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
404 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
405 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
406 queue_writel(queue, TBQPH,
407 upper_32_bits(queue->tx_ring_dma));
413 * macb_set_tx_clk() - Set a clock to a new frequency
414 * @clk Pointer to the clock to change
415 * @rate New frequency in Hz
416 * @dev Pointer to the struct net_device
418 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
420 long ferr, rate, rate_rounded;
439 rate_rounded = clk_round_rate(clk, rate);
440 if (rate_rounded < 0)
443 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
446 ferr = abs(rate_rounded - rate);
447 ferr = DIV_ROUND_UP(ferr, rate / 100000);
449 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
452 if (clk_set_rate(clk, rate_rounded))
453 netdev_err(dev, "adjusting tx_clk failed.\n");
456 static void macb_validate(struct phylink_config *config,
457 unsigned long *supported,
458 struct phylink_link_state *state)
460 struct net_device *ndev = to_net_dev(config->dev);
461 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
462 struct macb *bp = netdev_priv(ndev);
464 /* We only support MII, RMII, GMII, RGMII & SGMII. */
465 if (state->interface != PHY_INTERFACE_MODE_NA &&
466 state->interface != PHY_INTERFACE_MODE_MII &&
467 state->interface != PHY_INTERFACE_MODE_RMII &&
468 state->interface != PHY_INTERFACE_MODE_GMII &&
469 state->interface != PHY_INTERFACE_MODE_SGMII &&
470 !phy_interface_mode_is_rgmii(state->interface)) {
471 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
475 if (!macb_is_gem(bp) &&
476 (state->interface == PHY_INTERFACE_MODE_GMII ||
477 phy_interface_mode_is_rgmii(state->interface))) {
478 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
482 phylink_set_port_modes(mask);
483 phylink_set(mask, Autoneg);
484 phylink_set(mask, Asym_Pause);
486 phylink_set(mask, 10baseT_Half);
487 phylink_set(mask, 10baseT_Full);
488 phylink_set(mask, 100baseT_Half);
489 phylink_set(mask, 100baseT_Full);
491 if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE &&
492 (state->interface == PHY_INTERFACE_MODE_NA ||
493 state->interface == PHY_INTERFACE_MODE_GMII ||
494 state->interface == PHY_INTERFACE_MODE_SGMII ||
495 phy_interface_mode_is_rgmii(state->interface))) {
496 phylink_set(mask, 1000baseT_Full);
497 phylink_set(mask, 1000baseX_Full);
499 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
500 phylink_set(mask, 1000baseT_Half);
503 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
504 bitmap_and(state->advertising, state->advertising, mask,
505 __ETHTOOL_LINK_MODE_MASK_NBITS);
508 static void macb_mac_pcs_get_state(struct phylink_config *config,
509 struct phylink_link_state *state)
514 static void macb_mac_an_restart(struct phylink_config *config)
519 static void macb_mac_config(struct phylink_config *config, unsigned int mode,
520 const struct phylink_link_state *state)
522 struct net_device *ndev = to_net_dev(config->dev);
523 struct macb *bp = netdev_priv(ndev);
527 spin_lock_irqsave(&bp->lock, flags);
529 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
531 /* Clear all the bits we might set later */
532 ctrl &= ~(GEM_BIT(GBE) | MACB_BIT(SPD) | MACB_BIT(FD) | MACB_BIT(PAE) |
533 GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
535 if (state->speed == SPEED_1000)
536 ctrl |= GEM_BIT(GBE);
537 else if (state->speed == SPEED_100)
538 ctrl |= MACB_BIT(SPD);
541 ctrl |= MACB_BIT(FD);
543 /* We do not support MLO_PAUSE_RX yet */
544 if (state->pause & MLO_PAUSE_TX)
545 ctrl |= MACB_BIT(PAE);
547 if (state->interface == PHY_INTERFACE_MODE_SGMII)
548 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
550 /* Apply the new configuration, if any */
552 macb_or_gem_writel(bp, NCFGR, ctrl);
554 bp->speed = state->speed;
556 spin_unlock_irqrestore(&bp->lock, flags);
559 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
560 phy_interface_t interface)
562 struct net_device *ndev = to_net_dev(config->dev);
563 struct macb *bp = netdev_priv(ndev);
564 struct macb_queue *queue;
568 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
569 queue_writel(queue, IDR,
570 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
572 /* Disable Rx and Tx */
573 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
574 macb_writel(bp, NCR, ctrl);
576 netif_tx_stop_all_queues(ndev);
579 static void macb_mac_link_up(struct phylink_config *config, unsigned int mode,
580 phy_interface_t interface, struct phy_device *phy)
582 struct net_device *ndev = to_net_dev(config->dev);
583 struct macb *bp = netdev_priv(ndev);
584 struct macb_queue *queue;
587 macb_set_tx_clk(bp->tx_clk, bp->speed, ndev);
589 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
590 * cleared the pipeline and control registers.
592 bp->macbgem_ops.mog_init_rings(bp);
593 macb_init_buffers(bp);
595 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
596 queue_writel(queue, IER,
597 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
599 /* Enable Rx and Tx */
600 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
602 netif_tx_wake_all_queues(ndev);
605 static const struct phylink_mac_ops macb_phylink_ops = {
606 .validate = macb_validate,
607 .mac_pcs_get_state = macb_mac_pcs_get_state,
608 .mac_an_restart = macb_mac_an_restart,
609 .mac_config = macb_mac_config,
610 .mac_link_down = macb_mac_link_down,
611 .mac_link_up = macb_mac_link_up,
614 static int macb_phylink_connect(struct macb *bp)
616 struct net_device *dev = bp->dev;
617 struct phy_device *phydev;
620 if (bp->pdev->dev.of_node &&
621 of_parse_phandle(bp->pdev->dev.of_node, "phy-handle", 0)) {
622 ret = phylink_of_phy_connect(bp->phylink, bp->pdev->dev.of_node,
625 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
629 phydev = phy_find_first(bp->mii_bus);
631 netdev_err(dev, "no PHY found\n");
635 /* attach the mac to the phy */
636 ret = phylink_connect_phy(bp->phylink, phydev);
638 netdev_err(dev, "Could not attach to PHY (%d)\n", ret);
643 phylink_start(bp->phylink);
648 /* based on au1000_eth. c*/
649 static int macb_mii_probe(struct net_device *dev)
651 struct macb *bp = netdev_priv(dev);
653 bp->phylink_config.dev = &dev->dev;
654 bp->phylink_config.type = PHYLINK_NETDEV;
656 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
657 bp->phy_interface, &macb_phylink_ops);
658 if (IS_ERR(bp->phylink)) {
659 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
660 PTR_ERR(bp->phylink));
661 return PTR_ERR(bp->phylink);
667 static int macb_mdiobus_register(struct macb *bp)
669 struct device_node *child, *np = bp->pdev->dev.of_node;
671 /* Only create the PHY from the device tree if at least one PHY is
672 * described. Otherwise scan the entire MDIO bus. We do this to support
673 * old device tree that did not follow the best practices and did not
674 * describe their network PHYs.
676 for_each_available_child_of_node(np, child)
677 if (of_mdiobus_child_is_phy(child)) {
678 /* The loop increments the child refcount,
679 * decrement it before returning.
683 return of_mdiobus_register(bp->mii_bus, np);
686 return mdiobus_register(bp->mii_bus);
689 static int macb_mii_init(struct macb *bp)
693 /* Enable management port */
694 macb_writel(bp, NCR, MACB_BIT(MPE));
696 bp->mii_bus = mdiobus_alloc();
702 bp->mii_bus->name = "MACB_mii_bus";
703 bp->mii_bus->read = &macb_mdio_read;
704 bp->mii_bus->write = &macb_mdio_write;
705 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
706 bp->pdev->name, bp->pdev->id);
707 bp->mii_bus->priv = bp;
708 bp->mii_bus->parent = &bp->pdev->dev;
710 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
712 err = macb_mdiobus_register(bp);
714 goto err_out_free_mdiobus;
716 err = macb_mii_probe(bp->dev);
718 goto err_out_unregister_bus;
722 err_out_unregister_bus:
723 mdiobus_unregister(bp->mii_bus);
724 err_out_free_mdiobus:
725 mdiobus_free(bp->mii_bus);
730 static void macb_update_stats(struct macb *bp)
732 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
733 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
734 int offset = MACB_PFR;
736 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
738 for (; p < end; p++, offset += 4)
739 *p += bp->macb_reg_readl(bp, offset);
742 static int macb_halt_tx(struct macb *bp)
744 unsigned long halt_time, timeout;
747 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
749 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
752 status = macb_readl(bp, TSR);
753 if (!(status & MACB_BIT(TGO)))
757 } while (time_before(halt_time, timeout));
762 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
764 if (tx_skb->mapping) {
765 if (tx_skb->mapped_as_page)
766 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
767 tx_skb->size, DMA_TO_DEVICE);
769 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
770 tx_skb->size, DMA_TO_DEVICE);
775 dev_kfree_skb_any(tx_skb->skb);
780 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
782 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
783 struct macb_dma_desc_64 *desc_64;
785 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
786 desc_64 = macb_64b_desc(bp, desc);
787 desc_64->addrh = upper_32_bits(addr);
788 /* The low bits of RX address contain the RX_USED bit, clearing
789 * of which allows packet RX. Make sure the high bits are also
790 * visible to HW at that point.
795 desc->addr = lower_32_bits(addr);
798 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
801 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
802 struct macb_dma_desc_64 *desc_64;
804 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
805 desc_64 = macb_64b_desc(bp, desc);
806 addr = ((u64)(desc_64->addrh) << 32);
809 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
813 static void macb_tx_error_task(struct work_struct *work)
815 struct macb_queue *queue = container_of(work, struct macb_queue,
817 struct macb *bp = queue->bp;
818 struct macb_tx_skb *tx_skb;
819 struct macb_dma_desc *desc;
824 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
825 (unsigned int)(queue - bp->queues),
826 queue->tx_tail, queue->tx_head);
828 /* Prevent the queue IRQ handlers from running: each of them may call
829 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
830 * As explained below, we have to halt the transmission before updating
831 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
832 * network engine about the macb/gem being halted.
834 spin_lock_irqsave(&bp->lock, flags);
836 /* Make sure nobody is trying to queue up new packets */
837 netif_tx_stop_all_queues(bp->dev);
839 /* Stop transmission now
840 * (in case we have just queued new packets)
841 * macb/gem must be halted to write TBQP register
843 if (macb_halt_tx(bp))
844 /* Just complain for now, reinitializing TX path can be good */
845 netdev_err(bp->dev, "BUG: halt tx timed out\n");
847 /* Treat frames in TX queue including the ones that caused the error.
848 * Free transmit buffers in upper layer.
850 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
853 desc = macb_tx_desc(queue, tail);
855 tx_skb = macb_tx_skb(queue, tail);
858 if (ctrl & MACB_BIT(TX_USED)) {
859 /* skb is set for the last buffer of the frame */
861 macb_tx_unmap(bp, tx_skb);
863 tx_skb = macb_tx_skb(queue, tail);
867 /* ctrl still refers to the first buffer descriptor
868 * since it's the only one written back by the hardware
870 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
871 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
872 macb_tx_ring_wrap(bp, tail),
874 bp->dev->stats.tx_packets++;
875 queue->stats.tx_packets++;
876 bp->dev->stats.tx_bytes += skb->len;
877 queue->stats.tx_bytes += skb->len;
880 /* "Buffers exhausted mid-frame" errors may only happen
881 * if the driver is buggy, so complain loudly about
882 * those. Statistics are updated by hardware.
884 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
886 "BUG: TX buffers exhausted mid-frame\n");
888 desc->ctrl = ctrl | MACB_BIT(TX_USED);
891 macb_tx_unmap(bp, tx_skb);
894 /* Set end of TX queue */
895 desc = macb_tx_desc(queue, 0);
896 macb_set_addr(bp, desc, 0);
897 desc->ctrl = MACB_BIT(TX_USED);
899 /* Make descriptor updates visible to hardware */
902 /* Reinitialize the TX desc queue */
903 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
904 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
905 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
906 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
908 /* Make TX ring reflect state of hardware */
912 /* Housework before enabling TX IRQ */
913 macb_writel(bp, TSR, macb_readl(bp, TSR));
914 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
916 /* Now we are ready to start transmission again */
917 netif_tx_start_all_queues(bp->dev);
918 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
920 spin_unlock_irqrestore(&bp->lock, flags);
923 static void macb_tx_interrupt(struct macb_queue *queue)
928 struct macb *bp = queue->bp;
929 u16 queue_index = queue - bp->queues;
931 status = macb_readl(bp, TSR);
932 macb_writel(bp, TSR, status);
934 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
935 queue_writel(queue, ISR, MACB_BIT(TCOMP));
937 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
938 (unsigned long)status);
940 head = queue->tx_head;
941 for (tail = queue->tx_tail; tail != head; tail++) {
942 struct macb_tx_skb *tx_skb;
944 struct macb_dma_desc *desc;
947 desc = macb_tx_desc(queue, tail);
949 /* Make hw descriptor updates visible to CPU */
954 /* TX_USED bit is only set by hardware on the very first buffer
955 * descriptor of the transmitted frame.
957 if (!(ctrl & MACB_BIT(TX_USED)))
960 /* Process all buffers of the current transmitted frame */
962 tx_skb = macb_tx_skb(queue, tail);
965 /* First, update TX stats if needed */
967 if (unlikely(skb_shinfo(skb)->tx_flags &
969 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
970 /* skb now belongs to timestamp buffer
971 * and will be removed later
975 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
976 macb_tx_ring_wrap(bp, tail),
978 bp->dev->stats.tx_packets++;
979 queue->stats.tx_packets++;
980 bp->dev->stats.tx_bytes += skb->len;
981 queue->stats.tx_bytes += skb->len;
984 /* Now we can safely release resources */
985 macb_tx_unmap(bp, tx_skb);
987 /* skb is set only for the last buffer of the frame.
988 * WARNING: at this point skb has been freed by
996 queue->tx_tail = tail;
997 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
998 CIRC_CNT(queue->tx_head, queue->tx_tail,
999 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1000 netif_wake_subqueue(bp->dev, queue_index);
1003 static void gem_rx_refill(struct macb_queue *queue)
1006 struct sk_buff *skb;
1008 struct macb *bp = queue->bp;
1009 struct macb_dma_desc *desc;
1011 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1012 bp->rx_ring_size) > 0) {
1013 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1015 /* Make hw descriptor updates visible to CPU */
1018 queue->rx_prepared_head++;
1019 desc = macb_rx_desc(queue, entry);
1021 if (!queue->rx_skbuff[entry]) {
1022 /* allocate sk_buff for this free entry in ring */
1023 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1024 if (unlikely(!skb)) {
1026 "Unable to allocate sk_buff\n");
1030 /* now fill corresponding descriptor entry */
1031 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1034 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1039 queue->rx_skbuff[entry] = skb;
1041 if (entry == bp->rx_ring_size - 1)
1042 paddr |= MACB_BIT(RX_WRAP);
1044 /* Setting addr clears RX_USED and allows reception,
1045 * make sure ctrl is cleared first to avoid a race.
1048 macb_set_addr(bp, desc, paddr);
1050 /* properly align Ethernet header */
1051 skb_reserve(skb, NET_IP_ALIGN);
1055 desc->addr &= ~MACB_BIT(RX_USED);
1059 /* Make descriptor updates visible to hardware */
1062 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1063 queue, queue->rx_prepared_head, queue->rx_tail);
1066 /* Mark DMA descriptors from begin up to and not including end as unused */
1067 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1072 for (frag = begin; frag != end; frag++) {
1073 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1075 desc->addr &= ~MACB_BIT(RX_USED);
1078 /* Make descriptor updates visible to hardware */
1081 /* When this happens, the hardware stats registers for
1082 * whatever caused this is updated, so we don't have to record
1087 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1090 struct macb *bp = queue->bp;
1093 struct sk_buff *skb;
1094 struct macb_dma_desc *desc;
1097 while (count < budget) {
1102 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1103 desc = macb_rx_desc(queue, entry);
1105 /* Make hw descriptor updates visible to CPU */
1108 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1109 addr = macb_get_addr(bp, desc);
1114 /* Ensure ctrl is at least as up-to-date as rxused */
1122 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1124 "not whole frame pointed by descriptor\n");
1125 bp->dev->stats.rx_dropped++;
1126 queue->stats.rx_dropped++;
1129 skb = queue->rx_skbuff[entry];
1130 if (unlikely(!skb)) {
1132 "inconsistent Rx descriptor chain\n");
1133 bp->dev->stats.rx_dropped++;
1134 queue->stats.rx_dropped++;
1137 /* now everything is ready for receiving packet */
1138 queue->rx_skbuff[entry] = NULL;
1139 len = ctrl & bp->rx_frm_len_mask;
1141 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1144 dma_unmap_single(&bp->pdev->dev, addr,
1145 bp->rx_buffer_size, DMA_FROM_DEVICE);
1147 skb->protocol = eth_type_trans(skb, bp->dev);
1148 skb_checksum_none_assert(skb);
1149 if (bp->dev->features & NETIF_F_RXCSUM &&
1150 !(bp->dev->flags & IFF_PROMISC) &&
1151 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1152 skb->ip_summed = CHECKSUM_UNNECESSARY;
1154 bp->dev->stats.rx_packets++;
1155 queue->stats.rx_packets++;
1156 bp->dev->stats.rx_bytes += skb->len;
1157 queue->stats.rx_bytes += skb->len;
1159 gem_ptp_do_rxstamp(bp, skb, desc);
1161 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1162 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1163 skb->len, skb->csum);
1164 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1165 skb_mac_header(skb), 16, true);
1166 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1167 skb->data, 32, true);
1170 napi_gro_receive(napi, skb);
1173 gem_rx_refill(queue);
1178 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1179 unsigned int first_frag, unsigned int last_frag)
1183 unsigned int offset;
1184 struct sk_buff *skb;
1185 struct macb_dma_desc *desc;
1186 struct macb *bp = queue->bp;
1188 desc = macb_rx_desc(queue, last_frag);
1189 len = desc->ctrl & bp->rx_frm_len_mask;
1191 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1192 macb_rx_ring_wrap(bp, first_frag),
1193 macb_rx_ring_wrap(bp, last_frag), len);
1195 /* The ethernet header starts NET_IP_ALIGN bytes into the
1196 * first buffer. Since the header is 14 bytes, this makes the
1197 * payload word-aligned.
1199 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1200 * the two padding bytes into the skb so that we avoid hitting
1201 * the slowpath in memcpy(), and pull them off afterwards.
1203 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1205 bp->dev->stats.rx_dropped++;
1206 for (frag = first_frag; ; frag++) {
1207 desc = macb_rx_desc(queue, frag);
1208 desc->addr &= ~MACB_BIT(RX_USED);
1209 if (frag == last_frag)
1213 /* Make descriptor updates visible to hardware */
1220 len += NET_IP_ALIGN;
1221 skb_checksum_none_assert(skb);
1224 for (frag = first_frag; ; frag++) {
1225 unsigned int frag_len = bp->rx_buffer_size;
1227 if (offset + frag_len > len) {
1228 if (unlikely(frag != last_frag)) {
1229 dev_kfree_skb_any(skb);
1232 frag_len = len - offset;
1234 skb_copy_to_linear_data_offset(skb, offset,
1235 macb_rx_buffer(queue, frag),
1237 offset += bp->rx_buffer_size;
1238 desc = macb_rx_desc(queue, frag);
1239 desc->addr &= ~MACB_BIT(RX_USED);
1241 if (frag == last_frag)
1245 /* Make descriptor updates visible to hardware */
1248 __skb_pull(skb, NET_IP_ALIGN);
1249 skb->protocol = eth_type_trans(skb, bp->dev);
1251 bp->dev->stats.rx_packets++;
1252 bp->dev->stats.rx_bytes += skb->len;
1253 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1254 skb->len, skb->csum);
1255 napi_gro_receive(napi, skb);
1260 static inline void macb_init_rx_ring(struct macb_queue *queue)
1262 struct macb *bp = queue->bp;
1264 struct macb_dma_desc *desc = NULL;
1267 addr = queue->rx_buffers_dma;
1268 for (i = 0; i < bp->rx_ring_size; i++) {
1269 desc = macb_rx_desc(queue, i);
1270 macb_set_addr(bp, desc, addr);
1272 addr += bp->rx_buffer_size;
1274 desc->addr |= MACB_BIT(RX_WRAP);
1278 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1281 struct macb *bp = queue->bp;
1282 bool reset_rx_queue = false;
1285 int first_frag = -1;
1287 for (tail = queue->rx_tail; budget > 0; tail++) {
1288 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1291 /* Make hw descriptor updates visible to CPU */
1294 if (!(desc->addr & MACB_BIT(RX_USED)))
1297 /* Ensure ctrl is at least as up-to-date as addr */
1302 if (ctrl & MACB_BIT(RX_SOF)) {
1303 if (first_frag != -1)
1304 discard_partial_frame(queue, first_frag, tail);
1308 if (ctrl & MACB_BIT(RX_EOF)) {
1311 if (unlikely(first_frag == -1)) {
1312 reset_rx_queue = true;
1316 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1318 if (unlikely(dropped < 0)) {
1319 reset_rx_queue = true;
1329 if (unlikely(reset_rx_queue)) {
1330 unsigned long flags;
1333 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1335 spin_lock_irqsave(&bp->lock, flags);
1337 ctrl = macb_readl(bp, NCR);
1338 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1340 macb_init_rx_ring(queue);
1341 queue_writel(queue, RBQP, queue->rx_ring_dma);
1343 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1345 spin_unlock_irqrestore(&bp->lock, flags);
1349 if (first_frag != -1)
1350 queue->rx_tail = first_frag;
1352 queue->rx_tail = tail;
1357 static int macb_poll(struct napi_struct *napi, int budget)
1359 struct macb_queue *queue = container_of(napi, struct macb_queue, napi);
1360 struct macb *bp = queue->bp;
1364 status = macb_readl(bp, RSR);
1365 macb_writel(bp, RSR, status);
1367 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
1368 (unsigned long)status, budget);
1370 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1371 if (work_done < budget) {
1372 napi_complete_done(napi, work_done);
1374 /* Packets received while interrupts were disabled */
1375 status = macb_readl(bp, RSR);
1377 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1378 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1379 napi_reschedule(napi);
1381 queue_writel(queue, IER, bp->rx_intr_mask);
1385 /* TODO: Handle errors */
1390 static void macb_hresp_error_task(unsigned long data)
1392 struct macb *bp = (struct macb *)data;
1393 struct net_device *dev = bp->dev;
1394 struct macb_queue *queue = bp->queues;
1398 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1399 queue_writel(queue, IDR, bp->rx_intr_mask |
1403 ctrl = macb_readl(bp, NCR);
1404 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1405 macb_writel(bp, NCR, ctrl);
1407 netif_tx_stop_all_queues(dev);
1408 netif_carrier_off(dev);
1410 bp->macbgem_ops.mog_init_rings(bp);
1412 /* Initialize TX and RX buffers */
1413 macb_init_buffers(bp);
1415 /* Enable interrupts */
1416 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1417 queue_writel(queue, IER,
1422 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1423 macb_writel(bp, NCR, ctrl);
1425 netif_carrier_on(dev);
1426 netif_tx_start_all_queues(dev);
1429 static void macb_tx_restart(struct macb_queue *queue)
1431 unsigned int head = queue->tx_head;
1432 unsigned int tail = queue->tx_tail;
1433 struct macb *bp = queue->bp;
1435 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1436 queue_writel(queue, ISR, MACB_BIT(TXUBR));
1441 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1444 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1446 struct macb_queue *queue = dev_id;
1447 struct macb *bp = queue->bp;
1448 struct net_device *dev = bp->dev;
1451 status = queue_readl(queue, ISR);
1453 if (unlikely(!status))
1456 spin_lock(&bp->lock);
1459 /* close possible race with dev_close */
1460 if (unlikely(!netif_running(dev))) {
1461 queue_writel(queue, IDR, -1);
1462 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1463 queue_writel(queue, ISR, -1);
1467 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1468 (unsigned int)(queue - bp->queues),
1469 (unsigned long)status);
1471 if (status & bp->rx_intr_mask) {
1472 /* There's no point taking any more interrupts
1473 * until we have processed the buffers. The
1474 * scheduling call may fail if the poll routine
1475 * is already scheduled, so disable interrupts
1478 queue_writel(queue, IDR, bp->rx_intr_mask);
1479 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1480 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1482 if (napi_schedule_prep(&queue->napi)) {
1483 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1484 __napi_schedule(&queue->napi);
1488 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1489 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1490 schedule_work(&queue->tx_error_task);
1492 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1493 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1498 if (status & MACB_BIT(TCOMP))
1499 macb_tx_interrupt(queue);
1501 if (status & MACB_BIT(TXUBR))
1502 macb_tx_restart(queue);
1504 /* Link change detection isn't possible with RMII, so we'll
1505 * add that if/when we get our hands on a full-blown MII PHY.
1508 /* There is a hardware issue under heavy load where DMA can
1509 * stop, this causes endless "used buffer descriptor read"
1510 * interrupts but it can be cleared by re-enabling RX. See
1511 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1512 * section 16.7.4 for details. RXUBR is only enabled for
1513 * these two versions.
1515 if (status & MACB_BIT(RXUBR)) {
1516 ctrl = macb_readl(bp, NCR);
1517 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1519 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1521 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1522 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1525 if (status & MACB_BIT(ISR_ROVR)) {
1526 /* We missed at least one packet */
1527 if (macb_is_gem(bp))
1528 bp->hw_stats.gem.rx_overruns++;
1530 bp->hw_stats.macb.rx_overruns++;
1532 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1533 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1536 if (status & MACB_BIT(HRESP)) {
1537 tasklet_schedule(&bp->hresp_err_tasklet);
1538 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1540 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1541 queue_writel(queue, ISR, MACB_BIT(HRESP));
1543 status = queue_readl(queue, ISR);
1546 spin_unlock(&bp->lock);
1551 #ifdef CONFIG_NET_POLL_CONTROLLER
1552 /* Polling receive - used by netconsole and other diagnostic tools
1553 * to allow network i/o with interrupts disabled.
1555 static void macb_poll_controller(struct net_device *dev)
1557 struct macb *bp = netdev_priv(dev);
1558 struct macb_queue *queue;
1559 unsigned long flags;
1562 local_irq_save(flags);
1563 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1564 macb_interrupt(dev->irq, queue);
1565 local_irq_restore(flags);
1569 static unsigned int macb_tx_map(struct macb *bp,
1570 struct macb_queue *queue,
1571 struct sk_buff *skb,
1572 unsigned int hdrlen)
1575 unsigned int len, entry, i, tx_head = queue->tx_head;
1576 struct macb_tx_skb *tx_skb = NULL;
1577 struct macb_dma_desc *desc;
1578 unsigned int offset, size, count = 0;
1579 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1580 unsigned int eof = 1, mss_mfs = 0;
1581 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1584 if (skb_shinfo(skb)->gso_size != 0) {
1585 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1587 lso_ctrl = MACB_LSO_UFO_ENABLE;
1590 lso_ctrl = MACB_LSO_TSO_ENABLE;
1593 /* First, map non-paged data */
1594 len = skb_headlen(skb);
1596 /* first buffer length */
1601 entry = macb_tx_ring_wrap(bp, tx_head);
1602 tx_skb = &queue->tx_skb[entry];
1604 mapping = dma_map_single(&bp->pdev->dev,
1606 size, DMA_TO_DEVICE);
1607 if (dma_mapping_error(&bp->pdev->dev, mapping))
1610 /* Save info to properly release resources */
1612 tx_skb->mapping = mapping;
1613 tx_skb->size = size;
1614 tx_skb->mapped_as_page = false;
1621 size = min(len, bp->max_tx_length);
1624 /* Then, map paged data from fragments */
1625 for (f = 0; f < nr_frags; f++) {
1626 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1628 len = skb_frag_size(frag);
1631 size = min(len, bp->max_tx_length);
1632 entry = macb_tx_ring_wrap(bp, tx_head);
1633 tx_skb = &queue->tx_skb[entry];
1635 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1636 offset, size, DMA_TO_DEVICE);
1637 if (dma_mapping_error(&bp->pdev->dev, mapping))
1640 /* Save info to properly release resources */
1642 tx_skb->mapping = mapping;
1643 tx_skb->size = size;
1644 tx_skb->mapped_as_page = true;
1653 /* Should never happen */
1654 if (unlikely(!tx_skb)) {
1655 netdev_err(bp->dev, "BUG! empty skb!\n");
1659 /* This is the last buffer of the frame: save socket buffer */
1662 /* Update TX ring: update buffer descriptors in reverse order
1663 * to avoid race condition
1666 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1667 * to set the end of TX queue
1670 entry = macb_tx_ring_wrap(bp, i);
1671 ctrl = MACB_BIT(TX_USED);
1672 desc = macb_tx_desc(queue, entry);
1676 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
1677 /* include header and FCS in value given to h/w */
1678 mss_mfs = skb_shinfo(skb)->gso_size +
1679 skb_transport_offset(skb) +
1682 mss_mfs = skb_shinfo(skb)->gso_size;
1683 /* TCP Sequence Number Source Select
1684 * can be set only for TSO
1692 entry = macb_tx_ring_wrap(bp, i);
1693 tx_skb = &queue->tx_skb[entry];
1694 desc = macb_tx_desc(queue, entry);
1696 ctrl = (u32)tx_skb->size;
1698 ctrl |= MACB_BIT(TX_LAST);
1701 if (unlikely(entry == (bp->tx_ring_size - 1)))
1702 ctrl |= MACB_BIT(TX_WRAP);
1704 /* First descriptor is header descriptor */
1705 if (i == queue->tx_head) {
1706 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
1707 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
1708 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
1709 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl)
1710 ctrl |= MACB_BIT(TX_NOCRC);
1712 /* Only set MSS/MFS on payload descriptors
1713 * (second or later descriptor)
1715 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
1717 /* Set TX buffer descriptor */
1718 macb_set_addr(bp, desc, tx_skb->mapping);
1719 /* desc->addr must be visible to hardware before clearing
1720 * 'TX_USED' bit in desc->ctrl.
1724 } while (i != queue->tx_head);
1726 queue->tx_head = tx_head;
1731 netdev_err(bp->dev, "TX DMA map failed\n");
1733 for (i = queue->tx_head; i != tx_head; i++) {
1734 tx_skb = macb_tx_skb(queue, i);
1736 macb_tx_unmap(bp, tx_skb);
1742 static netdev_features_t macb_features_check(struct sk_buff *skb,
1743 struct net_device *dev,
1744 netdev_features_t features)
1746 unsigned int nr_frags, f;
1747 unsigned int hdrlen;
1749 /* Validate LSO compatibility */
1751 /* there is only one buffer */
1752 if (!skb_is_nonlinear(skb))
1755 /* length of header */
1756 hdrlen = skb_transport_offset(skb);
1757 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
1758 hdrlen += tcp_hdrlen(skb);
1761 * When software supplies two or more payload buffers all payload buffers
1762 * apart from the last must be a multiple of 8 bytes in size.
1764 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
1765 return features & ~MACB_NETIF_LSO;
1767 nr_frags = skb_shinfo(skb)->nr_frags;
1768 /* No need to check last fragment */
1770 for (f = 0; f < nr_frags; f++) {
1771 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1773 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
1774 return features & ~MACB_NETIF_LSO;
1779 static inline int macb_clear_csum(struct sk_buff *skb)
1781 /* no change for packets without checksum offloading */
1782 if (skb->ip_summed != CHECKSUM_PARTIAL)
1785 /* make sure we can modify the header */
1786 if (unlikely(skb_cow_head(skb, 0)))
1789 /* initialize checksum field
1790 * This is required - at least for Zynq, which otherwise calculates
1791 * wrong UDP header checksums for UDP packets with UDP data len <=2
1793 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
1797 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
1799 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb);
1800 int padlen = ETH_ZLEN - (*skb)->len;
1801 int headroom = skb_headroom(*skb);
1802 int tailroom = skb_tailroom(*skb);
1803 struct sk_buff *nskb;
1806 if (!(ndev->features & NETIF_F_HW_CSUM) ||
1807 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
1808 skb_shinfo(*skb)->gso_size) /* Not available for GSO */
1812 /* FCS could be appeded to tailroom. */
1813 if (tailroom >= ETH_FCS_LEN)
1815 /* FCS could be appeded by moving data to headroom. */
1816 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
1818 /* No room for FCS, need to reallocate skb. */
1820 padlen = ETH_FCS_LEN;
1822 /* Add room for FCS. */
1823 padlen += ETH_FCS_LEN;
1826 if (!cloned && headroom + tailroom >= padlen) {
1827 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
1828 skb_set_tail_pointer(*skb, (*skb)->len);
1830 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
1834 dev_consume_skb_any(*skb);
1838 if (padlen > ETH_FCS_LEN)
1839 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
1842 /* set FCS to packet */
1843 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
1846 skb_put_u8(*skb, fcs & 0xff);
1847 skb_put_u8(*skb, (fcs >> 8) & 0xff);
1848 skb_put_u8(*skb, (fcs >> 16) & 0xff);
1849 skb_put_u8(*skb, (fcs >> 24) & 0xff);
1854 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1856 u16 queue_index = skb_get_queue_mapping(skb);
1857 struct macb *bp = netdev_priv(dev);
1858 struct macb_queue *queue = &bp->queues[queue_index];
1859 unsigned long flags;
1860 unsigned int desc_cnt, nr_frags, frag_size, f;
1861 unsigned int hdrlen;
1862 bool is_lso, is_udp = 0;
1863 netdev_tx_t ret = NETDEV_TX_OK;
1865 if (macb_clear_csum(skb)) {
1866 dev_kfree_skb_any(skb);
1870 if (macb_pad_and_fcs(&skb, dev)) {
1871 dev_kfree_skb_any(skb);
1875 is_lso = (skb_shinfo(skb)->gso_size != 0);
1878 is_udp = !!(ip_hdr(skb)->protocol == IPPROTO_UDP);
1880 /* length of headers */
1882 /* only queue eth + ip headers separately for UDP */
1883 hdrlen = skb_transport_offset(skb);
1885 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb);
1886 if (skb_headlen(skb) < hdrlen) {
1887 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
1888 /* if this is required, would need to copy to single buffer */
1889 return NETDEV_TX_BUSY;
1892 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
1894 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1895 netdev_vdbg(bp->dev,
1896 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1897 queue_index, skb->len, skb->head, skb->data,
1898 skb_tail_pointer(skb), skb_end_pointer(skb));
1899 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1900 skb->data, 16, true);
1903 /* Count how many TX buffer descriptors are needed to send this
1904 * socket buffer: skb fragments of jumbo frames may need to be
1905 * split into many buffer descriptors.
1907 if (is_lso && (skb_headlen(skb) > hdrlen))
1908 /* extra header descriptor if also payload in first buffer */
1909 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
1911 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
1912 nr_frags = skb_shinfo(skb)->nr_frags;
1913 for (f = 0; f < nr_frags; f++) {
1914 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1915 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
1918 spin_lock_irqsave(&bp->lock, flags);
1920 /* This is a hard error, log it. */
1921 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
1922 bp->tx_ring_size) < desc_cnt) {
1923 netif_stop_subqueue(dev, queue_index);
1924 spin_unlock_irqrestore(&bp->lock, flags);
1925 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1926 queue->tx_head, queue->tx_tail);
1927 return NETDEV_TX_BUSY;
1930 /* Map socket buffer for DMA transfer */
1931 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
1932 dev_kfree_skb_any(skb);
1936 /* Make newly initialized descriptor visible to hardware */
1938 skb_tx_timestamp(skb);
1940 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1942 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
1943 netif_stop_subqueue(dev, queue_index);
1946 spin_unlock_irqrestore(&bp->lock, flags);
1951 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1953 if (!macb_is_gem(bp)) {
1954 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1956 bp->rx_buffer_size = size;
1958 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1960 "RX buffer must be multiple of %d bytes, expanding\n",
1961 RX_BUFFER_MULTIPLE);
1962 bp->rx_buffer_size =
1963 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1967 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
1968 bp->dev->mtu, bp->rx_buffer_size);
1971 static void gem_free_rx_buffers(struct macb *bp)
1973 struct sk_buff *skb;
1974 struct macb_dma_desc *desc;
1975 struct macb_queue *queue;
1980 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1981 if (!queue->rx_skbuff)
1984 for (i = 0; i < bp->rx_ring_size; i++) {
1985 skb = queue->rx_skbuff[i];
1990 desc = macb_rx_desc(queue, i);
1991 addr = macb_get_addr(bp, desc);
1993 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1995 dev_kfree_skb_any(skb);
1999 kfree(queue->rx_skbuff);
2000 queue->rx_skbuff = NULL;
2004 static void macb_free_rx_buffers(struct macb *bp)
2006 struct macb_queue *queue = &bp->queues[0];
2008 if (queue->rx_buffers) {
2009 dma_free_coherent(&bp->pdev->dev,
2010 bp->rx_ring_size * bp->rx_buffer_size,
2011 queue->rx_buffers, queue->rx_buffers_dma);
2012 queue->rx_buffers = NULL;
2016 static void macb_free_consistent(struct macb *bp)
2018 struct macb_queue *queue;
2022 bp->macbgem_ops.mog_free_rx_buffers(bp);
2024 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2025 kfree(queue->tx_skb);
2026 queue->tx_skb = NULL;
2027 if (queue->tx_ring) {
2028 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2029 dma_free_coherent(&bp->pdev->dev, size,
2030 queue->tx_ring, queue->tx_ring_dma);
2031 queue->tx_ring = NULL;
2033 if (queue->rx_ring) {
2034 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2035 dma_free_coherent(&bp->pdev->dev, size,
2036 queue->rx_ring, queue->rx_ring_dma);
2037 queue->rx_ring = NULL;
2042 static int gem_alloc_rx_buffers(struct macb *bp)
2044 struct macb_queue *queue;
2048 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2049 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2050 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2051 if (!queue->rx_skbuff)
2055 "Allocated %d RX struct sk_buff entries at %p\n",
2056 bp->rx_ring_size, queue->rx_skbuff);
2061 static int macb_alloc_rx_buffers(struct macb *bp)
2063 struct macb_queue *queue = &bp->queues[0];
2066 size = bp->rx_ring_size * bp->rx_buffer_size;
2067 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2068 &queue->rx_buffers_dma, GFP_KERNEL);
2069 if (!queue->rx_buffers)
2073 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2074 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2078 static int macb_alloc_consistent(struct macb *bp)
2080 struct macb_queue *queue;
2084 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2085 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2086 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2087 &queue->tx_ring_dma,
2089 if (!queue->tx_ring)
2092 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2093 q, size, (unsigned long)queue->tx_ring_dma,
2096 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2097 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2101 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2102 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2103 &queue->rx_ring_dma, GFP_KERNEL);
2104 if (!queue->rx_ring)
2107 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2108 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2110 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2116 macb_free_consistent(bp);
2120 static void gem_init_rings(struct macb *bp)
2122 struct macb_queue *queue;
2123 struct macb_dma_desc *desc = NULL;
2127 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2128 for (i = 0; i < bp->tx_ring_size; i++) {
2129 desc = macb_tx_desc(queue, i);
2130 macb_set_addr(bp, desc, 0);
2131 desc->ctrl = MACB_BIT(TX_USED);
2133 desc->ctrl |= MACB_BIT(TX_WRAP);
2138 queue->rx_prepared_head = 0;
2140 gem_rx_refill(queue);
2145 static void macb_init_rings(struct macb *bp)
2148 struct macb_dma_desc *desc = NULL;
2150 macb_init_rx_ring(&bp->queues[0]);
2152 for (i = 0; i < bp->tx_ring_size; i++) {
2153 desc = macb_tx_desc(&bp->queues[0], i);
2154 macb_set_addr(bp, desc, 0);
2155 desc->ctrl = MACB_BIT(TX_USED);
2157 bp->queues[0].tx_head = 0;
2158 bp->queues[0].tx_tail = 0;
2159 desc->ctrl |= MACB_BIT(TX_WRAP);
2162 static void macb_reset_hw(struct macb *bp)
2164 struct macb_queue *queue;
2166 u32 ctrl = macb_readl(bp, NCR);
2168 /* Disable RX and TX (XXX: Should we halt the transmission
2171 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2173 /* Clear the stats registers (XXX: Update stats first?) */
2174 ctrl |= MACB_BIT(CLRSTAT);
2176 macb_writel(bp, NCR, ctrl);
2178 /* Clear all status flags */
2179 macb_writel(bp, TSR, -1);
2180 macb_writel(bp, RSR, -1);
2182 /* Disable all interrupts */
2183 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2184 queue_writel(queue, IDR, -1);
2185 queue_readl(queue, ISR);
2186 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2187 queue_writel(queue, ISR, -1);
2191 static u32 gem_mdc_clk_div(struct macb *bp)
2194 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2196 if (pclk_hz <= 20000000)
2197 config = GEM_BF(CLK, GEM_CLK_DIV8);
2198 else if (pclk_hz <= 40000000)
2199 config = GEM_BF(CLK, GEM_CLK_DIV16);
2200 else if (pclk_hz <= 80000000)
2201 config = GEM_BF(CLK, GEM_CLK_DIV32);
2202 else if (pclk_hz <= 120000000)
2203 config = GEM_BF(CLK, GEM_CLK_DIV48);
2204 else if (pclk_hz <= 160000000)
2205 config = GEM_BF(CLK, GEM_CLK_DIV64);
2207 config = GEM_BF(CLK, GEM_CLK_DIV96);
2212 static u32 macb_mdc_clk_div(struct macb *bp)
2215 unsigned long pclk_hz;
2217 if (macb_is_gem(bp))
2218 return gem_mdc_clk_div(bp);
2220 pclk_hz = clk_get_rate(bp->pclk);
2221 if (pclk_hz <= 20000000)
2222 config = MACB_BF(CLK, MACB_CLK_DIV8);
2223 else if (pclk_hz <= 40000000)
2224 config = MACB_BF(CLK, MACB_CLK_DIV16);
2225 else if (pclk_hz <= 80000000)
2226 config = MACB_BF(CLK, MACB_CLK_DIV32);
2228 config = MACB_BF(CLK, MACB_CLK_DIV64);
2233 /* Get the DMA bus width field of the network configuration register that we
2234 * should program. We find the width from decoding the design configuration
2235 * register to find the maximum supported data bus width.
2237 static u32 macb_dbw(struct macb *bp)
2239 if (!macb_is_gem(bp))
2242 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2244 return GEM_BF(DBW, GEM_DBW128);
2246 return GEM_BF(DBW, GEM_DBW64);
2249 return GEM_BF(DBW, GEM_DBW32);
2253 /* Configure the receive DMA engine
2254 * - use the correct receive buffer size
2255 * - set best burst length for DMA operations
2256 * (if not supported by FIFO, it will fallback to default)
2257 * - set both rx/tx packet buffers to full memory size
2258 * These are configurable parameters for GEM.
2260 static void macb_configure_dma(struct macb *bp)
2262 struct macb_queue *queue;
2267 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2268 if (macb_is_gem(bp)) {
2269 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2270 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2272 queue_writel(queue, RBQS, buffer_size);
2274 dmacfg |= GEM_BF(RXBS, buffer_size);
2276 if (bp->dma_burst_length)
2277 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2278 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2279 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2282 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2284 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2286 if (bp->dev->features & NETIF_F_HW_CSUM)
2287 dmacfg |= GEM_BIT(TXCOEN);
2289 dmacfg &= ~GEM_BIT(TXCOEN);
2291 dmacfg &= ~GEM_BIT(ADDR64);
2292 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2293 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2294 dmacfg |= GEM_BIT(ADDR64);
2296 #ifdef CONFIG_MACB_USE_HWSTAMP
2297 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2298 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2300 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2302 gem_writel(bp, DMACFG, dmacfg);
2306 static void macb_init_hw(struct macb *bp)
2311 macb_set_hwaddr(bp);
2313 config = macb_mdc_clk_div(bp);
2314 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2315 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2316 if (bp->caps & MACB_CAPS_JUMBO)
2317 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2319 config |= MACB_BIT(BIG); /* Receive oversized frames */
2320 if (bp->dev->flags & IFF_PROMISC)
2321 config |= MACB_BIT(CAF); /* Copy All Frames */
2322 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2323 config |= GEM_BIT(RXCOEN);
2324 if (!(bp->dev->flags & IFF_BROADCAST))
2325 config |= MACB_BIT(NBC); /* No BroadCast */
2326 config |= macb_dbw(bp);
2327 macb_writel(bp, NCFGR, config);
2328 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2329 gem_writel(bp, JML, bp->jumbo_max_len);
2330 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2331 if (bp->caps & MACB_CAPS_JUMBO)
2332 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2334 macb_configure_dma(bp);
2337 /* The hash address register is 64 bits long and takes up two
2338 * locations in the memory map. The least significant bits are stored
2339 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2341 * The unicast hash enable and the multicast hash enable bits in the
2342 * network configuration register enable the reception of hash matched
2343 * frames. The destination address is reduced to a 6 bit index into
2344 * the 64 bit hash register using the following hash function. The
2345 * hash function is an exclusive or of every sixth bit of the
2346 * destination address.
2348 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2349 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2350 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2351 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2352 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2353 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2355 * da[0] represents the least significant bit of the first byte
2356 * received, that is, the multicast/unicast indicator, and da[47]
2357 * represents the most significant bit of the last byte received. If
2358 * the hash index, hi[n], points to a bit that is set in the hash
2359 * register then the frame will be matched according to whether the
2360 * frame is multicast or unicast. A multicast match will be signalled
2361 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2362 * index points to a bit set in the hash register. A unicast match
2363 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2364 * and the hash index points to a bit set in the hash register. To
2365 * receive all multicast frames, the hash register should be set with
2366 * all ones and the multicast hash enable bit should be set in the
2367 * network configuration register.
2370 static inline int hash_bit_value(int bitnr, __u8 *addr)
2372 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2377 /* Return the hash index value for the specified address. */
2378 static int hash_get_index(__u8 *addr)
2383 for (j = 0; j < 6; j++) {
2384 for (i = 0, bitval = 0; i < 8; i++)
2385 bitval ^= hash_bit_value(i * 6 + j, addr);
2387 hash_index |= (bitval << j);
2393 /* Add multicast addresses to the internal multicast-hash table. */
2394 static void macb_sethashtable(struct net_device *dev)
2396 struct netdev_hw_addr *ha;
2397 unsigned long mc_filter[2];
2399 struct macb *bp = netdev_priv(dev);
2404 netdev_for_each_mc_addr(ha, dev) {
2405 bitnr = hash_get_index(ha->addr);
2406 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2409 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2410 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2413 /* Enable/Disable promiscuous and multicast modes. */
2414 static void macb_set_rx_mode(struct net_device *dev)
2417 struct macb *bp = netdev_priv(dev);
2419 cfg = macb_readl(bp, NCFGR);
2421 if (dev->flags & IFF_PROMISC) {
2422 /* Enable promiscuous mode */
2423 cfg |= MACB_BIT(CAF);
2425 /* Disable RX checksum offload */
2426 if (macb_is_gem(bp))
2427 cfg &= ~GEM_BIT(RXCOEN);
2429 /* Disable promiscuous mode */
2430 cfg &= ~MACB_BIT(CAF);
2432 /* Enable RX checksum offload only if requested */
2433 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2434 cfg |= GEM_BIT(RXCOEN);
2437 if (dev->flags & IFF_ALLMULTI) {
2438 /* Enable all multicast mode */
2439 macb_or_gem_writel(bp, HRB, -1);
2440 macb_or_gem_writel(bp, HRT, -1);
2441 cfg |= MACB_BIT(NCFGR_MTI);
2442 } else if (!netdev_mc_empty(dev)) {
2443 /* Enable specific multicasts */
2444 macb_sethashtable(dev);
2445 cfg |= MACB_BIT(NCFGR_MTI);
2446 } else if (dev->flags & (~IFF_ALLMULTI)) {
2447 /* Disable all multicast mode */
2448 macb_or_gem_writel(bp, HRB, 0);
2449 macb_or_gem_writel(bp, HRT, 0);
2450 cfg &= ~MACB_BIT(NCFGR_MTI);
2453 macb_writel(bp, NCFGR, cfg);
2456 static int macb_open(struct net_device *dev)
2458 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2459 struct macb *bp = netdev_priv(dev);
2460 struct macb_queue *queue;
2464 netdev_dbg(bp->dev, "open\n");
2466 err = pm_runtime_get_sync(&bp->pdev->dev);
2470 /* RX buffers initialization */
2471 macb_init_rx_buffer_size(bp, bufsz);
2473 err = macb_alloc_consistent(bp);
2475 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2480 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2481 napi_enable(&queue->napi);
2485 err = macb_phylink_connect(bp);
2489 netif_tx_start_all_queues(dev);
2492 bp->ptp_info->ptp_init(dev);
2496 pm_runtime_put_sync(&bp->pdev->dev);
2502 static int macb_close(struct net_device *dev)
2504 struct macb *bp = netdev_priv(dev);
2505 struct macb_queue *queue;
2506 unsigned long flags;
2509 netif_tx_stop_all_queues(dev);
2511 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2512 napi_disable(&queue->napi);
2514 phylink_stop(bp->phylink);
2515 phylink_disconnect_phy(bp->phylink);
2517 spin_lock_irqsave(&bp->lock, flags);
2519 netif_carrier_off(dev);
2520 spin_unlock_irqrestore(&bp->lock, flags);
2522 macb_free_consistent(bp);
2525 bp->ptp_info->ptp_remove(dev);
2527 pm_runtime_put(&bp->pdev->dev);
2532 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2534 if (netif_running(dev))
2542 static void gem_update_stats(struct macb *bp)
2544 struct macb_queue *queue;
2545 unsigned int i, q, idx;
2546 unsigned long *stat;
2548 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2550 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2551 u32 offset = gem_statistics[i].offset;
2552 u64 val = bp->macb_reg_readl(bp, offset);
2554 bp->ethtool_stats[i] += val;
2557 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2558 /* Add GEM_OCTTXH, GEM_OCTRXH */
2559 val = bp->macb_reg_readl(bp, offset + 4);
2560 bp->ethtool_stats[i] += ((u64)val) << 32;
2565 idx = GEM_STATS_LEN;
2566 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2567 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2568 bp->ethtool_stats[idx++] = *stat;
2571 static struct net_device_stats *gem_get_stats(struct macb *bp)
2573 struct gem_stats *hwstat = &bp->hw_stats.gem;
2574 struct net_device_stats *nstat = &bp->dev->stats;
2576 gem_update_stats(bp);
2578 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2579 hwstat->rx_alignment_errors +
2580 hwstat->rx_resource_errors +
2581 hwstat->rx_overruns +
2582 hwstat->rx_oversize_frames +
2583 hwstat->rx_jabbers +
2584 hwstat->rx_undersized_frames +
2585 hwstat->rx_length_field_frame_errors);
2586 nstat->tx_errors = (hwstat->tx_late_collisions +
2587 hwstat->tx_excessive_collisions +
2588 hwstat->tx_underrun +
2589 hwstat->tx_carrier_sense_errors);
2590 nstat->multicast = hwstat->rx_multicast_frames;
2591 nstat->collisions = (hwstat->tx_single_collision_frames +
2592 hwstat->tx_multiple_collision_frames +
2593 hwstat->tx_excessive_collisions);
2594 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
2595 hwstat->rx_jabbers +
2596 hwstat->rx_undersized_frames +
2597 hwstat->rx_length_field_frame_errors);
2598 nstat->rx_over_errors = hwstat->rx_resource_errors;
2599 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
2600 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
2601 nstat->rx_fifo_errors = hwstat->rx_overruns;
2602 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
2603 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
2604 nstat->tx_fifo_errors = hwstat->tx_underrun;
2609 static void gem_get_ethtool_stats(struct net_device *dev,
2610 struct ethtool_stats *stats, u64 *data)
2614 bp = netdev_priv(dev);
2615 gem_update_stats(bp);
2616 memcpy(data, &bp->ethtool_stats, sizeof(u64)
2617 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
2620 static int gem_get_sset_count(struct net_device *dev, int sset)
2622 struct macb *bp = netdev_priv(dev);
2626 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
2632 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
2634 char stat_string[ETH_GSTRING_LEN];
2635 struct macb *bp = netdev_priv(dev);
2636 struct macb_queue *queue;
2642 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
2643 memcpy(p, gem_statistics[i].stat_string,
2646 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2647 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
2648 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
2649 q, queue_statistics[i].stat_string);
2650 memcpy(p, stat_string, ETH_GSTRING_LEN);
2657 static struct net_device_stats *macb_get_stats(struct net_device *dev)
2659 struct macb *bp = netdev_priv(dev);
2660 struct net_device_stats *nstat = &bp->dev->stats;
2661 struct macb_stats *hwstat = &bp->hw_stats.macb;
2663 if (macb_is_gem(bp))
2664 return gem_get_stats(bp);
2666 /* read stats from hardware */
2667 macb_update_stats(bp);
2669 /* Convert HW stats into netdevice stats */
2670 nstat->rx_errors = (hwstat->rx_fcs_errors +
2671 hwstat->rx_align_errors +
2672 hwstat->rx_resource_errors +
2673 hwstat->rx_overruns +
2674 hwstat->rx_oversize_pkts +
2675 hwstat->rx_jabbers +
2676 hwstat->rx_undersize_pkts +
2677 hwstat->rx_length_mismatch);
2678 nstat->tx_errors = (hwstat->tx_late_cols +
2679 hwstat->tx_excessive_cols +
2680 hwstat->tx_underruns +
2681 hwstat->tx_carrier_errors +
2682 hwstat->sqe_test_errors);
2683 nstat->collisions = (hwstat->tx_single_cols +
2684 hwstat->tx_multiple_cols +
2685 hwstat->tx_excessive_cols);
2686 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
2687 hwstat->rx_jabbers +
2688 hwstat->rx_undersize_pkts +
2689 hwstat->rx_length_mismatch);
2690 nstat->rx_over_errors = hwstat->rx_resource_errors +
2691 hwstat->rx_overruns;
2692 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
2693 nstat->rx_frame_errors = hwstat->rx_align_errors;
2694 nstat->rx_fifo_errors = hwstat->rx_overruns;
2695 /* XXX: What does "missed" mean? */
2696 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
2697 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
2698 nstat->tx_fifo_errors = hwstat->tx_underruns;
2699 /* Don't know about heartbeat or window errors... */
2704 static int macb_get_regs_len(struct net_device *netdev)
2706 return MACB_GREGS_NBR * sizeof(u32);
2709 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2712 struct macb *bp = netdev_priv(dev);
2713 unsigned int tail, head;
2716 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2717 | MACB_GREGS_VERSION;
2719 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
2720 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
2722 regs_buff[0] = macb_readl(bp, NCR);
2723 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2724 regs_buff[2] = macb_readl(bp, NSR);
2725 regs_buff[3] = macb_readl(bp, TSR);
2726 regs_buff[4] = macb_readl(bp, RBQP);
2727 regs_buff[5] = macb_readl(bp, TBQP);
2728 regs_buff[6] = macb_readl(bp, RSR);
2729 regs_buff[7] = macb_readl(bp, IMR);
2731 regs_buff[8] = tail;
2732 regs_buff[9] = head;
2733 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2734 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2736 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
2737 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2738 if (macb_is_gem(bp))
2739 regs_buff[13] = gem_readl(bp, DMACFG);
2742 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2744 struct macb *bp = netdev_priv(netdev);
2749 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET)
2750 phylink_ethtool_get_wol(bp->phylink, wol);
2753 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2755 struct macb *bp = netdev_priv(netdev);
2758 ret = phylink_ethtool_set_wol(bp->phylink, wol);
2762 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
2763 (wol->wolopts & ~WAKE_MAGIC))
2766 if (wol->wolopts & WAKE_MAGIC)
2767 bp->wol |= MACB_WOL_ENABLED;
2769 bp->wol &= ~MACB_WOL_ENABLED;
2771 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
2776 static int macb_get_link_ksettings(struct net_device *netdev,
2777 struct ethtool_link_ksettings *kset)
2779 struct macb *bp = netdev_priv(netdev);
2781 return phylink_ethtool_ksettings_get(bp->phylink, kset);
2784 static int macb_set_link_ksettings(struct net_device *netdev,
2785 const struct ethtool_link_ksettings *kset)
2787 struct macb *bp = netdev_priv(netdev);
2789 return phylink_ethtool_ksettings_set(bp->phylink, kset);
2792 static void macb_get_ringparam(struct net_device *netdev,
2793 struct ethtool_ringparam *ring)
2795 struct macb *bp = netdev_priv(netdev);
2797 ring->rx_max_pending = MAX_RX_RING_SIZE;
2798 ring->tx_max_pending = MAX_TX_RING_SIZE;
2800 ring->rx_pending = bp->rx_ring_size;
2801 ring->tx_pending = bp->tx_ring_size;
2804 static int macb_set_ringparam(struct net_device *netdev,
2805 struct ethtool_ringparam *ring)
2807 struct macb *bp = netdev_priv(netdev);
2808 u32 new_rx_size, new_tx_size;
2809 unsigned int reset = 0;
2811 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2814 new_rx_size = clamp_t(u32, ring->rx_pending,
2815 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
2816 new_rx_size = roundup_pow_of_two(new_rx_size);
2818 new_tx_size = clamp_t(u32, ring->tx_pending,
2819 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
2820 new_tx_size = roundup_pow_of_two(new_tx_size);
2822 if ((new_tx_size == bp->tx_ring_size) &&
2823 (new_rx_size == bp->rx_ring_size)) {
2828 if (netif_running(bp->dev)) {
2830 macb_close(bp->dev);
2833 bp->rx_ring_size = new_rx_size;
2834 bp->tx_ring_size = new_tx_size;
2842 #ifdef CONFIG_MACB_USE_HWSTAMP
2843 static unsigned int gem_get_tsu_rate(struct macb *bp)
2845 struct clk *tsu_clk;
2846 unsigned int tsu_rate;
2848 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
2849 if (!IS_ERR(tsu_clk))
2850 tsu_rate = clk_get_rate(tsu_clk);
2851 /* try pclk instead */
2852 else if (!IS_ERR(bp->pclk)) {
2854 tsu_rate = clk_get_rate(tsu_clk);
2860 static s32 gem_get_ptp_max_adj(void)
2865 static int gem_get_ts_info(struct net_device *dev,
2866 struct ethtool_ts_info *info)
2868 struct macb *bp = netdev_priv(dev);
2870 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
2871 ethtool_op_get_ts_info(dev, info);
2875 info->so_timestamping =
2876 SOF_TIMESTAMPING_TX_SOFTWARE |
2877 SOF_TIMESTAMPING_RX_SOFTWARE |
2878 SOF_TIMESTAMPING_SOFTWARE |
2879 SOF_TIMESTAMPING_TX_HARDWARE |
2880 SOF_TIMESTAMPING_RX_HARDWARE |
2881 SOF_TIMESTAMPING_RAW_HARDWARE;
2883 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
2884 (1 << HWTSTAMP_TX_OFF) |
2885 (1 << HWTSTAMP_TX_ON);
2887 (1 << HWTSTAMP_FILTER_NONE) |
2888 (1 << HWTSTAMP_FILTER_ALL);
2890 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
2895 static struct macb_ptp_info gem_ptp_info = {
2896 .ptp_init = gem_ptp_init,
2897 .ptp_remove = gem_ptp_remove,
2898 .get_ptp_max_adj = gem_get_ptp_max_adj,
2899 .get_tsu_rate = gem_get_tsu_rate,
2900 .get_ts_info = gem_get_ts_info,
2901 .get_hwtst = gem_get_hwtst,
2902 .set_hwtst = gem_set_hwtst,
2906 static int macb_get_ts_info(struct net_device *netdev,
2907 struct ethtool_ts_info *info)
2909 struct macb *bp = netdev_priv(netdev);
2912 return bp->ptp_info->get_ts_info(netdev, info);
2914 return ethtool_op_get_ts_info(netdev, info);
2917 static void gem_enable_flow_filters(struct macb *bp, bool enable)
2919 struct net_device *netdev = bp->dev;
2920 struct ethtool_rx_fs_item *item;
2924 if (!(netdev->features & NETIF_F_NTUPLE))
2927 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
2929 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
2930 struct ethtool_rx_flow_spec *fs = &item->fs;
2931 struct ethtool_tcpip4_spec *tp4sp_m;
2933 if (fs->location >= num_t2_scr)
2936 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
2938 /* enable/disable screener regs for the flow entry */
2939 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
2941 /* only enable fields with no masking */
2942 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2944 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
2945 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
2947 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
2949 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
2950 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
2952 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
2954 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
2955 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
2957 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
2959 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
2963 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
2965 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
2966 uint16_t index = fs->location;
2972 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
2973 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
2975 /* ignore field if any masking set */
2976 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
2977 /* 1st compare reg - IP source address */
2980 w0 = tp4sp_v->ip4src;
2981 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2982 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
2983 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
2984 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
2985 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
2989 /* ignore field if any masking set */
2990 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
2991 /* 2nd compare reg - IP destination address */
2994 w0 = tp4sp_v->ip4dst;
2995 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
2996 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
2997 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
2998 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
2999 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3003 /* ignore both port fields if masking set in both */
3004 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3005 /* 3rd compare reg - source port, destination port */
3008 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3009 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3010 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3011 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3012 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3013 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3015 /* only one port definition */
3016 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3017 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3018 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3019 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3020 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3021 } else { /* dst port */
3022 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3023 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3026 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3027 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3032 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3033 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3035 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3037 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3039 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3040 gem_writel_n(bp, SCRT2, index, t2_scr);
3043 static int gem_add_flow_filter(struct net_device *netdev,
3044 struct ethtool_rxnfc *cmd)
3046 struct macb *bp = netdev_priv(netdev);
3047 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3048 struct ethtool_rx_fs_item *item, *newfs;
3049 unsigned long flags;
3053 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3056 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3059 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3060 fs->flow_type, (int)fs->ring_cookie, fs->location,
3061 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3062 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3063 htons(fs->h_u.tcp_ip4_spec.psrc), htons(fs->h_u.tcp_ip4_spec.pdst));
3065 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3067 /* find correct place to add in list */
3068 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3069 if (item->fs.location > newfs->fs.location) {
3070 list_add_tail(&newfs->list, &item->list);
3073 } else if (item->fs.location == fs->location) {
3074 netdev_err(netdev, "Rule not added: location %d not free!\n",
3081 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3083 gem_prog_cmp_regs(bp, fs);
3084 bp->rx_fs_list.count++;
3085 /* enable filtering if NTUPLE on */
3086 gem_enable_flow_filters(bp, 1);
3088 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3092 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3097 static int gem_del_flow_filter(struct net_device *netdev,
3098 struct ethtool_rxnfc *cmd)
3100 struct macb *bp = netdev_priv(netdev);
3101 struct ethtool_rx_fs_item *item;
3102 struct ethtool_rx_flow_spec *fs;
3103 unsigned long flags;
3105 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3107 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3108 if (item->fs.location == cmd->fs.location) {
3109 /* disable screener regs for the flow entry */
3112 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3113 fs->flow_type, (int)fs->ring_cookie, fs->location,
3114 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3115 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3116 htons(fs->h_u.tcp_ip4_spec.psrc),
3117 htons(fs->h_u.tcp_ip4_spec.pdst));
3119 gem_writel_n(bp, SCRT2, fs->location, 0);
3121 list_del(&item->list);
3122 bp->rx_fs_list.count--;
3123 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3129 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3133 static int gem_get_flow_entry(struct net_device *netdev,
3134 struct ethtool_rxnfc *cmd)
3136 struct macb *bp = netdev_priv(netdev);
3137 struct ethtool_rx_fs_item *item;
3139 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3140 if (item->fs.location == cmd->fs.location) {
3141 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3148 static int gem_get_all_flow_entries(struct net_device *netdev,
3149 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3151 struct macb *bp = netdev_priv(netdev);
3152 struct ethtool_rx_fs_item *item;
3155 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3156 if (cnt == cmd->rule_cnt)
3158 rule_locs[cnt] = item->fs.location;
3161 cmd->data = bp->max_tuples;
3162 cmd->rule_cnt = cnt;
3167 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3170 struct macb *bp = netdev_priv(netdev);
3174 case ETHTOOL_GRXRINGS:
3175 cmd->data = bp->num_queues;
3177 case ETHTOOL_GRXCLSRLCNT:
3178 cmd->rule_cnt = bp->rx_fs_list.count;
3180 case ETHTOOL_GRXCLSRULE:
3181 ret = gem_get_flow_entry(netdev, cmd);
3183 case ETHTOOL_GRXCLSRLALL:
3184 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3188 "Command parameter %d is not supported\n", cmd->cmd);
3195 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3197 struct macb *bp = netdev_priv(netdev);
3201 case ETHTOOL_SRXCLSRLINS:
3202 if ((cmd->fs.location >= bp->max_tuples)
3203 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3207 ret = gem_add_flow_filter(netdev, cmd);
3209 case ETHTOOL_SRXCLSRLDEL:
3210 ret = gem_del_flow_filter(netdev, cmd);
3214 "Command parameter %d is not supported\n", cmd->cmd);
3221 static const struct ethtool_ops macb_ethtool_ops = {
3222 .get_regs_len = macb_get_regs_len,
3223 .get_regs = macb_get_regs,
3224 .get_link = ethtool_op_get_link,
3225 .get_ts_info = ethtool_op_get_ts_info,
3226 .get_wol = macb_get_wol,
3227 .set_wol = macb_set_wol,
3228 .get_link_ksettings = macb_get_link_ksettings,
3229 .set_link_ksettings = macb_set_link_ksettings,
3230 .get_ringparam = macb_get_ringparam,
3231 .set_ringparam = macb_set_ringparam,
3234 static const struct ethtool_ops gem_ethtool_ops = {
3235 .get_regs_len = macb_get_regs_len,
3236 .get_regs = macb_get_regs,
3237 .get_link = ethtool_op_get_link,
3238 .get_ts_info = macb_get_ts_info,
3239 .get_ethtool_stats = gem_get_ethtool_stats,
3240 .get_strings = gem_get_ethtool_strings,
3241 .get_sset_count = gem_get_sset_count,
3242 .get_link_ksettings = macb_get_link_ksettings,
3243 .set_link_ksettings = macb_set_link_ksettings,
3244 .get_ringparam = macb_get_ringparam,
3245 .set_ringparam = macb_set_ringparam,
3246 .get_rxnfc = gem_get_rxnfc,
3247 .set_rxnfc = gem_set_rxnfc,
3250 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3252 struct macb *bp = netdev_priv(dev);
3254 if (!netif_running(dev))
3260 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3262 return bp->ptp_info->get_hwtst(dev, rq);
3266 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3269 static inline void macb_set_txcsum_feature(struct macb *bp,
3270 netdev_features_t features)
3274 if (!macb_is_gem(bp))
3277 val = gem_readl(bp, DMACFG);
3278 if (features & NETIF_F_HW_CSUM)
3279 val |= GEM_BIT(TXCOEN);
3281 val &= ~GEM_BIT(TXCOEN);
3283 gem_writel(bp, DMACFG, val);
3286 static inline void macb_set_rxcsum_feature(struct macb *bp,
3287 netdev_features_t features)
3289 struct net_device *netdev = bp->dev;
3292 if (!macb_is_gem(bp))
3295 val = gem_readl(bp, NCFGR);
3296 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3297 val |= GEM_BIT(RXCOEN);
3299 val &= ~GEM_BIT(RXCOEN);
3301 gem_writel(bp, NCFGR, val);
3304 static inline void macb_set_rxflow_feature(struct macb *bp,
3305 netdev_features_t features)
3307 if (!macb_is_gem(bp))
3310 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3313 static int macb_set_features(struct net_device *netdev,
3314 netdev_features_t features)
3316 struct macb *bp = netdev_priv(netdev);
3317 netdev_features_t changed = features ^ netdev->features;
3319 /* TX checksum offload */
3320 if (changed & NETIF_F_HW_CSUM)
3321 macb_set_txcsum_feature(bp, features);
3323 /* RX checksum offload */
3324 if (changed & NETIF_F_RXCSUM)
3325 macb_set_rxcsum_feature(bp, features);
3327 /* RX Flow Filters */
3328 if (changed & NETIF_F_NTUPLE)
3329 macb_set_rxflow_feature(bp, features);
3334 static void macb_restore_features(struct macb *bp)
3336 struct net_device *netdev = bp->dev;
3337 netdev_features_t features = netdev->features;
3339 /* TX checksum offload */
3340 macb_set_txcsum_feature(bp, features);
3342 /* RX checksum offload */
3343 macb_set_rxcsum_feature(bp, features);
3345 /* RX Flow Filters */
3346 macb_set_rxflow_feature(bp, features);
3349 static const struct net_device_ops macb_netdev_ops = {
3350 .ndo_open = macb_open,
3351 .ndo_stop = macb_close,
3352 .ndo_start_xmit = macb_start_xmit,
3353 .ndo_set_rx_mode = macb_set_rx_mode,
3354 .ndo_get_stats = macb_get_stats,
3355 .ndo_do_ioctl = macb_ioctl,
3356 .ndo_validate_addr = eth_validate_addr,
3357 .ndo_change_mtu = macb_change_mtu,
3358 .ndo_set_mac_address = eth_mac_addr,
3359 #ifdef CONFIG_NET_POLL_CONTROLLER
3360 .ndo_poll_controller = macb_poll_controller,
3362 .ndo_set_features = macb_set_features,
3363 .ndo_features_check = macb_features_check,
3366 /* Configure peripheral capabilities according to device tree
3367 * and integration options used
3369 static void macb_configure_caps(struct macb *bp,
3370 const struct macb_config *dt_conf)
3375 bp->caps = dt_conf->caps;
3377 if (hw_is_gem(bp->regs, bp->native_io)) {
3378 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3380 dcfg = gem_readl(bp, DCFG1);
3381 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3382 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3383 dcfg = gem_readl(bp, DCFG2);
3384 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3385 bp->caps |= MACB_CAPS_FIFO_MODE;
3386 #ifdef CONFIG_MACB_USE_HWSTAMP
3387 if (gem_has_ptp(bp)) {
3388 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3389 dev_err(&bp->pdev->dev,
3390 "GEM doesn't support hardware ptp.\n");
3392 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3393 bp->ptp_info = &gem_ptp_info;
3399 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3402 static void macb_probe_queues(void __iomem *mem,
3404 unsigned int *queue_mask,
3405 unsigned int *num_queues)
3412 /* is it macb or gem ?
3414 * We need to read directly from the hardware here because
3415 * we are early in the probe process and don't have the
3416 * MACB_CAPS_MACB_IS_GEM flag positioned
3418 if (!hw_is_gem(mem, native_io))
3421 /* bit 0 is never set but queue 0 always exists */
3422 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
3426 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
3427 if (*queue_mask & (1 << hw_q))
3431 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3432 struct clk **hclk, struct clk **tx_clk,
3433 struct clk **rx_clk, struct clk **tsu_clk)
3435 struct macb_platform_data *pdata;
3438 pdata = dev_get_platdata(&pdev->dev);
3440 *pclk = pdata->pclk;
3441 *hclk = pdata->hclk;
3443 *pclk = devm_clk_get(&pdev->dev, "pclk");
3444 *hclk = devm_clk_get(&pdev->dev, "hclk");
3447 if (IS_ERR_OR_NULL(*pclk)) {
3448 err = PTR_ERR(*pclk);
3452 dev_err(&pdev->dev, "failed to get macb_clk (%d)\n", err);
3456 if (IS_ERR_OR_NULL(*hclk)) {
3457 err = PTR_ERR(*hclk);
3461 dev_err(&pdev->dev, "failed to get hclk (%d)\n", err);
3465 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
3466 if (IS_ERR(*tx_clk))
3467 return PTR_ERR(*tx_clk);
3469 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
3470 if (IS_ERR(*rx_clk))
3471 return PTR_ERR(*rx_clk);
3473 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
3474 if (IS_ERR(*tsu_clk))
3475 return PTR_ERR(*tsu_clk);
3477 err = clk_prepare_enable(*pclk);
3479 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3483 err = clk_prepare_enable(*hclk);
3485 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3486 goto err_disable_pclk;
3489 err = clk_prepare_enable(*tx_clk);
3491 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3492 goto err_disable_hclk;
3495 err = clk_prepare_enable(*rx_clk);
3497 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3498 goto err_disable_txclk;
3501 err = clk_prepare_enable(*tsu_clk);
3503 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
3504 goto err_disable_rxclk;
3510 clk_disable_unprepare(*rx_clk);
3513 clk_disable_unprepare(*tx_clk);
3516 clk_disable_unprepare(*hclk);
3519 clk_disable_unprepare(*pclk);
3524 static int macb_init(struct platform_device *pdev)
3526 struct net_device *dev = platform_get_drvdata(pdev);
3527 unsigned int hw_q, q;
3528 struct macb *bp = netdev_priv(dev);
3529 struct macb_queue *queue;
3533 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3534 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3536 /* set the queue register mapping once for all: queue0 has a special
3537 * register mapping but we don't want to test the queue index then
3538 * compute the corresponding register offset at run time.
3540 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3541 if (!(bp->queue_mask & (1 << hw_q)))
3544 queue = &bp->queues[q];
3546 netif_napi_add(dev, &queue->napi, macb_poll, NAPI_POLL_WEIGHT);
3548 queue->ISR = GEM_ISR(hw_q - 1);
3549 queue->IER = GEM_IER(hw_q - 1);
3550 queue->IDR = GEM_IDR(hw_q - 1);
3551 queue->IMR = GEM_IMR(hw_q - 1);
3552 queue->TBQP = GEM_TBQP(hw_q - 1);
3553 queue->RBQP = GEM_RBQP(hw_q - 1);
3554 queue->RBQS = GEM_RBQS(hw_q - 1);
3555 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3556 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3557 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3558 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3562 /* queue0 uses legacy registers */
3563 queue->ISR = MACB_ISR;
3564 queue->IER = MACB_IER;
3565 queue->IDR = MACB_IDR;
3566 queue->IMR = MACB_IMR;
3567 queue->TBQP = MACB_TBQP;
3568 queue->RBQP = MACB_RBQP;
3569 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3570 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3571 queue->TBQPH = MACB_TBQPH;
3572 queue->RBQPH = MACB_RBQPH;
3577 /* get irq: here we use the linux queue index, not the hardware
3578 * queue index. the queue irq definitions in the device tree
3579 * must remove the optional gaps that could exist in the
3580 * hardware queue mask.
3582 queue->irq = platform_get_irq(pdev, q);
3583 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
3584 IRQF_SHARED, dev->name, queue);
3587 "Unable to request IRQ %d (error %d)\n",
3592 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
3596 dev->netdev_ops = &macb_netdev_ops;
3598 /* setup appropriated routines according to adapter type */
3599 if (macb_is_gem(bp)) {
3600 bp->max_tx_length = GEM_MAX_TX_LEN;
3601 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
3602 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
3603 bp->macbgem_ops.mog_init_rings = gem_init_rings;
3604 bp->macbgem_ops.mog_rx = gem_rx;
3605 dev->ethtool_ops = &gem_ethtool_ops;
3607 bp->max_tx_length = MACB_MAX_TX_LEN;
3608 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
3609 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
3610 bp->macbgem_ops.mog_init_rings = macb_init_rings;
3611 bp->macbgem_ops.mog_rx = macb_rx;
3612 dev->ethtool_ops = &macb_ethtool_ops;
3616 dev->hw_features = NETIF_F_SG;
3618 /* Check LSO capability */
3619 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
3620 dev->hw_features |= MACB_NETIF_LSO;
3622 /* Checksum offload is only available on gem with packet buffer */
3623 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
3624 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
3625 if (bp->caps & MACB_CAPS_SG_DISABLED)
3626 dev->hw_features &= ~NETIF_F_SG;
3627 dev->features = dev->hw_features;
3629 /* Check RX Flow Filters support.
3630 * Max Rx flows set by availability of screeners & compare regs:
3631 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
3633 reg = gem_readl(bp, DCFG8);
3634 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
3635 GEM_BFEXT(T2SCR, reg));
3636 if (bp->max_tuples > 0) {
3637 /* also needs one ethtype match to check IPv4 */
3638 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
3639 /* program this reg now */
3641 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
3642 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
3643 /* Filtering is supported in hw but don't enable it in kernel now */
3644 dev->hw_features |= NETIF_F_NTUPLE;
3645 /* init Rx flow definitions */
3646 INIT_LIST_HEAD(&bp->rx_fs_list.list);
3647 bp->rx_fs_list.count = 0;
3648 spin_lock_init(&bp->rx_fs_lock);
3653 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
3655 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
3656 val = GEM_BIT(RGMII);
3657 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
3658 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3659 val = MACB_BIT(RMII);
3660 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
3661 val = MACB_BIT(MII);
3663 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
3664 val |= MACB_BIT(CLKEN);
3666 macb_or_gem_writel(bp, USRIO, val);
3669 /* Set MII management clock divider */
3670 val = macb_mdc_clk_div(bp);
3671 val |= macb_dbw(bp);
3672 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
3673 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
3674 macb_writel(bp, NCFGR, val);
3679 #if defined(CONFIG_OF)
3680 /* 1518 rounded up */
3681 #define AT91ETHER_MAX_RBUFF_SZ 0x600
3682 /* max number of receive buffers */
3683 #define AT91ETHER_MAX_RX_DESCR 9
3685 static struct sifive_fu540_macb_mgmt *mgmt;
3687 /* Initialize and start the Receiver and Transmit subsystems */
3688 static int at91ether_start(struct net_device *dev)
3690 struct macb *lp = netdev_priv(dev);
3691 struct macb_queue *q = &lp->queues[0];
3692 struct macb_dma_desc *desc;
3697 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
3698 (AT91ETHER_MAX_RX_DESCR *
3699 macb_dma_desc_get_size(lp)),
3700 &q->rx_ring_dma, GFP_KERNEL);
3704 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
3705 AT91ETHER_MAX_RX_DESCR *
3706 AT91ETHER_MAX_RBUFF_SZ,
3707 &q->rx_buffers_dma, GFP_KERNEL);
3708 if (!q->rx_buffers) {
3709 dma_free_coherent(&lp->pdev->dev,
3710 AT91ETHER_MAX_RX_DESCR *
3711 macb_dma_desc_get_size(lp),
3712 q->rx_ring, q->rx_ring_dma);
3717 addr = q->rx_buffers_dma;
3718 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
3719 desc = macb_rx_desc(q, i);
3720 macb_set_addr(lp, desc, addr);
3722 addr += AT91ETHER_MAX_RBUFF_SZ;
3725 /* Set the Wrap bit on the last descriptor */
3726 desc->addr |= MACB_BIT(RX_WRAP);
3728 /* Reset buffer index */
3731 /* Program address of descriptor list in Rx Buffer Queue register */
3732 macb_writel(lp, RBQP, q->rx_ring_dma);
3734 /* Enable Receive and Transmit */
3735 ctl = macb_readl(lp, NCR);
3736 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
3741 /* Open the ethernet interface */
3742 static int at91ether_open(struct net_device *dev)
3744 struct macb *lp = netdev_priv(dev);
3748 /* Clear internal statistics */
3749 ctl = macb_readl(lp, NCR);
3750 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
3752 macb_set_hwaddr(lp);
3754 ret = at91ether_start(dev);
3758 /* Enable MAC interrupts */
3759 macb_writel(lp, IER, MACB_BIT(RCOMP) |
3761 MACB_BIT(ISR_TUND) |
3764 MACB_BIT(ISR_ROVR) |
3767 ret = macb_phylink_connect(lp);
3771 netif_start_queue(dev);
3776 /* Close the interface */
3777 static int at91ether_close(struct net_device *dev)
3779 struct macb *lp = netdev_priv(dev);
3780 struct macb_queue *q = &lp->queues[0];
3783 /* Disable Receiver and Transmitter */
3784 ctl = macb_readl(lp, NCR);
3785 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
3787 /* Disable MAC interrupts */
3788 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
3790 MACB_BIT(ISR_TUND) |
3793 MACB_BIT(ISR_ROVR) |
3796 netif_stop_queue(dev);
3798 phylink_stop(lp->phylink);
3799 phylink_disconnect_phy(lp->phylink);
3801 dma_free_coherent(&lp->pdev->dev,
3802 AT91ETHER_MAX_RX_DESCR *
3803 macb_dma_desc_get_size(lp),
3804 q->rx_ring, q->rx_ring_dma);
3807 dma_free_coherent(&lp->pdev->dev,
3808 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
3809 q->rx_buffers, q->rx_buffers_dma);
3810 q->rx_buffers = NULL;
3815 /* Transmit packet */
3816 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
3817 struct net_device *dev)
3819 struct macb *lp = netdev_priv(dev);
3821 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
3822 netif_stop_queue(dev);
3824 /* Store packet information (to free when Tx completed) */
3826 lp->skb_length = skb->len;
3827 lp->skb_physaddr = dma_map_single(&lp->pdev->dev, skb->data,
3828 skb->len, DMA_TO_DEVICE);
3829 if (dma_mapping_error(&lp->pdev->dev, lp->skb_physaddr)) {
3830 dev_kfree_skb_any(skb);
3831 dev->stats.tx_dropped++;
3832 netdev_err(dev, "%s: DMA mapping error\n", __func__);
3833 return NETDEV_TX_OK;
3836 /* Set address of the data in the Transmit Address register */
3837 macb_writel(lp, TAR, lp->skb_physaddr);
3838 /* Set length of the packet in the Transmit Control register */
3839 macb_writel(lp, TCR, skb->len);
3842 netdev_err(dev, "%s called, but device is busy!\n", __func__);
3843 return NETDEV_TX_BUSY;
3846 return NETDEV_TX_OK;
3849 /* Extract received frame from buffer descriptors and sent to upper layers.
3850 * (Called from interrupt context)
3852 static void at91ether_rx(struct net_device *dev)
3854 struct macb *lp = netdev_priv(dev);
3855 struct macb_queue *q = &lp->queues[0];
3856 struct macb_dma_desc *desc;
3857 unsigned char *p_recv;
3858 struct sk_buff *skb;
3859 unsigned int pktlen;
3861 desc = macb_rx_desc(q, q->rx_tail);
3862 while (desc->addr & MACB_BIT(RX_USED)) {
3863 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
3864 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
3865 skb = netdev_alloc_skb(dev, pktlen + 2);
3867 skb_reserve(skb, 2);
3868 skb_put_data(skb, p_recv, pktlen);
3870 skb->protocol = eth_type_trans(skb, dev);
3871 dev->stats.rx_packets++;
3872 dev->stats.rx_bytes += pktlen;
3875 dev->stats.rx_dropped++;
3878 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
3879 dev->stats.multicast++;
3881 /* reset ownership bit */
3882 desc->addr &= ~MACB_BIT(RX_USED);
3884 /* wrap after last buffer */
3885 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
3890 desc = macb_rx_desc(q, q->rx_tail);
3894 /* MAC interrupt handler */
3895 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
3897 struct net_device *dev = dev_id;
3898 struct macb *lp = netdev_priv(dev);
3901 /* MAC Interrupt Status register indicates what interrupts are pending.
3902 * It is automatically cleared once read.
3904 intstatus = macb_readl(lp, ISR);
3906 /* Receive complete */
3907 if (intstatus & MACB_BIT(RCOMP))
3910 /* Transmit complete */
3911 if (intstatus & MACB_BIT(TCOMP)) {
3912 /* The TCOM bit is set even if the transmission failed */
3913 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
3914 dev->stats.tx_errors++;
3917 dev_consume_skb_irq(lp->skb);
3919 dma_unmap_single(&lp->pdev->dev, lp->skb_physaddr,
3920 lp->skb_length, DMA_TO_DEVICE);
3921 dev->stats.tx_packets++;
3922 dev->stats.tx_bytes += lp->skb_length;
3924 netif_wake_queue(dev);
3927 /* Work-around for EMAC Errata section 41.3.1 */
3928 if (intstatus & MACB_BIT(RXUBR)) {
3929 ctl = macb_readl(lp, NCR);
3930 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
3932 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
3935 if (intstatus & MACB_BIT(ISR_ROVR))
3936 netdev_err(dev, "ROVR error\n");
3941 #ifdef CONFIG_NET_POLL_CONTROLLER
3942 static void at91ether_poll_controller(struct net_device *dev)
3944 unsigned long flags;
3946 local_irq_save(flags);
3947 at91ether_interrupt(dev->irq, dev);
3948 local_irq_restore(flags);
3952 static const struct net_device_ops at91ether_netdev_ops = {
3953 .ndo_open = at91ether_open,
3954 .ndo_stop = at91ether_close,
3955 .ndo_start_xmit = at91ether_start_xmit,
3956 .ndo_get_stats = macb_get_stats,
3957 .ndo_set_rx_mode = macb_set_rx_mode,
3958 .ndo_set_mac_address = eth_mac_addr,
3959 .ndo_do_ioctl = macb_ioctl,
3960 .ndo_validate_addr = eth_validate_addr,
3961 #ifdef CONFIG_NET_POLL_CONTROLLER
3962 .ndo_poll_controller = at91ether_poll_controller,
3966 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
3967 struct clk **hclk, struct clk **tx_clk,
3968 struct clk **rx_clk, struct clk **tsu_clk)
3977 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
3979 return PTR_ERR(*pclk);
3981 err = clk_prepare_enable(*pclk);
3983 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3990 static int at91ether_init(struct platform_device *pdev)
3992 struct net_device *dev = platform_get_drvdata(pdev);
3993 struct macb *bp = netdev_priv(dev);
3997 bp->queues[0].bp = bp;
3999 dev->netdev_ops = &at91ether_netdev_ops;
4000 dev->ethtool_ops = &macb_ethtool_ops;
4002 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4007 macb_writel(bp, NCR, 0);
4009 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
4010 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
4011 reg |= MACB_BIT(RM9200_RMII);
4013 macb_writel(bp, NCFGR, reg);
4018 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4019 unsigned long parent_rate)
4024 static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4025 unsigned long *parent_rate)
4027 if (WARN_ON(rate < 2500000))
4029 else if (rate == 2500000)
4031 else if (WARN_ON(rate < 13750000))
4033 else if (WARN_ON(rate < 25000000))
4035 else if (rate == 25000000)
4037 else if (WARN_ON(rate < 75000000))
4039 else if (WARN_ON(rate < 125000000))
4041 else if (rate == 125000000)
4044 WARN_ON(rate > 125000000);
4049 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4050 unsigned long parent_rate)
4052 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4053 if (rate != 125000000)
4054 iowrite32(1, mgmt->reg);
4056 iowrite32(0, mgmt->reg);
4062 static const struct clk_ops fu540_c000_ops = {
4063 .recalc_rate = fu540_macb_tx_recalc_rate,
4064 .round_rate = fu540_macb_tx_round_rate,
4065 .set_rate = fu540_macb_tx_set_rate,
4068 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4069 struct clk **hclk, struct clk **tx_clk,
4070 struct clk **rx_clk, struct clk **tsu_clk)
4072 struct clk_init_data init;
4075 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4079 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4083 init.name = "sifive-gemgxl-mgmt";
4084 init.ops = &fu540_c000_ops;
4086 init.num_parents = 0;
4089 mgmt->hw.init = &init;
4091 *tx_clk = clk_register(NULL, &mgmt->hw);
4092 if (IS_ERR(*tx_clk))
4093 return PTR_ERR(*tx_clk);
4095 err = clk_prepare_enable(*tx_clk);
4097 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4099 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4104 static int fu540_c000_init(struct platform_device *pdev)
4106 struct resource *res;
4108 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
4112 mgmt->reg = ioremap(res->start, resource_size(res));
4116 return macb_init(pdev);
4119 static const struct macb_config fu540_c000_config = {
4120 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4121 MACB_CAPS_GEM_HAS_PTP,
4122 .dma_burst_length = 16,
4123 .clk_init = fu540_c000_clk_init,
4124 .init = fu540_c000_init,
4125 .jumbo_max_len = 10240,
4128 static const struct macb_config at91sam9260_config = {
4129 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4130 .clk_init = macb_clk_init,
4134 static const struct macb_config sama5d3macb_config = {
4135 .caps = MACB_CAPS_SG_DISABLED
4136 | MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4137 .clk_init = macb_clk_init,
4141 static const struct macb_config pc302gem_config = {
4142 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4143 .dma_burst_length = 16,
4144 .clk_init = macb_clk_init,
4148 static const struct macb_config sama5d2_config = {
4149 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4150 .dma_burst_length = 16,
4151 .clk_init = macb_clk_init,
4155 static const struct macb_config sama5d3_config = {
4156 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE
4157 | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4158 .dma_burst_length = 16,
4159 .clk_init = macb_clk_init,
4161 .jumbo_max_len = 10240,
4164 static const struct macb_config sama5d4_config = {
4165 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4166 .dma_burst_length = 4,
4167 .clk_init = macb_clk_init,
4171 static const struct macb_config emac_config = {
4172 .caps = MACB_CAPS_NEEDS_RSTONUBR,
4173 .clk_init = at91ether_clk_init,
4174 .init = at91ether_init,
4177 static const struct macb_config np4_config = {
4178 .caps = MACB_CAPS_USRIO_DISABLED,
4179 .clk_init = macb_clk_init,
4183 static const struct macb_config zynqmp_config = {
4184 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4186 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4187 .dma_burst_length = 16,
4188 .clk_init = macb_clk_init,
4190 .jumbo_max_len = 10240,
4193 static const struct macb_config zynq_config = {
4194 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4195 MACB_CAPS_NEEDS_RSTONUBR,
4196 .dma_burst_length = 16,
4197 .clk_init = macb_clk_init,
4201 static const struct of_device_id macb_dt_ids[] = {
4202 { .compatible = "cdns,at32ap7000-macb" },
4203 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4204 { .compatible = "cdns,macb" },
4205 { .compatible = "cdns,np4-macb", .data = &np4_config },
4206 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4207 { .compatible = "cdns,gem", .data = &pc302gem_config },
4208 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4209 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4210 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4211 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4212 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4213 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4214 { .compatible = "cdns,emac", .data = &emac_config },
4215 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
4216 { .compatible = "cdns,zynq-gem", .data = &zynq_config },
4217 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4220 MODULE_DEVICE_TABLE(of, macb_dt_ids);
4221 #endif /* CONFIG_OF */
4223 static const struct macb_config default_gem_config = {
4224 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4226 MACB_CAPS_GEM_HAS_PTP,
4227 .dma_burst_length = 16,
4228 .clk_init = macb_clk_init,
4230 .jumbo_max_len = 10240,
4233 static int macb_probe(struct platform_device *pdev)
4235 const struct macb_config *macb_config = &default_gem_config;
4236 int (*clk_init)(struct platform_device *, struct clk **,
4237 struct clk **, struct clk **, struct clk **,
4238 struct clk **) = macb_config->clk_init;
4239 int (*init)(struct platform_device *) = macb_config->init;
4240 struct device_node *np = pdev->dev.of_node;
4241 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4242 struct clk *tsu_clk = NULL;
4243 unsigned int queue_mask, num_queues;
4245 phy_interface_t interface;
4246 struct net_device *dev;
4247 struct resource *regs;
4253 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4254 mem = devm_ioremap_resource(&pdev->dev, regs);
4256 return PTR_ERR(mem);
4259 const struct of_device_id *match;
4261 match = of_match_node(macb_dt_ids, np);
4262 if (match && match->data) {
4263 macb_config = match->data;
4264 clk_init = macb_config->clk_init;
4265 init = macb_config->init;
4269 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
4273 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
4274 pm_runtime_use_autosuspend(&pdev->dev);
4275 pm_runtime_get_noresume(&pdev->dev);
4276 pm_runtime_set_active(&pdev->dev);
4277 pm_runtime_enable(&pdev->dev);
4278 native_io = hw_is_native_io(mem);
4280 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4281 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4284 goto err_disable_clocks;
4287 dev->base_addr = regs->start;
4289 SET_NETDEV_DEV(dev, &pdev->dev);
4291 bp = netdev_priv(dev);
4295 bp->native_io = native_io;
4297 bp->macb_reg_readl = hw_readl_native;
4298 bp->macb_reg_writel = hw_writel_native;
4300 bp->macb_reg_readl = hw_readl;
4301 bp->macb_reg_writel = hw_writel;
4303 bp->num_queues = num_queues;
4304 bp->queue_mask = queue_mask;
4306 bp->dma_burst_length = macb_config->dma_burst_length;
4309 bp->tx_clk = tx_clk;
4310 bp->rx_clk = rx_clk;
4311 bp->tsu_clk = tsu_clk;
4313 bp->jumbo_max_len = macb_config->jumbo_max_len;
4316 if (of_get_property(np, "magic-packet", NULL))
4317 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4318 device_init_wakeup(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4320 spin_lock_init(&bp->lock);
4322 /* setup capabilities */
4323 macb_configure_caps(bp, macb_config);
4325 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4326 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4327 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
4328 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4331 platform_set_drvdata(pdev, dev);
4333 dev->irq = platform_get_irq(pdev, 0);
4336 goto err_out_free_netdev;
4339 /* MTU range: 68 - 1500 or 10240 */
4340 dev->min_mtu = GEM_MTU_MIN_SIZE;
4341 if (bp->caps & MACB_CAPS_JUMBO)
4342 dev->max_mtu = gem_readl(bp, JML) - ETH_HLEN - ETH_FCS_LEN;
4344 dev->max_mtu = ETH_DATA_LEN;
4346 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4347 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4349 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4350 macb_dma_desc_get_size(bp);
4352 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4354 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4355 macb_dma_desc_get_size(bp);
4358 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4359 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4360 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4362 mac = of_get_mac_address(np);
4363 if (PTR_ERR(mac) == -EPROBE_DEFER) {
4364 err = -EPROBE_DEFER;
4365 goto err_out_free_netdev;
4366 } else if (!IS_ERR_OR_NULL(mac)) {
4367 ether_addr_copy(bp->dev->dev_addr, mac);
4369 macb_get_hwaddr(bp);
4372 err = of_get_phy_mode(np, &interface);
4374 /* not found in DT, MII by default */
4375 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4377 bp->phy_interface = interface;
4379 bp->speed = SPEED_UNKNOWN;
4381 /* IP specific init */
4384 goto err_out_free_netdev;
4386 err = macb_mii_init(bp);
4388 goto err_out_free_netdev;
4390 netif_carrier_off(dev);
4392 err = register_netdev(dev);
4394 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4395 goto err_out_unregister_mdio;
4398 tasklet_init(&bp->hresp_err_tasklet, macb_hresp_error_task,
4401 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4402 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4403 dev->base_addr, dev->irq, dev->dev_addr);
4405 pm_runtime_mark_last_busy(&bp->pdev->dev);
4406 pm_runtime_put_autosuspend(&bp->pdev->dev);
4410 err_out_unregister_mdio:
4411 mdiobus_unregister(bp->mii_bus);
4412 mdiobus_free(bp->mii_bus);
4414 err_out_free_netdev:
4418 clk_disable_unprepare(tx_clk);
4419 clk_unregister(tx_clk);
4420 clk_disable_unprepare(hclk);
4421 clk_disable_unprepare(pclk);
4422 clk_disable_unprepare(rx_clk);
4423 clk_disable_unprepare(tsu_clk);
4424 pm_runtime_disable(&pdev->dev);
4425 pm_runtime_set_suspended(&pdev->dev);
4426 pm_runtime_dont_use_autosuspend(&pdev->dev);
4431 static int macb_remove(struct platform_device *pdev)
4433 struct net_device *dev;
4436 dev = platform_get_drvdata(pdev);
4439 bp = netdev_priv(dev);
4440 mdiobus_unregister(bp->mii_bus);
4441 mdiobus_free(bp->mii_bus);
4443 unregister_netdev(dev);
4444 tasklet_kill(&bp->hresp_err_tasklet);
4445 pm_runtime_disable(&pdev->dev);
4446 pm_runtime_dont_use_autosuspend(&pdev->dev);
4447 if (!pm_runtime_suspended(&pdev->dev)) {
4448 clk_disable_unprepare(bp->tx_clk);
4449 clk_unregister(bp->tx_clk);
4450 clk_disable_unprepare(bp->hclk);
4451 clk_disable_unprepare(bp->pclk);
4452 clk_disable_unprepare(bp->rx_clk);
4453 clk_disable_unprepare(bp->tsu_clk);
4454 pm_runtime_set_suspended(&pdev->dev);
4456 phylink_destroy(bp->phylink);
4463 static int __maybe_unused macb_suspend(struct device *dev)
4465 struct net_device *netdev = dev_get_drvdata(dev);
4466 struct macb *bp = netdev_priv(netdev);
4467 struct macb_queue *queue = bp->queues;
4468 unsigned long flags;
4471 if (!netif_running(netdev))
4474 if (bp->wol & MACB_WOL_ENABLED) {
4475 macb_writel(bp, IER, MACB_BIT(WOL));
4476 macb_writel(bp, WOL, MACB_BIT(MAG));
4477 enable_irq_wake(bp->queues[0].irq);
4478 netif_device_detach(netdev);
4480 netif_device_detach(netdev);
4481 for (q = 0, queue = bp->queues; q < bp->num_queues;
4483 napi_disable(&queue->napi);
4485 phylink_stop(bp->phylink);
4487 spin_lock_irqsave(&bp->lock, flags);
4489 spin_unlock_irqrestore(&bp->lock, flags);
4491 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4492 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
4494 if (netdev->hw_features & NETIF_F_NTUPLE)
4495 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
4498 netif_carrier_off(netdev);
4500 bp->ptp_info->ptp_remove(netdev);
4501 pm_runtime_force_suspend(dev);
4506 static int __maybe_unused macb_resume(struct device *dev)
4508 struct net_device *netdev = dev_get_drvdata(dev);
4509 struct macb *bp = netdev_priv(netdev);
4510 struct macb_queue *queue = bp->queues;
4513 if (!netif_running(netdev))
4516 pm_runtime_force_resume(dev);
4518 if (bp->wol & MACB_WOL_ENABLED) {
4519 macb_writel(bp, IDR, MACB_BIT(WOL));
4520 macb_writel(bp, WOL, 0);
4521 disable_irq_wake(bp->queues[0].irq);
4523 macb_writel(bp, NCR, MACB_BIT(MPE));
4525 if (netdev->hw_features & NETIF_F_NTUPLE)
4526 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
4528 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
4529 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
4531 for (q = 0, queue = bp->queues; q < bp->num_queues;
4533 napi_enable(&queue->napi);
4535 phylink_start(bp->phylink);
4540 macb_set_rx_mode(netdev);
4541 macb_restore_features(bp);
4542 netif_device_attach(netdev);
4544 bp->ptp_info->ptp_init(netdev);
4549 static int __maybe_unused macb_runtime_suspend(struct device *dev)
4551 struct net_device *netdev = dev_get_drvdata(dev);
4552 struct macb *bp = netdev_priv(netdev);
4554 if (!(device_may_wakeup(&bp->dev->dev))) {
4555 clk_disable_unprepare(bp->tx_clk);
4556 clk_disable_unprepare(bp->hclk);
4557 clk_disable_unprepare(bp->pclk);
4558 clk_disable_unprepare(bp->rx_clk);
4560 clk_disable_unprepare(bp->tsu_clk);
4565 static int __maybe_unused macb_runtime_resume(struct device *dev)
4567 struct net_device *netdev = dev_get_drvdata(dev);
4568 struct macb *bp = netdev_priv(netdev);
4570 if (!(device_may_wakeup(&bp->dev->dev))) {
4571 clk_prepare_enable(bp->pclk);
4572 clk_prepare_enable(bp->hclk);
4573 clk_prepare_enable(bp->tx_clk);
4574 clk_prepare_enable(bp->rx_clk);
4576 clk_prepare_enable(bp->tsu_clk);
4581 static const struct dev_pm_ops macb_pm_ops = {
4582 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
4583 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
4586 static struct platform_driver macb_driver = {
4587 .probe = macb_probe,
4588 .remove = macb_remove,
4591 .of_match_table = of_match_ptr(macb_dt_ids),
4596 module_platform_driver(macb_driver);
4598 MODULE_LICENSE("GPL");
4599 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
4600 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
4601 MODULE_ALIAS("platform:macb");