drivers/net/ethernet/cavium/liquidio/request_manager.c

   1 /**********************************************************************
   2  * Author: Cavium, Inc.
   3  *
   4  * Contact: support@cavium.com
   5  *          Please include "LiquidIO" in the subject.
   6  *
   7  * Copyright (c) 2003-2016 Cavium, Inc.
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  **********************************************************************/
  19 #include <linux/pci.h>
  20 #include <linux/netdevice.h>
  21 #include <linux/vmalloc.h>
  22 #include "liquidio_common.h"
  23 #include "octeon_droq.h"
  24 #include "octeon_iq.h"
  25 #include "response_manager.h"
  26 #include "octeon_device.h"
  27 #include "octeon_main.h"
  28 #include "octeon_network.h"
  29 #include "cn66xx_device.h"
  30 #include "cn23xx_pf_device.h"
  31 #include "cn23xx_vf_device.h"
  32
  33 struct iq_post_status {
  34         int status;
  35         int index;
  36 };
  37
  38 static void check_db_timeout(struct work_struct *work);
  39 static void  __check_db_timeout(struct octeon_device *oct, u64 iq_no);
  40
  41 static void (*reqtype_free_fn[MAX_OCTEON_DEVICES][REQTYPE_LAST + 1]) (void *);
  42
  43 static inline int IQ_INSTR_MODE_64B(struct octeon_device *oct, int iq_no)
  44 {
  45         struct octeon_instr_queue *iq =
  46             (struct octeon_instr_queue *)oct->instr_queue[iq_no];
  47         return iq->iqcmd_64B;
  48 }
  49
  50 #define IQ_INSTR_MODE_32B(oct, iq_no)  (!IQ_INSTR_MODE_64B(oct, iq_no))
  51
  52 /* Define this to return the request status comaptible to old code */
  53 /*#define OCTEON_USE_OLD_REQ_STATUS*/
  54
  55 /* Return 0 on success, 1 on failure */
  56 int octeon_init_instr_queue(struct octeon_device *oct,
  57                             union oct_txpciq txpciq,
  58                             u32 num_descs)
  59 {
  60         struct octeon_instr_queue *iq;
  61         struct octeon_iq_config *conf = NULL;
  62         u32 iq_no = (u32)txpciq.s.q_no;
  63         u32 q_size;
  64         struct cavium_wq *db_wq;
  65         int numa_node = dev_to_node(&oct->pci_dev->dev);
  66
  67         if (OCTEON_CN6XXX(oct))
  68                 conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn6xxx)));
  69         else if (OCTEON_CN23XX_PF(oct))
  70                 conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn23xx_pf)));
  71         else if (OCTEON_CN23XX_VF(oct))
  72                 conf = &(CFG_GET_IQ_CFG(CHIP_CONF(oct, cn23xx_vf)));
  73
  74         if (!conf) {
  75                 dev_err(&oct->pci_dev->dev, "Unsupported Chip %x\n",
  76                         oct->chip_id);
  77                 return 1;
  78         }
  79
  80         q_size = (u32)conf->instr_type * num_descs;
  81
  82         iq = oct->instr_queue[iq_no];
  83
  84         iq->oct_dev = oct;
  85
  86         iq->base_addr = lio_dma_alloc(oct, q_size, &iq->base_addr_dma);
  87         if (!iq->base_addr) {
  88                 dev_err(&oct->pci_dev->dev, "Cannot allocate memory for instr queue %d\n",
  89                         iq_no);
  90                 return 1;
  91         }
  92
  93         iq->max_count = num_descs;
  94
  95         /* Initialize a list to holds requests that have been posted to Octeon
  96          * but has yet to be fetched by octeon
  97          */
  98         iq->request_list = vmalloc_node((sizeof(*iq->request_list) * num_descs),
  99                                                numa_node);
 100         if (!iq->request_list)
 101                 iq->request_list =
 102                         vmalloc(array_size(num_descs,
 103                                            sizeof(*iq->request_list)));
 104         if (!iq->request_list) {
 105                 lio_dma_free(oct, q_size, iq->base_addr, iq->base_addr_dma);
 106                 dev_err(&oct->pci_dev->dev, "Alloc failed for IQ[%d] nr free list\n",
 107                         iq_no);
 108                 return 1;
 109         }
 110
 111         memset(iq->request_list, 0, sizeof(*iq->request_list) * num_descs);
 112
 113         dev_dbg(&oct->pci_dev->dev, "IQ[%d]: base: %p basedma: %pad count: %d\n",
 114                 iq_no, iq->base_addr, &iq->base_addr_dma, iq->max_count);
 115
 116         iq->txpciq.u64 = txpciq.u64;
 117         iq->fill_threshold = (u32)conf->db_min;
 118         iq->fill_cnt = 0;
 119         iq->host_write_index = 0;
 120         iq->octeon_read_index = 0;
 121         iq->flush_index = 0;
 122         iq->last_db_time = 0;
 123         iq->do_auto_flush = 1;
 124         iq->db_timeout = (u32)conf->db_timeout;
 125         atomic_set(&iq->instr_pending, 0);
 126         iq->pkts_processed = 0;
 127
 128         /* Initialize the spinlock for this instruction queue */
 129         spin_lock_init(&iq->lock);
 130         if (iq_no == 0) {
 131                 iq->allow_soft_cmds = true;
 132                 spin_lock_init(&iq->post_lock);
 133         } else {
 134                 iq->allow_soft_cmds = false;
 135         }
 136
 137         spin_lock_init(&iq->iq_flush_running_lock);
 138
 139         oct->io_qmask.iq |= BIT_ULL(iq_no);
 140
 141         /* Set the 32B/64B mode for each input queue */
 142         oct->io_qmask.iq64B |= ((conf->instr_type == 64) << iq_no);
 143         iq->iqcmd_64B = (conf->instr_type == 64);
 144
 145         oct->fn_list.setup_iq_regs(oct, iq_no);
 146
 147         oct->check_db_wq[iq_no].wq = alloc_workqueue("check_iq_db",
 148                                                      WQ_MEM_RECLAIM,
 149                                                      0);
 150         if (!oct->check_db_wq[iq_no].wq) {
 151                 vfree(iq->request_list);
 152                 iq->request_list = NULL;
 153                 lio_dma_free(oct, q_size, iq->base_addr, iq->base_addr_dma);
 154                 dev_err(&oct->pci_dev->dev, "check db wq create failed for iq %d\n",
 155                         iq_no);
 156                 return 1;
 157         }
 158
 159         db_wq = &oct->check_db_wq[iq_no];
 160
 161         INIT_DELAYED_WORK(&db_wq->wk.work, check_db_timeout);
 162         db_wq->wk.ctxptr = oct;
 163         db_wq->wk.ctxul = iq_no;
 164         queue_delayed_work(db_wq->wq, &db_wq->wk.work, msecs_to_jiffies(1));
 165
 166         return 0;
 167 }
 168
 169 int octeon_delete_instr_queue(struct octeon_device *oct, u32 iq_no)
 170 {
 171         u64 desc_size = 0, q_size;
 172         struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
 173
 174         cancel_delayed_work_sync(&oct->check_db_wq[iq_no].wk.work);
 175         destroy_workqueue(oct->check_db_wq[iq_no].wq);
 176
 177         if (OCTEON_CN6XXX(oct))
 178                 desc_size =
 179                     CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn6xxx));
 180         else if (OCTEON_CN23XX_PF(oct))
 181                 desc_size =
 182                     CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn23xx_pf));
 183         else if (OCTEON_CN23XX_VF(oct))
 184                 desc_size =
 185                     CFG_GET_IQ_INSTR_TYPE(CHIP_CONF(oct, cn23xx_vf));
 186
 187         vfree(iq->request_list);
 188
 189         if (iq->base_addr) {
 190                 q_size = iq->max_count * desc_size;
 191                 lio_dma_free(oct, (u32)q_size, iq->base_addr,
 192                              iq->base_addr_dma);
 193                 oct->io_qmask.iq &= ~(1ULL << iq_no);
 194                 vfree(oct->instr_queue[iq_no]);
 195                 oct->instr_queue[iq_no] = NULL;
 196                 oct->num_iqs--;
 197                 return 0;
 198         }
 199         return 1;
 200 }
 201
 202 /* Return 0 on success, 1 on failure */
 203 int octeon_setup_iq(struct octeon_device *oct,
 204                     int ifidx,
 205                     int q_index,
 206                     union oct_txpciq txpciq,
 207                     u32 num_descs,
 208                     void *app_ctx)
 209 {
 210         u32 iq_no = (u32)txpciq.s.q_no;
 211         int numa_node = dev_to_node(&oct->pci_dev->dev);
 212
 213         if (oct->instr_queue[iq_no]) {
 214                 dev_dbg(&oct->pci_dev->dev, "IQ is in use. Cannot create the IQ: %d again\n",
 215                         iq_no);
 216                 oct->instr_queue[iq_no]->txpciq.u64 = txpciq.u64;
 217                 oct->instr_queue[iq_no]->app_ctx = app_ctx;
 218                 return 0;
 219         }
 220         oct->instr_queue[iq_no] =
 221             vmalloc_node(sizeof(struct octeon_instr_queue), numa_node);
 222         if (!oct->instr_queue[iq_no])
 223                 oct->instr_queue[iq_no] =
 224                     vmalloc(sizeof(struct octeon_instr_queue));
 225         if (!oct->instr_queue[iq_no])
 226                 return 1;
 227
 228         memset(oct->instr_queue[iq_no], 0,
 229                sizeof(struct octeon_instr_queue));
 230
 231         oct->instr_queue[iq_no]->q_index = q_index;
 232         oct->instr_queue[iq_no]->app_ctx = app_ctx;
 233         oct->instr_queue[iq_no]->ifidx = ifidx;
 234
 235         if (octeon_init_instr_queue(oct, txpciq, num_descs)) {
 236                 vfree(oct->instr_queue[iq_no]);
 237                 oct->instr_queue[iq_no] = NULL;
 238                 return 1;
 239         }
 240
 241         oct->num_iqs++;
 242         if (oct->fn_list.enable_io_queues(oct))
 243                 return 1;
 244
 245         return 0;
 246 }
 247
 248 int lio_wait_for_instr_fetch(struct octeon_device *oct)
 249 {
 250         int i, retry = 1000, pending, instr_cnt = 0;
 251
 252         do {
 253                 instr_cnt = 0;
 254
 255                 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) {
 256                         if (!(oct->io_qmask.iq & BIT_ULL(i)))
 257                                 continue;
 258                         pending =
 259                             atomic_read(&oct->instr_queue[i]->instr_pending);
 260                         if (pending)
 261                                 __check_db_timeout(oct, i);
 262                         instr_cnt += pending;
 263                 }
 264
 265                 if (instr_cnt == 0)
 266                         break;
 267
 268                 schedule_timeout_uninterruptible(1);
 269
 270         } while (retry-- && instr_cnt);
 271
 272         return instr_cnt;
 273 }
 274
 275 static inline void
 276 ring_doorbell(struct octeon_device *oct, struct octeon_instr_queue *iq)
 277 {
 278         if (atomic_read(&oct->status) == OCT_DEV_RUNNING) {
 279                 writel(iq->fill_cnt, iq->doorbell_reg);
 280                 /* make sure doorbell write goes through */
 281                 mmiowb();
 282                 iq->fill_cnt = 0;
 283                 iq->last_db_time = jiffies;
 284                 return;
 285         }
 286 }
 287
 288 void
 289 octeon_ring_doorbell_locked(struct octeon_device *oct, u32 iq_no)
 290 {
 291         struct octeon_instr_queue *iq;
 292
 293         iq = oct->instr_queue[iq_no];
 294         spin_lock(&iq->post_lock);
 295         if (iq->fill_cnt)
 296                 ring_doorbell(oct, iq);
 297         spin_unlock(&iq->post_lock);
 298 }
 299
 300 static inline void __copy_cmd_into_iq(struct octeon_instr_queue *iq,
 301                                       u8 *cmd)
 302 {
 303         u8 *iqptr, cmdsize;
 304
 305         cmdsize = ((iq->iqcmd_64B) ? 64 : 32);
 306         iqptr = iq->base_addr + (cmdsize * iq->host_write_index);
 307
 308         memcpy(iqptr, cmd, cmdsize);
 309 }
 310
 311 static inline struct iq_post_status
 312 __post_command2(struct octeon_instr_queue *iq, u8 *cmd)
 313 {
 314         struct iq_post_status st;
 315
 316         st.status = IQ_SEND_OK;
 317
 318         /* This ensures that the read index does not wrap around to the same
 319          * position if queue gets full before Octeon could fetch any instr.
 320          */
 321         if (atomic_read(&iq->instr_pending) >= (s32)(iq->max_count - 1)) {
 322                 st.status = IQ_SEND_FAILED;
 323                 st.index = -1;
 324                 return st;
 325         }
 326
 327         if (atomic_read(&iq->instr_pending) >= (s32)(iq->max_count - 2))
 328                 st.status = IQ_SEND_STOP;
 329
 330         __copy_cmd_into_iq(iq, cmd);
 331
 332         /* "index" is returned, host_write_index is modified. */
 333         st.index = iq->host_write_index;
 334         iq->host_write_index = incr_index(iq->host_write_index, 1,
 335                                           iq->max_count);
 336         iq->fill_cnt++;
 337
 338         /* Flush the command into memory. We need to be sure the data is in
 339          * memory before indicating that the instruction is pending.
 340          */
 341         wmb();
 342
 343         atomic_inc(&iq->instr_pending);
 344
 345         return st;
 346 }
 347
 348 int
 349 octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype,
 350                                 void (*fn)(void *))
 351 {
 352         if (reqtype > REQTYPE_LAST) {
 353                 dev_err(&oct->pci_dev->dev, "%s: Invalid reqtype: %d\n",
 354                         __func__, reqtype);
 355                 return -EINVAL;
 356         }
 357
 358         reqtype_free_fn[oct->octeon_id][reqtype] = fn;
 359
 360         return 0;
 361 }
 362
 363 static inline void
 364 __add_to_request_list(struct octeon_instr_queue *iq,
 365                       int idx, void *buf, int reqtype)
 366 {
 367         iq->request_list[idx].buf = buf;
 368         iq->request_list[idx].reqtype = reqtype;
 369 }
 370
 371 /* Can only run in process context */
 372 int
 373 lio_process_iq_request_list(struct octeon_device *oct,
 374                             struct octeon_instr_queue *iq, u32 napi_budget)
 375 {
 376         struct cavium_wq *cwq = &oct->dma_comp_wq;
 377         int reqtype;
 378         void *buf;
 379         u32 old = iq->flush_index;
 380         u32 inst_count = 0;
 381         unsigned int pkts_compl = 0, bytes_compl = 0;
 382         struct octeon_soft_command *sc;
 383         unsigned long flags;
 384
 385         while (old != iq->octeon_read_index) {
 386                 reqtype = iq->request_list[old].reqtype;
 387                 buf     = iq->request_list[old].buf;
 388
 389                 if (reqtype == REQTYPE_NONE)
 390                         goto skip_this;
 391
 392                 octeon_update_tx_completion_counters(buf, reqtype, &pkts_compl,
 393                                                      &bytes_compl);
 394
 395                 switch (reqtype) {
 396                 case REQTYPE_NORESP_NET:
 397                 case REQTYPE_NORESP_NET_SG:
 398                 case REQTYPE_RESP_NET_SG:
 399                         reqtype_free_fn[oct->octeon_id][reqtype](buf);
 400                         break;
 401                 case REQTYPE_RESP_NET:
 402                 case REQTYPE_SOFT_COMMAND:
 403                         sc = buf;
 404                         /* We're expecting a response from Octeon.
 405                          * It's up to lio_process_ordered_list() to
 406                          * process  sc. Add sc to the ordered soft
 407                          * command response list because we expect
 408                          * a response from Octeon.
 409                          */
 410                         spin_lock_irqsave(&oct->response_list
 411                                           [OCTEON_ORDERED_SC_LIST].lock, flags);
 412                         atomic_inc(&oct->response_list
 413                                    [OCTEON_ORDERED_SC_LIST].pending_req_count);
 414                         list_add_tail(&sc->node, &oct->response_list
 415                                 [OCTEON_ORDERED_SC_LIST].head);
 416                         spin_unlock_irqrestore(&oct->response_list
 417                                                [OCTEON_ORDERED_SC_LIST].lock,
 418                                                flags);
 419                         break;
 420                 default:
 421                         dev_err(&oct->pci_dev->dev,
 422                                 "%s Unknown reqtype: %d buf: %p at idx %d\n",
 423                                 __func__, reqtype, buf, old);
 424                 }
 425
 426                 iq->request_list[old].buf = NULL;
 427                 iq->request_list[old].reqtype = 0;
 428
 429  skip_this:
 430                 inst_count++;
 431                 old = incr_index(old, 1, iq->max_count);
 432
 433                 if ((napi_budget) && (inst_count >= napi_budget))
 434                         break;
 435         }
 436         if (bytes_compl)
 437                 octeon_report_tx_completion_to_bql(iq->app_ctx, pkts_compl,
 438                                                    bytes_compl);
 439         iq->flush_index = old;
 440
 441         if (atomic_read(&oct->response_list
 442                         [OCTEON_ORDERED_SC_LIST].pending_req_count))
 443                 queue_work(cwq->wq, &cwq->wk.work.work);
 444
 445         return inst_count;
 446 }
 447
 448 /* Can only be called from process context */
 449 int
 450 octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq,
 451                 u32 napi_budget)
 452 {
 453         u32 inst_processed = 0;
 454         u32 tot_inst_processed = 0;
 455         int tx_done = 1;
 456
 457         if (!spin_trylock(&iq->iq_flush_running_lock))
 458                 return tx_done;
 459
 460         spin_lock_bh(&iq->lock);
 461
 462         iq->octeon_read_index = oct->fn_list.update_iq_read_idx(iq);
 463
 464         do {
 465                 /* Process any outstanding IQ packets. */
 466                 if (iq->flush_index == iq->octeon_read_index)
 467                         break;
 468
 469                 if (napi_budget)
 470                         inst_processed =
 471                                 lio_process_iq_request_list(oct, iq,
 472                                                             napi_budget -
 473                                                             tot_inst_processed);
 474                 else
 475                         inst_processed =
 476                                 lio_process_iq_request_list(oct, iq, 0);
 477
 478                 if (inst_processed) {
 479                         iq->pkts_processed += inst_processed;
 480                         atomic_sub(inst_processed, &iq->instr_pending);
 481                         iq->stats.instr_processed += inst_processed;
 482                 }
 483
 484                 tot_inst_processed += inst_processed;
 485         } while (tot_inst_processed < napi_budget);
 486
 487         if (napi_budget && (tot_inst_processed >= napi_budget))
 488                 tx_done = 0;
 489
 490         iq->last_db_time = jiffies;
 491
 492         spin_unlock_bh(&iq->lock);
 493
 494         spin_unlock(&iq->iq_flush_running_lock);
 495
 496         return tx_done;
 497 }
 498
 499 /* Process instruction queue after timeout.
 500  * This routine gets called from a workqueue or when removing the module.
 501  */
 502 static void __check_db_timeout(struct octeon_device *oct, u64 iq_no)
 503 {
 504         struct octeon_instr_queue *iq;
 505         u64 next_time;
 506
 507         if (!oct)
 508                 return;
 509
 510         iq = oct->instr_queue[iq_no];
 511         if (!iq)
 512                 return;
 513
 514         /* return immediately, if no work pending */
 515         if (!atomic_read(&iq->instr_pending))
 516                 return;
 517         /* If jiffies - last_db_time < db_timeout do nothing  */
 518         next_time = iq->last_db_time + iq->db_timeout;
 519         if (!time_after(jiffies, (unsigned long)next_time))
 520                 return;
 521         iq->last_db_time = jiffies;
 522
 523         /* Flush the instruction queue */
 524         octeon_flush_iq(oct, iq, 0);
 525
 526         lio_enable_irq(NULL, iq);
 527 }
 528
 529 /* Called by the Poll thread at regular intervals to check the instruction
 530  * queue for commands to be posted and for commands that were fetched by Octeon.
 531  */
 532 static void check_db_timeout(struct work_struct *work)
 533 {
 534         struct cavium_wk *wk = (struct cavium_wk *)work;
 535         struct octeon_device *oct = (struct octeon_device *)wk->ctxptr;
 536         u64 iq_no = wk->ctxul;
 537         struct cavium_wq *db_wq = &oct->check_db_wq[iq_no];
 538         u32 delay = 10;
 539
 540         __check_db_timeout(oct, iq_no);
 541         queue_delayed_work(db_wq->wq, &db_wq->wk.work, msecs_to_jiffies(delay));
 542 }
 543
 544 int
 545 octeon_send_command(struct octeon_device *oct, u32 iq_no,
 546                     u32 force_db, void *cmd, void *buf,
 547                     u32 datasize, u32 reqtype)
 548 {
 549         int xmit_stopped;
 550         struct iq_post_status st;
 551         struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
 552
 553         /* Get the lock and prevent other tasks and tx interrupt handler from
 554          * running.
 555          */
 556         if (iq->allow_soft_cmds)
 557                 spin_lock_bh(&iq->post_lock);
 558
 559         st = __post_command2(iq, cmd);
 560
 561         if (st.status != IQ_SEND_FAILED) {
 562                 xmit_stopped = octeon_report_sent_bytes_to_bql(buf, reqtype);
 563                 __add_to_request_list(iq, st.index, buf, reqtype);
 564                 INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, bytes_sent, datasize);
 565                 INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, instr_posted, 1);
 566
 567                 if (iq->fill_cnt >= MAX_OCTEON_FILL_COUNT || force_db ||
 568                     xmit_stopped || st.status == IQ_SEND_STOP)
 569                         ring_doorbell(oct, iq);
 570         } else {
 571                 INCR_INSTRQUEUE_PKT_COUNT(oct, iq_no, instr_dropped, 1);
 572         }
 573
 574         if (iq->allow_soft_cmds)
 575                 spin_unlock_bh(&iq->post_lock);
 576
 577         /* This is only done here to expedite packets being flushed
 578          * for cases where there are no IQ completion interrupts.
 579          */
 580
 581         return st.status;
 582 }
 583
 584 void
 585 octeon_prepare_soft_command(struct octeon_device *oct,
 586                             struct octeon_soft_command *sc,
 587                             u8 opcode,
 588                             u8 subcode,
 589                             u32 irh_ossp,
 590                             u64 ossp0,
 591                             u64 ossp1)
 592 {
 593         struct octeon_config *oct_cfg;
 594         struct octeon_instr_ih2 *ih2;
 595         struct octeon_instr_ih3 *ih3;
 596         struct octeon_instr_pki_ih3 *pki_ih3;
 597         struct octeon_instr_irh *irh;
 598         struct octeon_instr_rdp *rdp;
 599
 600         WARN_ON(opcode > 15);
 601         WARN_ON(subcode > 127);
 602
 603         oct_cfg = octeon_get_conf(oct);
 604
 605         if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) {
 606                 ih3 = (struct octeon_instr_ih3 *)&sc->cmd.cmd3.ih3;
 607
 608                 ih3->pkind = oct->instr_queue[sc->iq_no]->txpciq.s.pkind;
 609
 610                 pki_ih3 = (struct octeon_instr_pki_ih3 *)&sc->cmd.cmd3.pki_ih3;
 611
 612                 pki_ih3->w           = 1;
 613                 pki_ih3->raw         = 1;
 614                 pki_ih3->utag        = 1;
 615                 pki_ih3->uqpg        =
 616                         oct->instr_queue[sc->iq_no]->txpciq.s.use_qpg;
 617                 pki_ih3->utt         = 1;
 618                 pki_ih3->tag     = LIO_CONTROL;
 619                 pki_ih3->tagtype = ATOMIC_TAG;
 620                 pki_ih3->qpg         =
 621                         oct->instr_queue[sc->iq_no]->txpciq.s.ctrl_qpg;
 622
 623                 pki_ih3->pm          = 0x7;
 624                 pki_ih3->sl          = 8;
 625
 626                 if (sc->datasize)
 627                         ih3->dlengsz = sc->datasize;
 628
 629                 irh            = (struct octeon_instr_irh *)&sc->cmd.cmd3.irh;
 630                 irh->opcode    = opcode;
 631                 irh->subcode   = subcode;
 632
 633                 /* opcode/subcode specific parameters (ossp) */
 634                 irh->ossp       = irh_ossp;
 635                 sc->cmd.cmd3.ossp[0] = ossp0;
 636                 sc->cmd.cmd3.ossp[1] = ossp1;
 637
 638                 if (sc->rdatasize) {
 639                         rdp = (struct octeon_instr_rdp *)&sc->cmd.cmd3.rdp;
 640                         rdp->pcie_port = oct->pcie_port;
 641                         rdp->rlen      = sc->rdatasize;
 642
 643                         irh->rflag =  1;
 644                         /*PKI IH3*/
 645                         /* pki_ih3 irh+ossp[0]+ossp[1]+rdp+rptr = 48 bytes */
 646                         ih3->fsz    = LIO_SOFTCMDRESP_IH3;
 647                 } else {
 648                         irh->rflag =  0;
 649                         /*PKI IH3*/
 650                         /* pki_h3 + irh + ossp[0] + ossp[1] = 32 bytes */
 651                         ih3->fsz    = LIO_PCICMD_O3;
 652                 }
 653
 654         } else {
 655                 ih2          = (struct octeon_instr_ih2 *)&sc->cmd.cmd2.ih2;
 656                 ih2->tagtype = ATOMIC_TAG;
 657                 ih2->tag     = LIO_CONTROL;
 658                 ih2->raw     = 1;
 659                 ih2->grp     = CFG_GET_CTRL_Q_GRP(oct_cfg);
 660
 661                 if (sc->datasize) {
 662                         ih2->dlengsz = sc->datasize;
 663                         ih2->rs = 1;
 664                 }
 665
 666                 irh            = (struct octeon_instr_irh *)&sc->cmd.cmd2.irh;
 667                 irh->opcode    = opcode;
 668                 irh->subcode   = subcode;
 669
 670                 /* opcode/subcode specific parameters (ossp) */
 671                 irh->ossp       = irh_ossp;
 672                 sc->cmd.cmd2.ossp[0] = ossp0;
 673                 sc->cmd.cmd2.ossp[1] = ossp1;
 674
 675                 if (sc->rdatasize) {
 676                         rdp = (struct octeon_instr_rdp *)&sc->cmd.cmd2.rdp;
 677                         rdp->pcie_port = oct->pcie_port;
 678                         rdp->rlen      = sc->rdatasize;
 679
 680                         irh->rflag =  1;
 681                         /* irh+ossp[0]+ossp[1]+rdp+rptr = 40 bytes */
 682                         ih2->fsz   = LIO_SOFTCMDRESP_IH2;
 683                 } else {
 684                         irh->rflag =  0;
 685                         /* irh + ossp[0] + ossp[1] = 24 bytes */
 686                         ih2->fsz   = LIO_PCICMD_O2;
 687                 }
 688         }
 689 }
 690
 691 int octeon_send_soft_command(struct octeon_device *oct,
 692                              struct octeon_soft_command *sc)
 693 {
 694         struct octeon_instr_queue *iq;
 695         struct octeon_instr_ih2 *ih2;
 696         struct octeon_instr_ih3 *ih3;
 697         struct octeon_instr_irh *irh;
 698         u32 len;
 699
 700         iq = oct->instr_queue[sc->iq_no];
 701         if (!iq->allow_soft_cmds) {
 702                 dev_err(&oct->pci_dev->dev, "Soft commands are not allowed on Queue %d\n",
 703                         sc->iq_no);
 704                 INCR_INSTRQUEUE_PKT_COUNT(oct, sc->iq_no, instr_dropped, 1);
 705                 return IQ_SEND_FAILED;
 706         }
 707
 708         if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) {
 709                 ih3 =  (struct octeon_instr_ih3 *)&sc->cmd.cmd3.ih3;
 710                 if (ih3->dlengsz) {
 711                         WARN_ON(!sc->dmadptr);
 712                         sc->cmd.cmd3.dptr = sc->dmadptr;
 713                 }
 714                 irh = (struct octeon_instr_irh *)&sc->cmd.cmd3.irh;
 715                 if (irh->rflag) {
 716                         WARN_ON(!sc->dmarptr);
 717                         WARN_ON(!sc->status_word);
 718                         *sc->status_word = COMPLETION_WORD_INIT;
 719                         sc->cmd.cmd3.rptr = sc->dmarptr;
 720                 }
 721                 len = (u32)ih3->dlengsz;
 722         } else {
 723                 ih2 = (struct octeon_instr_ih2 *)&sc->cmd.cmd2.ih2;
 724                 if (ih2->dlengsz) {
 725                         WARN_ON(!sc->dmadptr);
 726                         sc->cmd.cmd2.dptr = sc->dmadptr;
 727                 }
 728                 irh = (struct octeon_instr_irh *)&sc->cmd.cmd2.irh;
 729                 if (irh->rflag) {
 730                         WARN_ON(!sc->dmarptr);
 731                         WARN_ON(!sc->status_word);
 732                         *sc->status_word = COMPLETION_WORD_INIT;
 733                         sc->cmd.cmd2.rptr = sc->dmarptr;
 734                 }
 735                 len = (u32)ih2->dlengsz;
 736         }
 737
 738         sc->expiry_time = jiffies + msecs_to_jiffies(LIO_SC_MAX_TMO_MS);
 739
 740         return (octeon_send_command(oct, sc->iq_no, 1, &sc->cmd, sc,
 741                                     len, REQTYPE_SOFT_COMMAND));
 742 }
 743
 744 int octeon_setup_sc_buffer_pool(struct octeon_device *oct)
 745 {
 746         int i;
 747         u64 dma_addr;
 748         struct octeon_soft_command *sc;
 749
 750         INIT_LIST_HEAD(&oct->sc_buf_pool.head);
 751         spin_lock_init(&oct->sc_buf_pool.lock);
 752         atomic_set(&oct->sc_buf_pool.alloc_buf_count, 0);
 753
 754         for (i = 0; i < MAX_SOFT_COMMAND_BUFFERS; i++) {
 755                 sc = (struct octeon_soft_command *)
 756                         lio_dma_alloc(oct,
 757                                       SOFT_COMMAND_BUFFER_SIZE,
 758                                           (dma_addr_t *)&dma_addr);
 759                 if (!sc) {
 760                         octeon_free_sc_buffer_pool(oct);
 761                         return 1;
 762                 }
 763
 764                 sc->dma_addr = dma_addr;
 765                 sc->size = SOFT_COMMAND_BUFFER_SIZE;
 766
 767                 list_add_tail(&sc->node, &oct->sc_buf_pool.head);
 768         }
 769
 770         return 0;
 771 }
 772
 773 int octeon_free_sc_done_list(struct octeon_device *oct)
 774 {
 775         struct octeon_response_list *done_sc_list, *zombie_sc_list;
 776         struct octeon_soft_command *sc;
 777         struct list_head *tmp, *tmp2;
 778         spinlock_t *sc_lists_lock; /* lock for response_list */
 779
 780         done_sc_list = &oct->response_list[OCTEON_DONE_SC_LIST];
 781         zombie_sc_list = &oct->response_list[OCTEON_ZOMBIE_SC_LIST];
 782
 783         if (!atomic_read(&done_sc_list->pending_req_count))
 784                 return 0;
 785
 786         sc_lists_lock = &oct->response_list[OCTEON_ORDERED_SC_LIST].lock;
 787
 788         spin_lock_bh(sc_lists_lock);
 789
 790         list_for_each_safe(tmp, tmp2, &done_sc_list->head) {
 791                 sc = list_entry(tmp, struct octeon_soft_command, node);
 792
 793                 if (READ_ONCE(sc->caller_is_done)) {
 794                         list_del(&sc->node);
 795                         atomic_dec(&done_sc_list->pending_req_count);
 796
 797                         if (*sc->status_word == COMPLETION_WORD_INIT) {
 798                                 /* timeout; move sc to zombie list */
 799                                 list_add_tail(&sc->node, &zombie_sc_list->head);
 800                                 atomic_inc(&zombie_sc_list->pending_req_count);
 801                         } else {
 802                                 octeon_free_soft_command(oct, sc);
 803                         }
 804                 }
 805         }
 806
 807         spin_unlock_bh(sc_lists_lock);
 808
 809         return 0;
 810 }
 811
 812 int octeon_free_sc_zombie_list(struct octeon_device *oct)
 813 {
 814         struct octeon_response_list *zombie_sc_list;
 815         struct octeon_soft_command *sc;
 816         struct list_head *tmp, *tmp2;
 817         spinlock_t *sc_lists_lock; /* lock for response_list */
 818
 819         zombie_sc_list = &oct->response_list[OCTEON_ZOMBIE_SC_LIST];
 820         sc_lists_lock = &oct->response_list[OCTEON_ORDERED_SC_LIST].lock;
 821
 822         spin_lock_bh(sc_lists_lock);
 823
 824         list_for_each_safe(tmp, tmp2, &zombie_sc_list->head) {
 825                 list_del(tmp);
 826                 atomic_dec(&zombie_sc_list->pending_req_count);
 827                 sc = list_entry(tmp, struct octeon_soft_command, node);
 828                 octeon_free_soft_command(oct, sc);
 829         }
 830
 831         spin_unlock_bh(sc_lists_lock);
 832
 833         return 0;
 834 }
 835
 836 int octeon_free_sc_buffer_pool(struct octeon_device *oct)
 837 {
 838         struct list_head *tmp, *tmp2;
 839         struct octeon_soft_command *sc;
 840
 841         octeon_free_sc_zombie_list(oct);
 842
 843         spin_lock_bh(&oct->sc_buf_pool.lock);
 844
 845         list_for_each_safe(tmp, tmp2, &oct->sc_buf_pool.head) {
 846                 list_del(tmp);
 847
 848                 sc = (struct octeon_soft_command *)tmp;
 849
 850                 lio_dma_free(oct, sc->size, sc, sc->dma_addr);
 851         }
 852
 853         INIT_LIST_HEAD(&oct->sc_buf_pool.head);
 854
 855         spin_unlock_bh(&oct->sc_buf_pool.lock);
 856
 857         return 0;
 858 }
 859
 860 struct octeon_soft_command *octeon_alloc_soft_command(struct octeon_device *oct,
 861                                                       u32 datasize,
 862                                                       u32 rdatasize,
 863                                                       u32 ctxsize)
 864 {
 865         u64 dma_addr;
 866         u32 size;
 867         u32 offset = sizeof(struct octeon_soft_command);
 868         struct octeon_soft_command *sc = NULL;
 869         struct list_head *tmp;
 870
 871         if (!rdatasize)
 872                 rdatasize = 16;
 873
 874         WARN_ON((offset + datasize + rdatasize + ctxsize) >
 875                SOFT_COMMAND_BUFFER_SIZE);
 876
 877         spin_lock_bh(&oct->sc_buf_pool.lock);
 878
 879         if (list_empty(&oct->sc_buf_pool.head)) {
 880                 spin_unlock_bh(&oct->sc_buf_pool.lock);
 881                 return NULL;
 882         }
 883
 884         list_for_each(tmp, &oct->sc_buf_pool.head)
 885                 break;
 886
 887         list_del(tmp);
 888
 889         atomic_inc(&oct->sc_buf_pool.alloc_buf_count);
 890
 891         spin_unlock_bh(&oct->sc_buf_pool.lock);
 892
 893         sc = (struct octeon_soft_command *)tmp;
 894
 895         dma_addr = sc->dma_addr;
 896         size = sc->size;
 897
 898         memset(sc, 0, sc->size);
 899
 900         sc->dma_addr = dma_addr;
 901         sc->size = size;
 902
 903         if (ctxsize) {
 904                 sc->ctxptr = (u8 *)sc + offset;
 905                 sc->ctxsize = ctxsize;
 906         }
 907
 908         /* Start data at 128 byte boundary */
 909         offset = (offset + ctxsize + 127) & 0xffffff80;
 910
 911         if (datasize) {
 912                 sc->virtdptr = (u8 *)sc + offset;
 913                 sc->dmadptr = dma_addr + offset;
 914                 sc->datasize = datasize;
 915         }
 916
 917         /* Start rdata at 128 byte boundary */
 918         offset = (offset + datasize + 127) & 0xffffff80;
 919
 920         if (rdatasize) {
 921                 WARN_ON(rdatasize < 16);
 922                 sc->virtrptr = (u8 *)sc + offset;
 923                 sc->dmarptr = dma_addr + offset;
 924                 sc->rdatasize = rdatasize;
 925                 sc->status_word = (u64 *)((u8 *)(sc->virtrptr) + rdatasize - 8);
 926         }
 927
 928         return sc;
 929 }
 930
 931 void octeon_free_soft_command(struct octeon_device *oct,
 932                               struct octeon_soft_command *sc)
 933 {
 934         spin_lock_bh(&oct->sc_buf_pool.lock);
 935
 936         list_add_tail(&sc->node, &oct->sc_buf_pool.head);
 937
 938         atomic_dec(&oct->sc_buf_pool.alloc_buf_count);
 939
 940         spin_unlock_bh(&oct->sc_buf_pool.lock);
 941 }