2 * Copyright (C) 2015 Cavium, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
9 #include <linux/acpi.h>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/pci.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/phy.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
22 #include "thunder_bgx.h"
24 #define DRV_NAME "thunder-BGX"
25 #define DRV_VERSION "1.0"
35 int lmacid; /* ID within BGX */
36 int lmacid_bd; /* ID on board */
37 struct net_device netdev;
38 struct phy_device *phydev;
39 unsigned int last_duplex;
40 unsigned int last_link;
41 unsigned int last_speed;
43 struct delayed_work dwork;
44 struct workqueue_struct *check_link;
49 struct lmac lmac[MAX_LMAC_PER_BGX];
53 void __iomem *reg_base;
59 static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
60 static int lmac_count; /* Total no of LMACs in system */
62 static int bgx_xaui_check_link(struct lmac *lmac);
64 /* Supported devices */
65 static const struct pci_device_id bgx_id_table[] = {
66 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
67 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_RGX) },
68 { 0, } /* end of table */
71 MODULE_AUTHOR("Cavium Inc");
72 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
73 MODULE_LICENSE("GPL v2");
74 MODULE_VERSION(DRV_VERSION);
75 MODULE_DEVICE_TABLE(pci, bgx_id_table);
77 /* The Cavium ThunderX network controller can *only* be found in SoCs
78 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
79 * registers on this platform are implicitly strongly ordered with respect
80 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
81 * with no memory barriers in this driver. The readq()/writeq() functions add
82 * explicit ordering operation which in this case are redundant, and only
86 /* Register read/write APIs */
87 static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
89 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
91 return readq_relaxed(addr);
94 static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
96 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
98 writeq_relaxed(val, addr);
101 static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
103 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
105 writeq_relaxed(val | readq_relaxed(addr), addr);
108 static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
114 reg_val = bgx_reg_read(bgx, lmac, reg);
115 if (zero && !(reg_val & mask))
117 if (!zero && (reg_val & mask))
119 usleep_range(1000, 2000);
125 /* Return number of BGX present in HW */
126 unsigned bgx_get_map(int node)
131 for (i = 0; i < MAX_BGX_PER_NODE; i++) {
132 if (bgx_vnic[(node * MAX_BGX_PER_NODE) + i])
138 EXPORT_SYMBOL(bgx_get_map);
140 /* Return number of LMAC configured for this BGX */
141 int bgx_get_lmac_count(int node, int bgx_idx)
145 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
147 return bgx->lmac_count;
151 EXPORT_SYMBOL(bgx_get_lmac_count);
153 /* Returns the current link status of LMAC */
154 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
156 struct bgx_link_status *link = (struct bgx_link_status *)status;
160 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
164 lmac = &bgx->lmac[lmacid];
165 link->mac_type = lmac->lmac_type;
166 link->link_up = lmac->link_up;
167 link->duplex = lmac->last_duplex;
168 link->speed = lmac->last_speed;
170 EXPORT_SYMBOL(bgx_get_lmac_link_state);
172 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
174 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
177 return bgx->lmac[lmacid].mac;
181 EXPORT_SYMBOL(bgx_get_lmac_mac);
183 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
185 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
190 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
192 EXPORT_SYMBOL(bgx_set_lmac_mac);
194 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
196 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
202 lmac = &bgx->lmac[lmacid];
204 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
206 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
208 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
209 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
212 xcv_setup_link(enable ? lmac->link_up : 0, lmac->last_speed);
214 EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
216 void bgx_lmac_get_pfc(int node, int bgx_idx, int lmacid, void *pause)
218 struct pfc *pfc = (struct pfc *)pause;
219 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
225 lmac = &bgx->lmac[lmacid];
229 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
230 pfc->fc_rx = cfg & RX_EN;
231 pfc->fc_tx = cfg & TX_EN;
234 EXPORT_SYMBOL(bgx_lmac_get_pfc);
236 void bgx_lmac_set_pfc(int node, int bgx_idx, int lmacid, void *pause)
238 struct pfc *pfc = (struct pfc *)pause;
239 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
245 lmac = &bgx->lmac[lmacid];
249 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_CBFC_CTL);
250 cfg &= ~(RX_EN | TX_EN);
251 cfg |= (pfc->fc_rx ? RX_EN : 0x00);
252 cfg |= (pfc->fc_tx ? TX_EN : 0x00);
253 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, cfg);
255 EXPORT_SYMBOL(bgx_lmac_set_pfc);
257 static void bgx_sgmii_change_link_state(struct lmac *lmac)
259 struct bgx *bgx = lmac->bgx;
264 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
266 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
268 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
269 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
272 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
273 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
274 port_cfg |= (lmac->last_duplex << 2);
276 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
279 switch (lmac->last_speed) {
281 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
282 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
283 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
284 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
285 misc_ctl |= 50; /* samp_pt */
286 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
287 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
290 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
291 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
292 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
293 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
294 misc_ctl |= 5; /* samp_pt */
295 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
296 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
299 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
300 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
301 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
302 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
303 misc_ctl |= 1; /* samp_pt */
304 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
305 if (lmac->last_duplex)
306 bgx_reg_write(bgx, lmac->lmacid,
307 BGX_GMP_GMI_TXX_BURST, 0);
309 bgx_reg_write(bgx, lmac->lmacid,
310 BGX_GMP_GMI_TXX_BURST, 8192);
315 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
316 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
318 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
322 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
324 if (bgx->is_rgx && (cmr_cfg & (CMR_PKT_RX_EN | CMR_PKT_TX_EN)))
325 xcv_setup_link(lmac->link_up, lmac->last_speed);
328 static void bgx_lmac_handler(struct net_device *netdev)
330 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
331 struct phy_device *phydev;
332 int link_changed = 0;
337 phydev = lmac->phydev;
339 if (!phydev->link && lmac->last_link)
343 (lmac->last_duplex != phydev->duplex ||
344 lmac->last_link != phydev->link ||
345 lmac->last_speed != phydev->speed)) {
349 lmac->last_link = phydev->link;
350 lmac->last_speed = phydev->speed;
351 lmac->last_duplex = phydev->duplex;
356 if (link_changed > 0)
357 lmac->link_up = true;
359 lmac->link_up = false;
362 bgx_sgmii_change_link_state(lmac);
364 bgx_xaui_check_link(lmac);
367 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
371 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
377 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
379 EXPORT_SYMBOL(bgx_get_rx_stats);
381 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
385 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
389 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
391 EXPORT_SYMBOL(bgx_get_tx_stats);
393 static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac)
397 while (bgx->lmac[lmac].dmac > 0) {
398 offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) +
399 (lmac * MAX_DMAC_PER_LMAC * sizeof(u64));
400 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0);
401 bgx->lmac[lmac].dmac--;
405 /* Configure BGX LMAC in internal loopback mode */
406 void bgx_lmac_internal_loopback(int node, int bgx_idx,
407 int lmac_idx, bool enable)
413 bgx = bgx_vnic[(node * MAX_BGX_PER_NODE) + bgx_idx];
417 lmac = &bgx->lmac[lmac_idx];
418 if (lmac->is_sgmii) {
419 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
421 cfg |= PCS_MRX_CTL_LOOPBACK1;
423 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
424 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
426 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
428 cfg |= SPU_CTL_LOOPBACK;
430 cfg &= ~SPU_CTL_LOOPBACK;
431 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
434 EXPORT_SYMBOL(bgx_lmac_internal_loopback);
436 static int bgx_lmac_sgmii_init(struct bgx *bgx, struct lmac *lmac)
438 int lmacid = lmac->lmacid;
441 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
442 /* max packet size */
443 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
445 /* Disable frame alignment if using preamble */
446 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
448 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
451 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
454 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
455 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
456 PCS_MRX_CTL_RESET, true)) {
457 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
461 /* power down, reset autoneg, autoneg enable */
462 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
463 cfg &= ~PCS_MRX_CTL_PWR_DN;
464 cfg |= (PCS_MRX_CTL_RST_AN | PCS_MRX_CTL_AN_EN);
465 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
467 if (lmac->lmac_type == BGX_MODE_QSGMII) {
468 /* Disable disparity check for QSGMII */
469 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL);
470 cfg &= ~PCS_MISC_CTL_DISP_EN;
471 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MISCX_CTL, cfg);
475 if (lmac->lmac_type == BGX_MODE_SGMII) {
476 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
477 PCS_MRX_STATUS_AN_CPT, false)) {
478 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
486 static int bgx_lmac_xaui_init(struct bgx *bgx, struct lmac *lmac)
489 int lmacid = lmac->lmacid;
492 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
493 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
494 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
499 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
501 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
503 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
504 /* Set interleaved running disparity for RXAUI */
505 if (lmac->lmac_type == BGX_MODE_RXAUI)
506 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
507 SPU_MISC_CTL_INTLV_RDISP);
509 /* Clear receive packet disable */
510 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
511 cfg &= ~SPU_MISC_CTL_RX_DIS;
512 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
514 /* clear all interrupts */
515 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
516 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
517 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
518 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
519 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
520 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
522 if (lmac->use_training) {
523 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
524 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
525 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
526 /* training enable */
527 bgx_reg_modify(bgx, lmacid,
528 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
531 /* Append FCS to each packet */
532 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
534 /* Disable forward error correction */
535 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
536 cfg &= ~SPU_FEC_CTL_FEC_EN;
537 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
539 /* Disable autoneg */
540 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
541 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
542 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
544 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
545 if (lmac->lmac_type == BGX_MODE_10G_KR)
547 else if (lmac->lmac_type == BGX_MODE_40G_KR)
550 cfg &= ~((1 << 23) | (1 << 24));
551 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
552 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
554 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
555 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
556 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
559 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
561 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
562 cfg &= ~SPU_CTL_LOW_POWER;
563 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
565 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
566 cfg &= ~SMU_TX_CTL_UNI_EN;
567 cfg |= SMU_TX_CTL_DIC_EN;
568 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
570 /* Enable receive and transmission of pause frames */
571 bgx_reg_write(bgx, lmacid, BGX_SMUX_CBFC_CTL, ((0xffffULL << 32) |
572 BCK_EN | DRP_EN | TX_EN | RX_EN));
573 /* Configure pause time and interval */
574 bgx_reg_write(bgx, lmacid,
575 BGX_SMUX_TX_PAUSE_PKT_TIME, DEFAULT_PAUSE_TIME);
576 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL);
578 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_PKT_INTERVAL,
579 cfg | (DEFAULT_PAUSE_TIME - 0x1000));
580 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_PAUSE_ZERO, 0x01);
582 /* take lmac_count into account */
583 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
584 /* max packet size */
585 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
590 static int bgx_xaui_check_link(struct lmac *lmac)
592 struct bgx *bgx = lmac->bgx;
593 int lmacid = lmac->lmacid;
594 int lmac_type = lmac->lmac_type;
597 if (lmac->use_training) {
598 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
599 if (!(cfg & (1ull << 13))) {
600 cfg = (1ull << 13) | (1ull << 14);
601 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
602 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
604 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
609 /* wait for PCS to come out of reset */
610 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
611 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
615 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
616 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
617 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
618 SPU_BR_STATUS_BLK_LOCK, false)) {
619 dev_err(&bgx->pdev->dev,
620 "SPU_BR_STATUS_BLK_LOCK not completed\n");
624 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
625 SPU_BX_STATUS_RX_ALIGN, false)) {
626 dev_err(&bgx->pdev->dev,
627 "SPU_BX_STATUS_RX_ALIGN not completed\n");
632 /* Clear rcvflt bit (latching high) and read it back */
633 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT)
634 bgx_reg_modify(bgx, lmacid,
635 BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
636 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
637 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
638 if (lmac->use_training) {
639 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
640 if (!(cfg & (1ull << 13))) {
641 cfg = (1ull << 13) | (1ull << 14);
642 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
643 cfg = bgx_reg_read(bgx, lmacid,
644 BGX_SPUX_BR_PMD_CRTL);
646 bgx_reg_write(bgx, lmacid,
647 BGX_SPUX_BR_PMD_CRTL, cfg);
654 /* Wait for BGX RX to be idle */
655 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
656 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
660 /* Wait for BGX TX to be idle */
661 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
662 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
666 /* Check for MAC RX faults */
667 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_CTL);
668 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */
669 cfg &= SMU_RX_CTL_STATUS;
673 /* Rx local/remote fault seen.
674 * Do lmac reinit to see if condition recovers
676 bgx_lmac_xaui_init(bgx, lmac);
681 static void bgx_poll_for_link(struct work_struct *work)
684 u64 spu_link, smu_link;
686 lmac = container_of(work, struct lmac, dwork.work);
688 /* Receive link is latching low. Force it high and verify it */
689 bgx_reg_modify(lmac->bgx, lmac->lmacid,
690 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
691 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
692 SPU_STATUS1_RCV_LNK, false);
694 spu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
695 smu_link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SMUX_RX_CTL);
697 if ((spu_link & SPU_STATUS1_RCV_LNK) &&
698 !(smu_link & SMU_RX_CTL_STATUS)) {
700 if (lmac->lmac_type == BGX_MODE_XLAUI)
701 lmac->last_speed = 40000;
703 lmac->last_speed = 10000;
704 lmac->last_duplex = 1;
707 lmac->last_speed = SPEED_UNKNOWN;
708 lmac->last_duplex = DUPLEX_UNKNOWN;
711 if (lmac->last_link != lmac->link_up) {
713 if (bgx_xaui_check_link(lmac)) {
714 /* Errors, clear link_up state */
716 lmac->last_speed = SPEED_UNKNOWN;
717 lmac->last_duplex = DUPLEX_UNKNOWN;
720 lmac->last_link = lmac->link_up;
723 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
726 static int phy_interface_mode(u8 lmac_type)
728 if (lmac_type == BGX_MODE_QSGMII)
729 return PHY_INTERFACE_MODE_QSGMII;
730 if (lmac_type == BGX_MODE_RGMII)
731 return PHY_INTERFACE_MODE_RGMII;
733 return PHY_INTERFACE_MODE_SGMII;
736 static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
741 lmac = &bgx->lmac[lmacid];
744 if ((lmac->lmac_type == BGX_MODE_SGMII) ||
745 (lmac->lmac_type == BGX_MODE_QSGMII) ||
746 (lmac->lmac_type == BGX_MODE_RGMII)) {
748 if (bgx_lmac_sgmii_init(bgx, lmac))
752 if (bgx_lmac_xaui_init(bgx, lmac))
756 if (lmac->is_sgmii) {
757 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
758 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
759 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
760 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
762 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
763 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
764 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
765 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
769 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
771 /* Restore default cfg, incase low level firmware changed it */
772 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
774 if ((lmac->lmac_type != BGX_MODE_XFI) &&
775 (lmac->lmac_type != BGX_MODE_XLAUI) &&
776 (lmac->lmac_type != BGX_MODE_40G_KR) &&
777 (lmac->lmac_type != BGX_MODE_10G_KR)) {
781 lmac->phydev->dev_flags = 0;
783 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
785 phy_interface_mode(lmac->lmac_type)))
788 phy_start_aneg(lmac->phydev);
790 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
792 if (!lmac->check_link)
794 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
795 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
801 static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
806 lmac = &bgx->lmac[lmacid];
807 if (lmac->check_link) {
808 /* Destroy work queue */
809 cancel_delayed_work_sync(&lmac->dwork);
810 destroy_workqueue(lmac->check_link);
813 /* Disable packet reception */
814 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
815 cfg &= ~CMR_PKT_RX_EN;
816 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
818 /* Give chance for Rx/Tx FIFO to get drained */
819 bgx_poll_reg(bgx, lmacid, BGX_CMRX_RX_FIFO_LEN, (u64)0x1FFF, true);
820 bgx_poll_reg(bgx, lmacid, BGX_CMRX_TX_FIFO_LEN, (u64)0x3FFF, true);
822 /* Disable packet transmission */
823 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
824 cfg &= ~CMR_PKT_TX_EN;
825 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
827 /* Disable serdes lanes */
829 bgx_reg_modify(bgx, lmacid,
830 BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
832 bgx_reg_modify(bgx, lmacid,
833 BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_PWR_DN);
836 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
838 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
840 bgx_flush_dmac_addrs(bgx, lmacid);
842 if ((lmac->lmac_type != BGX_MODE_XFI) &&
843 (lmac->lmac_type != BGX_MODE_XLAUI) &&
844 (lmac->lmac_type != BGX_MODE_40G_KR) &&
845 (lmac->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
846 phy_disconnect(lmac->phydev);
851 static void bgx_init_hw(struct bgx *bgx)
856 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
857 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
858 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
860 /* Set lmac type and lane2serdes mapping */
861 for (i = 0; i < bgx->lmac_count; i++) {
862 lmac = &bgx->lmac[i];
863 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
864 (lmac->lmac_type << 8) | lmac->lane_to_sds);
865 bgx->lmac[i].lmacid_bd = lmac_count;
869 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
870 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
872 /* Set the backpressure AND mask */
873 for (i = 0; i < bgx->lmac_count; i++)
874 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
875 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
876 (i * MAX_BGX_CHANS_PER_LMAC));
878 /* Disable all MAC filtering */
879 for (i = 0; i < RX_DMAC_COUNT; i++)
880 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
882 /* Disable MAC steering (NCSI traffic) */
883 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
884 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00);
887 static u8 bgx_get_lane2sds_cfg(struct bgx *bgx, struct lmac *lmac)
889 return (u8)(bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG) & 0xFF);
892 static void bgx_print_qlm_mode(struct bgx *bgx, u8 lmacid)
894 struct device *dev = &bgx->pdev->dev;
899 if (lmacid > bgx->max_lmac)
902 lmac = &bgx->lmac[lmacid];
903 dlm = (lmacid / 2) + (bgx->bgx_id * 2);
905 sprintf(str, "BGX%d QLM mode", bgx->bgx_id);
907 sprintf(str, "BGX%d DLM%d mode", bgx->bgx_id, dlm);
909 switch (lmac->lmac_type) {
911 dev_info(dev, "%s: SGMII\n", (char *)str);
914 dev_info(dev, "%s: XAUI\n", (char *)str);
917 dev_info(dev, "%s: RXAUI\n", (char *)str);
920 if (!lmac->use_training)
921 dev_info(dev, "%s: XFI\n", (char *)str);
923 dev_info(dev, "%s: 10G_KR\n", (char *)str);
926 if (!lmac->use_training)
927 dev_info(dev, "%s: XLAUI\n", (char *)str);
929 dev_info(dev, "%s: 40G_KR4\n", (char *)str);
931 case BGX_MODE_QSGMII:
933 (bgx_get_lane2sds_cfg(bgx, lmac) != lmacid))
936 (bgx_get_lane2sds_cfg(bgx, lmac) == lmacid))
938 dev_info(dev, "%s: QSGMII\n", (char *)str);
941 dev_info(dev, "%s: RGMII\n", (char *)str);
943 case BGX_MODE_INVALID:
949 static void lmac_set_lane2sds(struct bgx *bgx, struct lmac *lmac)
951 switch (lmac->lmac_type) {
954 lmac->lane_to_sds = lmac->lmacid;
959 lmac->lane_to_sds = 0xE4;
962 lmac->lane_to_sds = (lmac->lmacid) ? 0xE : 0x4;
964 case BGX_MODE_QSGMII:
965 /* There is no way to determine if DLM0/2 is QSGMII or
966 * DLM1/3 is configured to QSGMII as bootloader will
967 * configure all LMACs, so take whatever is configured
968 * by low level firmware.
970 lmac->lane_to_sds = bgx_get_lane2sds_cfg(bgx, lmac);
973 lmac->lane_to_sds = 0;
978 static void lmac_set_training(struct bgx *bgx, struct lmac *lmac, int lmacid)
980 if ((lmac->lmac_type != BGX_MODE_10G_KR) &&
981 (lmac->lmac_type != BGX_MODE_40G_KR)) {
982 lmac->use_training = 0;
986 lmac->use_training = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL) &
987 SPU_PMD_CRTL_TRAIN_EN;
990 static void bgx_set_lmac_config(struct bgx *bgx, u8 idx)
998 lmac = &bgx->lmac[idx];
1000 if (!bgx->is_dlm || bgx->is_rgx) {
1001 /* Read LMAC0 type to figure out QLM mode
1002 * This is configured by low level firmware
1004 cmr_cfg = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
1005 lmac->lmac_type = (cmr_cfg >> 8) & 0x07;
1007 lmac->lmac_type = BGX_MODE_RGMII;
1008 lmac_set_training(bgx, lmac, 0);
1009 lmac_set_lane2sds(bgx, lmac);
1013 /* On 81xx BGX can be split across 2 DLMs
1014 * firmware programs lmac_type of LMAC0 and LMAC2
1016 if ((idx == 0) || (idx == 2)) {
1017 cmr_cfg = bgx_reg_read(bgx, idx, BGX_CMRX_CFG);
1018 lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
1019 lane_to_sds = (u8)(cmr_cfg & 0xFF);
1020 /* Check if config is not reset value */
1021 if ((lmac_type == 0) && (lane_to_sds == 0xE4))
1022 lmac->lmac_type = BGX_MODE_INVALID;
1024 lmac->lmac_type = lmac_type;
1025 lmac_set_training(bgx, lmac, lmac->lmacid);
1026 lmac_set_lane2sds(bgx, lmac);
1028 olmac = &bgx->lmac[idx + 1];
1029 /* Check if other LMAC on the same DLM is already configured by
1030 * firmware, if so use the same config or else set as same, as
1032 * This check is needed as on 80xx only one lane of each of the
1033 * DLM of BGX0 is used, so have to rely on firmware for
1034 * distingushing 80xx from 81xx.
1036 cmr_cfg = bgx_reg_read(bgx, idx + 1, BGX_CMRX_CFG);
1037 lmac_type = (u8)((cmr_cfg >> 8) & 0x07);
1038 lane_to_sds = (u8)(cmr_cfg & 0xFF);
1039 if ((lmac_type == 0) && (lane_to_sds == 0xE4)) {
1040 olmac->lmac_type = lmac->lmac_type;
1041 lmac_set_lane2sds(bgx, olmac);
1043 olmac->lmac_type = lmac_type;
1044 olmac->lane_to_sds = lane_to_sds;
1046 lmac_set_training(bgx, olmac, olmac->lmacid);
1050 static bool is_dlm0_in_bgx_mode(struct bgx *bgx)
1057 lmac = &bgx->lmac[0];
1058 if (lmac->lmac_type == BGX_MODE_INVALID)
1064 static void bgx_get_qlm_mode(struct bgx *bgx)
1067 struct lmac *lmac01;
1068 struct lmac *lmac23;
1071 /* Init all LMAC's type to invalid */
1072 for (idx = 0; idx < bgx->max_lmac; idx++) {
1073 lmac = &bgx->lmac[idx];
1075 lmac->lmac_type = BGX_MODE_INVALID;
1076 lmac->use_training = false;
1079 /* It is assumed that low level firmware sets this value */
1080 bgx->lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
1081 if (bgx->lmac_count > bgx->max_lmac)
1082 bgx->lmac_count = bgx->max_lmac;
1084 for (idx = 0; idx < bgx->max_lmac; idx++)
1085 bgx_set_lmac_config(bgx, idx);
1087 if (!bgx->is_dlm || bgx->is_rgx) {
1088 bgx_print_qlm_mode(bgx, 0);
1092 if (bgx->lmac_count) {
1093 bgx_print_qlm_mode(bgx, 0);
1094 bgx_print_qlm_mode(bgx, 2);
1097 /* If DLM0 is not in BGX mode then LMAC0/1 have
1098 * to be configured with serdes lanes of DLM1
1100 if (is_dlm0_in_bgx_mode(bgx) || (bgx->lmac_count > 2))
1102 for (idx = 0; idx < bgx->lmac_count; idx++) {
1103 lmac01 = &bgx->lmac[idx];
1104 lmac23 = &bgx->lmac[idx + 2];
1105 lmac01->lmac_type = lmac23->lmac_type;
1106 lmac01->lane_to_sds = lmac23->lane_to_sds;
1112 static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev,
1118 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
1119 "mac-address", mac, ETH_ALEN);
1123 if (!is_valid_ether_addr(mac)) {
1124 dev_err(dev, "MAC address invalid: %pM\n", mac);
1129 dev_info(dev, "MAC address set to: %pM\n", mac);
1131 memcpy(dst, mac, ETH_ALEN);
1136 /* Currently only sets the MAC address. */
1137 static acpi_status bgx_acpi_register_phy(acpi_handle handle,
1138 u32 lvl, void *context, void **rv)
1140 struct bgx *bgx = context;
1141 struct device *dev = &bgx->pdev->dev;
1142 struct acpi_device *adev;
1144 if (acpi_bus_get_device(handle, &adev))
1147 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->acpi_lmac_idx].mac);
1149 SET_NETDEV_DEV(&bgx->lmac[bgx->acpi_lmac_idx].netdev, dev);
1151 bgx->lmac[bgx->acpi_lmac_idx].lmacid = bgx->acpi_lmac_idx;
1152 bgx->acpi_lmac_idx++; /* move to next LMAC */
1157 static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
1158 void *context, void **ret_val)
1160 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1161 struct bgx *bgx = context;
1164 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
1165 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
1166 pr_warn("Invalid link device\n");
1170 if (strncmp(string.pointer, bgx_sel, 4))
1173 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
1174 bgx_acpi_register_phy, NULL, bgx, NULL);
1176 kfree(string.pointer);
1177 return AE_CTRL_TERMINATE;
1180 static int bgx_init_acpi_phy(struct bgx *bgx)
1182 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
1188 static int bgx_init_acpi_phy(struct bgx *bgx)
1193 #endif /* CONFIG_ACPI */
1195 #if IS_ENABLED(CONFIG_OF_MDIO)
1197 static int bgx_init_of_phy(struct bgx *bgx)
1199 struct fwnode_handle *fwn;
1200 struct device_node *node = NULL;
1203 device_for_each_child_node(&bgx->pdev->dev, fwn) {
1204 struct phy_device *pd;
1205 struct device_node *phy_np;
1208 /* Should always be an OF node. But if it is not, we
1209 * cannot handle it, so exit the loop.
1211 node = to_of_node(fwn);
1215 mac = of_get_mac_address(node);
1217 ether_addr_copy(bgx->lmac[lmac].mac, mac);
1219 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
1220 bgx->lmac[lmac].lmacid = lmac;
1222 phy_np = of_parse_phandle(node, "phy-handle", 0);
1223 /* If there is no phy or defective firmware presents
1224 * this cortina phy, for which there is no driver
1225 * support, ignore it.
1228 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) {
1229 /* Wait until the phy drivers are available */
1230 pd = of_phy_find_device(phy_np);
1233 bgx->lmac[lmac].phydev = pd;
1237 if (lmac == bgx->max_lmac) {
1245 /* We are bailing out, try not to leak device reference counts
1246 * for phy devices we may have already found.
1249 if (bgx->lmac[lmac].phydev) {
1250 put_device(&bgx->lmac[lmac].phydev->mdio.dev);
1251 bgx->lmac[lmac].phydev = NULL;
1256 return -EPROBE_DEFER;
1261 static int bgx_init_of_phy(struct bgx *bgx)
1266 #endif /* CONFIG_OF_MDIO */
1268 static int bgx_init_phy(struct bgx *bgx)
1271 return bgx_init_acpi_phy(bgx);
1273 return bgx_init_of_phy(bgx);
1276 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1279 struct device *dev = &pdev->dev;
1280 struct bgx *bgx = NULL;
1284 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1289 pci_set_drvdata(pdev, bgx);
1291 err = pci_enable_device(pdev);
1293 dev_err(dev, "Failed to enable PCI device\n");
1294 pci_set_drvdata(pdev, NULL);
1298 err = pci_request_regions(pdev, DRV_NAME);
1300 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1301 goto err_disable_device;
1304 /* MAP configuration registers */
1305 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1306 if (!bgx->reg_base) {
1307 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1309 goto err_release_regions;
1312 pci_read_config_word(pdev, PCI_DEVICE_ID, &sdevid);
1313 if (sdevid != PCI_DEVICE_ID_THUNDER_RGX) {
1314 bgx->bgx_id = (pci_resource_start(pdev,
1315 PCI_CFG_REG_BAR_NUM) >> 24) & BGX_ID_MASK;
1316 bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_NODE;
1317 bgx->max_lmac = MAX_LMAC_PER_BGX;
1318 bgx_vnic[bgx->bgx_id] = bgx;
1322 bgx->bgx_id = MAX_BGX_PER_CN81XX - 1;
1323 bgx_vnic[bgx->bgx_id] = bgx;
1327 /* On 81xx all are DLMs and on 83xx there are 3 BGX QLMs and one
1328 * BGX i.e BGX2 can be split across 2 DLMs.
1330 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &sdevid);
1331 if ((sdevid == PCI_SUBSYS_DEVID_81XX_BGX) ||
1332 ((sdevid == PCI_SUBSYS_DEVID_83XX_BGX) && (bgx->bgx_id == 2)))
1335 bgx_get_qlm_mode(bgx);
1337 err = bgx_init_phy(bgx);
1343 /* Enable all LMACs */
1344 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1345 err = bgx_lmac_enable(bgx, lmac);
1347 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1350 bgx_lmac_disable(bgx, --lmac);
1358 bgx_vnic[bgx->bgx_id] = NULL;
1359 err_release_regions:
1360 pci_release_regions(pdev);
1362 pci_disable_device(pdev);
1363 pci_set_drvdata(pdev, NULL);
1367 static void bgx_remove(struct pci_dev *pdev)
1369 struct bgx *bgx = pci_get_drvdata(pdev);
1372 /* Disable all LMACs */
1373 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1374 bgx_lmac_disable(bgx, lmac);
1376 bgx_vnic[bgx->bgx_id] = NULL;
1377 pci_release_regions(pdev);
1378 pci_disable_device(pdev);
1379 pci_set_drvdata(pdev, NULL);
1382 static struct pci_driver bgx_driver = {
1384 .id_table = bgx_id_table,
1386 .remove = bgx_remove,
1389 static int __init bgx_init_module(void)
1391 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1393 return pci_register_driver(&bgx_driver);
1396 static void __exit bgx_cleanup_module(void)
1398 pci_unregister_driver(&bgx_driver);
1401 module_init(bgx_init_module);
1402 module_exit(bgx_cleanup_module);