2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/bitops.h>
41 #include <linux/cache.h>
42 #include <linux/interrupt.h>
43 #include <linux/list.h>
44 #include <linux/netdevice.h>
45 #include <linux/pci.h>
46 #include <linux/spinlock.h>
47 #include <linux/timer.h>
48 #include <linux/vmalloc.h>
49 #include <linux/rhashtable.h>
50 #include <linux/etherdevice.h>
51 #include <linux/net_tstamp.h>
52 #include <linux/ptp_clock_kernel.h>
53 #include <linux/ptp_classify.h>
54 #include <linux/crash_dump.h>
55 #include <linux/thermal.h>
57 #include "t4_chip_type.h"
58 #include "cxgb4_uld.h"
60 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
61 extern struct list_head adapter_list;
62 extern struct mutex uld_mutex;
64 /* Suspend an Ethernet Tx queue with fewer available descriptors than this.
65 * This is the same as calc_tx_descs() for a TSO packet with
66 * nr_frags == MAX_SKB_FRAGS.
68 #define ETHTXQ_STOP_THRES \
69 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8))
72 MAX_NPORTS = 4, /* max # of ports */
73 SERNUM_LEN = 24, /* Serial # length */
74 EC_LEN = 16, /* E/C length */
75 ID_LEN = 16, /* ID length */
76 PN_LEN = 16, /* Part Number length */
77 MACADDR_LEN = 12, /* MAC Address length */
81 T4_REGMAP_SIZE = (160 * 1024),
82 T5_REGMAP_SIZE = (332 * 1024),
95 MEMWIN0_APERTURE = 2048,
96 MEMWIN0_BASE = 0x1b800,
97 MEMWIN1_APERTURE = 32768,
98 MEMWIN1_BASE = 0x28000,
99 MEMWIN1_BASE_T5 = 0x52000,
100 MEMWIN2_APERTURE = 65536,
101 MEMWIN2_BASE = 0x30000,
102 MEMWIN2_APERTURE_T5 = 131072,
103 MEMWIN2_BASE_T5 = 0x60000,
121 PAUSE_AUTONEG = 1 << 2
125 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
126 FEC_RS = 1 << 1, /* Reed-Solomon */
127 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
131 u64 tx_octets; /* total # of octets in good frames */
132 u64 tx_frames; /* all good frames */
133 u64 tx_bcast_frames; /* all broadcast frames */
134 u64 tx_mcast_frames; /* all multicast frames */
135 u64 tx_ucast_frames; /* all unicast frames */
136 u64 tx_error_frames; /* all error frames */
138 u64 tx_frames_64; /* # of Tx frames in a particular range */
139 u64 tx_frames_65_127;
140 u64 tx_frames_128_255;
141 u64 tx_frames_256_511;
142 u64 tx_frames_512_1023;
143 u64 tx_frames_1024_1518;
144 u64 tx_frames_1519_max;
146 u64 tx_drop; /* # of dropped Tx frames */
147 u64 tx_pause; /* # of transmitted pause frames */
148 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
149 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
150 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
151 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
152 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
153 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
154 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
155 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
157 u64 rx_octets; /* total # of octets in good frames */
158 u64 rx_frames; /* all good frames */
159 u64 rx_bcast_frames; /* all broadcast frames */
160 u64 rx_mcast_frames; /* all multicast frames */
161 u64 rx_ucast_frames; /* all unicast frames */
162 u64 rx_too_long; /* # of frames exceeding MTU */
163 u64 rx_jabber; /* # of jabber frames */
164 u64 rx_fcs_err; /* # of received frames with bad FCS */
165 u64 rx_len_err; /* # of received frames with length error */
166 u64 rx_symbol_err; /* symbol errors */
167 u64 rx_runt; /* # of short frames */
169 u64 rx_frames_64; /* # of Rx frames in a particular range */
170 u64 rx_frames_65_127;
171 u64 rx_frames_128_255;
172 u64 rx_frames_256_511;
173 u64 rx_frames_512_1023;
174 u64 rx_frames_1024_1518;
175 u64 rx_frames_1519_max;
177 u64 rx_pause; /* # of received pause frames */
178 u64 rx_ppp0; /* # of received PPP prio 0 frames */
179 u64 rx_ppp1; /* # of received PPP prio 1 frames */
180 u64 rx_ppp2; /* # of received PPP prio 2 frames */
181 u64 rx_ppp3; /* # of received PPP prio 3 frames */
182 u64 rx_ppp4; /* # of received PPP prio 4 frames */
183 u64 rx_ppp5; /* # of received PPP prio 5 frames */
184 u64 rx_ppp6; /* # of received PPP prio 6 frames */
185 u64 rx_ppp7; /* # of received PPP prio 7 frames */
187 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
188 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
189 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
190 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
191 u64 rx_trunc0; /* buffer-group 0 truncated packets */
192 u64 rx_trunc1; /* buffer-group 1 truncated packets */
193 u64 rx_trunc2; /* buffer-group 2 truncated packets */
194 u64 rx_trunc3; /* buffer-group 3 truncated packets */
197 struct lb_port_stats {
210 u64 frames_1024_1518;
225 struct tp_tcp_stats {
229 u64 tcp_retrans_segs;
232 struct tp_usm_stats {
238 struct tp_fcoe_stats {
244 struct tp_err_stats {
248 u32 tnl_cong_drops[4];
249 u32 ofld_chan_drops[4];
251 u32 ofld_vlan_drops[4];
257 struct tp_cpl_stats {
262 struct tp_rdma_stats {
268 u32 hps; /* host page size for our PF/VF */
269 u32 eq_qpp; /* egress queues/page for our PF/VF */
270 u32 iq_qpp; /* egress queues/page for our PF/VF */
274 unsigned int tre; /* log2 of core clocks per TP tick */
275 unsigned int la_mask; /* what events are recorded by TP LA */
276 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
279 uint32_t dack_re; /* DACK timer resolution */
280 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
282 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
284 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
286 /* cached TP_OUT_CONFIG compressed error vector
287 * and passing outer header info for encapsulated packets.
291 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
292 * subset of the set of fields which may be present in the Compressed
293 * Filter Tuple portion of filters and TCP TCB connections. The
294 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
295 * Since a variable number of fields may or may not be present, their
296 * shifted field positions within the Compressed Filter Tuple may
297 * vary, or not even be present if the field isn't selected in
298 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
299 * places we store their offsets here, or a -1 if the field isn't
313 u64 hash_filter_mask;
319 u8 sn[SERNUM_LEN + 1];
322 u8 na[MACADDR_LEN + 1];
325 /* Maximum resources provisioned for a PCI PF.
327 struct pf_resources {
328 unsigned int nvi; /* N virtual interfaces */
329 unsigned int neq; /* N egress Qs */
330 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
331 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
332 unsigned int niq; /* N ingress Qs */
333 unsigned int tc; /* PCI-E traffic class */
334 unsigned int pmask; /* port access rights mask */
335 unsigned int nexactf; /* N exact MPS filters */
336 unsigned int r_caps; /* read capabilities */
337 unsigned int wx_caps; /* write/execute capabilities */
341 unsigned int vpd_cap_addr;
346 struct devlog_params {
347 u32 memtype; /* which memory (EDC0, EDC1, MC) */
348 u32 start; /* start of log in firmware memory */
349 u32 size; /* size of log */
352 /* Stores chip specific parameters */
353 struct arch_specific_params {
356 u8 cng_ch_bits_log; /* congestion channel map bits width */
363 struct adapter_params {
364 struct sge_params sge;
366 struct vpd_params vpd;
367 struct pf_resources pfres;
368 struct pci_params pci;
369 struct devlog_params devlog;
370 enum pcie_memwin drv_memwin;
372 unsigned int cim_la_size;
374 unsigned int sf_size; /* serial flash size in bytes */
375 unsigned int sf_nsec; /* # of flash sectors */
377 unsigned int fw_vers; /* firmware version */
378 unsigned int bs_vers; /* bootstrap version */
379 unsigned int tp_vers; /* TP microcode version */
380 unsigned int er_vers; /* expansion ROM version */
381 unsigned int scfg_vers; /* Serial Configuration version */
382 unsigned int vpd_vers; /* VPD Version */
385 unsigned short mtus[NMTUS];
386 unsigned short a_wnd[NCCTRL_WIN];
387 unsigned short b_wnd[NCCTRL_WIN];
389 unsigned char nports; /* # of ethernet ports */
390 unsigned char portvec;
391 enum chip_type chip; /* chip code */
392 struct arch_specific_params arch; /* chip specific params */
393 unsigned char offload;
394 unsigned char crypto; /* HW capability for crypto */
395 unsigned char ethofld; /* QoS support */
397 unsigned char bypass;
398 unsigned char hash_filter;
400 unsigned int ofldq_wr_cred;
401 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
403 unsigned int nsched_cls; /* number of traffic classes */
404 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
405 unsigned int max_ird_adapter; /* Max read depth per adapter */
406 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
407 u8 fw_caps_support; /* 32-bit Port Capabilities */
408 bool filter2_wr_support; /* FW support for FILTER2_WR */
409 unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */
411 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is
414 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */
415 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */
416 bool write_cmpl_support; /* FW supports WRITE_CMPL */
419 /* State needed to monitor the forward progress of SGE Ingress DMA activities
420 * and possible hangs.
422 struct sge_idma_monitor_state {
423 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
424 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
425 unsigned int idma_state[2]; /* IDMA Hang detect state */
426 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
427 unsigned int idma_warn[2]; /* time to warning in HZ */
430 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
431 * The access and execute times are signed in order to accommodate negative
435 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */
436 u64 timestamp; /* OS-dependent timestamp */
437 u32 seqno; /* sequence number */
438 s16 access; /* time (ms) to access mailbox */
439 s16 execute; /* time (ms) to execute */
442 struct mbox_cmd_log {
443 unsigned int size; /* number of entries in the log */
444 unsigned int cursor; /* next position in the log to write */
445 u32 seqno; /* next sequence number */
446 /* variable length mailbox command log starts here */
449 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
450 * return a pointer to the specified entry.
452 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
453 unsigned int entry_idx)
455 return &((struct mbox_cmd *)&(log)[1])[entry_idx];
458 #include "t4fw_api.h"
460 #define FW_VERSION(chip) ( \
461 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
462 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
463 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
464 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
465 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
471 struct fw_hdr fw_hdr;
474 struct trace_params {
475 u32 data[TRACE_LEN / 4];
476 u32 mask[TRACE_LEN / 4];
477 unsigned short snap_len;
478 unsigned short min_len;
479 unsigned char skip_ofst;
480 unsigned char skip_len;
481 unsigned char invert;
485 /* Firmware Port Capabilities types. */
487 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
488 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
491 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
492 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
493 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
497 fw_port_cap32_t pcaps; /* link capabilities */
498 fw_port_cap32_t def_acaps; /* default advertised capabilities */
499 fw_port_cap32_t acaps; /* advertised capabilities */
500 fw_port_cap32_t lpacaps; /* peer advertised capabilities */
502 fw_port_cap32_t speed_caps; /* speed(s) user has requested */
503 unsigned int speed; /* actual link speed (Mb/s) */
505 enum cc_pause requested_fc; /* flow control user has requested */
506 enum cc_pause fc; /* actual link flow control */
508 enum cc_fec requested_fec; /* Forward Error Correction: */
509 enum cc_fec fec; /* requested and actual in use */
511 unsigned char autoneg; /* autonegotiating? */
513 unsigned char link_ok; /* link up? */
514 unsigned char link_down_rc; /* link down reason */
516 bool new_module; /* ->OS Transceiver Module inserted */
517 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */
520 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
523 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
524 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */
525 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
529 MAX_TXQ_ENTRIES = 16384,
530 MAX_CTRL_TXQ_ENTRIES = 1024,
531 MAX_RSPQ_ENTRIES = 16384,
532 MAX_RX_BUFFERS = 16384,
533 MIN_TXQ_ENTRIES = 32,
534 MIN_CTRL_TXQ_ENTRIES = 32,
535 MIN_RSPQ_ENTRIES = 128,
540 MAX_TXQ_DESC_SIZE = 64,
541 MAX_RXQ_DESC_SIZE = 128,
542 MAX_FL_DESC_SIZE = 8,
543 MAX_CTRL_TXQ_DESC_SIZE = 64,
547 INGQ_EXTRAS = 2, /* firmware event queue and */
548 /* forwarded interrupts */
549 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS,
553 PRIV_FLAG_PORT_TX_VM_BIT,
556 #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT)
558 #define PRIV_FLAGS_ADAP 0
559 #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM
564 #include "cxgb4_dcb.h"
566 #ifdef CONFIG_CHELSIO_T4_FCOE
567 #include "cxgb4_fcoe.h"
568 #endif /* CONFIG_CHELSIO_T4_FCOE */
571 struct adapter *adapter;
573 int xact_addr_filt; /* index of exact MAC address filter */
574 u16 rss_size; /* size of VI's RSS table slice */
576 enum fw_port_type port_type;
580 u8 lport; /* associated offload logical port */
581 u8 nqsets; /* # of qsets */
582 u8 first_qset; /* index of first qset */
584 struct link_config link_cfg;
586 struct port_stats stats_base;
587 #ifdef CONFIG_CHELSIO_T4_DCB
588 struct port_dcb_info dcb; /* Data Center Bridging support */
590 #ifdef CONFIG_CHELSIO_T4_FCOE
591 struct cxgb_fcoe fcoe;
592 #endif /* CONFIG_CHELSIO_T4_FCOE */
593 bool rxtstamp; /* Enable TS */
594 struct hwtstamp_config tstamp_config;
596 struct sched_table *sched_tbl;
599 /* viid and smt fields either returned by fw
600 * or decoded by parsing viid by driver.
607 bool tc_block_shared;
613 enum { /* adapter flags */
614 CXGB4_FULL_INIT_DONE = (1 << 0),
615 CXGB4_DEV_ENABLED = (1 << 1),
616 CXGB4_USING_MSI = (1 << 2),
617 CXGB4_USING_MSIX = (1 << 3),
618 CXGB4_FW_OK = (1 << 4),
619 CXGB4_RSS_TNLALLLOOKUP = (1 << 5),
620 CXGB4_USING_SOFT_PARAMS = (1 << 6),
621 CXGB4_MASTER_PF = (1 << 7),
622 CXGB4_FW_OFLD_CONN = (1 << 9),
623 CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10),
624 CXGB4_SHUTTING_DOWN = (1 << 11),
625 CXGB4_SGE_DBQ_TIMER = (1 << 12),
629 ULP_CRYPTO_LOOKASIDE = 1 << 0,
630 ULP_CRYPTO_IPSEC_INLINE = 1 << 1,
635 struct sge_fl { /* SGE free-buffer queue state */
636 unsigned int avail; /* # of available Rx buffers */
637 unsigned int pend_cred; /* new buffers since last FL DB ring */
638 unsigned int cidx; /* consumer index */
639 unsigned int pidx; /* producer index */
640 unsigned long alloc_failed; /* # of times buffer allocation failed */
641 unsigned long large_alloc_failed;
642 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */
643 unsigned long low; /* # of times momentarily starving */
644 unsigned long starving;
646 unsigned int cntxt_id; /* SGE context id for the free list */
647 unsigned int size; /* capacity of free list */
648 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
649 __be64 *desc; /* address of HW Rx descriptor ring */
650 dma_addr_t addr; /* bus address of HW ring start */
651 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
652 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
655 /* A packet gather list */
657 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */
658 struct page_frag frags[MAX_SKB_FRAGS];
659 void *va; /* virtual address of first byte */
660 unsigned int nfrags; /* # of fragments */
661 unsigned int tot_len; /* total length of fragments */
664 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
665 const struct pkt_gl *gl);
666 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
667 /* LRO related declarations for ULD */
669 #define MAX_LRO_SESSIONS 64
670 u8 lro_session_cnt; /* # of sessions to aggregate */
671 unsigned long lro_pkts; /* # of LRO super packets */
672 unsigned long lro_merged; /* # of wire packets merged by LRO */
673 struct sk_buff_head lroq; /* list of aggregated sessions */
676 struct sge_rspq { /* state for an SGE response queue */
677 struct napi_struct napi;
678 const __be64 *cur_desc; /* current descriptor in queue */
679 unsigned int cidx; /* consumer index */
680 u8 gen; /* current generation bit */
681 u8 intr_params; /* interrupt holdoff parameters */
682 u8 next_intr_params; /* holdoff params for next interrupt */
684 u8 pktcnt_idx; /* interrupt packet threshold */
685 u8 uld; /* ULD handling this queue */
686 u8 idx; /* queue index within its group */
687 int offset; /* offset into current Rx buffer */
688 u16 cntxt_id; /* SGE context id for the response q */
689 u16 abs_id; /* absolute SGE id for the response q */
690 __be64 *desc; /* address of HW response ring */
691 dma_addr_t phys_addr; /* physical address of the ring */
692 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
693 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
694 unsigned int iqe_len; /* entry size */
695 unsigned int size; /* capacity of response queue */
696 struct adapter *adap;
697 struct net_device *netdev; /* associated net device */
698 rspq_handler_t handler;
699 rspq_flush_handler_t flush_handler;
700 struct t4_lro_mgr lro_mgr;
703 struct sge_eth_stats { /* Ethernet queue statistics */
704 unsigned long pkts; /* # of ethernet packets */
705 unsigned long lro_pkts; /* # of LRO super packets */
706 unsigned long lro_merged; /* # of wire packets merged by LRO */
707 unsigned long rx_cso; /* # of Rx checksum offloads */
708 unsigned long vlan_ex; /* # of Rx VLAN extractions */
709 unsigned long rx_drops; /* # of packets dropped due to no mem */
710 unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */
713 struct sge_eth_rxq { /* SW Ethernet Rx queue */
714 struct sge_rspq rspq;
716 struct sge_eth_stats stats;
717 struct msix_info *msix;
718 } ____cacheline_aligned_in_smp;
720 struct sge_ofld_stats { /* offload queue statistics */
721 unsigned long pkts; /* # of packets */
722 unsigned long imm; /* # of immediate-data packets */
723 unsigned long an; /* # of asynchronous notifications */
724 unsigned long nomem; /* # of responses deferred due to no mem */
727 struct sge_ofld_rxq { /* SW offload Rx queue */
728 struct sge_rspq rspq;
730 struct sge_ofld_stats stats;
731 struct msix_info *msix;
732 } ____cacheline_aligned_in_smp;
741 unsigned int in_use; /* # of in-use Tx descriptors */
742 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */
743 unsigned int size; /* # of descriptors */
744 unsigned int cidx; /* SW consumer index */
745 unsigned int pidx; /* producer index */
746 unsigned long stops; /* # of times q has been stopped */
747 unsigned long restarts; /* # of queue restarts */
748 unsigned int cntxt_id; /* SGE context id for the Tx q */
749 struct tx_desc *desc; /* address of HW Tx descriptor ring */
750 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
751 struct sge_qstat *stat; /* queue status entry */
752 dma_addr_t phys_addr; /* physical address of the ring */
755 unsigned short db_pidx;
756 unsigned short db_pidx_inc;
757 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
758 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
761 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
763 struct netdev_queue *txq; /* associated netdev TX queue */
764 #ifdef CONFIG_CHELSIO_T4_DCB
765 u8 dcb_prio; /* DCB Priority bound to queue */
767 u8 dbqt; /* SGE Doorbell Queue Timer in use */
768 unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */
769 unsigned long tso; /* # of TSO requests */
770 unsigned long tx_cso; /* # of Tx checksum offloads */
771 unsigned long vlan_ins; /* # of Tx VLAN insertions */
772 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
773 } ____cacheline_aligned_in_smp;
775 struct sge_uld_txq { /* state for an SGE offload Tx queue */
777 struct adapter *adap;
778 struct sk_buff_head sendq; /* list of backpressured packets */
779 struct tasklet_struct qresume_tsk; /* restarts the queue */
780 bool service_ofldq_running; /* service_ofldq() is processing sendq */
781 u8 full; /* the Tx ring is full */
782 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
783 } ____cacheline_aligned_in_smp;
785 struct sge_ctrl_txq { /* state for an SGE control Tx queue */
787 struct adapter *adap;
788 struct sk_buff_head sendq; /* list of backpressured packets */
789 struct tasklet_struct qresume_tsk; /* restarts the queue */
790 u8 full; /* the Tx ring is full */
791 } ____cacheline_aligned_in_smp;
793 struct sge_uld_rxq_info {
794 char name[IFNAMSIZ]; /* name of ULD driver */
795 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */
796 u16 *rspq_id; /* response queue id's of rxq */
797 u16 nrxq; /* # of ingress uld queues */
798 u16 nciq; /* # of completion queues */
799 u8 uld; /* uld type */
802 struct sge_uld_txq_info {
803 struct sge_uld_txq *uldtxq; /* Txq's for ULD */
804 atomic_t users; /* num users */
805 u16 ntxq; /* # of egress uld queues */
808 enum sge_eosw_state {
809 CXGB4_EO_STATE_CLOSED = 0, /* Not ready to accept traffic */
810 CXGB4_EO_STATE_FLOWC_OPEN_SEND, /* Send FLOWC open request */
811 CXGB4_EO_STATE_FLOWC_OPEN_REPLY, /* Waiting for FLOWC open reply */
812 CXGB4_EO_STATE_ACTIVE, /* Ready to accept traffic */
813 CXGB4_EO_STATE_FLOWC_CLOSE_SEND, /* Send FLOWC close request */
814 CXGB4_EO_STATE_FLOWC_CLOSE_REPLY, /* Waiting for FLOWC close reply */
817 struct sge_eosw_desc {
818 struct sk_buff *skb; /* SKB to free after getting completion */
819 dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */
822 struct sge_eosw_txq {
823 spinlock_t lock; /* Per queue lock to synchronize completions */
824 enum sge_eosw_state state; /* Current ETHOFLD State */
825 struct sge_eosw_desc *desc; /* Descriptor ring to hold packets */
826 u32 ndesc; /* Number of descriptors */
827 u32 pidx; /* Current Producer Index */
828 u32 last_pidx; /* Last successfully transmitted Producer Index */
829 u32 cidx; /* Current Consumer Index */
830 u32 last_cidx; /* Last successfully reclaimed Consumer Index */
831 u32 flowc_idx; /* Descriptor containing a FLOWC request */
832 u32 inuse; /* Number of packets held in ring */
834 u32 cred; /* Current available credits */
835 u32 ncompl; /* # of completions posted */
836 u32 last_compl; /* # of credits consumed since last completion req */
838 u32 eotid; /* Index into EOTID table in software */
839 u32 hwtid; /* Hardware EOTID index */
841 u32 hwqid; /* Underlying hardware queue index */
842 struct net_device *netdev; /* Pointer to netdevice */
843 struct tasklet_struct qresume_tsk; /* Restarts the queue */
844 struct completion completion; /* completion for FLOWC rendezvous */
847 struct sge_eohw_txq {
848 spinlock_t lock; /* Per queue lock */
849 struct sge_txq q; /* HW Txq */
850 struct adapter *adap; /* Backpointer to adapter */
851 unsigned long tso; /* # of TSO requests */
852 unsigned long tx_cso; /* # of Tx checksum offloads */
853 unsigned long vlan_ins; /* # of Tx VLAN insertions */
854 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
858 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
859 struct sge_eth_txq ptptxq;
860 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
862 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
863 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
864 struct sge_uld_rxq_info **uld_rxq_info;
865 struct sge_uld_txq_info **uld_txq_info;
867 struct sge_rspq intrq ____cacheline_aligned_in_smp;
868 spinlock_t intrq_lock;
870 struct sge_eohw_txq *eohw_txq;
871 struct sge_ofld_rxq *eohw_rxq;
873 u16 max_ethqsets; /* # of available Ethernet queue sets */
874 u16 ethqsets; /* # of active Ethernet queue sets */
875 u16 ethtxq_rover; /* Tx queue to clean up next */
876 u16 ofldqsets; /* # of active ofld queue sets */
877 u16 nqs_per_uld; /* # of Rx queues per ULD */
878 u16 eoqsets; /* # of ETHOFLD queues */
880 u16 timer_val[SGE_NTIMERS];
881 u8 counter_val[SGE_NCOUNTERS];
883 u16 dbqtimer_val[SGE_NDBQTIMERS];
884 u32 fl_pg_order; /* large page allocation size */
885 u32 stat_len; /* length of status page at ring end */
886 u32 pktshift; /* padding between CPL & packet data */
887 u32 fl_align; /* response queue message alignment */
888 u32 fl_starve_thres; /* Free List starvation threshold */
890 struct sge_idma_monitor_state idma_monitor;
891 unsigned int egr_start;
893 unsigned int ingr_start;
894 unsigned int ingr_sz;
895 void **egr_map; /* qid->queue egress queue map */
896 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
897 unsigned long *starving_fl;
898 unsigned long *txq_maperr;
899 unsigned long *blocked_fl;
900 struct timer_list rx_timer; /* refills starving FLs */
901 struct timer_list tx_timer; /* checks Tx queues */
903 int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */
904 int nd_msix_idx; /* Index to non-data interrupts MSI-X info */
907 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
908 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
912 #ifdef CONFIG_PCI_IOV
914 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
915 * Configuration initialization for T5 only has SR-IOV functionality enabled
916 * on PF0-3 in order to simplify everything.
918 #define NUM_OF_PF_WITH_SRIOV 4
922 struct doorbell_stats {
928 struct hash_mac_addr {
929 struct list_head list;
931 unsigned int iface_mac;
935 unsigned long *msix_bmap;
936 unsigned int mapsize;
937 spinlock_t lock; /* lock for acquiring bitmap */
942 char desc[IFNAMSIZ + 10];
944 cpumask_var_t aff_mask;
948 unsigned char vf_mac_addr[ETH_ALEN];
949 unsigned int tx_rate;
956 HMA_DMA_MAPPED_FLAG = 1
961 struct sg_table *sgt;
962 dma_addr_t *phy_addr; /* physical address of the page */
966 struct list_head list;
969 #if IS_ENABLED(CONFIG_THERMAL)
971 struct thermal_zone_device *tzdev;
977 struct mps_entries_ref {
978 struct list_head list;
989 struct pci_dev *pdev;
990 struct device *pdev_dev;
995 unsigned int adap_idx;
1005 struct adapter_params params;
1006 struct cxgb4_virt_res vres;
1007 unsigned int swintr;
1009 /* MSI-X Info for NIC and OFLD queues */
1010 struct msix_info *msix_info;
1011 struct msix_bmap msix_bmap;
1013 struct doorbell_stats db_stats;
1016 struct net_device *port[MAX_NPORTS];
1017 u8 chan_map[NCHAN]; /* channel -> port map */
1019 struct vf_info *vfinfo;
1023 unsigned int l2t_start;
1024 unsigned int l2t_end;
1025 struct l2t_data *l2t;
1026 unsigned int clipt_start;
1027 unsigned int clipt_end;
1028 struct clip_tbl *clipt;
1029 unsigned int rawf_start;
1030 unsigned int rawf_cnt;
1031 struct smt_data *smt;
1032 struct cxgb4_uld_info *uld;
1033 void *uld_handle[CXGB4_ULD_MAX];
1034 unsigned int num_uld;
1035 unsigned int num_ofld_uld;
1036 struct list_head list_node;
1037 struct list_head rcu_node;
1038 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */
1039 struct list_head mps_ref;
1040 spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */
1044 struct tid_info tids;
1045 void **tid_release_head;
1046 spinlock_t tid_release_lock;
1047 struct workqueue_struct *workq;
1048 struct work_struct tid_release_task;
1049 struct work_struct db_full_task;
1050 struct work_struct db_drop_task;
1051 struct work_struct fatal_err_notify_task;
1052 bool tid_release_task_busy;
1054 /* lock for mailbox cmd list */
1055 spinlock_t mbox_lock;
1056 struct mbox_list mlist;
1058 /* support for mailbox command/reply logging */
1059 #define T4_OS_LOG_MBOX_CMDS 256
1060 struct mbox_cmd_log *mbox_log;
1062 struct mutex uld_mutex;
1064 struct dentry *debugfs_root;
1065 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
1066 bool trace_rss; /* 1 implies that different RSS flit per filter is
1067 * used per filter else if 0 default RSS flit is
1068 * used for all 4 filters.
1071 struct ptp_clock *ptp_clock;
1072 struct ptp_clock_info ptp_clock_info;
1073 struct sk_buff *ptp_tx_skb;
1075 spinlock_t ptp_lock;
1076 spinlock_t stats_lock;
1077 spinlock_t win0_lock ____cacheline_aligned_in_smp;
1079 /* TC u32 offload */
1080 struct cxgb4_tc_u32_table *tc_u32;
1081 struct chcr_stats_debug chcr_stats;
1083 /* TC flower offload */
1084 bool tc_flower_initialized;
1085 struct rhashtable flower_tbl;
1086 struct rhashtable_params flower_ht_params;
1087 struct timer_list flower_stats_timer;
1088 struct work_struct flower_stats_work;
1091 struct ethtool_dump eth_dump;
1094 struct hma_data hma;
1096 struct srq_data *srq;
1098 /* Dump buffer for collecting logs in kdump kernel */
1099 struct vmcoredd_data vmcoredd;
1100 #if IS_ENABLED(CONFIG_THERMAL)
1101 struct ch_thermal ch_thermal;
1104 /* TC MQPRIO offload */
1105 struct cxgb4_tc_mqprio *tc_mqprio;
1107 /* TC MATCHALL classifier offload */
1108 struct cxgb4_tc_matchall *tc_matchall;
1111 /* Support for "sched-class" command to allow a TX Scheduling Class to be
1112 * programmed with various parameters.
1114 struct ch_sched_params {
1115 s8 type; /* packet or flow */
1118 s8 level; /* scheduler hierarchy level */
1119 s8 mode; /* per-class or per-flow */
1120 s8 rateunit; /* bit or packet rate */
1121 s8 ratemode; /* %port relative or kbps absolute */
1122 s8 channel; /* scheduler channel [0..N] */
1123 s8 class; /* scheduler class [0..N] */
1124 s32 minrate; /* minimum rate */
1125 s32 maxrate; /* maximum rate */
1126 s16 weight; /* percent weight */
1127 s16 pktsize; /* average packet size */
1133 SCHED_CLASS_TYPE_PACKET = 0, /* class type */
1137 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */
1138 SCHED_CLASS_LEVEL_CH_RL = 2, /* channel rate limiter */
1142 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */
1143 SCHED_CLASS_MODE_FLOW, /* per-flow scheduling */
1147 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */
1151 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */
1154 struct tx_sw_desc { /* SW state per Tx descriptor */
1155 struct sk_buff *skb;
1156 struct ulptx_sgl *sgl;
1159 /* Support for "sched_queue" command to allow one or more NIC TX Queues
1160 * to be bound to a TX Scheduling Class.
1162 struct ch_sched_queue {
1163 s8 queue; /* queue index */
1164 s8 class; /* class index */
1167 /* Support for "sched_flowc" command to allow one or more FLOWC
1168 * to be bound to a TX Scheduling Class.
1170 struct ch_sched_flowc {
1171 s32 tid; /* TID to bind */
1172 s8 class; /* class index */
1175 /* Defined bit width of user definable filter tuples
1177 #define ETHTYPE_BITWIDTH 16
1178 #define FRAG_BITWIDTH 1
1179 #define MACIDX_BITWIDTH 9
1180 #define FCOE_BITWIDTH 1
1181 #define IPORT_BITWIDTH 3
1182 #define MATCHTYPE_BITWIDTH 3
1183 #define PROTO_BITWIDTH 8
1184 #define TOS_BITWIDTH 8
1185 #define PF_BITWIDTH 8
1186 #define VF_BITWIDTH 8
1187 #define IVLAN_BITWIDTH 16
1188 #define OVLAN_BITWIDTH 16
1189 #define ENCAP_VNI_BITWIDTH 24
1191 /* Filter matching rules. These consist of a set of ingress packet field
1192 * (value, mask) tuples. The associated ingress packet field matches the
1193 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
1194 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
1195 * matches an ingress packet when all of the individual individual field
1196 * matching rules are true.
1198 * Partial field masks are always valid, however, while it may be easy to
1199 * understand their meanings for some fields (e.g. IP address to match a
1200 * subnet), for others making sensible partial masks is less intuitive (e.g.
1201 * MPS match type) ...
1203 * Most of the following data structures are modeled on T4 capabilities.
1204 * Drivers for earlier chips use the subsets which make sense for those chips.
1205 * We really need to come up with a hardware-independent mechanism to
1206 * represent hardware filter capabilities ...
1208 struct ch_filter_tuple {
1209 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
1210 * register selects which of these fields will participate in the
1211 * filter match rules -- up to a maximum of 36 bits. Because
1212 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
1215 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
1216 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
1217 uint32_t ivlan_vld:1; /* inner VLAN valid */
1218 uint32_t ovlan_vld:1; /* outer VLAN valid */
1219 uint32_t pfvf_vld:1; /* PF/VF valid */
1220 uint32_t encap_vld:1; /* Encapsulation valid */
1221 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
1222 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
1223 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
1224 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
1225 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
1226 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
1227 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
1228 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
1229 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
1230 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
1231 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */
1233 /* Uncompressed header matching field rules. These are always
1234 * available for field rules.
1236 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
1237 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
1238 uint16_t lport; /* local port */
1239 uint16_t fport; /* foreign port */
1242 /* A filter ioctl command.
1244 struct ch_filter_specification {
1245 /* Administrative fields for filter.
1247 uint32_t hitcnts:1; /* count filter hits in TCB */
1248 uint32_t prio:1; /* filter has priority over active/server */
1250 /* Fundamental filter typing. This is the one element of filter
1251 * matching that doesn't exist as a (value, mask) tuple.
1253 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
1254 u32 hash:1; /* 0 => wild-card, 1 => exact-match */
1256 /* Packet dispatch information. Ingress packets which match the
1257 * filter rules will be dropped, passed to the host or switched back
1258 * out as egress packets.
1260 uint32_t action:2; /* drop, pass, switch */
1262 uint32_t rpttid:1; /* report TID in RSS hash field */
1264 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
1265 uint32_t iq:10; /* ingress queue */
1267 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
1268 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
1269 /* 1 => TCB contains IQ ID */
1271 /* Switch proxy/rewrite fields. An ingress packet which matches a
1272 * filter with "switch" set will be looped back out as an egress
1273 * packet -- potentially with some Ethernet header rewriting.
1275 uint32_t eport:2; /* egress port to switch packet out */
1276 uint32_t newdmac:1; /* rewrite destination MAC address */
1277 uint32_t newsmac:1; /* rewrite source MAC address */
1278 uint32_t newvlan:2; /* rewrite VLAN Tag */
1279 uint32_t nat_mode:3; /* specify NAT operation mode */
1280 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
1281 uint8_t smac[ETH_ALEN]; /* new source MAC address */
1282 uint16_t vlan; /* VLAN Tag to insert */
1284 u8 nat_lip[16]; /* local IP to use after NAT'ing */
1285 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */
1286 u16 nat_lport; /* local port to use after NAT'ing */
1287 u16 nat_fport; /* foreign port to use after NAT'ing */
1289 /* reservation for future additions */
1292 /* Filter rule value/mask pairs.
1294 struct ch_filter_tuple val;
1295 struct ch_filter_tuple mask;
1299 FILTER_PASS = 0, /* default */
1305 VLAN_NOCHANGE = 0, /* default */
1312 NAT_MODE_NONE = 0, /* No NAT performed */
1313 NAT_MODE_DIP, /* NAT on Dst IP */
1314 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */
1315 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */
1316 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */
1317 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */
1318 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */
1319 NAT_MODE_ALL /* NAT on entire 4-tuple */
1322 /* Host shadow copy of ingress filter entry. This is in host native format
1323 * and doesn't match the ordering or bit order, etc. of the hardware of the
1324 * firmware command. The use of bit-field structure elements is purely to
1325 * remind ourselves of the field size limitations and save memory in the case
1326 * where the filter table is large.
1328 struct filter_entry {
1329 /* Administrative fields for filter. */
1330 u32 valid:1; /* filter allocated and valid */
1331 u32 locked:1; /* filter is administratively locked */
1333 u32 pending:1; /* filter action is pending firmware reply */
1334 struct filter_ctx *ctx; /* Caller's completion hook */
1335 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
1336 struct smt_entry *smt; /* Source Mac Table entry for smac */
1337 struct net_device *dev; /* Associated net device */
1338 u32 tid; /* This will store the actual tid */
1340 /* The filter itself. Most of this is a straight copy of information
1341 * provided by the extended ioctl(). Some fields are translated to
1342 * internal forms -- for instance the Ingress Queue ID passed in from
1343 * the ioctl() is translated into the Absolute Ingress Queue ID.
1345 struct ch_filter_specification fs;
1348 static inline int is_offload(const struct adapter *adap)
1350 return adap->params.offload;
1353 static inline int is_hashfilter(const struct adapter *adap)
1355 return adap->params.hash_filter;
1358 static inline int is_pci_uld(const struct adapter *adap)
1360 return adap->params.crypto;
1363 static inline int is_uld(const struct adapter *adap)
1365 return (adap->params.offload || adap->params.crypto);
1368 static inline int is_ethofld(const struct adapter *adap)
1370 return adap->params.ethofld;
1373 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1375 return readl(adap->regs + reg_addr);
1378 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1380 writel(val, adap->regs + reg_addr);
1384 static inline u64 readq(const volatile void __iomem *addr)
1386 return readl(addr) + ((u64)readl(addr + 4) << 32);
1389 static inline void writeq(u64 val, volatile void __iomem *addr)
1392 writel(val >> 32, addr + 4);
1396 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1398 return readq(adap->regs + reg_addr);
1401 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1403 writeq(val, adap->regs + reg_addr);
1407 * t4_set_hw_addr - store a port's MAC address in SW
1408 * @adapter: the adapter
1409 * @port_idx: the port index
1410 * @hw_addr: the Ethernet address
1412 * Store the Ethernet address of the given port in SW. Called by the common
1413 * code when it retrieves a port's Ethernet address from EEPROM.
1415 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1418 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1419 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1423 * netdev2pinfo - return the port_info structure associated with a net_device
1426 * Return the struct port_info associated with a net_device
1428 static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1430 return netdev_priv(dev);
1434 * adap2pinfo - return the port_info of a port
1435 * @adap: the adapter
1436 * @idx: the port index
1438 * Return the port_info structure for the port of the given index.
1440 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1442 return netdev_priv(adap->port[idx]);
1446 * netdev2adap - return the adapter structure associated with a net_device
1449 * Return the struct adapter associated with a net_device
1451 static inline struct adapter *netdev2adap(const struct net_device *dev)
1453 return netdev2pinfo(dev)->adapter;
1456 /* Return a version number to identify the type of adapter. The scheme is:
1457 * - bits 0..9: chip version
1458 * - bits 10..15: chip revision
1459 * - bits 16..23: register dump version
1461 static inline unsigned int mk_adap_vers(struct adapter *ap)
1463 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1464 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1467 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1468 static inline unsigned int qtimer_val(const struct adapter *adap,
1469 const struct sge_rspq *q)
1471 unsigned int idx = q->intr_params >> 1;
1473 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1476 /* driver version & name used for ethtool_drvinfo */
1477 extern char cxgb4_driver_name[];
1478 extern const char cxgb4_driver_version[];
1480 void t4_os_portmod_changed(struct adapter *adap, int port_id);
1481 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1483 void t4_free_sge_resources(struct adapter *adap);
1484 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1485 irq_handler_t t4_intr_handler(struct adapter *adap);
1486 netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev);
1487 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1488 const struct pkt_gl *gl);
1489 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1490 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1491 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1492 struct net_device *dev, int intr_idx,
1493 struct sge_fl *fl, rspq_handler_t hnd,
1494 rspq_flush_handler_t flush_handler, int cong);
1495 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1496 struct net_device *dev, struct netdev_queue *netdevq,
1497 unsigned int iqid, u8 dbqt);
1498 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1499 struct net_device *dev, unsigned int iqid,
1500 unsigned int cmplqid);
1501 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
1502 unsigned int cmplqid);
1503 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
1504 struct net_device *dev, unsigned int iqid,
1505 unsigned int uld_type);
1506 int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq,
1507 struct net_device *dev, u32 iqid);
1508 void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq);
1509 irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1510 int t4_sge_init(struct adapter *adap);
1511 void t4_sge_start(struct adapter *adap);
1512 void t4_sge_stop(struct adapter *adap);
1513 int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q,
1515 void cxgb4_set_ethtool_ops(struct net_device *netdev);
1516 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1517 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb);
1518 extern int dbfifo_int_thresh;
1520 #define for_each_port(adapter, iter) \
1521 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1523 static inline int is_bypass(struct adapter *adap)
1525 return adap->params.bypass;
1528 static inline int is_bypass_device(int device)
1530 /* this should be set based upon device capabilities */
1540 static inline int is_10gbt_device(int device)
1542 /* this should be set based upon device capabilities */
1553 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1555 return adap->params.vpd.cclk / 1000;
1558 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1561 return (us * adap->params.vpd.cclk) / 1000;
1564 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1567 /* add Core Clock / 2 to round ticks to nearest uS */
1568 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1569 adapter->params.vpd.cclk);
1572 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
1575 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
1578 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1581 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1582 int size, void *rpl, bool sleep_ok, int timeout);
1583 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1584 void *rpl, bool sleep_ok);
1586 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1587 const void *cmd, int size, void *rpl,
1590 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1594 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1595 int size, void *rpl)
1597 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1600 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1601 int size, void *rpl)
1603 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1607 * hash_mac_addr - return the hash value of a MAC address
1608 * @addr: the 48-bit Ethernet MAC address
1610 * Hashes a MAC address according to the hash function used by HW inexact
1611 * (hash) address matching.
1613 static inline int hash_mac_addr(const u8 *addr)
1615 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1616 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1624 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1626 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1627 unsigned int us, unsigned int cnt,
1628 unsigned int size, unsigned int iqe_size)
1631 cxgb4_set_rspq_intr_params(q, us, cnt);
1632 q->iqe_len = iqe_size;
1637 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type
1638 * @fw_mod_type: the Firmware Mofule Type
1640 * Return whether the Firmware Module Type represents a real Transceiver
1641 * Module/Cable Module Type which has been inserted.
1643 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type)
1645 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE &&
1646 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED &&
1647 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN &&
1648 fw_mod_type != FW_PORT_MOD_TYPE_ERROR);
1651 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1652 unsigned int data_reg, const u32 *vals,
1653 unsigned int nregs, unsigned int start_idx);
1654 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1655 unsigned int data_reg, u32 *vals, unsigned int nregs,
1656 unsigned int start_idx);
1657 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1659 struct fw_filter_wr;
1661 void t4_intr_enable(struct adapter *adapter);
1662 void t4_intr_disable(struct adapter *adapter);
1663 int t4_slow_intr_handler(struct adapter *adapter);
1665 int t4_wait_dev_ready(void __iomem *regs);
1667 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
1668 struct link_config *lc);
1669 int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox,
1670 unsigned int port, struct link_config *lc,
1671 u8 sleep_ok, int timeout);
1673 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
1674 unsigned int port, struct link_config *lc)
1676 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1677 true, FW_CMD_MAX_TIMEOUT);
1680 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox,
1681 unsigned int port, struct link_config *lc)
1683 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1684 false, FW_CMD_MAX_TIMEOUT);
1687 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1689 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1690 u32 t4_get_util_window(struct adapter *adap);
1691 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1693 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
1694 u32 *mem_base, u32 *mem_aperture);
1695 void t4_memory_update_win(struct adapter *adap, int win, u32 addr);
1696 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
1698 #define T4_MEMORY_WRITE 0
1699 #define T4_MEMORY_READ 1
1700 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1701 void *buf, int dir);
1702 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1703 u32 len, __be32 *buf)
1705 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1708 unsigned int t4_get_regs_len(struct adapter *adapter);
1709 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1711 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
1712 int t4_seeprom_wp(struct adapter *adapter, bool enable);
1713 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1714 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1715 int t4_get_pfres(struct adapter *adapter);
1716 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1717 unsigned int nwords, u32 *data, int byte_oriented);
1718 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1719 int t4_load_phy_fw(struct adapter *adap,
1720 int win, spinlock_t *lock,
1721 int (*phy_fw_version)(const u8 *, size_t),
1722 const u8 *phy_fw_data, size_t phy_fw_size);
1723 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1724 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1725 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1726 const u8 *fw_data, unsigned int size, int force);
1727 int t4_fl_pkt_align(struct adapter *adap);
1728 unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1729 int t4_check_fw_version(struct adapter *adap);
1730 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
1731 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1732 int t4_get_bs_version(struct adapter *adapter, u32 *vers);
1733 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1734 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1735 int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
1736 int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
1737 int t4_get_version_info(struct adapter *adapter);
1738 void t4_dump_version_info(struct adapter *adapter);
1739 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1740 const u8 *fw_data, unsigned int fw_size,
1741 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1742 int t4_prep_adapter(struct adapter *adapter);
1743 int t4_shutdown_adapter(struct adapter *adapter);
1745 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1746 int t4_bar2_sge_qregs(struct adapter *adapter,
1748 enum t4_bar2_qtype qtype,
1751 unsigned int *pbar2_qid);
1753 unsigned int qtimer_val(const struct adapter *adap,
1754 const struct sge_rspq *q);
1756 int t4_init_devlog_params(struct adapter *adapter);
1757 int t4_init_sge_params(struct adapter *adapter);
1758 int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
1759 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1760 int t4_init_rss_mode(struct adapter *adap, int mbox);
1761 int t4_init_portinfo(struct port_info *pi, int mbox,
1762 int port, int pf, int vf, u8 mac[]);
1763 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1764 void t4_fatal_err(struct adapter *adapter);
1765 unsigned int t4_chip_rss_size(struct adapter *adapter);
1766 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1767 int start, int n, const u16 *rspq, unsigned int nrspq);
1768 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1769 unsigned int flags);
1770 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1771 unsigned int flags, unsigned int defq);
1772 int t4_read_rss(struct adapter *adapter, u16 *entries);
1773 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
1774 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
1776 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1777 u32 *valp, bool sleep_ok);
1778 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1779 u32 *vfl, u32 *vfh, bool sleep_ok);
1780 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
1781 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
1783 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
1784 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
1785 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1786 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1787 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1789 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1791 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1792 unsigned int *valp);
1793 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1794 const unsigned int *valp);
1795 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1796 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1797 unsigned int *pif_req_wrptr,
1798 unsigned int *pif_rsp_wrptr);
1799 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1800 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1801 const char *t4_get_port_type_description(enum fw_port_type port_type);
1802 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1803 void t4_get_port_stats_offset(struct adapter *adap, int idx,
1804 struct port_stats *stats,
1805 struct port_stats *offset);
1806 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1807 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1808 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1809 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1810 unsigned int mask, unsigned int val);
1811 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1812 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
1814 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
1816 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
1818 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
1820 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1821 struct tp_tcp_stats *v6, bool sleep_ok);
1822 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1823 struct tp_fcoe_stats *st, bool sleep_ok);
1824 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1825 const unsigned short *alpha, const unsigned short *beta);
1827 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1829 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1830 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1832 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1834 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1835 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1837 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1838 enum dev_master master, enum dev_state *state);
1839 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1840 int t4_early_init(struct adapter *adap, unsigned int mbox);
1841 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1842 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1843 unsigned int cache_line_size);
1844 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1845 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1846 unsigned int vf, unsigned int nparams, const u32 *params,
1848 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
1849 unsigned int vf, unsigned int nparams, const u32 *params,
1851 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1852 unsigned int vf, unsigned int nparams, const u32 *params,
1853 u32 *val, int rw, bool sleep_ok);
1854 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1855 unsigned int pf, unsigned int vf,
1856 unsigned int nparams, const u32 *params,
1857 const u32 *val, int timeout);
1858 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1859 unsigned int vf, unsigned int nparams, const u32 *params,
1861 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1862 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1863 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1864 unsigned int vi, unsigned int cmask, unsigned int pmask,
1865 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1866 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1867 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1868 unsigned int *rss_size, u8 *vivld, u8 *vin);
1869 int t4_free_vi(struct adapter *adap, unsigned int mbox,
1870 unsigned int pf, unsigned int vf,
1872 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1873 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1875 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
1876 const u8 *addr, const u8 *mask, unsigned int idx,
1877 u8 lookup_type, u8 port_id, bool sleep_ok);
1878 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx,
1880 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
1881 const u8 *addr, const u8 *mask, unsigned int vni,
1882 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
1884 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
1885 const u8 *addr, const u8 *mask, unsigned int idx,
1886 u8 lookup_type, u8 port_id, bool sleep_ok);
1887 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1888 unsigned int viid, bool free, unsigned int naddr,
1889 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1890 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
1891 unsigned int viid, unsigned int naddr,
1892 const u8 **addr, bool sleep_ok);
1893 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1894 int idx, const u8 *addr, bool persist, u8 *smt_idx);
1895 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1896 bool ucast, u64 vec, bool sleep_ok);
1897 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1898 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1899 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
1900 struct port_info *pi,
1901 bool rx_en, bool tx_en, bool dcb_en);
1902 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1903 bool rx_en, bool tx_en);
1904 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1905 unsigned int nblinks);
1906 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1907 unsigned int mmd, unsigned int reg, u16 *valp);
1908 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1909 unsigned int mmd, unsigned int reg, u16 val);
1910 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
1911 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1912 unsigned int fl0id, unsigned int fl1id);
1913 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1914 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1915 unsigned int fl0id, unsigned int fl1id);
1916 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1917 unsigned int vf, unsigned int eqid);
1918 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1919 unsigned int vf, unsigned int eqid);
1920 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1921 unsigned int vf, unsigned int eqid);
1922 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type);
1923 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
1925 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
1926 int t4_update_port_info(struct port_info *pi);
1927 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
1928 unsigned int *speedp, unsigned int *mtup);
1929 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1930 void t4_db_full(struct adapter *adapter);
1931 void t4_db_dropped(struct adapter *adapter);
1932 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1933 int filter_index, int enable);
1934 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1935 int filter_index, int *enabled);
1936 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1938 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
1939 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
1940 unsigned int *kbps, unsigned int *ipg, bool sleep_ok);
1941 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
1942 enum ctxt_type ctype, u32 *data);
1943 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
1944 enum ctxt_type ctype, u32 *data);
1945 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
1946 int rateunit, int ratemode, int channel, int class,
1947 int minrate, int maxrate, int weight, int pktsize);
1948 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
1949 void t4_idma_monitor_init(struct adapter *adapter,
1950 struct sge_idma_monitor_state *idma);
1951 void t4_idma_monitor(struct adapter *adapter,
1952 struct sge_idma_monitor_state *idma,
1954 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
1955 unsigned int naddr, u8 *addr);
1956 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1957 u32 start_index, bool sleep_ok);
1958 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1959 u32 start_index, bool sleep_ok);
1960 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
1961 u32 start_index, bool sleep_ok);
1963 void t4_uld_mem_free(struct adapter *adap);
1964 int t4_uld_mem_alloc(struct adapter *adap);
1965 void t4_uld_clean_up(struct adapter *adap);
1966 void t4_register_netevent_notifier(void);
1967 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
1968 unsigned int devid, unsigned int offset,
1969 unsigned int len, u8 *buf);
1970 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
1971 void free_tx_desc(struct adapter *adap, struct sge_txq *q,
1972 unsigned int n, bool unmap);
1973 void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq,
1975 int cxgb4_ethofld_send_flowc(struct net_device *dev, u32 eotid, u32 tc);
1976 void cxgb4_ethofld_restart(unsigned long data);
1977 int cxgb4_ethofld_rx_handler(struct sge_rspq *q, const __be64 *rsp,
1978 const struct pkt_gl *si);
1979 void free_txq(struct adapter *adap, struct sge_txq *q);
1980 void cxgb4_reclaim_completed_tx(struct adapter *adap,
1981 struct sge_txq *q, bool unmap);
1982 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb,
1984 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
1986 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q,
1987 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
1988 const dma_addr_t *addr);
1989 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n);
1990 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
1992 int cxgb4_dcb_enabled(const struct net_device *dev);
1994 int cxgb4_thermal_init(struct adapter *adap);
1995 int cxgb4_thermal_remove(struct adapter *adap);
1996 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec,
1997 cpumask_var_t *aff_mask, int idx);
1998 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask);
2000 int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
2001 int *tcam_idx, const u8 *addr,
2002 bool persistent, u8 *smt_idx);
2004 int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid,
2005 bool free, unsigned int naddr,
2006 const u8 **addr, u16 *idx,
2007 u64 *hash, bool sleep_ok);
2008 int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid,
2009 unsigned int naddr, const u8 **addr, bool sleep_ok);
2010 int cxgb4_init_mps_ref_entries(struct adapter *adap);
2011 void cxgb4_free_mps_ref_entries(struct adapter *adap);
2012 int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
2013 const u8 *addr, const u8 *mask,
2014 unsigned int vni, unsigned int vni_mask,
2015 u8 dip_hit, u8 lookup_type, bool sleep_ok);
2016 int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
2017 int idx, bool sleep_ok);
2018 int cxgb4_free_raw_mac_filt(struct adapter *adap,
2026 int cxgb4_alloc_raw_mac_filt(struct adapter *adap,
2034 int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid,
2035 int *tcam_idx, const u8 *addr,
2036 bool persistent, u8 *smt_idx);
2037 int cxgb4_get_msix_idx_from_bmap(struct adapter *adap);
2038 void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx);
2039 int cxgb_open(struct net_device *dev);
2040 int cxgb_close(struct net_device *dev);
2041 void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q);
2042 void cxgb4_quiesce_rx(struct sge_rspq *q);
2043 #endif /* __CXGB4_H__ */