2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/bitops.h>
41 #include <linux/cache.h>
42 #include <linux/interrupt.h>
43 #include <linux/list.h>
44 #include <linux/netdevice.h>
45 #include <linux/pci.h>
46 #include <linux/spinlock.h>
47 #include <linux/timer.h>
48 #include <linux/vmalloc.h>
49 #include <linux/rhashtable.h>
50 #include <linux/etherdevice.h>
51 #include <linux/net_tstamp.h>
52 #include <linux/ptp_clock_kernel.h>
53 #include <linux/ptp_classify.h>
54 #include <linux/crash_dump.h>
55 #include <linux/thermal.h>
57 #include "t4_chip_type.h"
58 #include "cxgb4_uld.h"
60 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
61 extern struct list_head adapter_list;
62 extern struct mutex uld_mutex;
64 /* Suspend an Ethernet Tx queue with fewer available descriptors than this.
65 * This is the same as calc_tx_descs() for a TSO packet with
66 * nr_frags == MAX_SKB_FRAGS.
68 #define ETHTXQ_STOP_THRES \
69 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8))
72 MAX_NPORTS = 4, /* max # of ports */
73 SERNUM_LEN = 24, /* Serial # length */
74 EC_LEN = 16, /* E/C length */
75 ID_LEN = 16, /* ID length */
76 PN_LEN = 16, /* Part Number length */
77 MACADDR_LEN = 12, /* MAC Address length */
81 T4_REGMAP_SIZE = (160 * 1024),
82 T5_REGMAP_SIZE = (332 * 1024),
95 MEMWIN0_APERTURE = 2048,
96 MEMWIN0_BASE = 0x1b800,
97 MEMWIN1_APERTURE = 32768,
98 MEMWIN1_BASE = 0x28000,
99 MEMWIN1_BASE_T5 = 0x52000,
100 MEMWIN2_APERTURE = 65536,
101 MEMWIN2_BASE = 0x30000,
102 MEMWIN2_APERTURE_T5 = 131072,
103 MEMWIN2_BASE_T5 = 0x60000,
121 PAUSE_AUTONEG = 1 << 2
125 FEC_AUTO = 1 << 0, /* IEEE 802.3 "automatic" */
126 FEC_RS = 1 << 1, /* Reed-Solomon */
127 FEC_BASER_RS = 1 << 2 /* BaseR/Reed-Solomon */
131 u64 tx_octets; /* total # of octets in good frames */
132 u64 tx_frames; /* all good frames */
133 u64 tx_bcast_frames; /* all broadcast frames */
134 u64 tx_mcast_frames; /* all multicast frames */
135 u64 tx_ucast_frames; /* all unicast frames */
136 u64 tx_error_frames; /* all error frames */
138 u64 tx_frames_64; /* # of Tx frames in a particular range */
139 u64 tx_frames_65_127;
140 u64 tx_frames_128_255;
141 u64 tx_frames_256_511;
142 u64 tx_frames_512_1023;
143 u64 tx_frames_1024_1518;
144 u64 tx_frames_1519_max;
146 u64 tx_drop; /* # of dropped Tx frames */
147 u64 tx_pause; /* # of transmitted pause frames */
148 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
149 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
150 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
151 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
152 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
153 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
154 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
155 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
157 u64 rx_octets; /* total # of octets in good frames */
158 u64 rx_frames; /* all good frames */
159 u64 rx_bcast_frames; /* all broadcast frames */
160 u64 rx_mcast_frames; /* all multicast frames */
161 u64 rx_ucast_frames; /* all unicast frames */
162 u64 rx_too_long; /* # of frames exceeding MTU */
163 u64 rx_jabber; /* # of jabber frames */
164 u64 rx_fcs_err; /* # of received frames with bad FCS */
165 u64 rx_len_err; /* # of received frames with length error */
166 u64 rx_symbol_err; /* symbol errors */
167 u64 rx_runt; /* # of short frames */
169 u64 rx_frames_64; /* # of Rx frames in a particular range */
170 u64 rx_frames_65_127;
171 u64 rx_frames_128_255;
172 u64 rx_frames_256_511;
173 u64 rx_frames_512_1023;
174 u64 rx_frames_1024_1518;
175 u64 rx_frames_1519_max;
177 u64 rx_pause; /* # of received pause frames */
178 u64 rx_ppp0; /* # of received PPP prio 0 frames */
179 u64 rx_ppp1; /* # of received PPP prio 1 frames */
180 u64 rx_ppp2; /* # of received PPP prio 2 frames */
181 u64 rx_ppp3; /* # of received PPP prio 3 frames */
182 u64 rx_ppp4; /* # of received PPP prio 4 frames */
183 u64 rx_ppp5; /* # of received PPP prio 5 frames */
184 u64 rx_ppp6; /* # of received PPP prio 6 frames */
185 u64 rx_ppp7; /* # of received PPP prio 7 frames */
187 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
188 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
189 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
190 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
191 u64 rx_trunc0; /* buffer-group 0 truncated packets */
192 u64 rx_trunc1; /* buffer-group 1 truncated packets */
193 u64 rx_trunc2; /* buffer-group 2 truncated packets */
194 u64 rx_trunc3; /* buffer-group 3 truncated packets */
197 struct lb_port_stats {
210 u64 frames_1024_1518;
225 struct tp_tcp_stats {
229 u64 tcp_retrans_segs;
232 struct tp_usm_stats {
238 struct tp_fcoe_stats {
244 struct tp_err_stats {
248 u32 tnl_cong_drops[4];
249 u32 ofld_chan_drops[4];
251 u32 ofld_vlan_drops[4];
257 struct tp_cpl_stats {
262 struct tp_rdma_stats {
268 u32 hps; /* host page size for our PF/VF */
269 u32 eq_qpp; /* egress queues/page for our PF/VF */
270 u32 iq_qpp; /* egress queues/page for our PF/VF */
274 unsigned int tre; /* log2 of core clocks per TP tick */
275 unsigned int la_mask; /* what events are recorded by TP LA */
276 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
279 uint32_t dack_re; /* DACK timer resolution */
280 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
282 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
284 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
286 /* cached TP_OUT_CONFIG compressed error vector
287 * and passing outer header info for encapsulated packets.
291 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
292 * subset of the set of fields which may be present in the Compressed
293 * Filter Tuple portion of filters and TCP TCB connections. The
294 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
295 * Since a variable number of fields may or may not be present, their
296 * shifted field positions within the Compressed Filter Tuple may
297 * vary, or not even be present if the field isn't selected in
298 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
299 * places we store their offsets here, or a -1 if the field isn't
313 u64 hash_filter_mask;
319 u8 sn[SERNUM_LEN + 1];
322 u8 na[MACADDR_LEN + 1];
325 /* Maximum resources provisioned for a PCI PF.
327 struct pf_resources {
328 unsigned int nvi; /* N virtual interfaces */
329 unsigned int neq; /* N egress Qs */
330 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
331 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
332 unsigned int niq; /* N ingress Qs */
333 unsigned int tc; /* PCI-E traffic class */
334 unsigned int pmask; /* port access rights mask */
335 unsigned int nexactf; /* N exact MPS filters */
336 unsigned int r_caps; /* read capabilities */
337 unsigned int wx_caps; /* write/execute capabilities */
341 unsigned int vpd_cap_addr;
346 struct devlog_params {
347 u32 memtype; /* which memory (EDC0, EDC1, MC) */
348 u32 start; /* start of log in firmware memory */
349 u32 size; /* size of log */
352 /* Stores chip specific parameters */
353 struct arch_specific_params {
356 u8 cng_ch_bits_log; /* congestion channel map bits width */
363 struct adapter_params {
364 struct sge_params sge;
366 struct vpd_params vpd;
367 struct pf_resources pfres;
368 struct pci_params pci;
369 struct devlog_params devlog;
370 enum pcie_memwin drv_memwin;
372 unsigned int cim_la_size;
374 unsigned int sf_size; /* serial flash size in bytes */
375 unsigned int sf_nsec; /* # of flash sectors */
377 unsigned int fw_vers; /* firmware version */
378 unsigned int bs_vers; /* bootstrap version */
379 unsigned int tp_vers; /* TP microcode version */
380 unsigned int er_vers; /* expansion ROM version */
381 unsigned int scfg_vers; /* Serial Configuration version */
382 unsigned int vpd_vers; /* VPD Version */
385 unsigned short mtus[NMTUS];
386 unsigned short a_wnd[NCCTRL_WIN];
387 unsigned short b_wnd[NCCTRL_WIN];
389 unsigned char nports; /* # of ethernet ports */
390 unsigned char portvec;
391 enum chip_type chip; /* chip code */
392 struct arch_specific_params arch; /* chip specific params */
393 unsigned char offload;
394 unsigned char crypto; /* HW capability for crypto */
395 unsigned char ethofld; /* QoS support */
397 unsigned char bypass;
398 unsigned char hash_filter;
400 unsigned int ofldq_wr_cred;
401 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
403 unsigned int nsched_cls; /* number of traffic classes */
404 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
405 unsigned int max_ird_adapter; /* Max read depth per adapter */
406 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
407 u8 fw_caps_support; /* 32-bit Port Capabilities */
408 bool filter2_wr_support; /* FW support for FILTER2_WR */
409 unsigned int viid_smt_extn_support:1; /* FW returns vin and smt index */
411 /* MPS Buffer Group Map[per Port]. Bit i is set if buffer group i is
414 u8 mps_bg_map[MAX_NPORTS]; /* MPS Buffer Group Map */
415 bool write_w_imm_support; /* FW supports WRITE_WITH_IMMEDIATE */
416 bool write_cmpl_support; /* FW supports WRITE_CMPL */
419 /* State needed to monitor the forward progress of SGE Ingress DMA activities
420 * and possible hangs.
422 struct sge_idma_monitor_state {
423 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
424 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
425 unsigned int idma_state[2]; /* IDMA Hang detect state */
426 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
427 unsigned int idma_warn[2]; /* time to warning in HZ */
430 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
431 * The access and execute times are signed in order to accommodate negative
435 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */
436 u64 timestamp; /* OS-dependent timestamp */
437 u32 seqno; /* sequence number */
438 s16 access; /* time (ms) to access mailbox */
439 s16 execute; /* time (ms) to execute */
442 struct mbox_cmd_log {
443 unsigned int size; /* number of entries in the log */
444 unsigned int cursor; /* next position in the log to write */
445 u32 seqno; /* next sequence number */
446 /* variable length mailbox command log starts here */
449 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
450 * return a pointer to the specified entry.
452 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
453 unsigned int entry_idx)
455 return &((struct mbox_cmd *)&(log)[1])[entry_idx];
458 #include "t4fw_api.h"
460 #define FW_VERSION(chip) ( \
461 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
462 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
463 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
464 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
465 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
471 struct fw_hdr fw_hdr;
474 struct trace_params {
475 u32 data[TRACE_LEN / 4];
476 u32 mask[TRACE_LEN / 4];
477 unsigned short snap_len;
478 unsigned short min_len;
479 unsigned char skip_ofst;
480 unsigned char skip_len;
481 unsigned char invert;
485 /* Firmware Port Capabilities types. */
487 typedef u16 fw_port_cap16_t; /* 16-bit Port Capabilities integral value */
488 typedef u32 fw_port_cap32_t; /* 32-bit Port Capabilities integral value */
491 FW_CAPS_UNKNOWN = 0, /* 0'ed out initial state */
492 FW_CAPS16 = 1, /* old Firmware: 16-bit Port Capabilities */
493 FW_CAPS32 = 2, /* new Firmware: 32-bit Port Capabilities */
497 fw_port_cap32_t pcaps; /* link capabilities */
498 fw_port_cap32_t def_acaps; /* default advertised capabilities */
499 fw_port_cap32_t acaps; /* advertised capabilities */
500 fw_port_cap32_t lpacaps; /* peer advertised capabilities */
502 fw_port_cap32_t speed_caps; /* speed(s) user has requested */
503 unsigned int speed; /* actual link speed (Mb/s) */
505 enum cc_pause requested_fc; /* flow control user has requested */
506 enum cc_pause fc; /* actual link flow control */
508 enum cc_fec requested_fec; /* Forward Error Correction: */
509 enum cc_fec fec; /* requested and actual in use */
511 unsigned char autoneg; /* autonegotiating? */
513 unsigned char link_ok; /* link up? */
514 unsigned char link_down_rc; /* link down reason */
516 bool new_module; /* ->OS Transceiver Module inserted */
517 bool redo_l1cfg; /* ->CC redo current "sticky" L1 CFG */
520 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
523 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
524 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */
525 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
529 MAX_TXQ_ENTRIES = 16384,
530 MAX_CTRL_TXQ_ENTRIES = 1024,
531 MAX_RSPQ_ENTRIES = 16384,
532 MAX_RX_BUFFERS = 16384,
533 MIN_TXQ_ENTRIES = 32,
534 MIN_CTRL_TXQ_ENTRIES = 32,
535 MIN_RSPQ_ENTRIES = 128,
540 MAX_TXQ_DESC_SIZE = 64,
541 MAX_RXQ_DESC_SIZE = 128,
542 MAX_FL_DESC_SIZE = 8,
543 MAX_CTRL_TXQ_DESC_SIZE = 64,
547 INGQ_EXTRAS = 2, /* firmware event queue and */
548 /* forwarded interrupts */
549 MAX_INGQ = MAX_ETH_QSETS + INGQ_EXTRAS,
553 PRIV_FLAG_PORT_TX_VM_BIT,
556 #define PRIV_FLAG_PORT_TX_VM BIT(PRIV_FLAG_PORT_TX_VM_BIT)
558 #define PRIV_FLAGS_ADAP 0
559 #define PRIV_FLAGS_PORT PRIV_FLAG_PORT_TX_VM
564 #include "cxgb4_dcb.h"
566 #ifdef CONFIG_CHELSIO_T4_FCOE
567 #include "cxgb4_fcoe.h"
568 #endif /* CONFIG_CHELSIO_T4_FCOE */
571 struct adapter *adapter;
573 int xact_addr_filt; /* index of exact MAC address filter */
574 u16 rss_size; /* size of VI's RSS table slice */
576 enum fw_port_type port_type;
580 u8 lport; /* associated offload logical port */
581 u8 nqsets; /* # of qsets */
582 u8 first_qset; /* index of first qset */
584 struct link_config link_cfg;
586 struct port_stats stats_base;
587 #ifdef CONFIG_CHELSIO_T4_DCB
588 struct port_dcb_info dcb; /* Data Center Bridging support */
590 #ifdef CONFIG_CHELSIO_T4_FCOE
591 struct cxgb_fcoe fcoe;
592 #endif /* CONFIG_CHELSIO_T4_FCOE */
593 bool rxtstamp; /* Enable TS */
594 struct hwtstamp_config tstamp_config;
596 struct sched_table *sched_tbl;
599 /* viid and smt fields either returned by fw
600 * or decoded by parsing viid by driver.
611 enum { /* adapter flags */
612 CXGB4_FULL_INIT_DONE = (1 << 0),
613 CXGB4_DEV_ENABLED = (1 << 1),
614 CXGB4_USING_MSI = (1 << 2),
615 CXGB4_USING_MSIX = (1 << 3),
616 CXGB4_FW_OK = (1 << 4),
617 CXGB4_RSS_TNLALLLOOKUP = (1 << 5),
618 CXGB4_USING_SOFT_PARAMS = (1 << 6),
619 CXGB4_MASTER_PF = (1 << 7),
620 CXGB4_FW_OFLD_CONN = (1 << 9),
621 CXGB4_ROOT_NO_RELAXED_ORDERING = (1 << 10),
622 CXGB4_SHUTTING_DOWN = (1 << 11),
623 CXGB4_SGE_DBQ_TIMER = (1 << 12),
627 ULP_CRYPTO_LOOKASIDE = 1 << 0,
628 ULP_CRYPTO_IPSEC_INLINE = 1 << 1,
633 struct sge_fl { /* SGE free-buffer queue state */
634 unsigned int avail; /* # of available Rx buffers */
635 unsigned int pend_cred; /* new buffers since last FL DB ring */
636 unsigned int cidx; /* consumer index */
637 unsigned int pidx; /* producer index */
638 unsigned long alloc_failed; /* # of times buffer allocation failed */
639 unsigned long large_alloc_failed;
640 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */
641 unsigned long low; /* # of times momentarily starving */
642 unsigned long starving;
644 unsigned int cntxt_id; /* SGE context id for the free list */
645 unsigned int size; /* capacity of free list */
646 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
647 __be64 *desc; /* address of HW Rx descriptor ring */
648 dma_addr_t addr; /* bus address of HW ring start */
649 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
650 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
653 /* A packet gather list */
655 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */
656 struct page_frag frags[MAX_SKB_FRAGS];
657 void *va; /* virtual address of first byte */
658 unsigned int nfrags; /* # of fragments */
659 unsigned int tot_len; /* total length of fragments */
662 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
663 const struct pkt_gl *gl);
664 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
665 /* LRO related declarations for ULD */
667 #define MAX_LRO_SESSIONS 64
668 u8 lro_session_cnt; /* # of sessions to aggregate */
669 unsigned long lro_pkts; /* # of LRO super packets */
670 unsigned long lro_merged; /* # of wire packets merged by LRO */
671 struct sk_buff_head lroq; /* list of aggregated sessions */
674 struct sge_rspq { /* state for an SGE response queue */
675 struct napi_struct napi;
676 const __be64 *cur_desc; /* current descriptor in queue */
677 unsigned int cidx; /* consumer index */
678 u8 gen; /* current generation bit */
679 u8 intr_params; /* interrupt holdoff parameters */
680 u8 next_intr_params; /* holdoff params for next interrupt */
682 u8 pktcnt_idx; /* interrupt packet threshold */
683 u8 uld; /* ULD handling this queue */
684 u8 idx; /* queue index within its group */
685 int offset; /* offset into current Rx buffer */
686 u16 cntxt_id; /* SGE context id for the response q */
687 u16 abs_id; /* absolute SGE id for the response q */
688 __be64 *desc; /* address of HW response ring */
689 dma_addr_t phys_addr; /* physical address of the ring */
690 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
691 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
692 unsigned int iqe_len; /* entry size */
693 unsigned int size; /* capacity of response queue */
694 struct adapter *adap;
695 struct net_device *netdev; /* associated net device */
696 rspq_handler_t handler;
697 rspq_flush_handler_t flush_handler;
698 struct t4_lro_mgr lro_mgr;
701 struct sge_eth_stats { /* Ethernet queue statistics */
702 unsigned long pkts; /* # of ethernet packets */
703 unsigned long lro_pkts; /* # of LRO super packets */
704 unsigned long lro_merged; /* # of wire packets merged by LRO */
705 unsigned long rx_cso; /* # of Rx checksum offloads */
706 unsigned long vlan_ex; /* # of Rx VLAN extractions */
707 unsigned long rx_drops; /* # of packets dropped due to no mem */
708 unsigned long bad_rx_pkts; /* # of packets with err_vec!=0 */
711 struct sge_eth_rxq { /* SW Ethernet Rx queue */
712 struct sge_rspq rspq;
714 struct sge_eth_stats stats;
715 struct msix_info *msix;
716 } ____cacheline_aligned_in_smp;
718 struct sge_ofld_stats { /* offload queue statistics */
719 unsigned long pkts; /* # of packets */
720 unsigned long imm; /* # of immediate-data packets */
721 unsigned long an; /* # of asynchronous notifications */
722 unsigned long nomem; /* # of responses deferred due to no mem */
725 struct sge_ofld_rxq { /* SW offload Rx queue */
726 struct sge_rspq rspq;
728 struct sge_ofld_stats stats;
729 struct msix_info *msix;
730 } ____cacheline_aligned_in_smp;
739 unsigned int in_use; /* # of in-use Tx descriptors */
740 unsigned int q_type; /* Q type Eth/Ctrl/Ofld */
741 unsigned int size; /* # of descriptors */
742 unsigned int cidx; /* SW consumer index */
743 unsigned int pidx; /* producer index */
744 unsigned long stops; /* # of times q has been stopped */
745 unsigned long restarts; /* # of queue restarts */
746 unsigned int cntxt_id; /* SGE context id for the Tx q */
747 struct tx_desc *desc; /* address of HW Tx descriptor ring */
748 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
749 struct sge_qstat *stat; /* queue status entry */
750 dma_addr_t phys_addr; /* physical address of the ring */
753 unsigned short db_pidx;
754 unsigned short db_pidx_inc;
755 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
756 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
759 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
761 struct netdev_queue *txq; /* associated netdev TX queue */
762 #ifdef CONFIG_CHELSIO_T4_DCB
763 u8 dcb_prio; /* DCB Priority bound to queue */
765 u8 dbqt; /* SGE Doorbell Queue Timer in use */
766 unsigned int dbqtimerix; /* SGE Doorbell Queue Timer Index */
767 unsigned long tso; /* # of TSO requests */
768 unsigned long tx_cso; /* # of Tx checksum offloads */
769 unsigned long vlan_ins; /* # of Tx VLAN insertions */
770 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
771 } ____cacheline_aligned_in_smp;
773 struct sge_uld_txq { /* state for an SGE offload Tx queue */
775 struct adapter *adap;
776 struct sk_buff_head sendq; /* list of backpressured packets */
777 struct tasklet_struct qresume_tsk; /* restarts the queue */
778 bool service_ofldq_running; /* service_ofldq() is processing sendq */
779 u8 full; /* the Tx ring is full */
780 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
781 } ____cacheline_aligned_in_smp;
783 struct sge_ctrl_txq { /* state for an SGE control Tx queue */
785 struct adapter *adap;
786 struct sk_buff_head sendq; /* list of backpressured packets */
787 struct tasklet_struct qresume_tsk; /* restarts the queue */
788 u8 full; /* the Tx ring is full */
789 } ____cacheline_aligned_in_smp;
791 struct sge_uld_rxq_info {
792 char name[IFNAMSIZ]; /* name of ULD driver */
793 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */
794 u16 *rspq_id; /* response queue id's of rxq */
795 u16 nrxq; /* # of ingress uld queues */
796 u16 nciq; /* # of completion queues */
797 u8 uld; /* uld type */
800 struct sge_uld_txq_info {
801 struct sge_uld_txq *uldtxq; /* Txq's for ULD */
802 atomic_t users; /* num users */
803 u16 ntxq; /* # of egress uld queues */
806 enum sge_eosw_state {
807 CXGB4_EO_STATE_CLOSED = 0, /* Not ready to accept traffic */
810 struct sge_eosw_desc {
811 struct sk_buff *skb; /* SKB to free after getting completion */
812 dma_addr_t addr[MAX_SKB_FRAGS + 1]; /* DMA mapped addresses */
815 struct sge_eosw_txq {
816 spinlock_t lock; /* Per queue lock to synchronize completions */
817 enum sge_eosw_state state; /* Current ETHOFLD State */
818 struct sge_eosw_desc *desc; /* Descriptor ring to hold packets */
819 u32 ndesc; /* Number of descriptors */
820 u32 pidx; /* Current Producer Index */
821 u32 last_pidx; /* Last successfully transmitted Producer Index */
822 u32 cidx; /* Current Consumer Index */
823 u32 last_cidx; /* Last successfully reclaimed Consumer Index */
824 u32 inuse; /* Number of packets held in ring */
826 u32 cred; /* Current available credits */
827 u32 ncompl; /* # of completions posted */
828 u32 last_compl; /* # of credits consumed since last completion req */
830 u32 eotid; /* Index into EOTID table in software */
831 u32 hwtid; /* Hardware EOTID index */
833 u32 hwqid; /* Underlying hardware queue index */
834 struct net_device *netdev; /* Pointer to netdevice */
835 struct tasklet_struct qresume_tsk; /* Restarts the queue */
838 struct sge_eohw_txq {
839 spinlock_t lock; /* Per queue lock */
840 struct sge_txq q; /* HW Txq */
841 struct adapter *adap; /* Backpointer to adapter */
842 unsigned long tso; /* # of TSO requests */
843 unsigned long tx_cso; /* # of Tx checksum offloads */
844 unsigned long vlan_ins; /* # of Tx VLAN insertions */
845 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
849 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
850 struct sge_eth_txq ptptxq;
851 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
853 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
854 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
855 struct sge_uld_rxq_info **uld_rxq_info;
856 struct sge_uld_txq_info **uld_txq_info;
858 struct sge_rspq intrq ____cacheline_aligned_in_smp;
859 spinlock_t intrq_lock;
861 struct sge_eohw_txq *eohw_txq;
862 struct sge_ofld_rxq *eohw_rxq;
864 u16 max_ethqsets; /* # of available Ethernet queue sets */
865 u16 ethqsets; /* # of active Ethernet queue sets */
866 u16 ethtxq_rover; /* Tx queue to clean up next */
867 u16 ofldqsets; /* # of active ofld queue sets */
868 u16 nqs_per_uld; /* # of Rx queues per ULD */
869 u16 eoqsets; /* # of ETHOFLD queues */
871 u16 timer_val[SGE_NTIMERS];
872 u8 counter_val[SGE_NCOUNTERS];
874 u16 dbqtimer_val[SGE_NDBQTIMERS];
875 u32 fl_pg_order; /* large page allocation size */
876 u32 stat_len; /* length of status page at ring end */
877 u32 pktshift; /* padding between CPL & packet data */
878 u32 fl_align; /* response queue message alignment */
879 u32 fl_starve_thres; /* Free List starvation threshold */
881 struct sge_idma_monitor_state idma_monitor;
882 unsigned int egr_start;
884 unsigned int ingr_start;
885 unsigned int ingr_sz;
886 void **egr_map; /* qid->queue egress queue map */
887 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
888 unsigned long *starving_fl;
889 unsigned long *txq_maperr;
890 unsigned long *blocked_fl;
891 struct timer_list rx_timer; /* refills starving FLs */
892 struct timer_list tx_timer; /* checks Tx queues */
894 int fwevtq_msix_idx; /* Index to firmware event queue MSI-X info */
895 int nd_msix_idx; /* Index to non-data interrupts MSI-X info */
898 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
899 #define for_each_ofldtxq(sge, i) for (i = 0; i < (sge)->ofldqsets; i++)
903 #ifdef CONFIG_PCI_IOV
905 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
906 * Configuration initialization for T5 only has SR-IOV functionality enabled
907 * on PF0-3 in order to simplify everything.
909 #define NUM_OF_PF_WITH_SRIOV 4
913 struct doorbell_stats {
919 struct hash_mac_addr {
920 struct list_head list;
922 unsigned int iface_mac;
926 unsigned long *msix_bmap;
927 unsigned int mapsize;
928 spinlock_t lock; /* lock for acquiring bitmap */
933 char desc[IFNAMSIZ + 10];
935 cpumask_var_t aff_mask;
939 unsigned char vf_mac_addr[ETH_ALEN];
940 unsigned int tx_rate;
947 HMA_DMA_MAPPED_FLAG = 1
952 struct sg_table *sgt;
953 dma_addr_t *phy_addr; /* physical address of the page */
957 struct list_head list;
960 #if IS_ENABLED(CONFIG_THERMAL)
962 struct thermal_zone_device *tzdev;
968 struct mps_entries_ref {
969 struct list_head list;
980 struct pci_dev *pdev;
981 struct device *pdev_dev;
986 unsigned int adap_idx;
996 struct adapter_params params;
997 struct cxgb4_virt_res vres;
1000 /* MSI-X Info for NIC and OFLD queues */
1001 struct msix_info *msix_info;
1002 struct msix_bmap msix_bmap;
1004 struct doorbell_stats db_stats;
1007 struct net_device *port[MAX_NPORTS];
1008 u8 chan_map[NCHAN]; /* channel -> port map */
1010 struct vf_info *vfinfo;
1014 unsigned int l2t_start;
1015 unsigned int l2t_end;
1016 struct l2t_data *l2t;
1017 unsigned int clipt_start;
1018 unsigned int clipt_end;
1019 struct clip_tbl *clipt;
1020 unsigned int rawf_start;
1021 unsigned int rawf_cnt;
1022 struct smt_data *smt;
1023 struct cxgb4_uld_info *uld;
1024 void *uld_handle[CXGB4_ULD_MAX];
1025 unsigned int num_uld;
1026 unsigned int num_ofld_uld;
1027 struct list_head list_node;
1028 struct list_head rcu_node;
1029 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */
1030 struct list_head mps_ref;
1031 spinlock_t mps_ref_lock; /* lock for syncing mps ref/def activities */
1035 struct tid_info tids;
1036 void **tid_release_head;
1037 spinlock_t tid_release_lock;
1038 struct workqueue_struct *workq;
1039 struct work_struct tid_release_task;
1040 struct work_struct db_full_task;
1041 struct work_struct db_drop_task;
1042 struct work_struct fatal_err_notify_task;
1043 bool tid_release_task_busy;
1045 /* lock for mailbox cmd list */
1046 spinlock_t mbox_lock;
1047 struct mbox_list mlist;
1049 /* support for mailbox command/reply logging */
1050 #define T4_OS_LOG_MBOX_CMDS 256
1051 struct mbox_cmd_log *mbox_log;
1053 struct mutex uld_mutex;
1055 struct dentry *debugfs_root;
1056 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
1057 bool trace_rss; /* 1 implies that different RSS flit per filter is
1058 * used per filter else if 0 default RSS flit is
1059 * used for all 4 filters.
1062 struct ptp_clock *ptp_clock;
1063 struct ptp_clock_info ptp_clock_info;
1064 struct sk_buff *ptp_tx_skb;
1066 spinlock_t ptp_lock;
1067 spinlock_t stats_lock;
1068 spinlock_t win0_lock ____cacheline_aligned_in_smp;
1070 /* TC u32 offload */
1071 struct cxgb4_tc_u32_table *tc_u32;
1072 struct chcr_stats_debug chcr_stats;
1074 /* TC flower offload */
1075 bool tc_flower_initialized;
1076 struct rhashtable flower_tbl;
1077 struct rhashtable_params flower_ht_params;
1078 struct timer_list flower_stats_timer;
1079 struct work_struct flower_stats_work;
1082 struct ethtool_dump eth_dump;
1085 struct hma_data hma;
1087 struct srq_data *srq;
1089 /* Dump buffer for collecting logs in kdump kernel */
1090 struct vmcoredd_data vmcoredd;
1091 #if IS_ENABLED(CONFIG_THERMAL)
1092 struct ch_thermal ch_thermal;
1095 /* TC MQPRIO offload */
1096 struct cxgb4_tc_mqprio *tc_mqprio;
1099 /* Support for "sched-class" command to allow a TX Scheduling Class to be
1100 * programmed with various parameters.
1102 struct ch_sched_params {
1103 s8 type; /* packet or flow */
1106 s8 level; /* scheduler hierarchy level */
1107 s8 mode; /* per-class or per-flow */
1108 s8 rateunit; /* bit or packet rate */
1109 s8 ratemode; /* %port relative or kbps absolute */
1110 s8 channel; /* scheduler channel [0..N] */
1111 s8 class; /* scheduler class [0..N] */
1112 s32 minrate; /* minimum rate */
1113 s32 maxrate; /* maximum rate */
1114 s16 weight; /* percent weight */
1115 s16 pktsize; /* average packet size */
1121 SCHED_CLASS_TYPE_PACKET = 0, /* class type */
1125 SCHED_CLASS_LEVEL_CL_RL = 0, /* class rate limiter */
1129 SCHED_CLASS_MODE_CLASS = 0, /* per-class scheduling */
1133 SCHED_CLASS_RATEUNIT_BITS = 0, /* bit rate scheduling */
1137 SCHED_CLASS_RATEMODE_ABS = 1, /* Kb/s */
1140 struct tx_sw_desc { /* SW state per Tx descriptor */
1141 struct sk_buff *skb;
1142 struct ulptx_sgl *sgl;
1145 /* Support for "sched_queue" command to allow one or more NIC TX Queues
1146 * to be bound to a TX Scheduling Class.
1148 struct ch_sched_queue {
1149 s8 queue; /* queue index */
1150 s8 class; /* class index */
1153 /* Defined bit width of user definable filter tuples
1155 #define ETHTYPE_BITWIDTH 16
1156 #define FRAG_BITWIDTH 1
1157 #define MACIDX_BITWIDTH 9
1158 #define FCOE_BITWIDTH 1
1159 #define IPORT_BITWIDTH 3
1160 #define MATCHTYPE_BITWIDTH 3
1161 #define PROTO_BITWIDTH 8
1162 #define TOS_BITWIDTH 8
1163 #define PF_BITWIDTH 8
1164 #define VF_BITWIDTH 8
1165 #define IVLAN_BITWIDTH 16
1166 #define OVLAN_BITWIDTH 16
1167 #define ENCAP_VNI_BITWIDTH 24
1169 /* Filter matching rules. These consist of a set of ingress packet field
1170 * (value, mask) tuples. The associated ingress packet field matches the
1171 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
1172 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
1173 * matches an ingress packet when all of the individual individual field
1174 * matching rules are true.
1176 * Partial field masks are always valid, however, while it may be easy to
1177 * understand their meanings for some fields (e.g. IP address to match a
1178 * subnet), for others making sensible partial masks is less intuitive (e.g.
1179 * MPS match type) ...
1181 * Most of the following data structures are modeled on T4 capabilities.
1182 * Drivers for earlier chips use the subsets which make sense for those chips.
1183 * We really need to come up with a hardware-independent mechanism to
1184 * represent hardware filter capabilities ...
1186 struct ch_filter_tuple {
1187 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
1188 * register selects which of these fields will participate in the
1189 * filter match rules -- up to a maximum of 36 bits. Because
1190 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
1193 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
1194 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
1195 uint32_t ivlan_vld:1; /* inner VLAN valid */
1196 uint32_t ovlan_vld:1; /* outer VLAN valid */
1197 uint32_t pfvf_vld:1; /* PF/VF valid */
1198 uint32_t encap_vld:1; /* Encapsulation valid */
1199 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
1200 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
1201 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
1202 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
1203 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
1204 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
1205 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
1206 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
1207 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
1208 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
1209 uint32_t vni:ENCAP_VNI_BITWIDTH; /* VNI of tunnel */
1211 /* Uncompressed header matching field rules. These are always
1212 * available for field rules.
1214 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
1215 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
1216 uint16_t lport; /* local port */
1217 uint16_t fport; /* foreign port */
1220 /* A filter ioctl command.
1222 struct ch_filter_specification {
1223 /* Administrative fields for filter.
1225 uint32_t hitcnts:1; /* count filter hits in TCB */
1226 uint32_t prio:1; /* filter has priority over active/server */
1228 /* Fundamental filter typing. This is the one element of filter
1229 * matching that doesn't exist as a (value, mask) tuple.
1231 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
1232 u32 hash:1; /* 0 => wild-card, 1 => exact-match */
1234 /* Packet dispatch information. Ingress packets which match the
1235 * filter rules will be dropped, passed to the host or switched back
1236 * out as egress packets.
1238 uint32_t action:2; /* drop, pass, switch */
1240 uint32_t rpttid:1; /* report TID in RSS hash field */
1242 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
1243 uint32_t iq:10; /* ingress queue */
1245 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
1246 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
1247 /* 1 => TCB contains IQ ID */
1249 /* Switch proxy/rewrite fields. An ingress packet which matches a
1250 * filter with "switch" set will be looped back out as an egress
1251 * packet -- potentially with some Ethernet header rewriting.
1253 uint32_t eport:2; /* egress port to switch packet out */
1254 uint32_t newdmac:1; /* rewrite destination MAC address */
1255 uint32_t newsmac:1; /* rewrite source MAC address */
1256 uint32_t newvlan:2; /* rewrite VLAN Tag */
1257 uint32_t nat_mode:3; /* specify NAT operation mode */
1258 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
1259 uint8_t smac[ETH_ALEN]; /* new source MAC address */
1260 uint16_t vlan; /* VLAN Tag to insert */
1262 u8 nat_lip[16]; /* local IP to use after NAT'ing */
1263 u8 nat_fip[16]; /* foreign IP to use after NAT'ing */
1264 u16 nat_lport; /* local port to use after NAT'ing */
1265 u16 nat_fport; /* foreign port to use after NAT'ing */
1267 /* reservation for future additions */
1270 /* Filter rule value/mask pairs.
1272 struct ch_filter_tuple val;
1273 struct ch_filter_tuple mask;
1277 FILTER_PASS = 0, /* default */
1283 VLAN_NOCHANGE = 0, /* default */
1290 NAT_MODE_NONE = 0, /* No NAT performed */
1291 NAT_MODE_DIP, /* NAT on Dst IP */
1292 NAT_MODE_DIP_DP, /* NAT on Dst IP, Dst Port */
1293 NAT_MODE_DIP_DP_SIP, /* NAT on Dst IP, Dst Port and Src IP */
1294 NAT_MODE_DIP_DP_SP, /* NAT on Dst IP, Dst Port and Src Port */
1295 NAT_MODE_SIP_SP, /* NAT on Src IP and Src Port */
1296 NAT_MODE_DIP_SIP_SP, /* NAT on Dst IP, Src IP and Src Port */
1297 NAT_MODE_ALL /* NAT on entire 4-tuple */
1300 /* Host shadow copy of ingress filter entry. This is in host native format
1301 * and doesn't match the ordering or bit order, etc. of the hardware of the
1302 * firmware command. The use of bit-field structure elements is purely to
1303 * remind ourselves of the field size limitations and save memory in the case
1304 * where the filter table is large.
1306 struct filter_entry {
1307 /* Administrative fields for filter. */
1308 u32 valid:1; /* filter allocated and valid */
1309 u32 locked:1; /* filter is administratively locked */
1311 u32 pending:1; /* filter action is pending firmware reply */
1312 struct filter_ctx *ctx; /* Caller's completion hook */
1313 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
1314 struct smt_entry *smt; /* Source Mac Table entry for smac */
1315 struct net_device *dev; /* Associated net device */
1316 u32 tid; /* This will store the actual tid */
1318 /* The filter itself. Most of this is a straight copy of information
1319 * provided by the extended ioctl(). Some fields are translated to
1320 * internal forms -- for instance the Ingress Queue ID passed in from
1321 * the ioctl() is translated into the Absolute Ingress Queue ID.
1323 struct ch_filter_specification fs;
1326 static inline int is_offload(const struct adapter *adap)
1328 return adap->params.offload;
1331 static inline int is_hashfilter(const struct adapter *adap)
1333 return adap->params.hash_filter;
1336 static inline int is_pci_uld(const struct adapter *adap)
1338 return adap->params.crypto;
1341 static inline int is_uld(const struct adapter *adap)
1343 return (adap->params.offload || adap->params.crypto);
1346 static inline int is_ethofld(const struct adapter *adap)
1348 return adap->params.ethofld;
1351 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1353 return readl(adap->regs + reg_addr);
1356 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1358 writel(val, adap->regs + reg_addr);
1362 static inline u64 readq(const volatile void __iomem *addr)
1364 return readl(addr) + ((u64)readl(addr + 4) << 32);
1367 static inline void writeq(u64 val, volatile void __iomem *addr)
1370 writel(val >> 32, addr + 4);
1374 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1376 return readq(adap->regs + reg_addr);
1379 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1381 writeq(val, adap->regs + reg_addr);
1385 * t4_set_hw_addr - store a port's MAC address in SW
1386 * @adapter: the adapter
1387 * @port_idx: the port index
1388 * @hw_addr: the Ethernet address
1390 * Store the Ethernet address of the given port in SW. Called by the common
1391 * code when it retrieves a port's Ethernet address from EEPROM.
1393 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1396 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1397 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1401 * netdev2pinfo - return the port_info structure associated with a net_device
1404 * Return the struct port_info associated with a net_device
1406 static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1408 return netdev_priv(dev);
1412 * adap2pinfo - return the port_info of a port
1413 * @adap: the adapter
1414 * @idx: the port index
1416 * Return the port_info structure for the port of the given index.
1418 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1420 return netdev_priv(adap->port[idx]);
1424 * netdev2adap - return the adapter structure associated with a net_device
1427 * Return the struct adapter associated with a net_device
1429 static inline struct adapter *netdev2adap(const struct net_device *dev)
1431 return netdev2pinfo(dev)->adapter;
1434 /* Return a version number to identify the type of adapter. The scheme is:
1435 * - bits 0..9: chip version
1436 * - bits 10..15: chip revision
1437 * - bits 16..23: register dump version
1439 static inline unsigned int mk_adap_vers(struct adapter *ap)
1441 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1442 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1445 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1446 static inline unsigned int qtimer_val(const struct adapter *adap,
1447 const struct sge_rspq *q)
1449 unsigned int idx = q->intr_params >> 1;
1451 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1454 /* driver version & name used for ethtool_drvinfo */
1455 extern char cxgb4_driver_name[];
1456 extern const char cxgb4_driver_version[];
1458 void t4_os_portmod_changed(struct adapter *adap, int port_id);
1459 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1461 void t4_free_sge_resources(struct adapter *adap);
1462 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1463 irq_handler_t t4_intr_handler(struct adapter *adap);
1464 netdev_tx_t t4_start_xmit(struct sk_buff *skb, struct net_device *dev);
1465 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1466 const struct pkt_gl *gl);
1467 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1468 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1469 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1470 struct net_device *dev, int intr_idx,
1471 struct sge_fl *fl, rspq_handler_t hnd,
1472 rspq_flush_handler_t flush_handler, int cong);
1473 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1474 struct net_device *dev, struct netdev_queue *netdevq,
1475 unsigned int iqid, u8 dbqt);
1476 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1477 struct net_device *dev, unsigned int iqid,
1478 unsigned int cmplqid);
1479 int t4_sge_mod_ctrl_txq(struct adapter *adap, unsigned int eqid,
1480 unsigned int cmplqid);
1481 int t4_sge_alloc_uld_txq(struct adapter *adap, struct sge_uld_txq *txq,
1482 struct net_device *dev, unsigned int iqid,
1483 unsigned int uld_type);
1484 int t4_sge_alloc_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq,
1485 struct net_device *dev, u32 iqid);
1486 void t4_sge_free_ethofld_txq(struct adapter *adap, struct sge_eohw_txq *txq);
1487 irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1488 int t4_sge_init(struct adapter *adap);
1489 void t4_sge_start(struct adapter *adap);
1490 void t4_sge_stop(struct adapter *adap);
1491 int t4_sge_eth_txq_egress_update(struct adapter *adap, struct sge_eth_txq *q,
1493 void cxgb4_set_ethtool_ops(struct net_device *netdev);
1494 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1495 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb);
1496 extern int dbfifo_int_thresh;
1498 #define for_each_port(adapter, iter) \
1499 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1501 static inline int is_bypass(struct adapter *adap)
1503 return adap->params.bypass;
1506 static inline int is_bypass_device(int device)
1508 /* this should be set based upon device capabilities */
1518 static inline int is_10gbt_device(int device)
1520 /* this should be set based upon device capabilities */
1531 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1533 return adap->params.vpd.cclk / 1000;
1536 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1539 return (us * adap->params.vpd.cclk) / 1000;
1542 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1545 /* add Core Clock / 2 to round ticks to nearest uS */
1546 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1547 adapter->params.vpd.cclk);
1550 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
1553 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
1556 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1559 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1560 int size, void *rpl, bool sleep_ok, int timeout);
1561 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1562 void *rpl, bool sleep_ok);
1564 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1565 const void *cmd, int size, void *rpl,
1568 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1572 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1573 int size, void *rpl)
1575 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1578 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1579 int size, void *rpl)
1581 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1585 * hash_mac_addr - return the hash value of a MAC address
1586 * @addr: the 48-bit Ethernet MAC address
1588 * Hashes a MAC address according to the hash function used by HW inexact
1589 * (hash) address matching.
1591 static inline int hash_mac_addr(const u8 *addr)
1593 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1594 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1602 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1604 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1605 unsigned int us, unsigned int cnt,
1606 unsigned int size, unsigned int iqe_size)
1609 cxgb4_set_rspq_intr_params(q, us, cnt);
1610 q->iqe_len = iqe_size;
1615 * t4_is_inserted_mod_type - is a plugged in Firmware Module Type
1616 * @fw_mod_type: the Firmware Mofule Type
1618 * Return whether the Firmware Module Type represents a real Transceiver
1619 * Module/Cable Module Type which has been inserted.
1621 static inline bool t4_is_inserted_mod_type(unsigned int fw_mod_type)
1623 return (fw_mod_type != FW_PORT_MOD_TYPE_NONE &&
1624 fw_mod_type != FW_PORT_MOD_TYPE_NOTSUPPORTED &&
1625 fw_mod_type != FW_PORT_MOD_TYPE_UNKNOWN &&
1626 fw_mod_type != FW_PORT_MOD_TYPE_ERROR);
1629 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1630 unsigned int data_reg, const u32 *vals,
1631 unsigned int nregs, unsigned int start_idx);
1632 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1633 unsigned int data_reg, u32 *vals, unsigned int nregs,
1634 unsigned int start_idx);
1635 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1637 struct fw_filter_wr;
1639 void t4_intr_enable(struct adapter *adapter);
1640 void t4_intr_disable(struct adapter *adapter);
1641 int t4_slow_intr_handler(struct adapter *adapter);
1643 int t4_wait_dev_ready(void __iomem *regs);
1645 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
1646 struct link_config *lc);
1647 int t4_link_l1cfg_core(struct adapter *adap, unsigned int mbox,
1648 unsigned int port, struct link_config *lc,
1649 u8 sleep_ok, int timeout);
1651 static inline int t4_link_l1cfg(struct adapter *adapter, unsigned int mbox,
1652 unsigned int port, struct link_config *lc)
1654 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1655 true, FW_CMD_MAX_TIMEOUT);
1658 static inline int t4_link_l1cfg_ns(struct adapter *adapter, unsigned int mbox,
1659 unsigned int port, struct link_config *lc)
1661 return t4_link_l1cfg_core(adapter, mbox, port, lc,
1662 false, FW_CMD_MAX_TIMEOUT);
1665 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1667 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1668 u32 t4_get_util_window(struct adapter *adap);
1669 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1671 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
1672 u32 *mem_base, u32 *mem_aperture);
1673 void t4_memory_update_win(struct adapter *adap, int win, u32 addr);
1674 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
1676 #define T4_MEMORY_WRITE 0
1677 #define T4_MEMORY_READ 1
1678 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1679 void *buf, int dir);
1680 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1681 u32 len, __be32 *buf)
1683 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1686 unsigned int t4_get_regs_len(struct adapter *adapter);
1687 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1689 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
1690 int t4_seeprom_wp(struct adapter *adapter, bool enable);
1691 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1692 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1693 int t4_get_pfres(struct adapter *adapter);
1694 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1695 unsigned int nwords, u32 *data, int byte_oriented);
1696 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1697 int t4_load_phy_fw(struct adapter *adap,
1698 int win, spinlock_t *lock,
1699 int (*phy_fw_version)(const u8 *, size_t),
1700 const u8 *phy_fw_data, size_t phy_fw_size);
1701 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1702 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1703 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1704 const u8 *fw_data, unsigned int size, int force);
1705 int t4_fl_pkt_align(struct adapter *adap);
1706 unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1707 int t4_check_fw_version(struct adapter *adap);
1708 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
1709 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1710 int t4_get_bs_version(struct adapter *adapter, u32 *vers);
1711 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1712 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1713 int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
1714 int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
1715 int t4_get_version_info(struct adapter *adapter);
1716 void t4_dump_version_info(struct adapter *adapter);
1717 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1718 const u8 *fw_data, unsigned int fw_size,
1719 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1720 int t4_prep_adapter(struct adapter *adapter);
1721 int t4_shutdown_adapter(struct adapter *adapter);
1723 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1724 int t4_bar2_sge_qregs(struct adapter *adapter,
1726 enum t4_bar2_qtype qtype,
1729 unsigned int *pbar2_qid);
1731 unsigned int qtimer_val(const struct adapter *adap,
1732 const struct sge_rspq *q);
1734 int t4_init_devlog_params(struct adapter *adapter);
1735 int t4_init_sge_params(struct adapter *adapter);
1736 int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
1737 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1738 int t4_init_rss_mode(struct adapter *adap, int mbox);
1739 int t4_init_portinfo(struct port_info *pi, int mbox,
1740 int port, int pf, int vf, u8 mac[]);
1741 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1742 void t4_fatal_err(struct adapter *adapter);
1743 unsigned int t4_chip_rss_size(struct adapter *adapter);
1744 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1745 int start, int n, const u16 *rspq, unsigned int nrspq);
1746 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1747 unsigned int flags);
1748 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1749 unsigned int flags, unsigned int defq);
1750 int t4_read_rss(struct adapter *adapter, u16 *entries);
1751 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
1752 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
1754 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1755 u32 *valp, bool sleep_ok);
1756 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1757 u32 *vfl, u32 *vfh, bool sleep_ok);
1758 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
1759 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
1761 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx);
1762 unsigned int t4_get_tp_ch_map(struct adapter *adapter, int pidx);
1763 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1764 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1765 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1767 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1769 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1770 unsigned int *valp);
1771 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1772 const unsigned int *valp);
1773 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1774 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1775 unsigned int *pif_req_wrptr,
1776 unsigned int *pif_rsp_wrptr);
1777 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1778 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1779 const char *t4_get_port_type_description(enum fw_port_type port_type);
1780 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1781 void t4_get_port_stats_offset(struct adapter *adap, int idx,
1782 struct port_stats *stats,
1783 struct port_stats *offset);
1784 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1785 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1786 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1787 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1788 unsigned int mask, unsigned int val);
1789 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1790 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
1792 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
1794 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
1796 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
1798 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1799 struct tp_tcp_stats *v6, bool sleep_ok);
1800 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1801 struct tp_fcoe_stats *st, bool sleep_ok);
1802 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1803 const unsigned short *alpha, const unsigned short *beta);
1805 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1807 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1808 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1810 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1812 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1813 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1815 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1816 enum dev_master master, enum dev_state *state);
1817 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1818 int t4_early_init(struct adapter *adap, unsigned int mbox);
1819 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1820 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1821 unsigned int cache_line_size);
1822 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1823 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1824 unsigned int vf, unsigned int nparams, const u32 *params,
1826 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
1827 unsigned int vf, unsigned int nparams, const u32 *params,
1829 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1830 unsigned int vf, unsigned int nparams, const u32 *params,
1831 u32 *val, int rw, bool sleep_ok);
1832 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1833 unsigned int pf, unsigned int vf,
1834 unsigned int nparams, const u32 *params,
1835 const u32 *val, int timeout);
1836 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1837 unsigned int vf, unsigned int nparams, const u32 *params,
1839 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1840 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1841 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1842 unsigned int vi, unsigned int cmask, unsigned int pmask,
1843 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1844 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1845 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1846 unsigned int *rss_size, u8 *vivld, u8 *vin);
1847 int t4_free_vi(struct adapter *adap, unsigned int mbox,
1848 unsigned int pf, unsigned int vf,
1850 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1851 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1853 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
1854 const u8 *addr, const u8 *mask, unsigned int idx,
1855 u8 lookup_type, u8 port_id, bool sleep_ok);
1856 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, int idx,
1858 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
1859 const u8 *addr, const u8 *mask, unsigned int vni,
1860 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
1862 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
1863 const u8 *addr, const u8 *mask, unsigned int idx,
1864 u8 lookup_type, u8 port_id, bool sleep_ok);
1865 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1866 unsigned int viid, bool free, unsigned int naddr,
1867 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1868 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
1869 unsigned int viid, unsigned int naddr,
1870 const u8 **addr, bool sleep_ok);
1871 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1872 int idx, const u8 *addr, bool persist, u8 *smt_idx);
1873 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1874 bool ucast, u64 vec, bool sleep_ok);
1875 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1876 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1877 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
1878 struct port_info *pi,
1879 bool rx_en, bool tx_en, bool dcb_en);
1880 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1881 bool rx_en, bool tx_en);
1882 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1883 unsigned int nblinks);
1884 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1885 unsigned int mmd, unsigned int reg, u16 *valp);
1886 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1887 unsigned int mmd, unsigned int reg, u16 val);
1888 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
1889 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1890 unsigned int fl0id, unsigned int fl1id);
1891 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1892 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1893 unsigned int fl0id, unsigned int fl1id);
1894 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1895 unsigned int vf, unsigned int eqid);
1896 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1897 unsigned int vf, unsigned int eqid);
1898 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1899 unsigned int vf, unsigned int eqid);
1900 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type);
1901 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
1903 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
1904 int t4_update_port_info(struct port_info *pi);
1905 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
1906 unsigned int *speedp, unsigned int *mtup);
1907 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1908 void t4_db_full(struct adapter *adapter);
1909 void t4_db_dropped(struct adapter *adapter);
1910 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1911 int filter_index, int enable);
1912 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1913 int filter_index, int *enabled);
1914 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1916 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
1917 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
1918 unsigned int *kbps, unsigned int *ipg, bool sleep_ok);
1919 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
1920 enum ctxt_type ctype, u32 *data);
1921 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
1922 enum ctxt_type ctype, u32 *data);
1923 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
1924 int rateunit, int ratemode, int channel, int class,
1925 int minrate, int maxrate, int weight, int pktsize);
1926 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
1927 void t4_idma_monitor_init(struct adapter *adapter,
1928 struct sge_idma_monitor_state *idma);
1929 void t4_idma_monitor(struct adapter *adapter,
1930 struct sge_idma_monitor_state *idma,
1932 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
1933 unsigned int naddr, u8 *addr);
1934 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1935 u32 start_index, bool sleep_ok);
1936 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
1937 u32 start_index, bool sleep_ok);
1938 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
1939 u32 start_index, bool sleep_ok);
1941 void t4_uld_mem_free(struct adapter *adap);
1942 int t4_uld_mem_alloc(struct adapter *adap);
1943 void t4_uld_clean_up(struct adapter *adap);
1944 void t4_register_netevent_notifier(void);
1945 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
1946 unsigned int devid, unsigned int offset,
1947 unsigned int len, u8 *buf);
1948 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
1949 void free_tx_desc(struct adapter *adap, struct sge_txq *q,
1950 unsigned int n, bool unmap);
1951 void cxgb4_eosw_txq_free_desc(struct adapter *adap, struct sge_eosw_txq *txq,
1953 void cxgb4_ethofld_restart(unsigned long data);
1954 void free_txq(struct adapter *adap, struct sge_txq *q);
1955 void cxgb4_reclaim_completed_tx(struct adapter *adap,
1956 struct sge_txq *q, bool unmap);
1957 int cxgb4_map_skb(struct device *dev, const struct sk_buff *skb,
1959 void cxgb4_inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
1961 void cxgb4_write_sgl(const struct sk_buff *skb, struct sge_txq *q,
1962 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
1963 const dma_addr_t *addr);
1964 void cxgb4_ring_tx_db(struct adapter *adap, struct sge_txq *q, int n);
1965 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
1967 int cxgb4_dcb_enabled(const struct net_device *dev);
1969 int cxgb4_thermal_init(struct adapter *adap);
1970 int cxgb4_thermal_remove(struct adapter *adap);
1971 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec,
1972 cpumask_var_t *aff_mask, int idx);
1973 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask);
1975 int cxgb4_change_mac(struct port_info *pi, unsigned int viid,
1976 int *tcam_idx, const u8 *addr,
1977 bool persistent, u8 *smt_idx);
1979 int cxgb4_alloc_mac_filt(struct adapter *adap, unsigned int viid,
1980 bool free, unsigned int naddr,
1981 const u8 **addr, u16 *idx,
1982 u64 *hash, bool sleep_ok);
1983 int cxgb4_free_mac_filt(struct adapter *adap, unsigned int viid,
1984 unsigned int naddr, const u8 **addr, bool sleep_ok);
1985 int cxgb4_init_mps_ref_entries(struct adapter *adap);
1986 void cxgb4_free_mps_ref_entries(struct adapter *adap);
1987 int cxgb4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
1988 const u8 *addr, const u8 *mask,
1989 unsigned int vni, unsigned int vni_mask,
1990 u8 dip_hit, u8 lookup_type, bool sleep_ok);
1991 int cxgb4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
1992 int idx, bool sleep_ok);
1993 int cxgb4_free_raw_mac_filt(struct adapter *adap,
2001 int cxgb4_alloc_raw_mac_filt(struct adapter *adap,
2009 int cxgb4_update_mac_filt(struct port_info *pi, unsigned int viid,
2010 int *tcam_idx, const u8 *addr,
2011 bool persistent, u8 *smt_idx);
2012 int cxgb4_get_msix_idx_from_bmap(struct adapter *adap);
2013 void cxgb4_free_msix_idx_in_bmap(struct adapter *adap, u32 msix_idx);
2014 int cxgb_open(struct net_device *dev);
2015 int cxgb_close(struct net_device *dev);
2016 void cxgb4_enable_rx(struct adapter *adap, struct sge_rspq *q);
2017 void cxgb4_quiesce_rx(struct sge_rspq *q);
2018 #endif /* __CXGB4_H__ */