2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #ifndef _T4FW_INTERFACE_H_
36 #define _T4FW_INTERFACE_H_
39 FW_SUCCESS = 0, /* completed sucessfully */
40 FW_EPERM = 1, /* operation not permitted */
41 FW_ENOENT = 2, /* no such file or directory */
42 FW_EIO = 5, /* input/output error; hw bad */
43 FW_ENOEXEC = 8, /* exec format error; inv microcode */
44 FW_EAGAIN = 11, /* try again */
45 FW_ENOMEM = 12, /* out of memory */
46 FW_EFAULT = 14, /* bad address; fw bad */
47 FW_EBUSY = 16, /* resource busy */
48 FW_EEXIST = 17, /* file exists */
49 FW_EINVAL = 22, /* invalid argument */
50 FW_ENOSPC = 28, /* no space left on device */
51 FW_ENOSYS = 38, /* functionality not implemented */
52 FW_EPROTO = 71, /* protocol error */
53 FW_EADDRINUSE = 98, /* address already in use */
54 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
55 FW_ENETDOWN = 100, /* network is down */
56 FW_ENETUNREACH = 101, /* network is unreachable */
57 FW_ENOBUFS = 105, /* no buffer space available */
58 FW_ETIMEDOUT = 110, /* timeout */
59 FW_EINPROGRESS = 115, /* fw internal */
60 FW_SCSI_ABORT_REQUESTED = 128, /* */
61 FW_SCSI_ABORT_TIMEDOUT = 129, /* */
62 FW_SCSI_ABORTED = 130, /* */
63 FW_SCSI_CLOSE_REQUESTED = 131, /* */
64 FW_ERR_LINK_DOWN = 132, /* */
65 FW_RDEV_NOT_READY = 133, /* */
66 FW_ERR_RDEV_LOST = 134, /* */
67 FW_ERR_RDEV_LOGO = 135, /* */
68 FW_FCOE_NO_XCHG = 136, /* */
69 FW_SCSI_RSP_ERR = 137, /* */
70 FW_ERR_RDEV_IMPL_LOGO = 138, /* */
71 FW_SCSI_UNDER_FLOW_ERR = 139, /* */
72 FW_SCSI_OVER_FLOW_ERR = 140, /* */
73 FW_SCSI_DDP_ERR = 141, /* DDP error*/
74 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */
77 #define FW_T4VF_SGE_BASE_ADDR 0x0000
78 #define FW_T4VF_MPS_BASE_ADDR 0x0100
79 #define FW_T4VF_PL_BASE_ADDR 0x0200
80 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240
81 #define FW_T4VF_CIM_BASE_ADDR 0x0300
87 FW_ETH_TX_PKT_WR = 0x08,
88 FW_OFLD_CONNECTION_WR = 0x2f,
90 FW_OFLD_TX_DATA_WR = 0x0b,
92 FW_ETH_TX_PKT_VM_WR = 0x11,
95 FW_RI_RDMA_WRITE_WR = 0x14,
97 FW_RI_RDMA_READ_WR = 0x16,
99 FW_RI_BIND_MW_WR = 0x18,
100 FW_RI_FR_NSMR_WR = 0x19,
101 FW_RI_INV_LSTAG_WR = 0x1a,
110 #define FW_WR_OP(x) ((x) << 24)
111 #define FW_WR_OP_GET(x) (((x) >> 24) & 0xff)
112 #define FW_WR_ATOMIC(x) ((x) << 23)
113 #define FW_WR_FLUSH(x) ((x) << 22)
114 #define FW_WR_COMPL(x) ((x) << 21)
115 #define FW_WR_IMMDLEN_MASK 0xff
116 #define FW_WR_IMMDLEN(x) ((x) << 0)
118 #define FW_WR_EQUIQ (1U << 31)
119 #define FW_WR_EQUEQ (1U << 30)
120 #define FW_WR_FLOWID(x) ((x) << 8)
121 #define FW_WR_LEN16(x) ((x) << 0)
123 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B
124 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327
126 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
127 enum fw_filter_wr_cookie {
128 FW_FILTER_WR_SUCCESS,
129 FW_FILTER_WR_FLT_ADDED,
130 FW_FILTER_WR_FLT_DELETED,
131 FW_FILTER_WR_SMT_TBL_FULL,
135 struct fw_filter_wr {
140 __be32 del_filter_to_l2tix;
143 __u8 frag_to_ovlan_vldm;
145 __be16 rx_chan_rx_rpl_iq;
146 __be32 maci_to_matchtypem;
167 #define S_FW_FILTER_WR_TID 12
168 #define M_FW_FILTER_WR_TID 0xfffff
169 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
170 #define G_FW_FILTER_WR_TID(x) \
171 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
173 #define S_FW_FILTER_WR_RQTYPE 11
174 #define M_FW_FILTER_WR_RQTYPE 0x1
175 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
176 #define G_FW_FILTER_WR_RQTYPE(x) \
177 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
178 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U)
180 #define S_FW_FILTER_WR_NOREPLY 10
181 #define M_FW_FILTER_WR_NOREPLY 0x1
182 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
183 #define G_FW_FILTER_WR_NOREPLY(x) \
184 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
185 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U)
187 #define S_FW_FILTER_WR_IQ 0
188 #define M_FW_FILTER_WR_IQ 0x3ff
189 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
190 #define G_FW_FILTER_WR_IQ(x) \
191 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
193 #define S_FW_FILTER_WR_DEL_FILTER 31
194 #define M_FW_FILTER_WR_DEL_FILTER 0x1
195 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
196 #define G_FW_FILTER_WR_DEL_FILTER(x) \
197 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
198 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
200 #define S_FW_FILTER_WR_RPTTID 25
201 #define M_FW_FILTER_WR_RPTTID 0x1
202 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
203 #define G_FW_FILTER_WR_RPTTID(x) \
204 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
205 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U)
207 #define S_FW_FILTER_WR_DROP 24
208 #define M_FW_FILTER_WR_DROP 0x1
209 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
210 #define G_FW_FILTER_WR_DROP(x) \
211 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
212 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U)
214 #define S_FW_FILTER_WR_DIRSTEER 23
215 #define M_FW_FILTER_WR_DIRSTEER 0x1
216 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
217 #define G_FW_FILTER_WR_DIRSTEER(x) \
218 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
219 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U)
221 #define S_FW_FILTER_WR_MASKHASH 22
222 #define M_FW_FILTER_WR_MASKHASH 0x1
223 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
224 #define G_FW_FILTER_WR_MASKHASH(x) \
225 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
226 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U)
228 #define S_FW_FILTER_WR_DIRSTEERHASH 21
229 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1
230 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
231 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \
232 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
233 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U)
235 #define S_FW_FILTER_WR_LPBK 20
236 #define M_FW_FILTER_WR_LPBK 0x1
237 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
238 #define G_FW_FILTER_WR_LPBK(x) \
239 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
240 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U)
242 #define S_FW_FILTER_WR_DMAC 19
243 #define M_FW_FILTER_WR_DMAC 0x1
244 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
245 #define G_FW_FILTER_WR_DMAC(x) \
246 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
247 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U)
249 #define S_FW_FILTER_WR_SMAC 18
250 #define M_FW_FILTER_WR_SMAC 0x1
251 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC)
252 #define G_FW_FILTER_WR_SMAC(x) \
253 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
254 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U)
256 #define S_FW_FILTER_WR_INSVLAN 17
257 #define M_FW_FILTER_WR_INSVLAN 0x1
258 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
259 #define G_FW_FILTER_WR_INSVLAN(x) \
260 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
261 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U)
263 #define S_FW_FILTER_WR_RMVLAN 16
264 #define M_FW_FILTER_WR_RMVLAN 0x1
265 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
266 #define G_FW_FILTER_WR_RMVLAN(x) \
267 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
268 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U)
270 #define S_FW_FILTER_WR_HITCNTS 15
271 #define M_FW_FILTER_WR_HITCNTS 0x1
272 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
273 #define G_FW_FILTER_WR_HITCNTS(x) \
274 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
275 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U)
277 #define S_FW_FILTER_WR_TXCHAN 13
278 #define M_FW_FILTER_WR_TXCHAN 0x3
279 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
280 #define G_FW_FILTER_WR_TXCHAN(x) \
281 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
283 #define S_FW_FILTER_WR_PRIO 12
284 #define M_FW_FILTER_WR_PRIO 0x1
285 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
286 #define G_FW_FILTER_WR_PRIO(x) \
287 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
288 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U)
290 #define S_FW_FILTER_WR_L2TIX 0
291 #define M_FW_FILTER_WR_L2TIX 0xfff
292 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
293 #define G_FW_FILTER_WR_L2TIX(x) \
294 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
296 #define S_FW_FILTER_WR_FRAG 7
297 #define M_FW_FILTER_WR_FRAG 0x1
298 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
299 #define G_FW_FILTER_WR_FRAG(x) \
300 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
301 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U)
303 #define S_FW_FILTER_WR_FRAGM 6
304 #define M_FW_FILTER_WR_FRAGM 0x1
305 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
306 #define G_FW_FILTER_WR_FRAGM(x) \
307 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
308 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U)
310 #define S_FW_FILTER_WR_IVLAN_VLD 5
311 #define M_FW_FILTER_WR_IVLAN_VLD 0x1
312 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
313 #define G_FW_FILTER_WR_IVLAN_VLD(x) \
314 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
315 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U)
317 #define S_FW_FILTER_WR_OVLAN_VLD 4
318 #define M_FW_FILTER_WR_OVLAN_VLD 0x1
319 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
320 #define G_FW_FILTER_WR_OVLAN_VLD(x) \
321 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
322 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U)
324 #define S_FW_FILTER_WR_IVLAN_VLDM 3
325 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1
326 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
327 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \
328 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
329 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U)
331 #define S_FW_FILTER_WR_OVLAN_VLDM 2
332 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1
333 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
334 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \
335 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
336 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U)
338 #define S_FW_FILTER_WR_RX_CHAN 15
339 #define M_FW_FILTER_WR_RX_CHAN 0x1
340 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
341 #define G_FW_FILTER_WR_RX_CHAN(x) \
342 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
343 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U)
345 #define S_FW_FILTER_WR_RX_RPL_IQ 0
346 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff
347 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
348 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \
349 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
351 #define S_FW_FILTER_WR_MACI 23
352 #define M_FW_FILTER_WR_MACI 0x1ff
353 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
354 #define G_FW_FILTER_WR_MACI(x) \
355 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
357 #define S_FW_FILTER_WR_MACIM 14
358 #define M_FW_FILTER_WR_MACIM 0x1ff
359 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
360 #define G_FW_FILTER_WR_MACIM(x) \
361 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
363 #define S_FW_FILTER_WR_FCOE 13
364 #define M_FW_FILTER_WR_FCOE 0x1
365 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
366 #define G_FW_FILTER_WR_FCOE(x) \
367 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
368 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U)
370 #define S_FW_FILTER_WR_FCOEM 12
371 #define M_FW_FILTER_WR_FCOEM 0x1
372 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
373 #define G_FW_FILTER_WR_FCOEM(x) \
374 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
375 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U)
377 #define S_FW_FILTER_WR_PORT 9
378 #define M_FW_FILTER_WR_PORT 0x7
379 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
380 #define G_FW_FILTER_WR_PORT(x) \
381 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
383 #define S_FW_FILTER_WR_PORTM 6
384 #define M_FW_FILTER_WR_PORTM 0x7
385 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
386 #define G_FW_FILTER_WR_PORTM(x) \
387 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
389 #define S_FW_FILTER_WR_MATCHTYPE 3
390 #define M_FW_FILTER_WR_MATCHTYPE 0x7
391 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
392 #define G_FW_FILTER_WR_MATCHTYPE(x) \
393 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
395 #define S_FW_FILTER_WR_MATCHTYPEM 0
396 #define M_FW_FILTER_WR_MATCHTYPEM 0x7
397 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
398 #define G_FW_FILTER_WR_MATCHTYPEM(x) \
399 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
408 __be32 op_to_immdlen;
413 struct fw_eth_tx_pkt_wr {
415 __be32 equiq_to_len16;
419 struct fw_ofld_connection_wr {
425 struct fw_ofld_connection_le {
431 union fw_ofld_connection_leip {
432 struct fw_ofld_connection_le_ipv4 {
439 struct fw_ofld_connection_le_ipv6 {
447 struct fw_ofld_connection_tcb {
448 __be32 t_state_to_astid;
449 __be16 cplrxdataack_cplpassacceptrpl;
461 #define S_FW_OFLD_CONNECTION_WR_VERSION 31
462 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1
463 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \
464 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
465 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \
466 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
467 M_FW_OFLD_CONNECTION_WR_VERSION)
468 #define F_FW_OFLD_CONNECTION_WR_VERSION \
469 V_FW_OFLD_CONNECTION_WR_VERSION(1U)
471 #define S_FW_OFLD_CONNECTION_WR_CPL 30
472 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1
473 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL)
474 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \
475 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
476 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U)
478 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28
479 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf
480 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \
481 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
482 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \
483 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
484 M_FW_OFLD_CONNECTION_WR_T_STATE)
486 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24
487 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf
488 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \
489 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
490 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \
491 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
492 M_FW_OFLD_CONNECTION_WR_RCV_SCALE)
494 #define S_FW_OFLD_CONNECTION_WR_ASTID 0
495 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff
496 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \
497 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
498 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \
499 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)
501 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15
502 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1
503 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \
504 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
505 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \
506 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
507 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
508 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \
509 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)
511 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14
512 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1
513 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \
514 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
515 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \
516 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
517 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
518 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \
519 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)
522 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */
526 FW_FLOWC_MNEM_SNDNXT,
527 FW_FLOWC_MNEM_RCVNXT,
528 FW_FLOWC_MNEM_SNDBUF,
532 struct fw_flowc_mnemval {
539 __be32 op_to_nparams;
540 #define FW_FLOWC_WR_NPARAMS(x) ((x) << 0)
542 struct fw_flowc_mnemval mnemval[0];
545 struct fw_ofld_tx_data_wr {
546 __be32 op_to_immdlen;
549 __be32 tunnel_to_proxy;
550 #define FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << 19)
551 #define FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << 18)
552 #define FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << 17)
553 #define FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << 16)
554 #define FW_OFLD_TX_DATA_WR_MORE(x) ((x) << 15)
555 #define FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << 14)
556 #define FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << 10)
557 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) ((x) << 6)
562 #define FW_CMD_WR_DMA (1U << 17)
567 struct fw_eth_tx_pkt_vm_wr {
569 __be32 equiq_to_len16;
577 #define FW_CMD_MAX_TIMEOUT 10000
580 * If a host driver does a HELLO and discovers that there's already a MASTER
581 * selected, we may have to wait for that MASTER to finish issuing RESET,
582 * configuration and INITIALIZE commands. Also, there's a possibility that
583 * our own HELLO may get lost if it happens right as the MASTER is issuign a
584 * RESET command, so we need to be willing to make a few retries of our HELLO.
586 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
587 #define FW_CMD_HELLO_RETRIES 3
590 enum fw_cmd_opcodes {
595 FW_INITIALIZE_CMD = 0x06,
596 FW_CAPS_CONFIG_CMD = 0x07,
597 FW_PARAMS_CMD = 0x08,
600 FW_EQ_MNGT_CMD = 0x11,
601 FW_EQ_ETH_CMD = 0x12,
602 FW_EQ_CTRL_CMD = 0x13,
603 FW_EQ_OFLD_CMD = 0x21,
605 FW_VI_MAC_CMD = 0x15,
606 FW_VI_RXMODE_CMD = 0x16,
607 FW_VI_ENABLE_CMD = 0x17,
608 FW_ACL_MAC_CMD = 0x18,
609 FW_ACL_VLAN_CMD = 0x19,
610 FW_VI_STATS_CMD = 0x1a,
612 FW_PORT_STATS_CMD = 0x1c,
613 FW_PORT_LB_STATS_CMD = 0x1d,
614 FW_PORT_TRACE_CMD = 0x1e,
615 FW_PORT_TRACE_MMAP_CMD = 0x1f,
616 FW_RSS_IND_TBL_CMD = 0x20,
617 FW_RSS_GLB_CONFIG_CMD = 0x22,
618 FW_RSS_VI_CONFIG_CMD = 0x23,
619 FW_LASTC2E_CMD = 0x40,
625 FW_CMD_CAP_PF = 0x01,
626 FW_CMD_CAP_DMAQ = 0x02,
627 FW_CMD_CAP_PORT = 0x04,
628 FW_CMD_CAP_PORTPROMISC = 0x08,
629 FW_CMD_CAP_PORTSTATS = 0x10,
630 FW_CMD_CAP_VF = 0x80,
634 * Generic command header flit0
641 #define FW_CMD_OP(x) ((x) << 24)
642 #define FW_CMD_OP_GET(x) (((x) >> 24) & 0xff)
643 #define FW_CMD_REQUEST (1U << 23)
644 #define FW_CMD_REQUEST_GET(x) (((x) >> 23) & 0x1)
645 #define FW_CMD_READ (1U << 22)
646 #define FW_CMD_WRITE (1U << 21)
647 #define FW_CMD_EXEC (1U << 20)
648 #define FW_CMD_RAMASK(x) ((x) << 20)
649 #define FW_CMD_RETVAL(x) ((x) << 8)
650 #define FW_CMD_RETVAL_GET(x) (((x) >> 8) & 0xff)
651 #define FW_CMD_LEN16(x) ((x) << 0)
652 #define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
654 enum fw_ldst_addrspc {
655 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
656 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
657 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
658 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
659 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
660 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
661 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
662 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
663 FW_LDST_ADDRSPC_MDIO = 0x0018,
664 FW_LDST_ADDRSPC_MPS = 0x0020,
665 FW_LDST_ADDRSPC_FUNC = 0x0028,
666 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
669 enum fw_ldst_mps_fid {
674 enum fw_ldst_func_access_ctl {
675 FW_LDST_FUNC_ACC_CTL_VIID,
676 FW_LDST_FUNC_ACC_CTL_FID
679 enum fw_ldst_func_mod_index {
684 __be32 op_to_addrspace;
685 #define FW_LDST_CMD_ADDRSPACE(x) ((x) << 0)
686 __be32 cycles_to_len16;
688 struct fw_ldst_addrval {
692 struct fw_ldst_idctxt {
704 struct fw_ldst_mdio {
720 struct fw_ldst_func {
728 struct fw_ldst_pcie {
741 #define FW_LDST_CMD_MSG(x) ((x) << 31)
742 #define FW_LDST_CMD_PADDR(x) ((x) << 8)
743 #define FW_LDST_CMD_MMD(x) ((x) << 0)
744 #define FW_LDST_CMD_FID(x) ((x) << 15)
745 #define FW_LDST_CMD_CTL(x) ((x) << 0)
746 #define FW_LDST_CMD_RPLCPF(x) ((x) << 0)
747 #define FW_LDST_CMD_LC (1U << 4)
748 #define FW_LDST_CMD_NACCESS(x) ((x) << 0)
749 #define FW_LDST_CMD_FN(x) ((x) << 0)
751 struct fw_reset_cmd {
758 #define FW_RESET_CMD_HALT_SHIFT 31
759 #define FW_RESET_CMD_HALT_MASK 0x1
760 #define FW_RESET_CMD_HALT(x) ((x) << FW_RESET_CMD_HALT_SHIFT)
761 #define FW_RESET_CMD_HALT_GET(x) \
762 (((x) >> FW_RESET_CMD_HALT_SHIFT) & FW_RESET_CMD_HALT_MASK)
765 fw_hello_cmd_stage_os = 0x0
768 struct fw_hello_cmd {
771 __be32 err_to_clearinit;
772 #define FW_HELLO_CMD_ERR (1U << 31)
773 #define FW_HELLO_CMD_INIT (1U << 30)
774 #define FW_HELLO_CMD_MASTERDIS(x) ((x) << 29)
775 #define FW_HELLO_CMD_MASTERFORCE(x) ((x) << 28)
776 #define FW_HELLO_CMD_MBMASTER_MASK 0xfU
777 #define FW_HELLO_CMD_MBMASTER_SHIFT 24
778 #define FW_HELLO_CMD_MBMASTER(x) ((x) << FW_HELLO_CMD_MBMASTER_SHIFT)
779 #define FW_HELLO_CMD_MBMASTER_GET(x) \
780 (((x) >> FW_HELLO_CMD_MBMASTER_SHIFT) & FW_HELLO_CMD_MBMASTER_MASK)
781 #define FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << 23)
782 #define FW_HELLO_CMD_MBASYNCNOT(x) ((x) << 20)
783 #define FW_HELLO_CMD_STAGE(x) ((x) << 17)
784 #define FW_HELLO_CMD_CLEARINIT (1U << 16)
794 struct fw_initialize_cmd {
800 enum fw_caps_config_hm {
801 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
802 FW_CAPS_CONFIG_HM_PL = 0x00000002,
803 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
804 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
805 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
806 FW_CAPS_CONFIG_HM_TP = 0x00000020,
807 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
808 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
809 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
810 FW_CAPS_CONFIG_HM_MC = 0x00000200,
811 FW_CAPS_CONFIG_HM_LE = 0x00000400,
812 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
813 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
814 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
815 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
816 FW_CAPS_CONFIG_HM_MI = 0x00008000,
817 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
818 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
819 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
820 FW_CAPS_CONFIG_HM_MA = 0x00080000,
821 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
822 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
823 FW_CAPS_CONFIG_HM_UART = 0x00400000,
824 FW_CAPS_CONFIG_HM_SF = 0x00800000,
827 enum fw_caps_config_nbm {
828 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
829 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
832 enum fw_caps_config_link {
833 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
834 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
835 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
838 enum fw_caps_config_switch {
839 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
840 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
843 enum fw_caps_config_nic {
844 FW_CAPS_CONFIG_NIC = 0x00000001,
845 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
848 enum fw_caps_config_ofld {
849 FW_CAPS_CONFIG_OFLD = 0x00000001,
852 enum fw_caps_config_rdma {
853 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
854 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
857 enum fw_caps_config_iscsi {
858 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
859 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
860 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
861 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
864 enum fw_caps_config_fcoe {
865 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
866 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
867 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004,
871 FW_MEMTYPE_CF_EDC0 = 0x0,
872 FW_MEMTYPE_CF_EDC1 = 0x1,
873 FW_MEMTYPE_CF_EXTMEM = 0x2,
874 FW_MEMTYPE_CF_FLASH = 0x4,
875 FW_MEMTYPE_CF_INTERNAL = 0x5,
878 struct fw_caps_config_cmd {
880 __be32 cfvalid_to_len16;
898 #define FW_CAPS_CONFIG_CMD_CFVALID (1U << 27)
899 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) ((x) << 24)
900 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) ((x) << 16)
903 * params command mnemonics
905 enum fw_params_mnem {
906 FW_PARAMS_MNEM_DEV = 1, /* device params */
907 FW_PARAMS_MNEM_PFVF = 2, /* function params */
908 FW_PARAMS_MNEM_REG = 3, /* limited register access */
909 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
916 enum fw_params_param_dev {
917 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
918 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
919 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
920 * allocated by the device's
923 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
924 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04,
925 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
926 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
927 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07,
928 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
929 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
930 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
931 FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
932 FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
933 FW_PARAMS_PARAM_DEV_CF = 0x0D,
937 * physical and virtual function parameters
939 enum fw_params_param_pfvf {
940 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
941 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
942 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
943 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
944 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
945 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
946 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
947 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
948 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
949 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
950 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
951 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
952 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
953 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
954 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
955 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
956 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
957 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
958 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
959 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
960 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
961 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
962 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
963 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
964 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
965 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
966 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
967 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
968 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26,
969 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27,
970 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28,
971 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
972 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
973 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B,
974 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C,
975 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
976 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
977 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
978 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
982 * dma queue parameters
984 enum fw_params_param_dmaq {
985 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
986 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
987 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
988 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
989 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
992 #define FW_PARAMS_MNEM(x) ((x) << 24)
993 #define FW_PARAMS_PARAM_X(x) ((x) << 16)
994 #define FW_PARAMS_PARAM_Y_SHIFT 8
995 #define FW_PARAMS_PARAM_Y_MASK 0xffU
996 #define FW_PARAMS_PARAM_Y(x) ((x) << FW_PARAMS_PARAM_Y_SHIFT)
997 #define FW_PARAMS_PARAM_Y_GET(x) (((x) >> FW_PARAMS_PARAM_Y_SHIFT) &\
998 FW_PARAMS_PARAM_Y_MASK)
999 #define FW_PARAMS_PARAM_Z_SHIFT 0
1000 #define FW_PARAMS_PARAM_Z_MASK 0xffu
1001 #define FW_PARAMS_PARAM_Z(x) ((x) << FW_PARAMS_PARAM_Z_SHIFT)
1002 #define FW_PARAMS_PARAM_Z_GET(x) (((x) >> FW_PARAMS_PARAM_Z_SHIFT) &\
1003 FW_PARAMS_PARAM_Z_MASK)
1004 #define FW_PARAMS_PARAM_XYZ(x) ((x) << 0)
1005 #define FW_PARAMS_PARAM_YZ(x) ((x) << 0)
1007 struct fw_params_cmd {
1009 __be32 retval_len16;
1010 struct fw_params_param {
1016 #define FW_PARAMS_CMD_PFN(x) ((x) << 8)
1017 #define FW_PARAMS_CMD_VFN(x) ((x) << 0)
1019 struct fw_pfvf_cmd {
1021 __be32 retval_len16;
1022 __be32 niqflint_niq;
1024 __be32 tc_to_nexactf;
1025 __be32 r_caps_to_nethctrl;
1031 #define FW_PFVF_CMD_PFN(x) ((x) << 8)
1032 #define FW_PFVF_CMD_VFN(x) ((x) << 0)
1034 #define FW_PFVF_CMD_NIQFLINT(x) ((x) << 20)
1035 #define FW_PFVF_CMD_NIQFLINT_GET(x) (((x) >> 20) & 0xfff)
1037 #define FW_PFVF_CMD_NIQ(x) ((x) << 0)
1038 #define FW_PFVF_CMD_NIQ_GET(x) (((x) >> 0) & 0xfffff)
1040 #define FW_PFVF_CMD_TYPE (1 << 31)
1041 #define FW_PFVF_CMD_TYPE_GET(x) (((x) >> 31) & 0x1)
1043 #define FW_PFVF_CMD_CMASK(x) ((x) << 24)
1044 #define FW_PFVF_CMD_CMASK_MASK 0xf
1045 #define FW_PFVF_CMD_CMASK_GET(x) (((x) >> 24) & FW_PFVF_CMD_CMASK_MASK)
1047 #define FW_PFVF_CMD_PMASK(x) ((x) << 20)
1048 #define FW_PFVF_CMD_PMASK_MASK 0xf
1049 #define FW_PFVF_CMD_PMASK_GET(x) (((x) >> 20) & FW_PFVF_CMD_PMASK_MASK)
1051 #define FW_PFVF_CMD_NEQ(x) ((x) << 0)
1052 #define FW_PFVF_CMD_NEQ_GET(x) (((x) >> 0) & 0xfffff)
1054 #define FW_PFVF_CMD_TC(x) ((x) << 24)
1055 #define FW_PFVF_CMD_TC_GET(x) (((x) >> 24) & 0xff)
1057 #define FW_PFVF_CMD_NVI(x) ((x) << 16)
1058 #define FW_PFVF_CMD_NVI_GET(x) (((x) >> 16) & 0xff)
1060 #define FW_PFVF_CMD_NEXACTF(x) ((x) << 0)
1061 #define FW_PFVF_CMD_NEXACTF_GET(x) (((x) >> 0) & 0xffff)
1063 #define FW_PFVF_CMD_R_CAPS(x) ((x) << 24)
1064 #define FW_PFVF_CMD_R_CAPS_GET(x) (((x) >> 24) & 0xff)
1066 #define FW_PFVF_CMD_WX_CAPS(x) ((x) << 16)
1067 #define FW_PFVF_CMD_WX_CAPS_GET(x) (((x) >> 16) & 0xff)
1069 #define FW_PFVF_CMD_NETHCTRL(x) ((x) << 0)
1070 #define FW_PFVF_CMD_NETHCTRL_GET(x) (((x) >> 0) & 0xffff)
1073 FW_IQ_TYPE_FL_INT_CAP,
1074 FW_IQ_TYPE_NO_FL_INT_CAP
1079 __be32 alloc_to_len16;
1084 __be32 type_to_iqandstindex;
1085 __be16 iqdroprss_to_iqesize;
1088 __be32 iqns_to_fl0congen;
1089 __be16 fl0dcaen_to_fl0cidxfthresh;
1092 __be32 fl1cngchmap_to_fl1congen;
1093 __be16 fl1dcaen_to_fl1cidxfthresh;
1098 #define FW_IQ_CMD_PFN(x) ((x) << 8)
1099 #define FW_IQ_CMD_VFN(x) ((x) << 0)
1101 #define FW_IQ_CMD_ALLOC (1U << 31)
1102 #define FW_IQ_CMD_FREE (1U << 30)
1103 #define FW_IQ_CMD_MODIFY (1U << 29)
1104 #define FW_IQ_CMD_IQSTART(x) ((x) << 28)
1105 #define FW_IQ_CMD_IQSTOP(x) ((x) << 27)
1107 #define FW_IQ_CMD_TYPE(x) ((x) << 29)
1108 #define FW_IQ_CMD_IQASYNCH(x) ((x) << 28)
1109 #define FW_IQ_CMD_VIID(x) ((x) << 16)
1110 #define FW_IQ_CMD_IQANDST(x) ((x) << 15)
1111 #define FW_IQ_CMD_IQANUS(x) ((x) << 14)
1112 #define FW_IQ_CMD_IQANUD(x) ((x) << 12)
1113 #define FW_IQ_CMD_IQANDSTINDEX(x) ((x) << 0)
1115 #define FW_IQ_CMD_IQDROPRSS (1U << 15)
1116 #define FW_IQ_CMD_IQGTSMODE (1U << 14)
1117 #define FW_IQ_CMD_IQPCIECH(x) ((x) << 12)
1118 #define FW_IQ_CMD_IQDCAEN(x) ((x) << 11)
1119 #define FW_IQ_CMD_IQDCACPU(x) ((x) << 6)
1120 #define FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << 4)
1121 #define FW_IQ_CMD_IQO (1U << 3)
1122 #define FW_IQ_CMD_IQCPRIO(x) ((x) << 2)
1123 #define FW_IQ_CMD_IQESIZE(x) ((x) << 0)
1125 #define FW_IQ_CMD_IQNS(x) ((x) << 31)
1126 #define FW_IQ_CMD_IQRO(x) ((x) << 30)
1127 #define FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << 28)
1128 #define FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << 27)
1129 #define FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << 26)
1130 #define FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << 20)
1131 #define FW_IQ_CMD_FL0CACHELOCK(x) ((x) << 15)
1132 #define FW_IQ_CMD_FL0DBP(x) ((x) << 14)
1133 #define FW_IQ_CMD_FL0DATANS(x) ((x) << 13)
1134 #define FW_IQ_CMD_FL0DATARO(x) ((x) << 12)
1135 #define FW_IQ_CMD_FL0CONGCIF(x) ((x) << 11)
1136 #define FW_IQ_CMD_FL0ONCHIP(x) ((x) << 10)
1137 #define FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << 9)
1138 #define FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << 8)
1139 #define FW_IQ_CMD_FL0FETCHNS(x) ((x) << 7)
1140 #define FW_IQ_CMD_FL0FETCHRO(x) ((x) << 6)
1141 #define FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << 4)
1142 #define FW_IQ_CMD_FL0CPRIO(x) ((x) << 3)
1143 #define FW_IQ_CMD_FL0PADEN(x) ((x) << 2)
1144 #define FW_IQ_CMD_FL0PACKEN(x) ((x) << 1)
1145 #define FW_IQ_CMD_FL0CONGEN (1U << 0)
1147 #define FW_IQ_CMD_FL0DCAEN(x) ((x) << 15)
1148 #define FW_IQ_CMD_FL0DCACPU(x) ((x) << 10)
1149 #define FW_IQ_CMD_FL0FBMIN(x) ((x) << 7)
1150 #define FW_IQ_CMD_FL0FBMAX(x) ((x) << 4)
1151 #define FW_IQ_CMD_FL0CIDXFTHRESHO (1U << 3)
1152 #define FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << 0)
1154 #define FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << 20)
1155 #define FW_IQ_CMD_FL1CACHELOCK(x) ((x) << 15)
1156 #define FW_IQ_CMD_FL1DBP(x) ((x) << 14)
1157 #define FW_IQ_CMD_FL1DATANS(x) ((x) << 13)
1158 #define FW_IQ_CMD_FL1DATARO(x) ((x) << 12)
1159 #define FW_IQ_CMD_FL1CONGCIF(x) ((x) << 11)
1160 #define FW_IQ_CMD_FL1ONCHIP(x) ((x) << 10)
1161 #define FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << 9)
1162 #define FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << 8)
1163 #define FW_IQ_CMD_FL1FETCHNS(x) ((x) << 7)
1164 #define FW_IQ_CMD_FL1FETCHRO(x) ((x) << 6)
1165 #define FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << 4)
1166 #define FW_IQ_CMD_FL1CPRIO(x) ((x) << 3)
1167 #define FW_IQ_CMD_FL1PADEN (1U << 2)
1168 #define FW_IQ_CMD_FL1PACKEN (1U << 1)
1169 #define FW_IQ_CMD_FL1CONGEN (1U << 0)
1171 #define FW_IQ_CMD_FL1DCAEN(x) ((x) << 15)
1172 #define FW_IQ_CMD_FL1DCACPU(x) ((x) << 10)
1173 #define FW_IQ_CMD_FL1FBMIN(x) ((x) << 7)
1174 #define FW_IQ_CMD_FL1FBMAX(x) ((x) << 4)
1175 #define FW_IQ_CMD_FL1CIDXFTHRESHO (1U << 3)
1176 #define FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << 0)
1178 struct fw_eq_eth_cmd {
1180 __be32 alloc_to_len16;
1182 __be32 physeqid_pkd;
1183 __be32 fetchszm_to_iqid;
1184 __be32 dcaen_to_eqsize;
1191 #define FW_EQ_ETH_CMD_PFN(x) ((x) << 8)
1192 #define FW_EQ_ETH_CMD_VFN(x) ((x) << 0)
1193 #define FW_EQ_ETH_CMD_ALLOC (1U << 31)
1194 #define FW_EQ_ETH_CMD_FREE (1U << 30)
1195 #define FW_EQ_ETH_CMD_MODIFY (1U << 29)
1196 #define FW_EQ_ETH_CMD_EQSTART (1U << 28)
1197 #define FW_EQ_ETH_CMD_EQSTOP (1U << 27)
1199 #define FW_EQ_ETH_CMD_EQID(x) ((x) << 0)
1200 #define FW_EQ_ETH_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
1201 #define FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << 0)
1202 #define FW_EQ_ETH_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
1204 #define FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << 26)
1205 #define FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << 25)
1206 #define FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << 24)
1207 #define FW_EQ_ETH_CMD_FETCHNS(x) ((x) << 23)
1208 #define FW_EQ_ETH_CMD_FETCHRO(x) ((x) << 22)
1209 #define FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << 20)
1210 #define FW_EQ_ETH_CMD_CPRIO(x) ((x) << 19)
1211 #define FW_EQ_ETH_CMD_ONCHIP(x) ((x) << 18)
1212 #define FW_EQ_ETH_CMD_PCIECHN(x) ((x) << 16)
1213 #define FW_EQ_ETH_CMD_IQID(x) ((x) << 0)
1215 #define FW_EQ_ETH_CMD_DCAEN(x) ((x) << 31)
1216 #define FW_EQ_ETH_CMD_DCACPU(x) ((x) << 26)
1217 #define FW_EQ_ETH_CMD_FBMIN(x) ((x) << 23)
1218 #define FW_EQ_ETH_CMD_FBMAX(x) ((x) << 20)
1219 #define FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << 19)
1220 #define FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << 16)
1221 #define FW_EQ_ETH_CMD_EQSIZE(x) ((x) << 0)
1223 #define FW_EQ_ETH_CMD_VIID(x) ((x) << 16)
1225 struct fw_eq_ctrl_cmd {
1227 __be32 alloc_to_len16;
1228 __be32 cmpliqid_eqid;
1229 __be32 physeqid_pkd;
1230 __be32 fetchszm_to_iqid;
1231 __be32 dcaen_to_eqsize;
1235 #define FW_EQ_CTRL_CMD_PFN(x) ((x) << 8)
1236 #define FW_EQ_CTRL_CMD_VFN(x) ((x) << 0)
1238 #define FW_EQ_CTRL_CMD_ALLOC (1U << 31)
1239 #define FW_EQ_CTRL_CMD_FREE (1U << 30)
1240 #define FW_EQ_CTRL_CMD_MODIFY (1U << 29)
1241 #define FW_EQ_CTRL_CMD_EQSTART (1U << 28)
1242 #define FW_EQ_CTRL_CMD_EQSTOP (1U << 27)
1244 #define FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << 20)
1245 #define FW_EQ_CTRL_CMD_EQID(x) ((x) << 0)
1246 #define FW_EQ_CTRL_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
1247 #define FW_EQ_CTRL_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
1249 #define FW_EQ_CTRL_CMD_FETCHSZM (1U << 26)
1250 #define FW_EQ_CTRL_CMD_STATUSPGNS (1U << 25)
1251 #define FW_EQ_CTRL_CMD_STATUSPGRO (1U << 24)
1252 #define FW_EQ_CTRL_CMD_FETCHNS (1U << 23)
1253 #define FW_EQ_CTRL_CMD_FETCHRO (1U << 22)
1254 #define FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << 20)
1255 #define FW_EQ_CTRL_CMD_CPRIO(x) ((x) << 19)
1256 #define FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << 18)
1257 #define FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << 16)
1258 #define FW_EQ_CTRL_CMD_IQID(x) ((x) << 0)
1260 #define FW_EQ_CTRL_CMD_DCAEN(x) ((x) << 31)
1261 #define FW_EQ_CTRL_CMD_DCACPU(x) ((x) << 26)
1262 #define FW_EQ_CTRL_CMD_FBMIN(x) ((x) << 23)
1263 #define FW_EQ_CTRL_CMD_FBMAX(x) ((x) << 20)
1264 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) ((x) << 19)
1265 #define FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << 16)
1266 #define FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << 0)
1268 struct fw_eq_ofld_cmd {
1270 __be32 alloc_to_len16;
1272 __be32 physeqid_pkd;
1273 __be32 fetchszm_to_iqid;
1274 __be32 dcaen_to_eqsize;
1278 #define FW_EQ_OFLD_CMD_PFN(x) ((x) << 8)
1279 #define FW_EQ_OFLD_CMD_VFN(x) ((x) << 0)
1281 #define FW_EQ_OFLD_CMD_ALLOC (1U << 31)
1282 #define FW_EQ_OFLD_CMD_FREE (1U << 30)
1283 #define FW_EQ_OFLD_CMD_MODIFY (1U << 29)
1284 #define FW_EQ_OFLD_CMD_EQSTART (1U << 28)
1285 #define FW_EQ_OFLD_CMD_EQSTOP (1U << 27)
1287 #define FW_EQ_OFLD_CMD_EQID(x) ((x) << 0)
1288 #define FW_EQ_OFLD_CMD_EQID_GET(x) (((x) >> 0) & 0xfffff)
1289 #define FW_EQ_OFLD_CMD_PHYSEQID_GET(x) (((x) >> 0) & 0xfffff)
1291 #define FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << 26)
1292 #define FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << 25)
1293 #define FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << 24)
1294 #define FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << 23)
1295 #define FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << 22)
1296 #define FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << 20)
1297 #define FW_EQ_OFLD_CMD_CPRIO(x) ((x) << 19)
1298 #define FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << 18)
1299 #define FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << 16)
1300 #define FW_EQ_OFLD_CMD_IQID(x) ((x) << 0)
1302 #define FW_EQ_OFLD_CMD_DCAEN(x) ((x) << 31)
1303 #define FW_EQ_OFLD_CMD_DCACPU(x) ((x) << 26)
1304 #define FW_EQ_OFLD_CMD_FBMIN(x) ((x) << 23)
1305 #define FW_EQ_OFLD_CMD_FBMAX(x) ((x) << 20)
1306 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) ((x) << 19)
1307 #define FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << 16)
1308 #define FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << 0)
1311 * Macros for VIID parsing:
1312 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1314 #define FW_VIID_PFN_GET(x) (((x) >> 8) & 0x7)
1315 #define FW_VIID_VIVLD_GET(x) (((x) >> 7) & 0x1)
1316 #define FW_VIID_VIN_GET(x) (((x) >> 0) & 0x7F)
1320 __be32 alloc_to_len16;
1336 #define FW_VI_CMD_PFN(x) ((x) << 8)
1337 #define FW_VI_CMD_VFN(x) ((x) << 0)
1338 #define FW_VI_CMD_ALLOC (1U << 31)
1339 #define FW_VI_CMD_FREE (1U << 30)
1340 #define FW_VI_CMD_VIID(x) ((x) << 0)
1341 #define FW_VI_CMD_VIID_GET(x) ((x) & 0xfff)
1342 #define FW_VI_CMD_PORTID(x) ((x) << 4)
1343 #define FW_VI_CMD_PORTID_GET(x) (((x) >> 4) & 0xf)
1344 #define FW_VI_CMD_RSSSIZE_GET(x) (((x) >> 0) & 0x7ff)
1346 /* Special VI_MAC command index ids */
1347 #define FW_VI_MAC_ADD_MAC 0x3FF
1348 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1349 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD
1350 #define FW_CLS_TCAM_NUM_ENTRIES 336
1352 enum fw_vi_mac_smac {
1353 FW_VI_MAC_MPS_TCAM_ENTRY,
1354 FW_VI_MAC_MPS_TCAM_ONLY,
1356 FW_VI_MAC_SMT_AND_MPSTCAM
1359 enum fw_vi_mac_result {
1360 FW_VI_MAC_R_SUCCESS,
1361 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
1362 FW_VI_MAC_R_SMAC_FAIL,
1363 FW_VI_MAC_R_F_ACL_CHECK
1366 struct fw_vi_mac_cmd {
1368 __be32 freemacs_to_len16;
1370 struct fw_vi_mac_exact {
1371 __be16 valid_to_idx;
1374 struct fw_vi_mac_hash {
1380 #define FW_VI_MAC_CMD_VIID(x) ((x) << 0)
1381 #define FW_VI_MAC_CMD_FREEMACS(x) ((x) << 31)
1382 #define FW_VI_MAC_CMD_HASHVECEN (1U << 23)
1383 #define FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << 22)
1384 #define FW_VI_MAC_CMD_VALID (1U << 15)
1385 #define FW_VI_MAC_CMD_PRIO(x) ((x) << 12)
1386 #define FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << 10)
1387 #define FW_VI_MAC_CMD_SMAC_RESULT_GET(x) (((x) >> 10) & 0x3)
1388 #define FW_VI_MAC_CMD_IDX(x) ((x) << 0)
1389 #define FW_VI_MAC_CMD_IDX_GET(x) (((x) >> 0) & 0x3ff)
1391 #define FW_RXMODE_MTU_NO_CHG 65535
1393 struct fw_vi_rxmode_cmd {
1395 __be32 retval_len16;
1396 __be32 mtu_to_vlanexen;
1400 #define FW_VI_RXMODE_CMD_VIID(x) ((x) << 0)
1401 #define FW_VI_RXMODE_CMD_MTU_MASK 0xffff
1402 #define FW_VI_RXMODE_CMD_MTU(x) ((x) << 16)
1403 #define FW_VI_RXMODE_CMD_PROMISCEN_MASK 0x3
1404 #define FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << 14)
1405 #define FW_VI_RXMODE_CMD_ALLMULTIEN_MASK 0x3
1406 #define FW_VI_RXMODE_CMD_ALLMULTIEN(x) ((x) << 12)
1407 #define FW_VI_RXMODE_CMD_BROADCASTEN_MASK 0x3
1408 #define FW_VI_RXMODE_CMD_BROADCASTEN(x) ((x) << 10)
1409 #define FW_VI_RXMODE_CMD_VLANEXEN_MASK 0x3
1410 #define FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << 8)
1412 struct fw_vi_enable_cmd {
1414 __be32 ien_to_len16;
1420 #define FW_VI_ENABLE_CMD_VIID(x) ((x) << 0)
1421 #define FW_VI_ENABLE_CMD_IEN(x) ((x) << 31)
1422 #define FW_VI_ENABLE_CMD_EEN(x) ((x) << 30)
1423 #define FW_VI_ENABLE_CMD_LED (1U << 29)
1425 /* VI VF stats offset definitions */
1426 #define VI_VF_NUM_STATS 16
1427 enum fw_vi_stats_vf_index {
1428 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
1429 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
1430 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
1431 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
1432 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
1433 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
1434 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
1435 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
1436 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
1437 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
1438 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
1439 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
1440 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
1441 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
1442 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
1443 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
1446 /* VI PF stats offset definitions */
1447 #define VI_PF_NUM_STATS 17
1448 enum fw_vi_stats_pf_index {
1449 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
1450 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
1451 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
1452 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
1453 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
1454 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
1455 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
1456 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
1457 FW_VI_PF_STAT_RX_BYTES_IX,
1458 FW_VI_PF_STAT_RX_FRAMES_IX,
1459 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
1460 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
1461 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
1462 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
1463 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
1464 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
1465 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
1468 struct fw_vi_stats_cmd {
1470 __be32 retval_len16;
1472 struct fw_vi_stats_ctl {
1483 struct fw_vi_stats_pf {
1484 __be64 tx_bcast_bytes;
1485 __be64 tx_bcast_frames;
1486 __be64 tx_mcast_bytes;
1487 __be64 tx_mcast_frames;
1488 __be64 tx_ucast_bytes;
1489 __be64 tx_ucast_frames;
1490 __be64 tx_offload_bytes;
1491 __be64 tx_offload_frames;
1493 __be64 rx_pf_frames;
1494 __be64 rx_bcast_bytes;
1495 __be64 rx_bcast_frames;
1496 __be64 rx_mcast_bytes;
1497 __be64 rx_mcast_frames;
1498 __be64 rx_ucast_bytes;
1499 __be64 rx_ucast_frames;
1500 __be64 rx_err_frames;
1502 struct fw_vi_stats_vf {
1503 __be64 tx_bcast_bytes;
1504 __be64 tx_bcast_frames;
1505 __be64 tx_mcast_bytes;
1506 __be64 tx_mcast_frames;
1507 __be64 tx_ucast_bytes;
1508 __be64 tx_ucast_frames;
1509 __be64 tx_drop_frames;
1510 __be64 tx_offload_bytes;
1511 __be64 tx_offload_frames;
1512 __be64 rx_bcast_bytes;
1513 __be64 rx_bcast_frames;
1514 __be64 rx_mcast_bytes;
1515 __be64 rx_mcast_frames;
1516 __be64 rx_ucast_bytes;
1517 __be64 rx_ucast_frames;
1518 __be64 rx_err_frames;
1523 #define FW_VI_STATS_CMD_VIID(x) ((x) << 0)
1524 #define FW_VI_STATS_CMD_NSTATS(x) ((x) << 12)
1525 #define FW_VI_STATS_CMD_IX(x) ((x) << 0)
1527 struct fw_acl_mac_cmd {
1542 #define FW_ACL_MAC_CMD_PFN(x) ((x) << 8)
1543 #define FW_ACL_MAC_CMD_VFN(x) ((x) << 0)
1544 #define FW_ACL_MAC_CMD_EN(x) ((x) << 31)
1546 struct fw_acl_vlan_cmd {
1555 #define FW_ACL_VLAN_CMD_PFN(x) ((x) << 8)
1556 #define FW_ACL_VLAN_CMD_VFN(x) ((x) << 0)
1557 #define FW_ACL_VLAN_CMD_EN(x) ((x) << 31)
1558 #define FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << 7)
1559 #define FW_ACL_VLAN_CMD_FM(x) ((x) << 6)
1562 FW_PORT_CAP_SPEED_100M = 0x0001,
1563 FW_PORT_CAP_SPEED_1G = 0x0002,
1564 FW_PORT_CAP_SPEED_2_5G = 0x0004,
1565 FW_PORT_CAP_SPEED_10G = 0x0008,
1566 FW_PORT_CAP_SPEED_40G = 0x0010,
1567 FW_PORT_CAP_SPEED_100G = 0x0020,
1568 FW_PORT_CAP_FC_RX = 0x0040,
1569 FW_PORT_CAP_FC_TX = 0x0080,
1570 FW_PORT_CAP_ANEG = 0x0100,
1571 FW_PORT_CAP_MDI_0 = 0x0200,
1572 FW_PORT_CAP_MDI_1 = 0x0400,
1573 FW_PORT_CAP_BEAN = 0x0800,
1574 FW_PORT_CAP_PMA_LPBK = 0x1000,
1575 FW_PORT_CAP_PCS_LPBK = 0x2000,
1576 FW_PORT_CAP_PHYXS_LPBK = 0x4000,
1577 FW_PORT_CAP_FAR_END_LPBK = 0x8000,
1581 FW_PORT_MDI_UNCHANGED,
1583 FW_PORT_MDI_F_STRAIGHT,
1584 FW_PORT_MDI_F_CROSSOVER
1587 #define FW_PORT_MDI(x) ((x) << 9)
1589 enum fw_port_action {
1590 FW_PORT_ACTION_L1_CFG = 0x0001,
1591 FW_PORT_ACTION_L2_CFG = 0x0002,
1592 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
1593 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
1594 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
1595 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
1596 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
1597 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
1598 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
1599 FW_PORT_ACTION_L1_LPBK = 0x0021,
1600 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022,
1601 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023,
1602 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
1603 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
1604 FW_PORT_ACTION_PHY_RESET = 0x0040,
1605 FW_PORT_ACTION_PMA_RESET = 0x0041,
1606 FW_PORT_ACTION_PCS_RESET = 0x0042,
1607 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
1608 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
1609 FW_PORT_ACTION_AN_RESET = 0x0045
1612 enum fw_port_l2cfg_ctlbf {
1613 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
1614 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
1615 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
1616 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
1617 FW_PORT_L2_CTLBF_IVLAN = 0x10,
1618 FW_PORT_L2_CTLBF_TXIPG = 0x20
1621 enum fw_port_dcb_cfg {
1622 FW_PORT_DCB_CFG_PG = 0x01,
1623 FW_PORT_DCB_CFG_PFC = 0x02,
1624 FW_PORT_DCB_CFG_APPL = 0x04
1627 enum fw_port_dcb_cfg_rc {
1628 FW_PORT_DCB_CFG_SUCCESS = 0x0,
1629 FW_PORT_DCB_CFG_ERROR = 0x1
1632 enum fw_port_dcb_type {
1633 FW_PORT_DCB_TYPE_PGID = 0x00,
1634 FW_PORT_DCB_TYPE_PGRATE = 0x01,
1635 FW_PORT_DCB_TYPE_PRIORATE = 0x02,
1636 FW_PORT_DCB_TYPE_PFC = 0x03,
1637 FW_PORT_DCB_TYPE_APP_ID = 0x04,
1640 struct fw_port_cmd {
1641 __be32 op_to_portid;
1642 __be32 action_to_len16;
1644 struct fw_port_l1cfg {
1648 struct fw_port_l2cfg {
1649 __be16 ctlbf_to_ivlan0;
1661 struct fw_port_info {
1662 __be32 lstatus_to_modtype;
1671 struct fw_port_ppp {
1672 __be32 pppen_to_ncsich;
1675 struct fw_port_dcb {
1682 __be32 pgid0_to_pgid7;
1689 #define FW_PORT_CMD_READ (1U << 22)
1691 #define FW_PORT_CMD_PORTID(x) ((x) << 0)
1692 #define FW_PORT_CMD_PORTID_GET(x) (((x) >> 0) & 0xf)
1694 #define FW_PORT_CMD_ACTION(x) ((x) << 16)
1695 #define FW_PORT_CMD_ACTION_GET(x) (((x) >> 16) & 0xffff)
1697 #define FW_PORT_CMD_CTLBF(x) ((x) << 10)
1698 #define FW_PORT_CMD_OVLAN3(x) ((x) << 7)
1699 #define FW_PORT_CMD_OVLAN2(x) ((x) << 6)
1700 #define FW_PORT_CMD_OVLAN1(x) ((x) << 5)
1701 #define FW_PORT_CMD_OVLAN0(x) ((x) << 4)
1702 #define FW_PORT_CMD_IVLAN0(x) ((x) << 3)
1704 #define FW_PORT_CMD_TXIPG(x) ((x) << 19)
1706 #define FW_PORT_CMD_LSTATUS (1U << 31)
1707 #define FW_PORT_CMD_LSTATUS_GET(x) (((x) >> 31) & 0x1)
1708 #define FW_PORT_CMD_LSPEED(x) ((x) << 24)
1709 #define FW_PORT_CMD_LSPEED_GET(x) (((x) >> 24) & 0x3f)
1710 #define FW_PORT_CMD_TXPAUSE (1U << 23)
1711 #define FW_PORT_CMD_RXPAUSE (1U << 22)
1712 #define FW_PORT_CMD_MDIOCAP (1U << 21)
1713 #define FW_PORT_CMD_MDIOADDR_GET(x) (((x) >> 16) & 0x1f)
1714 #define FW_PORT_CMD_LPTXPAUSE (1U << 15)
1715 #define FW_PORT_CMD_LPRXPAUSE (1U << 14)
1716 #define FW_PORT_CMD_PTYPE_MASK 0x1f
1717 #define FW_PORT_CMD_PTYPE_GET(x) (((x) >> 8) & FW_PORT_CMD_PTYPE_MASK)
1718 #define FW_PORT_CMD_MODTYPE_MASK 0x1f
1719 #define FW_PORT_CMD_MODTYPE_GET(x) (((x) >> 0) & FW_PORT_CMD_MODTYPE_MASK)
1721 #define FW_PORT_CMD_PPPEN(x) ((x) << 31)
1722 #define FW_PORT_CMD_TPSRC(x) ((x) << 28)
1723 #define FW_PORT_CMD_NCSISRC(x) ((x) << 24)
1725 #define FW_PORT_CMD_CH0(x) ((x) << 20)
1726 #define FW_PORT_CMD_CH1(x) ((x) << 16)
1727 #define FW_PORT_CMD_CH2(x) ((x) << 12)
1728 #define FW_PORT_CMD_CH3(x) ((x) << 8)
1729 #define FW_PORT_CMD_NCSICH(x) ((x) << 4)
1732 FW_PORT_TYPE_FIBER_XFI,
1733 FW_PORT_TYPE_FIBER_XAUI,
1734 FW_PORT_TYPE_BT_SGMII,
1735 FW_PORT_TYPE_BT_XFI,
1736 FW_PORT_TYPE_BT_XAUI,
1743 FW_PORT_TYPE_BP4_AP,
1745 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_MASK
1748 enum fw_port_module_type {
1749 FW_PORT_MOD_TYPE_NA,
1750 FW_PORT_MOD_TYPE_LR,
1751 FW_PORT_MOD_TYPE_SR,
1752 FW_PORT_MOD_TYPE_ER,
1753 FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
1754 FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
1755 FW_PORT_MOD_TYPE_LRM,
1756 FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_MASK - 3,
1757 FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_MASK - 2,
1758 FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_MASK - 1,
1760 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_MASK
1763 enum fw_port_mod_sub_type {
1764 FW_PORT_MOD_SUB_TYPE_NA,
1765 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
1766 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
1767 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
1768 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
1769 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
1770 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
1772 /* The following will never been in the VPD. They are TWINAX cable
1773 * lengths decoded from SFP+ module i2c PROMs. These should
1774 * almost certainly go somewhere else ...
1776 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
1777 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
1778 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
1779 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
1783 #define FW_NUM_PORT_STATS 50
1784 #define FW_NUM_PORT_TX_STATS 23
1785 #define FW_NUM_PORT_RX_STATS 27
1787 enum fw_port_stats_tx_index {
1788 FW_STAT_TX_PORT_BYTES_IX,
1789 FW_STAT_TX_PORT_FRAMES_IX,
1790 FW_STAT_TX_PORT_BCAST_IX,
1791 FW_STAT_TX_PORT_MCAST_IX,
1792 FW_STAT_TX_PORT_UCAST_IX,
1793 FW_STAT_TX_PORT_ERROR_IX,
1794 FW_STAT_TX_PORT_64B_IX,
1795 FW_STAT_TX_PORT_65B_127B_IX,
1796 FW_STAT_TX_PORT_128B_255B_IX,
1797 FW_STAT_TX_PORT_256B_511B_IX,
1798 FW_STAT_TX_PORT_512B_1023B_IX,
1799 FW_STAT_TX_PORT_1024B_1518B_IX,
1800 FW_STAT_TX_PORT_1519B_MAX_IX,
1801 FW_STAT_TX_PORT_DROP_IX,
1802 FW_STAT_TX_PORT_PAUSE_IX,
1803 FW_STAT_TX_PORT_PPP0_IX,
1804 FW_STAT_TX_PORT_PPP1_IX,
1805 FW_STAT_TX_PORT_PPP2_IX,
1806 FW_STAT_TX_PORT_PPP3_IX,
1807 FW_STAT_TX_PORT_PPP4_IX,
1808 FW_STAT_TX_PORT_PPP5_IX,
1809 FW_STAT_TX_PORT_PPP6_IX,
1810 FW_STAT_TX_PORT_PPP7_IX
1813 enum fw_port_stat_rx_index {
1814 FW_STAT_RX_PORT_BYTES_IX,
1815 FW_STAT_RX_PORT_FRAMES_IX,
1816 FW_STAT_RX_PORT_BCAST_IX,
1817 FW_STAT_RX_PORT_MCAST_IX,
1818 FW_STAT_RX_PORT_UCAST_IX,
1819 FW_STAT_RX_PORT_MTU_ERROR_IX,
1820 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
1821 FW_STAT_RX_PORT_CRC_ERROR_IX,
1822 FW_STAT_RX_PORT_LEN_ERROR_IX,
1823 FW_STAT_RX_PORT_SYM_ERROR_IX,
1824 FW_STAT_RX_PORT_64B_IX,
1825 FW_STAT_RX_PORT_65B_127B_IX,
1826 FW_STAT_RX_PORT_128B_255B_IX,
1827 FW_STAT_RX_PORT_256B_511B_IX,
1828 FW_STAT_RX_PORT_512B_1023B_IX,
1829 FW_STAT_RX_PORT_1024B_1518B_IX,
1830 FW_STAT_RX_PORT_1519B_MAX_IX,
1831 FW_STAT_RX_PORT_PAUSE_IX,
1832 FW_STAT_RX_PORT_PPP0_IX,
1833 FW_STAT_RX_PORT_PPP1_IX,
1834 FW_STAT_RX_PORT_PPP2_IX,
1835 FW_STAT_RX_PORT_PPP3_IX,
1836 FW_STAT_RX_PORT_PPP4_IX,
1837 FW_STAT_RX_PORT_PPP5_IX,
1838 FW_STAT_RX_PORT_PPP6_IX,
1839 FW_STAT_RX_PORT_PPP7_IX,
1840 FW_STAT_RX_PORT_LESS_64B_IX
1843 struct fw_port_stats_cmd {
1844 __be32 op_to_portid;
1845 __be32 retval_len16;
1846 union fw_port_stats {
1847 struct fw_port_stats_ctl {
1859 struct fw_port_stats_all {
1868 __be64 tx_128b_255b;
1869 __be64 tx_256b_511b;
1870 __be64 tx_512b_1023b;
1871 __be64 tx_1024b_1518b;
1872 __be64 tx_1519b_max;
1888 __be64 rx_mtu_error;
1889 __be64 rx_mtu_crc_error;
1890 __be64 rx_crc_error;
1891 __be64 rx_len_error;
1892 __be64 rx_sym_error;
1895 __be64 rx_128b_255b;
1896 __be64 rx_256b_511b;
1897 __be64 rx_512b_1023b;
1898 __be64 rx_1024b_1518b;
1899 __be64 rx_1519b_max;
1916 #define FW_PORT_STATS_CMD_NSTATS(x) ((x) << 4)
1917 #define FW_PORT_STATS_CMD_BG_BM(x) ((x) << 0)
1918 #define FW_PORT_STATS_CMD_TX(x) ((x) << 7)
1919 #define FW_PORT_STATS_CMD_IX(x) ((x) << 0)
1921 /* port loopback stats */
1922 #define FW_NUM_LB_STATS 16
1923 enum fw_port_lb_stats_index {
1924 FW_STAT_LB_PORT_BYTES_IX,
1925 FW_STAT_LB_PORT_FRAMES_IX,
1926 FW_STAT_LB_PORT_BCAST_IX,
1927 FW_STAT_LB_PORT_MCAST_IX,
1928 FW_STAT_LB_PORT_UCAST_IX,
1929 FW_STAT_LB_PORT_ERROR_IX,
1930 FW_STAT_LB_PORT_64B_IX,
1931 FW_STAT_LB_PORT_65B_127B_IX,
1932 FW_STAT_LB_PORT_128B_255B_IX,
1933 FW_STAT_LB_PORT_256B_511B_IX,
1934 FW_STAT_LB_PORT_512B_1023B_IX,
1935 FW_STAT_LB_PORT_1024B_1518B_IX,
1936 FW_STAT_LB_PORT_1519B_MAX_IX,
1937 FW_STAT_LB_PORT_DROP_FRAMES_IX
1940 struct fw_port_lb_stats_cmd {
1941 __be32 op_to_lbport;
1942 __be32 retval_len16;
1943 union fw_port_lb_stats {
1944 struct fw_port_lb_stats_ctl {
1956 struct fw_port_lb_stats_all {
1965 __be64 tx_128b_255b;
1966 __be64 tx_256b_511b;
1967 __be64 tx_512b_1023b;
1968 __be64 tx_1024b_1518b;
1969 __be64 tx_1519b_max;
1976 #define FW_PORT_LB_STATS_CMD_LBPORT(x) ((x) << 0)
1977 #define FW_PORT_LB_STATS_CMD_NSTATS(x) ((x) << 4)
1978 #define FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << 0)
1979 #define FW_PORT_LB_STATS_CMD_IX(x) ((x) << 0)
1981 struct fw_rss_ind_tbl_cmd {
1983 #define FW_RSS_IND_TBL_CMD_VIID(x) ((x) << 0)
1984 __be32 retval_len16;
1989 #define FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << 20)
1990 #define FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << 10)
1991 #define FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << 0)
1995 __be32 iq12_to_iq14;
1996 __be32 iq15_to_iq17;
1997 __be32 iq18_to_iq20;
1998 __be32 iq21_to_iq23;
1999 __be32 iq24_to_iq26;
2000 __be32 iq27_to_iq29;
2005 struct fw_rss_glb_config_cmd {
2007 __be32 retval_len16;
2008 union fw_rss_glb_config {
2009 struct fw_rss_glb_config_manual {
2015 struct fw_rss_glb_config_basicvirtual {
2017 __be32 synmapen_to_hashtoeplitz;
2018 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN (1U << 8)
2019 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 (1U << 7)
2020 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 (1U << 6)
2021 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 (1U << 5)
2022 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 (1U << 4)
2023 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN (1U << 3)
2024 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN (1U << 2)
2025 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP (1U << 1)
2026 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ (1U << 0)
2033 #define FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << 28)
2034 #define FW_RSS_GLB_CONFIG_CMD_MODE_GET(x) (((x) >> 28) & 0xf)
2036 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
2037 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2039 struct fw_rss_vi_config_cmd {
2041 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
2042 __be32 retval_len16;
2043 union fw_rss_vi_config {
2044 struct fw_rss_vi_config_manual {
2049 struct fw_rss_vi_config_basicvirtual {
2051 __be32 defaultq_to_udpen;
2052 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) ((x) << 16)
2053 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_GET(x) (((x) >> 16) & 0x3ff)
2054 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN (1U << 4)
2055 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN (1U << 3)
2056 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN (1U << 2)
2057 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN (1U << 1)
2058 #define FW_RSS_VI_CONFIG_CMD_UDPEN (1U << 0)
2065 enum fw_error_type {
2066 FW_ERROR_TYPE_EXCEPTION = 0x0,
2067 FW_ERROR_TYPE_HWMODULE = 0x1,
2068 FW_ERROR_TYPE_WR = 0x2,
2069 FW_ERROR_TYPE_ACL = 0x3,
2072 struct fw_error_cmd {
2076 struct fw_error_exception {
2079 struct fw_error_hwmodule {
2083 struct fw_error_wr {
2089 struct fw_error_acl {
2100 struct fw_debug_cmd {
2102 #define FW_DEBUG_CMD_TYPE_GET(x) ((x) & 0xff)
2105 struct fw_debug_assert {
2111 u8 filename_8_15[8];
2114 struct fw_debug_prt {
2117 __be32 dprtstrparam0;
2118 __be32 dprtstrparam1;
2119 __be32 dprtstrparam2;
2120 __be32 dprtstrparam3;
2125 #define FW_PCIE_FW_ERR (1U << 31)
2126 #define FW_PCIE_FW_INIT (1U << 30)
2127 #define FW_PCIE_FW_HALT (1U << 29)
2128 #define FW_PCIE_FW_MASTER_VLD (1U << 15)
2129 #define FW_PCIE_FW_MASTER_MASK 0x7
2130 #define FW_PCIE_FW_MASTER_SHIFT 12
2131 #define FW_PCIE_FW_MASTER(x) ((x) << FW_PCIE_FW_MASTER_SHIFT)
2132 #define FW_PCIE_FW_MASTER_GET(x) (((x) >> FW_PCIE_FW_MASTER_SHIFT) & \
2133 FW_PCIE_FW_MASTER_MASK)
2138 __be16 len512; /* bin length in units of 512-bytes */
2139 __be32 fw_ver; /* firmware version */
2140 __be32 tp_microcode_ver;
2145 u8 intfver_iscsipdu;
2153 __be32 reserved6[23];
2156 #define FW_HDR_FW_VER_MAJOR_GET(x) (((x) >> 24) & 0xff)
2157 #define FW_HDR_FW_VER_MINOR_GET(x) (((x) >> 16) & 0xff)
2158 #define FW_HDR_FW_VER_MICRO_GET(x) (((x) >> 8) & 0xff)
2159 #define FW_HDR_FW_VER_BUILD_GET(x) (((x) >> 0) & 0xff)
2161 enum fw_hdr_intfver {
2162 FW_HDR_INTFVER_NIC = 0x00,
2163 FW_HDR_INTFVER_VNIC = 0x00,
2164 FW_HDR_INTFVER_OFLD = 0x00,
2165 FW_HDR_INTFVER_RI = 0x00,
2166 FW_HDR_INTFVER_ISCSIPDU = 0x00,
2167 FW_HDR_INTFVER_ISCSI = 0x00,
2168 FW_HDR_INTFVER_FCOEPDU = 0x00,
2169 FW_HDR_INTFVER_FCOE = 0x00,
2173 FW_HDR_FLAGS_RESET_HALT = 0x00000001,
2176 #endif /* _T4FW_INTERFACE_H_ */