drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2009-2016 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef _T4FW_INTERFACE_H_
  36 #define _T4FW_INTERFACE_H_
  37
  38 enum fw_retval {
  39         FW_SUCCESS              = 0,    /* completed successfully */
  40         FW_EPERM                = 1,    /* operation not permitted */
  41         FW_ENOENT               = 2,    /* no such file or directory */
  42         FW_EIO                  = 5,    /* input/output error; hw bad */
  43         FW_ENOEXEC              = 8,    /* exec format error; inv microcode */
  44         FW_EAGAIN               = 11,   /* try again */
  45         FW_ENOMEM               = 12,   /* out of memory */
  46         FW_EFAULT               = 14,   /* bad address; fw bad */
  47         FW_EBUSY                = 16,   /* resource busy */
  48         FW_EEXIST               = 17,   /* file exists */
  49         FW_ENODEV               = 19,   /* no such device */
  50         FW_EINVAL               = 22,   /* invalid argument */
  51         FW_ENOSPC               = 28,   /* no space left on device */
  52         FW_ENOSYS               = 38,   /* functionality not implemented */
  53         FW_ENODATA              = 61,   /* no data available */
  54         FW_EPROTO               = 71,   /* protocol error */
  55         FW_EADDRINUSE           = 98,   /* address already in use */
  56         FW_EADDRNOTAVAIL        = 99,   /* cannot assigned requested address */
  57         FW_ENETDOWN             = 100,  /* network is down */
  58         FW_ENETUNREACH          = 101,  /* network is unreachable */
  59         FW_ENOBUFS              = 105,  /* no buffer space available */
  60         FW_ETIMEDOUT            = 110,  /* timeout */
  61         FW_EINPROGRESS          = 115,  /* fw internal */
  62         FW_SCSI_ABORT_REQUESTED = 128,  /* */
  63         FW_SCSI_ABORT_TIMEDOUT  = 129,  /* */
  64         FW_SCSI_ABORTED         = 130,  /* */
  65         FW_SCSI_CLOSE_REQUESTED = 131,  /* */
  66         FW_ERR_LINK_DOWN        = 132,  /* */
  67         FW_RDEV_NOT_READY       = 133,  /* */
  68         FW_ERR_RDEV_LOST        = 134,  /* */
  69         FW_ERR_RDEV_LOGO        = 135,  /* */
  70         FW_FCOE_NO_XCHG         = 136,  /* */
  71         FW_SCSI_RSP_ERR         = 137,  /* */
  72         FW_ERR_RDEV_IMPL_LOGO   = 138,  /* */
  73         FW_SCSI_UNDER_FLOW_ERR  = 139,  /* */
  74         FW_SCSI_OVER_FLOW_ERR   = 140,  /* */
  75         FW_SCSI_DDP_ERR         = 141,  /* DDP error*/
  76         FW_SCSI_TASK_ERR        = 142,  /* No SCSI tasks available */
  77 };
  78
  79 #define FW_T4VF_SGE_BASE_ADDR      0x0000
  80 #define FW_T4VF_MPS_BASE_ADDR      0x0100
  81 #define FW_T4VF_PL_BASE_ADDR       0x0200
  82 #define FW_T4VF_MBDATA_BASE_ADDR   0x0240
  83 #define FW_T4VF_CIM_BASE_ADDR      0x0300
  84
  85 enum fw_wr_opcodes {
  86         FW_FILTER_WR                   = 0x02,
  87         FW_ULPTX_WR                    = 0x04,
  88         FW_TP_WR                       = 0x05,
  89         FW_ETH_TX_PKT_WR               = 0x08,
  90         FW_ETH_TX_EO_WR                = 0x1c,
  91         FW_OFLD_CONNECTION_WR          = 0x2f,
  92         FW_FLOWC_WR                    = 0x0a,
  93         FW_OFLD_TX_DATA_WR             = 0x0b,
  94         FW_CMD_WR                      = 0x10,
  95         FW_ETH_TX_PKT_VM_WR            = 0x11,
  96         FW_RI_RES_WR                   = 0x0c,
  97         FW_RI_INIT_WR                  = 0x0d,
  98         FW_RI_RDMA_WRITE_WR            = 0x14,
  99         FW_RI_SEND_WR                  = 0x15,
 100         FW_RI_RDMA_READ_WR             = 0x16,
 101         FW_RI_RECV_WR                  = 0x17,
 102         FW_RI_BIND_MW_WR               = 0x18,
 103         FW_RI_FR_NSMR_WR               = 0x19,
 104         FW_RI_FR_NSMR_TPTE_WR          = 0x20,
 105         FW_RI_RDMA_WRITE_CMPL_WR       = 0x21,
 106         FW_RI_INV_LSTAG_WR             = 0x1a,
 107         FW_ISCSI_TX_DATA_WR            = 0x45,
 108         FW_PTP_TX_PKT_WR               = 0x46,
 109         FW_TLSTX_DATA_WR               = 0x68,
 110         FW_CRYPTO_LOOKASIDE_WR         = 0X6d,
 111         FW_LASTC2E_WR                  = 0x70,
 112         FW_FILTER2_WR                  = 0x77
 113 };
 114
 115 struct fw_wr_hdr {
 116         __be32 hi;
 117         __be32 lo;
 118 };
 119
 120 /* work request opcode (hi) */
 121 #define FW_WR_OP_S      24
 122 #define FW_WR_OP_M      0xff
 123 #define FW_WR_OP_V(x)   ((x) << FW_WR_OP_S)
 124 #define FW_WR_OP_G(x)   (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
 125
 126 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
 127 #define FW_WR_ATOMIC_S          23
 128 #define FW_WR_ATOMIC_V(x)       ((x) << FW_WR_ATOMIC_S)
 129
 130 /* flush flag (hi) - firmware flushes flushable work request buffered
 131  * in the flow context.
 132  */
 133 #define FW_WR_FLUSH_S     22
 134 #define FW_WR_FLUSH_V(x)  ((x) << FW_WR_FLUSH_S)
 135
 136 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
 137 #define FW_WR_COMPL_S     21
 138 #define FW_WR_COMPL_V(x)  ((x) << FW_WR_COMPL_S)
 139 #define FW_WR_COMPL_F     FW_WR_COMPL_V(1U)
 140
 141 /* work request immediate data length (hi) */
 142 #define FW_WR_IMMDLEN_S 0
 143 #define FW_WR_IMMDLEN_M 0xff
 144 #define FW_WR_IMMDLEN_V(x)      ((x) << FW_WR_IMMDLEN_S)
 145
 146 /* egress queue status update to associated ingress queue entry (lo) */
 147 #define FW_WR_EQUIQ_S           31
 148 #define FW_WR_EQUIQ_V(x)        ((x) << FW_WR_EQUIQ_S)
 149 #define FW_WR_EQUIQ_F           FW_WR_EQUIQ_V(1U)
 150
 151 /* egress queue status update to egress queue status entry (lo) */
 152 #define FW_WR_EQUEQ_S           30
 153 #define FW_WR_EQUEQ_V(x)        ((x) << FW_WR_EQUEQ_S)
 154 #define FW_WR_EQUEQ_F           FW_WR_EQUEQ_V(1U)
 155
 156 /* flow context identifier (lo) */
 157 #define FW_WR_FLOWID_S          8
 158 #define FW_WR_FLOWID_V(x)       ((x) << FW_WR_FLOWID_S)
 159
 160 /* length in units of 16-bytes (lo) */
 161 #define FW_WR_LEN16_S           0
 162 #define FW_WR_LEN16_V(x)        ((x) << FW_WR_LEN16_S)
 163
 164 #define HW_TPL_FR_MT_PR_IV_P_FC         0X32B
 165 #define HW_TPL_FR_MT_PR_OV_P_FC         0X327
 166
 167 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
 168 enum fw_filter_wr_cookie {
 169         FW_FILTER_WR_SUCCESS,
 170         FW_FILTER_WR_FLT_ADDED,
 171         FW_FILTER_WR_FLT_DELETED,
 172         FW_FILTER_WR_SMT_TBL_FULL,
 173         FW_FILTER_WR_EINVAL,
 174 };
 175
 176 struct fw_filter_wr {
 177         __be32 op_pkd;
 178         __be32 len16_pkd;
 179         __be64 r3;
 180         __be32 tid_to_iq;
 181         __be32 del_filter_to_l2tix;
 182         __be16 ethtype;
 183         __be16 ethtypem;
 184         __u8   frag_to_ovlan_vldm;
 185         __u8   smac_sel;
 186         __be16 rx_chan_rx_rpl_iq;
 187         __be32 maci_to_matchtypem;
 188         __u8   ptcl;
 189         __u8   ptclm;
 190         __u8   ttyp;
 191         __u8   ttypm;
 192         __be16 ivlan;
 193         __be16 ivlanm;
 194         __be16 ovlan;
 195         __be16 ovlanm;
 196         __u8   lip[16];
 197         __u8   lipm[16];
 198         __u8   fip[16];
 199         __u8   fipm[16];
 200         __be16 lp;
 201         __be16 lpm;
 202         __be16 fp;
 203         __be16 fpm;
 204         __be16 r7;
 205         __u8   sma[6];
 206 };
 207
 208 struct fw_filter2_wr {
 209         __be32 op_pkd;
 210         __be32 len16_pkd;
 211         __be64 r3;
 212         __be32 tid_to_iq;
 213         __be32 del_filter_to_l2tix;
 214         __be16 ethtype;
 215         __be16 ethtypem;
 216         __u8   frag_to_ovlan_vldm;
 217         __u8   smac_sel;
 218         __be16 rx_chan_rx_rpl_iq;
 219         __be32 maci_to_matchtypem;
 220         __u8   ptcl;
 221         __u8   ptclm;
 222         __u8   ttyp;
 223         __u8   ttypm;
 224         __be16 ivlan;
 225         __be16 ivlanm;
 226         __be16 ovlan;
 227         __be16 ovlanm;
 228         __u8   lip[16];
 229         __u8   lipm[16];
 230         __u8   fip[16];
 231         __u8   fipm[16];
 232         __be16 lp;
 233         __be16 lpm;
 234         __be16 fp;
 235         __be16 fpm;
 236         __be16 r7;
 237         __u8   sma[6];
 238         __be16 r8;
 239         __u8   filter_type_swapmac;
 240         __u8   natmode_to_ulp_type;
 241         __be16 newlport;
 242         __be16 newfport;
 243         __u8   newlip[16];
 244         __u8   newfip[16];
 245         __be32 natseqcheck;
 246         __be32 r9;
 247         __be64 r10;
 248         __be64 r11;
 249         __be64 r12;
 250         __be64 r13;
 251 };
 252
 253 #define FW_FILTER_WR_TID_S      12
 254 #define FW_FILTER_WR_TID_M      0xfffff
 255 #define FW_FILTER_WR_TID_V(x)   ((x) << FW_FILTER_WR_TID_S)
 256 #define FW_FILTER_WR_TID_G(x)   \
 257         (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
 258
 259 #define FW_FILTER_WR_RQTYPE_S           11
 260 #define FW_FILTER_WR_RQTYPE_M           0x1
 261 #define FW_FILTER_WR_RQTYPE_V(x)        ((x) << FW_FILTER_WR_RQTYPE_S)
 262 #define FW_FILTER_WR_RQTYPE_G(x)        \
 263         (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
 264 #define FW_FILTER_WR_RQTYPE_F   FW_FILTER_WR_RQTYPE_V(1U)
 265
 266 #define FW_FILTER_WR_NOREPLY_S          10
 267 #define FW_FILTER_WR_NOREPLY_M          0x1
 268 #define FW_FILTER_WR_NOREPLY_V(x)       ((x) << FW_FILTER_WR_NOREPLY_S)
 269 #define FW_FILTER_WR_NOREPLY_G(x)       \
 270         (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
 271 #define FW_FILTER_WR_NOREPLY_F  FW_FILTER_WR_NOREPLY_V(1U)
 272
 273 #define FW_FILTER_WR_IQ_S       0
 274 #define FW_FILTER_WR_IQ_M       0x3ff
 275 #define FW_FILTER_WR_IQ_V(x)    ((x) << FW_FILTER_WR_IQ_S)
 276 #define FW_FILTER_WR_IQ_G(x)    \
 277         (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
 278
 279 #define FW_FILTER_WR_DEL_FILTER_S       31
 280 #define FW_FILTER_WR_DEL_FILTER_M       0x1
 281 #define FW_FILTER_WR_DEL_FILTER_V(x)    ((x) << FW_FILTER_WR_DEL_FILTER_S)
 282 #define FW_FILTER_WR_DEL_FILTER_G(x)    \
 283         (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
 284 #define FW_FILTER_WR_DEL_FILTER_F       FW_FILTER_WR_DEL_FILTER_V(1U)
 285
 286 #define FW_FILTER_WR_RPTTID_S           25
 287 #define FW_FILTER_WR_RPTTID_M           0x1
 288 #define FW_FILTER_WR_RPTTID_V(x)        ((x) << FW_FILTER_WR_RPTTID_S)
 289 #define FW_FILTER_WR_RPTTID_G(x)        \
 290         (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
 291 #define FW_FILTER_WR_RPTTID_F   FW_FILTER_WR_RPTTID_V(1U)
 292
 293 #define FW_FILTER_WR_DROP_S     24
 294 #define FW_FILTER_WR_DROP_M     0x1
 295 #define FW_FILTER_WR_DROP_V(x)  ((x) << FW_FILTER_WR_DROP_S)
 296 #define FW_FILTER_WR_DROP_G(x)  \
 297         (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
 298 #define FW_FILTER_WR_DROP_F     FW_FILTER_WR_DROP_V(1U)
 299
 300 #define FW_FILTER_WR_DIRSTEER_S         23
 301 #define FW_FILTER_WR_DIRSTEER_M         0x1
 302 #define FW_FILTER_WR_DIRSTEER_V(x)      ((x) << FW_FILTER_WR_DIRSTEER_S)
 303 #define FW_FILTER_WR_DIRSTEER_G(x)      \
 304         (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
 305 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
 306
 307 #define FW_FILTER_WR_MASKHASH_S         22
 308 #define FW_FILTER_WR_MASKHASH_M         0x1
 309 #define FW_FILTER_WR_MASKHASH_V(x)      ((x) << FW_FILTER_WR_MASKHASH_S)
 310 #define FW_FILTER_WR_MASKHASH_G(x)      \
 311         (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
 312 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
 313
 314 #define FW_FILTER_WR_DIRSTEERHASH_S     21
 315 #define FW_FILTER_WR_DIRSTEERHASH_M     0x1
 316 #define FW_FILTER_WR_DIRSTEERHASH_V(x)  ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
 317 #define FW_FILTER_WR_DIRSTEERHASH_G(x)  \
 318         (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
 319 #define FW_FILTER_WR_DIRSTEERHASH_F     FW_FILTER_WR_DIRSTEERHASH_V(1U)
 320
 321 #define FW_FILTER_WR_LPBK_S     20
 322 #define FW_FILTER_WR_LPBK_M     0x1
 323 #define FW_FILTER_WR_LPBK_V(x)  ((x) << FW_FILTER_WR_LPBK_S)
 324 #define FW_FILTER_WR_LPBK_G(x)  \
 325         (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
 326 #define FW_FILTER_WR_LPBK_F     FW_FILTER_WR_LPBK_V(1U)
 327
 328 #define FW_FILTER_WR_DMAC_S     19
 329 #define FW_FILTER_WR_DMAC_M     0x1
 330 #define FW_FILTER_WR_DMAC_V(x)  ((x) << FW_FILTER_WR_DMAC_S)
 331 #define FW_FILTER_WR_DMAC_G(x)  \
 332         (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
 333 #define FW_FILTER_WR_DMAC_F     FW_FILTER_WR_DMAC_V(1U)
 334
 335 #define FW_FILTER_WR_SMAC_S     18
 336 #define FW_FILTER_WR_SMAC_M     0x1
 337 #define FW_FILTER_WR_SMAC_V(x)  ((x) << FW_FILTER_WR_SMAC_S)
 338 #define FW_FILTER_WR_SMAC_G(x)  \
 339         (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
 340 #define FW_FILTER_WR_SMAC_F     FW_FILTER_WR_SMAC_V(1U)
 341
 342 #define FW_FILTER_WR_INSVLAN_S          17
 343 #define FW_FILTER_WR_INSVLAN_M          0x1
 344 #define FW_FILTER_WR_INSVLAN_V(x)       ((x) << FW_FILTER_WR_INSVLAN_S)
 345 #define FW_FILTER_WR_INSVLAN_G(x)       \
 346         (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
 347 #define FW_FILTER_WR_INSVLAN_F  FW_FILTER_WR_INSVLAN_V(1U)
 348
 349 #define FW_FILTER_WR_RMVLAN_S           16
 350 #define FW_FILTER_WR_RMVLAN_M           0x1
 351 #define FW_FILTER_WR_RMVLAN_V(x)        ((x) << FW_FILTER_WR_RMVLAN_S)
 352 #define FW_FILTER_WR_RMVLAN_G(x)        \
 353         (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
 354 #define FW_FILTER_WR_RMVLAN_F   FW_FILTER_WR_RMVLAN_V(1U)
 355
 356 #define FW_FILTER_WR_HITCNTS_S          15
 357 #define FW_FILTER_WR_HITCNTS_M          0x1
 358 #define FW_FILTER_WR_HITCNTS_V(x)       ((x) << FW_FILTER_WR_HITCNTS_S)
 359 #define FW_FILTER_WR_HITCNTS_G(x)       \
 360         (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
 361 #define FW_FILTER_WR_HITCNTS_F  FW_FILTER_WR_HITCNTS_V(1U)
 362
 363 #define FW_FILTER_WR_TXCHAN_S           13
 364 #define FW_FILTER_WR_TXCHAN_M           0x3
 365 #define FW_FILTER_WR_TXCHAN_V(x)        ((x) << FW_FILTER_WR_TXCHAN_S)
 366 #define FW_FILTER_WR_TXCHAN_G(x)        \
 367         (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
 368
 369 #define FW_FILTER_WR_PRIO_S     12
 370 #define FW_FILTER_WR_PRIO_M     0x1
 371 #define FW_FILTER_WR_PRIO_V(x)  ((x) << FW_FILTER_WR_PRIO_S)
 372 #define FW_FILTER_WR_PRIO_G(x)  \
 373         (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
 374 #define FW_FILTER_WR_PRIO_F     FW_FILTER_WR_PRIO_V(1U)
 375
 376 #define FW_FILTER_WR_L2TIX_S    0
 377 #define FW_FILTER_WR_L2TIX_M    0xfff
 378 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
 379 #define FW_FILTER_WR_L2TIX_G(x) \
 380         (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
 381
 382 #define FW_FILTER_WR_FRAG_S     7
 383 #define FW_FILTER_WR_FRAG_M     0x1
 384 #define FW_FILTER_WR_FRAG_V(x)  ((x) << FW_FILTER_WR_FRAG_S)
 385 #define FW_FILTER_WR_FRAG_G(x)  \
 386         (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
 387 #define FW_FILTER_WR_FRAG_F     FW_FILTER_WR_FRAG_V(1U)
 388
 389 #define FW_FILTER_WR_FRAGM_S    6
 390 #define FW_FILTER_WR_FRAGM_M    0x1
 391 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
 392 #define FW_FILTER_WR_FRAGM_G(x) \
 393         (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
 394 #define FW_FILTER_WR_FRAGM_F    FW_FILTER_WR_FRAGM_V(1U)
 395
 396 #define FW_FILTER_WR_IVLAN_VLD_S        5
 397 #define FW_FILTER_WR_IVLAN_VLD_M        0x1
 398 #define FW_FILTER_WR_IVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_IVLAN_VLD_S)
 399 #define FW_FILTER_WR_IVLAN_VLD_G(x)     \
 400         (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
 401 #define FW_FILTER_WR_IVLAN_VLD_F        FW_FILTER_WR_IVLAN_VLD_V(1U)
 402
 403 #define FW_FILTER_WR_OVLAN_VLD_S        4
 404 #define FW_FILTER_WR_OVLAN_VLD_M        0x1
 405 #define FW_FILTER_WR_OVLAN_VLD_V(x)     ((x) << FW_FILTER_WR_OVLAN_VLD_S)
 406 #define FW_FILTER_WR_OVLAN_VLD_G(x)     \
 407         (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
 408 #define FW_FILTER_WR_OVLAN_VLD_F        FW_FILTER_WR_OVLAN_VLD_V(1U)
 409
 410 #define FW_FILTER_WR_IVLAN_VLDM_S       3
 411 #define FW_FILTER_WR_IVLAN_VLDM_M       0x1
 412 #define FW_FILTER_WR_IVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
 413 #define FW_FILTER_WR_IVLAN_VLDM_G(x)    \
 414         (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
 415 #define FW_FILTER_WR_IVLAN_VLDM_F       FW_FILTER_WR_IVLAN_VLDM_V(1U)
 416
 417 #define FW_FILTER_WR_OVLAN_VLDM_S       2
 418 #define FW_FILTER_WR_OVLAN_VLDM_M       0x1
 419 #define FW_FILTER_WR_OVLAN_VLDM_V(x)    ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
 420 #define FW_FILTER_WR_OVLAN_VLDM_G(x)    \
 421         (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
 422 #define FW_FILTER_WR_OVLAN_VLDM_F       FW_FILTER_WR_OVLAN_VLDM_V(1U)
 423
 424 #define FW_FILTER_WR_RX_CHAN_S          15
 425 #define FW_FILTER_WR_RX_CHAN_M          0x1
 426 #define FW_FILTER_WR_RX_CHAN_V(x)       ((x) << FW_FILTER_WR_RX_CHAN_S)
 427 #define FW_FILTER_WR_RX_CHAN_G(x)       \
 428         (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
 429 #define FW_FILTER_WR_RX_CHAN_F  FW_FILTER_WR_RX_CHAN_V(1U)
 430
 431 #define FW_FILTER_WR_RX_RPL_IQ_S        0
 432 #define FW_FILTER_WR_RX_RPL_IQ_M        0x3ff
 433 #define FW_FILTER_WR_RX_RPL_IQ_V(x)     ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
 434 #define FW_FILTER_WR_RX_RPL_IQ_G(x)     \
 435         (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
 436
 437 #define FW_FILTER2_WR_FILTER_TYPE_S     1
 438 #define FW_FILTER2_WR_FILTER_TYPE_M     0x1
 439 #define FW_FILTER2_WR_FILTER_TYPE_V(x)  ((x) << FW_FILTER2_WR_FILTER_TYPE_S)
 440 #define FW_FILTER2_WR_FILTER_TYPE_G(x)  \
 441         (((x) >> FW_FILTER2_WR_FILTER_TYPE_S) & FW_FILTER2_WR_FILTER_TYPE_M)
 442 #define FW_FILTER2_WR_FILTER_TYPE_F     FW_FILTER2_WR_FILTER_TYPE_V(1U)
 443
 444 #define FW_FILTER2_WR_NATMODE_S         5
 445 #define FW_FILTER2_WR_NATMODE_M         0x7
 446 #define FW_FILTER2_WR_NATMODE_V(x)      ((x) << FW_FILTER2_WR_NATMODE_S)
 447 #define FW_FILTER2_WR_NATMODE_G(x)      \
 448         (((x) >> FW_FILTER2_WR_NATMODE_S) & FW_FILTER2_WR_NATMODE_M)
 449
 450 #define FW_FILTER2_WR_NATFLAGCHECK_S    4
 451 #define FW_FILTER2_WR_NATFLAGCHECK_M    0x1
 452 #define FW_FILTER2_WR_NATFLAGCHECK_V(x) ((x) << FW_FILTER2_WR_NATFLAGCHECK_S)
 453 #define FW_FILTER2_WR_NATFLAGCHECK_G(x) \
 454         (((x) >> FW_FILTER2_WR_NATFLAGCHECK_S) & FW_FILTER2_WR_NATFLAGCHECK_M)
 455 #define FW_FILTER2_WR_NATFLAGCHECK_F    FW_FILTER2_WR_NATFLAGCHECK_V(1U)
 456
 457 #define FW_FILTER2_WR_ULP_TYPE_S        0
 458 #define FW_FILTER2_WR_ULP_TYPE_M        0xf
 459 #define FW_FILTER2_WR_ULP_TYPE_V(x)     ((x) << FW_FILTER2_WR_ULP_TYPE_S)
 460 #define FW_FILTER2_WR_ULP_TYPE_G(x)     \
 461         (((x) >> FW_FILTER2_WR_ULP_TYPE_S) & FW_FILTER2_WR_ULP_TYPE_M)
 462
 463 #define FW_FILTER_WR_MACI_S     23
 464 #define FW_FILTER_WR_MACI_M     0x1ff
 465 #define FW_FILTER_WR_MACI_V(x)  ((x) << FW_FILTER_WR_MACI_S)
 466 #define FW_FILTER_WR_MACI_G(x)  \
 467         (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
 468
 469 #define FW_FILTER_WR_MACIM_S    14
 470 #define FW_FILTER_WR_MACIM_M    0x1ff
 471 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
 472 #define FW_FILTER_WR_MACIM_G(x) \
 473         (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
 474
 475 #define FW_FILTER_WR_FCOE_S     13
 476 #define FW_FILTER_WR_FCOE_M     0x1
 477 #define FW_FILTER_WR_FCOE_V(x)  ((x) << FW_FILTER_WR_FCOE_S)
 478 #define FW_FILTER_WR_FCOE_G(x)  \
 479         (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
 480 #define FW_FILTER_WR_FCOE_F     FW_FILTER_WR_FCOE_V(1U)
 481
 482 #define FW_FILTER_WR_FCOEM_S    12
 483 #define FW_FILTER_WR_FCOEM_M    0x1
 484 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
 485 #define FW_FILTER_WR_FCOEM_G(x) \
 486         (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
 487 #define FW_FILTER_WR_FCOEM_F    FW_FILTER_WR_FCOEM_V(1U)
 488
 489 #define FW_FILTER_WR_PORT_S     9
 490 #define FW_FILTER_WR_PORT_M     0x7
 491 #define FW_FILTER_WR_PORT_V(x)  ((x) << FW_FILTER_WR_PORT_S)
 492 #define FW_FILTER_WR_PORT_G(x)  \
 493         (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
 494
 495 #define FW_FILTER_WR_PORTM_S    6
 496 #define FW_FILTER_WR_PORTM_M    0x7
 497 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
 498 #define FW_FILTER_WR_PORTM_G(x) \
 499         (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
 500
 501 #define FW_FILTER_WR_MATCHTYPE_S        3
 502 #define FW_FILTER_WR_MATCHTYPE_M        0x7
 503 #define FW_FILTER_WR_MATCHTYPE_V(x)     ((x) << FW_FILTER_WR_MATCHTYPE_S)
 504 #define FW_FILTER_WR_MATCHTYPE_G(x)     \
 505         (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
 506
 507 #define FW_FILTER_WR_MATCHTYPEM_S       0
 508 #define FW_FILTER_WR_MATCHTYPEM_M       0x7
 509 #define FW_FILTER_WR_MATCHTYPEM_V(x)    ((x) << FW_FILTER_WR_MATCHTYPEM_S)
 510 #define FW_FILTER_WR_MATCHTYPEM_G(x)    \
 511         (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
 512
 513 struct fw_ulptx_wr {
 514         __be32 op_to_compl;
 515         __be32 flowid_len16;
 516         u64 cookie;
 517 };
 518
 519 #define FW_ULPTX_WR_DATA_S      28
 520 #define FW_ULPTX_WR_DATA_M      0x1
 521 #define FW_ULPTX_WR_DATA_V(x)   ((x) << FW_ULPTX_WR_DATA_S)
 522 #define FW_ULPTX_WR_DATA_G(x)   \
 523         (((x) >> FW_ULPTX_WR_DATA_S) & FW_ULPTX_WR_DATA_M)
 524 #define FW_ULPTX_WR_DATA_F      FW_ULPTX_WR_DATA_V(1U)
 525
 526 struct fw_tp_wr {
 527         __be32 op_to_immdlen;
 528         __be32 flowid_len16;
 529         u64 cookie;
 530 };
 531
 532 struct fw_eth_tx_pkt_wr {
 533         __be32 op_immdlen;
 534         __be32 equiq_to_len16;
 535         __be64 r3;
 536 };
 537
 538 enum fw_eth_tx_eo_type {
 539         FW_ETH_TX_EO_TYPE_TCPSEG = 1,
 540 };
 541
 542 struct fw_eth_tx_eo_wr {
 543         __be32 op_immdlen;
 544         __be32 equiq_to_len16;
 545         __be64 r3;
 546         union fw_eth_tx_eo {
 547                 struct fw_eth_tx_eo_tcpseg {
 548                         __u8   type;
 549                         __u8   ethlen;
 550                         __be16 iplen;
 551                         __u8   tcplen;
 552                         __u8   tsclk_tsoff;
 553                         __be16 r4;
 554                         __be16 mss;
 555                         __be16 r5;
 556                         __be32 plen;
 557                 } tcpseg;
 558         } u;
 559 };
 560
 561 #define FW_ETH_TX_EO_WR_IMMDLEN_S       0
 562 #define FW_ETH_TX_EO_WR_IMMDLEN_M       0x1ff
 563 #define FW_ETH_TX_EO_WR_IMMDLEN_V(x)    ((x) << FW_ETH_TX_EO_WR_IMMDLEN_S)
 564 #define FW_ETH_TX_EO_WR_IMMDLEN_G(x)    \
 565         (((x) >> FW_ETH_TX_EO_WR_IMMDLEN_S) & FW_ETH_TX_EO_WR_IMMDLEN_M)
 566
 567 struct fw_ofld_connection_wr {
 568         __be32 op_compl;
 569         __be32 len16_pkd;
 570         __u64  cookie;
 571         __be64 r2;
 572         __be64 r3;
 573         struct fw_ofld_connection_le {
 574                 __be32 version_cpl;
 575                 __be32 filter;
 576                 __be32 r1;
 577                 __be16 lport;
 578                 __be16 pport;
 579                 union fw_ofld_connection_leip {
 580                         struct fw_ofld_connection_le_ipv4 {
 581                                 __be32 pip;
 582                                 __be32 lip;
 583                                 __be64 r0;
 584                                 __be64 r1;
 585                                 __be64 r2;
 586                         } ipv4;
 587                         struct fw_ofld_connection_le_ipv6 {
 588                                 __be64 pip_hi;
 589                                 __be64 pip_lo;
 590                                 __be64 lip_hi;
 591                                 __be64 lip_lo;
 592                         } ipv6;
 593                 } u;
 594         } le;
 595         struct fw_ofld_connection_tcb {
 596                 __be32 t_state_to_astid;
 597                 __be16 cplrxdataack_cplpassacceptrpl;
 598                 __be16 rcv_adv;
 599                 __be32 rcv_nxt;
 600                 __be32 tx_max;
 601                 __be64 opt0;
 602                 __be32 opt2;
 603                 __be32 r1;
 604                 __be64 r2;
 605                 __be64 r3;
 606         } tcb;
 607 };
 608
 609 #define FW_OFLD_CONNECTION_WR_VERSION_S                31
 610 #define FW_OFLD_CONNECTION_WR_VERSION_M                0x1
 611 #define FW_OFLD_CONNECTION_WR_VERSION_V(x)     \
 612         ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
 613 #define FW_OFLD_CONNECTION_WR_VERSION_G(x)     \
 614         (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
 615         FW_OFLD_CONNECTION_WR_VERSION_M)
 616 #define FW_OFLD_CONNECTION_WR_VERSION_F        \
 617         FW_OFLD_CONNECTION_WR_VERSION_V(1U)
 618
 619 #define FW_OFLD_CONNECTION_WR_CPL_S    30
 620 #define FW_OFLD_CONNECTION_WR_CPL_M    0x1
 621 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
 622 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
 623         (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
 624 #define FW_OFLD_CONNECTION_WR_CPL_F    FW_OFLD_CONNECTION_WR_CPL_V(1U)
 625
 626 #define FW_OFLD_CONNECTION_WR_T_STATE_S                28
 627 #define FW_OFLD_CONNECTION_WR_T_STATE_M                0xf
 628 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x)     \
 629         ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
 630 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x)     \
 631         (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
 632         FW_OFLD_CONNECTION_WR_T_STATE_M)
 633
 634 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S      24
 635 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M      0xf
 636 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x)   \
 637         ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
 638 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x)   \
 639         (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
 640         FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
 641
 642 #define FW_OFLD_CONNECTION_WR_ASTID_S          0
 643 #define FW_OFLD_CONNECTION_WR_ASTID_M          0xffffff
 644 #define FW_OFLD_CONNECTION_WR_ASTID_V(x)       \
 645         ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
 646 #define FW_OFLD_CONNECTION_WR_ASTID_G(x)       \
 647         (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
 648
 649 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S   15
 650 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M   0x1
 651 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x)        \
 652         ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
 653 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x)        \
 654         (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
 655         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
 656 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F   \
 657         FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
 658
 659 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S       14
 660 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M       0x1
 661 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x)    \
 662         ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
 663 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x)    \
 664         (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
 665         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
 666 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F       \
 667         FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
 668
 669 enum fw_flowc_mnem_tcpstate {
 670         FW_FLOWC_MNEM_TCPSTATE_CLOSED   = 0, /* illegal */
 671         FW_FLOWC_MNEM_TCPSTATE_LISTEN   = 1, /* illegal */
 672         FW_FLOWC_MNEM_TCPSTATE_SYNSENT  = 2, /* illegal */
 673         FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */
 674         FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */
 675         FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */
 676         FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and
 677                                               * will resend FIN - equiv ESTAB
 678                                               */
 679         FW_FLOWC_MNEM_TCPSTATE_CLOSING  = 7, /* haven't gotten ACK for FIN and
 680                                               * will resend FIN but have
 681                                               * received FIN
 682                                               */
 683         FW_FLOWC_MNEM_TCPSTATE_LASTACK  = 8, /* haven't gotten ACK for FIN and
 684                                               * will resend FIN but have
 685                                               * received FIN
 686                                               */
 687         FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK,
 688                                               * waiting for FIN
 689                                               */
 690         FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */
 691 };
 692
 693 enum fw_flowc_mnem {
 694         FW_FLOWC_MNEM_PFNVFN,           /* PFN [15:8] VFN [7:0] */
 695         FW_FLOWC_MNEM_CH,
 696         FW_FLOWC_MNEM_PORT,
 697         FW_FLOWC_MNEM_IQID,
 698         FW_FLOWC_MNEM_SNDNXT,
 699         FW_FLOWC_MNEM_RCVNXT,
 700         FW_FLOWC_MNEM_SNDBUF,
 701         FW_FLOWC_MNEM_MSS,
 702         FW_FLOWC_MNEM_TXDATAPLEN_MAX,
 703         FW_FLOWC_MNEM_TCPSTATE,
 704         FW_FLOWC_MNEM_EOSTATE,
 705         FW_FLOWC_MNEM_SCHEDCLASS,
 706         FW_FLOWC_MNEM_DCBPRIO,
 707         FW_FLOWC_MNEM_SND_SCALE,
 708         FW_FLOWC_MNEM_RCV_SCALE,
 709         FW_FLOWC_MNEM_ULD_MODE,
 710         FW_FLOWC_MNEM_MAX,
 711 };
 712
 713 struct fw_flowc_mnemval {
 714         u8 mnemonic;
 715         u8 r4[3];
 716         __be32 val;
 717 };
 718
 719 struct fw_flowc_wr {
 720         __be32 op_to_nparams;
 721         __be32 flowid_len16;
 722         struct fw_flowc_mnemval mnemval[0];
 723 };
 724
 725 #define FW_FLOWC_WR_NPARAMS_S           0
 726 #define FW_FLOWC_WR_NPARAMS_V(x)        ((x) << FW_FLOWC_WR_NPARAMS_S)
 727
 728 struct fw_ofld_tx_data_wr {
 729         __be32 op_to_immdlen;
 730         __be32 flowid_len16;
 731         __be32 plen;
 732         __be32 tunnel_to_proxy;
 733 };
 734
 735 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_S   30
 736 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_V(x) ((x) << FW_OFLD_TX_DATA_WR_ALIGNPLD_S)
 737 #define FW_OFLD_TX_DATA_WR_ALIGNPLD_F   FW_OFLD_TX_DATA_WR_ALIGNPLD_V(1U)
 738
 739 #define FW_OFLD_TX_DATA_WR_SHOVE_S      29
 740 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x)   ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
 741 #define FW_OFLD_TX_DATA_WR_SHOVE_F      FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
 742
 743 #define FW_OFLD_TX_DATA_WR_TUNNEL_S     19
 744 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x)  ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
 745
 746 #define FW_OFLD_TX_DATA_WR_SAVE_S       18
 747 #define FW_OFLD_TX_DATA_WR_SAVE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
 748
 749 #define FW_OFLD_TX_DATA_WR_FLUSH_S      17
 750 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x)   ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
 751 #define FW_OFLD_TX_DATA_WR_FLUSH_F      FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
 752
 753 #define FW_OFLD_TX_DATA_WR_URGENT_S     16
 754 #define FW_OFLD_TX_DATA_WR_URGENT_V(x)  ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
 755
 756 #define FW_OFLD_TX_DATA_WR_MORE_S       15
 757 #define FW_OFLD_TX_DATA_WR_MORE_V(x)    ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
 758
 759 #define FW_OFLD_TX_DATA_WR_ULPMODE_S    10
 760 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
 761
 762 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S         6
 763 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x)      \
 764         ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
 765
 766 struct fw_cmd_wr {
 767         __be32 op_dma;
 768         __be32 len16_pkd;
 769         __be64 cookie_daddr;
 770 };
 771
 772 #define FW_CMD_WR_DMA_S         17
 773 #define FW_CMD_WR_DMA_V(x)      ((x) << FW_CMD_WR_DMA_S)
 774
 775 struct fw_eth_tx_pkt_vm_wr {
 776         __be32 op_immdlen;
 777         __be32 equiq_to_len16;
 778         __be32 r3[2];
 779         u8 ethmacdst[6];
 780         u8 ethmacsrc[6];
 781         __be16 ethtype;
 782         __be16 vlantci;
 783 };
 784
 785 #define FW_CMD_MAX_TIMEOUT 10000
 786
 787 /*
 788  * If a host driver does a HELLO and discovers that there's already a MASTER
 789  * selected, we may have to wait for that MASTER to finish issuing RESET,
 790  * configuration and INITIALIZE commands.  Also, there's a possibility that
 791  * our own HELLO may get lost if it happens right as the MASTER is issuign a
 792  * RESET command, so we need to be willing to make a few retries of our HELLO.
 793  */
 794 #define FW_CMD_HELLO_TIMEOUT    (3 * FW_CMD_MAX_TIMEOUT)
 795 #define FW_CMD_HELLO_RETRIES    3
 796
 797
 798 enum fw_cmd_opcodes {
 799         FW_LDST_CMD                    = 0x01,
 800         FW_RESET_CMD                   = 0x03,
 801         FW_HELLO_CMD                   = 0x04,
 802         FW_BYE_CMD                     = 0x05,
 803         FW_INITIALIZE_CMD              = 0x06,
 804         FW_CAPS_CONFIG_CMD             = 0x07,
 805         FW_PARAMS_CMD                  = 0x08,
 806         FW_PFVF_CMD                    = 0x09,
 807         FW_IQ_CMD                      = 0x10,
 808         FW_EQ_MNGT_CMD                 = 0x11,
 809         FW_EQ_ETH_CMD                  = 0x12,
 810         FW_EQ_CTRL_CMD                 = 0x13,
 811         FW_EQ_OFLD_CMD                 = 0x21,
 812         FW_VI_CMD                      = 0x14,
 813         FW_VI_MAC_CMD                  = 0x15,
 814         FW_VI_RXMODE_CMD               = 0x16,
 815         FW_VI_ENABLE_CMD               = 0x17,
 816         FW_ACL_MAC_CMD                 = 0x18,
 817         FW_ACL_VLAN_CMD                = 0x19,
 818         FW_VI_STATS_CMD                = 0x1a,
 819         FW_PORT_CMD                    = 0x1b,
 820         FW_PORT_STATS_CMD              = 0x1c,
 821         FW_PORT_LB_STATS_CMD           = 0x1d,
 822         FW_PORT_TRACE_CMD              = 0x1e,
 823         FW_PORT_TRACE_MMAP_CMD         = 0x1f,
 824         FW_RSS_IND_TBL_CMD             = 0x20,
 825         FW_RSS_GLB_CONFIG_CMD          = 0x22,
 826         FW_RSS_VI_CONFIG_CMD           = 0x23,
 827         FW_SCHED_CMD                   = 0x24,
 828         FW_DEVLOG_CMD                  = 0x25,
 829         FW_CLIP_CMD                    = 0x28,
 830         FW_PTP_CMD                     = 0x3e,
 831         FW_HMA_CMD                     = 0x3f,
 832         FW_LASTC2E_CMD                 = 0x40,
 833         FW_ERROR_CMD                   = 0x80,
 834         FW_DEBUG_CMD                   = 0x81,
 835 };
 836
 837 enum fw_cmd_cap {
 838         FW_CMD_CAP_PF                  = 0x01,
 839         FW_CMD_CAP_DMAQ                = 0x02,
 840         FW_CMD_CAP_PORT                = 0x04,
 841         FW_CMD_CAP_PORTPROMISC         = 0x08,
 842         FW_CMD_CAP_PORTSTATS           = 0x10,
 843         FW_CMD_CAP_VF                  = 0x80,
 844 };
 845
 846 /*
 847  * Generic command header flit0
 848  */
 849 struct fw_cmd_hdr {
 850         __be32 hi;
 851         __be32 lo;
 852 };
 853
 854 #define FW_CMD_OP_S             24
 855 #define FW_CMD_OP_M             0xff
 856 #define FW_CMD_OP_V(x)          ((x) << FW_CMD_OP_S)
 857 #define FW_CMD_OP_G(x)          (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
 858
 859 #define FW_CMD_REQUEST_S        23
 860 #define FW_CMD_REQUEST_V(x)     ((x) << FW_CMD_REQUEST_S)
 861 #define FW_CMD_REQUEST_F        FW_CMD_REQUEST_V(1U)
 862
 863 #define FW_CMD_READ_S           22
 864 #define FW_CMD_READ_V(x)        ((x) << FW_CMD_READ_S)
 865 #define FW_CMD_READ_F           FW_CMD_READ_V(1U)
 866
 867 #define FW_CMD_WRITE_S          21
 868 #define FW_CMD_WRITE_V(x)       ((x) << FW_CMD_WRITE_S)
 869 #define FW_CMD_WRITE_F          FW_CMD_WRITE_V(1U)
 870
 871 #define FW_CMD_EXEC_S           20
 872 #define FW_CMD_EXEC_V(x)        ((x) << FW_CMD_EXEC_S)
 873 #define FW_CMD_EXEC_F           FW_CMD_EXEC_V(1U)
 874
 875 #define FW_CMD_RAMASK_S         20
 876 #define FW_CMD_RAMASK_V(x)      ((x) << FW_CMD_RAMASK_S)
 877
 878 #define FW_CMD_RETVAL_S         8
 879 #define FW_CMD_RETVAL_M         0xff
 880 #define FW_CMD_RETVAL_V(x)      ((x) << FW_CMD_RETVAL_S)
 881 #define FW_CMD_RETVAL_G(x)      (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
 882
 883 #define FW_CMD_LEN16_S          0
 884 #define FW_CMD_LEN16_V(x)       ((x) << FW_CMD_LEN16_S)
 885
 886 #define FW_LEN16(fw_struct)     FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
 887
 888 enum fw_ldst_addrspc {
 889         FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
 890         FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
 891         FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
 892         FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
 893         FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
 894         FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
 895         FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
 896         FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
 897         FW_LDST_ADDRSPC_MDIO      = 0x0018,
 898         FW_LDST_ADDRSPC_MPS       = 0x0020,
 899         FW_LDST_ADDRSPC_FUNC      = 0x0028,
 900         FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
 901         FW_LDST_ADDRSPC_I2C       = 0x0038,
 902 };
 903
 904 enum fw_ldst_mps_fid {
 905         FW_LDST_MPS_ATRB,
 906         FW_LDST_MPS_RPLC
 907 };
 908
 909 enum fw_ldst_func_access_ctl {
 910         FW_LDST_FUNC_ACC_CTL_VIID,
 911         FW_LDST_FUNC_ACC_CTL_FID
 912 };
 913
 914 enum fw_ldst_func_mod_index {
 915         FW_LDST_FUNC_MPS
 916 };
 917
 918 struct fw_ldst_cmd {
 919         __be32 op_to_addrspace;
 920         __be32 cycles_to_len16;
 921         union fw_ldst {
 922                 struct fw_ldst_addrval {
 923                         __be32 addr;
 924                         __be32 val;
 925                 } addrval;
 926                 struct fw_ldst_idctxt {
 927                         __be32 physid;
 928                         __be32 msg_ctxtflush;
 929                         __be32 ctxt_data7;
 930                         __be32 ctxt_data6;
 931                         __be32 ctxt_data5;
 932                         __be32 ctxt_data4;
 933                         __be32 ctxt_data3;
 934                         __be32 ctxt_data2;
 935                         __be32 ctxt_data1;
 936                         __be32 ctxt_data0;
 937                 } idctxt;
 938                 struct fw_ldst_mdio {
 939                         __be16 paddr_mmd;
 940                         __be16 raddr;
 941                         __be16 vctl;
 942                         __be16 rval;
 943                 } mdio;
 944                 struct fw_ldst_cim_rq {
 945                         u8 req_first64[8];
 946                         u8 req_second64[8];
 947                         u8 resp_first64[8];
 948                         u8 resp_second64[8];
 949                         __be32 r3[2];
 950                 } cim_rq;
 951                 union fw_ldst_mps {
 952                         struct fw_ldst_mps_rplc {
 953                                 __be16 fid_idx;
 954                                 __be16 rplcpf_pkd;
 955                                 __be32 rplc255_224;
 956                                 __be32 rplc223_192;
 957                                 __be32 rplc191_160;
 958                                 __be32 rplc159_128;
 959                                 __be32 rplc127_96;
 960                                 __be32 rplc95_64;
 961                                 __be32 rplc63_32;
 962                                 __be32 rplc31_0;
 963                         } rplc;
 964                         struct fw_ldst_mps_atrb {
 965                                 __be16 fid_mpsid;
 966                                 __be16 r2[3];
 967                                 __be32 r3[2];
 968                                 __be32 r4;
 969                                 __be32 atrb;
 970                                 __be16 vlan[16];
 971                         } atrb;
 972                 } mps;
 973                 struct fw_ldst_func {
 974                         u8 access_ctl;
 975                         u8 mod_index;
 976                         __be16 ctl_id;
 977                         __be32 offset;
 978                         __be64 data0;
 979                         __be64 data1;
 980                 } func;
 981                 struct fw_ldst_pcie {
 982                         u8 ctrl_to_fn;
 983                         u8 bnum;
 984                         u8 r;
 985                         u8 ext_r;
 986                         u8 select_naccess;
 987                         u8 pcie_fn;
 988                         __be16 nset_pkd;
 989                         __be32 data[12];
 990                 } pcie;
 991                 struct fw_ldst_i2c_deprecated {
 992                         u8 pid_pkd;
 993                         u8 base;
 994                         u8 boffset;
 995                         u8 data;
 996                         __be32 r9;
 997                 } i2c_deprecated;
 998                 struct fw_ldst_i2c {
 999                         u8 pid;
1000                         u8 did;
1001                         u8 boffset;
1002                         u8 blen;
1003                         __be32 r9;
1004                         __u8   data[48];
1005                 } i2c;
1006                 struct fw_ldst_le {
1007                         __be32 index;
1008                         __be32 r9;
1009                         u8 val[33];
1010                         u8 r11[7];
1011                 } le;
1012         } u;
1013 };
1014
1015 #define FW_LDST_CMD_ADDRSPACE_S         0
1016 #define FW_LDST_CMD_ADDRSPACE_V(x)      ((x) << FW_LDST_CMD_ADDRSPACE_S)
1017
1018 #define FW_LDST_CMD_MSG_S       31
1019 #define FW_LDST_CMD_MSG_V(x)    ((x) << FW_LDST_CMD_MSG_S)
1020
1021 #define FW_LDST_CMD_CTXTFLUSH_S         30
1022 #define FW_LDST_CMD_CTXTFLUSH_V(x)      ((x) << FW_LDST_CMD_CTXTFLUSH_S)
1023 #define FW_LDST_CMD_CTXTFLUSH_F         FW_LDST_CMD_CTXTFLUSH_V(1U)
1024
1025 #define FW_LDST_CMD_PADDR_S     8
1026 #define FW_LDST_CMD_PADDR_V(x)  ((x) << FW_LDST_CMD_PADDR_S)
1027
1028 #define FW_LDST_CMD_MMD_S       0
1029 #define FW_LDST_CMD_MMD_V(x)    ((x) << FW_LDST_CMD_MMD_S)
1030
1031 #define FW_LDST_CMD_FID_S       15
1032 #define FW_LDST_CMD_FID_V(x)    ((x) << FW_LDST_CMD_FID_S)
1033
1034 #define FW_LDST_CMD_IDX_S       0
1035 #define FW_LDST_CMD_IDX_V(x)    ((x) << FW_LDST_CMD_IDX_S)
1036
1037 #define FW_LDST_CMD_RPLCPF_S    0
1038 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
1039
1040 #define FW_LDST_CMD_LC_S        4
1041 #define FW_LDST_CMD_LC_V(x)     ((x) << FW_LDST_CMD_LC_S)
1042 #define FW_LDST_CMD_LC_F        FW_LDST_CMD_LC_V(1U)
1043
1044 #define FW_LDST_CMD_FN_S        0
1045 #define FW_LDST_CMD_FN_V(x)     ((x) << FW_LDST_CMD_FN_S)
1046
1047 #define FW_LDST_CMD_NACCESS_S           0
1048 #define FW_LDST_CMD_NACCESS_V(x)        ((x) << FW_LDST_CMD_NACCESS_S)
1049
1050 struct fw_reset_cmd {
1051         __be32 op_to_write;
1052         __be32 retval_len16;
1053         __be32 val;
1054         __be32 halt_pkd;
1055 };
1056
1057 #define FW_RESET_CMD_HALT_S     31
1058 #define FW_RESET_CMD_HALT_M     0x1
1059 #define FW_RESET_CMD_HALT_V(x)  ((x) << FW_RESET_CMD_HALT_S)
1060 #define FW_RESET_CMD_HALT_G(x)  \
1061         (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
1062 #define FW_RESET_CMD_HALT_F     FW_RESET_CMD_HALT_V(1U)
1063
1064 enum fw_hellow_cmd {
1065         fw_hello_cmd_stage_os           = 0x0
1066 };
1067
1068 struct fw_hello_cmd {
1069         __be32 op_to_write;
1070         __be32 retval_len16;
1071         __be32 err_to_clearinit;
1072         __be32 fwrev;
1073 };
1074
1075 #define FW_HELLO_CMD_ERR_S      31
1076 #define FW_HELLO_CMD_ERR_V(x)   ((x) << FW_HELLO_CMD_ERR_S)
1077 #define FW_HELLO_CMD_ERR_F      FW_HELLO_CMD_ERR_V(1U)
1078
1079 #define FW_HELLO_CMD_INIT_S     30
1080 #define FW_HELLO_CMD_INIT_V(x)  ((x) << FW_HELLO_CMD_INIT_S)
1081 #define FW_HELLO_CMD_INIT_F     FW_HELLO_CMD_INIT_V(1U)
1082
1083 #define FW_HELLO_CMD_MASTERDIS_S        29
1084 #define FW_HELLO_CMD_MASTERDIS_V(x)     ((x) << FW_HELLO_CMD_MASTERDIS_S)
1085
1086 #define FW_HELLO_CMD_MASTERFORCE_S      28
1087 #define FW_HELLO_CMD_MASTERFORCE_V(x)   ((x) << FW_HELLO_CMD_MASTERFORCE_S)
1088
1089 #define FW_HELLO_CMD_MBMASTER_S         24
1090 #define FW_HELLO_CMD_MBMASTER_M         0xfU
1091 #define FW_HELLO_CMD_MBMASTER_V(x)      ((x) << FW_HELLO_CMD_MBMASTER_S)
1092 #define FW_HELLO_CMD_MBMASTER_G(x)      \
1093         (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
1094
1095 #define FW_HELLO_CMD_MBASYNCNOTINT_S    23
1096 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
1097
1098 #define FW_HELLO_CMD_MBASYNCNOT_S       20
1099 #define FW_HELLO_CMD_MBASYNCNOT_V(x)    ((x) << FW_HELLO_CMD_MBASYNCNOT_S)
1100
1101 #define FW_HELLO_CMD_STAGE_S            17
1102 #define FW_HELLO_CMD_STAGE_V(x)         ((x) << FW_HELLO_CMD_STAGE_S)
1103
1104 #define FW_HELLO_CMD_CLEARINIT_S        16
1105 #define FW_HELLO_CMD_CLEARINIT_V(x)     ((x) << FW_HELLO_CMD_CLEARINIT_S)
1106 #define FW_HELLO_CMD_CLEARINIT_F        FW_HELLO_CMD_CLEARINIT_V(1U)
1107
1108 struct fw_bye_cmd {
1109         __be32 op_to_write;
1110         __be32 retval_len16;
1111         __be64 r3;
1112 };
1113
1114 struct fw_initialize_cmd {
1115         __be32 op_to_write;
1116         __be32 retval_len16;
1117         __be64 r3;
1118 };
1119
1120 enum fw_caps_config_hm {
1121         FW_CAPS_CONFIG_HM_PCIE          = 0x00000001,
1122         FW_CAPS_CONFIG_HM_PL            = 0x00000002,
1123         FW_CAPS_CONFIG_HM_SGE           = 0x00000004,
1124         FW_CAPS_CONFIG_HM_CIM           = 0x00000008,
1125         FW_CAPS_CONFIG_HM_ULPTX         = 0x00000010,
1126         FW_CAPS_CONFIG_HM_TP            = 0x00000020,
1127         FW_CAPS_CONFIG_HM_ULPRX         = 0x00000040,
1128         FW_CAPS_CONFIG_HM_PMRX          = 0x00000080,
1129         FW_CAPS_CONFIG_HM_PMTX          = 0x00000100,
1130         FW_CAPS_CONFIG_HM_MC            = 0x00000200,
1131         FW_CAPS_CONFIG_HM_LE            = 0x00000400,
1132         FW_CAPS_CONFIG_HM_MPS           = 0x00000800,
1133         FW_CAPS_CONFIG_HM_XGMAC         = 0x00001000,
1134         FW_CAPS_CONFIG_HM_CPLSWITCH     = 0x00002000,
1135         FW_CAPS_CONFIG_HM_T4DBG         = 0x00004000,
1136         FW_CAPS_CONFIG_HM_MI            = 0x00008000,
1137         FW_CAPS_CONFIG_HM_I2CM          = 0x00010000,
1138         FW_CAPS_CONFIG_HM_NCSI          = 0x00020000,
1139         FW_CAPS_CONFIG_HM_SMB           = 0x00040000,
1140         FW_CAPS_CONFIG_HM_MA            = 0x00080000,
1141         FW_CAPS_CONFIG_HM_EDRAM         = 0x00100000,
1142         FW_CAPS_CONFIG_HM_PMU           = 0x00200000,
1143         FW_CAPS_CONFIG_HM_UART          = 0x00400000,
1144         FW_CAPS_CONFIG_HM_SF            = 0x00800000,
1145 };
1146
1147 enum fw_caps_config_nbm {
1148         FW_CAPS_CONFIG_NBM_IPMI         = 0x00000001,
1149         FW_CAPS_CONFIG_NBM_NCSI         = 0x00000002,
1150 };
1151
1152 enum fw_caps_config_link {
1153         FW_CAPS_CONFIG_LINK_PPP         = 0x00000001,
1154         FW_CAPS_CONFIG_LINK_QFC         = 0x00000002,
1155         FW_CAPS_CONFIG_LINK_DCBX        = 0x00000004,
1156 };
1157
1158 enum fw_caps_config_switch {
1159         FW_CAPS_CONFIG_SWITCH_INGRESS   = 0x00000001,
1160         FW_CAPS_CONFIG_SWITCH_EGRESS    = 0x00000002,
1161 };
1162
1163 enum fw_caps_config_nic {
1164         FW_CAPS_CONFIG_NIC              = 0x00000001,
1165         FW_CAPS_CONFIG_NIC_VM           = 0x00000002,
1166         FW_CAPS_CONFIG_NIC_HASHFILTER   = 0x00000020,
1167         FW_CAPS_CONFIG_NIC_ETHOFLD      = 0x00000040,
1168 };
1169
1170 enum fw_caps_config_ofld {
1171         FW_CAPS_CONFIG_OFLD             = 0x00000001,
1172 };
1173
1174 enum fw_caps_config_rdma {
1175         FW_CAPS_CONFIG_RDMA_RDDP        = 0x00000001,
1176         FW_CAPS_CONFIG_RDMA_RDMAC       = 0x00000002,
1177 };
1178
1179 enum fw_caps_config_iscsi {
1180         FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
1181         FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
1182         FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
1183         FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
1184 };
1185
1186 enum fw_caps_config_crypto {
1187         FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
1188         FW_CAPS_CONFIG_TLS_INLINE = 0x00000002,
1189         FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004,
1190 };
1191
1192 enum fw_caps_config_fcoe {
1193         FW_CAPS_CONFIG_FCOE_INITIATOR   = 0x00000001,
1194         FW_CAPS_CONFIG_FCOE_TARGET      = 0x00000002,
1195         FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
1196 };
1197
1198 enum fw_memtype_cf {
1199         FW_MEMTYPE_CF_EDC0              = 0x0,
1200         FW_MEMTYPE_CF_EDC1              = 0x1,
1201         FW_MEMTYPE_CF_EXTMEM            = 0x2,
1202         FW_MEMTYPE_CF_FLASH             = 0x4,
1203         FW_MEMTYPE_CF_INTERNAL          = 0x5,
1204         FW_MEMTYPE_CF_EXTMEM1           = 0x6,
1205         FW_MEMTYPE_CF_HMA               = 0x7,
1206 };
1207
1208 struct fw_caps_config_cmd {
1209         __be32 op_to_write;
1210         __be32 cfvalid_to_len16;
1211         __be32 r2;
1212         __be32 hwmbitmap;
1213         __be16 nbmcaps;
1214         __be16 linkcaps;
1215         __be16 switchcaps;
1216         __be16 r3;
1217         __be16 niccaps;
1218         __be16 ofldcaps;
1219         __be16 rdmacaps;
1220         __be16 cryptocaps;
1221         __be16 iscsicaps;
1222         __be16 fcoecaps;
1223         __be32 cfcsum;
1224         __be32 finiver;
1225         __be32 finicsum;
1226 };
1227
1228 #define FW_CAPS_CONFIG_CMD_CFVALID_S    27
1229 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1230 #define FW_CAPS_CONFIG_CMD_CFVALID_F    FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1231
1232 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S         24
1233 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x)      \
1234         ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1235
1236 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S      16
1237 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x)   \
1238         ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1239
1240 /*
1241  * params command mnemonics
1242  */
1243 enum fw_params_mnem {
1244         FW_PARAMS_MNEM_DEV              = 1,    /* device params */
1245         FW_PARAMS_MNEM_PFVF             = 2,    /* function params */
1246         FW_PARAMS_MNEM_REG              = 3,    /* limited register access */
1247         FW_PARAMS_MNEM_DMAQ             = 4,    /* dma queue params */
1248         FW_PARAMS_MNEM_CHNET            = 5,    /* chnet params */
1249         FW_PARAMS_MNEM_LAST
1250 };
1251
1252 /*
1253  * device parameters
1254  */
1255
1256 #define FW_PARAMS_PARAM_FILTER_MODE_S 16
1257 #define FW_PARAMS_PARAM_FILTER_MODE_M 0xffff
1258 #define FW_PARAMS_PARAM_FILTER_MODE_V(x)          \
1259         ((x) << FW_PARAMS_PARAM_FILTER_MODE_S)
1260 #define FW_PARAMS_PARAM_FILTER_MODE_G(x)          \
1261         (((x) >> FW_PARAMS_PARAM_FILTER_MODE_S) & \
1262         FW_PARAMS_PARAM_FILTER_MODE_M)
1263
1264 #define FW_PARAMS_PARAM_FILTER_MASK_S 0
1265 #define FW_PARAMS_PARAM_FILTER_MASK_M 0xffff
1266 #define FW_PARAMS_PARAM_FILTER_MASK_V(x)          \
1267         ((x) << FW_PARAMS_PARAM_FILTER_MASK_S)
1268 #define FW_PARAMS_PARAM_FILTER_MASK_G(x)          \
1269         (((x) >> FW_PARAMS_PARAM_FILTER_MASK_S) & \
1270         FW_PARAMS_PARAM_FILTER_MASK_M)
1271
1272 enum fw_params_param_dev {
1273         FW_PARAMS_PARAM_DEV_CCLK        = 0x00, /* chip core clock in khz */
1274         FW_PARAMS_PARAM_DEV_PORTVEC     = 0x01, /* the port vector */
1275         FW_PARAMS_PARAM_DEV_NTID        = 0x02, /* reads the number of TIDs
1276                                                  * allocated by the device's
1277                                                  * Lookup Engine
1278                                                  */
1279         FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1280         FW_PARAMS_PARAM_DEV_INTVER_NIC  = 0x04,
1281         FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1282         FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1283         FW_PARAMS_PARAM_DEV_INTVER_RI   = 0x07,
1284         FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1285         FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1286         FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1287         FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1288         FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1289         FW_PARAMS_PARAM_DEV_CF = 0x0D,
1290         FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
1291         FW_PARAMS_PARAM_DEV_DIAG = 0x11,
1292         FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1293         FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1294         FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1295         FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
1296         FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A,
1297         FW_PARAMS_PARAM_DEV_VPDREV = 0x1B,
1298         FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR  = 0x1C,
1299         FW_PARAMS_PARAM_DEV_FILTER2_WR  = 0x1D,
1300         FW_PARAMS_PARAM_DEV_MPSBGMAP    = 0x1E,
1301         FW_PARAMS_PARAM_DEV_TPCHMAP     = 0x1F,
1302         FW_PARAMS_PARAM_DEV_HMA_SIZE    = 0x20,
1303         FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21,
1304         FW_PARAMS_PARAM_DEV_PPOD_EDRAM  = 0x23,
1305         FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR    = 0x24,
1306         FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27,
1307         FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28,
1308         FW_PARAMS_PARAM_DEV_DBQ_TIMER   = 0x29,
1309         FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A,
1310         FW_PARAMS_PARAM_DEV_NUM_TM_CLASS = 0x2B,
1311         FW_PARAMS_PARAM_DEV_FILTER = 0x2E,
1312 };
1313
1314 /*
1315  * physical and virtual function parameters
1316  */
1317 enum fw_params_param_pfvf {
1318         FW_PARAMS_PARAM_PFVF_RWXCAPS    = 0x00,
1319         FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1320         FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1321         FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1322         FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1323         FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1324         FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1325         FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1326         FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1327         FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1328         FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1329         FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1330         FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1331         FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1332         FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1333         FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1334         FW_PARAMS_PARAM_PFVF_RQ_END     = 0x10,
1335         FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1336         FW_PARAMS_PARAM_PFVF_PBL_END    = 0x12,
1337         FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1338         FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1339         FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1340         FW_PARAMS_PARAM_PFVF_SQRQ_END   = 0x16,
1341         FW_PARAMS_PARAM_PFVF_CQ_START   = 0x17,
1342         FW_PARAMS_PARAM_PFVF_CQ_END     = 0x18,
1343         FW_PARAMS_PARAM_PFVF_SRQ_START  = 0x19,
1344         FW_PARAMS_PARAM_PFVF_SRQ_END    = 0x1A,
1345         FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1346         FW_PARAMS_PARAM_PFVF_VIID       = 0x24,
1347         FW_PARAMS_PARAM_PFVF_CPMASK     = 0x25,
1348         FW_PARAMS_PARAM_PFVF_OCQ_START  = 0x26,
1349         FW_PARAMS_PARAM_PFVF_OCQ_END    = 0x27,
1350         FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
1351         FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1352         FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1353         FW_PARAMS_PARAM_PFVF_EQ_START   = 0x2B,
1354         FW_PARAMS_PARAM_PFVF_EQ_END     = 0x2C,
1355         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1356         FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1357         FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
1358         FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1359         FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
1360         FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,
1361         FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
1362         FW_PARAMS_PARAM_PFVF_TLS_START = 0x34,
1363         FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
1364         FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36,
1365         FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
1366         FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
1367         FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A,
1368         FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B,
1369         FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C,
1370         FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40,
1371 };
1372
1373 /* Virtual link state as seen by the specified VF */
1374 enum vf_link_states {
1375         FW_VF_LINK_STATE_AUTO           = 0x00,
1376         FW_VF_LINK_STATE_ENABLE         = 0x01,
1377         FW_VF_LINK_STATE_DISABLE        = 0x02,
1378 };
1379
1380 /*
1381  * dma queue parameters
1382  */
1383 enum fw_params_param_dmaq {
1384         FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1385         FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1386         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1387         FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1388         FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1389         FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1390         FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX = 0x15,
1391         FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
1392 };
1393
1394 enum fw_params_param_dev_phyfw {
1395         FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
1396         FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
1397 };
1398
1399 enum fw_params_param_dev_diag {
1400         FW_PARAM_DEV_DIAG_TMP           = 0x00,
1401         FW_PARAM_DEV_DIAG_VDD           = 0x01,
1402         FW_PARAM_DEV_DIAG_MAXTMPTHRESH  = 0x02,
1403 };
1404
1405 enum fw_params_param_dev_filter {
1406         FW_PARAM_DEV_FILTER_VNIC_MODE   = 0x00,
1407         FW_PARAM_DEV_FILTER_MODE_MASK   = 0x01,
1408 };
1409
1410 enum fw_params_param_dev_fwcache {
1411         FW_PARAM_DEV_FWCACHE_FLUSH      = 0x00,
1412         FW_PARAM_DEV_FWCACHE_FLUSHINV   = 0x01,
1413 };
1414
1415 #define FW_PARAMS_MNEM_S        24
1416 #define FW_PARAMS_MNEM_V(x)     ((x) << FW_PARAMS_MNEM_S)
1417
1418 #define FW_PARAMS_PARAM_X_S     16
1419 #define FW_PARAMS_PARAM_X_V(x)  ((x) << FW_PARAMS_PARAM_X_S)
1420
1421 #define FW_PARAMS_PARAM_Y_S     8
1422 #define FW_PARAMS_PARAM_Y_M     0xffU
1423 #define FW_PARAMS_PARAM_Y_V(x)  ((x) << FW_PARAMS_PARAM_Y_S)
1424 #define FW_PARAMS_PARAM_Y_G(x)  (((x) >> FW_PARAMS_PARAM_Y_S) &\
1425                 FW_PARAMS_PARAM_Y_M)
1426
1427 #define FW_PARAMS_PARAM_Z_S     0
1428 #define FW_PARAMS_PARAM_Z_M     0xffu
1429 #define FW_PARAMS_PARAM_Z_V(x)  ((x) << FW_PARAMS_PARAM_Z_S)
1430 #define FW_PARAMS_PARAM_Z_G(x)  (((x) >> FW_PARAMS_PARAM_Z_S) &\
1431                 FW_PARAMS_PARAM_Z_M)
1432
1433 #define FW_PARAMS_PARAM_XYZ_S           0
1434 #define FW_PARAMS_PARAM_XYZ_V(x)        ((x) << FW_PARAMS_PARAM_XYZ_S)
1435
1436 #define FW_PARAMS_PARAM_YZ_S            0
1437 #define FW_PARAMS_PARAM_YZ_V(x)         ((x) << FW_PARAMS_PARAM_YZ_S)
1438
1439 struct fw_params_cmd {
1440         __be32 op_to_vfn;
1441         __be32 retval_len16;
1442         struct fw_params_param {
1443                 __be32 mnem;
1444                 __be32 val;
1445         } param[7];
1446 };
1447
1448 #define FW_PARAMS_CMD_PFN_S     8
1449 #define FW_PARAMS_CMD_PFN_V(x)  ((x) << FW_PARAMS_CMD_PFN_S)
1450
1451 #define FW_PARAMS_CMD_VFN_S     0
1452 #define FW_PARAMS_CMD_VFN_V(x)  ((x) << FW_PARAMS_CMD_VFN_S)
1453
1454 struct fw_pfvf_cmd {
1455         __be32 op_to_vfn;
1456         __be32 retval_len16;
1457         __be32 niqflint_niq;
1458         __be32 type_to_neq;
1459         __be32 tc_to_nexactf;
1460         __be32 r_caps_to_nethctrl;
1461         __be16 nricq;
1462         __be16 nriqp;
1463         __be32 r4;
1464 };
1465
1466 #define FW_PFVF_CMD_PFN_S       8
1467 #define FW_PFVF_CMD_PFN_V(x)    ((x) << FW_PFVF_CMD_PFN_S)
1468
1469 #define FW_PFVF_CMD_VFN_S       0
1470 #define FW_PFVF_CMD_VFN_V(x)    ((x) << FW_PFVF_CMD_VFN_S)
1471
1472 #define FW_PFVF_CMD_NIQFLINT_S          20
1473 #define FW_PFVF_CMD_NIQFLINT_M          0xfff
1474 #define FW_PFVF_CMD_NIQFLINT_V(x)       ((x) << FW_PFVF_CMD_NIQFLINT_S)
1475 #define FW_PFVF_CMD_NIQFLINT_G(x)       \
1476         (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1477
1478 #define FW_PFVF_CMD_NIQ_S       0
1479 #define FW_PFVF_CMD_NIQ_M       0xfffff
1480 #define FW_PFVF_CMD_NIQ_V(x)    ((x) << FW_PFVF_CMD_NIQ_S)
1481 #define FW_PFVF_CMD_NIQ_G(x)    \
1482         (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1483
1484 #define FW_PFVF_CMD_TYPE_S      31
1485 #define FW_PFVF_CMD_TYPE_M      0x1
1486 #define FW_PFVF_CMD_TYPE_V(x)   ((x) << FW_PFVF_CMD_TYPE_S)
1487 #define FW_PFVF_CMD_TYPE_G(x)   \
1488         (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1489 #define FW_PFVF_CMD_TYPE_F      FW_PFVF_CMD_TYPE_V(1U)
1490
1491 #define FW_PFVF_CMD_CMASK_S     24
1492 #define FW_PFVF_CMD_CMASK_M     0xf
1493 #define FW_PFVF_CMD_CMASK_V(x)  ((x) << FW_PFVF_CMD_CMASK_S)
1494 #define FW_PFVF_CMD_CMASK_G(x)  \
1495         (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1496
1497 #define FW_PFVF_CMD_PMASK_S     20
1498 #define FW_PFVF_CMD_PMASK_M     0xf
1499 #define FW_PFVF_CMD_PMASK_V(x)  ((x) << FW_PFVF_CMD_PMASK_S)
1500 #define FW_PFVF_CMD_PMASK_G(x) \
1501         (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1502
1503 #define FW_PFVF_CMD_NEQ_S       0
1504 #define FW_PFVF_CMD_NEQ_M       0xfffff
1505 #define FW_PFVF_CMD_NEQ_V(x)    ((x) << FW_PFVF_CMD_NEQ_S)
1506 #define FW_PFVF_CMD_NEQ_G(x)    \
1507         (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1508
1509 #define FW_PFVF_CMD_TC_S        24
1510 #define FW_PFVF_CMD_TC_M        0xff
1511 #define FW_PFVF_CMD_TC_V(x)     ((x) << FW_PFVF_CMD_TC_S)
1512 #define FW_PFVF_CMD_TC_G(x)     (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1513
1514 #define FW_PFVF_CMD_NVI_S       16
1515 #define FW_PFVF_CMD_NVI_M       0xff
1516 #define FW_PFVF_CMD_NVI_V(x)    ((x) << FW_PFVF_CMD_NVI_S)
1517 #define FW_PFVF_CMD_NVI_G(x)    (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1518
1519 #define FW_PFVF_CMD_NEXACTF_S           0
1520 #define FW_PFVF_CMD_NEXACTF_M           0xffff
1521 #define FW_PFVF_CMD_NEXACTF_V(x)        ((x) << FW_PFVF_CMD_NEXACTF_S)
1522 #define FW_PFVF_CMD_NEXACTF_G(x)        \
1523         (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1524
1525 #define FW_PFVF_CMD_R_CAPS_S    24
1526 #define FW_PFVF_CMD_R_CAPS_M    0xff
1527 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1528 #define FW_PFVF_CMD_R_CAPS_G(x) \
1529         (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1530
1531 #define FW_PFVF_CMD_WX_CAPS_S           16
1532 #define FW_PFVF_CMD_WX_CAPS_M           0xff
1533 #define FW_PFVF_CMD_WX_CAPS_V(x)        ((x) << FW_PFVF_CMD_WX_CAPS_S)
1534 #define FW_PFVF_CMD_WX_CAPS_G(x)        \
1535         (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1536
1537 #define FW_PFVF_CMD_NETHCTRL_S          0
1538 #define FW_PFVF_CMD_NETHCTRL_M          0xffff
1539 #define FW_PFVF_CMD_NETHCTRL_V(x)       ((x) << FW_PFVF_CMD_NETHCTRL_S)
1540 #define FW_PFVF_CMD_NETHCTRL_G(x)       \
1541         (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1542
1543 enum fw_iq_type {
1544         FW_IQ_TYPE_FL_INT_CAP,
1545         FW_IQ_TYPE_NO_FL_INT_CAP
1546 };
1547
1548 enum fw_iq_iqtype {
1549         FW_IQ_IQTYPE_OTHER,
1550         FW_IQ_IQTYPE_NIC,
1551         FW_IQ_IQTYPE_OFLD,
1552 };
1553
1554 struct fw_iq_cmd {
1555         __be32 op_to_vfn;
1556         __be32 alloc_to_len16;
1557         __be16 physiqid;
1558         __be16 iqid;
1559         __be16 fl0id;
1560         __be16 fl1id;
1561         __be32 type_to_iqandstindex;
1562         __be16 iqdroprss_to_iqesize;
1563         __be16 iqsize;
1564         __be64 iqaddr;
1565         __be32 iqns_to_fl0congen;
1566         __be16 fl0dcaen_to_fl0cidxfthresh;
1567         __be16 fl0size;
1568         __be64 fl0addr;
1569         __be32 fl1cngchmap_to_fl1congen;
1570         __be16 fl1dcaen_to_fl1cidxfthresh;
1571         __be16 fl1size;
1572         __be64 fl1addr;
1573 };
1574
1575 #define FW_IQ_CMD_PFN_S         8
1576 #define FW_IQ_CMD_PFN_V(x)      ((x) << FW_IQ_CMD_PFN_S)
1577
1578 #define FW_IQ_CMD_VFN_S         0
1579 #define FW_IQ_CMD_VFN_V(x)      ((x) << FW_IQ_CMD_VFN_S)
1580
1581 #define FW_IQ_CMD_ALLOC_S       31
1582 #define FW_IQ_CMD_ALLOC_V(x)    ((x) << FW_IQ_CMD_ALLOC_S)
1583 #define FW_IQ_CMD_ALLOC_F       FW_IQ_CMD_ALLOC_V(1U)
1584
1585 #define FW_IQ_CMD_FREE_S        30
1586 #define FW_IQ_CMD_FREE_V(x)     ((x) << FW_IQ_CMD_FREE_S)
1587 #define FW_IQ_CMD_FREE_F        FW_IQ_CMD_FREE_V(1U)
1588
1589 #define FW_IQ_CMD_MODIFY_S      29
1590 #define FW_IQ_CMD_MODIFY_V(x)   ((x) << FW_IQ_CMD_MODIFY_S)
1591 #define FW_IQ_CMD_MODIFY_F      FW_IQ_CMD_MODIFY_V(1U)
1592
1593 #define FW_IQ_CMD_IQSTART_S     28
1594 #define FW_IQ_CMD_IQSTART_V(x)  ((x) << FW_IQ_CMD_IQSTART_S)
1595 #define FW_IQ_CMD_IQSTART_F     FW_IQ_CMD_IQSTART_V(1U)
1596
1597 #define FW_IQ_CMD_IQSTOP_S      27
1598 #define FW_IQ_CMD_IQSTOP_V(x)   ((x) << FW_IQ_CMD_IQSTOP_S)
1599 #define FW_IQ_CMD_IQSTOP_F      FW_IQ_CMD_IQSTOP_V(1U)
1600
1601 #define FW_IQ_CMD_TYPE_S        29
1602 #define FW_IQ_CMD_TYPE_V(x)     ((x) << FW_IQ_CMD_TYPE_S)
1603
1604 #define FW_IQ_CMD_IQASYNCH_S    28
1605 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)
1606
1607 #define FW_IQ_CMD_VIID_S        16
1608 #define FW_IQ_CMD_VIID_V(x)     ((x) << FW_IQ_CMD_VIID_S)
1609
1610 #define FW_IQ_CMD_IQANDST_S     15
1611 #define FW_IQ_CMD_IQANDST_V(x)  ((x) << FW_IQ_CMD_IQANDST_S)
1612
1613 #define FW_IQ_CMD_IQANUS_S      14
1614 #define FW_IQ_CMD_IQANUS_V(x)   ((x) << FW_IQ_CMD_IQANUS_S)
1615
1616 #define FW_IQ_CMD_IQANUD_S      12
1617 #define FW_IQ_CMD_IQANUD_V(x)   ((x) << FW_IQ_CMD_IQANUD_S)
1618
1619 #define FW_IQ_CMD_IQANDSTINDEX_S        0
1620 #define FW_IQ_CMD_IQANDSTINDEX_V(x)     ((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1621
1622 #define FW_IQ_CMD_IQDROPRSS_S           15
1623 #define FW_IQ_CMD_IQDROPRSS_V(x)        ((x) << FW_IQ_CMD_IQDROPRSS_S)
1624 #define FW_IQ_CMD_IQDROPRSS_F   FW_IQ_CMD_IQDROPRSS_V(1U)
1625
1626 #define FW_IQ_CMD_IQGTSMODE_S           14
1627 #define FW_IQ_CMD_IQGTSMODE_V(x)        ((x) << FW_IQ_CMD_IQGTSMODE_S)
1628 #define FW_IQ_CMD_IQGTSMODE_F           FW_IQ_CMD_IQGTSMODE_V(1U)
1629
1630 #define FW_IQ_CMD_IQPCIECH_S    12
1631 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)
1632
1633 #define FW_IQ_CMD_IQDCAEN_S     11
1634 #define FW_IQ_CMD_IQDCAEN_V(x)  ((x) << FW_IQ_CMD_IQDCAEN_S)
1635
1636 #define FW_IQ_CMD_IQDCACPU_S    6
1637 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)
1638
1639 #define FW_IQ_CMD_IQINTCNTTHRESH_S      4
1640 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x)   ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1641
1642 #define FW_IQ_CMD_IQO_S         3
1643 #define FW_IQ_CMD_IQO_V(x)      ((x) << FW_IQ_CMD_IQO_S)
1644 #define FW_IQ_CMD_IQO_F         FW_IQ_CMD_IQO_V(1U)
1645
1646 #define FW_IQ_CMD_IQCPRIO_S     2
1647 #define FW_IQ_CMD_IQCPRIO_V(x)  ((x) << FW_IQ_CMD_IQCPRIO_S)
1648
1649 #define FW_IQ_CMD_IQESIZE_S     0
1650 #define FW_IQ_CMD_IQESIZE_V(x)  ((x) << FW_IQ_CMD_IQESIZE_S)
1651
1652 #define FW_IQ_CMD_IQNS_S        31
1653 #define FW_IQ_CMD_IQNS_V(x)     ((x) << FW_IQ_CMD_IQNS_S)
1654
1655 #define FW_IQ_CMD_IQRO_S        30
1656 #define FW_IQ_CMD_IQRO_V(x)     ((x) << FW_IQ_CMD_IQRO_S)
1657
1658 #define FW_IQ_CMD_IQFLINTIQHSEN_S       28
1659 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1660
1661 #define FW_IQ_CMD_IQFLINTCONGEN_S       27
1662 #define FW_IQ_CMD_IQFLINTCONGEN_V(x)    ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1663 #define FW_IQ_CMD_IQFLINTCONGEN_F       FW_IQ_CMD_IQFLINTCONGEN_V(1U)
1664
1665 #define FW_IQ_CMD_IQFLINTISCSIC_S       26
1666 #define FW_IQ_CMD_IQFLINTISCSIC_V(x)    ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1667
1668 #define FW_IQ_CMD_IQTYPE_S              24
1669 #define FW_IQ_CMD_IQTYPE_M              0x3
1670 #define FW_IQ_CMD_IQTYPE_V(x)           ((x) << FW_IQ_CMD_IQTYPE_S)
1671 #define FW_IQ_CMD_IQTYPE_G(x)           \
1672         (((x) >> FW_IQ_CMD_IQTYPE_S) & FW_IQ_CMD_IQTYPE_M)
1673
1674 #define FW_IQ_CMD_FL0CNGCHMAP_S         20
1675 #define FW_IQ_CMD_FL0CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1676
1677 #define FW_IQ_CMD_FL0CACHELOCK_S        15
1678 #define FW_IQ_CMD_FL0CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1679
1680 #define FW_IQ_CMD_FL0DBP_S      14
1681 #define FW_IQ_CMD_FL0DBP_V(x)   ((x) << FW_IQ_CMD_FL0DBP_S)
1682
1683 #define FW_IQ_CMD_FL0DATANS_S           13
1684 #define FW_IQ_CMD_FL0DATANS_V(x)        ((x) << FW_IQ_CMD_FL0DATANS_S)
1685
1686 #define FW_IQ_CMD_FL0DATARO_S           12
1687 #define FW_IQ_CMD_FL0DATARO_V(x)        ((x) << FW_IQ_CMD_FL0DATARO_S)
1688 #define FW_IQ_CMD_FL0DATARO_F           FW_IQ_CMD_FL0DATARO_V(1U)
1689
1690 #define FW_IQ_CMD_FL0CONGCIF_S          11
1691 #define FW_IQ_CMD_FL0CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL0CONGCIF_S)
1692 #define FW_IQ_CMD_FL0CONGCIF_F          FW_IQ_CMD_FL0CONGCIF_V(1U)
1693
1694 #define FW_IQ_CMD_FL0ONCHIP_S           10
1695 #define FW_IQ_CMD_FL0ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL0ONCHIP_S)
1696
1697 #define FW_IQ_CMD_FL0STATUSPGNS_S       9
1698 #define FW_IQ_CMD_FL0STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1699
1700 #define FW_IQ_CMD_FL0STATUSPGRO_S       8
1701 #define FW_IQ_CMD_FL0STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1702
1703 #define FW_IQ_CMD_FL0FETCHNS_S          7
1704 #define FW_IQ_CMD_FL0FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL0FETCHNS_S)
1705
1706 #define FW_IQ_CMD_FL0FETCHRO_S          6
1707 #define FW_IQ_CMD_FL0FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL0FETCHRO_S)
1708 #define FW_IQ_CMD_FL0FETCHRO_F          FW_IQ_CMD_FL0FETCHRO_V(1U)
1709
1710 #define FW_IQ_CMD_FL0HOSTFCMODE_S       4
1711 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1712
1713 #define FW_IQ_CMD_FL0CPRIO_S    3
1714 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)
1715
1716 #define FW_IQ_CMD_FL0PADEN_S    2
1717 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)
1718 #define FW_IQ_CMD_FL0PADEN_F    FW_IQ_CMD_FL0PADEN_V(1U)
1719
1720 #define FW_IQ_CMD_FL0PACKEN_S           1
1721 #define FW_IQ_CMD_FL0PACKEN_V(x)        ((x) << FW_IQ_CMD_FL0PACKEN_S)
1722 #define FW_IQ_CMD_FL0PACKEN_F           FW_IQ_CMD_FL0PACKEN_V(1U)
1723
1724 #define FW_IQ_CMD_FL0CONGEN_S           0
1725 #define FW_IQ_CMD_FL0CONGEN_V(x)        ((x) << FW_IQ_CMD_FL0CONGEN_S)
1726 #define FW_IQ_CMD_FL0CONGEN_F           FW_IQ_CMD_FL0CONGEN_V(1U)
1727
1728 #define FW_IQ_CMD_FL0DCAEN_S    15
1729 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)
1730
1731 #define FW_IQ_CMD_FL0DCACPU_S           10
1732 #define FW_IQ_CMD_FL0DCACPU_V(x)        ((x) << FW_IQ_CMD_FL0DCACPU_S)
1733
1734 #define FW_IQ_CMD_FL0FBMIN_S    7
1735 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)
1736
1737 #define FW_IQ_CMD_FL0FBMAX_S    4
1738 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)
1739
1740 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S     3
1741 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1742 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F     FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1743
1744 #define FW_IQ_CMD_FL0CIDXFTHRESH_S      0
1745 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1746
1747 #define FW_IQ_CMD_FL1CNGCHMAP_S         20
1748 #define FW_IQ_CMD_FL1CNGCHMAP_V(x)      ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1749
1750 #define FW_IQ_CMD_FL1CACHELOCK_S        15
1751 #define FW_IQ_CMD_FL1CACHELOCK_V(x)     ((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1752
1753 #define FW_IQ_CMD_FL1DBP_S      14
1754 #define FW_IQ_CMD_FL1DBP_V(x)   ((x) << FW_IQ_CMD_FL1DBP_S)
1755
1756 #define FW_IQ_CMD_FL1DATANS_S           13
1757 #define FW_IQ_CMD_FL1DATANS_V(x)        ((x) << FW_IQ_CMD_FL1DATANS_S)
1758
1759 #define FW_IQ_CMD_FL1DATARO_S           12
1760 #define FW_IQ_CMD_FL1DATARO_V(x)        ((x) << FW_IQ_CMD_FL1DATARO_S)
1761
1762 #define FW_IQ_CMD_FL1CONGCIF_S          11
1763 #define FW_IQ_CMD_FL1CONGCIF_V(x)       ((x) << FW_IQ_CMD_FL1CONGCIF_S)
1764
1765 #define FW_IQ_CMD_FL1ONCHIP_S           10
1766 #define FW_IQ_CMD_FL1ONCHIP_V(x)        ((x) << FW_IQ_CMD_FL1ONCHIP_S)
1767
1768 #define FW_IQ_CMD_FL1STATUSPGNS_S       9
1769 #define FW_IQ_CMD_FL1STATUSPGNS_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1770
1771 #define FW_IQ_CMD_FL1STATUSPGRO_S       8
1772 #define FW_IQ_CMD_FL1STATUSPGRO_V(x)    ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1773
1774 #define FW_IQ_CMD_FL1FETCHNS_S          7
1775 #define FW_IQ_CMD_FL1FETCHNS_V(x)       ((x) << FW_IQ_CMD_FL1FETCHNS_S)
1776
1777 #define FW_IQ_CMD_FL1FETCHRO_S          6
1778 #define FW_IQ_CMD_FL1FETCHRO_V(x)       ((x) << FW_IQ_CMD_FL1FETCHRO_S)
1779
1780 #define FW_IQ_CMD_FL1HOSTFCMODE_S       4
1781 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x)    ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1782
1783 #define FW_IQ_CMD_FL1CPRIO_S    3
1784 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)
1785
1786 #define FW_IQ_CMD_FL1PADEN_S    2
1787 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)
1788 #define FW_IQ_CMD_FL1PADEN_F    FW_IQ_CMD_FL1PADEN_V(1U)
1789
1790 #define FW_IQ_CMD_FL1PACKEN_S           1
1791 #define FW_IQ_CMD_FL1PACKEN_V(x)        ((x) << FW_IQ_CMD_FL1PACKEN_S)
1792 #define FW_IQ_CMD_FL1PACKEN_F   FW_IQ_CMD_FL1PACKEN_V(1U)
1793
1794 #define FW_IQ_CMD_FL1CONGEN_S           0
1795 #define FW_IQ_CMD_FL1CONGEN_V(x)        ((x) << FW_IQ_CMD_FL1CONGEN_S)
1796 #define FW_IQ_CMD_FL1CONGEN_F   FW_IQ_CMD_FL1CONGEN_V(1U)
1797
1798 #define FW_IQ_CMD_FL1DCAEN_S    15
1799 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)
1800
1801 #define FW_IQ_CMD_FL1DCACPU_S           10
1802 #define FW_IQ_CMD_FL1DCACPU_V(x)        ((x) << FW_IQ_CMD_FL1DCACPU_S)
1803
1804 #define FW_IQ_CMD_FL1FBMIN_S    7
1805 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)
1806
1807 #define FW_IQ_CMD_FL1FBMAX_S    4
1808 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)
1809
1810 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S     3
1811 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x)  ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1812 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F     FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1813
1814 #define FW_IQ_CMD_FL1CIDXFTHRESH_S      0
1815 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x)   ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1816
1817 struct fw_eq_eth_cmd {
1818         __be32 op_to_vfn;
1819         __be32 alloc_to_len16;
1820         __be32 eqid_pkd;
1821         __be32 physeqid_pkd;
1822         __be32 fetchszm_to_iqid;
1823         __be32 dcaen_to_eqsize;
1824         __be64 eqaddr;
1825         __be32 autoequiqe_to_viid;
1826         __be32 timeren_timerix;
1827         __be64 r9;
1828 };
1829
1830 #define FW_EQ_ETH_CMD_PFN_S     8
1831 #define FW_EQ_ETH_CMD_PFN_V(x)  ((x) << FW_EQ_ETH_CMD_PFN_S)
1832
1833 #define FW_EQ_ETH_CMD_VFN_S     0
1834 #define FW_EQ_ETH_CMD_VFN_V(x)  ((x) << FW_EQ_ETH_CMD_VFN_S)
1835
1836 #define FW_EQ_ETH_CMD_ALLOC_S           31
1837 #define FW_EQ_ETH_CMD_ALLOC_V(x)        ((x) << FW_EQ_ETH_CMD_ALLOC_S)
1838 #define FW_EQ_ETH_CMD_ALLOC_F   FW_EQ_ETH_CMD_ALLOC_V(1U)
1839
1840 #define FW_EQ_ETH_CMD_FREE_S    30
1841 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)
1842 #define FW_EQ_ETH_CMD_FREE_F    FW_EQ_ETH_CMD_FREE_V(1U)
1843
1844 #define FW_EQ_ETH_CMD_MODIFY_S          29
1845 #define FW_EQ_ETH_CMD_MODIFY_V(x)       ((x) << FW_EQ_ETH_CMD_MODIFY_S)
1846 #define FW_EQ_ETH_CMD_MODIFY_F  FW_EQ_ETH_CMD_MODIFY_V(1U)
1847
1848 #define FW_EQ_ETH_CMD_EQSTART_S         28
1849 #define FW_EQ_ETH_CMD_EQSTART_V(x)      ((x) << FW_EQ_ETH_CMD_EQSTART_S)
1850 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U)
1851
1852 #define FW_EQ_ETH_CMD_EQSTOP_S          27
1853 #define FW_EQ_ETH_CMD_EQSTOP_V(x)       ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1854 #define FW_EQ_ETH_CMD_EQSTOP_F  FW_EQ_ETH_CMD_EQSTOP_V(1U)
1855
1856 #define FW_EQ_ETH_CMD_EQID_S    0
1857 #define FW_EQ_ETH_CMD_EQID_M    0xfffff
1858 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
1859 #define FW_EQ_ETH_CMD_EQID_G(x) \
1860         (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1861
1862 #define FW_EQ_ETH_CMD_PHYSEQID_S        0
1863 #define FW_EQ_ETH_CMD_PHYSEQID_M        0xfffff
1864 #define FW_EQ_ETH_CMD_PHYSEQID_V(x)     ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1865 #define FW_EQ_ETH_CMD_PHYSEQID_G(x)     \
1866         (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1867
1868 #define FW_EQ_ETH_CMD_FETCHSZM_S        26
1869 #define FW_EQ_ETH_CMD_FETCHSZM_V(x)     ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1870 #define FW_EQ_ETH_CMD_FETCHSZM_F        FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1871
1872 #define FW_EQ_ETH_CMD_STATUSPGNS_S      25
1873 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1874
1875 #define FW_EQ_ETH_CMD_STATUSPGRO_S      24
1876 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x)   ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1877
1878 #define FW_EQ_ETH_CMD_FETCHNS_S         23
1879 #define FW_EQ_ETH_CMD_FETCHNS_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1880
1881 #define FW_EQ_ETH_CMD_FETCHRO_S         22
1882 #define FW_EQ_ETH_CMD_FETCHRO_V(x)      ((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1883 #define FW_EQ_ETH_CMD_FETCHRO_F         FW_EQ_ETH_CMD_FETCHRO_V(1U)
1884
1885 #define FW_EQ_ETH_CMD_HOSTFCMODE_S      20
1886 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x)   ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1887
1888 #define FW_EQ_ETH_CMD_CPRIO_S           19
1889 #define FW_EQ_ETH_CMD_CPRIO_V(x)        ((x) << FW_EQ_ETH_CMD_CPRIO_S)
1890
1891 #define FW_EQ_ETH_CMD_ONCHIP_S          18
1892 #define FW_EQ_ETH_CMD_ONCHIP_V(x)       ((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1893
1894 #define FW_EQ_ETH_CMD_PCIECHN_S         16
1895 #define FW_EQ_ETH_CMD_PCIECHN_V(x)      ((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1896
1897 #define FW_EQ_ETH_CMD_IQID_S    0
1898 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)
1899
1900 #define FW_EQ_ETH_CMD_DCAEN_S           31
1901 #define FW_EQ_ETH_CMD_DCAEN_V(x)        ((x) << FW_EQ_ETH_CMD_DCAEN_S)
1902
1903 #define FW_EQ_ETH_CMD_DCACPU_S          26
1904 #define FW_EQ_ETH_CMD_DCACPU_V(x)       ((x) << FW_EQ_ETH_CMD_DCACPU_S)
1905
1906 #define FW_EQ_ETH_CMD_FBMIN_S           23
1907 #define FW_EQ_ETH_CMD_FBMIN_V(x)        ((x) << FW_EQ_ETH_CMD_FBMIN_S)
1908
1909 #define FW_EQ_ETH_CMD_FBMAX_S           20
1910 #define FW_EQ_ETH_CMD_FBMAX_V(x)        ((x) << FW_EQ_ETH_CMD_FBMAX_S)
1911
1912 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S    19
1913 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1914
1915 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S     16
1916 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x)  ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1917
1918 #define FW_EQ_ETH_CMD_EQSIZE_S          0
1919 #define FW_EQ_ETH_CMD_EQSIZE_V(x)       ((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1920
1921 #define FW_EQ_ETH_CMD_AUTOEQUIQE_S      31
1922 #define FW_EQ_ETH_CMD_AUTOEQUIQE_V(x)   ((x) << FW_EQ_ETH_CMD_AUTOEQUIQE_S)
1923 #define FW_EQ_ETH_CMD_AUTOEQUIQE_F      FW_EQ_ETH_CMD_AUTOEQUIQE_V(1U)
1924
1925 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S      30
1926 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x)   ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1927 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F      FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1928
1929 #define FW_EQ_ETH_CMD_VIID_S    16
1930 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)
1931
1932 #define FW_EQ_ETH_CMD_TIMEREN_S         3
1933 #define FW_EQ_ETH_CMD_TIMEREN_M         0x1
1934 #define FW_EQ_ETH_CMD_TIMEREN_V(x)      ((x) << FW_EQ_ETH_CMD_TIMEREN_S)
1935 #define FW_EQ_ETH_CMD_TIMEREN_G(x)      \
1936     (((x) >> FW_EQ_ETH_CMD_TIMEREN_S) & FW_EQ_ETH_CMD_TIMEREN_M)
1937 #define FW_EQ_ETH_CMD_TIMEREN_F FW_EQ_ETH_CMD_TIMEREN_V(1U)
1938
1939 #define FW_EQ_ETH_CMD_TIMERIX_S         0
1940 #define FW_EQ_ETH_CMD_TIMERIX_M         0x7
1941 #define FW_EQ_ETH_CMD_TIMERIX_V(x)      ((x) << FW_EQ_ETH_CMD_TIMERIX_S)
1942 #define FW_EQ_ETH_CMD_TIMERIX_G(x)      \
1943     (((x) >> FW_EQ_ETH_CMD_TIMERIX_S) & FW_EQ_ETH_CMD_TIMERIX_M)
1944
1945 struct fw_eq_ctrl_cmd {
1946         __be32 op_to_vfn;
1947         __be32 alloc_to_len16;
1948         __be32 cmpliqid_eqid;
1949         __be32 physeqid_pkd;
1950         __be32 fetchszm_to_iqid;
1951         __be32 dcaen_to_eqsize;
1952         __be64 eqaddr;
1953 };
1954
1955 #define FW_EQ_CTRL_CMD_PFN_S    8
1956 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)
1957
1958 #define FW_EQ_CTRL_CMD_VFN_S    0
1959 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)
1960
1961 #define FW_EQ_CTRL_CMD_ALLOC_S          31
1962 #define FW_EQ_CTRL_CMD_ALLOC_V(x)       ((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1963 #define FW_EQ_CTRL_CMD_ALLOC_F          FW_EQ_CTRL_CMD_ALLOC_V(1U)
1964
1965 #define FW_EQ_CTRL_CMD_FREE_S           30
1966 #define FW_EQ_CTRL_CMD_FREE_V(x)        ((x) << FW_EQ_CTRL_CMD_FREE_S)
1967 #define FW_EQ_CTRL_CMD_FREE_F           FW_EQ_CTRL_CMD_FREE_V(1U)
1968
1969 #define FW_EQ_CTRL_CMD_MODIFY_S         29
1970 #define FW_EQ_CTRL_CMD_MODIFY_V(x)      ((x) << FW_EQ_CTRL_CMD_MODIFY_S)
1971 #define FW_EQ_CTRL_CMD_MODIFY_F         FW_EQ_CTRL_CMD_MODIFY_V(1U)
1972
1973 #define FW_EQ_CTRL_CMD_EQSTART_S        28
1974 #define FW_EQ_CTRL_CMD_EQSTART_V(x)     ((x) << FW_EQ_CTRL_CMD_EQSTART_S)
1975 #define FW_EQ_CTRL_CMD_EQSTART_F        FW_EQ_CTRL_CMD_EQSTART_V(1U)
1976
1977 #define FW_EQ_CTRL_CMD_EQSTOP_S         27
1978 #define FW_EQ_CTRL_CMD_EQSTOP_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
1979 #define FW_EQ_CTRL_CMD_EQSTOP_F         FW_EQ_CTRL_CMD_EQSTOP_V(1U)
1980
1981 #define FW_EQ_CTRL_CMD_CMPLIQID_S       20
1982 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x)    ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
1983
1984 #define FW_EQ_CTRL_CMD_EQID_S           0
1985 #define FW_EQ_CTRL_CMD_EQID_M           0xfffff
1986 #define FW_EQ_CTRL_CMD_EQID_V(x)        ((x) << FW_EQ_CTRL_CMD_EQID_S)
1987 #define FW_EQ_CTRL_CMD_EQID_G(x)        \
1988         (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
1989
1990 #define FW_EQ_CTRL_CMD_PHYSEQID_S       0
1991 #define FW_EQ_CTRL_CMD_PHYSEQID_M       0xfffff
1992 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x)    \
1993         (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
1994
1995 #define FW_EQ_CTRL_CMD_FETCHSZM_S       26
1996 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
1997 #define FW_EQ_CTRL_CMD_FETCHSZM_F       FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
1998
1999 #define FW_EQ_CTRL_CMD_STATUSPGNS_S     25
2000 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
2001 #define FW_EQ_CTRL_CMD_STATUSPGNS_F     FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
2002
2003 #define FW_EQ_CTRL_CMD_STATUSPGRO_S     24
2004 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
2005 #define FW_EQ_CTRL_CMD_STATUSPGRO_F     FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
2006
2007 #define FW_EQ_CTRL_CMD_FETCHNS_S        23
2008 #define FW_EQ_CTRL_CMD_FETCHNS_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
2009 #define FW_EQ_CTRL_CMD_FETCHNS_F        FW_EQ_CTRL_CMD_FETCHNS_V(1U)
2010
2011 #define FW_EQ_CTRL_CMD_FETCHRO_S        22
2012 #define FW_EQ_CTRL_CMD_FETCHRO_V(x)     ((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
2013 #define FW_EQ_CTRL_CMD_FETCHRO_F        FW_EQ_CTRL_CMD_FETCHRO_V(1U)
2014
2015 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S     20
2016 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
2017
2018 #define FW_EQ_CTRL_CMD_CPRIO_S          19
2019 #define FW_EQ_CTRL_CMD_CPRIO_V(x)       ((x) << FW_EQ_CTRL_CMD_CPRIO_S)
2020
2021 #define FW_EQ_CTRL_CMD_ONCHIP_S         18
2022 #define FW_EQ_CTRL_CMD_ONCHIP_V(x)      ((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
2023
2024 #define FW_EQ_CTRL_CMD_PCIECHN_S        16
2025 #define FW_EQ_CTRL_CMD_PCIECHN_V(x)     ((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
2026
2027 #define FW_EQ_CTRL_CMD_IQID_S           0
2028 #define FW_EQ_CTRL_CMD_IQID_V(x)        ((x) << FW_EQ_CTRL_CMD_IQID_S)
2029
2030 #define FW_EQ_CTRL_CMD_DCAEN_S          31
2031 #define FW_EQ_CTRL_CMD_DCAEN_V(x)       ((x) << FW_EQ_CTRL_CMD_DCAEN_S)
2032
2033 #define FW_EQ_CTRL_CMD_DCACPU_S         26
2034 #define FW_EQ_CTRL_CMD_DCACPU_V(x)      ((x) << FW_EQ_CTRL_CMD_DCACPU_S)
2035
2036 #define FW_EQ_CTRL_CMD_FBMIN_S          23
2037 #define FW_EQ_CTRL_CMD_FBMIN_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMIN_S)
2038
2039 #define FW_EQ_CTRL_CMD_FBMAX_S          20
2040 #define FW_EQ_CTRL_CMD_FBMAX_V(x)       ((x) << FW_EQ_CTRL_CMD_FBMAX_S)
2041
2042 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S           19
2043 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x)        \
2044         ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
2045
2046 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S    16
2047 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
2048
2049 #define FW_EQ_CTRL_CMD_EQSIZE_S         0
2050 #define FW_EQ_CTRL_CMD_EQSIZE_V(x)      ((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
2051
2052 struct fw_eq_ofld_cmd {
2053         __be32 op_to_vfn;
2054         __be32 alloc_to_len16;
2055         __be32 eqid_pkd;
2056         __be32 physeqid_pkd;
2057         __be32 fetchszm_to_iqid;
2058         __be32 dcaen_to_eqsize;
2059         __be64 eqaddr;
2060 };
2061
2062 #define FW_EQ_OFLD_CMD_PFN_S    8
2063 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S)
2064
2065 #define FW_EQ_OFLD_CMD_VFN_S    0
2066 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S)
2067
2068 #define FW_EQ_OFLD_CMD_ALLOC_S          31
2069 #define FW_EQ_OFLD_CMD_ALLOC_V(x)       ((x) << FW_EQ_OFLD_CMD_ALLOC_S)
2070 #define FW_EQ_OFLD_CMD_ALLOC_F          FW_EQ_OFLD_CMD_ALLOC_V(1U)
2071
2072 #define FW_EQ_OFLD_CMD_FREE_S           30
2073 #define FW_EQ_OFLD_CMD_FREE_V(x)        ((x) << FW_EQ_OFLD_CMD_FREE_S)
2074 #define FW_EQ_OFLD_CMD_FREE_F           FW_EQ_OFLD_CMD_FREE_V(1U)
2075
2076 #define FW_EQ_OFLD_CMD_MODIFY_S         29
2077 #define FW_EQ_OFLD_CMD_MODIFY_V(x)      ((x) << FW_EQ_OFLD_CMD_MODIFY_S)
2078 #define FW_EQ_OFLD_CMD_MODIFY_F         FW_EQ_OFLD_CMD_MODIFY_V(1U)
2079
2080 #define FW_EQ_OFLD_CMD_EQSTART_S        28
2081 #define FW_EQ_OFLD_CMD_EQSTART_V(x)     ((x) << FW_EQ_OFLD_CMD_EQSTART_S)
2082 #define FW_EQ_OFLD_CMD_EQSTART_F        FW_EQ_OFLD_CMD_EQSTART_V(1U)
2083
2084 #define FW_EQ_OFLD_CMD_EQSTOP_S         27
2085 #define FW_EQ_OFLD_CMD_EQSTOP_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
2086 #define FW_EQ_OFLD_CMD_EQSTOP_F         FW_EQ_OFLD_CMD_EQSTOP_V(1U)
2087
2088 #define FW_EQ_OFLD_CMD_EQID_S           0
2089 #define FW_EQ_OFLD_CMD_EQID_M           0xfffff
2090 #define FW_EQ_OFLD_CMD_EQID_V(x)        ((x) << FW_EQ_OFLD_CMD_EQID_S)
2091 #define FW_EQ_OFLD_CMD_EQID_G(x)        \
2092         (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
2093
2094 #define FW_EQ_OFLD_CMD_PHYSEQID_S       0
2095 #define FW_EQ_OFLD_CMD_PHYSEQID_M       0xfffff
2096 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x)    \
2097         (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
2098
2099 #define FW_EQ_OFLD_CMD_FETCHSZM_S       26
2100 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x)    ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
2101
2102 #define FW_EQ_OFLD_CMD_STATUSPGNS_S     25
2103 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
2104
2105 #define FW_EQ_OFLD_CMD_STATUSPGRO_S     24
2106 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x)  ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
2107
2108 #define FW_EQ_OFLD_CMD_FETCHNS_S        23
2109 #define FW_EQ_OFLD_CMD_FETCHNS_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
2110
2111 #define FW_EQ_OFLD_CMD_FETCHRO_S        22
2112 #define FW_EQ_OFLD_CMD_FETCHRO_V(x)     ((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
2113 #define FW_EQ_OFLD_CMD_FETCHRO_F        FW_EQ_OFLD_CMD_FETCHRO_V(1U)
2114
2115 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S     20
2116 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x)  ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
2117
2118 #define FW_EQ_OFLD_CMD_CPRIO_S          19
2119 #define FW_EQ_OFLD_CMD_CPRIO_V(x)       ((x) << FW_EQ_OFLD_CMD_CPRIO_S)
2120
2121 #define FW_EQ_OFLD_CMD_ONCHIP_S         18
2122 #define FW_EQ_OFLD_CMD_ONCHIP_V(x)      ((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
2123
2124 #define FW_EQ_OFLD_CMD_PCIECHN_S        16
2125 #define FW_EQ_OFLD_CMD_PCIECHN_V(x)     ((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
2126
2127 #define FW_EQ_OFLD_CMD_IQID_S           0
2128 #define FW_EQ_OFLD_CMD_IQID_V(x)        ((x) << FW_EQ_OFLD_CMD_IQID_S)
2129
2130 #define FW_EQ_OFLD_CMD_DCAEN_S          31
2131 #define FW_EQ_OFLD_CMD_DCAEN_V(x)       ((x) << FW_EQ_OFLD_CMD_DCAEN_S)
2132
2133 #define FW_EQ_OFLD_CMD_DCACPU_S         26
2134 #define FW_EQ_OFLD_CMD_DCACPU_V(x)      ((x) << FW_EQ_OFLD_CMD_DCACPU_S)
2135
2136 #define FW_EQ_OFLD_CMD_FBMIN_S          23
2137 #define FW_EQ_OFLD_CMD_FBMIN_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMIN_S)
2138
2139 #define FW_EQ_OFLD_CMD_FBMAX_S          20
2140 #define FW_EQ_OFLD_CMD_FBMAX_V(x)       ((x) << FW_EQ_OFLD_CMD_FBMAX_S)
2141
2142 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S           19
2143 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x)        \
2144         ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
2145
2146 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S    16
2147 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
2148
2149 #define FW_EQ_OFLD_CMD_EQSIZE_S         0
2150 #define FW_EQ_OFLD_CMD_EQSIZE_V(x)      ((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
2151
2152 /*
2153  * Macros for VIID parsing:
2154  * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
2155  */
2156
2157 #define FW_VIID_PFN_S           8
2158 #define FW_VIID_PFN_M           0x7
2159 #define FW_VIID_PFN_G(x)        (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
2160
2161 #define FW_VIID_VIVLD_S         7
2162 #define FW_VIID_VIVLD_M         0x1
2163 #define FW_VIID_VIVLD_G(x)      (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
2164
2165 #define FW_VIID_VIN_S           0
2166 #define FW_VIID_VIN_M           0x7F
2167 #define FW_VIID_VIN_G(x)        (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
2168
2169 struct fw_vi_cmd {
2170         __be32 op_to_vfn;
2171         __be32 alloc_to_len16;
2172         __be16 type_viid;
2173         u8 mac[6];
2174         u8 portid_pkd;
2175         u8 nmac;
2176         u8 nmac0[6];
2177         __be16 rsssize_pkd;
2178         u8 nmac1[6];
2179         __be16 idsiiq_pkd;
2180         u8 nmac2[6];
2181         __be16 idseiq_pkd;
2182         u8 nmac3[6];
2183         __be64 r9;
2184         __be64 r10;
2185 };
2186
2187 #define FW_VI_CMD_PFN_S         8
2188 #define FW_VI_CMD_PFN_V(x)      ((x) << FW_VI_CMD_PFN_S)
2189
2190 #define FW_VI_CMD_VFN_S         0
2191 #define FW_VI_CMD_VFN_V(x)      ((x) << FW_VI_CMD_VFN_S)
2192
2193 #define FW_VI_CMD_ALLOC_S       31
2194 #define FW_VI_CMD_ALLOC_V(x)    ((x) << FW_VI_CMD_ALLOC_S)
2195 #define FW_VI_CMD_ALLOC_F       FW_VI_CMD_ALLOC_V(1U)
2196
2197 #define FW_VI_CMD_FREE_S        30
2198 #define FW_VI_CMD_FREE_V(x)     ((x) << FW_VI_CMD_FREE_S)
2199 #define FW_VI_CMD_FREE_F        FW_VI_CMD_FREE_V(1U)
2200
2201 #define FW_VI_CMD_VFVLD_S       24
2202 #define FW_VI_CMD_VFVLD_M       0x1
2203 #define FW_VI_CMD_VFVLD_V(x)    ((x) << FW_VI_CMD_VFVLD_S)
2204 #define FW_VI_CMD_VFVLD_G(x)    \
2205         (((x) >> FW_VI_CMD_VFVLD_S) & FW_VI_CMD_VFVLD_M)
2206 #define FW_VI_CMD_VFVLD_F       FW_VI_CMD_VFVLD_V(1U)
2207
2208 #define FW_VI_CMD_VIN_S         16
2209 #define FW_VI_CMD_VIN_M         0xff
2210 #define FW_VI_CMD_VIN_V(x)      ((x) << FW_VI_CMD_VIN_S)
2211 #define FW_VI_CMD_VIN_G(x)      \
2212         (((x) >> FW_VI_CMD_VIN_S) & FW_VI_CMD_VIN_M)
2213
2214 #define FW_VI_CMD_VIID_S        0
2215 #define FW_VI_CMD_VIID_M        0xfff
2216 #define FW_VI_CMD_VIID_V(x)     ((x) << FW_VI_CMD_VIID_S)
2217 #define FW_VI_CMD_VIID_G(x)     (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
2218
2219 #define FW_VI_CMD_PORTID_S      4
2220 #define FW_VI_CMD_PORTID_M      0xf
2221 #define FW_VI_CMD_PORTID_V(x)   ((x) << FW_VI_CMD_PORTID_S)
2222 #define FW_VI_CMD_PORTID_G(x)   \
2223         (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
2224
2225 #define FW_VI_CMD_RSSSIZE_S     0
2226 #define FW_VI_CMD_RSSSIZE_M     0x7ff
2227 #define FW_VI_CMD_RSSSIZE_G(x)  \
2228         (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
2229
2230 /* Special VI_MAC command index ids */
2231 #define FW_VI_MAC_ADD_MAC               0x3FF
2232 #define FW_VI_MAC_ADD_PERSIST_MAC       0x3FE
2233 #define FW_VI_MAC_MAC_BASED_FREE        0x3FD
2234 #define FW_VI_MAC_ID_BASED_FREE         0x3FC
2235 #define FW_CLS_TCAM_NUM_ENTRIES         336
2236
2237 enum fw_vi_mac_smac {
2238         FW_VI_MAC_MPS_TCAM_ENTRY,
2239         FW_VI_MAC_MPS_TCAM_ONLY,
2240         FW_VI_MAC_SMT_ONLY,
2241         FW_VI_MAC_SMT_AND_MPSTCAM
2242 };
2243
2244 enum fw_vi_mac_result {
2245         FW_VI_MAC_R_SUCCESS,
2246         FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
2247         FW_VI_MAC_R_SMAC_FAIL,
2248         FW_VI_MAC_R_F_ACL_CHECK
2249 };
2250
2251 enum fw_vi_mac_entry_types {
2252         FW_VI_MAC_TYPE_EXACTMAC,
2253         FW_VI_MAC_TYPE_HASHVEC,
2254         FW_VI_MAC_TYPE_RAW,
2255         FW_VI_MAC_TYPE_EXACTMAC_VNI,
2256 };
2257
2258 struct fw_vi_mac_cmd {
2259         __be32 op_to_viid;
2260         __be32 freemacs_to_len16;
2261         union fw_vi_mac {
2262                 struct fw_vi_mac_exact {
2263                         __be16 valid_to_idx;
2264                         u8 macaddr[6];
2265                 } exact[7];
2266                 struct fw_vi_mac_hash {
2267                         __be64 hashvec;
2268                 } hash;
2269                 struct fw_vi_mac_raw {
2270                         __be32 raw_idx_pkd;
2271                         __be32 data0_pkd;
2272                         __be32 data1[2];
2273                         __be64 data0m_pkd;
2274                         __be32 data1m[2];
2275                 } raw;
2276                 struct fw_vi_mac_vni {
2277                         __be16 valid_to_idx;
2278                         __u8 macaddr[6];
2279                         __be16 r7;
2280                         __u8 macaddr_mask[6];
2281                         __be32 lookup_type_to_vni;
2282                         __be32 vni_mask_pkd;
2283                 } exact_vni[2];
2284         } u;
2285 };
2286
2287 #define FW_VI_MAC_CMD_SMTID_S           12
2288 #define FW_VI_MAC_CMD_SMTID_M           0xff
2289 #define FW_VI_MAC_CMD_SMTID_V(x)        ((x) << FW_VI_MAC_CMD_SMTID_S)
2290 #define FW_VI_MAC_CMD_SMTID_G(x)        \
2291         (((x) >> FW_VI_MAC_CMD_SMTID_S) & FW_VI_MAC_CMD_SMTID_M)
2292
2293 #define FW_VI_MAC_CMD_VIID_S    0
2294 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S)
2295
2296 #define FW_VI_MAC_CMD_FREEMACS_S        31
2297 #define FW_VI_MAC_CMD_FREEMACS_V(x)     ((x) << FW_VI_MAC_CMD_FREEMACS_S)
2298
2299 #define FW_VI_MAC_CMD_ENTRY_TYPE_S      23
2300 #define FW_VI_MAC_CMD_ENTRY_TYPE_M      0x7
2301 #define FW_VI_MAC_CMD_ENTRY_TYPE_V(x)   ((x) << FW_VI_MAC_CMD_ENTRY_TYPE_S)
2302 #define FW_VI_MAC_CMD_ENTRY_TYPE_G(x)   \
2303         (((x) >> FW_VI_MAC_CMD_ENTRY_TYPE_S) & FW_VI_MAC_CMD_ENTRY_TYPE_M)
2304
2305 #define FW_VI_MAC_CMD_HASHVECEN_S       23
2306 #define FW_VI_MAC_CMD_HASHVECEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHVECEN_S)
2307 #define FW_VI_MAC_CMD_HASHVECEN_F       FW_VI_MAC_CMD_HASHVECEN_V(1U)
2308
2309 #define FW_VI_MAC_CMD_HASHUNIEN_S       22
2310 #define FW_VI_MAC_CMD_HASHUNIEN_V(x)    ((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
2311
2312 #define FW_VI_MAC_CMD_VALID_S           15
2313 #define FW_VI_MAC_CMD_VALID_V(x)        ((x) << FW_VI_MAC_CMD_VALID_S)
2314 #define FW_VI_MAC_CMD_VALID_F   FW_VI_MAC_CMD_VALID_V(1U)
2315
2316 #define FW_VI_MAC_CMD_PRIO_S    12
2317 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S)
2318
2319 #define FW_VI_MAC_CMD_SMAC_RESULT_S     10
2320 #define FW_VI_MAC_CMD_SMAC_RESULT_M     0x3
2321 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x)  ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
2322 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x)  \
2323         (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
2324
2325 #define FW_VI_MAC_CMD_IDX_S     0
2326 #define FW_VI_MAC_CMD_IDX_M     0x3ff
2327 #define FW_VI_MAC_CMD_IDX_V(x)  ((x) << FW_VI_MAC_CMD_IDX_S)
2328 #define FW_VI_MAC_CMD_IDX_G(x)  \
2329         (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
2330
2331 #define FW_VI_MAC_CMD_RAW_IDX_S         16
2332 #define FW_VI_MAC_CMD_RAW_IDX_M         0xffff
2333 #define FW_VI_MAC_CMD_RAW_IDX_V(x)      ((x) << FW_VI_MAC_CMD_RAW_IDX_S)
2334 #define FW_VI_MAC_CMD_RAW_IDX_G(x)      \
2335         (((x) >> FW_VI_MAC_CMD_RAW_IDX_S) & FW_VI_MAC_CMD_RAW_IDX_M)
2336
2337 #define FW_VI_MAC_CMD_LOOKUP_TYPE_S     31
2338 #define FW_VI_MAC_CMD_LOOKUP_TYPE_M     0x1
2339 #define FW_VI_MAC_CMD_LOOKUP_TYPE_V(x)  ((x) << FW_VI_MAC_CMD_LOOKUP_TYPE_S)
2340 #define FW_VI_MAC_CMD_LOOKUP_TYPE_G(x)  \
2341         (((x) >> FW_VI_MAC_CMD_LOOKUP_TYPE_S) & FW_VI_MAC_CMD_LOOKUP_TYPE_M)
2342 #define FW_VI_MAC_CMD_LOOKUP_TYPE_F     FW_VI_MAC_CMD_LOOKUP_TYPE_V(1U)
2343
2344 #define FW_VI_MAC_CMD_DIP_HIT_S         30
2345 #define FW_VI_MAC_CMD_DIP_HIT_M         0x1
2346 #define FW_VI_MAC_CMD_DIP_HIT_V(x)      ((x) << FW_VI_MAC_CMD_DIP_HIT_S)
2347 #define FW_VI_MAC_CMD_DIP_HIT_G(x)      \
2348         (((x) >> FW_VI_MAC_CMD_DIP_HIT_S) & FW_VI_MAC_CMD_DIP_HIT_M)
2349 #define FW_VI_MAC_CMD_DIP_HIT_F         FW_VI_MAC_CMD_DIP_HIT_V(1U)
2350
2351 #define FW_VI_MAC_CMD_VNI_S             0
2352 #define FW_VI_MAC_CMD_VNI_M             0xffffff
2353 #define FW_VI_MAC_CMD_VNI_V(x)          ((x) << FW_VI_MAC_CMD_VNI_S)
2354 #define FW_VI_MAC_CMD_VNI_G(x)          \
2355         (((x) >> FW_VI_MAC_CMD_VNI_S) & FW_VI_MAC_CMD_VNI_M)
2356
2357 #define FW_VI_MAC_CMD_VNI_MASK_S        0
2358 #define FW_VI_MAC_CMD_VNI_MASK_M        0xffffff
2359 #define FW_VI_MAC_CMD_VNI_MASK_V(x)     ((x) << FW_VI_MAC_CMD_VNI_MASK_S)
2360 #define FW_VI_MAC_CMD_VNI_MASK_G(x)     \
2361         (((x) >> FW_VI_MAC_CMD_VNI_MASK_S) & FW_VI_MAC_CMD_VNI_MASK_M)
2362
2363 #define FW_RXMODE_MTU_NO_CHG    65535
2364
2365 struct fw_vi_rxmode_cmd {
2366         __be32 op_to_viid;
2367         __be32 retval_len16;
2368         __be32 mtu_to_vlanexen;
2369         __be32 r4_lo;
2370 };
2371
2372 #define FW_VI_RXMODE_CMD_VIID_S         0
2373 #define FW_VI_RXMODE_CMD_VIID_V(x)      ((x) << FW_VI_RXMODE_CMD_VIID_S)
2374
2375 #define FW_VI_RXMODE_CMD_MTU_S          16
2376 #define FW_VI_RXMODE_CMD_MTU_M          0xffff
2377 #define FW_VI_RXMODE_CMD_MTU_V(x)       ((x) << FW_VI_RXMODE_CMD_MTU_S)
2378
2379 #define FW_VI_RXMODE_CMD_PROMISCEN_S    14
2380 #define FW_VI_RXMODE_CMD_PROMISCEN_M    0x3
2381 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
2382
2383 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S           12
2384 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M           0x3
2385 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x)        \
2386         ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
2387
2388 #define FW_VI_RXMODE_CMD_BROADCASTEN_S          10
2389 #define FW_VI_RXMODE_CMD_BROADCASTEN_M          0x3
2390 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x)       \
2391         ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
2392
2393 #define FW_VI_RXMODE_CMD_VLANEXEN_S     8
2394 #define FW_VI_RXMODE_CMD_VLANEXEN_M     0x3
2395 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x)  ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
2396
2397 struct fw_vi_enable_cmd {
2398         __be32 op_to_viid;
2399         __be32 ien_to_len16;
2400         __be16 blinkdur;
2401         __be16 r3;
2402         __be32 r4;
2403 };
2404
2405 #define FW_VI_ENABLE_CMD_VIID_S         0
2406 #define FW_VI_ENABLE_CMD_VIID_V(x)      ((x) << FW_VI_ENABLE_CMD_VIID_S)
2407
2408 #define FW_VI_ENABLE_CMD_IEN_S          31
2409 #define FW_VI_ENABLE_CMD_IEN_V(x)       ((x) << FW_VI_ENABLE_CMD_IEN_S)
2410
2411 #define FW_VI_ENABLE_CMD_EEN_S          30
2412 #define FW_VI_ENABLE_CMD_EEN_V(x)       ((x) << FW_VI_ENABLE_CMD_EEN_S)
2413
2414 #define FW_VI_ENABLE_CMD_LED_S          29
2415 #define FW_VI_ENABLE_CMD_LED_V(x)       ((x) << FW_VI_ENABLE_CMD_LED_S)
2416 #define FW_VI_ENABLE_CMD_LED_F  FW_VI_ENABLE_CMD_LED_V(1U)
2417
2418 #define FW_VI_ENABLE_CMD_DCB_INFO_S     28
2419 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x)  ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2420
2421 /* VI VF stats offset definitions */
2422 #define VI_VF_NUM_STATS 16
2423 enum fw_vi_stats_vf_index {
2424         FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
2425         FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
2426         FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
2427         FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
2428         FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
2429         FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
2430         FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
2431         FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
2432         FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
2433         FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
2434         FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
2435         FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
2436         FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
2437         FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
2438         FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
2439         FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2440 };
2441
2442 /* VI PF stats offset definitions */
2443 #define VI_PF_NUM_STATS 17
2444 enum fw_vi_stats_pf_index {
2445         FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
2446         FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
2447         FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
2448         FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
2449         FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
2450         FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
2451         FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
2452         FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
2453         FW_VI_PF_STAT_RX_BYTES_IX,
2454         FW_VI_PF_STAT_RX_FRAMES_IX,
2455         FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
2456         FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
2457         FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
2458         FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
2459         FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
2460         FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
2461         FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2462 };
2463
2464 struct fw_vi_stats_cmd {
2465         __be32 op_to_viid;
2466         __be32 retval_len16;
2467         union fw_vi_stats {
2468                 struct fw_vi_stats_ctl {
2469                         __be16 nstats_ix;
2470                         __be16 r6;
2471                         __be32 r7;
2472                         __be64 stat0;
2473                         __be64 stat1;
2474                         __be64 stat2;
2475                         __be64 stat3;
2476                         __be64 stat4;
2477                         __be64 stat5;
2478                 } ctl;
2479                 struct fw_vi_stats_pf {
2480                         __be64 tx_bcast_bytes;
2481                         __be64 tx_bcast_frames;
2482                         __be64 tx_mcast_bytes;
2483                         __be64 tx_mcast_frames;
2484                         __be64 tx_ucast_bytes;
2485                         __be64 tx_ucast_frames;
2486                         __be64 tx_offload_bytes;
2487                         __be64 tx_offload_frames;
2488                         __be64 rx_pf_bytes;
2489                         __be64 rx_pf_frames;
2490                         __be64 rx_bcast_bytes;
2491                         __be64 rx_bcast_frames;
2492                         __be64 rx_mcast_bytes;
2493                         __be64 rx_mcast_frames;
2494                         __be64 rx_ucast_bytes;
2495                         __be64 rx_ucast_frames;
2496                         __be64 rx_err_frames;
2497                 } pf;
2498                 struct fw_vi_stats_vf {
2499                         __be64 tx_bcast_bytes;
2500                         __be64 tx_bcast_frames;
2501                         __be64 tx_mcast_bytes;
2502                         __be64 tx_mcast_frames;
2503                         __be64 tx_ucast_bytes;
2504                         __be64 tx_ucast_frames;
2505                         __be64 tx_drop_frames;
2506                         __be64 tx_offload_bytes;
2507                         __be64 tx_offload_frames;
2508                         __be64 rx_bcast_bytes;
2509                         __be64 rx_bcast_frames;
2510                         __be64 rx_mcast_bytes;
2511                         __be64 rx_mcast_frames;
2512                         __be64 rx_ucast_bytes;
2513                         __be64 rx_ucast_frames;
2514                         __be64 rx_err_frames;
2515                 } vf;
2516         } u;
2517 };
2518
2519 #define FW_VI_STATS_CMD_VIID_S          0
2520 #define FW_VI_STATS_CMD_VIID_V(x)       ((x) << FW_VI_STATS_CMD_VIID_S)
2521
2522 #define FW_VI_STATS_CMD_NSTATS_S        12
2523 #define FW_VI_STATS_CMD_NSTATS_V(x)     ((x) << FW_VI_STATS_CMD_NSTATS_S)
2524
2525 #define FW_VI_STATS_CMD_IX_S    0
2526 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S)
2527
2528 struct fw_acl_mac_cmd {
2529         __be32 op_to_vfn;
2530         __be32 en_to_len16;
2531         u8 nmac;
2532         u8 r3[7];
2533         __be16 r4;
2534         u8 macaddr0[6];
2535         __be16 r5;
2536         u8 macaddr1[6];
2537         __be16 r6;
2538         u8 macaddr2[6];
2539         __be16 r7;
2540         u8 macaddr3[6];
2541 };
2542
2543 #define FW_ACL_MAC_CMD_PFN_S    8
2544 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S)
2545
2546 #define FW_ACL_MAC_CMD_VFN_S    0
2547 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S)
2548
2549 #define FW_ACL_MAC_CMD_EN_S     31
2550 #define FW_ACL_MAC_CMD_EN_V(x)  ((x) << FW_ACL_MAC_CMD_EN_S)
2551
2552 struct fw_acl_vlan_cmd {
2553         __be32 op_to_vfn;
2554         __be32 en_to_len16;
2555         u8 nvlan;
2556         u8 dropnovlan_fm;
2557         u8 r3_lo[6];
2558         __be16 vlanid[16];
2559 };
2560
2561 #define FW_ACL_VLAN_CMD_PFN_S           8
2562 #define FW_ACL_VLAN_CMD_PFN_V(x)        ((x) << FW_ACL_VLAN_CMD_PFN_S)
2563
2564 #define FW_ACL_VLAN_CMD_VFN_S           0
2565 #define FW_ACL_VLAN_CMD_VFN_V(x)        ((x) << FW_ACL_VLAN_CMD_VFN_S)
2566
2567 #define FW_ACL_VLAN_CMD_EN_S            31
2568 #define FW_ACL_VLAN_CMD_EN_M            0x1
2569 #define FW_ACL_VLAN_CMD_EN_V(x)         ((x) << FW_ACL_VLAN_CMD_EN_S)
2570 #define FW_ACL_VLAN_CMD_EN_G(x)         \
2571         (((x) >> S_FW_ACL_VLAN_CMD_EN_S) & FW_ACL_VLAN_CMD_EN_M)
2572 #define FW_ACL_VLAN_CMD_EN_F            FW_ACL_VLAN_CMD_EN_V(1U)
2573
2574 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S    7
2575 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2576 #define FW_ACL_VLAN_CMD_DROPNOVLAN_F    FW_ACL_VLAN_CMD_DROPNOVLAN_V(1U)
2577
2578 #define FW_ACL_VLAN_CMD_FM_S            6
2579 #define FW_ACL_VLAN_CMD_FM_M            0x1
2580 #define FW_ACL_VLAN_CMD_FM_V(x)         ((x) << FW_ACL_VLAN_CMD_FM_S)
2581 #define FW_ACL_VLAN_CMD_FM_G(x)         \
2582         (((x) >> FW_ACL_VLAN_CMD_FM_S) & FW_ACL_VLAN_CMD_FM_M)
2583 #define FW_ACL_VLAN_CMD_FM_F            FW_ACL_VLAN_CMD_FM_V(1U)
2584
2585 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */
2586 enum fw_port_cap {
2587         FW_PORT_CAP_SPEED_100M          = 0x0001,
2588         FW_PORT_CAP_SPEED_1G            = 0x0002,
2589         FW_PORT_CAP_SPEED_25G           = 0x0004,
2590         FW_PORT_CAP_SPEED_10G           = 0x0008,
2591         FW_PORT_CAP_SPEED_40G           = 0x0010,
2592         FW_PORT_CAP_SPEED_100G          = 0x0020,
2593         FW_PORT_CAP_FC_RX               = 0x0040,
2594         FW_PORT_CAP_FC_TX               = 0x0080,
2595         FW_PORT_CAP_ANEG                = 0x0100,
2596         FW_PORT_CAP_MDIAUTO             = 0x0200,
2597         FW_PORT_CAP_MDISTRAIGHT         = 0x0400,
2598         FW_PORT_CAP_FEC_RS              = 0x0800,
2599         FW_PORT_CAP_FEC_BASER_RS        = 0x1000,
2600         FW_PORT_CAP_FORCE_PAUSE         = 0x2000,
2601         FW_PORT_CAP_802_3_PAUSE         = 0x4000,
2602         FW_PORT_CAP_802_3_ASM_DIR       = 0x8000,
2603 };
2604
2605 #define FW_PORT_CAP_SPEED_S     0
2606 #define FW_PORT_CAP_SPEED_M     0x3f
2607 #define FW_PORT_CAP_SPEED_V(x)  ((x) << FW_PORT_CAP_SPEED_S)
2608 #define FW_PORT_CAP_SPEED_G(x) \
2609         (((x) >> FW_PORT_CAP_SPEED_S) & FW_PORT_CAP_SPEED_M)
2610
2611 enum fw_port_mdi {
2612         FW_PORT_CAP_MDI_UNCHANGED,
2613         FW_PORT_CAP_MDI_AUTO,
2614         FW_PORT_CAP_MDI_F_STRAIGHT,
2615         FW_PORT_CAP_MDI_F_CROSSOVER
2616 };
2617
2618 #define FW_PORT_CAP_MDI_S 9
2619 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2620
2621 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */
2622 #define FW_PORT_CAP32_SPEED_100M        0x00000001UL
2623 #define FW_PORT_CAP32_SPEED_1G          0x00000002UL
2624 #define FW_PORT_CAP32_SPEED_10G         0x00000004UL
2625 #define FW_PORT_CAP32_SPEED_25G         0x00000008UL
2626 #define FW_PORT_CAP32_SPEED_40G         0x00000010UL
2627 #define FW_PORT_CAP32_SPEED_50G         0x00000020UL
2628 #define FW_PORT_CAP32_SPEED_100G        0x00000040UL
2629 #define FW_PORT_CAP32_SPEED_200G        0x00000080UL
2630 #define FW_PORT_CAP32_SPEED_400G        0x00000100UL
2631 #define FW_PORT_CAP32_SPEED_RESERVED1   0x00000200UL
2632 #define FW_PORT_CAP32_SPEED_RESERVED2   0x00000400UL
2633 #define FW_PORT_CAP32_SPEED_RESERVED3   0x00000800UL
2634 #define FW_PORT_CAP32_RESERVED1         0x0000f000UL
2635 #define FW_PORT_CAP32_FC_RX             0x00010000UL
2636 #define FW_PORT_CAP32_FC_TX             0x00020000UL
2637 #define FW_PORT_CAP32_802_3_PAUSE       0x00040000UL
2638 #define FW_PORT_CAP32_802_3_ASM_DIR     0x00080000UL
2639 #define FW_PORT_CAP32_ANEG              0x00100000UL
2640 #define FW_PORT_CAP32_MDIAUTO           0x00200000UL
2641 #define FW_PORT_CAP32_MDISTRAIGHT       0x00400000UL
2642 #define FW_PORT_CAP32_FEC_RS            0x00800000UL
2643 #define FW_PORT_CAP32_FEC_BASER_RS      0x01000000UL
2644 #define FW_PORT_CAP32_FEC_RESERVED1     0x02000000UL
2645 #define FW_PORT_CAP32_FEC_RESERVED2     0x04000000UL
2646 #define FW_PORT_CAP32_FEC_RESERVED3     0x08000000UL
2647 #define FW_PORT_CAP32_FORCE_PAUSE       0x10000000UL
2648 #define FW_PORT_CAP32_RESERVED2         0xe0000000UL
2649
2650 #define FW_PORT_CAP32_SPEED_S   0
2651 #define FW_PORT_CAP32_SPEED_M   0xfff
2652 #define FW_PORT_CAP32_SPEED_V(x)        ((x) << FW_PORT_CAP32_SPEED_S)
2653 #define FW_PORT_CAP32_SPEED_G(x) \
2654         (((x) >> FW_PORT_CAP32_SPEED_S) & FW_PORT_CAP32_SPEED_M)
2655
2656 #define FW_PORT_CAP32_FC_S      16
2657 #define FW_PORT_CAP32_FC_M      0x3
2658 #define FW_PORT_CAP32_FC_V(x)   ((x) << FW_PORT_CAP32_FC_S)
2659 #define FW_PORT_CAP32_FC_G(x) \
2660         (((x) >> FW_PORT_CAP32_FC_S) & FW_PORT_CAP32_FC_M)
2661
2662 #define FW_PORT_CAP32_802_3_S   18
2663 #define FW_PORT_CAP32_802_3_M   0x3
2664 #define FW_PORT_CAP32_802_3_V(x)        ((x) << FW_PORT_CAP32_802_3_S)
2665 #define FW_PORT_CAP32_802_3_G(x) \
2666         (((x) >> FW_PORT_CAP32_802_3_S) & FW_PORT_CAP32_802_3_M)
2667
2668 #define FW_PORT_CAP32_ANEG_S    20
2669 #define FW_PORT_CAP32_ANEG_M    0x1
2670 #define FW_PORT_CAP32_ANEG_V(x) ((x) << FW_PORT_CAP32_ANEG_S)
2671 #define FW_PORT_CAP32_ANEG_G(x) \
2672         (((x) >> FW_PORT_CAP32_ANEG_S) & FW_PORT_CAP32_ANEG_M)
2673
2674 enum fw_port_mdi32 {
2675         FW_PORT_CAP32_MDI_UNCHANGED,
2676         FW_PORT_CAP32_MDI_AUTO,
2677         FW_PORT_CAP32_MDI_F_STRAIGHT,
2678         FW_PORT_CAP32_MDI_F_CROSSOVER
2679 };
2680
2681 #define FW_PORT_CAP32_MDI_S 21
2682 #define FW_PORT_CAP32_MDI_M 3
2683 #define FW_PORT_CAP32_MDI_V(x) ((x) << FW_PORT_CAP32_MDI_S)
2684 #define FW_PORT_CAP32_MDI_G(x) \
2685         (((x) >> FW_PORT_CAP32_MDI_S) & FW_PORT_CAP32_MDI_M)
2686
2687 #define FW_PORT_CAP32_FEC_S     23
2688 #define FW_PORT_CAP32_FEC_M     0x1f
2689 #define FW_PORT_CAP32_FEC_V(x)  ((x) << FW_PORT_CAP32_FEC_S)
2690 #define FW_PORT_CAP32_FEC_G(x) \
2691         (((x) >> FW_PORT_CAP32_FEC_S) & FW_PORT_CAP32_FEC_M)
2692
2693 /* macros to isolate various 32-bit Port Capabilities sub-fields */
2694 #define CAP32_SPEED(__cap32) \
2695         (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) & __cap32)
2696
2697 #define CAP32_FEC(__cap32) \
2698         (FW_PORT_CAP32_FEC_V(FW_PORT_CAP32_FEC_M) & __cap32)
2699
2700 enum fw_port_action {
2701         FW_PORT_ACTION_L1_CFG           = 0x0001,
2702         FW_PORT_ACTION_L2_CFG           = 0x0002,
2703         FW_PORT_ACTION_GET_PORT_INFO    = 0x0003,
2704         FW_PORT_ACTION_L2_PPP_CFG       = 0x0004,
2705         FW_PORT_ACTION_L2_DCB_CFG       = 0x0005,
2706         FW_PORT_ACTION_DCB_READ_TRANS   = 0x0006,
2707         FW_PORT_ACTION_DCB_READ_RECV    = 0x0007,
2708         FW_PORT_ACTION_DCB_READ_DET     = 0x0008,
2709         FW_PORT_ACTION_L1_CFG32         = 0x0009,
2710         FW_PORT_ACTION_GET_PORT_INFO32  = 0x000a,
2711         FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
2712         FW_PORT_ACTION_L1_LOW_PWR_EN    = 0x0011,
2713         FW_PORT_ACTION_L2_WOL_MODE_EN   = 0x0012,
2714         FW_PORT_ACTION_LPBK_TO_NORMAL   = 0x0020,
2715         FW_PORT_ACTION_L1_LPBK          = 0x0021,
2716         FW_PORT_ACTION_L1_PMA_LPBK      = 0x0022,
2717         FW_PORT_ACTION_L1_PCS_LPBK      = 0x0023,
2718         FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
2719         FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
2720         FW_PORT_ACTION_PHY_RESET        = 0x0040,
2721         FW_PORT_ACTION_PMA_RESET        = 0x0041,
2722         FW_PORT_ACTION_PCS_RESET        = 0x0042,
2723         FW_PORT_ACTION_PHYXS_RESET      = 0x0043,
2724         FW_PORT_ACTION_DTEXS_REEST      = 0x0044,
2725         FW_PORT_ACTION_AN_RESET         = 0x0045
2726 };
2727
2728 enum fw_port_l2cfg_ctlbf {
2729         FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
2730         FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
2731         FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
2732         FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
2733         FW_PORT_L2_CTLBF_IVLAN  = 0x10,
2734         FW_PORT_L2_CTLBF_TXIPG  = 0x20
2735 };
2736
2737 enum fw_port_dcb_versions {
2738         FW_PORT_DCB_VER_UNKNOWN,
2739         FW_PORT_DCB_VER_CEE1D0,
2740         FW_PORT_DCB_VER_CEE1D01,
2741         FW_PORT_DCB_VER_IEEE,
2742         FW_PORT_DCB_VER_AUTO = 7
2743 };
2744
2745 enum fw_port_dcb_cfg {
2746         FW_PORT_DCB_CFG_PG      = 0x01,
2747         FW_PORT_DCB_CFG_PFC     = 0x02,
2748         FW_PORT_DCB_CFG_APPL    = 0x04
2749 };
2750
2751 enum fw_port_dcb_cfg_rc {
2752         FW_PORT_DCB_CFG_SUCCESS = 0x0,
2753         FW_PORT_DCB_CFG_ERROR   = 0x1
2754 };
2755
2756 enum fw_port_dcb_type {
2757         FW_PORT_DCB_TYPE_PGID           = 0x00,
2758         FW_PORT_DCB_TYPE_PGRATE         = 0x01,
2759         FW_PORT_DCB_TYPE_PRIORATE       = 0x02,
2760         FW_PORT_DCB_TYPE_PFC            = 0x03,
2761         FW_PORT_DCB_TYPE_APP_ID         = 0x04,
2762         FW_PORT_DCB_TYPE_CONTROL        = 0x05,
2763 };
2764
2765 enum fw_port_dcb_feature_state {
2766         FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
2767         FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
2768         FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
2769         FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
2770 };
2771
2772 struct fw_port_cmd {
2773         __be32 op_to_portid;
2774         __be32 action_to_len16;
2775         union fw_port {
2776                 struct fw_port_l1cfg {
2777                         __be32 rcap;
2778                         __be32 r;
2779                 } l1cfg;
2780                 struct fw_port_l2cfg {
2781                         __u8   ctlbf;
2782                         __u8   ovlan3_to_ivlan0;
2783                         __be16 ivlantype;
2784                         __be16 txipg_force_pinfo;
2785                         __be16 mtu;
2786                         __be16 ovlan0mask;
2787                         __be16 ovlan0type;
2788                         __be16 ovlan1mask;
2789                         __be16 ovlan1type;
2790                         __be16 ovlan2mask;
2791                         __be16 ovlan2type;
2792                         __be16 ovlan3mask;
2793                         __be16 ovlan3type;
2794                 } l2cfg;
2795                 struct fw_port_info {
2796                         __be32 lstatus_to_modtype;
2797                         __be16 pcap;
2798                         __be16 acap;
2799                         __be16 mtu;
2800                         __u8   cbllen;
2801                         __u8   auxlinfo;
2802                         __u8   dcbxdis_pkd;
2803                         __u8   r8_lo;
2804                         __be16 lpacap;
2805                         __be64 r9;
2806                 } info;
2807                 struct fw_port_diags {
2808                         __u8   diagop;
2809                         __u8   r[3];
2810                         __be32 diagval;
2811                 } diags;
2812                 union fw_port_dcb {
2813                         struct fw_port_dcb_pgid {
2814                                 __u8   type;
2815                                 __u8   apply_pkd;
2816                                 __u8   r10_lo[2];
2817                                 __be32 pgid;
2818                                 __be64 r11;
2819                         } pgid;
2820                         struct fw_port_dcb_pgrate {
2821                                 __u8   type;
2822                                 __u8   apply_pkd;
2823                                 __u8   r10_lo[5];
2824                                 __u8   num_tcs_supported;
2825                                 __u8   pgrate[8];
2826                                 __u8   tsa[8];
2827                         } pgrate;
2828                         struct fw_port_dcb_priorate {
2829                                 __u8   type;
2830                                 __u8   apply_pkd;
2831                                 __u8   r10_lo[6];
2832                                 __u8   strict_priorate[8];
2833                         } priorate;
2834                         struct fw_port_dcb_pfc {
2835                                 __u8   type;
2836                                 __u8   pfcen;
2837                                 __u8   r10[5];
2838                                 __u8   max_pfc_tcs;
2839                                 __be64 r11;
2840                         } pfc;
2841                         struct fw_port_app_priority {
2842                                 __u8   type;
2843                                 __u8   r10[2];
2844                                 __u8   idx;
2845                                 __u8   user_prio_map;
2846                                 __u8   sel_field;
2847                                 __be16 protocolid;
2848                                 __be64 r12;
2849                         } app_priority;
2850                         struct fw_port_dcb_control {
2851                                 __u8   type;
2852                                 __u8   all_syncd_pkd;
2853                                 __be16 dcb_version_to_app_state;
2854                                 __be32 r11;
2855                                 __be64 r12;
2856                         } control;
2857                 } dcb;
2858                 struct fw_port_l1cfg32 {
2859                         __be32 rcap32;
2860                         __be32 r;
2861                 } l1cfg32;
2862                 struct fw_port_info32 {
2863                         __be32 lstatus32_to_cbllen32;
2864                         __be32 auxlinfo32_mtu32;
2865                         __be32 linkattr32;
2866                         __be32 pcaps32;
2867                         __be32 acaps32;
2868                         __be32 lpacaps32;
2869                 } info32;
2870         } u;
2871 };
2872
2873 #define FW_PORT_CMD_READ_S      22
2874 #define FW_PORT_CMD_READ_V(x)   ((x) << FW_PORT_CMD_READ_S)
2875 #define FW_PORT_CMD_READ_F      FW_PORT_CMD_READ_V(1U)
2876
2877 #define FW_PORT_CMD_PORTID_S    0
2878 #define FW_PORT_CMD_PORTID_M    0xf
2879 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S)
2880 #define FW_PORT_CMD_PORTID_G(x) \
2881         (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2882
2883 #define FW_PORT_CMD_ACTION_S    16
2884 #define FW_PORT_CMD_ACTION_M    0xffff
2885 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S)
2886 #define FW_PORT_CMD_ACTION_G(x) \
2887         (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2888
2889 #define FW_PORT_CMD_OVLAN3_S    7
2890 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S)
2891
2892 #define FW_PORT_CMD_OVLAN2_S    6
2893 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S)
2894
2895 #define FW_PORT_CMD_OVLAN1_S    5
2896 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S)
2897
2898 #define FW_PORT_CMD_OVLAN0_S    4
2899 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S)
2900
2901 #define FW_PORT_CMD_IVLAN0_S    3
2902 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S)
2903
2904 #define FW_PORT_CMD_TXIPG_S     3
2905 #define FW_PORT_CMD_TXIPG_V(x)  ((x) << FW_PORT_CMD_TXIPG_S)
2906
2907 #define FW_PORT_CMD_LSTATUS_S           31
2908 #define FW_PORT_CMD_LSTATUS_M           0x1
2909 #define FW_PORT_CMD_LSTATUS_V(x)        ((x) << FW_PORT_CMD_LSTATUS_S)
2910 #define FW_PORT_CMD_LSTATUS_G(x)        \
2911         (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2912 #define FW_PORT_CMD_LSTATUS_F   FW_PORT_CMD_LSTATUS_V(1U)
2913
2914 #define FW_PORT_CMD_LSPEED_S    24
2915 #define FW_PORT_CMD_LSPEED_M    0x3f
2916 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S)
2917 #define FW_PORT_CMD_LSPEED_G(x) \
2918         (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2919
2920 #define FW_PORT_CMD_TXPAUSE_S           23
2921 #define FW_PORT_CMD_TXPAUSE_V(x)        ((x) << FW_PORT_CMD_TXPAUSE_S)
2922 #define FW_PORT_CMD_TXPAUSE_F   FW_PORT_CMD_TXPAUSE_V(1U)
2923
2924 #define FW_PORT_CMD_RXPAUSE_S           22
2925 #define FW_PORT_CMD_RXPAUSE_V(x)        ((x) << FW_PORT_CMD_RXPAUSE_S)
2926 #define FW_PORT_CMD_RXPAUSE_F   FW_PORT_CMD_RXPAUSE_V(1U)
2927
2928 #define FW_PORT_CMD_MDIOCAP_S           21
2929 #define FW_PORT_CMD_MDIOCAP_V(x)        ((x) << FW_PORT_CMD_MDIOCAP_S)
2930 #define FW_PORT_CMD_MDIOCAP_F   FW_PORT_CMD_MDIOCAP_V(1U)
2931
2932 #define FW_PORT_CMD_MDIOADDR_S          16
2933 #define FW_PORT_CMD_MDIOADDR_M          0x1f
2934 #define FW_PORT_CMD_MDIOADDR_G(x)       \
2935         (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2936
2937 #define FW_PORT_CMD_LPTXPAUSE_S         15
2938 #define FW_PORT_CMD_LPTXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPTXPAUSE_S)
2939 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U)
2940
2941 #define FW_PORT_CMD_LPRXPAUSE_S         14
2942 #define FW_PORT_CMD_LPRXPAUSE_V(x)      ((x) << FW_PORT_CMD_LPRXPAUSE_S)
2943 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U)
2944
2945 #define FW_PORT_CMD_PTYPE_S     8
2946 #define FW_PORT_CMD_PTYPE_M     0x1f
2947 #define FW_PORT_CMD_PTYPE_G(x)  \
2948         (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2949
2950 #define FW_PORT_CMD_LINKDNRC_S          5
2951 #define FW_PORT_CMD_LINKDNRC_M          0x7
2952 #define FW_PORT_CMD_LINKDNRC_G(x)       \
2953         (((x) >> FW_PORT_CMD_LINKDNRC_S) & FW_PORT_CMD_LINKDNRC_M)
2954
2955 #define FW_PORT_CMD_MODTYPE_S           0
2956 #define FW_PORT_CMD_MODTYPE_M           0x1f
2957 #define FW_PORT_CMD_MODTYPE_V(x)        ((x) << FW_PORT_CMD_MODTYPE_S)
2958 #define FW_PORT_CMD_MODTYPE_G(x)        \
2959         (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2960
2961 #define FW_PORT_CMD_DCBXDIS_S           7
2962 #define FW_PORT_CMD_DCBXDIS_V(x)        ((x) << FW_PORT_CMD_DCBXDIS_S)
2963 #define FW_PORT_CMD_DCBXDIS_F   FW_PORT_CMD_DCBXDIS_V(1U)
2964
2965 #define FW_PORT_CMD_APPLY_S     7
2966 #define FW_PORT_CMD_APPLY_V(x)  ((x) << FW_PORT_CMD_APPLY_S)
2967 #define FW_PORT_CMD_APPLY_F     FW_PORT_CMD_APPLY_V(1U)
2968
2969 #define FW_PORT_CMD_ALL_SYNCD_S         7
2970 #define FW_PORT_CMD_ALL_SYNCD_V(x)      ((x) << FW_PORT_CMD_ALL_SYNCD_S)
2971 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U)
2972
2973 #define FW_PORT_CMD_DCB_VERSION_S       12
2974 #define FW_PORT_CMD_DCB_VERSION_M       0x7
2975 #define FW_PORT_CMD_DCB_VERSION_G(x)    \
2976         (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
2977
2978 #define FW_PORT_CMD_LSTATUS32_S         31
2979 #define FW_PORT_CMD_LSTATUS32_M         0x1
2980 #define FW_PORT_CMD_LSTATUS32_V(x)      ((x) << FW_PORT_CMD_LSTATUS32_S)
2981 #define FW_PORT_CMD_LSTATUS32_G(x)      \
2982         (((x) >> FW_PORT_CMD_LSTATUS32_S) & FW_PORT_CMD_LSTATUS32_M)
2983 #define FW_PORT_CMD_LSTATUS32_F FW_PORT_CMD_LSTATUS32_V(1U)
2984
2985 #define FW_PORT_CMD_LINKDNRC32_S        28
2986 #define FW_PORT_CMD_LINKDNRC32_M        0x7
2987 #define FW_PORT_CMD_LINKDNRC32_V(x)     ((x) << FW_PORT_CMD_LINKDNRC32_S)
2988 #define FW_PORT_CMD_LINKDNRC32_G(x)     \
2989         (((x) >> FW_PORT_CMD_LINKDNRC32_S) & FW_PORT_CMD_LINKDNRC32_M)
2990
2991 #define FW_PORT_CMD_DCBXDIS32_S         27
2992 #define FW_PORT_CMD_DCBXDIS32_M         0x1
2993 #define FW_PORT_CMD_DCBXDIS32_V(x)      ((x) << FW_PORT_CMD_DCBXDIS32_S)
2994 #define FW_PORT_CMD_DCBXDIS32_G(x)      \
2995         (((x) >> FW_PORT_CMD_DCBXDIS32_S) & FW_PORT_CMD_DCBXDIS32_M)
2996 #define FW_PORT_CMD_DCBXDIS32_F FW_PORT_CMD_DCBXDIS32_V(1U)
2997
2998 #define FW_PORT_CMD_MDIOCAP32_S         26
2999 #define FW_PORT_CMD_MDIOCAP32_M         0x1
3000 #define FW_PORT_CMD_MDIOCAP32_V(x)      ((x) << FW_PORT_CMD_MDIOCAP32_S)
3001 #define FW_PORT_CMD_MDIOCAP32_G(x)      \
3002         (((x) >> FW_PORT_CMD_MDIOCAP32_S) & FW_PORT_CMD_MDIOCAP32_M)
3003 #define FW_PORT_CMD_MDIOCAP32_F FW_PORT_CMD_MDIOCAP32_V(1U)
3004
3005 #define FW_PORT_CMD_MDIOADDR32_S        21
3006 #define FW_PORT_CMD_MDIOADDR32_M        0x1f
3007 #define FW_PORT_CMD_MDIOADDR32_V(x)     ((x) << FW_PORT_CMD_MDIOADDR32_S)
3008 #define FW_PORT_CMD_MDIOADDR32_G(x)     \
3009         (((x) >> FW_PORT_CMD_MDIOADDR32_S) & FW_PORT_CMD_MDIOADDR32_M)
3010
3011 #define FW_PORT_CMD_PORTTYPE32_S        13
3012 #define FW_PORT_CMD_PORTTYPE32_M        0xff
3013 #define FW_PORT_CMD_PORTTYPE32_V(x)     ((x) << FW_PORT_CMD_PORTTYPE32_S)
3014 #define FW_PORT_CMD_PORTTYPE32_G(x)     \
3015         (((x) >> FW_PORT_CMD_PORTTYPE32_S) & FW_PORT_CMD_PORTTYPE32_M)
3016
3017 #define FW_PORT_CMD_MODTYPE32_S         8
3018 #define FW_PORT_CMD_MODTYPE32_M         0x1f
3019 #define FW_PORT_CMD_MODTYPE32_V(x)      ((x) << FW_PORT_CMD_MODTYPE32_S)
3020 #define FW_PORT_CMD_MODTYPE32_G(x)      \
3021         (((x) >> FW_PORT_CMD_MODTYPE32_S) & FW_PORT_CMD_MODTYPE32_M)
3022
3023 #define FW_PORT_CMD_CBLLEN32_S          0
3024 #define FW_PORT_CMD_CBLLEN32_M          0xff
3025 #define FW_PORT_CMD_CBLLEN32_V(x)       ((x) << FW_PORT_CMD_CBLLEN32_S)
3026 #define FW_PORT_CMD_CBLLEN32_G(x)       \
3027         (((x) >> FW_PORT_CMD_CBLLEN32_S) & FW_PORT_CMD_CBLLEN32_M)
3028
3029 #define FW_PORT_CMD_AUXLINFO32_S        24
3030 #define FW_PORT_CMD_AUXLINFO32_M        0xff
3031 #define FW_PORT_CMD_AUXLINFO32_V(x)     ((x) << FW_PORT_CMD_AUXLINFO32_S)
3032 #define FW_PORT_CMD_AUXLINFO32_G(x)     \
3033         (((x) >> FW_PORT_CMD_AUXLINFO32_S) & FW_PORT_CMD_AUXLINFO32_M)
3034
3035 #define FW_PORT_AUXLINFO32_KX4_S        2
3036 #define FW_PORT_AUXLINFO32_KX4_M        0x1
3037 #define FW_PORT_AUXLINFO32_KX4_V(x) \
3038         ((x) << FW_PORT_AUXLINFO32_KX4_S)
3039 #define FW_PORT_AUXLINFO32_KX4_G(x) \
3040         (((x) >> FW_PORT_AUXLINFO32_KX4_S) & FW_PORT_AUXLINFO32_KX4_M)
3041 #define FW_PORT_AUXLINFO32_KX4_F        FW_PORT_AUXLINFO32_KX4_V(1U)
3042
3043 #define FW_PORT_AUXLINFO32_KR_S 1
3044 #define FW_PORT_AUXLINFO32_KR_M 0x1
3045 #define FW_PORT_AUXLINFO32_KR_V(x) \
3046         ((x) << FW_PORT_AUXLINFO32_KR_S)
3047 #define FW_PORT_AUXLINFO32_KR_G(x) \
3048         (((x) >> FW_PORT_AUXLINFO32_KR_S) & FW_PORT_AUXLINFO32_KR_M)
3049 #define FW_PORT_AUXLINFO32_KR_F FW_PORT_AUXLINFO32_KR_V(1U)
3050
3051 #define FW_PORT_CMD_MTU32_S     0
3052 #define FW_PORT_CMD_MTU32_M     0xffff
3053 #define FW_PORT_CMD_MTU32_V(x)  ((x) << FW_PORT_CMD_MTU32_S)
3054 #define FW_PORT_CMD_MTU32_G(x)  \
3055         (((x) >> FW_PORT_CMD_MTU32_S) & FW_PORT_CMD_MTU32_M)
3056
3057 enum fw_port_type {
3058         FW_PORT_TYPE_FIBER_XFI,
3059         FW_PORT_TYPE_FIBER_XAUI,
3060         FW_PORT_TYPE_BT_SGMII,
3061         FW_PORT_TYPE_BT_XFI,
3062         FW_PORT_TYPE_BT_XAUI,
3063         FW_PORT_TYPE_KX4,
3064         FW_PORT_TYPE_CX4,
3065         FW_PORT_TYPE_KX,
3066         FW_PORT_TYPE_KR,
3067         FW_PORT_TYPE_SFP,
3068         FW_PORT_TYPE_BP_AP,
3069         FW_PORT_TYPE_BP4_AP,
3070         FW_PORT_TYPE_QSFP_10G,
3071         FW_PORT_TYPE_QSA,
3072         FW_PORT_TYPE_QSFP,
3073         FW_PORT_TYPE_BP40_BA,
3074         FW_PORT_TYPE_KR4_100G,
3075         FW_PORT_TYPE_CR4_QSFP,
3076         FW_PORT_TYPE_CR_QSFP,
3077         FW_PORT_TYPE_CR2_QSFP,
3078         FW_PORT_TYPE_SFP28,
3079         FW_PORT_TYPE_KR_SFP28,
3080         FW_PORT_TYPE_KR_XLAUI,
3081
3082         FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
3083 };
3084
3085 enum fw_port_module_type {
3086         FW_PORT_MOD_TYPE_NA,
3087         FW_PORT_MOD_TYPE_LR,
3088         FW_PORT_MOD_TYPE_SR,
3089         FW_PORT_MOD_TYPE_ER,
3090         FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
3091         FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
3092         FW_PORT_MOD_TYPE_LRM,
3093         FW_PORT_MOD_TYPE_ERROR          = FW_PORT_CMD_MODTYPE_M - 3,
3094         FW_PORT_MOD_TYPE_UNKNOWN        = FW_PORT_CMD_MODTYPE_M - 2,
3095         FW_PORT_MOD_TYPE_NOTSUPPORTED   = FW_PORT_CMD_MODTYPE_M - 1,
3096
3097         FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M
3098 };
3099
3100 enum fw_port_mod_sub_type {
3101         FW_PORT_MOD_SUB_TYPE_NA,
3102         FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
3103         FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
3104         FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
3105         FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
3106         FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
3107         FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
3108
3109         /* The following will never been in the VPD.  They are TWINAX cable
3110          * lengths decoded from SFP+ module i2c PROMs.  These should
3111          * almost certainly go somewhere else ...
3112          */
3113         FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
3114         FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
3115         FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
3116         FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
3117 };
3118
3119 enum fw_port_stats_tx_index {
3120         FW_STAT_TX_PORT_BYTES_IX = 0,
3121         FW_STAT_TX_PORT_FRAMES_IX,
3122         FW_STAT_TX_PORT_BCAST_IX,
3123         FW_STAT_TX_PORT_MCAST_IX,
3124         FW_STAT_TX_PORT_UCAST_IX,
3125         FW_STAT_TX_PORT_ERROR_IX,
3126         FW_STAT_TX_PORT_64B_IX,
3127         FW_STAT_TX_PORT_65B_127B_IX,
3128         FW_STAT_TX_PORT_128B_255B_IX,
3129         FW_STAT_TX_PORT_256B_511B_IX,
3130         FW_STAT_TX_PORT_512B_1023B_IX,
3131         FW_STAT_TX_PORT_1024B_1518B_IX,
3132         FW_STAT_TX_PORT_1519B_MAX_IX,
3133         FW_STAT_TX_PORT_DROP_IX,
3134         FW_STAT_TX_PORT_PAUSE_IX,
3135         FW_STAT_TX_PORT_PPP0_IX,
3136         FW_STAT_TX_PORT_PPP1_IX,
3137         FW_STAT_TX_PORT_PPP2_IX,
3138         FW_STAT_TX_PORT_PPP3_IX,
3139         FW_STAT_TX_PORT_PPP4_IX,
3140         FW_STAT_TX_PORT_PPP5_IX,
3141         FW_STAT_TX_PORT_PPP6_IX,
3142         FW_STAT_TX_PORT_PPP7_IX,
3143         FW_NUM_PORT_TX_STATS
3144 };
3145
3146 enum fw_port_stat_rx_index {
3147         FW_STAT_RX_PORT_BYTES_IX = 0,
3148         FW_STAT_RX_PORT_FRAMES_IX,
3149         FW_STAT_RX_PORT_BCAST_IX,
3150         FW_STAT_RX_PORT_MCAST_IX,
3151         FW_STAT_RX_PORT_UCAST_IX,
3152         FW_STAT_RX_PORT_MTU_ERROR_IX,
3153         FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
3154         FW_STAT_RX_PORT_CRC_ERROR_IX,
3155         FW_STAT_RX_PORT_LEN_ERROR_IX,
3156         FW_STAT_RX_PORT_SYM_ERROR_IX,
3157         FW_STAT_RX_PORT_64B_IX,
3158         FW_STAT_RX_PORT_65B_127B_IX,
3159         FW_STAT_RX_PORT_128B_255B_IX,
3160         FW_STAT_RX_PORT_256B_511B_IX,
3161         FW_STAT_RX_PORT_512B_1023B_IX,
3162         FW_STAT_RX_PORT_1024B_1518B_IX,
3163         FW_STAT_RX_PORT_1519B_MAX_IX,
3164         FW_STAT_RX_PORT_PAUSE_IX,
3165         FW_STAT_RX_PORT_PPP0_IX,
3166         FW_STAT_RX_PORT_PPP1_IX,
3167         FW_STAT_RX_PORT_PPP2_IX,
3168         FW_STAT_RX_PORT_PPP3_IX,
3169         FW_STAT_RX_PORT_PPP4_IX,
3170         FW_STAT_RX_PORT_PPP5_IX,
3171         FW_STAT_RX_PORT_PPP6_IX,
3172         FW_STAT_RX_PORT_PPP7_IX,
3173         FW_STAT_RX_PORT_LESS_64B_IX,
3174         FW_STAT_RX_PORT_MAC_ERROR_IX,
3175         FW_NUM_PORT_RX_STATS
3176 };
3177
3178 /* port stats */
3179 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + FW_NUM_PORT_RX_STATS)
3180
3181 struct fw_port_stats_cmd {
3182         __be32 op_to_portid;
3183         __be32 retval_len16;
3184         union fw_port_stats {
3185                 struct fw_port_stats_ctl {
3186                         u8 nstats_bg_bm;
3187                         u8 tx_ix;
3188                         __be16 r6;
3189                         __be32 r7;
3190                         __be64 stat0;
3191                         __be64 stat1;
3192                         __be64 stat2;
3193                         __be64 stat3;
3194                         __be64 stat4;
3195                         __be64 stat5;
3196                 } ctl;
3197                 struct fw_port_stats_all {
3198                         __be64 tx_bytes;
3199                         __be64 tx_frames;
3200                         __be64 tx_bcast;
3201                         __be64 tx_mcast;
3202                         __be64 tx_ucast;
3203                         __be64 tx_error;
3204                         __be64 tx_64b;
3205                         __be64 tx_65b_127b;
3206                         __be64 tx_128b_255b;
3207                         __be64 tx_256b_511b;
3208                         __be64 tx_512b_1023b;
3209                         __be64 tx_1024b_1518b;
3210                         __be64 tx_1519b_max;
3211                         __be64 tx_drop;
3212                         __be64 tx_pause;
3213                         __be64 tx_ppp0;
3214                         __be64 tx_ppp1;
3215                         __be64 tx_ppp2;
3216                         __be64 tx_ppp3;
3217                         __be64 tx_ppp4;
3218                         __be64 tx_ppp5;
3219                         __be64 tx_ppp6;
3220                         __be64 tx_ppp7;
3221                         __be64 rx_bytes;
3222                         __be64 rx_frames;
3223                         __be64 rx_bcast;
3224                         __be64 rx_mcast;
3225                         __be64 rx_ucast;
3226                         __be64 rx_mtu_error;
3227                         __be64 rx_mtu_crc_error;
3228                         __be64 rx_crc_error;
3229                         __be64 rx_len_error;
3230                         __be64 rx_sym_error;
3231                         __be64 rx_64b;
3232                         __be64 rx_65b_127b;
3233                         __be64 rx_128b_255b;
3234                         __be64 rx_256b_511b;
3235                         __be64 rx_512b_1023b;
3236                         __be64 rx_1024b_1518b;
3237                         __be64 rx_1519b_max;
3238                         __be64 rx_pause;
3239                         __be64 rx_ppp0;
3240                         __be64 rx_ppp1;
3241                         __be64 rx_ppp2;
3242                         __be64 rx_ppp3;
3243                         __be64 rx_ppp4;
3244                         __be64 rx_ppp5;
3245                         __be64 rx_ppp6;
3246                         __be64 rx_ppp7;
3247                         __be64 rx_less_64b;
3248                         __be64 rx_bg_drop;
3249                         __be64 rx_bg_trunc;
3250                 } all;
3251         } u;
3252 };
3253
3254 /* port loopback stats */
3255 #define FW_NUM_LB_STATS 16
3256 enum fw_port_lb_stats_index {
3257         FW_STAT_LB_PORT_BYTES_IX,
3258         FW_STAT_LB_PORT_FRAMES_IX,
3259         FW_STAT_LB_PORT_BCAST_IX,
3260         FW_STAT_LB_PORT_MCAST_IX,
3261         FW_STAT_LB_PORT_UCAST_IX,
3262         FW_STAT_LB_PORT_ERROR_IX,
3263         FW_STAT_LB_PORT_64B_IX,
3264         FW_STAT_LB_PORT_65B_127B_IX,
3265         FW_STAT_LB_PORT_128B_255B_IX,
3266         FW_STAT_LB_PORT_256B_511B_IX,
3267         FW_STAT_LB_PORT_512B_1023B_IX,
3268         FW_STAT_LB_PORT_1024B_1518B_IX,
3269         FW_STAT_LB_PORT_1519B_MAX_IX,
3270         FW_STAT_LB_PORT_DROP_FRAMES_IX
3271 };
3272
3273 struct fw_port_lb_stats_cmd {
3274         __be32 op_to_lbport;
3275         __be32 retval_len16;
3276         union fw_port_lb_stats {
3277                 struct fw_port_lb_stats_ctl {
3278                         u8 nstats_bg_bm;
3279                         u8 ix_pkd;
3280                         __be16 r6;
3281                         __be32 r7;
3282                         __be64 stat0;
3283                         __be64 stat1;
3284                         __be64 stat2;
3285                         __be64 stat3;
3286                         __be64 stat4;
3287                         __be64 stat5;
3288                 } ctl;
3289                 struct fw_port_lb_stats_all {
3290                         __be64 tx_bytes;
3291                         __be64 tx_frames;
3292                         __be64 tx_bcast;
3293                         __be64 tx_mcast;
3294                         __be64 tx_ucast;
3295                         __be64 tx_error;
3296                         __be64 tx_64b;
3297                         __be64 tx_65b_127b;
3298                         __be64 tx_128b_255b;
3299                         __be64 tx_256b_511b;
3300                         __be64 tx_512b_1023b;
3301                         __be64 tx_1024b_1518b;
3302                         __be64 tx_1519b_max;
3303                         __be64 rx_lb_drop;
3304                         __be64 rx_lb_trunc;
3305                 } all;
3306         } u;
3307 };
3308
3309 enum fw_ptp_subop {
3310         /* none */
3311         FW_PTP_SC_INIT_TIMER            = 0x00,
3312         FW_PTP_SC_TX_TYPE               = 0x01,
3313         /* init */
3314         FW_PTP_SC_RXTIME_STAMP          = 0x08,
3315         FW_PTP_SC_RDRX_TYPE             = 0x09,
3316         /* ts */
3317         FW_PTP_SC_ADJ_FREQ              = 0x10,
3318         FW_PTP_SC_ADJ_TIME              = 0x11,
3319         FW_PTP_SC_ADJ_FTIME             = 0x12,
3320         FW_PTP_SC_WALL_CLOCK            = 0x13,
3321         FW_PTP_SC_GET_TIME              = 0x14,
3322         FW_PTP_SC_SET_TIME              = 0x15,
3323 };
3324
3325 struct fw_ptp_cmd {
3326         __be32 op_to_portid;
3327         __be32 retval_len16;
3328         union fw_ptp {
3329                 struct fw_ptp_sc {
3330                         __u8   sc;
3331                         __u8   r3[7];
3332                 } scmd;
3333                 struct fw_ptp_init {
3334                         __u8   sc;
3335                         __u8   txchan;
3336                         __be16 absid;
3337                         __be16 mode;
3338                         __be16 r3;
3339                 } init;
3340                 struct fw_ptp_ts {
3341                         __u8   sc;
3342                         __u8   sign;
3343                         __be16 r3;
3344                         __be32 ppb;
3345                         __be64 tm;
3346                 } ts;
3347         } u;
3348         __be64 r3;
3349 };
3350
3351 #define FW_PTP_CMD_PORTID_S             0
3352 #define FW_PTP_CMD_PORTID_M             0xf
3353 #define FW_PTP_CMD_PORTID_V(x)          ((x) << FW_PTP_CMD_PORTID_S)
3354 #define FW_PTP_CMD_PORTID_G(x)          \
3355         (((x) >> FW_PTP_CMD_PORTID_S) & FW_PTP_CMD_PORTID_M)
3356
3357 struct fw_rss_ind_tbl_cmd {
3358         __be32 op_to_viid;
3359         __be32 retval_len16;
3360         __be16 niqid;
3361         __be16 startidx;
3362         __be32 r3;
3363         __be32 iq0_to_iq2;
3364         __be32 iq3_to_iq5;
3365         __be32 iq6_to_iq8;
3366         __be32 iq9_to_iq11;
3367         __be32 iq12_to_iq14;
3368         __be32 iq15_to_iq17;
3369         __be32 iq18_to_iq20;
3370         __be32 iq21_to_iq23;
3371         __be32 iq24_to_iq26;
3372         __be32 iq27_to_iq29;
3373         __be32 iq30_iq31;
3374         __be32 r15_lo;
3375 };
3376
3377 #define FW_RSS_IND_TBL_CMD_VIID_S       0
3378 #define FW_RSS_IND_TBL_CMD_VIID_V(x)    ((x) << FW_RSS_IND_TBL_CMD_VIID_S)
3379
3380 #define FW_RSS_IND_TBL_CMD_IQ0_S        20
3381 #define FW_RSS_IND_TBL_CMD_IQ0_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
3382
3383 #define FW_RSS_IND_TBL_CMD_IQ1_S        10
3384 #define FW_RSS_IND_TBL_CMD_IQ1_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
3385
3386 #define FW_RSS_IND_TBL_CMD_IQ2_S        0
3387 #define FW_RSS_IND_TBL_CMD_IQ2_V(x)     ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
3388
3389 struct fw_rss_glb_config_cmd {
3390         __be32 op_to_write;
3391         __be32 retval_len16;
3392         union fw_rss_glb_config {
3393                 struct fw_rss_glb_config_manual {
3394                         __be32 mode_pkd;
3395                         __be32 r3;
3396                         __be64 r4;
3397                         __be64 r5;
3398                 } manual;
3399                 struct fw_rss_glb_config_basicvirtual {
3400                         __be32 mode_pkd;
3401                         __be32 synmapen_to_hashtoeplitz;
3402                         __be64 r8;
3403                         __be64 r9;
3404                 } basicvirtual;
3405         } u;
3406 };
3407
3408 #define FW_RSS_GLB_CONFIG_CMD_MODE_S    28
3409 #define FW_RSS_GLB_CONFIG_CMD_MODE_M    0xf
3410 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
3411 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \
3412         (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
3413
3414 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL       0
3415 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
3416
3417 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S        8
3418 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x)     \
3419         ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
3420 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F        \
3421         FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
3422
3423 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S           7
3424 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x)        \
3425         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
3426 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F   \
3427         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
3428
3429 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S           6
3430 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x)        \
3431         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
3432 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F   \
3433         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
3434
3435 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S           5
3436 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x)        \
3437         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
3438 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F   \
3439         FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
3440
3441 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S           4
3442 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x)        \
3443         ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
3444 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F   \
3445         FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
3446
3447 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S        3
3448 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x)     \
3449         ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
3450 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F        \
3451         FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
3452
3453 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S        2
3454 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x)     \
3455         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
3456 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F        \
3457         FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
3458
3459 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S       1
3460 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x)    \
3461         ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
3462 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F       \
3463         FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
3464
3465 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S    0
3466 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \
3467         ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
3468 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F    \
3469         FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
3470
3471 struct fw_rss_vi_config_cmd {
3472         __be32 op_to_viid;
3473 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
3474         __be32 retval_len16;
3475         union fw_rss_vi_config {
3476                 struct fw_rss_vi_config_manual {
3477                         __be64 r3;
3478                         __be64 r4;
3479                         __be64 r5;
3480                 } manual;
3481                 struct fw_rss_vi_config_basicvirtual {
3482                         __be32 r6;
3483                         __be32 defaultq_to_udpen;
3484                         __be64 r9;
3485                         __be64 r10;
3486                 } basicvirtual;
3487         } u;
3488 };
3489
3490 #define FW_RSS_VI_CONFIG_CMD_VIID_S     0
3491 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x)  ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
3492
3493 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S         16
3494 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M         0x3ff
3495 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x)      \
3496         ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
3497 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x)      \
3498         (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
3499          FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
3500
3501 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S     4
3502 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x)  \
3503         ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
3504 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F     \
3505         FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
3506
3507 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S      3
3508 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x)   \
3509         ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
3510 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F      \
3511         FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
3512
3513 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S     2
3514 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x)  \
3515         ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
3516 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F     \
3517         FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
3518
3519 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S      1
3520 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x)   \
3521         ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
3522 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F      \
3523         FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
3524
3525 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S    0
3526 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
3527 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F    FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
3528
3529 enum fw_sched_sc {
3530         FW_SCHED_SC_PARAMS              = 1,
3531 };
3532
3533 struct fw_sched_cmd {
3534         __be32 op_to_write;
3535         __be32 retval_len16;
3536         union fw_sched {
3537                 struct fw_sched_config {
3538                         __u8   sc;
3539                         __u8   type;
3540                         __u8   minmaxen;
3541                         __u8   r3[5];
3542                         __u8   nclasses[4];
3543                         __be32 r4;
3544                 } config;
3545                 struct fw_sched_params {
3546                         __u8   sc;
3547                         __u8   type;
3548                         __u8   level;
3549                         __u8   mode;
3550                         __u8   unit;
3551                         __u8   rate;
3552                         __u8   ch;
3553                         __u8   cl;
3554                         __be32 min;
3555                         __be32 max;
3556                         __be16 weight;
3557                         __be16 pktsize;
3558                         __be16 burstsize;
3559                         __be16 r4;
3560                 } params;
3561         } u;
3562 };
3563
3564 struct fw_clip_cmd {
3565         __be32 op_to_write;
3566         __be32 alloc_to_len16;
3567         __be64 ip_hi;
3568         __be64 ip_lo;
3569         __be32 r4[2];
3570 };
3571
3572 #define FW_CLIP_CMD_ALLOC_S     31
3573 #define FW_CLIP_CMD_ALLOC_V(x)  ((x) << FW_CLIP_CMD_ALLOC_S)
3574 #define FW_CLIP_CMD_ALLOC_F     FW_CLIP_CMD_ALLOC_V(1U)
3575
3576 #define FW_CLIP_CMD_FREE_S      30
3577 #define FW_CLIP_CMD_FREE_V(x)   ((x) << FW_CLIP_CMD_FREE_S)
3578 #define FW_CLIP_CMD_FREE_F      FW_CLIP_CMD_FREE_V(1U)
3579
3580 enum fw_error_type {
3581         FW_ERROR_TYPE_EXCEPTION         = 0x0,
3582         FW_ERROR_TYPE_HWMODULE          = 0x1,
3583         FW_ERROR_TYPE_WR                = 0x2,
3584         FW_ERROR_TYPE_ACL               = 0x3,
3585 };
3586
3587 struct fw_error_cmd {
3588         __be32 op_to_type;
3589         __be32 len16_pkd;
3590         union fw_error {
3591                 struct fw_error_exception {
3592                         __be32 info[6];
3593                 } exception;
3594                 struct fw_error_hwmodule {
3595                         __be32 regaddr;
3596                         __be32 regval;
3597                 } hwmodule;
3598                 struct fw_error_wr {
3599                         __be16 cidx;
3600                         __be16 pfn_vfn;
3601                         __be32 eqid;
3602                         u8 wrhdr[16];
3603                 } wr;
3604                 struct fw_error_acl {
3605                         __be16 cidx;
3606                         __be16 pfn_vfn;
3607                         __be32 eqid;
3608                         __be16 mv_pkd;
3609                         u8 val[6];
3610                         __be64 r4;
3611                 } acl;
3612         } u;
3613 };
3614
3615 struct fw_debug_cmd {
3616         __be32 op_type;
3617         __be32 len16_pkd;
3618         union fw_debug {
3619                 struct fw_debug_assert {
3620                         __be32 fcid;
3621                         __be32 line;
3622                         __be32 x;
3623                         __be32 y;
3624                         u8 filename_0_7[8];
3625                         u8 filename_8_15[8];
3626                         __be64 r3;
3627                 } assert;
3628                 struct fw_debug_prt {
3629                         __be16 dprtstridx;
3630                         __be16 r3[3];
3631                         __be32 dprtstrparam0;
3632                         __be32 dprtstrparam1;
3633                         __be32 dprtstrparam2;
3634                         __be32 dprtstrparam3;
3635                 } prt;
3636         } u;
3637 };
3638
3639 #define FW_DEBUG_CMD_TYPE_S     0
3640 #define FW_DEBUG_CMD_TYPE_M     0xff
3641 #define FW_DEBUG_CMD_TYPE_G(x)  \
3642         (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
3643
3644 struct fw_hma_cmd {
3645         __be32 op_pkd;
3646         __be32 retval_len16;
3647         __be32 mode_to_pcie_params;
3648         __be32 naddr_size;
3649         __be32 addr_size_pkd;
3650         __be32 r6;
3651         __be64 phy_address[5];
3652 };
3653
3654 #define FW_HMA_CMD_MODE_S       31
3655 #define FW_HMA_CMD_MODE_M       0x1
3656 #define FW_HMA_CMD_MODE_V(x)    ((x) << FW_HMA_CMD_MODE_S)
3657 #define FW_HMA_CMD_MODE_G(x)    \
3658         (((x) >> FW_HMA_CMD_MODE_S) & FW_HMA_CMD_MODE_M)
3659 #define FW_HMA_CMD_MODE_F       FW_HMA_CMD_MODE_V(1U)
3660
3661 #define FW_HMA_CMD_SOC_S        30
3662 #define FW_HMA_CMD_SOC_M        0x1
3663 #define FW_HMA_CMD_SOC_V(x)     ((x) << FW_HMA_CMD_SOC_S)
3664 #define FW_HMA_CMD_SOC_G(x)     (((x) >> FW_HMA_CMD_SOC_S) & FW_HMA_CMD_SOC_M)
3665 #define FW_HMA_CMD_SOC_F        FW_HMA_CMD_SOC_V(1U)
3666
3667 #define FW_HMA_CMD_EOC_S        29
3668 #define FW_HMA_CMD_EOC_M        0x1
3669 #define FW_HMA_CMD_EOC_V(x)     ((x) << FW_HMA_CMD_EOC_S)
3670 #define FW_HMA_CMD_EOC_G(x)     (((x) >> FW_HMA_CMD_EOC_S) & FW_HMA_CMD_EOC_M)
3671 #define FW_HMA_CMD_EOC_F        FW_HMA_CMD_EOC_V(1U)
3672
3673 #define FW_HMA_CMD_PCIE_PARAMS_S        0
3674 #define FW_HMA_CMD_PCIE_PARAMS_M        0x7ffffff
3675 #define FW_HMA_CMD_PCIE_PARAMS_V(x)     ((x) << FW_HMA_CMD_PCIE_PARAMS_S)
3676 #define FW_HMA_CMD_PCIE_PARAMS_G(x)     \
3677         (((x) >> FW_HMA_CMD_PCIE_PARAMS_S) & FW_HMA_CMD_PCIE_PARAMS_M)
3678
3679 #define FW_HMA_CMD_NADDR_S      12
3680 #define FW_HMA_CMD_NADDR_M      0x3f
3681 #define FW_HMA_CMD_NADDR_V(x)   ((x) << FW_HMA_CMD_NADDR_S)
3682 #define FW_HMA_CMD_NADDR_G(x)   \
3683         (((x) >> FW_HMA_CMD_NADDR_S) & FW_HMA_CMD_NADDR_M)
3684
3685 #define FW_HMA_CMD_SIZE_S       0
3686 #define FW_HMA_CMD_SIZE_M       0xfff
3687 #define FW_HMA_CMD_SIZE_V(x)    ((x) << FW_HMA_CMD_SIZE_S)
3688 #define FW_HMA_CMD_SIZE_G(x)    \
3689         (((x) >> FW_HMA_CMD_SIZE_S) & FW_HMA_CMD_SIZE_M)
3690
3691 #define FW_HMA_CMD_ADDR_SIZE_S          11
3692 #define FW_HMA_CMD_ADDR_SIZE_M          0x1fffff
3693 #define FW_HMA_CMD_ADDR_SIZE_V(x)       ((x) << FW_HMA_CMD_ADDR_SIZE_S)
3694 #define FW_HMA_CMD_ADDR_SIZE_G(x)       \
3695         (((x) >> FW_HMA_CMD_ADDR_SIZE_S) & FW_HMA_CMD_ADDR_SIZE_M)
3696
3697 enum pcie_fw_eval {
3698         PCIE_FW_EVAL_CRASH = 0,
3699 };
3700
3701 #define PCIE_FW_ERR_S           31
3702 #define PCIE_FW_ERR_V(x)        ((x) << PCIE_FW_ERR_S)
3703 #define PCIE_FW_ERR_F           PCIE_FW_ERR_V(1U)
3704
3705 #define PCIE_FW_INIT_S          30
3706 #define PCIE_FW_INIT_V(x)       ((x) << PCIE_FW_INIT_S)
3707 #define PCIE_FW_INIT_F          PCIE_FW_INIT_V(1U)
3708
3709 #define PCIE_FW_HALT_S          29
3710 #define PCIE_FW_HALT_V(x)       ((x) << PCIE_FW_HALT_S)
3711 #define PCIE_FW_HALT_F          PCIE_FW_HALT_V(1U)
3712
3713 #define PCIE_FW_EVAL_S          24
3714 #define PCIE_FW_EVAL_M          0x7
3715 #define PCIE_FW_EVAL_G(x)       (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
3716
3717 #define PCIE_FW_MASTER_VLD_S    15
3718 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)
3719 #define PCIE_FW_MASTER_VLD_F    PCIE_FW_MASTER_VLD_V(1U)
3720
3721 #define PCIE_FW_MASTER_S        12
3722 #define PCIE_FW_MASTER_M        0x7
3723 #define PCIE_FW_MASTER_V(x)     ((x) << PCIE_FW_MASTER_S)
3724 #define PCIE_FW_MASTER_G(x)     (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
3725
3726 struct fw_hdr {
3727         u8 ver;
3728         u8 chip;                        /* terminator chip type */
3729         __be16  len512;                 /* bin length in units of 512-bytes */
3730         __be32  fw_ver;                 /* firmware version */
3731         __be32  tp_microcode_ver;
3732         u8 intfver_nic;
3733         u8 intfver_vnic;
3734         u8 intfver_ofld;
3735         u8 intfver_ri;
3736         u8 intfver_iscsipdu;
3737         u8 intfver_iscsi;
3738         u8 intfver_fcoepdu;
3739         u8 intfver_fcoe;
3740         __u32   reserved2;
3741         __u32   reserved3;
3742         __u32   reserved4;
3743         __be32  flags;
3744         __be32  reserved6[23];
3745 };
3746
3747 enum fw_hdr_chip {
3748         FW_HDR_CHIP_T4,
3749         FW_HDR_CHIP_T5,
3750         FW_HDR_CHIP_T6
3751 };
3752
3753 #define FW_HDR_FW_VER_MAJOR_S   24
3754 #define FW_HDR_FW_VER_MAJOR_M   0xff
3755 #define FW_HDR_FW_VER_MAJOR_V(x) \
3756         ((x) << FW_HDR_FW_VER_MAJOR_S)
3757 #define FW_HDR_FW_VER_MAJOR_G(x) \
3758         (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3759
3760 #define FW_HDR_FW_VER_MINOR_S   16
3761 #define FW_HDR_FW_VER_MINOR_M   0xff
3762 #define FW_HDR_FW_VER_MINOR_V(x) \
3763         ((x) << FW_HDR_FW_VER_MINOR_S)
3764 #define FW_HDR_FW_VER_MINOR_G(x) \
3765         (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3766
3767 #define FW_HDR_FW_VER_MICRO_S   8
3768 #define FW_HDR_FW_VER_MICRO_M   0xff
3769 #define FW_HDR_FW_VER_MICRO_V(x) \
3770         ((x) << FW_HDR_FW_VER_MICRO_S)
3771 #define FW_HDR_FW_VER_MICRO_G(x) \
3772         (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3773
3774 #define FW_HDR_FW_VER_BUILD_S   0
3775 #define FW_HDR_FW_VER_BUILD_M   0xff
3776 #define FW_HDR_FW_VER_BUILD_V(x) \
3777         ((x) << FW_HDR_FW_VER_BUILD_S)
3778 #define FW_HDR_FW_VER_BUILD_G(x) \
3779         (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3780
3781 enum fw_hdr_intfver {
3782         FW_HDR_INTFVER_NIC      = 0x00,
3783         FW_HDR_INTFVER_VNIC     = 0x00,
3784         FW_HDR_INTFVER_OFLD     = 0x00,
3785         FW_HDR_INTFVER_RI       = 0x00,
3786         FW_HDR_INTFVER_ISCSIPDU = 0x00,
3787         FW_HDR_INTFVER_ISCSI    = 0x00,
3788         FW_HDR_INTFVER_FCOEPDU  = 0x00,
3789         FW_HDR_INTFVER_FCOE     = 0x00,
3790 };
3791
3792 enum fw_hdr_flags {
3793         FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3794 };
3795
3796 /* length of the formatting string  */
3797 #define FW_DEVLOG_FMT_LEN       192
3798
3799 /* maximum number of the formatting string parameters */
3800 #define FW_DEVLOG_FMT_PARAMS_NUM 8
3801
3802 /* priority levels */
3803 enum fw_devlog_level {
3804         FW_DEVLOG_LEVEL_EMERG   = 0x0,
3805         FW_DEVLOG_LEVEL_CRIT    = 0x1,
3806         FW_DEVLOG_LEVEL_ERR     = 0x2,
3807         FW_DEVLOG_LEVEL_NOTICE  = 0x3,
3808         FW_DEVLOG_LEVEL_INFO    = 0x4,
3809         FW_DEVLOG_LEVEL_DEBUG   = 0x5,
3810         FW_DEVLOG_LEVEL_MAX     = 0x5,
3811 };
3812
3813 /* facilities that may send a log message */
3814 enum fw_devlog_facility {
3815         FW_DEVLOG_FACILITY_CORE         = 0x00,
3816         FW_DEVLOG_FACILITY_CF           = 0x01,
3817         FW_DEVLOG_FACILITY_SCHED        = 0x02,
3818         FW_DEVLOG_FACILITY_TIMER        = 0x04,
3819         FW_DEVLOG_FACILITY_RES          = 0x06,
3820         FW_DEVLOG_FACILITY_HW           = 0x08,
3821         FW_DEVLOG_FACILITY_FLR          = 0x10,
3822         FW_DEVLOG_FACILITY_DMAQ         = 0x12,
3823         FW_DEVLOG_FACILITY_PHY          = 0x14,
3824         FW_DEVLOG_FACILITY_MAC          = 0x16,
3825         FW_DEVLOG_FACILITY_PORT         = 0x18,
3826         FW_DEVLOG_FACILITY_VI           = 0x1A,
3827         FW_DEVLOG_FACILITY_FILTER       = 0x1C,
3828         FW_DEVLOG_FACILITY_ACL          = 0x1E,
3829         FW_DEVLOG_FACILITY_TM           = 0x20,
3830         FW_DEVLOG_FACILITY_QFC          = 0x22,
3831         FW_DEVLOG_FACILITY_DCB          = 0x24,
3832         FW_DEVLOG_FACILITY_ETH          = 0x26,
3833         FW_DEVLOG_FACILITY_OFLD         = 0x28,
3834         FW_DEVLOG_FACILITY_RI           = 0x2A,
3835         FW_DEVLOG_FACILITY_ISCSI        = 0x2C,
3836         FW_DEVLOG_FACILITY_FCOE         = 0x2E,
3837         FW_DEVLOG_FACILITY_FOISCSI      = 0x30,
3838         FW_DEVLOG_FACILITY_FOFCOE       = 0x32,
3839         FW_DEVLOG_FACILITY_CHNET        = 0x34,
3840         FW_DEVLOG_FACILITY_MAX          = 0x34,
3841 };
3842
3843 /* log message format */
3844 struct fw_devlog_e {
3845         __be64  timestamp;
3846         __be32  seqno;
3847         __be16  reserved1;
3848         __u8    level;
3849         __u8    facility;
3850         __u8    fmt[FW_DEVLOG_FMT_LEN];
3851         __be32  params[FW_DEVLOG_FMT_PARAMS_NUM];
3852         __be32  reserved3[4];
3853 };
3854
3855 struct fw_devlog_cmd {
3856         __be32 op_to_write;
3857         __be32 retval_len16;
3858         __u8   level;
3859         __u8   r2[7];
3860         __be32 memtype_devlog_memaddr16_devlog;
3861         __be32 memsize_devlog;
3862         __be32 r3[2];
3863 };
3864
3865 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S          28
3866 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M          0xf
3867 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x)       \
3868         (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
3869          FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
3870
3871 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S        0
3872 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M        0xfffffff
3873 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x)     \
3874         (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
3875          FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
3876
3877 /* P C I E   F W   P F 7   R E G I S T E R */
3878
3879 /* PF7 stores the Firmware Device Log parameters which allows Host Drivers to
3880  * access the "devlog" which needing to contact firmware.  The encoding is
3881  * mostly the same as that returned by the DEVLOG command except for the size
3882  * which is encoded as the number of entries in multiples-1 of 128 here rather
3883  * than the memory size as is done in the DEVLOG command.  Thus, 0 means 128
3884  * and 15 means 2048.  This of course in turn constrains the allowed values
3885  * for the devlog size ...
3886  */
3887 #define PCIE_FW_PF_DEVLOG               7
3888
3889 #define PCIE_FW_PF_DEVLOG_NENTRIES128_S 28
3890 #define PCIE_FW_PF_DEVLOG_NENTRIES128_M 0xf
3891 #define PCIE_FW_PF_DEVLOG_NENTRIES128_V(x) \
3892         ((x) << PCIE_FW_PF_DEVLOG_NENTRIES128_S)
3893 #define PCIE_FW_PF_DEVLOG_NENTRIES128_G(x) \
3894         (((x) >> PCIE_FW_PF_DEVLOG_NENTRIES128_S) & \
3895          PCIE_FW_PF_DEVLOG_NENTRIES128_M)
3896
3897 #define PCIE_FW_PF_DEVLOG_ADDR16_S      4
3898 #define PCIE_FW_PF_DEVLOG_ADDR16_M      0xffffff
3899 #define PCIE_FW_PF_DEVLOG_ADDR16_V(x)   ((x) << PCIE_FW_PF_DEVLOG_ADDR16_S)
3900 #define PCIE_FW_PF_DEVLOG_ADDR16_G(x) \
3901         (((x) >> PCIE_FW_PF_DEVLOG_ADDR16_S) & PCIE_FW_PF_DEVLOG_ADDR16_M)
3902
3903 #define PCIE_FW_PF_DEVLOG_MEMTYPE_S     0
3904 #define PCIE_FW_PF_DEVLOG_MEMTYPE_M     0xf
3905 #define PCIE_FW_PF_DEVLOG_MEMTYPE_V(x)  ((x) << PCIE_FW_PF_DEVLOG_MEMTYPE_S)
3906 #define PCIE_FW_PF_DEVLOG_MEMTYPE_G(x) \
3907         (((x) >> PCIE_FW_PF_DEVLOG_MEMTYPE_S) & PCIE_FW_PF_DEVLOG_MEMTYPE_M)
3908
3909 #define MAX_IMM_OFLD_TX_DATA_WR_LEN (0xff + sizeof(struct fw_ofld_tx_data_wr))
3910
3911 struct fw_crypto_lookaside_wr {
3912         __be32 op_to_cctx_size;
3913         __be32 len16_pkd;
3914         __be32 session_id;
3915         __be32 rx_chid_to_rx_q_id;
3916         __be32 key_addr;
3917         __be32 pld_size_hash_size;
3918         __be64 cookie;
3919 };
3920
3921 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_S 24
3922 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_M 0xff
3923 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_V(x) \
3924         ((x) << FW_CRYPTO_LOOKASIDE_WR_OPCODE_S)
3925 #define FW_CRYPTO_LOOKASIDE_WR_OPCODE_G(x) \
3926         (((x) >> FW_CRYPTO_LOOKASIDE_WR_OPCODE_S) & \
3927          FW_CRYPTO_LOOKASIDE_WR_OPCODE_M)
3928
3929 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_S 23
3930 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_M 0x1
3931 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_V(x) \
3932         ((x) << FW_CRYPTO_LOOKASIDE_WR_COMPL_S)
3933 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_G(x) \
3934         (((x) >> FW_CRYPTO_LOOKASIDE_WR_COMPL_S) & \
3935          FW_CRYPTO_LOOKASIDE_WR_COMPL_M)
3936 #define FW_CRYPTO_LOOKASIDE_WR_COMPL_F FW_CRYPTO_LOOKASIDE_WR_COMPL_V(1U)
3937
3938 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S 15
3939 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M 0xff
3940 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_V(x) \
3941         ((x) << FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S)
3942 #define FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_G(x) \
3943         (((x) >> FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_S) & \
3944          FW_CRYPTO_LOOKASIDE_WR_IMM_LEN_M)
3945
3946 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S 5
3947 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M 0x3
3948 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_V(x) \
3949         ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S)
3950 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_G(x) \
3951         (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_S) & \
3952          FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC_M)
3953
3954 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S 0
3955 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M 0x1f
3956 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_V(x) \
3957         ((x) << FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S)
3958 #define FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_G(x) \
3959         (((x) >> FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_S) & \
3960          FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE_M)
3961
3962 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_S 0
3963 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_M 0xff
3964 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_V(x) \
3965         ((x) << FW_CRYPTO_LOOKASIDE_WR_LEN16_S)
3966 #define FW_CRYPTO_LOOKASIDE_WR_LEN16_G(x) \
3967         (((x) >> FW_CRYPTO_LOOKASIDE_WR_LEN16_S) & \
3968          FW_CRYPTO_LOOKASIDE_WR_LEN16_M)
3969
3970 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S 29
3971 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M 0x3
3972 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_V(x) \
3973         ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S)
3974 #define FW_CRYPTO_LOOKASIDE_WR_RX_CHID_G(x) \
3975         (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_CHID_S) & \
3976          FW_CRYPTO_LOOKASIDE_WR_RX_CHID_M)
3977
3978 #define FW_CRYPTO_LOOKASIDE_WR_LCB_S  27
3979 #define FW_CRYPTO_LOOKASIDE_WR_LCB_M  0x3
3980 #define FW_CRYPTO_LOOKASIDE_WR_LCB_V(x) \
3981         ((x) << FW_CRYPTO_LOOKASIDE_WR_LCB_S)
3982 #define FW_CRYPTO_LOOKASIDE_WR_LCB_G(x) \
3983         (((x) >> FW_CRYPTO_LOOKASIDE_WR_LCB_S) & FW_CRYPTO_LOOKASIDE_WR_LCB_M)
3984
3985 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_S 25
3986 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_M 0x3
3987 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_V(x) \
3988         ((x) << FW_CRYPTO_LOOKASIDE_WR_PHASH_S)
3989 #define FW_CRYPTO_LOOKASIDE_WR_PHASH_G(x) \
3990         (((x) >> FW_CRYPTO_LOOKASIDE_WR_PHASH_S) & \
3991          FW_CRYPTO_LOOKASIDE_WR_PHASH_M)
3992
3993 #define FW_CRYPTO_LOOKASIDE_WR_IV_S   23
3994 #define FW_CRYPTO_LOOKASIDE_WR_IV_M   0x3
3995 #define FW_CRYPTO_LOOKASIDE_WR_IV_V(x) \
3996         ((x) << FW_CRYPTO_LOOKASIDE_WR_IV_S)
3997 #define FW_CRYPTO_LOOKASIDE_WR_IV_G(x) \
3998         (((x) >> FW_CRYPTO_LOOKASIDE_WR_IV_S) & FW_CRYPTO_LOOKASIDE_WR_IV_M)
3999
4000 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_S   15
4001 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_M   0xff
4002 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_V(x) \
4003         ((x) << FW_CRYPTO_LOOKASIDE_WR_FQIDX_S)
4004 #define FW_CRYPTO_LOOKASIDE_WR_FQIDX_G(x) \
4005         (((x) >> FW_CRYPTO_LOOKASIDE_WR_FQIDX_S) & \
4006          FW_CRYPTO_LOOKASIDE_WR_FQIDX_M)
4007
4008 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_S 10
4009 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_M 0x3
4010 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_V(x) \
4011         ((x) << FW_CRYPTO_LOOKASIDE_WR_TX_CH_S)
4012 #define FW_CRYPTO_LOOKASIDE_WR_TX_CH_G(x) \
4013         (((x) >> FW_CRYPTO_LOOKASIDE_WR_TX_CH_S) & \
4014          FW_CRYPTO_LOOKASIDE_WR_TX_CH_M)
4015
4016 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S 0
4017 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M 0x3ff
4018 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_V(x) \
4019         ((x) << FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S)
4020 #define FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_G(x) \
4021         (((x) >> FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_S) & \
4022          FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID_M)
4023
4024 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S 24
4025 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M 0xff
4026 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_V(x) \
4027         ((x) << FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S)
4028 #define FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_G(x) \
4029         (((x) >> FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_S) & \
4030          FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE_M)
4031
4032 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S 17
4033 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M 0x7f
4034 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_V(x) \
4035         ((x) << FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S)
4036 #define FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_G(x) \
4037         (((x) >> FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_S) & \
4038          FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE_M)
4039
4040 struct fw_tlstx_data_wr {
4041         __be32 op_to_immdlen;
4042         __be32 flowid_len16;
4043         __be32 plen;
4044         __be32 lsodisable_to_flags;
4045         __be32 r5;
4046         __be32 ctxloc_to_exp;
4047         __be16 mfs;
4048         __be16 adjustedplen_pkd;
4049         __be16 expinplenmax_pkd;
4050         u8   pdusinplenmax_pkd;
4051         u8   r10;
4052 };
4053
4054 #define FW_TLSTX_DATA_WR_OPCODE_S       24
4055 #define FW_TLSTX_DATA_WR_OPCODE_M       0xff
4056 #define FW_TLSTX_DATA_WR_OPCODE_V(x)    ((x) << FW_TLSTX_DATA_WR_OPCODE_S)
4057 #define FW_TLSTX_DATA_WR_OPCODE_G(x)    \
4058         (((x) >> FW_TLSTX_DATA_WR_OPCODE_S) & FW_TLSTX_DATA_WR_OPCODE_M)
4059
4060 #define FW_TLSTX_DATA_WR_COMPL_S        21
4061 #define FW_TLSTX_DATA_WR_COMPL_M        0x1
4062 #define FW_TLSTX_DATA_WR_COMPL_V(x)     ((x) << FW_TLSTX_DATA_WR_COMPL_S)
4063 #define FW_TLSTX_DATA_WR_COMPL_G(x)     \
4064         (((x) >> FW_TLSTX_DATA_WR_COMPL_S) & FW_TLSTX_DATA_WR_COMPL_M)
4065 #define FW_TLSTX_DATA_WR_COMPL_F        FW_TLSTX_DATA_WR_COMPL_V(1U)
4066
4067 #define FW_TLSTX_DATA_WR_IMMDLEN_S      0
4068 #define FW_TLSTX_DATA_WR_IMMDLEN_M      0xff
4069 #define FW_TLSTX_DATA_WR_IMMDLEN_V(x)   ((x) << FW_TLSTX_DATA_WR_IMMDLEN_S)
4070 #define FW_TLSTX_DATA_WR_IMMDLEN_G(x)   \
4071         (((x) >> FW_TLSTX_DATA_WR_IMMDLEN_S) & FW_TLSTX_DATA_WR_IMMDLEN_M)
4072
4073 #define FW_TLSTX_DATA_WR_FLOWID_S       8
4074 #define FW_TLSTX_DATA_WR_FLOWID_M       0xfffff
4075 #define FW_TLSTX_DATA_WR_FLOWID_V(x)    ((x) << FW_TLSTX_DATA_WR_FLOWID_S)
4076 #define FW_TLSTX_DATA_WR_FLOWID_G(x)    \
4077         (((x) >> FW_TLSTX_DATA_WR_FLOWID_S) & FW_TLSTX_DATA_WR_FLOWID_M)
4078
4079 #define FW_TLSTX_DATA_WR_LEN16_S        0
4080 #define FW_TLSTX_DATA_WR_LEN16_M        0xff
4081 #define FW_TLSTX_DATA_WR_LEN16_V(x)     ((x) << FW_TLSTX_DATA_WR_LEN16_S)
4082 #define FW_TLSTX_DATA_WR_LEN16_G(x)     \
4083         (((x) >> FW_TLSTX_DATA_WR_LEN16_S) & FW_TLSTX_DATA_WR_LEN16_M)
4084
4085 #define FW_TLSTX_DATA_WR_LSODISABLE_S   31
4086 #define FW_TLSTX_DATA_WR_LSODISABLE_M   0x1
4087 #define FW_TLSTX_DATA_WR_LSODISABLE_V(x) \
4088         ((x) << FW_TLSTX_DATA_WR_LSODISABLE_S)
4089 #define FW_TLSTX_DATA_WR_LSODISABLE_G(x) \
4090         (((x) >> FW_TLSTX_DATA_WR_LSODISABLE_S) & FW_TLSTX_DATA_WR_LSODISABLE_M)
4091 #define FW_TLSTX_DATA_WR_LSODISABLE_F   FW_TLSTX_DATA_WR_LSODISABLE_V(1U)
4092
4093 #define FW_TLSTX_DATA_WR_ALIGNPLD_S     30
4094 #define FW_TLSTX_DATA_WR_ALIGNPLD_M     0x1
4095 #define FW_TLSTX_DATA_WR_ALIGNPLD_V(x)  ((x) << FW_TLSTX_DATA_WR_ALIGNPLD_S)
4096 #define FW_TLSTX_DATA_WR_ALIGNPLD_G(x)  \
4097         (((x) >> FW_TLSTX_DATA_WR_ALIGNPLD_S) & FW_TLSTX_DATA_WR_ALIGNPLD_M)
4098 #define FW_TLSTX_DATA_WR_ALIGNPLD_F     FW_TLSTX_DATA_WR_ALIGNPLD_V(1U)
4099
4100 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S 29
4101 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M 0x1
4102 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(x) \
4103         ((x) << FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S)
4104 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_G(x) \
4105         (((x) >> FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_S) & \
4106         FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_M)
4107 #define FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_F FW_TLSTX_DATA_WR_ALIGNPLDSHOVE_V(1U)
4108
4109 #define FW_TLSTX_DATA_WR_FLAGS_S        0
4110 #define FW_TLSTX_DATA_WR_FLAGS_M        0xfffffff
4111 #define FW_TLSTX_DATA_WR_FLAGS_V(x)     ((x) << FW_TLSTX_DATA_WR_FLAGS_S)
4112 #define FW_TLSTX_DATA_WR_FLAGS_G(x)     \
4113         (((x) >> FW_TLSTX_DATA_WR_FLAGS_S) & FW_TLSTX_DATA_WR_FLAGS_M)
4114
4115 #define FW_TLSTX_DATA_WR_CTXLOC_S       30
4116 #define FW_TLSTX_DATA_WR_CTXLOC_M       0x3
4117 #define FW_TLSTX_DATA_WR_CTXLOC_V(x)    ((x) << FW_TLSTX_DATA_WR_CTXLOC_S)
4118 #define FW_TLSTX_DATA_WR_CTXLOC_G(x)    \
4119         (((x) >> FW_TLSTX_DATA_WR_CTXLOC_S) & FW_TLSTX_DATA_WR_CTXLOC_M)
4120
4121 #define FW_TLSTX_DATA_WR_IVDSGL_S       29
4122 #define FW_TLSTX_DATA_WR_IVDSGL_M       0x1
4123 #define FW_TLSTX_DATA_WR_IVDSGL_V(x)    ((x) << FW_TLSTX_DATA_WR_IVDSGL_S)
4124 #define FW_TLSTX_DATA_WR_IVDSGL_G(x)    \
4125         (((x) >> FW_TLSTX_DATA_WR_IVDSGL_S) & FW_TLSTX_DATA_WR_IVDSGL_M)
4126 #define FW_TLSTX_DATA_WR_IVDSGL_F       FW_TLSTX_DATA_WR_IVDSGL_V(1U)
4127
4128 #define FW_TLSTX_DATA_WR_KEYSIZE_S      24
4129 #define FW_TLSTX_DATA_WR_KEYSIZE_M      0x1f
4130 #define FW_TLSTX_DATA_WR_KEYSIZE_V(x)   ((x) << FW_TLSTX_DATA_WR_KEYSIZE_S)
4131 #define FW_TLSTX_DATA_WR_KEYSIZE_G(x)   \
4132         (((x) >> FW_TLSTX_DATA_WR_KEYSIZE_S) & FW_TLSTX_DATA_WR_KEYSIZE_M)
4133
4134 #define FW_TLSTX_DATA_WR_NUMIVS_S       14
4135 #define FW_TLSTX_DATA_WR_NUMIVS_M       0xff
4136 #define FW_TLSTX_DATA_WR_NUMIVS_V(x)    ((x) << FW_TLSTX_DATA_WR_NUMIVS_S)
4137 #define FW_TLSTX_DATA_WR_NUMIVS_G(x)    \
4138         (((x) >> FW_TLSTX_DATA_WR_NUMIVS_S) & FW_TLSTX_DATA_WR_NUMIVS_M)
4139
4140 #define FW_TLSTX_DATA_WR_EXP_S          0
4141 #define FW_TLSTX_DATA_WR_EXP_M          0x3fff
4142 #define FW_TLSTX_DATA_WR_EXP_V(x)       ((x) << FW_TLSTX_DATA_WR_EXP_S)
4143 #define FW_TLSTX_DATA_WR_EXP_G(x)       \
4144         (((x) >> FW_TLSTX_DATA_WR_EXP_S) & FW_TLSTX_DATA_WR_EXP_M)
4145
4146 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S 1
4147 #define FW_TLSTX_DATA_WR_ADJUSTEDPLEN_V(x) \
4148         ((x) << FW_TLSTX_DATA_WR_ADJUSTEDPLEN_S)
4149
4150 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_S 4
4151 #define FW_TLSTX_DATA_WR_EXPINPLENMAX_V(x) \
4152         ((x) << FW_TLSTX_DATA_WR_EXPINPLENMAX_S)
4153
4154 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_S 2
4155 #define FW_TLSTX_DATA_WR_PDUSINPLENMAX_V(x) \
4156         ((x) << FW_TLSTX_DATA_WR_PDUSINPLENMAX_S)
4157
4158 #endif /* _T4FW_INTERFACE_H_ */