1 /* Copyright 2008 - 2016 Freescale Semiconductor Inc.
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are met:
5 * * Redistributions of source code must retain the above copyright
6 * notice, this list of conditions and the following disclaimer.
7 * * Redistributions in binary form must reproduce the above copyright
8 * notice, this list of conditions and the following disclaimer in the
9 * documentation and/or other materials provided with the distribution.
10 * * Neither the name of Freescale Semiconductor nor the
11 * names of its contributors may be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * ALTERNATIVELY, this software may be distributed under the terms of the
15 * GNU General Public License ("GPL") as published by the Free Software
16 * Foundation, either version 2 of that License or (at your option) any
19 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33 #include <linux/init.h>
34 #include <linux/module.h>
35 #include <linux/of_platform.h>
36 #include <linux/of_mdio.h>
37 #include <linux/of_net.h>
39 #include <linux/if_arp.h>
40 #include <linux/if_vlan.h>
41 #include <linux/icmp.h>
43 #include <linux/ipv6.h>
44 #include <linux/udp.h>
45 #include <linux/tcp.h>
46 #include <linux/net.h>
47 #include <linux/skbuff.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/highmem.h>
51 #include <linux/percpu.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/sort.h>
54 #include <soc/fsl/bman.h>
55 #include <soc/fsl/qman.h>
58 #include "fman_port.h"
62 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpaa files
63 * using trace events only need to #include <trace/events/sched.h>
65 #define CREATE_TRACE_POINTS
66 #include "dpaa_eth_trace.h"
68 static int debug = -1;
69 module_param(debug, int, 0444);
70 MODULE_PARM_DESC(debug, "Module/Driver verbosity level (0=none,...,16=all)");
72 static u16 tx_timeout = 1000;
73 module_param(tx_timeout, ushort, 0444);
74 MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms");
76 #define FM_FD_STAT_RX_ERRORS \
77 (FM_FD_ERR_DMA | FM_FD_ERR_PHYSICAL | \
78 FM_FD_ERR_SIZE | FM_FD_ERR_CLS_DISCARD | \
79 FM_FD_ERR_EXTRACTION | FM_FD_ERR_NO_SCHEME | \
80 FM_FD_ERR_PRS_TIMEOUT | FM_FD_ERR_PRS_ILL_INSTRUCT | \
81 FM_FD_ERR_PRS_HDR_ERR)
83 #define FM_FD_STAT_TX_ERRORS \
84 (FM_FD_ERR_UNSUPPORTED_FORMAT | \
85 FM_FD_ERR_LENGTH | FM_FD_ERR_DMA)
87 #define DPAA_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
88 NETIF_MSG_LINK | NETIF_MSG_IFUP | \
91 #define DPAA_INGRESS_CS_THRESHOLD 0x10000000
92 /* Ingress congestion threshold on FMan ports
93 * The size in bytes of the ingress tail-drop threshold on FMan ports.
94 * Traffic piling up above this value will be rejected by QMan and discarded
98 /* Size in bytes of the FQ taildrop threshold */
99 #define DPAA_FQ_TD 0x200000
101 #define DPAA_CS_THRESHOLD_1G 0x06000000
102 /* Egress congestion threshold on 1G ports, range 0x1000 .. 0x10000000
103 * The size in bytes of the egress Congestion State notification threshold on
104 * 1G ports. The 1G dTSECs can quite easily be flooded by cores doing Tx in a
105 * tight loop (e.g. by sending UDP datagrams at "while(1) speed"),
106 * and the larger the frame size, the more acute the problem.
107 * So we have to find a balance between these factors:
108 * - avoiding the device staying congested for a prolonged time (risking
109 * the netdev watchdog to fire - see also the tx_timeout module param);
110 * - affecting performance of protocols such as TCP, which otherwise
111 * behave well under the congestion notification mechanism;
112 * - preventing the Tx cores from tightly-looping (as if the congestion
113 * threshold was too low to be effective);
114 * - running out of memory if the CS threshold is set too high.
117 #define DPAA_CS_THRESHOLD_10G 0x10000000
118 /* The size in bytes of the egress Congestion State notification threshold on
119 * 10G ports, range 0x1000 .. 0x10000000
122 /* Largest value that the FQD's OAL field can hold */
123 #define FSL_QMAN_MAX_OAL 127
125 /* Default alignment for start of data in an Rx FD */
126 #define DPAA_FD_DATA_ALIGNMENT 16
128 /* Values for the L3R field of the FM Parse Results
130 /* L3 Type field: First IP Present IPv4 */
131 #define FM_L3_PARSE_RESULT_IPV4 0x8000
132 /* L3 Type field: First IP Present IPv6 */
133 #define FM_L3_PARSE_RESULT_IPV6 0x4000
134 /* Values for the L4R field of the FM Parse Results */
135 /* L4 Type field: UDP */
136 #define FM_L4_PARSE_RESULT_UDP 0x40
137 /* L4 Type field: TCP */
138 #define FM_L4_PARSE_RESULT_TCP 0x20
140 /* FD status field indicating whether the FM Parser has attempted to validate
141 * the L4 csum of the frame.
142 * Note that having this bit set doesn't necessarily imply that the checksum
143 * is valid. One would have to check the parse results to find that out.
145 #define FM_FD_STAT_L4CV 0x00000004
147 #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */
148 #define DPAA_BUFF_RELEASE_MAX 8 /* maximum number of buffers released at once */
150 #define FSL_DPAA_BPID_INV 0xff
151 #define FSL_DPAA_ETH_MAX_BUF_COUNT 128
152 #define FSL_DPAA_ETH_REFILL_THRESHOLD 80
154 #define DPAA_TX_PRIV_DATA_SIZE 16
155 #define DPAA_PARSE_RESULTS_SIZE sizeof(struct fman_prs_result)
156 #define DPAA_TIME_STAMP_SIZE 8
157 #define DPAA_HASH_RESULTS_SIZE 8
158 #define DPAA_RX_PRIV_DATA_SIZE (u16)(DPAA_TX_PRIV_DATA_SIZE + \
159 dpaa_rx_extra_headroom)
161 #define DPAA_ETH_PCD_RXQ_NUM 128
163 #define DPAA_ENQUEUE_RETRIES 100000
165 enum port_type {RX, TX};
168 struct dpaa_fq *tx_defq;
169 struct dpaa_fq *tx_errq;
170 struct dpaa_fq *rx_defq;
171 struct dpaa_fq *rx_errq;
172 struct dpaa_fq *rx_pcdq;
175 /* All the dpa bps in use at any moment */
176 static struct dpaa_bp *dpaa_bp_array[BM_MAX_NUM_OF_POOLS];
178 /* The raw buffer size must be cacheline aligned */
179 #define DPAA_BP_RAW_SIZE 4096
180 /* When using more than one buffer pool, the raw sizes are as follows:
183 * 3 bp: 1KB, 2KB, 4KB
184 * 4 bp: 1KB, 2KB, 4KB, 8KB
186 static inline size_t bpool_buffer_raw_size(u8 index, u8 cnt)
188 size_t res = DPAA_BP_RAW_SIZE / 4;
191 for (i = (cnt < 3) ? cnt : 3; i < 3 + index; i++)
196 /* FMan-DMA requires 16-byte alignment for Rx buffers, but SKB_DATA_ALIGN is
197 * even stronger (SMP_CACHE_BYTES-aligned), so we just get away with that,
198 * via SKB_WITH_OVERHEAD(). We can't rely on netdev_alloc_frag() giving us
199 * half-page-aligned buffers, so we reserve some more space for start-of-buffer
202 #define dpaa_bp_size(raw_size) SKB_WITH_OVERHEAD((raw_size) - SMP_CACHE_BYTES)
204 static int dpaa_max_frm;
206 static int dpaa_rx_extra_headroom;
208 #define dpaa_get_max_mtu() \
209 (dpaa_max_frm - (VLAN_ETH_HLEN + ETH_FCS_LEN))
211 static int dpaa_netdev_init(struct net_device *net_dev,
212 const struct net_device_ops *dpaa_ops,
215 struct dpaa_priv *priv = netdev_priv(net_dev);
216 struct device *dev = net_dev->dev.parent;
217 struct dpaa_percpu_priv *percpu_priv;
221 /* Although we access another CPU's private data here
222 * we do it at initialization so it is safe
224 for_each_possible_cpu(i) {
225 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
226 percpu_priv->net_dev = net_dev;
229 net_dev->netdev_ops = dpaa_ops;
230 mac_addr = priv->mac_dev->addr;
232 net_dev->mem_start = priv->mac_dev->res->start;
233 net_dev->mem_end = priv->mac_dev->res->end;
235 net_dev->min_mtu = ETH_MIN_MTU;
236 net_dev->max_mtu = dpaa_get_max_mtu();
238 net_dev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
239 NETIF_F_LLTX | NETIF_F_RXHASH);
241 net_dev->hw_features |= NETIF_F_SG | NETIF_F_HIGHDMA;
242 /* The kernels enables GSO automatically, if we declare NETIF_F_SG.
243 * For conformity, we'll still declare GSO explicitly.
245 net_dev->features |= NETIF_F_GSO;
246 net_dev->features |= NETIF_F_RXCSUM;
248 net_dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
249 /* we do not want shared skbs on TX */
250 net_dev->priv_flags &= ~IFF_TX_SKB_SHARING;
252 net_dev->features |= net_dev->hw_features;
253 net_dev->vlan_features = net_dev->features;
255 memcpy(net_dev->perm_addr, mac_addr, net_dev->addr_len);
256 memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len);
258 net_dev->ethtool_ops = &dpaa_ethtool_ops;
260 net_dev->needed_headroom = priv->tx_headroom;
261 net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout);
263 /* start without the RUNNING flag, phylib controls it later */
264 netif_carrier_off(net_dev);
266 err = register_netdev(net_dev);
268 dev_err(dev, "register_netdev() = %d\n", err);
275 static int dpaa_stop(struct net_device *net_dev)
277 struct mac_device *mac_dev;
278 struct dpaa_priv *priv;
281 priv = netdev_priv(net_dev);
282 mac_dev = priv->mac_dev;
284 netif_tx_stop_all_queues(net_dev);
285 /* Allow the Fman (Tx) port to process in-flight frames before we
286 * try switching it off.
288 usleep_range(5000, 10000);
290 err = mac_dev->stop(mac_dev);
292 netif_err(priv, ifdown, net_dev, "mac_dev->stop() = %d\n",
295 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
296 error = fman_port_disable(mac_dev->port[i]);
302 phy_disconnect(net_dev->phydev);
303 net_dev->phydev = NULL;
308 static void dpaa_tx_timeout(struct net_device *net_dev)
310 struct dpaa_percpu_priv *percpu_priv;
311 const struct dpaa_priv *priv;
313 priv = netdev_priv(net_dev);
314 percpu_priv = this_cpu_ptr(priv->percpu_priv);
316 netif_crit(priv, timer, net_dev, "Transmit timeout latency: %u ms\n",
317 jiffies_to_msecs(jiffies - dev_trans_start(net_dev)));
319 percpu_priv->stats.tx_errors++;
322 /* Calculates the statistics for the given device by adding the statistics
323 * collected by each CPU.
325 static void dpaa_get_stats64(struct net_device *net_dev,
326 struct rtnl_link_stats64 *s)
328 int numstats = sizeof(struct rtnl_link_stats64) / sizeof(u64);
329 struct dpaa_priv *priv = netdev_priv(net_dev);
330 struct dpaa_percpu_priv *percpu_priv;
331 u64 *netstats = (u64 *)s;
335 for_each_possible_cpu(i) {
336 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
338 cpustats = (u64 *)&percpu_priv->stats;
340 /* add stats from all CPUs */
341 for (j = 0; j < numstats; j++)
342 netstats[j] += cpustats[j];
346 static int dpaa_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
349 struct dpaa_priv *priv = netdev_priv(net_dev);
350 struct tc_mqprio_qopt *mqprio = type_data;
354 if (type != TC_SETUP_QDISC_MQPRIO)
357 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
358 num_tc = mqprio->num_tc;
360 if (num_tc == priv->num_tc)
364 netdev_reset_tc(net_dev);
368 if (num_tc > DPAA_TC_NUM) {
369 netdev_err(net_dev, "Too many traffic classes: max %d supported.\n",
374 netdev_set_num_tc(net_dev, num_tc);
376 for (i = 0; i < num_tc; i++)
377 netdev_set_tc_queue(net_dev, i, DPAA_TC_TXQ_NUM,
378 i * DPAA_TC_TXQ_NUM);
381 priv->num_tc = num_tc ? : 1;
382 netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM);
386 static struct mac_device *dpaa_mac_dev_get(struct platform_device *pdev)
388 struct dpaa_eth_data *eth_data;
389 struct device *dpaa_dev;
390 struct mac_device *mac_dev;
392 dpaa_dev = &pdev->dev;
393 eth_data = dpaa_dev->platform_data;
395 dev_err(dpaa_dev, "eth_data missing\n");
396 return ERR_PTR(-ENODEV);
398 mac_dev = eth_data->mac_dev;
400 dev_err(dpaa_dev, "mac_dev missing\n");
401 return ERR_PTR(-EINVAL);
407 static int dpaa_set_mac_address(struct net_device *net_dev, void *addr)
409 const struct dpaa_priv *priv;
410 struct mac_device *mac_dev;
411 struct sockaddr old_addr;
414 priv = netdev_priv(net_dev);
416 memcpy(old_addr.sa_data, net_dev->dev_addr, ETH_ALEN);
418 err = eth_mac_addr(net_dev, addr);
420 netif_err(priv, drv, net_dev, "eth_mac_addr() = %d\n", err);
424 mac_dev = priv->mac_dev;
426 err = mac_dev->change_addr(mac_dev->fman_mac,
427 (enet_addr_t *)net_dev->dev_addr);
429 netif_err(priv, drv, net_dev, "mac_dev->change_addr() = %d\n",
431 /* reverting to previous address */
432 eth_mac_addr(net_dev, &old_addr);
440 static void dpaa_set_rx_mode(struct net_device *net_dev)
442 const struct dpaa_priv *priv;
445 priv = netdev_priv(net_dev);
447 if (!!(net_dev->flags & IFF_PROMISC) != priv->mac_dev->promisc) {
448 priv->mac_dev->promisc = !priv->mac_dev->promisc;
449 err = priv->mac_dev->set_promisc(priv->mac_dev->fman_mac,
450 priv->mac_dev->promisc);
452 netif_err(priv, drv, net_dev,
453 "mac_dev->set_promisc() = %d\n",
457 if (!!(net_dev->flags & IFF_ALLMULTI) != priv->mac_dev->allmulti) {
458 priv->mac_dev->allmulti = !priv->mac_dev->allmulti;
459 err = priv->mac_dev->set_allmulti(priv->mac_dev->fman_mac,
460 priv->mac_dev->allmulti);
462 netif_err(priv, drv, net_dev,
463 "mac_dev->set_allmulti() = %d\n",
467 err = priv->mac_dev->set_multi(net_dev, priv->mac_dev);
469 netif_err(priv, drv, net_dev, "mac_dev->set_multi() = %d\n",
473 static struct dpaa_bp *dpaa_bpid2pool(int bpid)
475 if (WARN_ON(bpid < 0 || bpid >= BM_MAX_NUM_OF_POOLS))
478 return dpaa_bp_array[bpid];
481 /* checks if this bpool is already allocated */
482 static bool dpaa_bpid2pool_use(int bpid)
484 if (dpaa_bpid2pool(bpid)) {
485 atomic_inc(&dpaa_bp_array[bpid]->refs);
492 /* called only once per bpid by dpaa_bp_alloc_pool() */
493 static void dpaa_bpid2pool_map(int bpid, struct dpaa_bp *dpaa_bp)
495 dpaa_bp_array[bpid] = dpaa_bp;
496 atomic_set(&dpaa_bp->refs, 1);
499 static int dpaa_bp_alloc_pool(struct dpaa_bp *dpaa_bp)
503 if (dpaa_bp->size == 0 || dpaa_bp->config_count == 0) {
504 pr_err("%s: Buffer pool is not properly initialized! Missing size or initial number of buffers\n",
509 /* If the pool is already specified, we only create one per bpid */
510 if (dpaa_bp->bpid != FSL_DPAA_BPID_INV &&
511 dpaa_bpid2pool_use(dpaa_bp->bpid))
514 if (dpaa_bp->bpid == FSL_DPAA_BPID_INV) {
515 dpaa_bp->pool = bman_new_pool();
516 if (!dpaa_bp->pool) {
517 pr_err("%s: bman_new_pool() failed\n",
522 dpaa_bp->bpid = (u8)bman_get_bpid(dpaa_bp->pool);
525 if (dpaa_bp->seed_cb) {
526 err = dpaa_bp->seed_cb(dpaa_bp);
528 goto pool_seed_failed;
531 dpaa_bpid2pool_map(dpaa_bp->bpid, dpaa_bp);
536 pr_err("%s: pool seeding failed\n", __func__);
537 bman_free_pool(dpaa_bp->pool);
542 /* remove and free all the buffers from the given buffer pool */
543 static void dpaa_bp_drain(struct dpaa_bp *bp)
549 struct bm_buffer bmb[8];
552 ret = bman_acquire(bp->pool, bmb, num);
555 /* we have less than 8 buffers left;
556 * drain them one by one
562 /* Pool is fully drained */
568 for (i = 0; i < num; i++)
569 bp->free_buf_cb(bp, &bmb[i]);
573 static void dpaa_bp_free(struct dpaa_bp *dpaa_bp)
575 struct dpaa_bp *bp = dpaa_bpid2pool(dpaa_bp->bpid);
577 /* the mapping between bpid and dpaa_bp is done very late in the
578 * allocation procedure; if something failed before the mapping, the bp
579 * was not configured, therefore we don't need the below instructions
584 if (!atomic_dec_and_test(&bp->refs))
590 dpaa_bp_array[bp->bpid] = NULL;
591 bman_free_pool(bp->pool);
594 static void dpaa_bps_free(struct dpaa_priv *priv)
598 for (i = 0; i < DPAA_BPS_NUM; i++)
599 dpaa_bp_free(priv->dpaa_bps[i]);
602 /* Use multiple WQs for FQ assignment:
603 * - Tx Confirmation queues go to WQ1.
604 * - Rx Error and Tx Error queues go to WQ5 (giving them a better chance
605 * to be scheduled, in case there are many more FQs in WQ6).
606 * - Rx Default goes to WQ6.
607 * - Tx queues go to different WQs depending on their priority. Equal
608 * chunks of NR_CPUS queues go to WQ6 (lowest priority), WQ2, WQ1 and
609 * WQ0 (highest priority).
610 * This ensures that Tx-confirmed buffers are timely released. In particular,
611 * it avoids congestion on the Tx Confirm FQs, which can pile up PFDRs if they
612 * are greatly outnumbered by other FQs in the system, while
613 * dequeue scheduling is round-robin.
615 static inline void dpaa_assign_wq(struct dpaa_fq *fq, int idx)
617 switch (fq->fq_type) {
618 case FQ_TYPE_TX_CONFIRM:
619 case FQ_TYPE_TX_CONF_MQ:
622 case FQ_TYPE_RX_ERROR:
623 case FQ_TYPE_TX_ERROR:
626 case FQ_TYPE_RX_DEFAULT:
631 switch (idx / DPAA_TC_TXQ_NUM) {
633 /* Low priority (best effort) */
637 /* Medium priority */
645 /* Very high priority */
649 WARN(1, "Too many TX FQs: more than %d!\n",
654 WARN(1, "Invalid FQ type %d for FQID %d!\n",
655 fq->fq_type, fq->fqid);
659 static struct dpaa_fq *dpaa_fq_alloc(struct device *dev,
660 u32 start, u32 count,
661 struct list_head *list,
662 enum dpaa_fq_type fq_type)
664 struct dpaa_fq *dpaa_fq;
667 dpaa_fq = devm_kcalloc(dev, count, sizeof(*dpaa_fq),
672 for (i = 0; i < count; i++) {
673 dpaa_fq[i].fq_type = fq_type;
674 dpaa_fq[i].fqid = start ? start + i : 0;
675 list_add_tail(&dpaa_fq[i].list, list);
678 for (i = 0; i < count; i++)
679 dpaa_assign_wq(dpaa_fq + i, i);
684 static int dpaa_alloc_all_fqs(struct device *dev, struct list_head *list,
685 struct fm_port_fqs *port_fqs)
687 struct dpaa_fq *dpaa_fq;
688 u32 fq_base, fq_base_aligned, i;
690 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_ERROR);
692 goto fq_alloc_failed;
694 port_fqs->rx_errq = &dpaa_fq[0];
696 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_DEFAULT);
698 goto fq_alloc_failed;
700 port_fqs->rx_defq = &dpaa_fq[0];
702 /* the PCD FQIDs range needs to be aligned for correct operation */
703 if (qman_alloc_fqid_range(&fq_base, 2 * DPAA_ETH_PCD_RXQ_NUM))
704 goto fq_alloc_failed;
706 fq_base_aligned = ALIGN(fq_base, DPAA_ETH_PCD_RXQ_NUM);
708 for (i = fq_base; i < fq_base_aligned; i++)
709 qman_release_fqid(i);
711 for (i = fq_base_aligned + DPAA_ETH_PCD_RXQ_NUM;
712 i < (fq_base + 2 * DPAA_ETH_PCD_RXQ_NUM); i++)
713 qman_release_fqid(i);
715 dpaa_fq = dpaa_fq_alloc(dev, fq_base_aligned, DPAA_ETH_PCD_RXQ_NUM,
716 list, FQ_TYPE_RX_PCD);
718 goto fq_alloc_failed;
720 port_fqs->rx_pcdq = &dpaa_fq[0];
722 if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX_CONF_MQ))
723 goto fq_alloc_failed;
725 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_ERROR);
727 goto fq_alloc_failed;
729 port_fqs->tx_errq = &dpaa_fq[0];
731 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_CONFIRM);
733 goto fq_alloc_failed;
735 port_fqs->tx_defq = &dpaa_fq[0];
737 if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX))
738 goto fq_alloc_failed;
743 dev_err(dev, "dpaa_fq_alloc() failed\n");
747 static u32 rx_pool_channel;
748 static DEFINE_SPINLOCK(rx_pool_channel_init);
750 static int dpaa_get_channel(void)
752 spin_lock(&rx_pool_channel_init);
753 if (!rx_pool_channel) {
757 ret = qman_alloc_pool(&pool);
760 rx_pool_channel = pool;
762 spin_unlock(&rx_pool_channel_init);
763 if (!rx_pool_channel)
765 return rx_pool_channel;
768 static void dpaa_release_channel(void)
770 qman_release_pool(rx_pool_channel);
773 static void dpaa_eth_add_channel(u16 channel)
775 u32 pool = QM_SDQCR_CHANNELS_POOL_CONV(channel);
776 const cpumask_t *cpus = qman_affine_cpus();
777 struct qman_portal *portal;
780 for_each_cpu(cpu, cpus) {
781 portal = qman_get_affine_portal(cpu);
782 qman_p_static_dequeue_add(portal, pool);
786 /* Congestion group state change notification callback.
787 * Stops the device's egress queues while they are congested and
788 * wakes them upon exiting congested state.
789 * Also updates some CGR-related stats.
791 static void dpaa_eth_cgscn(struct qman_portal *qm, struct qman_cgr *cgr,
794 struct dpaa_priv *priv = (struct dpaa_priv *)container_of(cgr,
795 struct dpaa_priv, cgr_data.cgr);
798 priv->cgr_data.congestion_start_jiffies = jiffies;
799 netif_tx_stop_all_queues(priv->net_dev);
800 priv->cgr_data.cgr_congested_count++;
802 priv->cgr_data.congested_jiffies +=
803 (jiffies - priv->cgr_data.congestion_start_jiffies);
804 netif_tx_wake_all_queues(priv->net_dev);
808 static int dpaa_eth_cgr_init(struct dpaa_priv *priv)
810 struct qm_mcc_initcgr initcgr;
814 err = qman_alloc_cgrid(&priv->cgr_data.cgr.cgrid);
816 if (netif_msg_drv(priv))
817 pr_err("%s: Error %d allocating CGR ID\n",
821 priv->cgr_data.cgr.cb = dpaa_eth_cgscn;
823 /* Enable Congestion State Change Notifications and CS taildrop */
824 memset(&initcgr, 0, sizeof(initcgr));
825 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES);
826 initcgr.cgr.cscn_en = QM_CGR_EN;
828 /* Set different thresholds based on the MAC speed.
829 * This may turn suboptimal if the MAC is reconfigured at a speed
830 * lower than its max, e.g. if a dTSEC later negotiates a 100Mbps link.
831 * In such cases, we ought to reconfigure the threshold, too.
833 if (priv->mac_dev->if_support & SUPPORTED_10000baseT_Full)
834 cs_th = DPAA_CS_THRESHOLD_10G;
836 cs_th = DPAA_CS_THRESHOLD_1G;
837 qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
839 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN);
840 initcgr.cgr.cstd_en = QM_CGR_EN;
842 err = qman_create_cgr(&priv->cgr_data.cgr, QMAN_CGR_FLAG_USE_INIT,
845 if (netif_msg_drv(priv))
846 pr_err("%s: Error %d creating CGR with ID %d\n",
847 __func__, err, priv->cgr_data.cgr.cgrid);
848 qman_release_cgrid(priv->cgr_data.cgr.cgrid);
851 if (netif_msg_drv(priv))
852 pr_debug("Created CGR %d for netdev with hwaddr %pM on QMan channel %d\n",
853 priv->cgr_data.cgr.cgrid, priv->mac_dev->addr,
854 priv->cgr_data.cgr.chan);
860 static inline void dpaa_setup_ingress(const struct dpaa_priv *priv,
862 const struct qman_fq *template)
864 fq->fq_base = *template;
865 fq->net_dev = priv->net_dev;
867 fq->flags = QMAN_FQ_FLAG_NO_ENQUEUE;
868 fq->channel = priv->channel;
871 static inline void dpaa_setup_egress(const struct dpaa_priv *priv,
873 struct fman_port *port,
874 const struct qman_fq *template)
876 fq->fq_base = *template;
877 fq->net_dev = priv->net_dev;
880 fq->flags = QMAN_FQ_FLAG_TO_DCPORTAL;
881 fq->channel = (u16)fman_port_get_qman_channel_id(port);
883 fq->flags = QMAN_FQ_FLAG_NO_MODIFY;
887 static void dpaa_fq_setup(struct dpaa_priv *priv,
888 const struct dpaa_fq_cbs *fq_cbs,
889 struct fman_port *tx_port)
891 int egress_cnt = 0, conf_cnt = 0, num_portals = 0, portal_cnt = 0, cpu;
892 const cpumask_t *affine_cpus = qman_affine_cpus();
893 u16 channels[NR_CPUS];
896 for_each_cpu(cpu, affine_cpus)
897 channels[num_portals++] = qman_affine_channel(cpu);
899 if (num_portals == 0)
900 dev_err(priv->net_dev->dev.parent,
901 "No Qman software (affine) channels found");
903 /* Initialize each FQ in the list */
904 list_for_each_entry(fq, &priv->dpaa_fq_list, list) {
905 switch (fq->fq_type) {
906 case FQ_TYPE_RX_DEFAULT:
907 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
909 case FQ_TYPE_RX_ERROR:
910 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_errq);
915 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
916 fq->channel = channels[portal_cnt++ % num_portals];
919 dpaa_setup_egress(priv, fq, tx_port,
920 &fq_cbs->egress_ern);
921 /* If we have more Tx queues than the number of cores,
922 * just ignore the extra ones.
924 if (egress_cnt < DPAA_ETH_TXQ_NUM)
925 priv->egress_fqs[egress_cnt++] = &fq->fq_base;
927 case FQ_TYPE_TX_CONF_MQ:
928 priv->conf_fqs[conf_cnt++] = &fq->fq_base;
930 case FQ_TYPE_TX_CONFIRM:
931 dpaa_setup_ingress(priv, fq, &fq_cbs->tx_defq);
933 case FQ_TYPE_TX_ERROR:
934 dpaa_setup_ingress(priv, fq, &fq_cbs->tx_errq);
937 dev_warn(priv->net_dev->dev.parent,
938 "Unknown FQ type detected!\n");
943 /* Make sure all CPUs receive a corresponding Tx queue. */
944 while (egress_cnt < DPAA_ETH_TXQ_NUM) {
945 list_for_each_entry(fq, &priv->dpaa_fq_list, list) {
946 if (fq->fq_type != FQ_TYPE_TX)
948 priv->egress_fqs[egress_cnt++] = &fq->fq_base;
949 if (egress_cnt == DPAA_ETH_TXQ_NUM)
955 static inline int dpaa_tx_fq_to_id(const struct dpaa_priv *priv,
956 struct qman_fq *tx_fq)
960 for (i = 0; i < DPAA_ETH_TXQ_NUM; i++)
961 if (priv->egress_fqs[i] == tx_fq)
967 static int dpaa_fq_init(struct dpaa_fq *dpaa_fq, bool td_enable)
969 const struct dpaa_priv *priv;
970 struct qman_fq *confq = NULL;
971 struct qm_mcc_initfq initfq;
977 priv = netdev_priv(dpaa_fq->net_dev);
978 dev = dpaa_fq->net_dev->dev.parent;
980 if (dpaa_fq->fqid == 0)
981 dpaa_fq->flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
983 dpaa_fq->init = !(dpaa_fq->flags & QMAN_FQ_FLAG_NO_MODIFY);
985 err = qman_create_fq(dpaa_fq->fqid, dpaa_fq->flags, &dpaa_fq->fq_base);
987 dev_err(dev, "qman_create_fq() failed\n");
990 fq = &dpaa_fq->fq_base;
993 memset(&initfq, 0, sizeof(initfq));
995 initfq.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL);
996 /* Note: we may get to keep an empty FQ in cache */
997 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_PREFERINCACHE);
999 /* Try to reduce the number of portal interrupts for
1000 * Tx Confirmation FQs.
1002 if (dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM)
1003 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_AVOIDBLOCK);
1006 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_DESTWQ);
1008 qm_fqd_set_destwq(&initfq.fqd, dpaa_fq->channel, dpaa_fq->wq);
1010 /* Put all egress queues in a congestion group of their own.
1011 * Sensu stricto, the Tx confirmation queues are Rx FQs,
1012 * rather than Tx - but they nonetheless account for the
1013 * memory footprint on behalf of egress traffic. We therefore
1014 * place them in the netdev's CGR, along with the Tx FQs.
1016 if (dpaa_fq->fq_type == FQ_TYPE_TX ||
1017 dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM ||
1018 dpaa_fq->fq_type == FQ_TYPE_TX_CONF_MQ) {
1019 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID);
1020 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE);
1021 initfq.fqd.cgid = (u8)priv->cgr_data.cgr.cgrid;
1022 /* Set a fixed overhead accounting, in an attempt to
1023 * reduce the impact of fixed-size skb shells and the
1024 * driver's needed headroom on system memory. This is
1025 * especially the case when the egress traffic is
1026 * composed of small datagrams.
1027 * Unfortunately, QMan's OAL value is capped to an
1028 * insufficient value, but even that is better than
1029 * no overhead accounting at all.
1031 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC);
1032 qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
1033 qm_fqd_set_oal(&initfq.fqd,
1034 min(sizeof(struct sk_buff) +
1036 (size_t)FSL_QMAN_MAX_OAL));
1040 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_TDTHRESH);
1041 qm_fqd_set_taildrop(&initfq.fqd, DPAA_FQ_TD, 1);
1042 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_TDE);
1045 if (dpaa_fq->fq_type == FQ_TYPE_TX) {
1046 queue_id = dpaa_tx_fq_to_id(priv, &dpaa_fq->fq_base);
1048 confq = priv->conf_fqs[queue_id];
1051 cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1052 /* ContextA: OVOM=1(use contextA2 bits instead of ICAD)
1053 * A2V=1 (contextA A2 field is valid)
1054 * A0V=1 (contextA A0 field is valid)
1055 * B0V=1 (contextB field is valid)
1056 * ContextA A2: EBD=1 (deallocate buffers inside FMan)
1057 * ContextB B0(ASPID): 0 (absolute Virtual Storage ID)
1059 qm_fqd_context_a_set64(&initfq.fqd,
1060 0x1e00000080000000ULL);
1064 /* Put all the ingress queues in our "ingress CGR". */
1065 if (priv->use_ingress_cgr &&
1066 (dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT ||
1067 dpaa_fq->fq_type == FQ_TYPE_RX_ERROR ||
1068 dpaa_fq->fq_type == FQ_TYPE_RX_PCD)) {
1069 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID);
1070 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE);
1071 initfq.fqd.cgid = (u8)priv->ingress_cgr.cgrid;
1072 /* Set a fixed overhead accounting, just like for the
1075 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC);
1076 qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
1077 qm_fqd_set_oal(&initfq.fqd,
1078 min(sizeof(struct sk_buff) +
1080 (size_t)FSL_QMAN_MAX_OAL));
1083 /* Initialization common to all ingress queues */
1084 if (dpaa_fq->flags & QMAN_FQ_FLAG_NO_ENQUEUE) {
1085 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1086 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_HOLDACTIVE |
1087 QM_FQCTRL_CTXASTASHING);
1088 initfq.fqd.context_a.stashing.exclusive =
1089 QM_STASHING_EXCL_DATA | QM_STASHING_EXCL_CTX |
1090 QM_STASHING_EXCL_ANNOTATION;
1091 qm_fqd_set_stashing(&initfq.fqd, 1, 2,
1092 DIV_ROUND_UP(sizeof(struct qman_fq),
1096 err = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq);
1098 dev_err(dev, "qman_init_fq(%u) = %d\n",
1099 qman_fq_fqid(fq), err);
1100 qman_destroy_fq(fq);
1105 dpaa_fq->fqid = qman_fq_fqid(fq);
1110 static int dpaa_fq_free_entry(struct device *dev, struct qman_fq *fq)
1112 const struct dpaa_priv *priv;
1113 struct dpaa_fq *dpaa_fq;
1118 dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
1119 priv = netdev_priv(dpaa_fq->net_dev);
1121 if (dpaa_fq->init) {
1122 err = qman_retire_fq(fq, NULL);
1123 if (err < 0 && netif_msg_drv(priv))
1124 dev_err(dev, "qman_retire_fq(%u) = %d\n",
1125 qman_fq_fqid(fq), err);
1127 error = qman_oos_fq(fq);
1128 if (error < 0 && netif_msg_drv(priv)) {
1129 dev_err(dev, "qman_oos_fq(%u) = %d\n",
1130 qman_fq_fqid(fq), error);
1136 qman_destroy_fq(fq);
1137 list_del(&dpaa_fq->list);
1142 static int dpaa_fq_free(struct device *dev, struct list_head *list)
1144 struct dpaa_fq *dpaa_fq, *tmp;
1148 list_for_each_entry_safe(dpaa_fq, tmp, list, list) {
1149 error = dpaa_fq_free_entry(dev, (struct qman_fq *)dpaa_fq);
1150 if (error < 0 && err >= 0)
1157 static int dpaa_eth_init_tx_port(struct fman_port *port, struct dpaa_fq *errq,
1158 struct dpaa_fq *defq,
1159 struct dpaa_buffer_layout *buf_layout)
1161 struct fman_buffer_prefix_content buf_prefix_content;
1162 struct fman_port_params params;
1165 memset(¶ms, 0, sizeof(params));
1166 memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
1168 buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
1169 buf_prefix_content.pass_prs_result = true;
1170 buf_prefix_content.pass_hash_result = true;
1171 buf_prefix_content.pass_time_stamp = false;
1172 buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT;
1174 params.specific_params.non_rx_params.err_fqid = errq->fqid;
1175 params.specific_params.non_rx_params.dflt_fqid = defq->fqid;
1177 err = fman_port_config(port, ¶ms);
1179 pr_err("%s: fman_port_config failed\n", __func__);
1183 err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
1185 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
1190 err = fman_port_init(port);
1192 pr_err("%s: fm_port_init failed\n", __func__);
1197 static int dpaa_eth_init_rx_port(struct fman_port *port, struct dpaa_bp **bps,
1198 size_t count, struct dpaa_fq *errq,
1199 struct dpaa_fq *defq, struct dpaa_fq *pcdq,
1200 struct dpaa_buffer_layout *buf_layout)
1202 struct fman_buffer_prefix_content buf_prefix_content;
1203 struct fman_port_rx_params *rx_p;
1204 struct fman_port_params params;
1207 memset(¶ms, 0, sizeof(params));
1208 memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
1210 buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
1211 buf_prefix_content.pass_prs_result = true;
1212 buf_prefix_content.pass_hash_result = true;
1213 buf_prefix_content.pass_time_stamp = false;
1214 buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT;
1216 rx_p = ¶ms.specific_params.rx_params;
1217 rx_p->err_fqid = errq->fqid;
1218 rx_p->dflt_fqid = defq->fqid;
1220 rx_p->pcd_base_fqid = pcdq->fqid;
1221 rx_p->pcd_fqs_count = DPAA_ETH_PCD_RXQ_NUM;
1224 count = min(ARRAY_SIZE(rx_p->ext_buf_pools.ext_buf_pool), count);
1225 rx_p->ext_buf_pools.num_of_pools_used = (u8)count;
1226 for (i = 0; i < count; i++) {
1227 rx_p->ext_buf_pools.ext_buf_pool[i].id = bps[i]->bpid;
1228 rx_p->ext_buf_pools.ext_buf_pool[i].size = (u16)bps[i]->size;
1231 err = fman_port_config(port, ¶ms);
1233 pr_err("%s: fman_port_config failed\n", __func__);
1237 err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
1239 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
1244 err = fman_port_init(port);
1246 pr_err("%s: fm_port_init failed\n", __func__);
1251 static int dpaa_eth_init_ports(struct mac_device *mac_dev,
1252 struct dpaa_bp **bps, size_t count,
1253 struct fm_port_fqs *port_fqs,
1254 struct dpaa_buffer_layout *buf_layout,
1257 struct fman_port *rxport = mac_dev->port[RX];
1258 struct fman_port *txport = mac_dev->port[TX];
1261 err = dpaa_eth_init_tx_port(txport, port_fqs->tx_errq,
1262 port_fqs->tx_defq, &buf_layout[TX]);
1266 err = dpaa_eth_init_rx_port(rxport, bps, count, port_fqs->rx_errq,
1267 port_fqs->rx_defq, port_fqs->rx_pcdq,
1273 static int dpaa_bman_release(const struct dpaa_bp *dpaa_bp,
1274 struct bm_buffer *bmb, int cnt)
1278 err = bman_release(dpaa_bp->pool, bmb, cnt);
1279 /* Should never occur, address anyway to avoid leaking the buffers */
1280 if (unlikely(WARN_ON(err)) && dpaa_bp->free_buf_cb)
1282 dpaa_bp->free_buf_cb(dpaa_bp, &bmb[cnt]);
1287 static void dpaa_release_sgt_members(struct qm_sg_entry *sgt)
1289 struct bm_buffer bmb[DPAA_BUFF_RELEASE_MAX];
1290 struct dpaa_bp *dpaa_bp;
1293 memset(bmb, 0, sizeof(bmb));
1296 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1302 WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1304 bm_buffer_set64(&bmb[j], qm_sg_entry_get64(&sgt[i]));
1307 } while (j < ARRAY_SIZE(bmb) &&
1308 !qm_sg_entry_is_final(&sgt[i - 1]) &&
1309 sgt[i - 1].bpid == sgt[i].bpid);
1311 dpaa_bman_release(dpaa_bp, bmb, j);
1312 } while (!qm_sg_entry_is_final(&sgt[i - 1]));
1315 static void dpaa_fd_release(const struct net_device *net_dev,
1316 const struct qm_fd *fd)
1318 struct qm_sg_entry *sgt;
1319 struct dpaa_bp *dpaa_bp;
1320 struct bm_buffer bmb;
1325 bm_buffer_set64(&bmb, qm_fd_addr(fd));
1327 dpaa_bp = dpaa_bpid2pool(fd->bpid);
1331 if (qm_fd_get_format(fd) == qm_fd_sg) {
1332 vaddr = phys_to_virt(qm_fd_addr(fd));
1333 sgt = vaddr + qm_fd_get_offset(fd);
1335 dma_unmap_single(dpaa_bp->dev, qm_fd_addr(fd), dpaa_bp->size,
1338 dpaa_release_sgt_members(sgt);
1340 addr = dma_map_single(dpaa_bp->dev, vaddr, dpaa_bp->size,
1342 if (dma_mapping_error(dpaa_bp->dev, addr)) {
1343 dev_err(dpaa_bp->dev, "DMA mapping failed");
1346 bm_buffer_set64(&bmb, addr);
1349 dpaa_bman_release(dpaa_bp, &bmb, 1);
1352 static void count_ern(struct dpaa_percpu_priv *percpu_priv,
1353 const union qm_mr_entry *msg)
1355 switch (msg->ern.rc & QM_MR_RC_MASK) {
1356 case QM_MR_RC_CGR_TAILDROP:
1357 percpu_priv->ern_cnt.cg_tdrop++;
1360 percpu_priv->ern_cnt.wred++;
1362 case QM_MR_RC_ERROR:
1363 percpu_priv->ern_cnt.err_cond++;
1365 case QM_MR_RC_ORPWINDOW_EARLY:
1366 percpu_priv->ern_cnt.early_window++;
1368 case QM_MR_RC_ORPWINDOW_LATE:
1369 percpu_priv->ern_cnt.late_window++;
1371 case QM_MR_RC_FQ_TAILDROP:
1372 percpu_priv->ern_cnt.fq_tdrop++;
1374 case QM_MR_RC_ORPWINDOW_RETIRED:
1375 percpu_priv->ern_cnt.fq_retired++;
1377 case QM_MR_RC_ORP_ZERO:
1378 percpu_priv->ern_cnt.orp_zero++;
1383 /* Turn on HW checksum computation for this outgoing frame.
1384 * If the current protocol is not something we support in this regard
1385 * (or if the stack has already computed the SW checksum), we do nothing.
1387 * Returns 0 if all goes well (or HW csum doesn't apply), and a negative value
1390 * Note that this function may modify the fd->cmd field and the skb data buffer
1391 * (the Parse Results area).
1393 static int dpaa_enable_tx_csum(struct dpaa_priv *priv,
1394 struct sk_buff *skb,
1396 char *parse_results)
1398 struct fman_prs_result *parse_result;
1399 u16 ethertype = ntohs(skb->protocol);
1400 struct ipv6hdr *ipv6h = NULL;
1405 if (skb->ip_summed != CHECKSUM_PARTIAL)
1408 /* Note: L3 csum seems to be already computed in sw, but we can't choose
1409 * L4 alone from the FM configuration anyway.
1412 /* Fill in some fields of the Parse Results array, so the FMan
1413 * can find them as if they came from the FMan Parser.
1415 parse_result = (struct fman_prs_result *)parse_results;
1417 /* If we're dealing with VLAN, get the real Ethernet type */
1418 if (ethertype == ETH_P_8021Q) {
1419 /* We can't always assume the MAC header is set correctly
1420 * by the stack, so reset to beginning of skb->data
1422 skb_reset_mac_header(skb);
1423 ethertype = ntohs(vlan_eth_hdr(skb)->h_vlan_encapsulated_proto);
1426 /* Fill in the relevant L3 parse result fields
1427 * and read the L4 protocol type
1429 switch (ethertype) {
1431 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV4);
1434 l4_proto = iph->protocol;
1437 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV6);
1438 ipv6h = ipv6_hdr(skb);
1440 l4_proto = ipv6h->nexthdr;
1443 /* We shouldn't even be here */
1444 if (net_ratelimit())
1445 netif_alert(priv, tx_err, priv->net_dev,
1446 "Can't compute HW csum for L3 proto 0x%x\n",
1447 ntohs(skb->protocol));
1452 /* Fill in the relevant L4 parse result fields */
1455 parse_result->l4r = FM_L4_PARSE_RESULT_UDP;
1458 parse_result->l4r = FM_L4_PARSE_RESULT_TCP;
1461 if (net_ratelimit())
1462 netif_alert(priv, tx_err, priv->net_dev,
1463 "Can't compute HW csum for L4 proto 0x%x\n",
1469 /* At index 0 is IPOffset_1 as defined in the Parse Results */
1470 parse_result->ip_off[0] = (u8)skb_network_offset(skb);
1471 parse_result->l4_off = (u8)skb_transport_offset(skb);
1473 /* Enable L3 (and L4, if TCP or UDP) HW checksum. */
1474 fd->cmd |= cpu_to_be32(FM_FD_CMD_RPD | FM_FD_CMD_DTC);
1476 /* On P1023 and similar platforms fd->cmd interpretation could
1477 * be disabled by setting CONTEXT_A bit ICMD; currently this bit
1478 * is not set so we do not need to check; in the future, if/when
1479 * using context_a we need to check this bit
1486 static int dpaa_bp_add_8_bufs(const struct dpaa_bp *dpaa_bp)
1488 struct device *dev = dpaa_bp->dev;
1489 struct bm_buffer bmb[8];
1494 for (i = 0; i < 8; i++) {
1495 new_buf = netdev_alloc_frag(dpaa_bp->raw_size);
1496 if (unlikely(!new_buf)) {
1497 dev_err(dev, "netdev_alloc_frag() failed, size %zu\n",
1499 goto release_previous_buffs;
1501 new_buf = PTR_ALIGN(new_buf, SMP_CACHE_BYTES);
1503 addr = dma_map_single(dev, new_buf,
1504 dpaa_bp->size, DMA_FROM_DEVICE);
1505 if (unlikely(dma_mapping_error(dev, addr))) {
1506 dev_err(dpaa_bp->dev, "DMA map failed");
1507 goto release_previous_buffs;
1511 bm_buffer_set64(&bmb[i], addr);
1515 return dpaa_bman_release(dpaa_bp, bmb, i);
1517 release_previous_buffs:
1518 WARN_ONCE(1, "dpaa_eth: failed to add buffers on Rx\n");
1520 bm_buffer_set64(&bmb[i], 0);
1521 /* Avoid releasing a completely null buffer; bman_release() requires
1522 * at least one buffer.
1530 static int dpaa_bp_seed(struct dpaa_bp *dpaa_bp)
1534 /* Give each CPU an allotment of "config_count" buffers */
1535 for_each_possible_cpu(i) {
1536 int *count_ptr = per_cpu_ptr(dpaa_bp->percpu_count, i);
1539 /* Although we access another CPU's counters here
1540 * we do it at boot time so it is safe
1542 for (j = 0; j < dpaa_bp->config_count; j += 8)
1543 *count_ptr += dpaa_bp_add_8_bufs(dpaa_bp);
1548 /* Add buffers/(pages) for Rx processing whenever bpool count falls below
1551 static int dpaa_eth_refill_bpool(struct dpaa_bp *dpaa_bp, int *countptr)
1553 int count = *countptr;
1556 if (unlikely(count < FSL_DPAA_ETH_REFILL_THRESHOLD)) {
1558 new_bufs = dpaa_bp_add_8_bufs(dpaa_bp);
1559 if (unlikely(!new_bufs)) {
1560 /* Avoid looping forever if we've temporarily
1561 * run out of memory. We'll try again at the
1567 } while (count < FSL_DPAA_ETH_MAX_BUF_COUNT);
1570 if (unlikely(count < FSL_DPAA_ETH_MAX_BUF_COUNT))
1577 static int dpaa_eth_refill_bpools(struct dpaa_priv *priv)
1579 struct dpaa_bp *dpaa_bp;
1583 for (i = 0; i < DPAA_BPS_NUM; i++) {
1584 dpaa_bp = priv->dpaa_bps[i];
1587 countptr = this_cpu_ptr(dpaa_bp->percpu_count);
1588 res = dpaa_eth_refill_bpool(dpaa_bp, countptr);
1595 /* Cleanup function for outgoing frame descriptors that were built on Tx path,
1596 * either contiguous frames or scatter/gather ones.
1597 * Skb freeing is not handled here.
1599 * This function may be called on error paths in the Tx function, so guard
1600 * against cases when not all fd relevant fields were filled in.
1602 * Return the skb backpointer, since for S/G frames the buffer containing it
1605 static struct sk_buff *dpaa_cleanup_tx_fd(const struct dpaa_priv *priv,
1606 const struct qm_fd *fd)
1608 const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
1609 struct device *dev = priv->net_dev->dev.parent;
1610 dma_addr_t addr = qm_fd_addr(fd);
1611 const struct qm_sg_entry *sgt;
1612 struct sk_buff **skbh, *skb;
1615 skbh = (struct sk_buff **)phys_to_virt(addr);
1618 if (unlikely(qm_fd_get_format(fd) == qm_fd_sg)) {
1619 nr_frags = skb_shinfo(skb)->nr_frags;
1620 dma_unmap_single(dev, addr, qm_fd_get_offset(fd) +
1621 sizeof(struct qm_sg_entry) * (1 + nr_frags),
1624 /* The sgt buffer has been allocated with netdev_alloc_frag(),
1627 sgt = phys_to_virt(addr + qm_fd_get_offset(fd));
1629 /* sgt[0] is from lowmem, was dma_map_single()-ed */
1630 dma_unmap_single(dev, qm_sg_addr(&sgt[0]),
1631 qm_sg_entry_get_len(&sgt[0]), dma_dir);
1633 /* remaining pages were mapped with skb_frag_dma_map() */
1634 for (i = 1; i < nr_frags; i++) {
1635 WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1637 dma_unmap_page(dev, qm_sg_addr(&sgt[i]),
1638 qm_sg_entry_get_len(&sgt[i]), dma_dir);
1641 /* Free the page frag that we allocated on Tx */
1642 skb_free_frag(phys_to_virt(addr));
1644 dma_unmap_single(dev, addr,
1645 skb_tail_pointer(skb) - (u8 *)skbh, dma_dir);
1651 static u8 rx_csum_offload(const struct dpaa_priv *priv, const struct qm_fd *fd)
1653 /* The parser has run and performed L4 checksum validation.
1654 * We know there were no parser errors (and implicitly no
1655 * L4 csum error), otherwise we wouldn't be here.
1657 if ((priv->net_dev->features & NETIF_F_RXCSUM) &&
1658 (be32_to_cpu(fd->status) & FM_FD_STAT_L4CV))
1659 return CHECKSUM_UNNECESSARY;
1661 /* We're here because either the parser didn't run or the L4 checksum
1662 * was not verified. This may include the case of a UDP frame with
1663 * checksum zero or an L4 proto other than TCP/UDP
1665 return CHECKSUM_NONE;
1668 /* Build a linear skb around the received buffer.
1669 * We are guaranteed there is enough room at the end of the data buffer to
1670 * accommodate the shared info area of the skb.
1672 static struct sk_buff *contig_fd_to_skb(const struct dpaa_priv *priv,
1673 const struct qm_fd *fd)
1675 ssize_t fd_off = qm_fd_get_offset(fd);
1676 dma_addr_t addr = qm_fd_addr(fd);
1677 struct dpaa_bp *dpaa_bp;
1678 struct sk_buff *skb;
1681 vaddr = phys_to_virt(addr);
1682 WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
1684 dpaa_bp = dpaa_bpid2pool(fd->bpid);
1688 skb = build_skb(vaddr, dpaa_bp->size +
1689 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
1690 if (unlikely(!skb)) {
1691 WARN_ONCE(1, "Build skb failure on Rx\n");
1694 WARN_ON(fd_off != priv->rx_headroom);
1695 skb_reserve(skb, fd_off);
1696 skb_put(skb, qm_fd_get_length(fd));
1698 skb->ip_summed = rx_csum_offload(priv, fd);
1703 skb_free_frag(vaddr);
1707 /* Build an skb with the data of the first S/G entry in the linear portion and
1708 * the rest of the frame as skb fragments.
1710 * The page fragment holding the S/G Table is recycled here.
1712 static struct sk_buff *sg_fd_to_skb(const struct dpaa_priv *priv,
1713 const struct qm_fd *fd)
1715 ssize_t fd_off = qm_fd_get_offset(fd);
1716 dma_addr_t addr = qm_fd_addr(fd);
1717 const struct qm_sg_entry *sgt;
1718 struct page *page, *head_page;
1719 struct dpaa_bp *dpaa_bp;
1720 void *vaddr, *sg_vaddr;
1721 int frag_off, frag_len;
1722 struct sk_buff *skb;
1729 vaddr = phys_to_virt(addr);
1730 WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
1732 /* Iterate through the SGT entries and add data buffers to the skb */
1733 sgt = vaddr + fd_off;
1735 for (i = 0; i < DPAA_SGT_MAX_ENTRIES; i++) {
1736 /* Extension bit is not supported */
1737 WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1739 sg_addr = qm_sg_addr(&sgt[i]);
1740 sg_vaddr = phys_to_virt(sg_addr);
1741 WARN_ON(!IS_ALIGNED((unsigned long)sg_vaddr,
1744 /* We may use multiple Rx pools */
1745 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1749 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1750 dma_unmap_single(dpaa_bp->dev, sg_addr, dpaa_bp->size,
1753 sz = dpaa_bp->size +
1754 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1755 skb = build_skb(sg_vaddr, sz);
1756 if (WARN_ON(unlikely(!skb)))
1759 skb->ip_summed = rx_csum_offload(priv, fd);
1761 /* Make sure forwarded skbs will have enough space
1762 * on Tx, if extra headers are added.
1764 WARN_ON(fd_off != priv->rx_headroom);
1765 skb_reserve(skb, fd_off);
1766 skb_put(skb, qm_sg_entry_get_len(&sgt[i]));
1768 /* Not the first S/G entry; all data from buffer will
1769 * be added in an skb fragment; fragment index is offset
1770 * by one since first S/G entry was incorporated in the
1771 * linear part of the skb.
1773 * Caution: 'page' may be a tail page.
1775 page = virt_to_page(sg_vaddr);
1776 head_page = virt_to_head_page(sg_vaddr);
1778 /* Compute offset in (possibly tail) page */
1779 page_offset = ((unsigned long)sg_vaddr &
1781 (page_address(page) - page_address(head_page));
1782 /* page_offset only refers to the beginning of sgt[i];
1783 * but the buffer itself may have an internal offset.
1785 frag_off = qm_sg_entry_get_off(&sgt[i]) + page_offset;
1786 frag_len = qm_sg_entry_get_len(&sgt[i]);
1787 /* skb_add_rx_frag() does no checking on the page; if
1788 * we pass it a tail page, we'll end up with
1789 * bad page accounting and eventually with segafults.
1791 skb_add_rx_frag(skb, i - 1, head_page, frag_off,
1792 frag_len, dpaa_bp->size);
1794 /* Update the pool count for the current {cpu x bpool} */
1797 if (qm_sg_entry_is_final(&sgt[i]))
1800 WARN_ONCE(i == DPAA_SGT_MAX_ENTRIES, "No final bit on SGT\n");
1802 /* free the SG table buffer */
1803 skb_free_frag(vaddr);
1808 /* compensate sw bpool counter changes */
1809 for (i--; i >= 0; i--) {
1810 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1812 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1816 /* free all the SG entries */
1817 for (i = 0; i < DPAA_SGT_MAX_ENTRIES ; i++) {
1818 sg_addr = qm_sg_addr(&sgt[i]);
1819 sg_vaddr = phys_to_virt(sg_addr);
1820 skb_free_frag(sg_vaddr);
1821 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1823 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1827 if (qm_sg_entry_is_final(&sgt[i]))
1830 /* free the SGT fragment */
1831 skb_free_frag(vaddr);
1836 static int skb_to_contig_fd(struct dpaa_priv *priv,
1837 struct sk_buff *skb, struct qm_fd *fd,
1840 struct net_device *net_dev = priv->net_dev;
1841 struct device *dev = net_dev->dev.parent;
1842 enum dma_data_direction dma_dir;
1843 unsigned char *buffer_start;
1844 struct sk_buff **skbh;
1848 /* We are guaranteed to have at least tx_headroom bytes
1849 * available, so just use that for offset.
1851 fd->bpid = FSL_DPAA_BPID_INV;
1852 buffer_start = skb->data - priv->tx_headroom;
1853 dma_dir = DMA_TO_DEVICE;
1855 skbh = (struct sk_buff **)buffer_start;
1858 /* Enable L3/L4 hardware checksum computation.
1860 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may
1861 * need to write into the skb.
1863 err = dpaa_enable_tx_csum(priv, skb, fd,
1864 ((char *)skbh) + DPAA_TX_PRIV_DATA_SIZE);
1865 if (unlikely(err < 0)) {
1866 if (net_ratelimit())
1867 netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
1872 /* Fill in the rest of the FD fields */
1873 qm_fd_set_contig(fd, priv->tx_headroom, skb->len);
1874 fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO);
1876 /* Map the entire buffer size that may be seen by FMan, but no more */
1877 addr = dma_map_single(dev, skbh,
1878 skb_tail_pointer(skb) - buffer_start, dma_dir);
1879 if (unlikely(dma_mapping_error(dev, addr))) {
1880 if (net_ratelimit())
1881 netif_err(priv, tx_err, net_dev, "dma_map_single() failed\n");
1884 qm_fd_addr_set64(fd, addr);
1889 static int skb_to_sg_fd(struct dpaa_priv *priv,
1890 struct sk_buff *skb, struct qm_fd *fd)
1892 const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
1893 const int nr_frags = skb_shinfo(skb)->nr_frags;
1894 struct net_device *net_dev = priv->net_dev;
1895 struct device *dev = net_dev->dev.parent;
1896 struct qm_sg_entry *sgt;
1897 struct sk_buff **skbh;
1905 /* get a page frag to store the SGTable */
1906 sz = SKB_DATA_ALIGN(priv->tx_headroom +
1907 sizeof(struct qm_sg_entry) * (1 + nr_frags));
1908 sgt_buf = netdev_alloc_frag(sz);
1909 if (unlikely(!sgt_buf)) {
1910 netdev_err(net_dev, "netdev_alloc_frag() failed for size %d\n",
1915 /* Enable L3/L4 hardware checksum computation.
1917 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may
1918 * need to write into the skb.
1920 err = dpaa_enable_tx_csum(priv, skb, fd,
1921 sgt_buf + DPAA_TX_PRIV_DATA_SIZE);
1922 if (unlikely(err < 0)) {
1923 if (net_ratelimit())
1924 netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
1929 /* SGT[0] is used by the linear part */
1930 sgt = (struct qm_sg_entry *)(sgt_buf + priv->tx_headroom);
1931 frag_len = skb_headlen(skb);
1932 qm_sg_entry_set_len(&sgt[0], frag_len);
1933 sgt[0].bpid = FSL_DPAA_BPID_INV;
1935 addr = dma_map_single(dev, skb->data,
1936 skb_headlen(skb), dma_dir);
1937 if (unlikely(dma_mapping_error(dev, addr))) {
1938 dev_err(dev, "DMA mapping failed");
1940 goto sg0_map_failed;
1942 qm_sg_entry_set64(&sgt[0], addr);
1944 /* populate the rest of SGT entries */
1945 for (i = 0; i < nr_frags; i++) {
1946 frag = &skb_shinfo(skb)->frags[i];
1947 frag_len = frag->size;
1948 WARN_ON(!skb_frag_page(frag));
1949 addr = skb_frag_dma_map(dev, frag, 0,
1951 if (unlikely(dma_mapping_error(dev, addr))) {
1952 dev_err(dev, "DMA mapping failed");
1957 qm_sg_entry_set_len(&sgt[i + 1], frag_len);
1958 sgt[i + 1].bpid = FSL_DPAA_BPID_INV;
1959 sgt[i + 1].offset = 0;
1961 /* keep the offset in the address */
1962 qm_sg_entry_set64(&sgt[i + 1], addr);
1965 /* Set the final bit in the last used entry of the SGT */
1966 qm_sg_entry_set_f(&sgt[nr_frags], frag_len);
1968 qm_fd_set_sg(fd, priv->tx_headroom, skb->len);
1970 /* DMA map the SGT page */
1971 buffer_start = (void *)sgt - priv->tx_headroom;
1972 skbh = (struct sk_buff **)buffer_start;
1975 addr = dma_map_single(dev, buffer_start, priv->tx_headroom +
1976 sizeof(struct qm_sg_entry) * (1 + nr_frags),
1978 if (unlikely(dma_mapping_error(dev, addr))) {
1979 dev_err(dev, "DMA mapping failed");
1981 goto sgt_map_failed;
1984 fd->bpid = FSL_DPAA_BPID_INV;
1985 fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO);
1986 qm_fd_addr_set64(fd, addr);
1992 for (j = 0; j < i; j++)
1993 dma_unmap_page(dev, qm_sg_addr(&sgt[j]),
1994 qm_sg_entry_get_len(&sgt[j]), dma_dir);
1997 skb_free_frag(sgt_buf);
2002 static inline int dpaa_xmit(struct dpaa_priv *priv,
2003 struct rtnl_link_stats64 *percpu_stats,
2007 struct qman_fq *egress_fq;
2010 egress_fq = priv->egress_fqs[queue];
2011 if (fd->bpid == FSL_DPAA_BPID_INV)
2012 fd->cmd |= cpu_to_be32(qman_fq_fqid(priv->conf_fqs[queue]));
2014 /* Trace this Tx fd */
2015 trace_dpaa_tx_fd(priv->net_dev, egress_fq, fd);
2017 for (i = 0; i < DPAA_ENQUEUE_RETRIES; i++) {
2018 err = qman_enqueue(egress_fq, fd);
2023 if (unlikely(err < 0)) {
2024 percpu_stats->tx_fifo_errors++;
2028 percpu_stats->tx_packets++;
2029 percpu_stats->tx_bytes += qm_fd_get_length(fd);
2034 static int dpaa_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
2036 const int queue_mapping = skb_get_queue_mapping(skb);
2037 bool nonlinear = skb_is_nonlinear(skb);
2038 struct rtnl_link_stats64 *percpu_stats;
2039 struct dpaa_percpu_priv *percpu_priv;
2040 struct dpaa_priv *priv;
2045 priv = netdev_priv(net_dev);
2046 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2047 percpu_stats = &percpu_priv->stats;
2049 qm_fd_clear_fd(&fd);
2052 /* We're going to store the skb backpointer at the beginning
2053 * of the data buffer, so we need a privately owned skb
2055 * We've made sure skb is not shared in dev->priv_flags,
2056 * we need to verify the skb head is not cloned
2058 if (skb_cow_head(skb, priv->tx_headroom))
2061 WARN_ON(skb_is_nonlinear(skb));
2064 /* MAX_SKB_FRAGS is equal or larger than our dpaa_SGT_MAX_ENTRIES;
2065 * make sure we don't feed FMan with more fragments than it supports.
2067 if (unlikely(nonlinear &&
2068 (skb_shinfo(skb)->nr_frags >= DPAA_SGT_MAX_ENTRIES))) {
2069 /* If the egress skb contains more fragments than we support
2070 * we have no choice but to linearize it ourselves.
2072 if (__skb_linearize(skb))
2075 nonlinear = skb_is_nonlinear(skb);
2079 /* Just create a S/G fd based on the skb */
2080 err = skb_to_sg_fd(priv, skb, &fd);
2081 percpu_priv->tx_frag_skbuffs++;
2083 /* Create a contig FD from this skb */
2084 err = skb_to_contig_fd(priv, skb, &fd, &offset);
2086 if (unlikely(err < 0))
2087 goto skb_to_fd_failed;
2089 if (likely(dpaa_xmit(priv, percpu_stats, queue_mapping, &fd) == 0))
2090 return NETDEV_TX_OK;
2092 dpaa_cleanup_tx_fd(priv, &fd);
2095 percpu_stats->tx_errors++;
2097 return NETDEV_TX_OK;
2100 static void dpaa_rx_error(struct net_device *net_dev,
2101 const struct dpaa_priv *priv,
2102 struct dpaa_percpu_priv *percpu_priv,
2103 const struct qm_fd *fd,
2106 if (net_ratelimit())
2107 netif_err(priv, hw, net_dev, "Err FD status = 0x%08x\n",
2108 be32_to_cpu(fd->status) & FM_FD_STAT_RX_ERRORS);
2110 percpu_priv->stats.rx_errors++;
2112 if (be32_to_cpu(fd->status) & FM_FD_ERR_DMA)
2113 percpu_priv->rx_errors.dme++;
2114 if (be32_to_cpu(fd->status) & FM_FD_ERR_PHYSICAL)
2115 percpu_priv->rx_errors.fpe++;
2116 if (be32_to_cpu(fd->status) & FM_FD_ERR_SIZE)
2117 percpu_priv->rx_errors.fse++;
2118 if (be32_to_cpu(fd->status) & FM_FD_ERR_PRS_HDR_ERR)
2119 percpu_priv->rx_errors.phe++;
2121 dpaa_fd_release(net_dev, fd);
2124 static void dpaa_tx_error(struct net_device *net_dev,
2125 const struct dpaa_priv *priv,
2126 struct dpaa_percpu_priv *percpu_priv,
2127 const struct qm_fd *fd,
2130 struct sk_buff *skb;
2132 if (net_ratelimit())
2133 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2134 be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS);
2136 percpu_priv->stats.tx_errors++;
2138 skb = dpaa_cleanup_tx_fd(priv, fd);
2142 static int dpaa_eth_poll(struct napi_struct *napi, int budget)
2144 struct dpaa_napi_portal *np =
2145 container_of(napi, struct dpaa_napi_portal, napi);
2147 int cleaned = qman_p_poll_dqrr(np->p, budget);
2149 if (cleaned < budget) {
2150 napi_complete_done(napi, cleaned);
2151 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
2153 } else if (np->down) {
2154 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
2160 static void dpaa_tx_conf(struct net_device *net_dev,
2161 const struct dpaa_priv *priv,
2162 struct dpaa_percpu_priv *percpu_priv,
2163 const struct qm_fd *fd,
2166 struct sk_buff *skb;
2168 if (unlikely(be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS)) {
2169 if (net_ratelimit())
2170 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2171 be32_to_cpu(fd->status) &
2172 FM_FD_STAT_TX_ERRORS);
2174 percpu_priv->stats.tx_errors++;
2177 percpu_priv->tx_confirm++;
2179 skb = dpaa_cleanup_tx_fd(priv, fd);
2184 static inline int dpaa_eth_napi_schedule(struct dpaa_percpu_priv *percpu_priv,
2185 struct qman_portal *portal)
2187 if (unlikely(in_irq() || !in_serving_softirq())) {
2188 /* Disable QMan IRQ and invoke NAPI */
2189 qman_p_irqsource_remove(portal, QM_PIRQ_DQRI);
2191 percpu_priv->np.p = portal;
2192 napi_schedule(&percpu_priv->np.napi);
2193 percpu_priv->in_interrupt++;
2199 static enum qman_cb_dqrr_result rx_error_dqrr(struct qman_portal *portal,
2201 const struct qm_dqrr_entry *dq)
2203 struct dpaa_fq *dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
2204 struct dpaa_percpu_priv *percpu_priv;
2205 struct net_device *net_dev;
2206 struct dpaa_bp *dpaa_bp;
2207 struct dpaa_priv *priv;
2209 net_dev = dpaa_fq->net_dev;
2210 priv = netdev_priv(net_dev);
2211 dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
2213 return qman_cb_dqrr_consume;
2215 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2217 if (dpaa_eth_napi_schedule(percpu_priv, portal))
2218 return qman_cb_dqrr_stop;
2220 dpaa_eth_refill_bpools(priv);
2221 dpaa_rx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2223 return qman_cb_dqrr_consume;
2226 static enum qman_cb_dqrr_result rx_default_dqrr(struct qman_portal *portal,
2228 const struct qm_dqrr_entry *dq)
2230 struct rtnl_link_stats64 *percpu_stats;
2231 struct dpaa_percpu_priv *percpu_priv;
2232 const struct qm_fd *fd = &dq->fd;
2233 dma_addr_t addr = qm_fd_addr(fd);
2234 enum qm_fd_format fd_format;
2235 struct net_device *net_dev;
2236 u32 fd_status, hash_offset;
2237 struct dpaa_bp *dpaa_bp;
2238 struct dpaa_priv *priv;
2239 unsigned int skb_len;
2240 struct sk_buff *skb;
2244 fd_status = be32_to_cpu(fd->status);
2245 fd_format = qm_fd_get_format(fd);
2246 net_dev = ((struct dpaa_fq *)fq)->net_dev;
2247 priv = netdev_priv(net_dev);
2248 dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
2250 return qman_cb_dqrr_consume;
2252 /* Trace the Rx fd */
2253 trace_dpaa_rx_fd(net_dev, fq, &dq->fd);
2255 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2256 percpu_stats = &percpu_priv->stats;
2258 if (unlikely(dpaa_eth_napi_schedule(percpu_priv, portal)))
2259 return qman_cb_dqrr_stop;
2261 /* Make sure we didn't run out of buffers */
2262 if (unlikely(dpaa_eth_refill_bpools(priv))) {
2263 /* Unable to refill the buffer pool due to insufficient
2264 * system memory. Just release the frame back into the pool,
2265 * otherwise we'll soon end up with an empty buffer pool.
2267 dpaa_fd_release(net_dev, &dq->fd);
2268 return qman_cb_dqrr_consume;
2271 if (unlikely(fd_status & FM_FD_STAT_RX_ERRORS) != 0) {
2272 if (net_ratelimit())
2273 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2274 fd_status & FM_FD_STAT_RX_ERRORS);
2276 percpu_stats->rx_errors++;
2277 dpaa_fd_release(net_dev, fd);
2278 return qman_cb_dqrr_consume;
2281 dpaa_bp = dpaa_bpid2pool(fd->bpid);
2283 return qman_cb_dqrr_consume;
2285 dma_unmap_single(dpaa_bp->dev, addr, dpaa_bp->size, DMA_FROM_DEVICE);
2287 /* prefetch the first 64 bytes of the frame or the SGT start */
2288 vaddr = phys_to_virt(addr);
2289 prefetch(vaddr + qm_fd_get_offset(fd));
2291 /* The only FD types that we may receive are contig and S/G */
2292 WARN_ON((fd_format != qm_fd_contig) && (fd_format != qm_fd_sg));
2294 /* Account for either the contig buffer or the SGT buffer (depending on
2295 * which case we were in) having been removed from the pool.
2297 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
2300 if (likely(fd_format == qm_fd_contig))
2301 skb = contig_fd_to_skb(priv, fd);
2303 skb = sg_fd_to_skb(priv, fd);
2305 return qman_cb_dqrr_consume;
2307 skb->protocol = eth_type_trans(skb, net_dev);
2309 if (net_dev->features & NETIF_F_RXHASH && priv->keygen_in_use &&
2310 !fman_port_get_hash_result_offset(priv->mac_dev->port[RX],
2312 enum pkt_hash_types type;
2314 /* if L4 exists, it was used in the hash generation */
2315 type = be32_to_cpu(fd->status) & FM_FD_STAT_L4CV ?
2316 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3;
2317 skb_set_hash(skb, be32_to_cpu(*(u32 *)(vaddr + hash_offset)),
2323 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP)) {
2324 percpu_stats->rx_dropped++;
2325 return qman_cb_dqrr_consume;
2328 percpu_stats->rx_packets++;
2329 percpu_stats->rx_bytes += skb_len;
2331 return qman_cb_dqrr_consume;
2334 static enum qman_cb_dqrr_result conf_error_dqrr(struct qman_portal *portal,
2336 const struct qm_dqrr_entry *dq)
2338 struct dpaa_percpu_priv *percpu_priv;
2339 struct net_device *net_dev;
2340 struct dpaa_priv *priv;
2342 net_dev = ((struct dpaa_fq *)fq)->net_dev;
2343 priv = netdev_priv(net_dev);
2345 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2347 if (dpaa_eth_napi_schedule(percpu_priv, portal))
2348 return qman_cb_dqrr_stop;
2350 dpaa_tx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2352 return qman_cb_dqrr_consume;
2355 static enum qman_cb_dqrr_result conf_dflt_dqrr(struct qman_portal *portal,
2357 const struct qm_dqrr_entry *dq)
2359 struct dpaa_percpu_priv *percpu_priv;
2360 struct net_device *net_dev;
2361 struct dpaa_priv *priv;
2363 net_dev = ((struct dpaa_fq *)fq)->net_dev;
2364 priv = netdev_priv(net_dev);
2367 trace_dpaa_tx_conf_fd(net_dev, fq, &dq->fd);
2369 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2371 if (dpaa_eth_napi_schedule(percpu_priv, portal))
2372 return qman_cb_dqrr_stop;
2374 dpaa_tx_conf(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2376 return qman_cb_dqrr_consume;
2379 static void egress_ern(struct qman_portal *portal,
2381 const union qm_mr_entry *msg)
2383 const struct qm_fd *fd = &msg->ern.fd;
2384 struct dpaa_percpu_priv *percpu_priv;
2385 const struct dpaa_priv *priv;
2386 struct net_device *net_dev;
2387 struct sk_buff *skb;
2389 net_dev = ((struct dpaa_fq *)fq)->net_dev;
2390 priv = netdev_priv(net_dev);
2391 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2393 percpu_priv->stats.tx_dropped++;
2394 percpu_priv->stats.tx_fifo_errors++;
2395 count_ern(percpu_priv, msg);
2397 skb = dpaa_cleanup_tx_fd(priv, fd);
2398 dev_kfree_skb_any(skb);
2401 static const struct dpaa_fq_cbs dpaa_fq_cbs = {
2402 .rx_defq = { .cb = { .dqrr = rx_default_dqrr } },
2403 .tx_defq = { .cb = { .dqrr = conf_dflt_dqrr } },
2404 .rx_errq = { .cb = { .dqrr = rx_error_dqrr } },
2405 .tx_errq = { .cb = { .dqrr = conf_error_dqrr } },
2406 .egress_ern = { .cb = { .ern = egress_ern } }
2409 static void dpaa_eth_napi_enable(struct dpaa_priv *priv)
2411 struct dpaa_percpu_priv *percpu_priv;
2414 for_each_possible_cpu(i) {
2415 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2417 percpu_priv->np.down = 0;
2418 napi_enable(&percpu_priv->np.napi);
2422 static void dpaa_eth_napi_disable(struct dpaa_priv *priv)
2424 struct dpaa_percpu_priv *percpu_priv;
2427 for_each_possible_cpu(i) {
2428 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2430 percpu_priv->np.down = 1;
2431 napi_disable(&percpu_priv->np.napi);
2435 static void dpaa_adjust_link(struct net_device *net_dev)
2437 struct mac_device *mac_dev;
2438 struct dpaa_priv *priv;
2440 priv = netdev_priv(net_dev);
2441 mac_dev = priv->mac_dev;
2442 mac_dev->adjust_link(mac_dev);
2445 static int dpaa_phy_init(struct net_device *net_dev)
2447 struct mac_device *mac_dev;
2448 struct phy_device *phy_dev;
2449 struct dpaa_priv *priv;
2451 priv = netdev_priv(net_dev);
2452 mac_dev = priv->mac_dev;
2454 phy_dev = of_phy_connect(net_dev, mac_dev->phy_node,
2455 &dpaa_adjust_link, 0,
2458 netif_err(priv, ifup, net_dev, "init_phy() failed\n");
2462 /* Remove any features not supported by the controller */
2463 phy_dev->supported &= mac_dev->if_support;
2464 phy_dev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
2465 phy_dev->advertising = phy_dev->supported;
2467 mac_dev->phy_dev = phy_dev;
2468 net_dev->phydev = phy_dev;
2473 static int dpaa_open(struct net_device *net_dev)
2475 struct mac_device *mac_dev;
2476 struct dpaa_priv *priv;
2479 priv = netdev_priv(net_dev);
2480 mac_dev = priv->mac_dev;
2481 dpaa_eth_napi_enable(priv);
2483 err = dpaa_phy_init(net_dev);
2485 goto phy_init_failed;
2487 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
2488 err = fman_port_enable(mac_dev->port[i]);
2490 goto mac_start_failed;
2493 err = priv->mac_dev->start(mac_dev);
2495 netif_err(priv, ifup, net_dev, "mac_dev->start() = %d\n", err);
2496 goto mac_start_failed;
2499 netif_tx_start_all_queues(net_dev);
2504 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++)
2505 fman_port_disable(mac_dev->port[i]);
2508 dpaa_eth_napi_disable(priv);
2513 static int dpaa_eth_stop(struct net_device *net_dev)
2515 struct dpaa_priv *priv;
2518 err = dpaa_stop(net_dev);
2520 priv = netdev_priv(net_dev);
2521 dpaa_eth_napi_disable(priv);
2526 static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
2528 if (!net_dev->phydev)
2530 return phy_mii_ioctl(net_dev->phydev, rq, cmd);
2533 static const struct net_device_ops dpaa_ops = {
2534 .ndo_open = dpaa_open,
2535 .ndo_start_xmit = dpaa_start_xmit,
2536 .ndo_stop = dpaa_eth_stop,
2537 .ndo_tx_timeout = dpaa_tx_timeout,
2538 .ndo_get_stats64 = dpaa_get_stats64,
2539 .ndo_set_mac_address = dpaa_set_mac_address,
2540 .ndo_validate_addr = eth_validate_addr,
2541 .ndo_set_rx_mode = dpaa_set_rx_mode,
2542 .ndo_do_ioctl = dpaa_ioctl,
2543 .ndo_setup_tc = dpaa_setup_tc,
2546 static int dpaa_napi_add(struct net_device *net_dev)
2548 struct dpaa_priv *priv = netdev_priv(net_dev);
2549 struct dpaa_percpu_priv *percpu_priv;
2552 for_each_possible_cpu(cpu) {
2553 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
2555 netif_napi_add(net_dev, &percpu_priv->np.napi,
2556 dpaa_eth_poll, NAPI_POLL_WEIGHT);
2562 static void dpaa_napi_del(struct net_device *net_dev)
2564 struct dpaa_priv *priv = netdev_priv(net_dev);
2565 struct dpaa_percpu_priv *percpu_priv;
2568 for_each_possible_cpu(cpu) {
2569 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
2571 netif_napi_del(&percpu_priv->np.napi);
2575 static inline void dpaa_bp_free_pf(const struct dpaa_bp *bp,
2576 struct bm_buffer *bmb)
2578 dma_addr_t addr = bm_buf_addr(bmb);
2580 dma_unmap_single(bp->dev, addr, bp->size, DMA_FROM_DEVICE);
2582 skb_free_frag(phys_to_virt(addr));
2585 /* Alloc the dpaa_bp struct and configure default values */
2586 static struct dpaa_bp *dpaa_bp_alloc(struct device *dev)
2588 struct dpaa_bp *dpaa_bp;
2590 dpaa_bp = devm_kzalloc(dev, sizeof(*dpaa_bp), GFP_KERNEL);
2592 return ERR_PTR(-ENOMEM);
2594 dpaa_bp->bpid = FSL_DPAA_BPID_INV;
2595 dpaa_bp->percpu_count = devm_alloc_percpu(dev, *dpaa_bp->percpu_count);
2596 if (!dpaa_bp->percpu_count)
2597 return ERR_PTR(-ENOMEM);
2599 dpaa_bp->config_count = FSL_DPAA_ETH_MAX_BUF_COUNT;
2601 dpaa_bp->seed_cb = dpaa_bp_seed;
2602 dpaa_bp->free_buf_cb = dpaa_bp_free_pf;
2607 /* Place all ingress FQs (Rx Default, Rx Error) in a dedicated CGR.
2608 * We won't be sending congestion notifications to FMan; for now, we just use
2609 * this CGR to generate enqueue rejections to FMan in order to drop the frames
2610 * before they reach our ingress queues and eat up memory.
2612 static int dpaa_ingress_cgr_init(struct dpaa_priv *priv)
2614 struct qm_mcc_initcgr initcgr;
2618 err = qman_alloc_cgrid(&priv->ingress_cgr.cgrid);
2620 if (netif_msg_drv(priv))
2621 pr_err("Error %d allocating CGR ID\n", err);
2625 /* Enable CS TD, but disable Congestion State Change Notifications. */
2626 memset(&initcgr, 0, sizeof(initcgr));
2627 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CS_THRES);
2628 initcgr.cgr.cscn_en = QM_CGR_EN;
2629 cs_th = DPAA_INGRESS_CS_THRESHOLD;
2630 qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
2632 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN);
2633 initcgr.cgr.cstd_en = QM_CGR_EN;
2635 /* This CGR will be associated with the SWP affined to the current CPU.
2636 * However, we'll place all our ingress FQs in it.
2638 err = qman_create_cgr(&priv->ingress_cgr, QMAN_CGR_FLAG_USE_INIT,
2641 if (netif_msg_drv(priv))
2642 pr_err("Error %d creating ingress CGR with ID %d\n",
2643 err, priv->ingress_cgr.cgrid);
2644 qman_release_cgrid(priv->ingress_cgr.cgrid);
2647 if (netif_msg_drv(priv))
2648 pr_debug("Created ingress CGR %d for netdev with hwaddr %pM\n",
2649 priv->ingress_cgr.cgrid, priv->mac_dev->addr);
2651 priv->use_ingress_cgr = true;
2657 static const struct of_device_id dpaa_match[];
2659 static inline u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl)
2663 /* The frame headroom must accommodate:
2664 * - the driver private data area
2665 * - parse results, hash results, timestamp if selected
2666 * If either hash results or time stamp are selected, both will
2667 * be copied to/from the frame headroom, as TS is located between PR and
2668 * HR in the IC and IC copy size has a granularity of 16bytes
2669 * (see description of FMBM_RICP and FMBM_TICP registers in DPAARM)
2671 * Also make sure the headroom is a multiple of data_align bytes
2673 headroom = (u16)(bl->priv_data_size + DPAA_PARSE_RESULTS_SIZE +
2674 DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE);
2676 return DPAA_FD_DATA_ALIGNMENT ? ALIGN(headroom,
2677 DPAA_FD_DATA_ALIGNMENT) :
2681 static int dpaa_eth_probe(struct platform_device *pdev)
2683 struct dpaa_bp *dpaa_bps[DPAA_BPS_NUM] = {NULL};
2684 struct net_device *net_dev = NULL;
2685 struct dpaa_fq *dpaa_fq, *tmp;
2686 struct dpaa_priv *priv = NULL;
2687 struct fm_port_fqs port_fqs;
2688 struct mac_device *mac_dev;
2689 int err = 0, i, channel;
2692 /* device used for DMA mapping */
2693 dev = pdev->dev.parent;
2694 err = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(40));
2696 dev_err(dev, "dma_coerce_mask_and_coherent() failed\n");
2700 /* Allocate this early, so we can store relevant information in
2703 net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA_ETH_TXQ_NUM);
2705 dev_err(dev, "alloc_etherdev_mq() failed\n");
2709 /* Do this here, so we can be verbose early */
2710 SET_NETDEV_DEV(net_dev, dev);
2711 dev_set_drvdata(dev, net_dev);
2713 priv = netdev_priv(net_dev);
2714 priv->net_dev = net_dev;
2716 priv->msg_enable = netif_msg_init(debug, DPAA_MSG_DEFAULT);
2718 mac_dev = dpaa_mac_dev_get(pdev);
2719 if (IS_ERR(mac_dev)) {
2720 dev_err(dev, "dpaa_mac_dev_get() failed\n");
2721 err = PTR_ERR(mac_dev);
2725 /* If fsl_fm_max_frm is set to a higher value than the all-common 1500,
2726 * we choose conservatively and let the user explicitly set a higher
2727 * MTU via ifconfig. Otherwise, the user may end up with different MTUs
2729 * If on the other hand fsl_fm_max_frm has been chosen below 1500,
2730 * start with the maximum allowed.
2732 net_dev->mtu = min(dpaa_get_max_mtu(), ETH_DATA_LEN);
2734 netdev_dbg(net_dev, "Setting initial MTU on net device: %d\n",
2737 priv->buf_layout[RX].priv_data_size = DPAA_RX_PRIV_DATA_SIZE; /* Rx */
2738 priv->buf_layout[TX].priv_data_size = DPAA_TX_PRIV_DATA_SIZE; /* Tx */
2741 for (i = 0; i < DPAA_BPS_NUM; i++) {
2742 dpaa_bps[i] = dpaa_bp_alloc(dev);
2743 if (IS_ERR(dpaa_bps[i])) {
2744 err = PTR_ERR(dpaa_bps[i]);
2747 /* the raw size of the buffers used for reception */
2748 dpaa_bps[i]->raw_size = bpool_buffer_raw_size(i, DPAA_BPS_NUM);
2749 /* avoid runtime computations by keeping the usable size here */
2750 dpaa_bps[i]->size = dpaa_bp_size(dpaa_bps[i]->raw_size);
2751 dpaa_bps[i]->dev = dev;
2753 err = dpaa_bp_alloc_pool(dpaa_bps[i]);
2756 priv->dpaa_bps[i] = dpaa_bps[i];
2759 INIT_LIST_HEAD(&priv->dpaa_fq_list);
2761 memset(&port_fqs, 0, sizeof(port_fqs));
2763 err = dpaa_alloc_all_fqs(dev, &priv->dpaa_fq_list, &port_fqs);
2765 dev_err(dev, "dpaa_alloc_all_fqs() failed\n");
2769 priv->mac_dev = mac_dev;
2771 channel = dpaa_get_channel();
2773 dev_err(dev, "dpaa_get_channel() failed\n");
2778 priv->channel = (u16)channel;
2780 /* Walk the CPUs with affine portals
2781 * and add this pool channel to each's dequeue mask.
2783 dpaa_eth_add_channel(priv->channel);
2785 dpaa_fq_setup(priv, &dpaa_fq_cbs, priv->mac_dev->port[TX]);
2787 /* Create a congestion group for this netdev, with
2788 * dynamically-allocated CGR ID.
2789 * Must be executed after probing the MAC, but before
2790 * assigning the egress FQs to the CGRs.
2792 err = dpaa_eth_cgr_init(priv);
2794 dev_err(dev, "Error initializing CGR\n");
2798 err = dpaa_ingress_cgr_init(priv);
2800 dev_err(dev, "Error initializing ingress CGR\n");
2801 goto delete_egress_cgr;
2804 /* Add the FQs to the interface, and make them active */
2805 list_for_each_entry_safe(dpaa_fq, tmp, &priv->dpaa_fq_list, list) {
2806 err = dpaa_fq_init(dpaa_fq, false);
2811 priv->tx_headroom = dpaa_get_headroom(&priv->buf_layout[TX]);
2812 priv->rx_headroom = dpaa_get_headroom(&priv->buf_layout[RX]);
2814 /* All real interfaces need their ports initialized */
2815 err = dpaa_eth_init_ports(mac_dev, dpaa_bps, DPAA_BPS_NUM, &port_fqs,
2816 &priv->buf_layout[0], dev);
2820 /* Rx traffic distribution based on keygen hashing defaults to on */
2821 priv->keygen_in_use = true;
2823 priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv);
2824 if (!priv->percpu_priv) {
2825 dev_err(dev, "devm_alloc_percpu() failed\n");
2831 netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM);
2833 /* Initialize NAPI */
2834 err = dpaa_napi_add(net_dev);
2836 goto delete_dpaa_napi;
2838 err = dpaa_netdev_init(net_dev, &dpaa_ops, tx_timeout);
2840 goto delete_dpaa_napi;
2842 dpaa_eth_sysfs_init(&net_dev->dev);
2844 netif_info(priv, probe, net_dev, "Probed interface %s\n",
2850 dpaa_napi_del(net_dev);
2852 dpaa_fq_free(dev, &priv->dpaa_fq_list);
2853 qman_delete_cgr_safe(&priv->ingress_cgr);
2854 qman_release_cgrid(priv->ingress_cgr.cgrid);
2856 qman_delete_cgr_safe(&priv->cgr_data.cgr);
2857 qman_release_cgrid(priv->cgr_data.cgr.cgrid);
2859 dpaa_bps_free(priv);
2861 dev_set_drvdata(dev, NULL);
2862 free_netdev(net_dev);
2867 static int dpaa_remove(struct platform_device *pdev)
2869 struct net_device *net_dev;
2870 struct dpaa_priv *priv;
2874 dev = pdev->dev.parent;
2875 net_dev = dev_get_drvdata(dev);
2877 priv = netdev_priv(net_dev);
2879 dpaa_eth_sysfs_remove(dev);
2881 dev_set_drvdata(dev, NULL);
2882 unregister_netdev(net_dev);
2884 err = dpaa_fq_free(dev, &priv->dpaa_fq_list);
2886 qman_delete_cgr_safe(&priv->ingress_cgr);
2887 qman_release_cgrid(priv->ingress_cgr.cgrid);
2888 qman_delete_cgr_safe(&priv->cgr_data.cgr);
2889 qman_release_cgrid(priv->cgr_data.cgr.cgrid);
2891 dpaa_napi_del(net_dev);
2893 dpaa_bps_free(priv);
2895 free_netdev(net_dev);
2900 static const struct platform_device_id dpaa_devtype[] = {
2902 .name = "dpaa-ethernet",
2907 MODULE_DEVICE_TABLE(platform, dpaa_devtype);
2909 static struct platform_driver dpaa_driver = {
2911 .name = KBUILD_MODNAME,
2913 .id_table = dpaa_devtype,
2914 .probe = dpaa_eth_probe,
2915 .remove = dpaa_remove
2918 static int __init dpaa_load(void)
2922 pr_debug("FSL DPAA Ethernet driver\n");
2924 /* initialize dpaa_eth mirror values */
2925 dpaa_rx_extra_headroom = fman_get_rx_extra_headroom();
2926 dpaa_max_frm = fman_get_max_frm();
2928 err = platform_driver_register(&dpaa_driver);
2930 pr_err("Error, platform_driver_register() = %d\n", err);
2934 module_init(dpaa_load);
2936 static void __exit dpaa_unload(void)
2938 platform_driver_unregister(&dpaa_driver);
2940 /* Only one channel is used and needs to be released after all
2941 * interfaces are removed
2943 dpaa_release_channel();
2945 module_exit(dpaa_unload);
2947 MODULE_LICENSE("Dual BSD/GPL");
2948 MODULE_DESCRIPTION("FSL DPAA Ethernet driver");