1 /* Copyright 2008 - 2016 Freescale Semiconductor Inc.
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are met:
5 * * Redistributions of source code must retain the above copyright
6 * notice, this list of conditions and the following disclaimer.
7 * * Redistributions in binary form must reproduce the above copyright
8 * notice, this list of conditions and the following disclaimer in the
9 * documentation and/or other materials provided with the distribution.
10 * * Neither the name of Freescale Semiconductor nor the
11 * names of its contributors may be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * ALTERNATIVELY, this software may be distributed under the terms of the
15 * GNU General Public License ("GPL") as published by the Free Software
16 * Foundation, either version 2 of that License or (at your option) any
19 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
33 #include <linux/init.h>
34 #include <linux/module.h>
35 #include <linux/of_platform.h>
36 #include <linux/of_mdio.h>
37 #include <linux/of_net.h>
39 #include <linux/if_arp.h>
40 #include <linux/if_vlan.h>
41 #include <linux/icmp.h>
43 #include <linux/ipv6.h>
44 #include <linux/udp.h>
45 #include <linux/tcp.h>
46 #include <linux/net.h>
47 #include <linux/skbuff.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/highmem.h>
51 #include <linux/percpu.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/sort.h>
54 #include <linux/phy_fixed.h>
55 #include <soc/fsl/bman.h>
56 #include <soc/fsl/qman.h>
58 #include "fman_port.h"
62 /* CREATE_TRACE_POINTS only needs to be defined once. Other dpaa files
63 * using trace events only need to #include <trace/events/sched.h>
65 #define CREATE_TRACE_POINTS
66 #include "dpaa_eth_trace.h"
68 static int debug = -1;
69 module_param(debug, int, 0444);
70 MODULE_PARM_DESC(debug, "Module/Driver verbosity level (0=none,...,16=all)");
72 static u16 tx_timeout = 1000;
73 module_param(tx_timeout, ushort, 0444);
74 MODULE_PARM_DESC(tx_timeout, "The Tx timeout in ms");
76 #define FM_FD_STAT_RX_ERRORS \
77 (FM_FD_ERR_DMA | FM_FD_ERR_PHYSICAL | \
78 FM_FD_ERR_SIZE | FM_FD_ERR_CLS_DISCARD | \
79 FM_FD_ERR_EXTRACTION | FM_FD_ERR_NO_SCHEME | \
80 FM_FD_ERR_PRS_TIMEOUT | FM_FD_ERR_PRS_ILL_INSTRUCT | \
81 FM_FD_ERR_PRS_HDR_ERR)
83 #define FM_FD_STAT_TX_ERRORS \
84 (FM_FD_ERR_UNSUPPORTED_FORMAT | \
85 FM_FD_ERR_LENGTH | FM_FD_ERR_DMA)
87 #define DPAA_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
88 NETIF_MSG_LINK | NETIF_MSG_IFUP | \
91 #define DPAA_INGRESS_CS_THRESHOLD 0x10000000
92 /* Ingress congestion threshold on FMan ports
93 * The size in bytes of the ingress tail-drop threshold on FMan ports.
94 * Traffic piling up above this value will be rejected by QMan and discarded
98 /* Size in bytes of the FQ taildrop threshold */
99 #define DPAA_FQ_TD 0x200000
101 #define DPAA_CS_THRESHOLD_1G 0x06000000
102 /* Egress congestion threshold on 1G ports, range 0x1000 .. 0x10000000
103 * The size in bytes of the egress Congestion State notification threshold on
104 * 1G ports. The 1G dTSECs can quite easily be flooded by cores doing Tx in a
105 * tight loop (e.g. by sending UDP datagrams at "while(1) speed"),
106 * and the larger the frame size, the more acute the problem.
107 * So we have to find a balance between these factors:
108 * - avoiding the device staying congested for a prolonged time (risking
109 * the netdev watchdog to fire - see also the tx_timeout module param);
110 * - affecting performance of protocols such as TCP, which otherwise
111 * behave well under the congestion notification mechanism;
112 * - preventing the Tx cores from tightly-looping (as if the congestion
113 * threshold was too low to be effective);
114 * - running out of memory if the CS threshold is set too high.
117 #define DPAA_CS_THRESHOLD_10G 0x10000000
118 /* The size in bytes of the egress Congestion State notification threshold on
119 * 10G ports, range 0x1000 .. 0x10000000
122 /* Largest value that the FQD's OAL field can hold */
123 #define FSL_QMAN_MAX_OAL 127
125 /* Default alignment for start of data in an Rx FD */
126 #define DPAA_FD_DATA_ALIGNMENT 16
128 /* The DPAA requires 256 bytes reserved and mapped for the SGT */
129 #define DPAA_SGT_SIZE 256
131 /* Values for the L3R field of the FM Parse Results
133 /* L3 Type field: First IP Present IPv4 */
134 #define FM_L3_PARSE_RESULT_IPV4 0x8000
135 /* L3 Type field: First IP Present IPv6 */
136 #define FM_L3_PARSE_RESULT_IPV6 0x4000
137 /* Values for the L4R field of the FM Parse Results */
138 /* L4 Type field: UDP */
139 #define FM_L4_PARSE_RESULT_UDP 0x40
140 /* L4 Type field: TCP */
141 #define FM_L4_PARSE_RESULT_TCP 0x20
143 /* FD status field indicating whether the FM Parser has attempted to validate
144 * the L4 csum of the frame.
145 * Note that having this bit set doesn't necessarily imply that the checksum
146 * is valid. One would have to check the parse results to find that out.
148 #define FM_FD_STAT_L4CV 0x00000004
150 #define DPAA_SGT_MAX_ENTRIES 16 /* maximum number of entries in SG Table */
151 #define DPAA_BUFF_RELEASE_MAX 8 /* maximum number of buffers released at once */
153 #define FSL_DPAA_BPID_INV 0xff
154 #define FSL_DPAA_ETH_MAX_BUF_COUNT 128
155 #define FSL_DPAA_ETH_REFILL_THRESHOLD 80
157 #define DPAA_TX_PRIV_DATA_SIZE 16
158 #define DPAA_PARSE_RESULTS_SIZE sizeof(struct fman_prs_result)
159 #define DPAA_TIME_STAMP_SIZE 8
160 #define DPAA_HASH_RESULTS_SIZE 8
161 #define DPAA_RX_PRIV_DATA_SIZE (u16)(DPAA_TX_PRIV_DATA_SIZE + \
162 dpaa_rx_extra_headroom)
164 #define DPAA_ETH_PCD_RXQ_NUM 128
166 #define DPAA_ENQUEUE_RETRIES 100000
168 enum port_type {RX, TX};
171 struct dpaa_fq *tx_defq;
172 struct dpaa_fq *tx_errq;
173 struct dpaa_fq *rx_defq;
174 struct dpaa_fq *rx_errq;
175 struct dpaa_fq *rx_pcdq;
178 /* All the dpa bps in use at any moment */
179 static struct dpaa_bp *dpaa_bp_array[BM_MAX_NUM_OF_POOLS];
181 #define DPAA_BP_RAW_SIZE 4096
183 #define dpaa_bp_size(raw_size) SKB_WITH_OVERHEAD(raw_size)
185 static int dpaa_max_frm;
187 static int dpaa_rx_extra_headroom;
189 #define dpaa_get_max_mtu() \
190 (dpaa_max_frm - (VLAN_ETH_HLEN + ETH_FCS_LEN))
192 static int dpaa_netdev_init(struct net_device *net_dev,
193 const struct net_device_ops *dpaa_ops,
196 struct dpaa_priv *priv = netdev_priv(net_dev);
197 struct device *dev = net_dev->dev.parent;
198 struct dpaa_percpu_priv *percpu_priv;
202 /* Although we access another CPU's private data here
203 * we do it at initialization so it is safe
205 for_each_possible_cpu(i) {
206 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
207 percpu_priv->net_dev = net_dev;
210 net_dev->netdev_ops = dpaa_ops;
211 mac_addr = priv->mac_dev->addr;
213 net_dev->mem_start = priv->mac_dev->res->start;
214 net_dev->mem_end = priv->mac_dev->res->end;
216 net_dev->min_mtu = ETH_MIN_MTU;
217 net_dev->max_mtu = dpaa_get_max_mtu();
219 net_dev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
220 NETIF_F_LLTX | NETIF_F_RXHASH);
222 net_dev->hw_features |= NETIF_F_SG | NETIF_F_HIGHDMA;
223 /* The kernels enables GSO automatically, if we declare NETIF_F_SG.
224 * For conformity, we'll still declare GSO explicitly.
226 net_dev->features |= NETIF_F_GSO;
227 net_dev->features |= NETIF_F_RXCSUM;
229 net_dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
230 /* we do not want shared skbs on TX */
231 net_dev->priv_flags &= ~IFF_TX_SKB_SHARING;
233 net_dev->features |= net_dev->hw_features;
234 net_dev->vlan_features = net_dev->features;
236 memcpy(net_dev->perm_addr, mac_addr, net_dev->addr_len);
237 memcpy(net_dev->dev_addr, mac_addr, net_dev->addr_len);
239 net_dev->ethtool_ops = &dpaa_ethtool_ops;
241 net_dev->needed_headroom = priv->tx_headroom;
242 net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout);
244 /* start without the RUNNING flag, phylib controls it later */
245 netif_carrier_off(net_dev);
247 err = register_netdev(net_dev);
249 dev_err(dev, "register_netdev() = %d\n", err);
256 static int dpaa_stop(struct net_device *net_dev)
258 struct mac_device *mac_dev;
259 struct dpaa_priv *priv;
262 priv = netdev_priv(net_dev);
263 mac_dev = priv->mac_dev;
265 netif_tx_stop_all_queues(net_dev);
266 /* Allow the Fman (Tx) port to process in-flight frames before we
267 * try switching it off.
271 err = mac_dev->stop(mac_dev);
273 netif_err(priv, ifdown, net_dev, "mac_dev->stop() = %d\n",
276 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
277 error = fman_port_disable(mac_dev->port[i]);
283 phy_disconnect(net_dev->phydev);
284 net_dev->phydev = NULL;
291 static void dpaa_tx_timeout(struct net_device *net_dev)
293 struct dpaa_percpu_priv *percpu_priv;
294 const struct dpaa_priv *priv;
296 priv = netdev_priv(net_dev);
297 percpu_priv = this_cpu_ptr(priv->percpu_priv);
299 netif_crit(priv, timer, net_dev, "Transmit timeout latency: %u ms\n",
300 jiffies_to_msecs(jiffies - dev_trans_start(net_dev)));
302 percpu_priv->stats.tx_errors++;
305 /* Calculates the statistics for the given device by adding the statistics
306 * collected by each CPU.
308 static void dpaa_get_stats64(struct net_device *net_dev,
309 struct rtnl_link_stats64 *s)
311 int numstats = sizeof(struct rtnl_link_stats64) / sizeof(u64);
312 struct dpaa_priv *priv = netdev_priv(net_dev);
313 struct dpaa_percpu_priv *percpu_priv;
314 u64 *netstats = (u64 *)s;
318 for_each_possible_cpu(i) {
319 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
321 cpustats = (u64 *)&percpu_priv->stats;
323 /* add stats from all CPUs */
324 for (j = 0; j < numstats; j++)
325 netstats[j] += cpustats[j];
329 static int dpaa_setup_tc(struct net_device *net_dev, enum tc_setup_type type,
332 struct dpaa_priv *priv = netdev_priv(net_dev);
333 struct tc_mqprio_qopt *mqprio = type_data;
337 if (type != TC_SETUP_QDISC_MQPRIO)
340 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
341 num_tc = mqprio->num_tc;
343 if (num_tc == priv->num_tc)
347 netdev_reset_tc(net_dev);
351 if (num_tc > DPAA_TC_NUM) {
352 netdev_err(net_dev, "Too many traffic classes: max %d supported.\n",
357 netdev_set_num_tc(net_dev, num_tc);
359 for (i = 0; i < num_tc; i++)
360 netdev_set_tc_queue(net_dev, i, DPAA_TC_TXQ_NUM,
361 i * DPAA_TC_TXQ_NUM);
364 priv->num_tc = num_tc ? : 1;
365 netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM);
369 static struct mac_device *dpaa_mac_dev_get(struct platform_device *pdev)
371 struct dpaa_eth_data *eth_data;
372 struct device *dpaa_dev;
373 struct mac_device *mac_dev;
375 dpaa_dev = &pdev->dev;
376 eth_data = dpaa_dev->platform_data;
378 dev_err(dpaa_dev, "eth_data missing\n");
379 return ERR_PTR(-ENODEV);
381 mac_dev = eth_data->mac_dev;
383 dev_err(dpaa_dev, "mac_dev missing\n");
384 return ERR_PTR(-EINVAL);
390 static int dpaa_set_mac_address(struct net_device *net_dev, void *addr)
392 const struct dpaa_priv *priv;
393 struct mac_device *mac_dev;
394 struct sockaddr old_addr;
397 priv = netdev_priv(net_dev);
399 memcpy(old_addr.sa_data, net_dev->dev_addr, ETH_ALEN);
401 err = eth_mac_addr(net_dev, addr);
403 netif_err(priv, drv, net_dev, "eth_mac_addr() = %d\n", err);
407 mac_dev = priv->mac_dev;
409 err = mac_dev->change_addr(mac_dev->fman_mac,
410 (enet_addr_t *)net_dev->dev_addr);
412 netif_err(priv, drv, net_dev, "mac_dev->change_addr() = %d\n",
414 /* reverting to previous address */
415 eth_mac_addr(net_dev, &old_addr);
423 static void dpaa_set_rx_mode(struct net_device *net_dev)
425 const struct dpaa_priv *priv;
428 priv = netdev_priv(net_dev);
430 if (!!(net_dev->flags & IFF_PROMISC) != priv->mac_dev->promisc) {
431 priv->mac_dev->promisc = !priv->mac_dev->promisc;
432 err = priv->mac_dev->set_promisc(priv->mac_dev->fman_mac,
433 priv->mac_dev->promisc);
435 netif_err(priv, drv, net_dev,
436 "mac_dev->set_promisc() = %d\n",
440 if (!!(net_dev->flags & IFF_ALLMULTI) != priv->mac_dev->allmulti) {
441 priv->mac_dev->allmulti = !priv->mac_dev->allmulti;
442 err = priv->mac_dev->set_allmulti(priv->mac_dev->fman_mac,
443 priv->mac_dev->allmulti);
445 netif_err(priv, drv, net_dev,
446 "mac_dev->set_allmulti() = %d\n",
450 err = priv->mac_dev->set_multi(net_dev, priv->mac_dev);
452 netif_err(priv, drv, net_dev, "mac_dev->set_multi() = %d\n",
456 static struct dpaa_bp *dpaa_bpid2pool(int bpid)
458 if (WARN_ON(bpid < 0 || bpid >= BM_MAX_NUM_OF_POOLS))
461 return dpaa_bp_array[bpid];
464 /* checks if this bpool is already allocated */
465 static bool dpaa_bpid2pool_use(int bpid)
467 if (dpaa_bpid2pool(bpid)) {
468 refcount_inc(&dpaa_bp_array[bpid]->refs);
475 /* called only once per bpid by dpaa_bp_alloc_pool() */
476 static void dpaa_bpid2pool_map(int bpid, struct dpaa_bp *dpaa_bp)
478 dpaa_bp_array[bpid] = dpaa_bp;
479 refcount_set(&dpaa_bp->refs, 1);
482 static int dpaa_bp_alloc_pool(struct dpaa_bp *dpaa_bp)
486 if (dpaa_bp->size == 0 || dpaa_bp->config_count == 0) {
487 pr_err("%s: Buffer pool is not properly initialized! Missing size or initial number of buffers\n",
492 /* If the pool is already specified, we only create one per bpid */
493 if (dpaa_bp->bpid != FSL_DPAA_BPID_INV &&
494 dpaa_bpid2pool_use(dpaa_bp->bpid))
497 if (dpaa_bp->bpid == FSL_DPAA_BPID_INV) {
498 dpaa_bp->pool = bman_new_pool();
499 if (!dpaa_bp->pool) {
500 pr_err("%s: bman_new_pool() failed\n",
505 dpaa_bp->bpid = (u8)bman_get_bpid(dpaa_bp->pool);
508 if (dpaa_bp->seed_cb) {
509 err = dpaa_bp->seed_cb(dpaa_bp);
511 goto pool_seed_failed;
514 dpaa_bpid2pool_map(dpaa_bp->bpid, dpaa_bp);
519 pr_err("%s: pool seeding failed\n", __func__);
520 bman_free_pool(dpaa_bp->pool);
525 /* remove and free all the buffers from the given buffer pool */
526 static void dpaa_bp_drain(struct dpaa_bp *bp)
532 struct bm_buffer bmb[8];
535 ret = bman_acquire(bp->pool, bmb, num);
538 /* we have less than 8 buffers left;
539 * drain them one by one
545 /* Pool is fully drained */
551 for (i = 0; i < num; i++)
552 bp->free_buf_cb(bp, &bmb[i]);
556 static void dpaa_bp_free(struct dpaa_bp *dpaa_bp)
558 struct dpaa_bp *bp = dpaa_bpid2pool(dpaa_bp->bpid);
560 /* the mapping between bpid and dpaa_bp is done very late in the
561 * allocation procedure; if something failed before the mapping, the bp
562 * was not configured, therefore we don't need the below instructions
567 if (!refcount_dec_and_test(&bp->refs))
573 dpaa_bp_array[bp->bpid] = NULL;
574 bman_free_pool(bp->pool);
577 static void dpaa_bps_free(struct dpaa_priv *priv)
579 dpaa_bp_free(priv->dpaa_bp);
582 /* Use multiple WQs for FQ assignment:
583 * - Tx Confirmation queues go to WQ1.
584 * - Rx Error and Tx Error queues go to WQ5 (giving them a better chance
585 * to be scheduled, in case there are many more FQs in WQ6).
586 * - Rx Default goes to WQ6.
587 * - Tx queues go to different WQs depending on their priority. Equal
588 * chunks of NR_CPUS queues go to WQ6 (lowest priority), WQ2, WQ1 and
589 * WQ0 (highest priority).
590 * This ensures that Tx-confirmed buffers are timely released. In particular,
591 * it avoids congestion on the Tx Confirm FQs, which can pile up PFDRs if they
592 * are greatly outnumbered by other FQs in the system, while
593 * dequeue scheduling is round-robin.
595 static inline void dpaa_assign_wq(struct dpaa_fq *fq, int idx)
597 switch (fq->fq_type) {
598 case FQ_TYPE_TX_CONFIRM:
599 case FQ_TYPE_TX_CONF_MQ:
602 case FQ_TYPE_RX_ERROR:
603 case FQ_TYPE_TX_ERROR:
606 case FQ_TYPE_RX_DEFAULT:
611 switch (idx / DPAA_TC_TXQ_NUM) {
613 /* Low priority (best effort) */
617 /* Medium priority */
625 /* Very high priority */
629 WARN(1, "Too many TX FQs: more than %d!\n",
634 WARN(1, "Invalid FQ type %d for FQID %d!\n",
635 fq->fq_type, fq->fqid);
639 static struct dpaa_fq *dpaa_fq_alloc(struct device *dev,
640 u32 start, u32 count,
641 struct list_head *list,
642 enum dpaa_fq_type fq_type)
644 struct dpaa_fq *dpaa_fq;
647 dpaa_fq = devm_kcalloc(dev, count, sizeof(*dpaa_fq),
652 for (i = 0; i < count; i++) {
653 dpaa_fq[i].fq_type = fq_type;
654 dpaa_fq[i].fqid = start ? start + i : 0;
655 list_add_tail(&dpaa_fq[i].list, list);
658 for (i = 0; i < count; i++)
659 dpaa_assign_wq(dpaa_fq + i, i);
664 static int dpaa_alloc_all_fqs(struct device *dev, struct list_head *list,
665 struct fm_port_fqs *port_fqs)
667 struct dpaa_fq *dpaa_fq;
668 u32 fq_base, fq_base_aligned, i;
670 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_ERROR);
672 goto fq_alloc_failed;
674 port_fqs->rx_errq = &dpaa_fq[0];
676 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_RX_DEFAULT);
678 goto fq_alloc_failed;
680 port_fqs->rx_defq = &dpaa_fq[0];
682 /* the PCD FQIDs range needs to be aligned for correct operation */
683 if (qman_alloc_fqid_range(&fq_base, 2 * DPAA_ETH_PCD_RXQ_NUM))
684 goto fq_alloc_failed;
686 fq_base_aligned = ALIGN(fq_base, DPAA_ETH_PCD_RXQ_NUM);
688 for (i = fq_base; i < fq_base_aligned; i++)
689 qman_release_fqid(i);
691 for (i = fq_base_aligned + DPAA_ETH_PCD_RXQ_NUM;
692 i < (fq_base + 2 * DPAA_ETH_PCD_RXQ_NUM); i++)
693 qman_release_fqid(i);
695 dpaa_fq = dpaa_fq_alloc(dev, fq_base_aligned, DPAA_ETH_PCD_RXQ_NUM,
696 list, FQ_TYPE_RX_PCD);
698 goto fq_alloc_failed;
700 port_fqs->rx_pcdq = &dpaa_fq[0];
702 if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX_CONF_MQ))
703 goto fq_alloc_failed;
705 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_ERROR);
707 goto fq_alloc_failed;
709 port_fqs->tx_errq = &dpaa_fq[0];
711 dpaa_fq = dpaa_fq_alloc(dev, 0, 1, list, FQ_TYPE_TX_CONFIRM);
713 goto fq_alloc_failed;
715 port_fqs->tx_defq = &dpaa_fq[0];
717 if (!dpaa_fq_alloc(dev, 0, DPAA_ETH_TXQ_NUM, list, FQ_TYPE_TX))
718 goto fq_alloc_failed;
723 dev_err(dev, "dpaa_fq_alloc() failed\n");
727 static u32 rx_pool_channel;
728 static DEFINE_SPINLOCK(rx_pool_channel_init);
730 static int dpaa_get_channel(void)
732 spin_lock(&rx_pool_channel_init);
733 if (!rx_pool_channel) {
737 ret = qman_alloc_pool(&pool);
740 rx_pool_channel = pool;
742 spin_unlock(&rx_pool_channel_init);
743 if (!rx_pool_channel)
745 return rx_pool_channel;
748 static void dpaa_release_channel(void)
750 qman_release_pool(rx_pool_channel);
753 static void dpaa_eth_add_channel(u16 channel)
755 u32 pool = QM_SDQCR_CHANNELS_POOL_CONV(channel);
756 const cpumask_t *cpus = qman_affine_cpus();
757 struct qman_portal *portal;
760 for_each_cpu_and(cpu, cpus, cpu_online_mask) {
761 portal = qman_get_affine_portal(cpu);
762 qman_p_static_dequeue_add(portal, pool);
766 /* Congestion group state change notification callback.
767 * Stops the device's egress queues while they are congested and
768 * wakes them upon exiting congested state.
769 * Also updates some CGR-related stats.
771 static void dpaa_eth_cgscn(struct qman_portal *qm, struct qman_cgr *cgr,
774 struct dpaa_priv *priv = (struct dpaa_priv *)container_of(cgr,
775 struct dpaa_priv, cgr_data.cgr);
778 priv->cgr_data.congestion_start_jiffies = jiffies;
779 netif_tx_stop_all_queues(priv->net_dev);
780 priv->cgr_data.cgr_congested_count++;
782 priv->cgr_data.congested_jiffies +=
783 (jiffies - priv->cgr_data.congestion_start_jiffies);
784 netif_tx_wake_all_queues(priv->net_dev);
788 static int dpaa_eth_cgr_init(struct dpaa_priv *priv)
790 struct qm_mcc_initcgr initcgr;
794 err = qman_alloc_cgrid(&priv->cgr_data.cgr.cgrid);
796 if (netif_msg_drv(priv))
797 pr_err("%s: Error %d allocating CGR ID\n",
801 priv->cgr_data.cgr.cb = dpaa_eth_cgscn;
803 /* Enable Congestion State Change Notifications and CS taildrop */
804 memset(&initcgr, 0, sizeof(initcgr));
805 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CSCN_EN | QM_CGR_WE_CS_THRES);
806 initcgr.cgr.cscn_en = QM_CGR_EN;
808 /* Set different thresholds based on the MAC speed.
809 * This may turn suboptimal if the MAC is reconfigured at a speed
810 * lower than its max, e.g. if a dTSEC later negotiates a 100Mbps link.
811 * In such cases, we ought to reconfigure the threshold, too.
813 if (priv->mac_dev->if_support & SUPPORTED_10000baseT_Full)
814 cs_th = DPAA_CS_THRESHOLD_10G;
816 cs_th = DPAA_CS_THRESHOLD_1G;
817 qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
819 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN);
820 initcgr.cgr.cstd_en = QM_CGR_EN;
822 err = qman_create_cgr(&priv->cgr_data.cgr, QMAN_CGR_FLAG_USE_INIT,
825 if (netif_msg_drv(priv))
826 pr_err("%s: Error %d creating CGR with ID %d\n",
827 __func__, err, priv->cgr_data.cgr.cgrid);
828 qman_release_cgrid(priv->cgr_data.cgr.cgrid);
831 if (netif_msg_drv(priv))
832 pr_debug("Created CGR %d for netdev with hwaddr %pM on QMan channel %d\n",
833 priv->cgr_data.cgr.cgrid, priv->mac_dev->addr,
834 priv->cgr_data.cgr.chan);
840 static inline void dpaa_setup_ingress(const struct dpaa_priv *priv,
842 const struct qman_fq *template)
844 fq->fq_base = *template;
845 fq->net_dev = priv->net_dev;
847 fq->flags = QMAN_FQ_FLAG_NO_ENQUEUE;
848 fq->channel = priv->channel;
851 static inline void dpaa_setup_egress(const struct dpaa_priv *priv,
853 struct fman_port *port,
854 const struct qman_fq *template)
856 fq->fq_base = *template;
857 fq->net_dev = priv->net_dev;
860 fq->flags = QMAN_FQ_FLAG_TO_DCPORTAL;
861 fq->channel = (u16)fman_port_get_qman_channel_id(port);
863 fq->flags = QMAN_FQ_FLAG_NO_MODIFY;
867 static void dpaa_fq_setup(struct dpaa_priv *priv,
868 const struct dpaa_fq_cbs *fq_cbs,
869 struct fman_port *tx_port)
871 int egress_cnt = 0, conf_cnt = 0, num_portals = 0, portal_cnt = 0, cpu;
872 const cpumask_t *affine_cpus = qman_affine_cpus();
873 u16 channels[NR_CPUS];
876 for_each_cpu_and(cpu, affine_cpus, cpu_online_mask)
877 channels[num_portals++] = qman_affine_channel(cpu);
879 if (num_portals == 0)
880 dev_err(priv->net_dev->dev.parent,
881 "No Qman software (affine) channels found\n");
883 /* Initialize each FQ in the list */
884 list_for_each_entry(fq, &priv->dpaa_fq_list, list) {
885 switch (fq->fq_type) {
886 case FQ_TYPE_RX_DEFAULT:
887 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
889 case FQ_TYPE_RX_ERROR:
890 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_errq);
895 dpaa_setup_ingress(priv, fq, &fq_cbs->rx_defq);
896 fq->channel = channels[portal_cnt++ % num_portals];
899 dpaa_setup_egress(priv, fq, tx_port,
900 &fq_cbs->egress_ern);
901 /* If we have more Tx queues than the number of cores,
902 * just ignore the extra ones.
904 if (egress_cnt < DPAA_ETH_TXQ_NUM)
905 priv->egress_fqs[egress_cnt++] = &fq->fq_base;
907 case FQ_TYPE_TX_CONF_MQ:
908 priv->conf_fqs[conf_cnt++] = &fq->fq_base;
910 case FQ_TYPE_TX_CONFIRM:
911 dpaa_setup_ingress(priv, fq, &fq_cbs->tx_defq);
913 case FQ_TYPE_TX_ERROR:
914 dpaa_setup_ingress(priv, fq, &fq_cbs->tx_errq);
917 dev_warn(priv->net_dev->dev.parent,
918 "Unknown FQ type detected!\n");
923 /* Make sure all CPUs receive a corresponding Tx queue. */
924 while (egress_cnt < DPAA_ETH_TXQ_NUM) {
925 list_for_each_entry(fq, &priv->dpaa_fq_list, list) {
926 if (fq->fq_type != FQ_TYPE_TX)
928 priv->egress_fqs[egress_cnt++] = &fq->fq_base;
929 if (egress_cnt == DPAA_ETH_TXQ_NUM)
935 static inline int dpaa_tx_fq_to_id(const struct dpaa_priv *priv,
936 struct qman_fq *tx_fq)
940 for (i = 0; i < DPAA_ETH_TXQ_NUM; i++)
941 if (priv->egress_fqs[i] == tx_fq)
947 static int dpaa_fq_init(struct dpaa_fq *dpaa_fq, bool td_enable)
949 const struct dpaa_priv *priv;
950 struct qman_fq *confq = NULL;
951 struct qm_mcc_initfq initfq;
957 priv = netdev_priv(dpaa_fq->net_dev);
958 dev = dpaa_fq->net_dev->dev.parent;
960 if (dpaa_fq->fqid == 0)
961 dpaa_fq->flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
963 dpaa_fq->init = !(dpaa_fq->flags & QMAN_FQ_FLAG_NO_MODIFY);
965 err = qman_create_fq(dpaa_fq->fqid, dpaa_fq->flags, &dpaa_fq->fq_base);
967 dev_err(dev, "qman_create_fq() failed\n");
970 fq = &dpaa_fq->fq_base;
973 memset(&initfq, 0, sizeof(initfq));
975 initfq.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL);
976 /* Note: we may get to keep an empty FQ in cache */
977 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_PREFERINCACHE);
979 /* Try to reduce the number of portal interrupts for
980 * Tx Confirmation FQs.
982 if (dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM)
983 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_AVOIDBLOCK);
986 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_DESTWQ);
988 qm_fqd_set_destwq(&initfq.fqd, dpaa_fq->channel, dpaa_fq->wq);
990 /* Put all egress queues in a congestion group of their own.
991 * Sensu stricto, the Tx confirmation queues are Rx FQs,
992 * rather than Tx - but they nonetheless account for the
993 * memory footprint on behalf of egress traffic. We therefore
994 * place them in the netdev's CGR, along with the Tx FQs.
996 if (dpaa_fq->fq_type == FQ_TYPE_TX ||
997 dpaa_fq->fq_type == FQ_TYPE_TX_CONFIRM ||
998 dpaa_fq->fq_type == FQ_TYPE_TX_CONF_MQ) {
999 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID);
1000 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE);
1001 initfq.fqd.cgid = (u8)priv->cgr_data.cgr.cgrid;
1002 /* Set a fixed overhead accounting, in an attempt to
1003 * reduce the impact of fixed-size skb shells and the
1004 * driver's needed headroom on system memory. This is
1005 * especially the case when the egress traffic is
1006 * composed of small datagrams.
1007 * Unfortunately, QMan's OAL value is capped to an
1008 * insufficient value, but even that is better than
1009 * no overhead accounting at all.
1011 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC);
1012 qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
1013 qm_fqd_set_oal(&initfq.fqd,
1014 min(sizeof(struct sk_buff) +
1016 (size_t)FSL_QMAN_MAX_OAL));
1020 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_TDTHRESH);
1021 qm_fqd_set_taildrop(&initfq.fqd, DPAA_FQ_TD, 1);
1022 initfq.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_TDE);
1025 if (dpaa_fq->fq_type == FQ_TYPE_TX) {
1026 queue_id = dpaa_tx_fq_to_id(priv, &dpaa_fq->fq_base);
1028 confq = priv->conf_fqs[queue_id];
1031 cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1032 /* ContextA: OVOM=1(use contextA2 bits instead of ICAD)
1033 * A2V=1 (contextA A2 field is valid)
1034 * A0V=1 (contextA A0 field is valid)
1035 * B0V=1 (contextB field is valid)
1036 * ContextA A2: EBD=1 (deallocate buffers inside FMan)
1037 * ContextB B0(ASPID): 0 (absolute Virtual Storage ID)
1039 qm_fqd_context_a_set64(&initfq.fqd,
1040 0x1e00000080000000ULL);
1044 /* Put all the ingress queues in our "ingress CGR". */
1045 if (priv->use_ingress_cgr &&
1046 (dpaa_fq->fq_type == FQ_TYPE_RX_DEFAULT ||
1047 dpaa_fq->fq_type == FQ_TYPE_RX_ERROR ||
1048 dpaa_fq->fq_type == FQ_TYPE_RX_PCD)) {
1049 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CGID);
1050 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_CGE);
1051 initfq.fqd.cgid = (u8)priv->ingress_cgr.cgrid;
1052 /* Set a fixed overhead accounting, just like for the
1055 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_OAC);
1056 qm_fqd_set_oac(&initfq.fqd, QM_OAC_CG);
1057 qm_fqd_set_oal(&initfq.fqd,
1058 min(sizeof(struct sk_buff) +
1060 (size_t)FSL_QMAN_MAX_OAL));
1063 /* Initialization common to all ingress queues */
1064 if (dpaa_fq->flags & QMAN_FQ_FLAG_NO_ENQUEUE) {
1065 initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
1066 initfq.fqd.fq_ctrl |= cpu_to_be16(QM_FQCTRL_HOLDACTIVE |
1067 QM_FQCTRL_CTXASTASHING);
1068 initfq.fqd.context_a.stashing.exclusive =
1069 QM_STASHING_EXCL_DATA | QM_STASHING_EXCL_CTX |
1070 QM_STASHING_EXCL_ANNOTATION;
1071 qm_fqd_set_stashing(&initfq.fqd, 1, 2,
1072 DIV_ROUND_UP(sizeof(struct qman_fq),
1076 err = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &initfq);
1078 dev_err(dev, "qman_init_fq(%u) = %d\n",
1079 qman_fq_fqid(fq), err);
1080 qman_destroy_fq(fq);
1085 dpaa_fq->fqid = qman_fq_fqid(fq);
1090 static int dpaa_fq_free_entry(struct device *dev, struct qman_fq *fq)
1092 const struct dpaa_priv *priv;
1093 struct dpaa_fq *dpaa_fq;
1098 dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
1099 priv = netdev_priv(dpaa_fq->net_dev);
1101 if (dpaa_fq->init) {
1102 err = qman_retire_fq(fq, NULL);
1103 if (err < 0 && netif_msg_drv(priv))
1104 dev_err(dev, "qman_retire_fq(%u) = %d\n",
1105 qman_fq_fqid(fq), err);
1107 error = qman_oos_fq(fq);
1108 if (error < 0 && netif_msg_drv(priv)) {
1109 dev_err(dev, "qman_oos_fq(%u) = %d\n",
1110 qman_fq_fqid(fq), error);
1116 qman_destroy_fq(fq);
1117 list_del(&dpaa_fq->list);
1122 static int dpaa_fq_free(struct device *dev, struct list_head *list)
1124 struct dpaa_fq *dpaa_fq, *tmp;
1128 list_for_each_entry_safe(dpaa_fq, tmp, list, list) {
1129 error = dpaa_fq_free_entry(dev, (struct qman_fq *)dpaa_fq);
1130 if (error < 0 && err >= 0)
1137 static int dpaa_eth_init_tx_port(struct fman_port *port, struct dpaa_fq *errq,
1138 struct dpaa_fq *defq,
1139 struct dpaa_buffer_layout *buf_layout)
1141 struct fman_buffer_prefix_content buf_prefix_content;
1142 struct fman_port_params params;
1145 memset(¶ms, 0, sizeof(params));
1146 memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
1148 buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
1149 buf_prefix_content.pass_prs_result = true;
1150 buf_prefix_content.pass_hash_result = true;
1151 buf_prefix_content.pass_time_stamp = true;
1152 buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT;
1154 params.specific_params.non_rx_params.err_fqid = errq->fqid;
1155 params.specific_params.non_rx_params.dflt_fqid = defq->fqid;
1157 err = fman_port_config(port, ¶ms);
1159 pr_err("%s: fman_port_config failed\n", __func__);
1163 err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
1165 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
1170 err = fman_port_init(port);
1172 pr_err("%s: fm_port_init failed\n", __func__);
1177 static int dpaa_eth_init_rx_port(struct fman_port *port, struct dpaa_bp *bp,
1178 struct dpaa_fq *errq,
1179 struct dpaa_fq *defq, struct dpaa_fq *pcdq,
1180 struct dpaa_buffer_layout *buf_layout)
1182 struct fman_buffer_prefix_content buf_prefix_content;
1183 struct fman_port_rx_params *rx_p;
1184 struct fman_port_params params;
1187 memset(¶ms, 0, sizeof(params));
1188 memset(&buf_prefix_content, 0, sizeof(buf_prefix_content));
1190 buf_prefix_content.priv_data_size = buf_layout->priv_data_size;
1191 buf_prefix_content.pass_prs_result = true;
1192 buf_prefix_content.pass_hash_result = true;
1193 buf_prefix_content.pass_time_stamp = true;
1194 buf_prefix_content.data_align = DPAA_FD_DATA_ALIGNMENT;
1196 rx_p = ¶ms.specific_params.rx_params;
1197 rx_p->err_fqid = errq->fqid;
1198 rx_p->dflt_fqid = defq->fqid;
1200 rx_p->pcd_base_fqid = pcdq->fqid;
1201 rx_p->pcd_fqs_count = DPAA_ETH_PCD_RXQ_NUM;
1204 rx_p->ext_buf_pools.num_of_pools_used = 1;
1205 rx_p->ext_buf_pools.ext_buf_pool[0].id = bp->bpid;
1206 rx_p->ext_buf_pools.ext_buf_pool[0].size = (u16)bp->size;
1208 err = fman_port_config(port, ¶ms);
1210 pr_err("%s: fman_port_config failed\n", __func__);
1214 err = fman_port_cfg_buf_prefix_content(port, &buf_prefix_content);
1216 pr_err("%s: fman_port_cfg_buf_prefix_content failed\n",
1221 err = fman_port_init(port);
1223 pr_err("%s: fm_port_init failed\n", __func__);
1228 static int dpaa_eth_init_ports(struct mac_device *mac_dev,
1230 struct fm_port_fqs *port_fqs,
1231 struct dpaa_buffer_layout *buf_layout,
1234 struct fman_port *rxport = mac_dev->port[RX];
1235 struct fman_port *txport = mac_dev->port[TX];
1238 err = dpaa_eth_init_tx_port(txport, port_fqs->tx_errq,
1239 port_fqs->tx_defq, &buf_layout[TX]);
1243 err = dpaa_eth_init_rx_port(rxport, bp, port_fqs->rx_errq,
1244 port_fqs->rx_defq, port_fqs->rx_pcdq,
1250 static int dpaa_bman_release(const struct dpaa_bp *dpaa_bp,
1251 struct bm_buffer *bmb, int cnt)
1255 err = bman_release(dpaa_bp->pool, bmb, cnt);
1256 /* Should never occur, address anyway to avoid leaking the buffers */
1257 if (WARN_ON(err) && dpaa_bp->free_buf_cb)
1259 dpaa_bp->free_buf_cb(dpaa_bp, &bmb[cnt]);
1264 static void dpaa_release_sgt_members(struct qm_sg_entry *sgt)
1266 struct bm_buffer bmb[DPAA_BUFF_RELEASE_MAX];
1267 struct dpaa_bp *dpaa_bp;
1270 memset(bmb, 0, sizeof(bmb));
1273 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1279 WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1281 bm_buffer_set64(&bmb[j], qm_sg_entry_get64(&sgt[i]));
1284 } while (j < ARRAY_SIZE(bmb) &&
1285 !qm_sg_entry_is_final(&sgt[i - 1]) &&
1286 sgt[i - 1].bpid == sgt[i].bpid);
1288 dpaa_bman_release(dpaa_bp, bmb, j);
1289 } while (!qm_sg_entry_is_final(&sgt[i - 1]));
1292 static void dpaa_fd_release(const struct net_device *net_dev,
1293 const struct qm_fd *fd)
1295 struct qm_sg_entry *sgt;
1296 struct dpaa_bp *dpaa_bp;
1297 struct bm_buffer bmb;
1302 bm_buffer_set64(&bmb, qm_fd_addr(fd));
1304 dpaa_bp = dpaa_bpid2pool(fd->bpid);
1308 if (qm_fd_get_format(fd) == qm_fd_sg) {
1309 vaddr = phys_to_virt(qm_fd_addr(fd));
1310 sgt = vaddr + qm_fd_get_offset(fd);
1312 dma_unmap_page(dpaa_bp->priv->rx_dma_dev, qm_fd_addr(fd),
1313 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);
1315 dpaa_release_sgt_members(sgt);
1317 addr = dma_map_page(dpaa_bp->priv->rx_dma_dev,
1318 virt_to_page(vaddr), 0, DPAA_BP_RAW_SIZE,
1320 if (dma_mapping_error(dpaa_bp->priv->rx_dma_dev, addr)) {
1321 netdev_err(net_dev, "DMA mapping failed\n");
1324 bm_buffer_set64(&bmb, addr);
1327 dpaa_bman_release(dpaa_bp, &bmb, 1);
1330 static void count_ern(struct dpaa_percpu_priv *percpu_priv,
1331 const union qm_mr_entry *msg)
1333 switch (msg->ern.rc & QM_MR_RC_MASK) {
1334 case QM_MR_RC_CGR_TAILDROP:
1335 percpu_priv->ern_cnt.cg_tdrop++;
1338 percpu_priv->ern_cnt.wred++;
1340 case QM_MR_RC_ERROR:
1341 percpu_priv->ern_cnt.err_cond++;
1343 case QM_MR_RC_ORPWINDOW_EARLY:
1344 percpu_priv->ern_cnt.early_window++;
1346 case QM_MR_RC_ORPWINDOW_LATE:
1347 percpu_priv->ern_cnt.late_window++;
1349 case QM_MR_RC_FQ_TAILDROP:
1350 percpu_priv->ern_cnt.fq_tdrop++;
1352 case QM_MR_RC_ORPWINDOW_RETIRED:
1353 percpu_priv->ern_cnt.fq_retired++;
1355 case QM_MR_RC_ORP_ZERO:
1356 percpu_priv->ern_cnt.orp_zero++;
1361 /* Turn on HW checksum computation for this outgoing frame.
1362 * If the current protocol is not something we support in this regard
1363 * (or if the stack has already computed the SW checksum), we do nothing.
1365 * Returns 0 if all goes well (or HW csum doesn't apply), and a negative value
1368 * Note that this function may modify the fd->cmd field and the skb data buffer
1369 * (the Parse Results area).
1371 static int dpaa_enable_tx_csum(struct dpaa_priv *priv,
1372 struct sk_buff *skb,
1374 void *parse_results)
1376 struct fman_prs_result *parse_result;
1377 u16 ethertype = ntohs(skb->protocol);
1378 struct ipv6hdr *ipv6h = NULL;
1383 if (skb->ip_summed != CHECKSUM_PARTIAL)
1386 /* Note: L3 csum seems to be already computed in sw, but we can't choose
1387 * L4 alone from the FM configuration anyway.
1390 /* Fill in some fields of the Parse Results array, so the FMan
1391 * can find them as if they came from the FMan Parser.
1393 parse_result = (struct fman_prs_result *)parse_results;
1395 /* If we're dealing with VLAN, get the real Ethernet type */
1396 if (ethertype == ETH_P_8021Q) {
1397 /* We can't always assume the MAC header is set correctly
1398 * by the stack, so reset to beginning of skb->data
1400 skb_reset_mac_header(skb);
1401 ethertype = ntohs(vlan_eth_hdr(skb)->h_vlan_encapsulated_proto);
1404 /* Fill in the relevant L3 parse result fields
1405 * and read the L4 protocol type
1407 switch (ethertype) {
1409 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV4);
1412 l4_proto = iph->protocol;
1415 parse_result->l3r = cpu_to_be16(FM_L3_PARSE_RESULT_IPV6);
1416 ipv6h = ipv6_hdr(skb);
1418 l4_proto = ipv6h->nexthdr;
1421 /* We shouldn't even be here */
1422 if (net_ratelimit())
1423 netif_alert(priv, tx_err, priv->net_dev,
1424 "Can't compute HW csum for L3 proto 0x%x\n",
1425 ntohs(skb->protocol));
1430 /* Fill in the relevant L4 parse result fields */
1433 parse_result->l4r = FM_L4_PARSE_RESULT_UDP;
1436 parse_result->l4r = FM_L4_PARSE_RESULT_TCP;
1439 if (net_ratelimit())
1440 netif_alert(priv, tx_err, priv->net_dev,
1441 "Can't compute HW csum for L4 proto 0x%x\n",
1447 /* At index 0 is IPOffset_1 as defined in the Parse Results */
1448 parse_result->ip_off[0] = (u8)skb_network_offset(skb);
1449 parse_result->l4_off = (u8)skb_transport_offset(skb);
1451 /* Enable L3 (and L4, if TCP or UDP) HW checksum. */
1452 fd->cmd |= cpu_to_be32(FM_FD_CMD_RPD | FM_FD_CMD_DTC);
1454 /* On P1023 and similar platforms fd->cmd interpretation could
1455 * be disabled by setting CONTEXT_A bit ICMD; currently this bit
1456 * is not set so we do not need to check; in the future, if/when
1457 * using context_a we need to check this bit
1464 static int dpaa_bp_add_8_bufs(const struct dpaa_bp *dpaa_bp)
1466 struct net_device *net_dev = dpaa_bp->priv->net_dev;
1467 struct bm_buffer bmb[8];
1472 for (i = 0; i < 8; i++) {
1473 p = dev_alloc_pages(0);
1475 netdev_err(net_dev, "dev_alloc_pages() failed\n");
1476 goto release_previous_buffs;
1479 addr = dma_map_page(dpaa_bp->priv->rx_dma_dev, p, 0,
1480 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);
1481 if (unlikely(dma_mapping_error(dpaa_bp->priv->rx_dma_dev,
1483 netdev_err(net_dev, "DMA map failed\n");
1484 goto release_previous_buffs;
1488 bm_buffer_set64(&bmb[i], addr);
1492 return dpaa_bman_release(dpaa_bp, bmb, i);
1494 release_previous_buffs:
1495 WARN_ONCE(1, "dpaa_eth: failed to add buffers on Rx\n");
1497 bm_buffer_set64(&bmb[i], 0);
1498 /* Avoid releasing a completely null buffer; bman_release() requires
1499 * at least one buffer.
1507 static int dpaa_bp_seed(struct dpaa_bp *dpaa_bp)
1511 /* Give each CPU an allotment of "config_count" buffers */
1512 for_each_possible_cpu(i) {
1513 int *count_ptr = per_cpu_ptr(dpaa_bp->percpu_count, i);
1516 /* Although we access another CPU's counters here
1517 * we do it at boot time so it is safe
1519 for (j = 0; j < dpaa_bp->config_count; j += 8)
1520 *count_ptr += dpaa_bp_add_8_bufs(dpaa_bp);
1525 /* Add buffers/(pages) for Rx processing whenever bpool count falls below
1528 static int dpaa_eth_refill_bpool(struct dpaa_bp *dpaa_bp, int *countptr)
1530 int count = *countptr;
1533 if (unlikely(count < FSL_DPAA_ETH_REFILL_THRESHOLD)) {
1535 new_bufs = dpaa_bp_add_8_bufs(dpaa_bp);
1536 if (unlikely(!new_bufs)) {
1537 /* Avoid looping forever if we've temporarily
1538 * run out of memory. We'll try again at the
1544 } while (count < FSL_DPAA_ETH_MAX_BUF_COUNT);
1547 if (unlikely(count < FSL_DPAA_ETH_MAX_BUF_COUNT))
1554 static int dpaa_eth_refill_bpools(struct dpaa_priv *priv)
1556 struct dpaa_bp *dpaa_bp;
1560 dpaa_bp = priv->dpaa_bp;
1563 countptr = this_cpu_ptr(dpaa_bp->percpu_count);
1564 res = dpaa_eth_refill_bpool(dpaa_bp, countptr);
1571 /* Cleanup function for outgoing frame descriptors that were built on Tx path,
1572 * either contiguous frames or scatter/gather ones.
1573 * Skb freeing is not handled here.
1575 * This function may be called on error paths in the Tx function, so guard
1576 * against cases when not all fd relevant fields were filled in. To avoid
1577 * reading the invalid transmission timestamp for the error paths set ts to
1580 * Return the skb backpointer, since for S/G frames the buffer containing it
1583 static struct sk_buff *dpaa_cleanup_tx_fd(const struct dpaa_priv *priv,
1584 const struct qm_fd *fd, bool ts)
1586 const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
1587 struct device *dev = priv->net_dev->dev.parent;
1588 struct skb_shared_hwtstamps shhwtstamps;
1589 dma_addr_t addr = qm_fd_addr(fd);
1590 void *vaddr = phys_to_virt(addr);
1591 const struct qm_sg_entry *sgt;
1592 struct sk_buff *skb;
1596 if (unlikely(qm_fd_get_format(fd) == qm_fd_sg)) {
1597 dma_unmap_page(priv->tx_dma_dev, addr,
1598 qm_fd_get_offset(fd) + DPAA_SGT_SIZE,
1601 /* The sgt buffer has been allocated with netdev_alloc_frag(),
1604 sgt = vaddr + qm_fd_get_offset(fd);
1606 /* sgt[0] is from lowmem, was dma_map_single()-ed */
1607 dma_unmap_single(priv->tx_dma_dev, qm_sg_addr(&sgt[0]),
1608 qm_sg_entry_get_len(&sgt[0]), dma_dir);
1610 /* remaining pages were mapped with skb_frag_dma_map() */
1611 for (i = 1; (i < DPAA_SGT_MAX_ENTRIES) &&
1612 !qm_sg_entry_is_final(&sgt[i - 1]); i++) {
1613 WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1615 dma_unmap_page(priv->tx_dma_dev, qm_sg_addr(&sgt[i]),
1616 qm_sg_entry_get_len(&sgt[i]), dma_dir);
1619 dma_unmap_single(priv->tx_dma_dev, addr,
1620 priv->tx_headroom + qm_fd_get_length(fd),
1624 skb = *(struct sk_buff **)vaddr;
1626 /* DMA unmapping is required before accessing the HW provided info */
1627 if (ts && priv->tx_tstamp &&
1628 skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
1629 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
1631 if (!fman_port_get_tstamp(priv->mac_dev->port[TX], vaddr,
1633 shhwtstamps.hwtstamp = ns_to_ktime(ns);
1634 skb_tstamp_tx(skb, &shhwtstamps);
1636 dev_warn(dev, "fman_port_get_tstamp failed!\n");
1640 if (qm_fd_get_format(fd) == qm_fd_sg)
1641 /* Free the page that we allocated on Tx for the SGT */
1642 free_pages((unsigned long)vaddr, 0);
1647 static u8 rx_csum_offload(const struct dpaa_priv *priv, const struct qm_fd *fd)
1649 /* The parser has run and performed L4 checksum validation.
1650 * We know there were no parser errors (and implicitly no
1651 * L4 csum error), otherwise we wouldn't be here.
1653 if ((priv->net_dev->features & NETIF_F_RXCSUM) &&
1654 (be32_to_cpu(fd->status) & FM_FD_STAT_L4CV))
1655 return CHECKSUM_UNNECESSARY;
1657 /* We're here because either the parser didn't run or the L4 checksum
1658 * was not verified. This may include the case of a UDP frame with
1659 * checksum zero or an L4 proto other than TCP/UDP
1661 return CHECKSUM_NONE;
1664 /* Build a linear skb around the received buffer.
1665 * We are guaranteed there is enough room at the end of the data buffer to
1666 * accommodate the shared info area of the skb.
1668 static struct sk_buff *contig_fd_to_skb(const struct dpaa_priv *priv,
1669 const struct qm_fd *fd)
1671 ssize_t fd_off = qm_fd_get_offset(fd);
1672 dma_addr_t addr = qm_fd_addr(fd);
1673 struct dpaa_bp *dpaa_bp;
1674 struct sk_buff *skb;
1677 vaddr = phys_to_virt(addr);
1678 WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
1680 dpaa_bp = dpaa_bpid2pool(fd->bpid);
1684 skb = build_skb(vaddr, dpaa_bp->size +
1685 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
1686 if (WARN_ONCE(!skb, "Build skb failure on Rx\n"))
1688 WARN_ON(fd_off != priv->rx_headroom);
1689 skb_reserve(skb, fd_off);
1690 skb_put(skb, qm_fd_get_length(fd));
1692 skb->ip_summed = rx_csum_offload(priv, fd);
1697 free_pages((unsigned long)vaddr, 0);
1701 /* Build an skb with the data of the first S/G entry in the linear portion and
1702 * the rest of the frame as skb fragments.
1704 * The page fragment holding the S/G Table is recycled here.
1706 static struct sk_buff *sg_fd_to_skb(const struct dpaa_priv *priv,
1707 const struct qm_fd *fd)
1709 ssize_t fd_off = qm_fd_get_offset(fd);
1710 dma_addr_t addr = qm_fd_addr(fd);
1711 const struct qm_sg_entry *sgt;
1712 struct page *page, *head_page;
1713 struct dpaa_bp *dpaa_bp;
1714 void *vaddr, *sg_vaddr;
1715 int frag_off, frag_len;
1716 struct sk_buff *skb;
1723 vaddr = phys_to_virt(addr);
1724 WARN_ON(!IS_ALIGNED((unsigned long)vaddr, SMP_CACHE_BYTES));
1726 /* Iterate through the SGT entries and add data buffers to the skb */
1727 sgt = vaddr + fd_off;
1729 for (i = 0; i < DPAA_SGT_MAX_ENTRIES; i++) {
1730 /* Extension bit is not supported */
1731 WARN_ON(qm_sg_entry_is_ext(&sgt[i]));
1733 sg_addr = qm_sg_addr(&sgt[i]);
1734 sg_vaddr = phys_to_virt(sg_addr);
1735 WARN_ON(!IS_ALIGNED((unsigned long)sg_vaddr,
1738 /* We may use multiple Rx pools */
1739 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1743 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1744 dma_unmap_page(priv->rx_dma_dev, sg_addr,
1745 DPAA_BP_RAW_SIZE, DMA_FROM_DEVICE);
1747 sz = dpaa_bp->size +
1748 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
1749 skb = build_skb(sg_vaddr, sz);
1753 skb->ip_summed = rx_csum_offload(priv, fd);
1755 /* Make sure forwarded skbs will have enough space
1756 * on Tx, if extra headers are added.
1758 WARN_ON(fd_off != priv->rx_headroom);
1759 skb_reserve(skb, fd_off);
1760 skb_put(skb, qm_sg_entry_get_len(&sgt[i]));
1762 /* Not the first S/G entry; all data from buffer will
1763 * be added in an skb fragment; fragment index is offset
1764 * by one since first S/G entry was incorporated in the
1765 * linear part of the skb.
1767 * Caution: 'page' may be a tail page.
1769 page = virt_to_page(sg_vaddr);
1770 head_page = virt_to_head_page(sg_vaddr);
1772 /* Compute offset in (possibly tail) page */
1773 page_offset = ((unsigned long)sg_vaddr &
1775 (page_address(page) - page_address(head_page));
1776 /* page_offset only refers to the beginning of sgt[i];
1777 * but the buffer itself may have an internal offset.
1779 frag_off = qm_sg_entry_get_off(&sgt[i]) + page_offset;
1780 frag_len = qm_sg_entry_get_len(&sgt[i]);
1781 /* skb_add_rx_frag() does no checking on the page; if
1782 * we pass it a tail page, we'll end up with
1783 * bad page accounting and eventually with segafults.
1785 skb_add_rx_frag(skb, i - 1, head_page, frag_off,
1786 frag_len, dpaa_bp->size);
1788 /* Update the pool count for the current {cpu x bpool} */
1791 if (qm_sg_entry_is_final(&sgt[i]))
1794 WARN_ONCE(i == DPAA_SGT_MAX_ENTRIES, "No final bit on SGT\n");
1796 /* free the SG table buffer */
1797 free_pages((unsigned long)vaddr, 0);
1802 /* compensate sw bpool counter changes */
1803 for (i--; i >= 0; i--) {
1804 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1806 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1810 /* free all the SG entries */
1811 for (i = 0; i < DPAA_SGT_MAX_ENTRIES ; i++) {
1812 sg_addr = qm_sg_addr(&sgt[i]);
1813 sg_vaddr = phys_to_virt(sg_addr);
1814 free_pages((unsigned long)sg_vaddr, 0);
1815 dpaa_bp = dpaa_bpid2pool(sgt[i].bpid);
1817 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
1821 if (qm_sg_entry_is_final(&sgt[i]))
1824 /* free the SGT fragment */
1825 free_pages((unsigned long)vaddr, 0);
1830 static int skb_to_contig_fd(struct dpaa_priv *priv,
1831 struct sk_buff *skb, struct qm_fd *fd,
1834 struct net_device *net_dev = priv->net_dev;
1835 enum dma_data_direction dma_dir;
1836 unsigned char *buff_start;
1837 struct sk_buff **skbh;
1841 /* We are guaranteed to have at least tx_headroom bytes
1842 * available, so just use that for offset.
1844 fd->bpid = FSL_DPAA_BPID_INV;
1845 buff_start = skb->data - priv->tx_headroom;
1846 dma_dir = DMA_TO_DEVICE;
1848 skbh = (struct sk_buff **)buff_start;
1851 /* Enable L3/L4 hardware checksum computation.
1853 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may
1854 * need to write into the skb.
1856 err = dpaa_enable_tx_csum(priv, skb, fd,
1857 buff_start + DPAA_TX_PRIV_DATA_SIZE);
1858 if (unlikely(err < 0)) {
1859 if (net_ratelimit())
1860 netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
1865 /* Fill in the rest of the FD fields */
1866 qm_fd_set_contig(fd, priv->tx_headroom, skb->len);
1867 fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO);
1869 /* Map the entire buffer size that may be seen by FMan, but no more */
1870 addr = dma_map_single(priv->tx_dma_dev, buff_start,
1871 priv->tx_headroom + skb->len, dma_dir);
1872 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
1873 if (net_ratelimit())
1874 netif_err(priv, tx_err, net_dev, "dma_map_single() failed\n");
1877 qm_fd_addr_set64(fd, addr);
1882 static int skb_to_sg_fd(struct dpaa_priv *priv,
1883 struct sk_buff *skb, struct qm_fd *fd)
1885 const enum dma_data_direction dma_dir = DMA_TO_DEVICE;
1886 const int nr_frags = skb_shinfo(skb)->nr_frags;
1887 struct net_device *net_dev = priv->net_dev;
1888 struct qm_sg_entry *sgt;
1889 struct sk_buff **skbh;
1897 /* get a page to store the SGTable */
1898 p = dev_alloc_pages(0);
1900 netdev_err(net_dev, "dev_alloc_pages() failed\n");
1903 buff_start = page_address(p);
1905 /* Enable L3/L4 hardware checksum computation.
1907 * We must do this before dma_map_single(DMA_TO_DEVICE), because we may
1908 * need to write into the skb.
1910 err = dpaa_enable_tx_csum(priv, skb, fd,
1911 buff_start + DPAA_TX_PRIV_DATA_SIZE);
1912 if (unlikely(err < 0)) {
1913 if (net_ratelimit())
1914 netif_err(priv, tx_err, net_dev, "HW csum error: %d\n",
1919 /* SGT[0] is used by the linear part */
1920 sgt = (struct qm_sg_entry *)(buff_start + priv->tx_headroom);
1921 frag_len = skb_headlen(skb);
1922 qm_sg_entry_set_len(&sgt[0], frag_len);
1923 sgt[0].bpid = FSL_DPAA_BPID_INV;
1925 addr = dma_map_single(priv->tx_dma_dev, skb->data,
1926 skb_headlen(skb), dma_dir);
1927 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
1928 netdev_err(priv->net_dev, "DMA mapping failed\n");
1930 goto sg0_map_failed;
1932 qm_sg_entry_set64(&sgt[0], addr);
1934 /* populate the rest of SGT entries */
1935 for (i = 0; i < nr_frags; i++) {
1936 frag = &skb_shinfo(skb)->frags[i];
1937 frag_len = skb_frag_size(frag);
1938 WARN_ON(!skb_frag_page(frag));
1939 addr = skb_frag_dma_map(priv->tx_dma_dev, frag, 0,
1941 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
1942 netdev_err(priv->net_dev, "DMA mapping failed\n");
1947 qm_sg_entry_set_len(&sgt[i + 1], frag_len);
1948 sgt[i + 1].bpid = FSL_DPAA_BPID_INV;
1949 sgt[i + 1].offset = 0;
1951 /* keep the offset in the address */
1952 qm_sg_entry_set64(&sgt[i + 1], addr);
1955 /* Set the final bit in the last used entry of the SGT */
1956 qm_sg_entry_set_f(&sgt[nr_frags], frag_len);
1958 /* set fd offset to priv->tx_headroom */
1959 qm_fd_set_sg(fd, priv->tx_headroom, skb->len);
1961 /* DMA map the SGT page */
1962 skbh = (struct sk_buff **)buff_start;
1965 addr = dma_map_page(priv->tx_dma_dev, p, 0,
1966 priv->tx_headroom + DPAA_SGT_SIZE, dma_dir);
1967 if (unlikely(dma_mapping_error(priv->tx_dma_dev, addr))) {
1968 netdev_err(priv->net_dev, "DMA mapping failed\n");
1970 goto sgt_map_failed;
1973 fd->bpid = FSL_DPAA_BPID_INV;
1974 fd->cmd |= cpu_to_be32(FM_FD_CMD_FCO);
1975 qm_fd_addr_set64(fd, addr);
1981 for (j = 0; j < i; j++)
1982 dma_unmap_page(priv->tx_dma_dev, qm_sg_addr(&sgt[j]),
1983 qm_sg_entry_get_len(&sgt[j]), dma_dir);
1986 free_pages((unsigned long)buff_start, 0);
1991 static inline int dpaa_xmit(struct dpaa_priv *priv,
1992 struct rtnl_link_stats64 *percpu_stats,
1996 struct qman_fq *egress_fq;
1999 egress_fq = priv->egress_fqs[queue];
2000 if (fd->bpid == FSL_DPAA_BPID_INV)
2001 fd->cmd |= cpu_to_be32(qman_fq_fqid(priv->conf_fqs[queue]));
2003 /* Trace this Tx fd */
2004 trace_dpaa_tx_fd(priv->net_dev, egress_fq, fd);
2006 for (i = 0; i < DPAA_ENQUEUE_RETRIES; i++) {
2007 err = qman_enqueue(egress_fq, fd);
2012 if (unlikely(err < 0)) {
2013 percpu_stats->tx_fifo_errors++;
2017 percpu_stats->tx_packets++;
2018 percpu_stats->tx_bytes += qm_fd_get_length(fd);
2024 dpaa_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
2026 const int queue_mapping = skb_get_queue_mapping(skb);
2027 bool nonlinear = skb_is_nonlinear(skb);
2028 struct rtnl_link_stats64 *percpu_stats;
2029 struct dpaa_percpu_priv *percpu_priv;
2030 struct netdev_queue *txq;
2031 struct dpaa_priv *priv;
2036 priv = netdev_priv(net_dev);
2037 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2038 percpu_stats = &percpu_priv->stats;
2040 qm_fd_clear_fd(&fd);
2043 /* We're going to store the skb backpointer at the beginning
2044 * of the data buffer, so we need a privately owned skb
2046 * We've made sure skb is not shared in dev->priv_flags,
2047 * we need to verify the skb head is not cloned
2049 if (skb_cow_head(skb, priv->tx_headroom))
2052 WARN_ON(skb_is_nonlinear(skb));
2055 /* MAX_SKB_FRAGS is equal or larger than our dpaa_SGT_MAX_ENTRIES;
2056 * make sure we don't feed FMan with more fragments than it supports.
2058 if (unlikely(nonlinear &&
2059 (skb_shinfo(skb)->nr_frags >= DPAA_SGT_MAX_ENTRIES))) {
2060 /* If the egress skb contains more fragments than we support
2061 * we have no choice but to linearize it ourselves.
2063 if (__skb_linearize(skb))
2066 nonlinear = skb_is_nonlinear(skb);
2070 /* Just create a S/G fd based on the skb */
2071 err = skb_to_sg_fd(priv, skb, &fd);
2072 percpu_priv->tx_frag_skbuffs++;
2074 /* Create a contig FD from this skb */
2075 err = skb_to_contig_fd(priv, skb, &fd, &offset);
2077 if (unlikely(err < 0))
2078 goto skb_to_fd_failed;
2080 txq = netdev_get_tx_queue(net_dev, queue_mapping);
2082 /* LLTX requires to do our own update of trans_start */
2083 txq->trans_start = jiffies;
2085 if (priv->tx_tstamp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) {
2086 fd.cmd |= cpu_to_be32(FM_FD_CMD_UPD);
2087 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2090 if (likely(dpaa_xmit(priv, percpu_stats, queue_mapping, &fd) == 0))
2091 return NETDEV_TX_OK;
2093 dpaa_cleanup_tx_fd(priv, &fd, false);
2096 percpu_stats->tx_errors++;
2098 return NETDEV_TX_OK;
2101 static void dpaa_rx_error(struct net_device *net_dev,
2102 const struct dpaa_priv *priv,
2103 struct dpaa_percpu_priv *percpu_priv,
2104 const struct qm_fd *fd,
2107 if (net_ratelimit())
2108 netif_err(priv, hw, net_dev, "Err FD status = 0x%08x\n",
2109 be32_to_cpu(fd->status) & FM_FD_STAT_RX_ERRORS);
2111 percpu_priv->stats.rx_errors++;
2113 if (be32_to_cpu(fd->status) & FM_FD_ERR_DMA)
2114 percpu_priv->rx_errors.dme++;
2115 if (be32_to_cpu(fd->status) & FM_FD_ERR_PHYSICAL)
2116 percpu_priv->rx_errors.fpe++;
2117 if (be32_to_cpu(fd->status) & FM_FD_ERR_SIZE)
2118 percpu_priv->rx_errors.fse++;
2119 if (be32_to_cpu(fd->status) & FM_FD_ERR_PRS_HDR_ERR)
2120 percpu_priv->rx_errors.phe++;
2122 dpaa_fd_release(net_dev, fd);
2125 static void dpaa_tx_error(struct net_device *net_dev,
2126 const struct dpaa_priv *priv,
2127 struct dpaa_percpu_priv *percpu_priv,
2128 const struct qm_fd *fd,
2131 struct sk_buff *skb;
2133 if (net_ratelimit())
2134 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2135 be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS);
2137 percpu_priv->stats.tx_errors++;
2139 skb = dpaa_cleanup_tx_fd(priv, fd, false);
2143 static int dpaa_eth_poll(struct napi_struct *napi, int budget)
2145 struct dpaa_napi_portal *np =
2146 container_of(napi, struct dpaa_napi_portal, napi);
2148 int cleaned = qman_p_poll_dqrr(np->p, budget);
2150 if (cleaned < budget) {
2151 napi_complete_done(napi, cleaned);
2152 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
2153 } else if (np->down) {
2154 qman_p_irqsource_add(np->p, QM_PIRQ_DQRI);
2160 static void dpaa_tx_conf(struct net_device *net_dev,
2161 const struct dpaa_priv *priv,
2162 struct dpaa_percpu_priv *percpu_priv,
2163 const struct qm_fd *fd,
2166 struct sk_buff *skb;
2168 if (unlikely(be32_to_cpu(fd->status) & FM_FD_STAT_TX_ERRORS)) {
2169 if (net_ratelimit())
2170 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2171 be32_to_cpu(fd->status) &
2172 FM_FD_STAT_TX_ERRORS);
2174 percpu_priv->stats.tx_errors++;
2177 percpu_priv->tx_confirm++;
2179 skb = dpaa_cleanup_tx_fd(priv, fd, true);
2184 static inline int dpaa_eth_napi_schedule(struct dpaa_percpu_priv *percpu_priv,
2185 struct qman_portal *portal)
2187 if (unlikely(in_irq() || !in_serving_softirq())) {
2188 /* Disable QMan IRQ and invoke NAPI */
2189 qman_p_irqsource_remove(portal, QM_PIRQ_DQRI);
2191 percpu_priv->np.p = portal;
2192 napi_schedule(&percpu_priv->np.napi);
2193 percpu_priv->in_interrupt++;
2199 static enum qman_cb_dqrr_result rx_error_dqrr(struct qman_portal *portal,
2201 const struct qm_dqrr_entry *dq)
2203 struct dpaa_fq *dpaa_fq = container_of(fq, struct dpaa_fq, fq_base);
2204 struct dpaa_percpu_priv *percpu_priv;
2205 struct net_device *net_dev;
2206 struct dpaa_bp *dpaa_bp;
2207 struct dpaa_priv *priv;
2209 net_dev = dpaa_fq->net_dev;
2210 priv = netdev_priv(net_dev);
2211 dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
2213 return qman_cb_dqrr_consume;
2215 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2217 if (dpaa_eth_napi_schedule(percpu_priv, portal))
2218 return qman_cb_dqrr_stop;
2220 dpaa_eth_refill_bpools(priv);
2221 dpaa_rx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2223 return qman_cb_dqrr_consume;
2226 static enum qman_cb_dqrr_result rx_default_dqrr(struct qman_portal *portal,
2228 const struct qm_dqrr_entry *dq)
2230 struct skb_shared_hwtstamps *shhwtstamps;
2231 struct rtnl_link_stats64 *percpu_stats;
2232 struct dpaa_percpu_priv *percpu_priv;
2233 const struct qm_fd *fd = &dq->fd;
2234 dma_addr_t addr = qm_fd_addr(fd);
2235 enum qm_fd_format fd_format;
2236 struct net_device *net_dev;
2237 u32 fd_status, hash_offset;
2238 struct dpaa_bp *dpaa_bp;
2239 struct dpaa_priv *priv;
2240 unsigned int skb_len;
2241 struct sk_buff *skb;
2246 fd_status = be32_to_cpu(fd->status);
2247 fd_format = qm_fd_get_format(fd);
2248 net_dev = ((struct dpaa_fq *)fq)->net_dev;
2249 priv = netdev_priv(net_dev);
2250 dpaa_bp = dpaa_bpid2pool(dq->fd.bpid);
2252 return qman_cb_dqrr_consume;
2254 /* Trace the Rx fd */
2255 trace_dpaa_rx_fd(net_dev, fq, &dq->fd);
2257 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2258 percpu_stats = &percpu_priv->stats;
2260 if (unlikely(dpaa_eth_napi_schedule(percpu_priv, portal)))
2261 return qman_cb_dqrr_stop;
2263 /* Make sure we didn't run out of buffers */
2264 if (unlikely(dpaa_eth_refill_bpools(priv))) {
2265 /* Unable to refill the buffer pool due to insufficient
2266 * system memory. Just release the frame back into the pool,
2267 * otherwise we'll soon end up with an empty buffer pool.
2269 dpaa_fd_release(net_dev, &dq->fd);
2270 return qman_cb_dqrr_consume;
2273 if (unlikely(fd_status & FM_FD_STAT_RX_ERRORS) != 0) {
2274 if (net_ratelimit())
2275 netif_warn(priv, hw, net_dev, "FD status = 0x%08x\n",
2276 fd_status & FM_FD_STAT_RX_ERRORS);
2278 percpu_stats->rx_errors++;
2279 dpaa_fd_release(net_dev, fd);
2280 return qman_cb_dqrr_consume;
2283 dma_unmap_page(dpaa_bp->priv->rx_dma_dev, addr, DPAA_BP_RAW_SIZE,
2286 /* prefetch the first 64 bytes of the frame or the SGT start */
2287 vaddr = phys_to_virt(addr);
2288 prefetch(vaddr + qm_fd_get_offset(fd));
2290 /* The only FD types that we may receive are contig and S/G */
2291 WARN_ON((fd_format != qm_fd_contig) && (fd_format != qm_fd_sg));
2293 /* Account for either the contig buffer or the SGT buffer (depending on
2294 * which case we were in) having been removed from the pool.
2296 count_ptr = this_cpu_ptr(dpaa_bp->percpu_count);
2299 if (likely(fd_format == qm_fd_contig))
2300 skb = contig_fd_to_skb(priv, fd);
2302 skb = sg_fd_to_skb(priv, fd);
2304 return qman_cb_dqrr_consume;
2306 if (priv->rx_tstamp) {
2307 shhwtstamps = skb_hwtstamps(skb);
2308 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2310 if (!fman_port_get_tstamp(priv->mac_dev->port[RX], vaddr, &ns))
2311 shhwtstamps->hwtstamp = ns_to_ktime(ns);
2313 dev_warn(net_dev->dev.parent, "fman_port_get_tstamp failed!\n");
2316 skb->protocol = eth_type_trans(skb, net_dev);
2318 if (net_dev->features & NETIF_F_RXHASH && priv->keygen_in_use &&
2319 !fman_port_get_hash_result_offset(priv->mac_dev->port[RX],
2321 enum pkt_hash_types type;
2323 /* if L4 exists, it was used in the hash generation */
2324 type = be32_to_cpu(fd->status) & FM_FD_STAT_L4CV ?
2325 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3;
2326 skb_set_hash(skb, be32_to_cpu(*(u32 *)(vaddr + hash_offset)),
2332 if (unlikely(netif_receive_skb(skb) == NET_RX_DROP)) {
2333 percpu_stats->rx_dropped++;
2334 return qman_cb_dqrr_consume;
2337 percpu_stats->rx_packets++;
2338 percpu_stats->rx_bytes += skb_len;
2340 return qman_cb_dqrr_consume;
2343 static enum qman_cb_dqrr_result conf_error_dqrr(struct qman_portal *portal,
2345 const struct qm_dqrr_entry *dq)
2347 struct dpaa_percpu_priv *percpu_priv;
2348 struct net_device *net_dev;
2349 struct dpaa_priv *priv;
2351 net_dev = ((struct dpaa_fq *)fq)->net_dev;
2352 priv = netdev_priv(net_dev);
2354 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2356 if (dpaa_eth_napi_schedule(percpu_priv, portal))
2357 return qman_cb_dqrr_stop;
2359 dpaa_tx_error(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2361 return qman_cb_dqrr_consume;
2364 static enum qman_cb_dqrr_result conf_dflt_dqrr(struct qman_portal *portal,
2366 const struct qm_dqrr_entry *dq)
2368 struct dpaa_percpu_priv *percpu_priv;
2369 struct net_device *net_dev;
2370 struct dpaa_priv *priv;
2372 net_dev = ((struct dpaa_fq *)fq)->net_dev;
2373 priv = netdev_priv(net_dev);
2376 trace_dpaa_tx_conf_fd(net_dev, fq, &dq->fd);
2378 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2380 if (dpaa_eth_napi_schedule(percpu_priv, portal))
2381 return qman_cb_dqrr_stop;
2383 dpaa_tx_conf(net_dev, priv, percpu_priv, &dq->fd, fq->fqid);
2385 return qman_cb_dqrr_consume;
2388 static void egress_ern(struct qman_portal *portal,
2390 const union qm_mr_entry *msg)
2392 const struct qm_fd *fd = &msg->ern.fd;
2393 struct dpaa_percpu_priv *percpu_priv;
2394 const struct dpaa_priv *priv;
2395 struct net_device *net_dev;
2396 struct sk_buff *skb;
2398 net_dev = ((struct dpaa_fq *)fq)->net_dev;
2399 priv = netdev_priv(net_dev);
2400 percpu_priv = this_cpu_ptr(priv->percpu_priv);
2402 percpu_priv->stats.tx_dropped++;
2403 percpu_priv->stats.tx_fifo_errors++;
2404 count_ern(percpu_priv, msg);
2406 skb = dpaa_cleanup_tx_fd(priv, fd, false);
2407 dev_kfree_skb_any(skb);
2410 static const struct dpaa_fq_cbs dpaa_fq_cbs = {
2411 .rx_defq = { .cb = { .dqrr = rx_default_dqrr } },
2412 .tx_defq = { .cb = { .dqrr = conf_dflt_dqrr } },
2413 .rx_errq = { .cb = { .dqrr = rx_error_dqrr } },
2414 .tx_errq = { .cb = { .dqrr = conf_error_dqrr } },
2415 .egress_ern = { .cb = { .ern = egress_ern } }
2418 static void dpaa_eth_napi_enable(struct dpaa_priv *priv)
2420 struct dpaa_percpu_priv *percpu_priv;
2423 for_each_online_cpu(i) {
2424 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2426 percpu_priv->np.down = 0;
2427 napi_enable(&percpu_priv->np.napi);
2431 static void dpaa_eth_napi_disable(struct dpaa_priv *priv)
2433 struct dpaa_percpu_priv *percpu_priv;
2436 for_each_online_cpu(i) {
2437 percpu_priv = per_cpu_ptr(priv->percpu_priv, i);
2439 percpu_priv->np.down = 1;
2440 napi_disable(&percpu_priv->np.napi);
2444 static void dpaa_adjust_link(struct net_device *net_dev)
2446 struct mac_device *mac_dev;
2447 struct dpaa_priv *priv;
2449 priv = netdev_priv(net_dev);
2450 mac_dev = priv->mac_dev;
2451 mac_dev->adjust_link(mac_dev);
2454 static int dpaa_phy_init(struct net_device *net_dev)
2456 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
2457 struct mac_device *mac_dev;
2458 struct phy_device *phy_dev;
2459 struct dpaa_priv *priv;
2461 priv = netdev_priv(net_dev);
2462 mac_dev = priv->mac_dev;
2464 phy_dev = of_phy_connect(net_dev, mac_dev->phy_node,
2465 &dpaa_adjust_link, 0,
2468 netif_err(priv, ifup, net_dev, "init_phy() failed\n");
2472 /* Remove any features not supported by the controller */
2473 ethtool_convert_legacy_u32_to_link_mode(mask, mac_dev->if_support);
2474 linkmode_and(phy_dev->supported, phy_dev->supported, mask);
2476 phy_support_asym_pause(phy_dev);
2478 mac_dev->phy_dev = phy_dev;
2479 net_dev->phydev = phy_dev;
2484 static int dpaa_open(struct net_device *net_dev)
2486 struct mac_device *mac_dev;
2487 struct dpaa_priv *priv;
2490 priv = netdev_priv(net_dev);
2491 mac_dev = priv->mac_dev;
2492 dpaa_eth_napi_enable(priv);
2494 err = dpaa_phy_init(net_dev);
2496 goto phy_init_failed;
2498 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
2499 err = fman_port_enable(mac_dev->port[i]);
2501 goto mac_start_failed;
2504 err = priv->mac_dev->start(mac_dev);
2506 netif_err(priv, ifup, net_dev, "mac_dev->start() = %d\n", err);
2507 goto mac_start_failed;
2510 netif_tx_start_all_queues(net_dev);
2515 for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++)
2516 fman_port_disable(mac_dev->port[i]);
2519 dpaa_eth_napi_disable(priv);
2524 static int dpaa_eth_stop(struct net_device *net_dev)
2526 struct dpaa_priv *priv;
2529 err = dpaa_stop(net_dev);
2531 priv = netdev_priv(net_dev);
2532 dpaa_eth_napi_disable(priv);
2537 static int dpaa_ts_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2539 struct dpaa_priv *priv = netdev_priv(dev);
2540 struct hwtstamp_config config;
2542 if (copy_from_user(&config, rq->ifr_data, sizeof(config)))
2545 switch (config.tx_type) {
2546 case HWTSTAMP_TX_OFF:
2547 /* Couldn't disable rx/tx timestamping separately.
2550 priv->tx_tstamp = false;
2552 case HWTSTAMP_TX_ON:
2553 priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true);
2554 priv->tx_tstamp = true;
2560 if (config.rx_filter == HWTSTAMP_FILTER_NONE) {
2561 /* Couldn't disable rx/tx timestamping separately.
2564 priv->rx_tstamp = false;
2566 priv->mac_dev->set_tstamp(priv->mac_dev->fman_mac, true);
2567 priv->rx_tstamp = true;
2568 /* TS is set for all frame types, not only those requested */
2569 config.rx_filter = HWTSTAMP_FILTER_ALL;
2572 return copy_to_user(rq->ifr_data, &config, sizeof(config)) ?
2576 static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
2580 if (cmd == SIOCGMIIREG) {
2581 if (net_dev->phydev)
2582 return phy_mii_ioctl(net_dev->phydev, rq, cmd);
2585 if (cmd == SIOCSHWTSTAMP)
2586 return dpaa_ts_ioctl(net_dev, rq, cmd);
2591 static const struct net_device_ops dpaa_ops = {
2592 .ndo_open = dpaa_open,
2593 .ndo_start_xmit = dpaa_start_xmit,
2594 .ndo_stop = dpaa_eth_stop,
2595 .ndo_tx_timeout = dpaa_tx_timeout,
2596 .ndo_get_stats64 = dpaa_get_stats64,
2597 .ndo_change_carrier = fixed_phy_change_carrier,
2598 .ndo_set_mac_address = dpaa_set_mac_address,
2599 .ndo_validate_addr = eth_validate_addr,
2600 .ndo_set_rx_mode = dpaa_set_rx_mode,
2601 .ndo_do_ioctl = dpaa_ioctl,
2602 .ndo_setup_tc = dpaa_setup_tc,
2605 static int dpaa_napi_add(struct net_device *net_dev)
2607 struct dpaa_priv *priv = netdev_priv(net_dev);
2608 struct dpaa_percpu_priv *percpu_priv;
2611 for_each_possible_cpu(cpu) {
2612 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
2614 netif_napi_add(net_dev, &percpu_priv->np.napi,
2615 dpaa_eth_poll, NAPI_POLL_WEIGHT);
2621 static void dpaa_napi_del(struct net_device *net_dev)
2623 struct dpaa_priv *priv = netdev_priv(net_dev);
2624 struct dpaa_percpu_priv *percpu_priv;
2627 for_each_possible_cpu(cpu) {
2628 percpu_priv = per_cpu_ptr(priv->percpu_priv, cpu);
2630 netif_napi_del(&percpu_priv->np.napi);
2634 static inline void dpaa_bp_free_pf(const struct dpaa_bp *bp,
2635 struct bm_buffer *bmb)
2637 dma_addr_t addr = bm_buf_addr(bmb);
2639 dma_unmap_page(bp->priv->rx_dma_dev, addr, DPAA_BP_RAW_SIZE,
2642 skb_free_frag(phys_to_virt(addr));
2645 /* Alloc the dpaa_bp struct and configure default values */
2646 static struct dpaa_bp *dpaa_bp_alloc(struct device *dev)
2648 struct dpaa_bp *dpaa_bp;
2650 dpaa_bp = devm_kzalloc(dev, sizeof(*dpaa_bp), GFP_KERNEL);
2652 return ERR_PTR(-ENOMEM);
2654 dpaa_bp->bpid = FSL_DPAA_BPID_INV;
2655 dpaa_bp->percpu_count = devm_alloc_percpu(dev, *dpaa_bp->percpu_count);
2656 if (!dpaa_bp->percpu_count)
2657 return ERR_PTR(-ENOMEM);
2659 dpaa_bp->config_count = FSL_DPAA_ETH_MAX_BUF_COUNT;
2661 dpaa_bp->seed_cb = dpaa_bp_seed;
2662 dpaa_bp->free_buf_cb = dpaa_bp_free_pf;
2667 /* Place all ingress FQs (Rx Default, Rx Error) in a dedicated CGR.
2668 * We won't be sending congestion notifications to FMan; for now, we just use
2669 * this CGR to generate enqueue rejections to FMan in order to drop the frames
2670 * before they reach our ingress queues and eat up memory.
2672 static int dpaa_ingress_cgr_init(struct dpaa_priv *priv)
2674 struct qm_mcc_initcgr initcgr;
2678 err = qman_alloc_cgrid(&priv->ingress_cgr.cgrid);
2680 if (netif_msg_drv(priv))
2681 pr_err("Error %d allocating CGR ID\n", err);
2685 /* Enable CS TD, but disable Congestion State Change Notifications. */
2686 memset(&initcgr, 0, sizeof(initcgr));
2687 initcgr.we_mask = cpu_to_be16(QM_CGR_WE_CS_THRES);
2688 initcgr.cgr.cscn_en = QM_CGR_EN;
2689 cs_th = DPAA_INGRESS_CS_THRESHOLD;
2690 qm_cgr_cs_thres_set64(&initcgr.cgr.cs_thres, cs_th, 1);
2692 initcgr.we_mask |= cpu_to_be16(QM_CGR_WE_CSTD_EN);
2693 initcgr.cgr.cstd_en = QM_CGR_EN;
2695 /* This CGR will be associated with the SWP affined to the current CPU.
2696 * However, we'll place all our ingress FQs in it.
2698 err = qman_create_cgr(&priv->ingress_cgr, QMAN_CGR_FLAG_USE_INIT,
2701 if (netif_msg_drv(priv))
2702 pr_err("Error %d creating ingress CGR with ID %d\n",
2703 err, priv->ingress_cgr.cgrid);
2704 qman_release_cgrid(priv->ingress_cgr.cgrid);
2707 if (netif_msg_drv(priv))
2708 pr_debug("Created ingress CGR %d for netdev with hwaddr %pM\n",
2709 priv->ingress_cgr.cgrid, priv->mac_dev->addr);
2711 priv->use_ingress_cgr = true;
2717 static inline u16 dpaa_get_headroom(struct dpaa_buffer_layout *bl)
2721 /* The frame headroom must accommodate:
2722 * - the driver private data area
2723 * - parse results, hash results, timestamp if selected
2724 * If either hash results or time stamp are selected, both will
2725 * be copied to/from the frame headroom, as TS is located between PR and
2726 * HR in the IC and IC copy size has a granularity of 16bytes
2727 * (see description of FMBM_RICP and FMBM_TICP registers in DPAARM)
2729 * Also make sure the headroom is a multiple of data_align bytes
2731 headroom = (u16)(bl->priv_data_size + DPAA_PARSE_RESULTS_SIZE +
2732 DPAA_TIME_STAMP_SIZE + DPAA_HASH_RESULTS_SIZE);
2734 return DPAA_FD_DATA_ALIGNMENT ? ALIGN(headroom,
2735 DPAA_FD_DATA_ALIGNMENT) :
2739 static int dpaa_eth_probe(struct platform_device *pdev)
2741 struct net_device *net_dev = NULL;
2742 struct dpaa_bp *dpaa_bp = NULL;
2743 struct dpaa_fq *dpaa_fq, *tmp;
2744 struct dpaa_priv *priv = NULL;
2745 struct fm_port_fqs port_fqs;
2746 struct mac_device *mac_dev;
2747 int err = 0, channel;
2752 err = bman_is_probed();
2754 return -EPROBE_DEFER;
2756 dev_err(dev, "failing probe due to bman probe error\n");
2759 err = qman_is_probed();
2761 return -EPROBE_DEFER;
2763 dev_err(dev, "failing probe due to qman probe error\n");
2766 err = bman_portals_probed();
2768 return -EPROBE_DEFER;
2771 "failing probe due to bman portals probe error\n");
2774 err = qman_portals_probed();
2776 return -EPROBE_DEFER;
2779 "failing probe due to qman portals probe error\n");
2783 /* Allocate this early, so we can store relevant information in
2786 net_dev = alloc_etherdev_mq(sizeof(*priv), DPAA_ETH_TXQ_NUM);
2788 dev_err(dev, "alloc_etherdev_mq() failed\n");
2792 /* Do this here, so we can be verbose early */
2793 SET_NETDEV_DEV(net_dev, dev);
2794 dev_set_drvdata(dev, net_dev);
2796 priv = netdev_priv(net_dev);
2797 priv->net_dev = net_dev;
2799 priv->msg_enable = netif_msg_init(debug, DPAA_MSG_DEFAULT);
2801 mac_dev = dpaa_mac_dev_get(pdev);
2802 if (IS_ERR(mac_dev)) {
2803 netdev_err(net_dev, "dpaa_mac_dev_get() failed\n");
2804 err = PTR_ERR(mac_dev);
2808 /* Devices used for DMA mapping */
2809 priv->rx_dma_dev = fman_port_get_device(mac_dev->port[RX]);
2810 priv->tx_dma_dev = fman_port_get_device(mac_dev->port[TX]);
2811 err = dma_coerce_mask_and_coherent(priv->rx_dma_dev, DMA_BIT_MASK(40));
2813 err = dma_coerce_mask_and_coherent(priv->tx_dma_dev,
2816 netdev_err(net_dev, "dma_coerce_mask_and_coherent() failed\n");
2820 /* If fsl_fm_max_frm is set to a higher value than the all-common 1500,
2821 * we choose conservatively and let the user explicitly set a higher
2822 * MTU via ifconfig. Otherwise, the user may end up with different MTUs
2824 * If on the other hand fsl_fm_max_frm has been chosen below 1500,
2825 * start with the maximum allowed.
2827 net_dev->mtu = min(dpaa_get_max_mtu(), ETH_DATA_LEN);
2829 netdev_dbg(net_dev, "Setting initial MTU on net device: %d\n",
2832 priv->buf_layout[RX].priv_data_size = DPAA_RX_PRIV_DATA_SIZE; /* Rx */
2833 priv->buf_layout[TX].priv_data_size = DPAA_TX_PRIV_DATA_SIZE; /* Tx */
2836 dpaa_bp = dpaa_bp_alloc(dev);
2837 if (IS_ERR(dpaa_bp)) {
2838 err = PTR_ERR(dpaa_bp);
2841 /* the raw size of the buffers used for reception */
2842 dpaa_bp->raw_size = DPAA_BP_RAW_SIZE;
2843 /* avoid runtime computations by keeping the usable size here */
2844 dpaa_bp->size = dpaa_bp_size(dpaa_bp->raw_size);
2845 dpaa_bp->priv = priv;
2847 err = dpaa_bp_alloc_pool(dpaa_bp);
2850 priv->dpaa_bp = dpaa_bp;
2852 INIT_LIST_HEAD(&priv->dpaa_fq_list);
2854 memset(&port_fqs, 0, sizeof(port_fqs));
2856 err = dpaa_alloc_all_fqs(dev, &priv->dpaa_fq_list, &port_fqs);
2858 dev_err(dev, "dpaa_alloc_all_fqs() failed\n");
2862 priv->mac_dev = mac_dev;
2864 channel = dpaa_get_channel();
2866 dev_err(dev, "dpaa_get_channel() failed\n");
2871 priv->channel = (u16)channel;
2873 /* Walk the CPUs with affine portals
2874 * and add this pool channel to each's dequeue mask.
2876 dpaa_eth_add_channel(priv->channel);
2878 dpaa_fq_setup(priv, &dpaa_fq_cbs, priv->mac_dev->port[TX]);
2880 /* Create a congestion group for this netdev, with
2881 * dynamically-allocated CGR ID.
2882 * Must be executed after probing the MAC, but before
2883 * assigning the egress FQs to the CGRs.
2885 err = dpaa_eth_cgr_init(priv);
2887 dev_err(dev, "Error initializing CGR\n");
2891 err = dpaa_ingress_cgr_init(priv);
2893 dev_err(dev, "Error initializing ingress CGR\n");
2894 goto delete_egress_cgr;
2897 /* Add the FQs to the interface, and make them active */
2898 list_for_each_entry_safe(dpaa_fq, tmp, &priv->dpaa_fq_list, list) {
2899 err = dpaa_fq_init(dpaa_fq, false);
2904 priv->tx_headroom = dpaa_get_headroom(&priv->buf_layout[TX]);
2905 priv->rx_headroom = dpaa_get_headroom(&priv->buf_layout[RX]);
2907 /* All real interfaces need their ports initialized */
2908 err = dpaa_eth_init_ports(mac_dev, dpaa_bp, &port_fqs,
2909 &priv->buf_layout[0], dev);
2913 /* Rx traffic distribution based on keygen hashing defaults to on */
2914 priv->keygen_in_use = true;
2916 priv->percpu_priv = devm_alloc_percpu(dev, *priv->percpu_priv);
2917 if (!priv->percpu_priv) {
2918 dev_err(dev, "devm_alloc_percpu() failed\n");
2924 netif_set_real_num_tx_queues(net_dev, priv->num_tc * DPAA_TC_TXQ_NUM);
2926 /* Initialize NAPI */
2927 err = dpaa_napi_add(net_dev);
2929 goto delete_dpaa_napi;
2931 err = dpaa_netdev_init(net_dev, &dpaa_ops, tx_timeout);
2933 goto delete_dpaa_napi;
2935 dpaa_eth_sysfs_init(&net_dev->dev);
2937 netif_info(priv, probe, net_dev, "Probed interface %s\n",
2943 dpaa_napi_del(net_dev);
2945 dpaa_fq_free(dev, &priv->dpaa_fq_list);
2946 qman_delete_cgr_safe(&priv->ingress_cgr);
2947 qman_release_cgrid(priv->ingress_cgr.cgrid);
2949 qman_delete_cgr_safe(&priv->cgr_data.cgr);
2950 qman_release_cgrid(priv->cgr_data.cgr.cgrid);
2952 dpaa_bps_free(priv);
2954 dev_set_drvdata(dev, NULL);
2955 free_netdev(net_dev);
2960 static int dpaa_remove(struct platform_device *pdev)
2962 struct net_device *net_dev;
2963 struct dpaa_priv *priv;
2968 net_dev = dev_get_drvdata(dev);
2970 priv = netdev_priv(net_dev);
2972 dpaa_eth_sysfs_remove(dev);
2974 dev_set_drvdata(dev, NULL);
2975 unregister_netdev(net_dev);
2977 err = dpaa_fq_free(dev, &priv->dpaa_fq_list);
2979 qman_delete_cgr_safe(&priv->ingress_cgr);
2980 qman_release_cgrid(priv->ingress_cgr.cgrid);
2981 qman_delete_cgr_safe(&priv->cgr_data.cgr);
2982 qman_release_cgrid(priv->cgr_data.cgr.cgrid);
2984 dpaa_napi_del(net_dev);
2986 dpaa_bps_free(priv);
2988 free_netdev(net_dev);
2993 static const struct platform_device_id dpaa_devtype[] = {
2995 .name = "dpaa-ethernet",
3000 MODULE_DEVICE_TABLE(platform, dpaa_devtype);
3002 static struct platform_driver dpaa_driver = {
3004 .name = KBUILD_MODNAME,
3006 .id_table = dpaa_devtype,
3007 .probe = dpaa_eth_probe,
3008 .remove = dpaa_remove
3011 static int __init dpaa_load(void)
3015 pr_debug("FSL DPAA Ethernet driver\n");
3017 /* initialize dpaa_eth mirror values */
3018 dpaa_rx_extra_headroom = fman_get_rx_extra_headroom();
3019 dpaa_max_frm = fman_get_max_frm();
3021 err = platform_driver_register(&dpaa_driver);
3023 pr_err("Error, platform_driver_register() = %d\n", err);
3027 module_init(dpaa_load);
3029 static void __exit dpaa_unload(void)
3031 platform_driver_unregister(&dpaa_driver);
3033 /* Only one channel is used and needs to be released after all
3034 * interfaces are removed
3036 dpaa_release_channel();
3038 module_exit(dpaa_unload);
3040 MODULE_LICENSE("Dual BSD/GPL");
3041 MODULE_DESCRIPTION("FSL DPAA Ethernet driver");