1 // SPDX-License-Identifier: GPL-2.0+
3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
6 * Right now, I am very wasteful with the buffers. I allocate memory
7 * pages and then divide them into 2K frame buffers. This way I know I
8 * have buffers large enough to hold one frame within one buffer descriptor.
9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10 * will be much more memory efficient and will easily handle lots of
13 * Much better multiple PHY support by Magnus Damm.
14 * Copyright (c) 2000 Ericsson Radio Systems AB.
16 * Support for FEC controller of ColdFire processors.
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/string.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/ptrace.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/slab.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/icmp.h>
45 #include <linux/spinlock.h>
46 #include <linux/workqueue.h>
47 #include <linux/bitops.h>
49 #include <linux/irq.h>
50 #include <linux/clk.h>
51 #include <linux/crc32.h>
52 #include <linux/platform_device.h>
53 #include <linux/mdio.h>
54 #include <linux/phy.h>
55 #include <linux/fec.h>
57 #include <linux/of_device.h>
58 #include <linux/of_gpio.h>
59 #include <linux/of_mdio.h>
60 #include <linux/of_net.h>
61 #include <linux/regulator/consumer.h>
62 #include <linux/if_vlan.h>
63 #include <linux/pinctrl/consumer.h>
64 #include <linux/prefetch.h>
65 #include <soc/imx/cpuidle.h>
67 #include <asm/cacheflush.h>
71 static void set_multicast_list(struct net_device *ndev);
72 static void fec_enet_itr_coal_init(struct net_device *ndev);
74 #define DRIVER_NAME "fec"
76 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
78 /* Pause frame feild and FIFO threshold */
79 #define FEC_ENET_FCE (1 << 5)
80 #define FEC_ENET_RSEM_V 0x84
81 #define FEC_ENET_RSFL_V 16
82 #define FEC_ENET_RAEM_V 0x8
83 #define FEC_ENET_RAFL_V 0x8
84 #define FEC_ENET_OPD_V 0xFFF0
85 #define FEC_MDIO_PM_TIMEOUT 100 /* ms */
87 static struct platform_device_id fec_devtype[] = {
89 /* keep it for coldfire */
94 .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
98 .driver_data = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG,
101 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
102 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
107 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
108 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
111 .name = "mvf600-fec",
112 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC,
114 .name = "imx6sx-fec",
115 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
116 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
117 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
118 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
119 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE,
121 .name = "imx6ul-fec",
122 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
125 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
126 FEC_QUIRK_HAS_COALESCE,
131 MODULE_DEVICE_TABLE(platform, fec_devtype);
134 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
135 IMX27_FEC, /* runs on i.mx27/35/51 */
143 static const struct of_device_id fec_dt_ids[] = {
144 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
145 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
146 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
147 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
148 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
149 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
150 { .compatible = "fsl,imx6ul-fec", .data = &fec_devtype[IMX6UL_FEC], },
153 MODULE_DEVICE_TABLE(of, fec_dt_ids);
155 static unsigned char macaddr[ETH_ALEN];
156 module_param_array(macaddr, byte, NULL, 0);
157 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
159 #if defined(CONFIG_M5272)
161 * Some hardware gets it MAC address out of local flash memory.
162 * if this is non-zero then assume it is the address to get MAC from.
164 #if defined(CONFIG_NETtel)
165 #define FEC_FLASHMAC 0xf0006006
166 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
167 #define FEC_FLASHMAC 0xf0006000
168 #elif defined(CONFIG_CANCam)
169 #define FEC_FLASHMAC 0xf0020000
170 #elif defined (CONFIG_M5272C3)
171 #define FEC_FLASHMAC (0xffe04000 + 4)
172 #elif defined(CONFIG_MOD5272)
173 #define FEC_FLASHMAC 0xffc0406b
175 #define FEC_FLASHMAC 0
177 #endif /* CONFIG_M5272 */
179 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
181 * 2048 byte skbufs are allocated. However, alignment requirements
182 * varies between FEC variants. Worst case is 64, so round down by 64.
184 #define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64))
185 #define PKT_MINBUF_SIZE 64
187 /* FEC receive acceleration */
188 #define FEC_RACC_IPDIS (1 << 1)
189 #define FEC_RACC_PRODIS (1 << 2)
190 #define FEC_RACC_SHIFT16 BIT(7)
191 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
193 /* MIB Control Register */
194 #define FEC_MIB_CTRLSTAT_DISABLE BIT(31)
197 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
198 * size bits. Other FEC hardware does not, so we need to take that into
199 * account when setting it.
201 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
202 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
203 defined(CONFIG_ARM64)
204 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
206 #define OPT_FRAME_SIZE 0
209 /* FEC MII MMFR bits definition */
210 #define FEC_MMFR_ST (1 << 30)
211 #define FEC_MMFR_ST_C45 (0)
212 #define FEC_MMFR_OP_READ (2 << 28)
213 #define FEC_MMFR_OP_READ_C45 (3 << 28)
214 #define FEC_MMFR_OP_WRITE (1 << 28)
215 #define FEC_MMFR_OP_ADDR_WRITE (0)
216 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
217 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
218 #define FEC_MMFR_TA (2 << 16)
219 #define FEC_MMFR_DATA(v) (v & 0xffff)
220 /* FEC ECR bits definition */
221 #define FEC_ECR_MAGICEN (1 << 2)
222 #define FEC_ECR_SLEEP (1 << 3)
224 #define FEC_MII_TIMEOUT 30000 /* us */
226 /* Transmitter timeout */
227 #define TX_TIMEOUT (2 * HZ)
229 #define FEC_PAUSE_FLAG_AUTONEG 0x1
230 #define FEC_PAUSE_FLAG_ENABLE 0x2
231 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
232 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
233 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
235 #define COPYBREAK_DEFAULT 256
237 /* Max number of allowed TCP segments for software TSO */
238 #define FEC_MAX_TSO_SEGS 100
239 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
241 #define IS_TSO_HEADER(txq, addr) \
242 ((addr >= txq->tso_hdrs_dma) && \
243 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
247 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
248 struct bufdesc_prop *bd)
250 return (bdp >= bd->last) ? bd->base
251 : (struct bufdesc *)(((void *)bdp) + bd->dsize);
254 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
255 struct bufdesc_prop *bd)
257 return (bdp <= bd->base) ? bd->last
258 : (struct bufdesc *)(((void *)bdp) - bd->dsize);
261 static int fec_enet_get_bd_index(struct bufdesc *bdp,
262 struct bufdesc_prop *bd)
264 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
267 static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
271 entries = (((const char *)txq->dirty_tx -
272 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
274 return entries >= 0 ? entries : entries + txq->bd.ring_size;
277 static void swap_buffer(void *bufaddr, int len)
280 unsigned int *buf = bufaddr;
282 for (i = 0; i < len; i += 4, buf++)
286 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
289 unsigned int *src = src_buf;
290 unsigned int *dst = dst_buf;
292 for (i = 0; i < len; i += 4, src++, dst++)
296 static void fec_dump(struct net_device *ndev)
298 struct fec_enet_private *fep = netdev_priv(ndev);
300 struct fec_enet_priv_tx_q *txq;
303 netdev_info(ndev, "TX ring dump\n");
304 pr_info("Nr SC addr len SKB\n");
306 txq = fep->tx_queue[0];
310 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
312 bdp == txq->bd.cur ? 'S' : ' ',
313 bdp == txq->dirty_tx ? 'H' : ' ',
314 fec16_to_cpu(bdp->cbd_sc),
315 fec32_to_cpu(bdp->cbd_bufaddr),
316 fec16_to_cpu(bdp->cbd_datlen),
317 txq->tx_skbuff[index]);
318 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
320 } while (bdp != txq->bd.base);
323 static inline bool is_ipv4_pkt(struct sk_buff *skb)
325 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
329 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
331 /* Only run for packets requiring a checksum. */
332 if (skb->ip_summed != CHECKSUM_PARTIAL)
335 if (unlikely(skb_cow_head(skb, 0)))
338 if (is_ipv4_pkt(skb))
339 ip_hdr(skb)->check = 0;
340 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
345 static struct bufdesc *
346 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
348 struct net_device *ndev)
350 struct fec_enet_private *fep = netdev_priv(ndev);
351 struct bufdesc *bdp = txq->bd.cur;
352 struct bufdesc_ex *ebdp;
353 int nr_frags = skb_shinfo(skb)->nr_frags;
355 unsigned short status;
356 unsigned int estatus = 0;
357 skb_frag_t *this_frag;
363 for (frag = 0; frag < nr_frags; frag++) {
364 this_frag = &skb_shinfo(skb)->frags[frag];
365 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
366 ebdp = (struct bufdesc_ex *)bdp;
368 status = fec16_to_cpu(bdp->cbd_sc);
369 status &= ~BD_ENET_TX_STATS;
370 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
371 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]);
373 /* Handle the last BD specially */
374 if (frag == nr_frags - 1) {
375 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
376 if (fep->bufdesc_ex) {
377 estatus |= BD_ENET_TX_INT;
378 if (unlikely(skb_shinfo(skb)->tx_flags &
379 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
380 estatus |= BD_ENET_TX_TS;
384 if (fep->bufdesc_ex) {
385 if (fep->quirks & FEC_QUIRK_HAS_AVB)
386 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
387 if (skb->ip_summed == CHECKSUM_PARTIAL)
388 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
390 ebdp->cbd_esc = cpu_to_fec32(estatus);
393 bufaddr = skb_frag_address(this_frag);
395 index = fec_enet_get_bd_index(bdp, &txq->bd);
396 if (((unsigned long) bufaddr) & fep->tx_align ||
397 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
398 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
399 bufaddr = txq->tx_bounce[index];
401 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
402 swap_buffer(bufaddr, frag_len);
405 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
407 if (dma_mapping_error(&fep->pdev->dev, addr)) {
409 netdev_err(ndev, "Tx DMA memory map failed\n");
410 goto dma_mapping_error;
413 bdp->cbd_bufaddr = cpu_to_fec32(addr);
414 bdp->cbd_datlen = cpu_to_fec16(frag_len);
415 /* Make sure the updates to rest of the descriptor are
416 * performed before transferring ownership.
419 bdp->cbd_sc = cpu_to_fec16(status);
425 for (i = 0; i < frag; i++) {
426 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
427 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
428 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
430 return ERR_PTR(-ENOMEM);
433 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
434 struct sk_buff *skb, struct net_device *ndev)
436 struct fec_enet_private *fep = netdev_priv(ndev);
437 int nr_frags = skb_shinfo(skb)->nr_frags;
438 struct bufdesc *bdp, *last_bdp;
441 unsigned short status;
442 unsigned short buflen;
443 unsigned int estatus = 0;
447 entries_free = fec_enet_get_free_txdesc_num(txq);
448 if (entries_free < MAX_SKB_FRAGS + 1) {
449 dev_kfree_skb_any(skb);
451 netdev_err(ndev, "NOT enough BD for SG!\n");
455 /* Protocol checksum off-load for TCP and UDP. */
456 if (fec_enet_clear_csum(skb, ndev)) {
457 dev_kfree_skb_any(skb);
461 /* Fill in a Tx ring entry */
464 status = fec16_to_cpu(bdp->cbd_sc);
465 status &= ~BD_ENET_TX_STATS;
467 /* Set buffer length and buffer pointer */
469 buflen = skb_headlen(skb);
471 index = fec_enet_get_bd_index(bdp, &txq->bd);
472 if (((unsigned long) bufaddr) & fep->tx_align ||
473 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
474 memcpy(txq->tx_bounce[index], skb->data, buflen);
475 bufaddr = txq->tx_bounce[index];
477 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
478 swap_buffer(bufaddr, buflen);
481 /* Push the data cache so the CPM does not get stale memory data. */
482 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
483 if (dma_mapping_error(&fep->pdev->dev, addr)) {
484 dev_kfree_skb_any(skb);
486 netdev_err(ndev, "Tx DMA memory map failed\n");
491 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
492 if (IS_ERR(last_bdp)) {
493 dma_unmap_single(&fep->pdev->dev, addr,
494 buflen, DMA_TO_DEVICE);
495 dev_kfree_skb_any(skb);
499 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
500 if (fep->bufdesc_ex) {
501 estatus = BD_ENET_TX_INT;
502 if (unlikely(skb_shinfo(skb)->tx_flags &
503 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
504 estatus |= BD_ENET_TX_TS;
507 bdp->cbd_bufaddr = cpu_to_fec32(addr);
508 bdp->cbd_datlen = cpu_to_fec16(buflen);
510 if (fep->bufdesc_ex) {
512 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
514 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
516 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
518 if (fep->quirks & FEC_QUIRK_HAS_AVB)
519 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
521 if (skb->ip_summed == CHECKSUM_PARTIAL)
522 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
525 ebdp->cbd_esc = cpu_to_fec32(estatus);
528 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
529 /* Save skb pointer */
530 txq->tx_skbuff[index] = skb;
532 /* Make sure the updates to rest of the descriptor are performed before
533 * transferring ownership.
537 /* Send it on its way. Tell FEC it's ready, interrupt when done,
538 * it's the last BD of the frame, and to put the CRC on the end.
540 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
541 bdp->cbd_sc = cpu_to_fec16(status);
543 /* If this was the last BD in the ring, start at the beginning again. */
544 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
546 skb_tx_timestamp(skb);
548 /* Make sure the update to bdp and tx_skbuff are performed before
554 /* Trigger transmission start */
555 writel(0, txq->bd.reg_desc_active);
561 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
562 struct net_device *ndev,
563 struct bufdesc *bdp, int index, char *data,
564 int size, bool last_tcp, bool is_last)
566 struct fec_enet_private *fep = netdev_priv(ndev);
567 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
568 unsigned short status;
569 unsigned int estatus = 0;
572 status = fec16_to_cpu(bdp->cbd_sc);
573 status &= ~BD_ENET_TX_STATS;
575 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
577 if (((unsigned long) data) & fep->tx_align ||
578 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
579 memcpy(txq->tx_bounce[index], data, size);
580 data = txq->tx_bounce[index];
582 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
583 swap_buffer(data, size);
586 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
587 if (dma_mapping_error(&fep->pdev->dev, addr)) {
588 dev_kfree_skb_any(skb);
590 netdev_err(ndev, "Tx DMA memory map failed\n");
591 return NETDEV_TX_BUSY;
594 bdp->cbd_datlen = cpu_to_fec16(size);
595 bdp->cbd_bufaddr = cpu_to_fec32(addr);
597 if (fep->bufdesc_ex) {
598 if (fep->quirks & FEC_QUIRK_HAS_AVB)
599 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
600 if (skb->ip_summed == CHECKSUM_PARTIAL)
601 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
603 ebdp->cbd_esc = cpu_to_fec32(estatus);
606 /* Handle the last BD specially */
608 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
610 status |= BD_ENET_TX_INTR;
612 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
615 bdp->cbd_sc = cpu_to_fec16(status);
621 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
622 struct sk_buff *skb, struct net_device *ndev,
623 struct bufdesc *bdp, int index)
625 struct fec_enet_private *fep = netdev_priv(ndev);
626 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
627 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
629 unsigned long dmabuf;
630 unsigned short status;
631 unsigned int estatus = 0;
633 status = fec16_to_cpu(bdp->cbd_sc);
634 status &= ~BD_ENET_TX_STATS;
635 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
637 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
638 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
639 if (((unsigned long)bufaddr) & fep->tx_align ||
640 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
641 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
642 bufaddr = txq->tx_bounce[index];
644 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
645 swap_buffer(bufaddr, hdr_len);
647 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
648 hdr_len, DMA_TO_DEVICE);
649 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
650 dev_kfree_skb_any(skb);
652 netdev_err(ndev, "Tx DMA memory map failed\n");
653 return NETDEV_TX_BUSY;
657 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
658 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
660 if (fep->bufdesc_ex) {
661 if (fep->quirks & FEC_QUIRK_HAS_AVB)
662 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
663 if (skb->ip_summed == CHECKSUM_PARTIAL)
664 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
666 ebdp->cbd_esc = cpu_to_fec32(estatus);
669 bdp->cbd_sc = cpu_to_fec16(status);
674 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
676 struct net_device *ndev)
678 struct fec_enet_private *fep = netdev_priv(ndev);
679 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
680 int total_len, data_left;
681 struct bufdesc *bdp = txq->bd.cur;
683 unsigned int index = 0;
686 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
687 dev_kfree_skb_any(skb);
689 netdev_err(ndev, "NOT enough BD for TSO!\n");
693 /* Protocol checksum off-load for TCP and UDP. */
694 if (fec_enet_clear_csum(skb, ndev)) {
695 dev_kfree_skb_any(skb);
699 /* Initialize the TSO handler, and prepare the first payload */
700 tso_start(skb, &tso);
702 total_len = skb->len - hdr_len;
703 while (total_len > 0) {
706 index = fec_enet_get_bd_index(bdp, &txq->bd);
707 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
708 total_len -= data_left;
710 /* prepare packet headers: MAC + IP + TCP */
711 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
712 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
713 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
717 while (data_left > 0) {
720 size = min_t(int, tso.size, data_left);
721 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
722 index = fec_enet_get_bd_index(bdp, &txq->bd);
723 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
732 tso_build_data(skb, &tso, size);
735 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
738 /* Save skb pointer */
739 txq->tx_skbuff[index] = skb;
741 skb_tx_timestamp(skb);
744 /* Trigger transmission start */
745 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
746 !readl(txq->bd.reg_desc_active) ||
747 !readl(txq->bd.reg_desc_active) ||
748 !readl(txq->bd.reg_desc_active) ||
749 !readl(txq->bd.reg_desc_active))
750 writel(0, txq->bd.reg_desc_active);
755 /* TODO: Release all used data descriptors for TSO */
760 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
762 struct fec_enet_private *fep = netdev_priv(ndev);
764 unsigned short queue;
765 struct fec_enet_priv_tx_q *txq;
766 struct netdev_queue *nq;
769 queue = skb_get_queue_mapping(skb);
770 txq = fep->tx_queue[queue];
771 nq = netdev_get_tx_queue(ndev, queue);
774 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
776 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
780 entries_free = fec_enet_get_free_txdesc_num(txq);
781 if (entries_free <= txq->tx_stop_threshold)
782 netif_tx_stop_queue(nq);
787 /* Init RX & TX buffer descriptors
789 static void fec_enet_bd_init(struct net_device *dev)
791 struct fec_enet_private *fep = netdev_priv(dev);
792 struct fec_enet_priv_tx_q *txq;
793 struct fec_enet_priv_rx_q *rxq;
798 for (q = 0; q < fep->num_rx_queues; q++) {
799 /* Initialize the receive buffer descriptors. */
800 rxq = fep->rx_queue[q];
803 for (i = 0; i < rxq->bd.ring_size; i++) {
805 /* Initialize the BD for every fragment in the page. */
806 if (bdp->cbd_bufaddr)
807 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
809 bdp->cbd_sc = cpu_to_fec16(0);
810 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
813 /* Set the last buffer to wrap */
814 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
815 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
817 rxq->bd.cur = rxq->bd.base;
820 for (q = 0; q < fep->num_tx_queues; q++) {
821 /* ...and the same for transmit */
822 txq = fep->tx_queue[q];
826 for (i = 0; i < txq->bd.ring_size; i++) {
827 /* Initialize the BD for every fragment in the page. */
828 bdp->cbd_sc = cpu_to_fec16(0);
829 if (bdp->cbd_bufaddr &&
830 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
831 dma_unmap_single(&fep->pdev->dev,
832 fec32_to_cpu(bdp->cbd_bufaddr),
833 fec16_to_cpu(bdp->cbd_datlen),
835 if (txq->tx_skbuff[i]) {
836 dev_kfree_skb_any(txq->tx_skbuff[i]);
837 txq->tx_skbuff[i] = NULL;
839 bdp->cbd_bufaddr = cpu_to_fec32(0);
840 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
843 /* Set the last buffer to wrap */
844 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
845 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
850 static void fec_enet_active_rxring(struct net_device *ndev)
852 struct fec_enet_private *fep = netdev_priv(ndev);
855 for (i = 0; i < fep->num_rx_queues; i++)
856 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
859 static void fec_enet_enable_ring(struct net_device *ndev)
861 struct fec_enet_private *fep = netdev_priv(ndev);
862 struct fec_enet_priv_tx_q *txq;
863 struct fec_enet_priv_rx_q *rxq;
866 for (i = 0; i < fep->num_rx_queues; i++) {
867 rxq = fep->rx_queue[i];
868 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
869 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
873 writel(RCMR_MATCHEN | RCMR_CMP(i),
874 fep->hwp + FEC_RCMR(i));
877 for (i = 0; i < fep->num_tx_queues; i++) {
878 txq = fep->tx_queue[i];
879 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
883 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
884 fep->hwp + FEC_DMA_CFG(i));
888 static void fec_enet_reset_skb(struct net_device *ndev)
890 struct fec_enet_private *fep = netdev_priv(ndev);
891 struct fec_enet_priv_tx_q *txq;
894 for (i = 0; i < fep->num_tx_queues; i++) {
895 txq = fep->tx_queue[i];
897 for (j = 0; j < txq->bd.ring_size; j++) {
898 if (txq->tx_skbuff[j]) {
899 dev_kfree_skb_any(txq->tx_skbuff[j]);
900 txq->tx_skbuff[j] = NULL;
907 * This function is called to start or restart the FEC during a link
908 * change, transmit timeout, or to reconfigure the FEC. The network
909 * packet processing for this device must be stopped before this call.
912 fec_restart(struct net_device *ndev)
914 struct fec_enet_private *fep = netdev_priv(ndev);
917 u32 rcntl = OPT_FRAME_SIZE | 0x04;
918 u32 ecntl = 0x2; /* ETHEREN */
920 /* Whack a reset. We should wait for this.
921 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
922 * instead of reset MAC itself.
924 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
925 writel(0, fep->hwp + FEC_ECNTRL);
927 writel(1, fep->hwp + FEC_ECNTRL);
932 * enet-mac reset will reset mac address registers too,
933 * so need to reconfigure it.
935 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
936 writel((__force u32)cpu_to_be32(temp_mac[0]),
937 fep->hwp + FEC_ADDR_LOW);
938 writel((__force u32)cpu_to_be32(temp_mac[1]),
939 fep->hwp + FEC_ADDR_HIGH);
941 /* Clear any outstanding interrupt. */
942 writel(0xffffffff, fep->hwp + FEC_IEVENT);
944 fec_enet_bd_init(ndev);
946 fec_enet_enable_ring(ndev);
948 /* Reset tx SKB buffers. */
949 fec_enet_reset_skb(ndev);
951 /* Enable MII mode */
952 if (fep->full_duplex == DUPLEX_FULL) {
954 writel(0x04, fep->hwp + FEC_X_CNTRL);
958 writel(0x0, fep->hwp + FEC_X_CNTRL);
962 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
964 #if !defined(CONFIG_M5272)
965 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
966 val = readl(fep->hwp + FEC_RACC);
967 /* align IP header */
968 val |= FEC_RACC_SHIFT16;
969 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
970 /* set RX checksum */
971 val |= FEC_RACC_OPTIONS;
973 val &= ~FEC_RACC_OPTIONS;
974 writel(val, fep->hwp + FEC_RACC);
975 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
980 * The phy interface and speed need to get configured
981 * differently on enet-mac.
983 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
984 /* Enable flow control and length check */
985 rcntl |= 0x40000000 | 0x00000020;
987 /* RGMII, RMII or MII */
988 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
989 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
990 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
991 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
993 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
998 /* 1G, 100M or 10M */
1000 if (ndev->phydev->speed == SPEED_1000)
1002 else if (ndev->phydev->speed == SPEED_100)
1008 #ifdef FEC_MIIGSK_ENR
1009 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1011 /* disable the gasket and wait */
1012 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1013 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1017 * configure the gasket:
1018 * RMII, 50 MHz, no loopback, no echo
1019 * MII, 25 MHz, no loopback, no echo
1021 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1022 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1023 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1024 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1025 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1027 /* re-enable the gasket */
1028 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1033 #if !defined(CONFIG_M5272)
1034 /* enable pause frame*/
1035 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1036 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1037 ndev->phydev && ndev->phydev->pause)) {
1038 rcntl |= FEC_ENET_FCE;
1040 /* set FIFO threshold parameter to reduce overrun */
1041 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1042 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1043 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1044 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1047 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1049 rcntl &= ~FEC_ENET_FCE;
1051 #endif /* !defined(CONFIG_M5272) */
1053 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1055 /* Setup multicast filter. */
1056 set_multicast_list(ndev);
1057 #ifndef CONFIG_M5272
1058 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1059 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1062 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1063 /* enable ENET endian swap */
1065 /* enable ENET store and forward mode */
1066 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1069 if (fep->bufdesc_ex)
1072 #ifndef CONFIG_M5272
1073 /* Enable the MIB statistic event counters */
1074 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1077 /* And last, enable the transmit and receive processing */
1078 writel(ecntl, fep->hwp + FEC_ECNTRL);
1079 fec_enet_active_rxring(ndev);
1081 if (fep->bufdesc_ex)
1082 fec_ptp_start_cyclecounter(ndev);
1084 /* Enable interrupts we wish to service */
1086 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1088 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1090 /* Init the interrupt coalescing */
1091 fec_enet_itr_coal_init(ndev);
1096 fec_stop(struct net_device *ndev)
1098 struct fec_enet_private *fep = netdev_priv(ndev);
1099 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1100 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1103 /* We cannot expect a graceful transmit stop without link !!! */
1105 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1107 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1108 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1111 /* Whack a reset. We should wait for this.
1112 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1113 * instead of reset MAC itself.
1115 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1116 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1117 writel(0, fep->hwp + FEC_ECNTRL);
1119 writel(1, fep->hwp + FEC_ECNTRL);
1122 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1124 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1125 val = readl(fep->hwp + FEC_ECNTRL);
1126 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1127 writel(val, fep->hwp + FEC_ECNTRL);
1129 if (pdata && pdata->sleep_mode_enable)
1130 pdata->sleep_mode_enable(true);
1132 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1134 /* We have to keep ENET enabled to have MII interrupt stay working */
1135 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1136 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1137 writel(2, fep->hwp + FEC_ECNTRL);
1138 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1144 fec_timeout(struct net_device *ndev, unsigned int txqueue)
1146 struct fec_enet_private *fep = netdev_priv(ndev);
1150 ndev->stats.tx_errors++;
1152 schedule_work(&fep->tx_timeout_work);
1155 static void fec_enet_timeout_work(struct work_struct *work)
1157 struct fec_enet_private *fep =
1158 container_of(work, struct fec_enet_private, tx_timeout_work);
1159 struct net_device *ndev = fep->netdev;
1162 if (netif_device_present(ndev) || netif_running(ndev)) {
1163 napi_disable(&fep->napi);
1164 netif_tx_lock_bh(ndev);
1166 netif_tx_wake_all_queues(ndev);
1167 netif_tx_unlock_bh(ndev);
1168 napi_enable(&fep->napi);
1174 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1175 struct skb_shared_hwtstamps *hwtstamps)
1177 unsigned long flags;
1180 spin_lock_irqsave(&fep->tmreg_lock, flags);
1181 ns = timecounter_cyc2time(&fep->tc, ts);
1182 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1184 memset(hwtstamps, 0, sizeof(*hwtstamps));
1185 hwtstamps->hwtstamp = ns_to_ktime(ns);
1189 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1191 struct fec_enet_private *fep;
1192 struct bufdesc *bdp;
1193 unsigned short status;
1194 struct sk_buff *skb;
1195 struct fec_enet_priv_tx_q *txq;
1196 struct netdev_queue *nq;
1200 fep = netdev_priv(ndev);
1202 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1204 txq = fep->tx_queue[queue_id];
1205 /* get next bdp of dirty_tx */
1206 nq = netdev_get_tx_queue(ndev, queue_id);
1207 bdp = txq->dirty_tx;
1209 /* get next bdp of dirty_tx */
1210 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1212 while (bdp != READ_ONCE(txq->bd.cur)) {
1213 /* Order the load of bd.cur and cbd_sc */
1215 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1216 if (status & BD_ENET_TX_READY)
1219 index = fec_enet_get_bd_index(bdp, &txq->bd);
1221 skb = txq->tx_skbuff[index];
1222 txq->tx_skbuff[index] = NULL;
1223 if (!IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1224 dma_unmap_single(&fep->pdev->dev,
1225 fec32_to_cpu(bdp->cbd_bufaddr),
1226 fec16_to_cpu(bdp->cbd_datlen),
1228 bdp->cbd_bufaddr = cpu_to_fec32(0);
1232 /* Check for errors. */
1233 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1234 BD_ENET_TX_RL | BD_ENET_TX_UN |
1236 ndev->stats.tx_errors++;
1237 if (status & BD_ENET_TX_HB) /* No heartbeat */
1238 ndev->stats.tx_heartbeat_errors++;
1239 if (status & BD_ENET_TX_LC) /* Late collision */
1240 ndev->stats.tx_window_errors++;
1241 if (status & BD_ENET_TX_RL) /* Retrans limit */
1242 ndev->stats.tx_aborted_errors++;
1243 if (status & BD_ENET_TX_UN) /* Underrun */
1244 ndev->stats.tx_fifo_errors++;
1245 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1246 ndev->stats.tx_carrier_errors++;
1248 ndev->stats.tx_packets++;
1249 ndev->stats.tx_bytes += skb->len;
1252 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1254 struct skb_shared_hwtstamps shhwtstamps;
1255 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1257 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1258 skb_tstamp_tx(skb, &shhwtstamps);
1261 /* Deferred means some collisions occurred during transmit,
1262 * but we eventually sent the packet OK.
1264 if (status & BD_ENET_TX_DEF)
1265 ndev->stats.collisions++;
1267 /* Free the sk buffer associated with this last transmit */
1268 dev_kfree_skb_any(skb);
1270 /* Make sure the update to bdp and tx_skbuff are performed
1274 txq->dirty_tx = bdp;
1276 /* Update pointer to next buffer descriptor to be transmitted */
1277 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1279 /* Since we have freed up a buffer, the ring is no longer full
1281 if (netif_tx_queue_stopped(nq)) {
1282 entries_free = fec_enet_get_free_txdesc_num(txq);
1283 if (entries_free >= txq->tx_wake_threshold)
1284 netif_tx_wake_queue(nq);
1288 /* ERR006358: Keep the transmitter going */
1289 if (bdp != txq->bd.cur &&
1290 readl(txq->bd.reg_desc_active) == 0)
1291 writel(0, txq->bd.reg_desc_active);
1295 fec_enet_tx(struct net_device *ndev)
1297 struct fec_enet_private *fep = netdev_priv(ndev);
1299 /* First process class A queue, then Class B and Best Effort queue */
1300 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1301 clear_bit(queue_id, &fep->work_tx);
1302 fec_enet_tx_queue(ndev, queue_id);
1308 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1310 struct fec_enet_private *fep = netdev_priv(ndev);
1313 off = ((unsigned long)skb->data) & fep->rx_align;
1315 skb_reserve(skb, fep->rx_align + 1 - off);
1317 bdp->cbd_bufaddr = cpu_to_fec32(dma_map_single(&fep->pdev->dev, skb->data, FEC_ENET_RX_FRSIZE - fep->rx_align, DMA_FROM_DEVICE));
1318 if (dma_mapping_error(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr))) {
1319 if (net_ratelimit())
1320 netdev_err(ndev, "Rx DMA memory map failed\n");
1327 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1328 struct bufdesc *bdp, u32 length, bool swap)
1330 struct fec_enet_private *fep = netdev_priv(ndev);
1331 struct sk_buff *new_skb;
1333 if (length > fep->rx_copybreak)
1336 new_skb = netdev_alloc_skb(ndev, length);
1340 dma_sync_single_for_cpu(&fep->pdev->dev,
1341 fec32_to_cpu(bdp->cbd_bufaddr),
1342 FEC_ENET_RX_FRSIZE - fep->rx_align,
1345 memcpy(new_skb->data, (*skb)->data, length);
1347 swap_buffer2(new_skb->data, (*skb)->data, length);
1353 /* During a receive, the bd_rx.cur points to the current incoming buffer.
1354 * When we update through the ring, if the next incoming buffer has
1355 * not been given to the system, we just set the empty indicator,
1356 * effectively tossing the packet.
1359 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1361 struct fec_enet_private *fep = netdev_priv(ndev);
1362 struct fec_enet_priv_rx_q *rxq;
1363 struct bufdesc *bdp;
1364 unsigned short status;
1365 struct sk_buff *skb_new = NULL;
1366 struct sk_buff *skb;
1369 int pkt_received = 0;
1370 struct bufdesc_ex *ebdp = NULL;
1371 bool vlan_packet_rcvd = false;
1375 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1380 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1381 rxq = fep->rx_queue[queue_id];
1383 /* First, grab all of the stats for the incoming packet.
1384 * These get messed up if we get called due to a busy condition.
1388 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1390 if (pkt_received >= budget)
1394 writel(FEC_ENET_RXF, fep->hwp + FEC_IEVENT);
1396 /* Check for errors. */
1397 status ^= BD_ENET_RX_LAST;
1398 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1399 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1401 ndev->stats.rx_errors++;
1402 if (status & BD_ENET_RX_OV) {
1404 ndev->stats.rx_fifo_errors++;
1405 goto rx_processing_done;
1407 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1408 | BD_ENET_RX_LAST)) {
1409 /* Frame too long or too short. */
1410 ndev->stats.rx_length_errors++;
1411 if (status & BD_ENET_RX_LAST)
1412 netdev_err(ndev, "rcv is not +last\n");
1414 if (status & BD_ENET_RX_CR) /* CRC Error */
1415 ndev->stats.rx_crc_errors++;
1416 /* Report late collisions as a frame error. */
1417 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1418 ndev->stats.rx_frame_errors++;
1419 goto rx_processing_done;
1422 /* Process the incoming frame. */
1423 ndev->stats.rx_packets++;
1424 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1425 ndev->stats.rx_bytes += pkt_len;
1427 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1428 skb = rxq->rx_skbuff[index];
1430 /* The packet length includes FCS, but we don't want to
1431 * include that when passing upstream as it messes up
1432 * bridging applications.
1434 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1436 if (!is_copybreak) {
1437 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1438 if (unlikely(!skb_new)) {
1439 ndev->stats.rx_dropped++;
1440 goto rx_processing_done;
1442 dma_unmap_single(&fep->pdev->dev,
1443 fec32_to_cpu(bdp->cbd_bufaddr),
1444 FEC_ENET_RX_FRSIZE - fep->rx_align,
1448 prefetch(skb->data - NET_IP_ALIGN);
1449 skb_put(skb, pkt_len - 4);
1452 if (!is_copybreak && need_swap)
1453 swap_buffer(data, pkt_len);
1455 #if !defined(CONFIG_M5272)
1456 if (fep->quirks & FEC_QUIRK_HAS_RACC)
1457 data = skb_pull_inline(skb, 2);
1460 /* Extract the enhanced buffer descriptor */
1462 if (fep->bufdesc_ex)
1463 ebdp = (struct bufdesc_ex *)bdp;
1465 /* If this is a VLAN packet remove the VLAN Tag */
1466 vlan_packet_rcvd = false;
1467 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1469 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1470 /* Push and remove the vlan tag */
1471 struct vlan_hdr *vlan_header =
1472 (struct vlan_hdr *) (data + ETH_HLEN);
1473 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1475 vlan_packet_rcvd = true;
1477 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1478 skb_pull(skb, VLAN_HLEN);
1481 skb->protocol = eth_type_trans(skb, ndev);
1483 /* Get receive timestamp from the skb */
1484 if (fep->hwts_rx_en && fep->bufdesc_ex)
1485 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1486 skb_hwtstamps(skb));
1488 if (fep->bufdesc_ex &&
1489 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1490 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1491 /* don't check it */
1492 skb->ip_summed = CHECKSUM_UNNECESSARY;
1494 skb_checksum_none_assert(skb);
1498 /* Handle received VLAN packets */
1499 if (vlan_packet_rcvd)
1500 __vlan_hwaccel_put_tag(skb,
1504 napi_gro_receive(&fep->napi, skb);
1507 dma_sync_single_for_device(&fep->pdev->dev,
1508 fec32_to_cpu(bdp->cbd_bufaddr),
1509 FEC_ENET_RX_FRSIZE - fep->rx_align,
1512 rxq->rx_skbuff[index] = skb_new;
1513 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1517 /* Clear the status flags for this buffer */
1518 status &= ~BD_ENET_RX_STATS;
1520 /* Mark the buffer empty */
1521 status |= BD_ENET_RX_EMPTY;
1523 if (fep->bufdesc_ex) {
1524 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1526 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1530 /* Make sure the updates to rest of the descriptor are
1531 * performed before transferring ownership.
1534 bdp->cbd_sc = cpu_to_fec16(status);
1536 /* Update BD pointer to next entry */
1537 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1539 /* Doing this here will keep the FEC running while we process
1540 * incoming frames. On a heavily loaded network, we should be
1541 * able to keep up at the expense of system resources.
1543 writel(0, rxq->bd.reg_desc_active);
1546 return pkt_received;
1550 fec_enet_rx(struct net_device *ndev, int budget)
1552 int pkt_received = 0;
1554 struct fec_enet_private *fep = netdev_priv(ndev);
1556 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1559 ret = fec_enet_rx_queue(ndev,
1560 budget - pkt_received, queue_id);
1562 if (ret < budget - pkt_received)
1563 clear_bit(queue_id, &fep->work_rx);
1565 pkt_received += ret;
1567 return pkt_received;
1571 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1573 if (int_events == 0)
1576 if (int_events & FEC_ENET_RXF_0)
1577 fep->work_rx |= (1 << 2);
1578 if (int_events & FEC_ENET_RXF_1)
1579 fep->work_rx |= (1 << 0);
1580 if (int_events & FEC_ENET_RXF_2)
1581 fep->work_rx |= (1 << 1);
1583 if (int_events & FEC_ENET_TXF_0)
1584 fep->work_tx |= (1 << 2);
1585 if (int_events & FEC_ENET_TXF_1)
1586 fep->work_tx |= (1 << 0);
1587 if (int_events & FEC_ENET_TXF_2)
1588 fep->work_tx |= (1 << 1);
1594 fec_enet_interrupt(int irq, void *dev_id)
1596 struct net_device *ndev = dev_id;
1597 struct fec_enet_private *fep = netdev_priv(ndev);
1599 irqreturn_t ret = IRQ_NONE;
1601 int_events = readl(fep->hwp + FEC_IEVENT);
1602 writel(int_events, fep->hwp + FEC_IEVENT);
1603 fec_enet_collect_events(fep, int_events);
1605 if ((fep->work_tx || fep->work_rx) && fep->link) {
1608 if (napi_schedule_prep(&fep->napi)) {
1609 /* Disable the NAPI interrupts */
1610 writel(FEC_NAPI_IMASK, fep->hwp + FEC_IMASK);
1611 __napi_schedule(&fep->napi);
1615 if (int_events & FEC_ENET_MII) {
1617 complete(&fep->mdio_done);
1622 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1624 struct net_device *ndev = napi->dev;
1625 struct fec_enet_private *fep = netdev_priv(ndev);
1628 pkts = fec_enet_rx(ndev, budget);
1632 if (pkts < budget) {
1633 napi_complete_done(napi, pkts);
1634 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1639 /* ------------------------------------------------------------------------- */
1640 static void fec_get_mac(struct net_device *ndev)
1642 struct fec_enet_private *fep = netdev_priv(ndev);
1643 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1644 unsigned char *iap, tmpaddr[ETH_ALEN];
1647 * try to get mac address in following order:
1649 * 1) module parameter via kernel command line in form
1650 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1655 * 2) from device tree data
1657 if (!is_valid_ether_addr(iap)) {
1658 struct device_node *np = fep->pdev->dev.of_node;
1660 const char *mac = of_get_mac_address(np);
1662 iap = (unsigned char *) mac;
1667 * 3) from flash or fuse (via platform data)
1669 if (!is_valid_ether_addr(iap)) {
1672 iap = (unsigned char *)FEC_FLASHMAC;
1675 iap = (unsigned char *)&pdata->mac;
1680 * 4) FEC mac registers set by bootloader
1682 if (!is_valid_ether_addr(iap)) {
1683 *((__be32 *) &tmpaddr[0]) =
1684 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1685 *((__be16 *) &tmpaddr[4]) =
1686 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1691 * 5) random mac address
1693 if (!is_valid_ether_addr(iap)) {
1694 /* Report it and use a random ethernet address instead */
1695 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap);
1696 eth_hw_addr_random(ndev);
1697 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n",
1702 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1704 /* Adjust MAC if using macaddr */
1706 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1709 /* ------------------------------------------------------------------------- */
1714 static void fec_enet_adjust_link(struct net_device *ndev)
1716 struct fec_enet_private *fep = netdev_priv(ndev);
1717 struct phy_device *phy_dev = ndev->phydev;
1718 int status_change = 0;
1721 * If the netdev is down, or is going down, we're not interested
1722 * in link state events, so just mark our idea of the link as down
1723 * and ignore the event.
1725 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1727 } else if (phy_dev->link) {
1729 fep->link = phy_dev->link;
1733 if (fep->full_duplex != phy_dev->duplex) {
1734 fep->full_duplex = phy_dev->duplex;
1738 if (phy_dev->speed != fep->speed) {
1739 fep->speed = phy_dev->speed;
1743 /* if any of the above changed restart the FEC */
1744 if (status_change) {
1745 napi_disable(&fep->napi);
1746 netif_tx_lock_bh(ndev);
1748 netif_tx_wake_all_queues(ndev);
1749 netif_tx_unlock_bh(ndev);
1750 napi_enable(&fep->napi);
1754 napi_disable(&fep->napi);
1755 netif_tx_lock_bh(ndev);
1757 netif_tx_unlock_bh(ndev);
1758 napi_enable(&fep->napi);
1759 fep->link = phy_dev->link;
1765 phy_print_status(phy_dev);
1768 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1770 struct fec_enet_private *fep = bus->priv;
1771 struct device *dev = &fep->pdev->dev;
1772 unsigned long time_left;
1773 int ret = 0, frame_start, frame_addr, frame_op;
1774 bool is_c45 = !!(regnum & MII_ADDR_C45);
1776 ret = pm_runtime_get_sync(dev);
1780 reinit_completion(&fep->mdio_done);
1783 frame_start = FEC_MMFR_ST_C45;
1786 frame_addr = (regnum >> 16);
1787 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
1788 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1789 FEC_MMFR_TA | (regnum & 0xFFFF),
1790 fep->hwp + FEC_MII_DATA);
1792 /* wait for end of transfer */
1793 time_left = wait_for_completion_timeout(&fep->mdio_done,
1794 usecs_to_jiffies(FEC_MII_TIMEOUT));
1795 if (time_left == 0) {
1796 netdev_err(fep->netdev, "MDIO address write timeout\n");
1801 frame_op = FEC_MMFR_OP_READ_C45;
1805 frame_op = FEC_MMFR_OP_READ;
1806 frame_start = FEC_MMFR_ST;
1807 frame_addr = regnum;
1810 /* start a read op */
1811 writel(frame_start | frame_op |
1812 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1813 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1815 /* wait for end of transfer */
1816 time_left = wait_for_completion_timeout(&fep->mdio_done,
1817 usecs_to_jiffies(FEC_MII_TIMEOUT));
1818 if (time_left == 0) {
1819 netdev_err(fep->netdev, "MDIO read timeout\n");
1824 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1827 pm_runtime_mark_last_busy(dev);
1828 pm_runtime_put_autosuspend(dev);
1833 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1836 struct fec_enet_private *fep = bus->priv;
1837 struct device *dev = &fep->pdev->dev;
1838 unsigned long time_left;
1839 int ret, frame_start, frame_addr;
1840 bool is_c45 = !!(regnum & MII_ADDR_C45);
1842 ret = pm_runtime_get_sync(dev);
1848 reinit_completion(&fep->mdio_done);
1851 frame_start = FEC_MMFR_ST_C45;
1854 frame_addr = (regnum >> 16);
1855 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
1856 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1857 FEC_MMFR_TA | (regnum & 0xFFFF),
1858 fep->hwp + FEC_MII_DATA);
1860 /* wait for end of transfer */
1861 time_left = wait_for_completion_timeout(&fep->mdio_done,
1862 usecs_to_jiffies(FEC_MII_TIMEOUT));
1863 if (time_left == 0) {
1864 netdev_err(fep->netdev, "MDIO address write timeout\n");
1870 frame_start = FEC_MMFR_ST;
1871 frame_addr = regnum;
1874 /* start a write op */
1875 writel(frame_start | FEC_MMFR_OP_WRITE |
1876 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
1877 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1878 fep->hwp + FEC_MII_DATA);
1880 /* wait for end of transfer */
1881 time_left = wait_for_completion_timeout(&fep->mdio_done,
1882 usecs_to_jiffies(FEC_MII_TIMEOUT));
1883 if (time_left == 0) {
1884 netdev_err(fep->netdev, "MDIO write timeout\n");
1889 pm_runtime_mark_last_busy(dev);
1890 pm_runtime_put_autosuspend(dev);
1895 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1897 struct fec_enet_private *fep = netdev_priv(ndev);
1901 ret = clk_prepare_enable(fep->clk_enet_out);
1906 mutex_lock(&fep->ptp_clk_mutex);
1907 ret = clk_prepare_enable(fep->clk_ptp);
1909 mutex_unlock(&fep->ptp_clk_mutex);
1910 goto failed_clk_ptp;
1912 fep->ptp_clk_on = true;
1914 mutex_unlock(&fep->ptp_clk_mutex);
1917 ret = clk_prepare_enable(fep->clk_ref);
1919 goto failed_clk_ref;
1921 phy_reset_after_clk_enable(ndev->phydev);
1923 clk_disable_unprepare(fep->clk_enet_out);
1925 mutex_lock(&fep->ptp_clk_mutex);
1926 clk_disable_unprepare(fep->clk_ptp);
1927 fep->ptp_clk_on = false;
1928 mutex_unlock(&fep->ptp_clk_mutex);
1930 clk_disable_unprepare(fep->clk_ref);
1937 clk_disable_unprepare(fep->clk_ref);
1939 if (fep->clk_enet_out)
1940 clk_disable_unprepare(fep->clk_enet_out);
1945 static int fec_enet_mii_probe(struct net_device *ndev)
1947 struct fec_enet_private *fep = netdev_priv(ndev);
1948 struct phy_device *phy_dev = NULL;
1949 char mdio_bus_id[MII_BUS_ID_SIZE];
1950 char phy_name[MII_BUS_ID_SIZE + 3];
1952 int dev_id = fep->dev_id;
1954 if (fep->phy_node) {
1955 phy_dev = of_phy_connect(ndev, fep->phy_node,
1956 &fec_enet_adjust_link, 0,
1957 fep->phy_interface);
1959 netdev_err(ndev, "Unable to connect to phy\n");
1963 /* check for attached phy */
1964 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1965 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
1969 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1973 if (phy_id >= PHY_MAX_ADDR) {
1974 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1975 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1979 snprintf(phy_name, sizeof(phy_name),
1980 PHY_ID_FMT, mdio_bus_id, phy_id);
1981 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1982 fep->phy_interface);
1985 if (IS_ERR(phy_dev)) {
1986 netdev_err(ndev, "could not attach to PHY\n");
1987 return PTR_ERR(phy_dev);
1990 /* mask with MAC supported features */
1991 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1992 phy_set_max_speed(phy_dev, 1000);
1993 phy_remove_link_mode(phy_dev,
1994 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
1995 #if !defined(CONFIG_M5272)
1996 phy_support_sym_pause(phy_dev);
2000 phy_set_max_speed(phy_dev, 100);
2003 fep->full_duplex = 0;
2005 phy_attached_info(phy_dev);
2010 static int fec_enet_mii_init(struct platform_device *pdev)
2012 static struct mii_bus *fec0_mii_bus;
2013 struct net_device *ndev = platform_get_drvdata(pdev);
2014 struct fec_enet_private *fep = netdev_priv(ndev);
2015 struct device_node *node;
2017 u32 mii_speed, holdtime;
2020 * The i.MX28 dual fec interfaces are not equal.
2021 * Here are the differences:
2023 * - fec0 supports MII & RMII modes while fec1 only supports RMII
2024 * - fec0 acts as the 1588 time master while fec1 is slave
2025 * - external phys can only be configured by fec0
2027 * That is to say fec1 can not work independently. It only works
2028 * when fec0 is working. The reason behind this design is that the
2029 * second interface is added primarily for Switch mode.
2031 * Because of the last point above, both phys are attached on fec0
2032 * mdio interface in board design, and need to be configured by
2035 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2036 /* fec1 uses fec0 mii_bus */
2037 if (mii_cnt && fec0_mii_bus) {
2038 fep->mii_bus = fec0_mii_bus;
2046 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
2048 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2049 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2050 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2053 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2054 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2056 if (mii_speed > 63) {
2058 "fec clock (%lu) too fast to get right mii speed\n",
2059 clk_get_rate(fep->clk_ipg));
2065 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2066 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2067 * versions are RAZ there, so just ignore the difference and write the
2069 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2070 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2072 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2073 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2074 * holdtime cannot result in a value greater than 3.
2076 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2078 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2080 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2082 fep->mii_bus = mdiobus_alloc();
2083 if (fep->mii_bus == NULL) {
2088 fep->mii_bus->name = "fec_enet_mii_bus";
2089 fep->mii_bus->read = fec_enet_mdio_read;
2090 fep->mii_bus->write = fec_enet_mdio_write;
2091 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2092 pdev->name, fep->dev_id + 1);
2093 fep->mii_bus->priv = fep;
2094 fep->mii_bus->parent = &pdev->dev;
2096 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2097 err = of_mdiobus_register(fep->mii_bus, node);
2100 goto err_out_free_mdiobus;
2104 /* save fec0 mii_bus */
2105 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2106 fec0_mii_bus = fep->mii_bus;
2110 err_out_free_mdiobus:
2111 mdiobus_free(fep->mii_bus);
2116 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2118 if (--mii_cnt == 0) {
2119 mdiobus_unregister(fep->mii_bus);
2120 mdiobus_free(fep->mii_bus);
2124 static void fec_enet_get_drvinfo(struct net_device *ndev,
2125 struct ethtool_drvinfo *info)
2127 struct fec_enet_private *fep = netdev_priv(ndev);
2129 strlcpy(info->driver, fep->pdev->dev.driver->name,
2130 sizeof(info->driver));
2131 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2132 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2135 static int fec_enet_get_regs_len(struct net_device *ndev)
2137 struct fec_enet_private *fep = netdev_priv(ndev);
2141 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2143 s = resource_size(r);
2148 /* List of registers that can be safety be read to dump them with ethtool */
2149 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2150 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2151 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2152 static __u32 fec_enet_register_version = 2;
2153 static u32 fec_enet_register_offset[] = {
2154 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2155 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2156 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2157 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2158 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2159 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2160 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2161 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2162 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2163 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2164 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2165 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2166 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2167 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2168 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2169 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2170 RMON_T_P_GTE2048, RMON_T_OCTETS,
2171 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2172 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2173 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2174 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2175 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2176 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2177 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2178 RMON_R_P_GTE2048, RMON_R_OCTETS,
2179 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2180 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2183 static __u32 fec_enet_register_version = 1;
2184 static u32 fec_enet_register_offset[] = {
2185 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2186 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2187 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2188 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2189 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2190 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2191 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2192 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2193 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2197 static void fec_enet_get_regs(struct net_device *ndev,
2198 struct ethtool_regs *regs, void *regbuf)
2200 struct fec_enet_private *fep = netdev_priv(ndev);
2201 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2202 struct device *dev = &fep->pdev->dev;
2203 u32 *buf = (u32 *)regbuf;
2207 ret = pm_runtime_get_sync(dev);
2211 regs->version = fec_enet_register_version;
2213 memset(buf, 0, regs->len);
2215 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) {
2216 off = fec_enet_register_offset[i];
2218 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2219 !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2223 buf[off] = readl(&theregs[off]);
2226 pm_runtime_mark_last_busy(dev);
2227 pm_runtime_put_autosuspend(dev);
2230 static int fec_enet_get_ts_info(struct net_device *ndev,
2231 struct ethtool_ts_info *info)
2233 struct fec_enet_private *fep = netdev_priv(ndev);
2235 if (fep->bufdesc_ex) {
2237 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2238 SOF_TIMESTAMPING_RX_SOFTWARE |
2239 SOF_TIMESTAMPING_SOFTWARE |
2240 SOF_TIMESTAMPING_TX_HARDWARE |
2241 SOF_TIMESTAMPING_RX_HARDWARE |
2242 SOF_TIMESTAMPING_RAW_HARDWARE;
2244 info->phc_index = ptp_clock_index(fep->ptp_clock);
2246 info->phc_index = -1;
2248 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2249 (1 << HWTSTAMP_TX_ON);
2251 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2252 (1 << HWTSTAMP_FILTER_ALL);
2255 return ethtool_op_get_ts_info(ndev, info);
2259 #if !defined(CONFIG_M5272)
2261 static void fec_enet_get_pauseparam(struct net_device *ndev,
2262 struct ethtool_pauseparam *pause)
2264 struct fec_enet_private *fep = netdev_priv(ndev);
2266 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2267 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2268 pause->rx_pause = pause->tx_pause;
2271 static int fec_enet_set_pauseparam(struct net_device *ndev,
2272 struct ethtool_pauseparam *pause)
2274 struct fec_enet_private *fep = netdev_priv(ndev);
2279 if (pause->tx_pause != pause->rx_pause) {
2281 "hardware only support enable/disable both tx and rx");
2285 fep->pause_flag = 0;
2287 /* tx pause must be same as rx pause */
2288 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2289 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2291 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause,
2294 if (pause->autoneg) {
2295 if (netif_running(ndev))
2297 phy_start_aneg(ndev->phydev);
2299 if (netif_running(ndev)) {
2300 napi_disable(&fep->napi);
2301 netif_tx_lock_bh(ndev);
2303 netif_tx_wake_all_queues(ndev);
2304 netif_tx_unlock_bh(ndev);
2305 napi_enable(&fep->napi);
2311 static const struct fec_stat {
2312 char name[ETH_GSTRING_LEN];
2316 { "tx_dropped", RMON_T_DROP },
2317 { "tx_packets", RMON_T_PACKETS },
2318 { "tx_broadcast", RMON_T_BC_PKT },
2319 { "tx_multicast", RMON_T_MC_PKT },
2320 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2321 { "tx_undersize", RMON_T_UNDERSIZE },
2322 { "tx_oversize", RMON_T_OVERSIZE },
2323 { "tx_fragment", RMON_T_FRAG },
2324 { "tx_jabber", RMON_T_JAB },
2325 { "tx_collision", RMON_T_COL },
2326 { "tx_64byte", RMON_T_P64 },
2327 { "tx_65to127byte", RMON_T_P65TO127 },
2328 { "tx_128to255byte", RMON_T_P128TO255 },
2329 { "tx_256to511byte", RMON_T_P256TO511 },
2330 { "tx_512to1023byte", RMON_T_P512TO1023 },
2331 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2332 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2333 { "tx_octets", RMON_T_OCTETS },
2336 { "IEEE_tx_drop", IEEE_T_DROP },
2337 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2338 { "IEEE_tx_1col", IEEE_T_1COL },
2339 { "IEEE_tx_mcol", IEEE_T_MCOL },
2340 { "IEEE_tx_def", IEEE_T_DEF },
2341 { "IEEE_tx_lcol", IEEE_T_LCOL },
2342 { "IEEE_tx_excol", IEEE_T_EXCOL },
2343 { "IEEE_tx_macerr", IEEE_T_MACERR },
2344 { "IEEE_tx_cserr", IEEE_T_CSERR },
2345 { "IEEE_tx_sqe", IEEE_T_SQE },
2346 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2347 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2350 { "rx_packets", RMON_R_PACKETS },
2351 { "rx_broadcast", RMON_R_BC_PKT },
2352 { "rx_multicast", RMON_R_MC_PKT },
2353 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2354 { "rx_undersize", RMON_R_UNDERSIZE },
2355 { "rx_oversize", RMON_R_OVERSIZE },
2356 { "rx_fragment", RMON_R_FRAG },
2357 { "rx_jabber", RMON_R_JAB },
2358 { "rx_64byte", RMON_R_P64 },
2359 { "rx_65to127byte", RMON_R_P65TO127 },
2360 { "rx_128to255byte", RMON_R_P128TO255 },
2361 { "rx_256to511byte", RMON_R_P256TO511 },
2362 { "rx_512to1023byte", RMON_R_P512TO1023 },
2363 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2364 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2365 { "rx_octets", RMON_R_OCTETS },
2368 { "IEEE_rx_drop", IEEE_R_DROP },
2369 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2370 { "IEEE_rx_crc", IEEE_R_CRC },
2371 { "IEEE_rx_align", IEEE_R_ALIGN },
2372 { "IEEE_rx_macerr", IEEE_R_MACERR },
2373 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2374 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2377 #define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2379 static void fec_enet_update_ethtool_stats(struct net_device *dev)
2381 struct fec_enet_private *fep = netdev_priv(dev);
2384 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2385 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2388 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2389 struct ethtool_stats *stats, u64 *data)
2391 struct fec_enet_private *fep = netdev_priv(dev);
2393 if (netif_running(dev))
2394 fec_enet_update_ethtool_stats(dev);
2396 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
2399 static void fec_enet_get_strings(struct net_device *netdev,
2400 u32 stringset, u8 *data)
2403 switch (stringset) {
2405 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2406 memcpy(data + i * ETH_GSTRING_LEN,
2407 fec_stats[i].name, ETH_GSTRING_LEN);
2412 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2416 return ARRAY_SIZE(fec_stats);
2422 static void fec_enet_clear_ethtool_stats(struct net_device *dev)
2424 struct fec_enet_private *fep = netdev_priv(dev);
2427 /* Disable MIB statistics counters */
2428 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
2430 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2431 writel(0, fep->hwp + fec_stats[i].offset);
2433 /* Don't disable MIB statistics counters */
2434 writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
2437 #else /* !defined(CONFIG_M5272) */
2438 #define FEC_STATS_SIZE 0
2439 static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
2443 static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
2446 #endif /* !defined(CONFIG_M5272) */
2448 /* ITR clock source is enet system clock (clk_ahb).
2449 * TCTT unit is cycle_ns * 64 cycle
2450 * So, the ICTT value = X us / (cycle_ns * 64)
2452 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2454 struct fec_enet_private *fep = netdev_priv(ndev);
2456 return us * (fep->itr_clk_rate / 64000) / 1000;
2459 /* Set threshold for interrupt coalescing */
2460 static void fec_enet_itr_coal_set(struct net_device *ndev)
2462 struct fec_enet_private *fep = netdev_priv(ndev);
2465 /* Must be greater than zero to avoid unpredictable behavior */
2466 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2467 !fep->tx_time_itr || !fep->tx_pkts_itr)
2470 /* Select enet system clock as Interrupt Coalescing
2471 * timer Clock Source
2473 rx_itr = FEC_ITR_CLK_SEL;
2474 tx_itr = FEC_ITR_CLK_SEL;
2476 /* set ICFT and ICTT */
2477 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2478 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2479 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2480 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2482 rx_itr |= FEC_ITR_EN;
2483 tx_itr |= FEC_ITR_EN;
2485 writel(tx_itr, fep->hwp + FEC_TXIC0);
2486 writel(rx_itr, fep->hwp + FEC_RXIC0);
2487 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
2488 writel(tx_itr, fep->hwp + FEC_TXIC1);
2489 writel(rx_itr, fep->hwp + FEC_RXIC1);
2490 writel(tx_itr, fep->hwp + FEC_TXIC2);
2491 writel(rx_itr, fep->hwp + FEC_RXIC2);
2496 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2498 struct fec_enet_private *fep = netdev_priv(ndev);
2500 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2503 ec->rx_coalesce_usecs = fep->rx_time_itr;
2504 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2506 ec->tx_coalesce_usecs = fep->tx_time_itr;
2507 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2513 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2515 struct fec_enet_private *fep = netdev_priv(ndev);
2516 struct device *dev = &fep->pdev->dev;
2519 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
2522 if (ec->rx_max_coalesced_frames > 255) {
2523 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n");
2527 if (ec->tx_max_coalesced_frames > 255) {
2528 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n");
2532 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2533 if (cycle > 0xFFFF) {
2534 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
2538 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2539 if (cycle > 0xFFFF) {
2540 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
2544 fep->rx_time_itr = ec->rx_coalesce_usecs;
2545 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2547 fep->tx_time_itr = ec->tx_coalesce_usecs;
2548 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2550 fec_enet_itr_coal_set(ndev);
2555 static void fec_enet_itr_coal_init(struct net_device *ndev)
2557 struct ethtool_coalesce ec;
2559 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2560 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2562 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2563 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2565 fec_enet_set_coalesce(ndev, &ec);
2568 static int fec_enet_get_tunable(struct net_device *netdev,
2569 const struct ethtool_tunable *tuna,
2572 struct fec_enet_private *fep = netdev_priv(netdev);
2576 case ETHTOOL_RX_COPYBREAK:
2577 *(u32 *)data = fep->rx_copybreak;
2587 static int fec_enet_set_tunable(struct net_device *netdev,
2588 const struct ethtool_tunable *tuna,
2591 struct fec_enet_private *fep = netdev_priv(netdev);
2595 case ETHTOOL_RX_COPYBREAK:
2596 fep->rx_copybreak = *(u32 *)data;
2607 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2609 struct fec_enet_private *fep = netdev_priv(ndev);
2611 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2612 wol->supported = WAKE_MAGIC;
2613 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2615 wol->supported = wol->wolopts = 0;
2620 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2622 struct fec_enet_private *fep = netdev_priv(ndev);
2624 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2627 if (wol->wolopts & ~WAKE_MAGIC)
2630 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2631 if (device_may_wakeup(&ndev->dev)) {
2632 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2633 if (fep->irq[0] > 0)
2634 enable_irq_wake(fep->irq[0]);
2636 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2637 if (fep->irq[0] > 0)
2638 disable_irq_wake(fep->irq[0]);
2644 static const struct ethtool_ops fec_enet_ethtool_ops = {
2645 .get_drvinfo = fec_enet_get_drvinfo,
2646 .get_regs_len = fec_enet_get_regs_len,
2647 .get_regs = fec_enet_get_regs,
2648 .nway_reset = phy_ethtool_nway_reset,
2649 .get_link = ethtool_op_get_link,
2650 .get_coalesce = fec_enet_get_coalesce,
2651 .set_coalesce = fec_enet_set_coalesce,
2652 #ifndef CONFIG_M5272
2653 .get_pauseparam = fec_enet_get_pauseparam,
2654 .set_pauseparam = fec_enet_set_pauseparam,
2655 .get_strings = fec_enet_get_strings,
2656 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2657 .get_sset_count = fec_enet_get_sset_count,
2659 .get_ts_info = fec_enet_get_ts_info,
2660 .get_tunable = fec_enet_get_tunable,
2661 .set_tunable = fec_enet_set_tunable,
2662 .get_wol = fec_enet_get_wol,
2663 .set_wol = fec_enet_set_wol,
2664 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2665 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2668 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2670 struct fec_enet_private *fep = netdev_priv(ndev);
2671 struct phy_device *phydev = ndev->phydev;
2673 if (!netif_running(ndev))
2679 if (fep->bufdesc_ex) {
2680 if (cmd == SIOCSHWTSTAMP)
2681 return fec_ptp_set(ndev, rq);
2682 if (cmd == SIOCGHWTSTAMP)
2683 return fec_ptp_get(ndev, rq);
2686 return phy_mii_ioctl(phydev, rq, cmd);
2689 static void fec_enet_free_buffers(struct net_device *ndev)
2691 struct fec_enet_private *fep = netdev_priv(ndev);
2693 struct sk_buff *skb;
2694 struct bufdesc *bdp;
2695 struct fec_enet_priv_tx_q *txq;
2696 struct fec_enet_priv_rx_q *rxq;
2699 for (q = 0; q < fep->num_rx_queues; q++) {
2700 rxq = fep->rx_queue[q];
2702 for (i = 0; i < rxq->bd.ring_size; i++) {
2703 skb = rxq->rx_skbuff[i];
2704 rxq->rx_skbuff[i] = NULL;
2706 dma_unmap_single(&fep->pdev->dev,
2707 fec32_to_cpu(bdp->cbd_bufaddr),
2708 FEC_ENET_RX_FRSIZE - fep->rx_align,
2712 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2716 for (q = 0; q < fep->num_tx_queues; q++) {
2717 txq = fep->tx_queue[q];
2718 for (i = 0; i < txq->bd.ring_size; i++) {
2719 kfree(txq->tx_bounce[i]);
2720 txq->tx_bounce[i] = NULL;
2721 skb = txq->tx_skbuff[i];
2722 txq->tx_skbuff[i] = NULL;
2728 static void fec_enet_free_queue(struct net_device *ndev)
2730 struct fec_enet_private *fep = netdev_priv(ndev);
2732 struct fec_enet_priv_tx_q *txq;
2734 for (i = 0; i < fep->num_tx_queues; i++)
2735 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2736 txq = fep->tx_queue[i];
2737 dma_free_coherent(&fep->pdev->dev,
2738 txq->bd.ring_size * TSO_HEADER_SIZE,
2743 for (i = 0; i < fep->num_rx_queues; i++)
2744 kfree(fep->rx_queue[i]);
2745 for (i = 0; i < fep->num_tx_queues; i++)
2746 kfree(fep->tx_queue[i]);
2749 static int fec_enet_alloc_queue(struct net_device *ndev)
2751 struct fec_enet_private *fep = netdev_priv(ndev);
2754 struct fec_enet_priv_tx_q *txq;
2756 for (i = 0; i < fep->num_tx_queues; i++) {
2757 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2763 fep->tx_queue[i] = txq;
2764 txq->bd.ring_size = TX_RING_SIZE;
2765 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
2767 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2768 txq->tx_wake_threshold =
2769 (txq->bd.ring_size - txq->tx_stop_threshold) / 2;
2771 txq->tso_hdrs = dma_alloc_coherent(&fep->pdev->dev,
2772 txq->bd.ring_size * TSO_HEADER_SIZE,
2775 if (!txq->tso_hdrs) {
2781 for (i = 0; i < fep->num_rx_queues; i++) {
2782 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2784 if (!fep->rx_queue[i]) {
2789 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
2790 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
2795 fec_enet_free_queue(ndev);
2800 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2802 struct fec_enet_private *fep = netdev_priv(ndev);
2804 struct sk_buff *skb;
2805 struct bufdesc *bdp;
2806 struct fec_enet_priv_rx_q *rxq;
2808 rxq = fep->rx_queue[queue];
2810 for (i = 0; i < rxq->bd.ring_size; i++) {
2811 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2815 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2820 rxq->rx_skbuff[i] = skb;
2821 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
2823 if (fep->bufdesc_ex) {
2824 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2825 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
2828 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
2831 /* Set the last buffer to wrap. */
2832 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
2833 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2837 fec_enet_free_buffers(ndev);
2842 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2844 struct fec_enet_private *fep = netdev_priv(ndev);
2846 struct bufdesc *bdp;
2847 struct fec_enet_priv_tx_q *txq;
2849 txq = fep->tx_queue[queue];
2851 for (i = 0; i < txq->bd.ring_size; i++) {
2852 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2853 if (!txq->tx_bounce[i])
2856 bdp->cbd_sc = cpu_to_fec16(0);
2857 bdp->cbd_bufaddr = cpu_to_fec32(0);
2859 if (fep->bufdesc_ex) {
2860 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2861 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
2864 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
2867 /* Set the last buffer to wrap. */
2868 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
2869 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
2874 fec_enet_free_buffers(ndev);
2878 static int fec_enet_alloc_buffers(struct net_device *ndev)
2880 struct fec_enet_private *fep = netdev_priv(ndev);
2883 for (i = 0; i < fep->num_rx_queues; i++)
2884 if (fec_enet_alloc_rxq_buffers(ndev, i))
2887 for (i = 0; i < fep->num_tx_queues; i++)
2888 if (fec_enet_alloc_txq_buffers(ndev, i))
2894 fec_enet_open(struct net_device *ndev)
2896 struct fec_enet_private *fep = netdev_priv(ndev);
2900 ret = pm_runtime_get_sync(&fep->pdev->dev);
2904 pinctrl_pm_select_default_state(&fep->pdev->dev);
2905 ret = fec_enet_clk_enable(ndev, true);
2909 /* During the first fec_enet_open call the PHY isn't probed at this
2910 * point. Therefore the phy_reset_after_clk_enable() call within
2911 * fec_enet_clk_enable() fails. As we need this reset in order to be
2912 * sure the PHY is working correctly we check if we need to reset again
2913 * later when the PHY is probed
2915 if (ndev->phydev && ndev->phydev->drv)
2916 reset_again = false;
2920 /* I should reset the ring buffers here, but I don't yet know
2921 * a simple way to do that.
2924 ret = fec_enet_alloc_buffers(ndev);
2926 goto err_enet_alloc;
2928 /* Init MAC prior to mii bus probe */
2931 /* Probe and connect to PHY when open the interface */
2932 ret = fec_enet_mii_probe(ndev);
2934 goto err_enet_mii_probe;
2936 /* Call phy_reset_after_clk_enable() again if it failed during
2937 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
2940 phy_reset_after_clk_enable(ndev->phydev);
2942 if (fep->quirks & FEC_QUIRK_ERR006687)
2943 imx6q_cpuidle_fec_irqs_used();
2945 napi_enable(&fep->napi);
2946 phy_start(ndev->phydev);
2947 netif_tx_start_all_queues(ndev);
2949 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2950 FEC_WOL_FLAG_ENABLE);
2955 fec_enet_free_buffers(ndev);
2957 fec_enet_clk_enable(ndev, false);
2959 pm_runtime_mark_last_busy(&fep->pdev->dev);
2960 pm_runtime_put_autosuspend(&fep->pdev->dev);
2961 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2966 fec_enet_close(struct net_device *ndev)
2968 struct fec_enet_private *fep = netdev_priv(ndev);
2970 phy_stop(ndev->phydev);
2972 if (netif_device_present(ndev)) {
2973 napi_disable(&fep->napi);
2974 netif_tx_disable(ndev);
2978 phy_disconnect(ndev->phydev);
2980 if (fep->quirks & FEC_QUIRK_ERR006687)
2981 imx6q_cpuidle_fec_irqs_unused();
2983 fec_enet_update_ethtool_stats(ndev);
2985 fec_enet_clk_enable(ndev, false);
2986 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2987 pm_runtime_mark_last_busy(&fep->pdev->dev);
2988 pm_runtime_put_autosuspend(&fep->pdev->dev);
2990 fec_enet_free_buffers(ndev);
2995 /* Set or clear the multicast filter for this adaptor.
2996 * Skeleton taken from sunlance driver.
2997 * The CPM Ethernet implementation allows Multicast as well as individual
2998 * MAC address filtering. Some of the drivers check to make sure it is
2999 * a group multicast address, and discard those that are not. I guess I
3000 * will do the same for now, but just remove the test if you want
3001 * individual filtering as well (do the upper net layers want or support
3002 * this kind of feature?).
3005 #define FEC_HASH_BITS 6 /* #bits in hash */
3007 static void set_multicast_list(struct net_device *ndev)
3009 struct fec_enet_private *fep = netdev_priv(ndev);
3010 struct netdev_hw_addr *ha;
3011 unsigned int crc, tmp;
3013 unsigned int hash_high = 0, hash_low = 0;
3015 if (ndev->flags & IFF_PROMISC) {
3016 tmp = readl(fep->hwp + FEC_R_CNTRL);
3018 writel(tmp, fep->hwp + FEC_R_CNTRL);
3022 tmp = readl(fep->hwp + FEC_R_CNTRL);
3024 writel(tmp, fep->hwp + FEC_R_CNTRL);
3026 if (ndev->flags & IFF_ALLMULTI) {
3027 /* Catch all multicast addresses, so set the
3030 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3031 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3036 /* Add the addresses in hash register */
3037 netdev_for_each_mc_addr(ha, ndev) {
3038 /* calculate crc32 value of mac address */
3039 crc = ether_crc_le(ndev->addr_len, ha->addr);
3041 /* only upper 6 bits (FEC_HASH_BITS) are used
3042 * which point to specific bit in the hash registers
3044 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
3047 hash_high |= 1 << (hash - 32);
3049 hash_low |= 1 << hash;
3052 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3053 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3056 /* Set a MAC change in hardware. */
3058 fec_set_mac_address(struct net_device *ndev, void *p)
3060 struct fec_enet_private *fep = netdev_priv(ndev);
3061 struct sockaddr *addr = p;
3064 if (!is_valid_ether_addr(addr->sa_data))
3065 return -EADDRNOTAVAIL;
3066 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3069 /* Add netif status check here to avoid system hang in below case:
3070 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3071 * After ethx down, fec all clocks are gated off and then register
3072 * access causes system hang.
3074 if (!netif_running(ndev))
3077 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3078 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3079 fep->hwp + FEC_ADDR_LOW);
3080 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3081 fep->hwp + FEC_ADDR_HIGH);
3085 #ifdef CONFIG_NET_POLL_CONTROLLER
3087 * fec_poll_controller - FEC Poll controller function
3088 * @dev: The FEC network adapter
3090 * Polled functionality used by netconsole and others in non interrupt mode
3093 static void fec_poll_controller(struct net_device *dev)
3096 struct fec_enet_private *fep = netdev_priv(dev);
3098 for (i = 0; i < FEC_IRQ_NUM; i++) {
3099 if (fep->irq[i] > 0) {
3100 disable_irq(fep->irq[i]);
3101 fec_enet_interrupt(fep->irq[i], dev);
3102 enable_irq(fep->irq[i]);
3108 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3109 netdev_features_t features)
3111 struct fec_enet_private *fep = netdev_priv(netdev);
3112 netdev_features_t changed = features ^ netdev->features;
3114 netdev->features = features;
3116 /* Receive checksum has been changed */
3117 if (changed & NETIF_F_RXCSUM) {
3118 if (features & NETIF_F_RXCSUM)
3119 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3121 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3125 static int fec_set_features(struct net_device *netdev,
3126 netdev_features_t features)
3128 struct fec_enet_private *fep = netdev_priv(netdev);
3129 netdev_features_t changed = features ^ netdev->features;
3131 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3132 napi_disable(&fep->napi);
3133 netif_tx_lock_bh(netdev);
3135 fec_enet_set_netdev_features(netdev, features);
3136 fec_restart(netdev);
3137 netif_tx_wake_all_queues(netdev);
3138 netif_tx_unlock_bh(netdev);
3139 napi_enable(&fep->napi);
3141 fec_enet_set_netdev_features(netdev, features);
3147 static const struct net_device_ops fec_netdev_ops = {
3148 .ndo_open = fec_enet_open,
3149 .ndo_stop = fec_enet_close,
3150 .ndo_start_xmit = fec_enet_start_xmit,
3151 .ndo_set_rx_mode = set_multicast_list,
3152 .ndo_validate_addr = eth_validate_addr,
3153 .ndo_tx_timeout = fec_timeout,
3154 .ndo_set_mac_address = fec_set_mac_address,
3155 .ndo_do_ioctl = fec_enet_ioctl,
3156 #ifdef CONFIG_NET_POLL_CONTROLLER
3157 .ndo_poll_controller = fec_poll_controller,
3159 .ndo_set_features = fec_set_features,
3162 static const unsigned short offset_des_active_rxq[] = {
3163 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
3166 static const unsigned short offset_des_active_txq[] = {
3167 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
3171 * XXX: We need to clean up on failure exits here.
3174 static int fec_enet_init(struct net_device *ndev)
3176 struct fec_enet_private *fep = netdev_priv(ndev);
3177 struct bufdesc *cbd_base;
3181 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
3182 sizeof(struct bufdesc);
3183 unsigned dsize_log2 = __fls(dsize);
3186 WARN_ON(dsize != (1 << dsize_log2));
3187 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
3188 fep->rx_align = 0xf;
3189 fep->tx_align = 0xf;
3191 fep->rx_align = 0x3;
3192 fep->tx_align = 0x3;
3195 /* Check mask of the streaming and coherent API */
3196 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
3198 dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
3202 fec_enet_alloc_queue(ndev);
3204 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
3206 /* Allocate memory for buffer descriptors. */
3207 cbd_base = dmam_alloc_coherent(&fep->pdev->dev, bd_size, &bd_dma,
3213 /* Get the Ethernet address */
3215 /* make sure MAC we just acquired is programmed into the hw */
3216 fec_set_mac_address(ndev, NULL);
3218 /* Set receive and transmit descriptor base. */
3219 for (i = 0; i < fep->num_rx_queues; i++) {
3220 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
3221 unsigned size = dsize * rxq->bd.ring_size;
3224 rxq->bd.base = cbd_base;
3225 rxq->bd.cur = cbd_base;
3226 rxq->bd.dma = bd_dma;
3227 rxq->bd.dsize = dsize;
3228 rxq->bd.dsize_log2 = dsize_log2;
3229 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
3231 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3232 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3235 for (i = 0; i < fep->num_tx_queues; i++) {
3236 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
3237 unsigned size = dsize * txq->bd.ring_size;
3240 txq->bd.base = cbd_base;
3241 txq->bd.cur = cbd_base;
3242 txq->bd.dma = bd_dma;
3243 txq->bd.dsize = dsize;
3244 txq->bd.dsize_log2 = dsize_log2;
3245 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
3247 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
3248 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
3252 /* The FEC Ethernet specific entries in the device structure */
3253 ndev->watchdog_timeo = TX_TIMEOUT;
3254 ndev->netdev_ops = &fec_netdev_ops;
3255 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3257 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3258 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3260 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3261 /* enable hw VLAN support */
3262 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3264 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3265 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3267 /* enable hw accelerator */
3268 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3269 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3270 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3273 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3275 fep->rx_align = 0x3f;
3278 ndev->hw_features = ndev->features;
3282 if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
3283 fec_enet_clear_ethtool_stats(ndev);
3285 fec_enet_update_ethtool_stats(ndev);
3291 static int fec_reset_phy(struct platform_device *pdev)
3294 bool active_high = false;
3295 int msec = 1, phy_post_delay = 0;
3296 struct device_node *np = pdev->dev.of_node;
3301 err = of_property_read_u32(np, "phy-reset-duration", &msec);
3302 /* A sane reset duration should not be longer than 1s */
3303 if (!err && msec > 1000)
3306 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3307 if (phy_reset == -EPROBE_DEFER)
3309 else if (!gpio_is_valid(phy_reset))
3312 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
3313 /* valid reset duration should be less than 1s */
3314 if (!err && phy_post_delay > 1000)
3317 active_high = of_property_read_bool(np, "phy-reset-active-high");
3319 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3320 active_high ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW,
3323 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3330 usleep_range(msec * 1000, msec * 1000 + 1000);
3332 gpio_set_value_cansleep(phy_reset, !active_high);
3334 if (!phy_post_delay)
3337 if (phy_post_delay > 20)
3338 msleep(phy_post_delay);
3340 usleep_range(phy_post_delay * 1000,
3341 phy_post_delay * 1000 + 1000);
3345 #else /* CONFIG_OF */
3346 static int fec_reset_phy(struct platform_device *pdev)
3349 * In case of platform probe, the reset has been done
3354 #endif /* CONFIG_OF */
3357 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3359 struct device_node *np = pdev->dev.of_node;
3361 *num_tx = *num_rx = 1;
3363 if (!np || !of_device_is_available(np))
3366 /* parse the num of tx and rx queues */
3367 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3369 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3371 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3372 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3378 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3379 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3387 static int fec_enet_get_irq_cnt(struct platform_device *pdev)
3389 int irq_cnt = platform_irq_count(pdev);
3391 if (irq_cnt > FEC_IRQ_NUM)
3392 irq_cnt = FEC_IRQ_NUM; /* last for pps */
3393 else if (irq_cnt == 2)
3394 irq_cnt = 1; /* last for pps */
3395 else if (irq_cnt <= 0)
3396 irq_cnt = 1; /* At least 1 irq is needed */
3401 fec_probe(struct platform_device *pdev)
3403 struct fec_enet_private *fep;
3404 struct fec_platform_data *pdata;
3405 phy_interface_t interface;
3406 struct net_device *ndev;
3407 int i, irq, ret = 0;
3408 const struct of_device_id *of_id;
3410 struct device_node *np = pdev->dev.of_node, *phy_node;
3416 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3418 /* Init network device */
3419 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
3420 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
3424 SET_NETDEV_DEV(ndev, &pdev->dev);
3426 /* setup board info structure */
3427 fep = netdev_priv(ndev);
3429 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3431 pdev->id_entry = of_id->data;
3432 fep->quirks = pdev->id_entry->driver_data;
3435 fep->num_rx_queues = num_rx_qs;
3436 fep->num_tx_queues = num_tx_qs;
3438 #if !defined(CONFIG_M5272)
3439 /* default enable pause frame auto negotiation */
3440 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3441 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3444 /* Select default pin state */
3445 pinctrl_pm_select_default_state(&pdev->dev);
3447 fep->hwp = devm_platform_ioremap_resource(pdev, 0);
3448 if (IS_ERR(fep->hwp)) {
3449 ret = PTR_ERR(fep->hwp);
3450 goto failed_ioremap;
3454 fep->dev_id = dev_id++;
3456 platform_set_drvdata(pdev, ndev);
3458 if ((of_machine_is_compatible("fsl,imx6q") ||
3459 of_machine_is_compatible("fsl,imx6dl")) &&
3460 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
3461 fep->quirks |= FEC_QUIRK_ERR006687;
3463 if (of_get_property(np, "fsl,magic-packet", NULL))
3464 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3466 phy_node = of_parse_phandle(np, "phy-handle", 0);
3467 if (!phy_node && of_phy_is_fixed_link(np)) {
3468 ret = of_phy_register_fixed_link(np);
3471 "broken fixed-link specification\n");
3474 phy_node = of_node_get(np);
3476 fep->phy_node = phy_node;
3478 ret = of_get_phy_mode(pdev->dev.of_node, &interface);
3480 pdata = dev_get_platdata(&pdev->dev);
3482 fep->phy_interface = pdata->phy;
3484 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3486 fep->phy_interface = interface;
3489 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3490 if (IS_ERR(fep->clk_ipg)) {
3491 ret = PTR_ERR(fep->clk_ipg);
3495 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3496 if (IS_ERR(fep->clk_ahb)) {
3497 ret = PTR_ERR(fep->clk_ahb);
3501 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3503 /* enet_out is optional, depends on board */
3504 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3505 if (IS_ERR(fep->clk_enet_out))
3506 fep->clk_enet_out = NULL;
3508 fep->ptp_clk_on = false;
3509 mutex_init(&fep->ptp_clk_mutex);
3511 /* clk_ref is optional, depends on board */
3512 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3513 if (IS_ERR(fep->clk_ref))
3514 fep->clk_ref = NULL;
3516 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3517 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3518 if (IS_ERR(fep->clk_ptp)) {
3519 fep->clk_ptp = NULL;
3520 fep->bufdesc_ex = false;
3523 ret = fec_enet_clk_enable(ndev, true);
3527 ret = clk_prepare_enable(fep->clk_ipg);
3529 goto failed_clk_ipg;
3530 ret = clk_prepare_enable(fep->clk_ahb);
3532 goto failed_clk_ahb;
3534 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy");
3535 if (!IS_ERR(fep->reg_phy)) {
3536 ret = regulator_enable(fep->reg_phy);
3539 "Failed to enable phy regulator: %d\n", ret);
3540 goto failed_regulator;
3543 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
3544 ret = -EPROBE_DEFER;
3545 goto failed_regulator;
3547 fep->reg_phy = NULL;
3550 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
3551 pm_runtime_use_autosuspend(&pdev->dev);
3552 pm_runtime_get_noresume(&pdev->dev);
3553 pm_runtime_set_active(&pdev->dev);
3554 pm_runtime_enable(&pdev->dev);
3556 ret = fec_reset_phy(pdev);
3560 irq_cnt = fec_enet_get_irq_cnt(pdev);
3561 if (fep->bufdesc_ex)
3562 fec_ptp_init(pdev, irq_cnt);
3564 ret = fec_enet_init(ndev);
3568 for (i = 0; i < irq_cnt; i++) {
3569 snprintf(irq_name, sizeof(irq_name), "int%d", i);
3570 irq = platform_get_irq_byname_optional(pdev, irq_name);
3572 irq = platform_get_irq(pdev, i);
3577 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3578 0, pdev->name, ndev);
3585 init_completion(&fep->mdio_done);
3586 ret = fec_enet_mii_init(pdev);
3588 goto failed_mii_init;
3590 /* Carrier starts down, phylib will bring it up */
3591 netif_carrier_off(ndev);
3592 fec_enet_clk_enable(ndev, false);
3593 pinctrl_pm_select_sleep_state(&pdev->dev);
3595 ret = register_netdev(ndev);
3597 goto failed_register;
3599 device_init_wakeup(&ndev->dev, fep->wol_flag &
3600 FEC_WOL_HAS_MAGIC_PACKET);
3602 if (fep->bufdesc_ex && fep->ptp_clock)
3603 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3605 fep->rx_copybreak = COPYBREAK_DEFAULT;
3606 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3608 pm_runtime_mark_last_busy(&pdev->dev);
3609 pm_runtime_put_autosuspend(&pdev->dev);
3614 fec_enet_mii_remove(fep);
3620 regulator_disable(fep->reg_phy);
3622 pm_runtime_put_noidle(&pdev->dev);
3623 pm_runtime_disable(&pdev->dev);
3625 clk_disable_unprepare(fep->clk_ahb);
3627 clk_disable_unprepare(fep->clk_ipg);
3629 fec_enet_clk_enable(ndev, false);
3631 if (of_phy_is_fixed_link(np))
3632 of_phy_deregister_fixed_link(np);
3633 of_node_put(phy_node);
3643 fec_drv_remove(struct platform_device *pdev)
3645 struct net_device *ndev = platform_get_drvdata(pdev);
3646 struct fec_enet_private *fep = netdev_priv(ndev);
3647 struct device_node *np = pdev->dev.of_node;
3650 ret = pm_runtime_get_sync(&pdev->dev);
3654 cancel_work_sync(&fep->tx_timeout_work);
3656 unregister_netdev(ndev);
3657 fec_enet_mii_remove(fep);
3659 regulator_disable(fep->reg_phy);
3661 if (of_phy_is_fixed_link(np))
3662 of_phy_deregister_fixed_link(np);
3663 of_node_put(fep->phy_node);
3666 clk_disable_unprepare(fep->clk_ahb);
3667 clk_disable_unprepare(fep->clk_ipg);
3668 pm_runtime_put_noidle(&pdev->dev);
3669 pm_runtime_disable(&pdev->dev);
3674 static int __maybe_unused fec_suspend(struct device *dev)
3676 struct net_device *ndev = dev_get_drvdata(dev);
3677 struct fec_enet_private *fep = netdev_priv(ndev);
3680 if (netif_running(ndev)) {
3681 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3682 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3683 phy_stop(ndev->phydev);
3684 napi_disable(&fep->napi);
3685 netif_tx_lock_bh(ndev);
3686 netif_device_detach(ndev);
3687 netif_tx_unlock_bh(ndev);
3689 fec_enet_clk_enable(ndev, false);
3690 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3691 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3695 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3696 regulator_disable(fep->reg_phy);
3698 /* SOC supply clock to phy, when clock is disabled, phy link down
3699 * SOC control phy regulator, when regulator is disabled, phy link down
3701 if (fep->clk_enet_out || fep->reg_phy)
3707 static int __maybe_unused fec_resume(struct device *dev)
3709 struct net_device *ndev = dev_get_drvdata(dev);
3710 struct fec_enet_private *fep = netdev_priv(ndev);
3711 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3715 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3716 ret = regulator_enable(fep->reg_phy);
3722 if (netif_running(ndev)) {
3723 ret = fec_enet_clk_enable(ndev, true);
3728 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3729 if (pdata && pdata->sleep_mode_enable)
3730 pdata->sleep_mode_enable(false);
3731 val = readl(fep->hwp + FEC_ECNTRL);
3732 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3733 writel(val, fep->hwp + FEC_ECNTRL);
3734 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3736 pinctrl_pm_select_default_state(&fep->pdev->dev);
3739 netif_tx_lock_bh(ndev);
3740 netif_device_attach(ndev);
3741 netif_tx_unlock_bh(ndev);
3742 napi_enable(&fep->napi);
3743 phy_start(ndev->phydev);
3751 regulator_disable(fep->reg_phy);
3755 static int __maybe_unused fec_runtime_suspend(struct device *dev)
3757 struct net_device *ndev = dev_get_drvdata(dev);
3758 struct fec_enet_private *fep = netdev_priv(ndev);
3760 clk_disable_unprepare(fep->clk_ahb);
3761 clk_disable_unprepare(fep->clk_ipg);
3766 static int __maybe_unused fec_runtime_resume(struct device *dev)
3768 struct net_device *ndev = dev_get_drvdata(dev);
3769 struct fec_enet_private *fep = netdev_priv(ndev);
3772 ret = clk_prepare_enable(fep->clk_ahb);
3775 ret = clk_prepare_enable(fep->clk_ipg);
3777 goto failed_clk_ipg;
3782 clk_disable_unprepare(fep->clk_ahb);
3786 static const struct dev_pm_ops fec_pm_ops = {
3787 SET_SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
3788 SET_RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
3791 static struct platform_driver fec_driver = {
3793 .name = DRIVER_NAME,
3795 .of_match_table = fec_dt_ids,
3797 .id_table = fec_devtype,
3799 .remove = fec_drv_remove,
3802 module_platform_driver(fec_driver);
3804 MODULE_ALIAS("platform:"DRIVER_NAME);
3805 MODULE_LICENSE("GPL");