drivers/net/ethernet/freescale/gianfar.c

   1 /* drivers/net/ethernet/freescale/gianfar.c
   2  *
   3  * Gianfar Ethernet Driver
   4  * This driver is designed for the non-CPM ethernet controllers
   5  * on the 85xx and 83xx family of integrated processors
   6  * Based on 8260_io/fcc_enet.c
   7  *
   8  * Author: Andy Fleming
   9  * Maintainer: Kumar Gala
  10  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  11  *
  12  * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
  13  * Copyright 2007 MontaVista Software, Inc.
  14  *
  15  * This program is free software; you can redistribute  it and/or modify it
  16  * under  the terms of  the GNU General  Public License as published by the
  17  * Free Software Foundation;  either version 2 of the  License, or (at your
  18  * option) any later version.
  19  *
  20  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  21  *  RA 11 31 24.2
  22  *  Dec +69 19 52
  23  *  V 3.84
  24  *  B-V +1.62
  25  *
  26  *  Theory of operation
  27  *
  28  *  The driver is initialized through of_device. Configuration information
  29  *  is therefore conveyed through an OF-style device tree.
  30  *
  31  *  The Gianfar Ethernet Controller uses a ring of buffer
  32  *  descriptors.  The beginning is indicated by a register
  33  *  pointing to the physical address of the start of the ring.
  34  *  The end is determined by a "wrap" bit being set in the
  35  *  last descriptor of the ring.
  36  *
  37  *  When a packet is received, the RXF bit in the
  38  *  IEVENT register is set, triggering an interrupt when the
  39  *  corresponding bit in the IMASK register is also set (if
  40  *  interrupt coalescing is active, then the interrupt may not
  41  *  happen immediately, but will wait until either a set number
  42  *  of frames or amount of time have passed).  In NAPI, the
  43  *  interrupt handler will signal there is work to be done, and
  44  *  exit. This method will start at the last known empty
  45  *  descriptor, and process every subsequent descriptor until there
  46  *  are none left with data (NAPI will stop after a set number of
  47  *  packets to give time to other tasks, but will eventually
  48  *  process all the packets).  The data arrives inside a
  49  *  pre-allocated skb, and so after the skb is passed up to the
  50  *  stack, a new skb must be allocated, and the address field in
  51  *  the buffer descriptor must be updated to indicate this new
  52  *  skb.
  53  *
  54  *  When the kernel requests that a packet be transmitted, the
  55  *  driver starts where it left off last time, and points the
  56  *  descriptor at the buffer which was passed in.  The driver
  57  *  then informs the DMA engine that there are packets ready to
  58  *  be transmitted.  Once the controller is finished transmitting
  59  *  the packet, an interrupt may be triggered (under the same
  60  *  conditions as for reception, but depending on the TXF bit).
  61  *  The driver then cleans up the buffer.
  62  */
  63
  64 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  65 #define DEBUG
  66
  67 #include <linux/kernel.h>
  68 #include <linux/string.h>
  69 #include <linux/errno.h>
  70 #include <linux/unistd.h>
  71 #include <linux/slab.h>
  72 #include <linux/interrupt.h>
  73 #include <linux/delay.h>
  74 #include <linux/netdevice.h>
  75 #include <linux/etherdevice.h>
  76 #include <linux/skbuff.h>
  77 #include <linux/if_vlan.h>
  78 #include <linux/spinlock.h>
  79 #include <linux/mm.h>
  80 #include <linux/of_address.h>
  81 #include <linux/of_irq.h>
  82 #include <linux/of_mdio.h>
  83 #include <linux/of_platform.h>
  84 #include <linux/ip.h>
  85 #include <linux/tcp.h>
  86 #include <linux/udp.h>
  87 #include <linux/in.h>
  88 #include <linux/net_tstamp.h>
  89
  90 #include <asm/io.h>
  91 #ifdef CONFIG_PPC
  92 #include <asm/reg.h>
  93 #include <asm/mpc85xx.h>
  94 #endif
  95 #include <asm/irq.h>
  96 #include <asm/uaccess.h>
  97 #include <linux/module.h>
  98 #include <linux/dma-mapping.h>
  99 #include <linux/crc32.h>
 100 #include <linux/mii.h>
 101 #include <linux/phy.h>
 102 #include <linux/phy_fixed.h>
 103 #include <linux/of.h>
 104 #include <linux/of_net.h>
 105 #include <linux/of_address.h>
 106 #include <linux/of_irq.h>
 107
 108 #include "gianfar.h"
 109
 110 #define TX_TIMEOUT      (5*HZ)
 111
 112 const char gfar_driver_version[] = "2.0";
 113
 114 static int gfar_enet_open(struct net_device *dev);
 115 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 116 static void gfar_reset_task(struct work_struct *work);
 117 static void gfar_timeout(struct net_device *dev);
 118 static int gfar_close(struct net_device *dev);
 119 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
 120                                 int alloc_cnt);
 121 static int gfar_set_mac_address(struct net_device *dev);
 122 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 123 static irqreturn_t gfar_error(int irq, void *dev_id);
 124 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 125 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 126 static void adjust_link(struct net_device *dev);
 127 static noinline void gfar_update_link_state(struct gfar_private *priv);
 128 static int init_phy(struct net_device *dev);
 129 static int gfar_probe(struct platform_device *ofdev);
 130 static int gfar_remove(struct platform_device *ofdev);
 131 static void free_skb_resources(struct gfar_private *priv);
 132 static void gfar_set_multi(struct net_device *dev);
 133 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 134 static void gfar_configure_serdes(struct net_device *dev);
 135 static int gfar_poll_rx(struct napi_struct *napi, int budget);
 136 static int gfar_poll_tx(struct napi_struct *napi, int budget);
 137 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget);
 138 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget);
 139 #ifdef CONFIG_NET_POLL_CONTROLLER
 140 static void gfar_netpoll(struct net_device *dev);
 141 #endif
 142 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 143 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 144 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb);
 145 static void gfar_halt_nodisable(struct gfar_private *priv);
 146 static void gfar_clear_exact_match(struct net_device *dev);
 147 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 148                                   const u8 *addr);
 149 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 150
 151 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 152 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 153 MODULE_LICENSE("GPL");
 154
 155 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 156                             dma_addr_t buf)
 157 {
 158         u32 lstatus;
 159
 160         bdp->bufPtr = cpu_to_be32(buf);
 161
 162         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 163         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 164                 lstatus |= BD_LFLAG(RXBD_WRAP);
 165
 166         gfar_wmb();
 167
 168         bdp->lstatus = cpu_to_be32(lstatus);
 169 }
 170
 171 static void gfar_init_bds(struct net_device *ndev)
 172 {
 173         struct gfar_private *priv = netdev_priv(ndev);
 174         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 175         struct gfar_priv_tx_q *tx_queue = NULL;
 176         struct gfar_priv_rx_q *rx_queue = NULL;
 177         struct txbd8 *txbdp;
 178         u32 __iomem *rfbptr;
 179         int i, j;
 180
 181         for (i = 0; i < priv->num_tx_queues; i++) {
 182                 tx_queue = priv->tx_queue[i];
 183                 /* Initialize some variables in our dev structure */
 184                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 185                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 186                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 187                 tx_queue->skb_curtx = 0;
 188                 tx_queue->skb_dirtytx = 0;
 189
 190                 /* Initialize Transmit Descriptor Ring */
 191                 txbdp = tx_queue->tx_bd_base;
 192                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 193                         txbdp->lstatus = 0;
 194                         txbdp->bufPtr = 0;
 195                         txbdp++;
 196                 }
 197
 198                 /* Set the last descriptor in the ring to indicate wrap */
 199                 txbdp--;
 200                 txbdp->status = cpu_to_be16(be16_to_cpu(txbdp->status) |
 201                                             TXBD_WRAP);
 202         }
 203
 204         rfbptr = &regs->rfbptr0;
 205         for (i = 0; i < priv->num_rx_queues; i++) {
 206                 rx_queue = priv->rx_queue[i];
 207
 208                 rx_queue->next_to_clean = 0;
 209                 rx_queue->next_to_use = 0;
 210                 rx_queue->next_to_alloc = 0;
 211
 212                 /* make sure next_to_clean != next_to_use after this
 213                  * by leaving at least 1 unused descriptor
 214                  */
 215                 gfar_alloc_rx_buffs(rx_queue, gfar_rxbd_unused(rx_queue));
 216
 217                 rx_queue->rfbptr = rfbptr;
 218                 rfbptr += 2;
 219         }
 220 }
 221
 222 static int gfar_alloc_skb_resources(struct net_device *ndev)
 223 {
 224         void *vaddr;
 225         dma_addr_t addr;
 226         int i, j;
 227         struct gfar_private *priv = netdev_priv(ndev);
 228         struct device *dev = priv->dev;
 229         struct gfar_priv_tx_q *tx_queue = NULL;
 230         struct gfar_priv_rx_q *rx_queue = NULL;
 231
 232         priv->total_tx_ring_size = 0;
 233         for (i = 0; i < priv->num_tx_queues; i++)
 234                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 235
 236         priv->total_rx_ring_size = 0;
 237         for (i = 0; i < priv->num_rx_queues; i++)
 238                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 239
 240         /* Allocate memory for the buffer descriptors */
 241         vaddr = dma_alloc_coherent(dev,
 242                                    (priv->total_tx_ring_size *
 243                                     sizeof(struct txbd8)) +
 244                                    (priv->total_rx_ring_size *
 245                                     sizeof(struct rxbd8)),
 246                                    &addr, GFP_KERNEL);
 247         if (!vaddr)
 248                 return -ENOMEM;
 249
 250         for (i = 0; i < priv->num_tx_queues; i++) {
 251                 tx_queue = priv->tx_queue[i];
 252                 tx_queue->tx_bd_base = vaddr;
 253                 tx_queue->tx_bd_dma_base = addr;
 254                 tx_queue->dev = ndev;
 255                 /* enet DMA only understands physical addresses */
 256                 addr  += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 257                 vaddr += sizeof(struct txbd8) * tx_queue->tx_ring_size;
 258         }
 259
 260         /* Start the rx descriptor ring where the tx ring leaves off */
 261         for (i = 0; i < priv->num_rx_queues; i++) {
 262                 rx_queue = priv->rx_queue[i];
 263                 rx_queue->rx_bd_base = vaddr;
 264                 rx_queue->rx_bd_dma_base = addr;
 265                 rx_queue->ndev = ndev;
 266                 rx_queue->dev = dev;
 267                 addr  += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 268                 vaddr += sizeof(struct rxbd8) * rx_queue->rx_ring_size;
 269         }
 270
 271         /* Setup the skbuff rings */
 272         for (i = 0; i < priv->num_tx_queues; i++) {
 273                 tx_queue = priv->tx_queue[i];
 274                 tx_queue->tx_skbuff =
 275                         kmalloc_array(tx_queue->tx_ring_size,
 276                                       sizeof(*tx_queue->tx_skbuff),
 277                                       GFP_KERNEL);
 278                 if (!tx_queue->tx_skbuff)
 279                         goto cleanup;
 280
 281                 for (j = 0; j < tx_queue->tx_ring_size; j++)
 282                         tx_queue->tx_skbuff[j] = NULL;
 283         }
 284
 285         for (i = 0; i < priv->num_rx_queues; i++) {
 286                 rx_queue = priv->rx_queue[i];
 287                 rx_queue->rx_buff = kcalloc(rx_queue->rx_ring_size,
 288                                             sizeof(*rx_queue->rx_buff),
 289                                             GFP_KERNEL);
 290                 if (!rx_queue->rx_buff)
 291                         goto cleanup;
 292         }
 293
 294         gfar_init_bds(ndev);
 295
 296         return 0;
 297
 298 cleanup:
 299         free_skb_resources(priv);
 300         return -ENOMEM;
 301 }
 302
 303 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 304 {
 305         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 306         u32 __iomem *baddr;
 307         int i;
 308
 309         baddr = &regs->tbase0;
 310         for (i = 0; i < priv->num_tx_queues; i++) {
 311                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 312                 baddr += 2;
 313         }
 314
 315         baddr = &regs->rbase0;
 316         for (i = 0; i < priv->num_rx_queues; i++) {
 317                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 318                 baddr += 2;
 319         }
 320 }
 321
 322 static void gfar_init_rqprm(struct gfar_private *priv)
 323 {
 324         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 325         u32 __iomem *baddr;
 326         int i;
 327
 328         baddr = &regs->rqprm0;
 329         for (i = 0; i < priv->num_rx_queues; i++) {
 330                 gfar_write(baddr, priv->rx_queue[i]->rx_ring_size |
 331                            (DEFAULT_RX_LFC_THR << FBTHR_SHIFT));
 332                 baddr++;
 333         }
 334 }
 335
 336 static void gfar_rx_offload_en(struct gfar_private *priv)
 337 {
 338         /* set this when rx hw offload (TOE) functions are being used */
 339         priv->uses_rxfcb = 0;
 340
 341         if (priv->ndev->features & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX))
 342                 priv->uses_rxfcb = 1;
 343
 344         if (priv->hwts_rx_en || priv->rx_filer_enable)
 345                 priv->uses_rxfcb = 1;
 346 }
 347
 348 static void gfar_mac_rx_config(struct gfar_private *priv)
 349 {
 350         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 351         u32 rctrl = 0;
 352
 353         if (priv->rx_filer_enable) {
 354                 rctrl |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
 355                 /* Program the RIR0 reg with the required distribution */
 356                 if (priv->poll_mode == GFAR_SQ_POLLING)
 357                         gfar_write(&regs->rir0, DEFAULT_2RXQ_RIR0);
 358                 else /* GFAR_MQ_POLLING */
 359                         gfar_write(&regs->rir0, DEFAULT_8RXQ_RIR0);
 360         }
 361
 362         /* Restore PROMISC mode */
 363         if (priv->ndev->flags & IFF_PROMISC)
 364                 rctrl |= RCTRL_PROM;
 365
 366         if (priv->ndev->features & NETIF_F_RXCSUM)
 367                 rctrl |= RCTRL_CHECKSUMMING;
 368
 369         if (priv->extended_hash)
 370                 rctrl |= RCTRL_EXTHASH | RCTRL_EMEN;
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Enable HW time stamping if requested from user space */
 378         if (priv->hwts_rx_en)
 379                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 380
 381         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
 382                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 383
 384         /* Clear the LFC bit */
 385         gfar_write(&regs->rctrl, rctrl);
 386         /* Init flow control threshold values */
 387         gfar_init_rqprm(priv);
 388         gfar_write(&regs->ptv, DEFAULT_LFC_PTVVAL);
 389         rctrl |= RCTRL_LFC;
 390
 391         /* Init rctrl based on our settings */
 392         gfar_write(&regs->rctrl, rctrl);
 393 }
 394
 395 static void gfar_mac_tx_config(struct gfar_private *priv)
 396 {
 397         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 398         u32 tctrl = 0;
 399
 400         if (priv->ndev->features & NETIF_F_IP_CSUM)
 401                 tctrl |= TCTRL_INIT_CSUM;
 402
 403         if (priv->prio_sched_en)
 404                 tctrl |= TCTRL_TXSCHED_PRIO;
 405         else {
 406                 tctrl |= TCTRL_TXSCHED_WRRS;
 407                 gfar_write(&regs->tr03wt, DEFAULT_WRRS_WEIGHT);
 408                 gfar_write(&regs->tr47wt, DEFAULT_WRRS_WEIGHT);
 409         }
 410
 411         if (priv->ndev->features & NETIF_F_HW_VLAN_CTAG_TX)
 412                 tctrl |= TCTRL_VLINS;
 413
 414         gfar_write(&regs->tctrl, tctrl);
 415 }
 416
 417 static void gfar_configure_coalescing(struct gfar_private *priv,
 418                                unsigned long tx_mask, unsigned long rx_mask)
 419 {
 420         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 421         u32 __iomem *baddr;
 422
 423         if (priv->mode == MQ_MG_MODE) {
 424                 int i = 0;
 425
 426                 baddr = &regs->txic0;
 427                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
 428                         gfar_write(baddr + i, 0);
 429                         if (likely(priv->tx_queue[i]->txcoalescing))
 430                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
 431                 }
 432
 433                 baddr = &regs->rxic0;
 434                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
 435                         gfar_write(baddr + i, 0);
 436                         if (likely(priv->rx_queue[i]->rxcoalescing))
 437                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
 438                 }
 439         } else {
 440                 /* Backward compatible case -- even if we enable
 441                  * multiple queues, there's only single reg to program
 442                  */
 443                 gfar_write(&regs->txic, 0);
 444                 if (likely(priv->tx_queue[0]->txcoalescing))
 445                         gfar_write(&regs->txic, priv->tx_queue[0]->txic);
 446
 447                 gfar_write(&regs->rxic, 0);
 448                 if (unlikely(priv->rx_queue[0]->rxcoalescing))
 449                         gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
 450         }
 451 }
 452
 453 void gfar_configure_coalescing_all(struct gfar_private *priv)
 454 {
 455         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 456 }
 457
 458 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 459 {
 460         struct gfar_private *priv = netdev_priv(dev);
 461         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 462         unsigned long tx_packets = 0, tx_bytes = 0;
 463         int i;
 464
 465         for (i = 0; i < priv->num_rx_queues; i++) {
 466                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 467                 rx_bytes   += priv->rx_queue[i]->stats.rx_bytes;
 468                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 469         }
 470
 471         dev->stats.rx_packets = rx_packets;
 472         dev->stats.rx_bytes   = rx_bytes;
 473         dev->stats.rx_dropped = rx_dropped;
 474
 475         for (i = 0; i < priv->num_tx_queues; i++) {
 476                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 477                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 478         }
 479
 480         dev->stats.tx_bytes   = tx_bytes;
 481         dev->stats.tx_packets = tx_packets;
 482
 483         return &dev->stats;
 484 }
 485
 486 static int gfar_set_mac_addr(struct net_device *dev, void *p)
 487 {
 488         eth_mac_addr(dev, p);
 489
 490         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
 491
 492         return 0;
 493 }
 494
 495 static const struct net_device_ops gfar_netdev_ops = {
 496         .ndo_open = gfar_enet_open,
 497         .ndo_start_xmit = gfar_start_xmit,
 498         .ndo_stop = gfar_close,
 499         .ndo_change_mtu = gfar_change_mtu,
 500         .ndo_set_features = gfar_set_features,
 501         .ndo_set_rx_mode = gfar_set_multi,
 502         .ndo_tx_timeout = gfar_timeout,
 503         .ndo_do_ioctl = gfar_ioctl,
 504         .ndo_get_stats = gfar_get_stats,
 505         .ndo_set_mac_address = gfar_set_mac_addr,
 506         .ndo_validate_addr = eth_validate_addr,
 507 #ifdef CONFIG_NET_POLL_CONTROLLER
 508         .ndo_poll_controller = gfar_netpoll,
 509 #endif
 510 };
 511
 512 static void gfar_ints_disable(struct gfar_private *priv)
 513 {
 514         int i;
 515         for (i = 0; i < priv->num_grps; i++) {
 516                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 517                 /* Clear IEVENT */
 518                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
 519
 520                 /* Initialize IMASK */
 521                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
 522         }
 523 }
 524
 525 static void gfar_ints_enable(struct gfar_private *priv)
 526 {
 527         int i;
 528         for (i = 0; i < priv->num_grps; i++) {
 529                 struct gfar __iomem *regs = priv->gfargrp[i].regs;
 530                 /* Unmask the interrupts we look for */
 531                 gfar_write(&regs->imask, IMASK_DEFAULT);
 532         }
 533 }
 534
 535 static int gfar_alloc_tx_queues(struct gfar_private *priv)
 536 {
 537         int i;
 538
 539         for (i = 0; i < priv->num_tx_queues; i++) {
 540                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 541                                             GFP_KERNEL);
 542                 if (!priv->tx_queue[i])
 543                         return -ENOMEM;
 544
 545                 priv->tx_queue[i]->tx_skbuff = NULL;
 546                 priv->tx_queue[i]->qindex = i;
 547                 priv->tx_queue[i]->dev = priv->ndev;
 548                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 549         }
 550         return 0;
 551 }
 552
 553 static int gfar_alloc_rx_queues(struct gfar_private *priv)
 554 {
 555         int i;
 556
 557         for (i = 0; i < priv->num_rx_queues; i++) {
 558                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 559                                             GFP_KERNEL);
 560                 if (!priv->rx_queue[i])
 561                         return -ENOMEM;
 562
 563                 priv->rx_queue[i]->qindex = i;
 564                 priv->rx_queue[i]->ndev = priv->ndev;
 565         }
 566         return 0;
 567 }
 568
 569 static void gfar_free_tx_queues(struct gfar_private *priv)
 570 {
 571         int i;
 572
 573         for (i = 0; i < priv->num_tx_queues; i++)
 574                 kfree(priv->tx_queue[i]);
 575 }
 576
 577 static void gfar_free_rx_queues(struct gfar_private *priv)
 578 {
 579         int i;
 580
 581         for (i = 0; i < priv->num_rx_queues; i++)
 582                 kfree(priv->rx_queue[i]);
 583 }
 584
 585 static void unmap_group_regs(struct gfar_private *priv)
 586 {
 587         int i;
 588
 589         for (i = 0; i < MAXGROUPS; i++)
 590                 if (priv->gfargrp[i].regs)
 591                         iounmap(priv->gfargrp[i].regs);
 592 }
 593
 594 static void free_gfar_dev(struct gfar_private *priv)
 595 {
 596         int i, j;
 597
 598         for (i = 0; i < priv->num_grps; i++)
 599                 for (j = 0; j < GFAR_NUM_IRQS; j++) {
 600                         kfree(priv->gfargrp[i].irqinfo[j]);
 601                         priv->gfargrp[i].irqinfo[j] = NULL;
 602                 }
 603
 604         free_netdev(priv->ndev);
 605 }
 606
 607 static void disable_napi(struct gfar_private *priv)
 608 {
 609         int i;
 610
 611         for (i = 0; i < priv->num_grps; i++) {
 612                 napi_disable(&priv->gfargrp[i].napi_rx);
 613                 napi_disable(&priv->gfargrp[i].napi_tx);
 614         }
 615 }
 616
 617 static void enable_napi(struct gfar_private *priv)
 618 {
 619         int i;
 620
 621         for (i = 0; i < priv->num_grps; i++) {
 622                 napi_enable(&priv->gfargrp[i].napi_rx);
 623                 napi_enable(&priv->gfargrp[i].napi_tx);
 624         }
 625 }
 626
 627 static int gfar_parse_group(struct device_node *np,
 628                             struct gfar_private *priv, const char *model)
 629 {
 630         struct gfar_priv_grp *grp = &priv->gfargrp[priv->num_grps];
 631         int i;
 632
 633         for (i = 0; i < GFAR_NUM_IRQS; i++) {
 634                 grp->irqinfo[i] = kzalloc(sizeof(struct gfar_irqinfo),
 635                                           GFP_KERNEL);
 636                 if (!grp->irqinfo[i])
 637                         return -ENOMEM;
 638         }
 639
 640         grp->regs = of_iomap(np, 0);
 641         if (!grp->regs)
 642                 return -ENOMEM;
 643
 644         gfar_irq(grp, TX)->irq = irq_of_parse_and_map(np, 0);
 645
 646         /* If we aren't the FEC we have multiple interrupts */
 647         if (model && strcasecmp(model, "FEC")) {
 648                 gfar_irq(grp, RX)->irq = irq_of_parse_and_map(np, 1);
 649                 gfar_irq(grp, ER)->irq = irq_of_parse_and_map(np, 2);
 650                 if (!gfar_irq(grp, TX)->irq ||
 651                     !gfar_irq(grp, RX)->irq ||
 652                     !gfar_irq(grp, ER)->irq)
 653                         return -EINVAL;
 654         }
 655
 656         grp->priv = priv;
 657         spin_lock_init(&grp->grplock);
 658         if (priv->mode == MQ_MG_MODE) {
 659                 u32 rxq_mask, txq_mask;
 660                 int ret;
 661
 662                 grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 663                 grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 664
 665                 ret = of_property_read_u32(np, "fsl,rx-bit-map", &rxq_mask);
 666                 if (!ret) {
 667                         grp->rx_bit_map = rxq_mask ?
 668                         rxq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 669                 }
 670
 671                 ret = of_property_read_u32(np, "fsl,tx-bit-map", &txq_mask);
 672                 if (!ret) {
 673                         grp->tx_bit_map = txq_mask ?
 674                         txq_mask : (DEFAULT_MAPPING >> priv->num_grps);
 675                 }
 676
 677                 if (priv->poll_mode == GFAR_SQ_POLLING) {
 678                         /* One Q per interrupt group: Q0 to G0, Q1 to G1 */
 679                         grp->rx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 680                         grp->tx_bit_map = (DEFAULT_MAPPING >> priv->num_grps);
 681                 }
 682         } else {
 683                 grp->rx_bit_map = 0xFF;
 684                 grp->tx_bit_map = 0xFF;
 685         }
 686
 687         /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
 688          * right to left, so we need to revert the 8 bits to get the q index
 689          */
 690         grp->rx_bit_map = bitrev8(grp->rx_bit_map);
 691         grp->tx_bit_map = bitrev8(grp->tx_bit_map);
 692
 693         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
 694          * also assign queues to groups
 695          */
 696         for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
 697                 if (!grp->rx_queue)
 698                         grp->rx_queue = priv->rx_queue[i];
 699                 grp->num_rx_queues++;
 700                 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
 701                 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
 702                 priv->rx_queue[i]->grp = grp;
 703         }
 704
 705         for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
 706                 if (!grp->tx_queue)
 707                         grp->tx_queue = priv->tx_queue[i];
 708                 grp->num_tx_queues++;
 709                 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
 710                 priv->tqueue |= (TQUEUE_EN0 >> i);
 711                 priv->tx_queue[i]->grp = grp;
 712         }
 713
 714         priv->num_grps++;
 715
 716         return 0;
 717 }
 718
 719 static int gfar_of_group_count(struct device_node *np)
 720 {
 721         struct device_node *child;
 722         int num = 0;
 723
 724         for_each_available_child_of_node(np, child)
 725                 if (!of_node_cmp(child->name, "queue-group"))
 726                         num++;
 727
 728         return num;
 729 }
 730
 731 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 732 {
 733         const char *model;
 734         const char *ctype;
 735         const void *mac_addr;
 736         int err = 0, i;
 737         struct net_device *dev = NULL;
 738         struct gfar_private *priv = NULL;
 739         struct device_node *np = ofdev->dev.of_node;
 740         struct device_node *child = NULL;
 741         u32 stash_len = 0;
 742         u32 stash_idx = 0;
 743         unsigned int num_tx_qs, num_rx_qs;
 744         unsigned short mode, poll_mode;
 745
 746         if (!np)
 747                 return -ENODEV;
 748
 749         if (of_device_is_compatible(np, "fsl,etsec2")) {
 750                 mode = MQ_MG_MODE;
 751                 poll_mode = GFAR_SQ_POLLING;
 752         } else {
 753                 mode = SQ_SG_MODE;
 754                 poll_mode = GFAR_SQ_POLLING;
 755         }
 756
 757         if (mode == SQ_SG_MODE) {
 758                 num_tx_qs = 1;
 759                 num_rx_qs = 1;
 760         } else { /* MQ_MG_MODE */
 761                 /* get the actual number of supported groups */
 762                 unsigned int num_grps = gfar_of_group_count(np);
 763
 764                 if (num_grps == 0 || num_grps > MAXGROUPS) {
 765                         dev_err(&ofdev->dev, "Invalid # of int groups(%d)\n",
 766                                 num_grps);
 767                         pr_err("Cannot do alloc_etherdev, aborting\n");
 768                         return -EINVAL;
 769                 }
 770
 771                 if (poll_mode == GFAR_SQ_POLLING) {
 772                         num_tx_qs = num_grps; /* one txq per int group */
 773                         num_rx_qs = num_grps; /* one rxq per int group */
 774                 } else { /* GFAR_MQ_POLLING */
 775                         u32 tx_queues, rx_queues;
 776                         int ret;
 777
 778                         /* parse the num of HW tx and rx queues */
 779                         ret = of_property_read_u32(np, "fsl,num_tx_queues",
 780                                                    &tx_queues);
 781                         num_tx_qs = ret ? 1 : tx_queues;
 782
 783                         ret = of_property_read_u32(np, "fsl,num_rx_queues",
 784                                                    &rx_queues);
 785                         num_rx_qs = ret ? 1 : rx_queues;
 786                 }
 787         }
 788
 789         if (num_tx_qs > MAX_TX_QS) {
 790                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 791                        num_tx_qs, MAX_TX_QS);
 792                 pr_err("Cannot do alloc_etherdev, aborting\n");
 793                 return -EINVAL;
 794         }
 795
 796         if (num_rx_qs > MAX_RX_QS) {
 797                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 798                        num_rx_qs, MAX_RX_QS);
 799                 pr_err("Cannot do alloc_etherdev, aborting\n");
 800                 return -EINVAL;
 801         }
 802
 803         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 804         dev = *pdev;
 805         if (NULL == dev)
 806                 return -ENOMEM;
 807
 808         priv = netdev_priv(dev);
 809         priv->ndev = dev;
 810
 811         priv->mode = mode;
 812         priv->poll_mode = poll_mode;
 813
 814         priv->num_tx_queues = num_tx_qs;
 815         netif_set_real_num_rx_queues(dev, num_rx_qs);
 816         priv->num_rx_queues = num_rx_qs;
 817
 818         err = gfar_alloc_tx_queues(priv);
 819         if (err)
 820                 goto tx_alloc_failed;
 821
 822         err = gfar_alloc_rx_queues(priv);
 823         if (err)
 824                 goto rx_alloc_failed;
 825
 826         err = of_property_read_string(np, "model", &model);
 827         if (err) {
 828                 pr_err("Device model property missing, aborting\n");
 829                 goto rx_alloc_failed;
 830         }
 831
 832         /* Init Rx queue filer rule set linked list */
 833         INIT_LIST_HEAD(&priv->rx_list.list);
 834         priv->rx_list.count = 0;
 835         mutex_init(&priv->rx_queue_access);
 836
 837         for (i = 0; i < MAXGROUPS; i++)
 838                 priv->gfargrp[i].regs = NULL;
 839
 840         /* Parse and initialize group specific information */
 841         if (priv->mode == MQ_MG_MODE) {
 842                 for_each_available_child_of_node(np, child) {
 843                         if (of_node_cmp(child->name, "queue-group"))
 844                                 continue;
 845
 846                         err = gfar_parse_group(child, priv, model);
 847                         if (err)
 848                                 goto err_grp_init;
 849                 }
 850         } else { /* SQ_SG_MODE */
 851                 err = gfar_parse_group(np, priv, model);
 852                 if (err)
 853                         goto err_grp_init;
 854         }
 855
 856         if (of_property_read_bool(np, "bd-stash")) {
 857                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 858                 priv->bd_stash_en = 1;
 859         }
 860
 861         err = of_property_read_u32(np, "rx-stash-len", &stash_len);
 862
 863         if (err == 0)
 864                 priv->rx_stash_size = stash_len;
 865
 866         err = of_property_read_u32(np, "rx-stash-idx", &stash_idx);
 867
 868         if (err == 0)
 869                 priv->rx_stash_index = stash_idx;
 870
 871         if (stash_len || stash_idx)
 872                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 873
 874         mac_addr = of_get_mac_address(np);
 875
 876         if (mac_addr)
 877                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 878
 879         if (model && !strcasecmp(model, "TSEC"))
 880                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 881                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 882                                      FSL_GIANFAR_DEV_HAS_RMON |
 883                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 884
 885         if (model && !strcasecmp(model, "eTSEC"))
 886                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
 887                                      FSL_GIANFAR_DEV_HAS_COALESCE |
 888                                      FSL_GIANFAR_DEV_HAS_RMON |
 889                                      FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 890                                      FSL_GIANFAR_DEV_HAS_CSUM |
 891                                      FSL_GIANFAR_DEV_HAS_VLAN |
 892                                      FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 893                                      FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 894                                      FSL_GIANFAR_DEV_HAS_TIMER |
 895                                      FSL_GIANFAR_DEV_HAS_RX_FILER;
 896
 897         err = of_property_read_string(np, "phy-connection-type", &ctype);
 898
 899         /* We only care about rgmii-id.  The rest are autodetected */
 900         if (err == 0 && !strcmp(ctype, "rgmii-id"))
 901                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 902         else
 903                 priv->interface = PHY_INTERFACE_MODE_MII;
 904
 905         if (of_find_property(np, "fsl,magic-packet", NULL))
 906                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 907
 908         if (of_get_property(np, "fsl,wake-on-filer", NULL))
 909                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER;
 910
 911         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 912
 913         /* In the case of a fixed PHY, the DT node associated
 914          * to the PHY is the Ethernet MAC DT node.
 915          */
 916         if (!priv->phy_node && of_phy_is_fixed_link(np)) {
 917                 err = of_phy_register_fixed_link(np);
 918                 if (err)
 919                         goto err_grp_init;
 920
 921                 priv->phy_node = of_node_get(np);
 922         }
 923
 924         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 925         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 926
 927         return 0;
 928
 929 err_grp_init:
 930         unmap_group_regs(priv);
 931 rx_alloc_failed:
 932         gfar_free_rx_queues(priv);
 933 tx_alloc_failed:
 934         gfar_free_tx_queues(priv);
 935         free_gfar_dev(priv);
 936         return err;
 937 }
 938
 939 static int gfar_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
 940 {
 941         struct hwtstamp_config config;
 942         struct gfar_private *priv = netdev_priv(netdev);
 943
 944         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 945                 return -EFAULT;
 946
 947         /* reserved for future extensions */
 948         if (config.flags)
 949                 return -EINVAL;
 950
 951         switch (config.tx_type) {
 952         case HWTSTAMP_TX_OFF:
 953                 priv->hwts_tx_en = 0;
 954                 break;
 955         case HWTSTAMP_TX_ON:
 956                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 957                         return -ERANGE;
 958                 priv->hwts_tx_en = 1;
 959                 break;
 960         default:
 961                 return -ERANGE;
 962         }
 963
 964         switch (config.rx_filter) {
 965         case HWTSTAMP_FILTER_NONE:
 966                 if (priv->hwts_rx_en) {
 967                         priv->hwts_rx_en = 0;
 968                         reset_gfar(netdev);
 969                 }
 970                 break;
 971         default:
 972                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 973                         return -ERANGE;
 974                 if (!priv->hwts_rx_en) {
 975                         priv->hwts_rx_en = 1;
 976                         reset_gfar(netdev);
 977                 }
 978                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 979                 break;
 980         }
 981
 982         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 983                 -EFAULT : 0;
 984 }
 985
 986 static int gfar_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
 987 {
 988         struct hwtstamp_config config;
 989         struct gfar_private *priv = netdev_priv(netdev);
 990
 991         config.flags = 0;
 992         config.tx_type = priv->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
 993         config.rx_filter = (priv->hwts_rx_en ?
 994                             HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE);
 995
 996         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 997                 -EFAULT : 0;
 998 }
 999
1000 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1001 {
1002         struct phy_device *phydev = dev->phydev;
1003
1004         if (!netif_running(dev))
1005                 return -EINVAL;
1006
1007         if (cmd == SIOCSHWTSTAMP)
1008                 return gfar_hwtstamp_set(dev, rq);
1009         if (cmd == SIOCGHWTSTAMP)
1010                 return gfar_hwtstamp_get(dev, rq);
1011
1012         if (!phydev)
1013                 return -ENODEV;
1014
1015         return phy_mii_ioctl(phydev, rq, cmd);
1016 }
1017
1018 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
1019                                    u32 class)
1020 {
1021         u32 rqfpr = FPR_FILER_MASK;
1022         u32 rqfcr = 0x0;
1023
1024         rqfar--;
1025         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
1026         priv->ftp_rqfpr[rqfar] = rqfpr;
1027         priv->ftp_rqfcr[rqfar] = rqfcr;
1028         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1029
1030         rqfar--;
1031         rqfcr = RQFCR_CMP_NOMATCH;
1032         priv->ftp_rqfpr[rqfar] = rqfpr;
1033         priv->ftp_rqfcr[rqfar] = rqfcr;
1034         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1035
1036         rqfar--;
1037         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
1038         rqfpr = class;
1039         priv->ftp_rqfcr[rqfar] = rqfcr;
1040         priv->ftp_rqfpr[rqfar] = rqfpr;
1041         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1042
1043         rqfar--;
1044         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
1045         rqfpr = class;
1046         priv->ftp_rqfcr[rqfar] = rqfcr;
1047         priv->ftp_rqfpr[rqfar] = rqfpr;
1048         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1049
1050         return rqfar;
1051 }
1052
1053 static void gfar_init_filer_table(struct gfar_private *priv)
1054 {
1055         int i = 0x0;
1056         u32 rqfar = MAX_FILER_IDX;
1057         u32 rqfcr = 0x0;
1058         u32 rqfpr = FPR_FILER_MASK;
1059
1060         /* Default rule */
1061         rqfcr = RQFCR_CMP_MATCH;
1062         priv->ftp_rqfcr[rqfar] = rqfcr;
1063         priv->ftp_rqfpr[rqfar] = rqfpr;
1064         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
1065
1066         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
1067         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
1068         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
1069         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
1070         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
1071         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
1072
1073         /* cur_filer_idx indicated the first non-masked rule */
1074         priv->cur_filer_idx = rqfar;
1075
1076         /* Rest are masked rules */
1077         rqfcr = RQFCR_CMP_NOMATCH;
1078         for (i = 0; i < rqfar; i++) {
1079                 priv->ftp_rqfcr[i] = rqfcr;
1080                 priv->ftp_rqfpr[i] = rqfpr;
1081                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1082         }
1083 }
1084
1085 #ifdef CONFIG_PPC
1086 static void __gfar_detect_errata_83xx(struct gfar_private *priv)
1087 {
1088         unsigned int pvr = mfspr(SPRN_PVR);
1089         unsigned int svr = mfspr(SPRN_SVR);
1090         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
1091         unsigned int rev = svr & 0xffff;
1092
1093         /* MPC8313 Rev 2.0 and higher; All MPC837x */
1094         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
1095             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1096                 priv->errata |= GFAR_ERRATA_74;
1097
1098         /* MPC8313 and MPC837x all rev */
1099         if ((pvr == 0x80850010 && mod == 0x80b0) ||
1100             (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
1101                 priv->errata |= GFAR_ERRATA_76;
1102
1103         /* MPC8313 Rev < 2.0 */
1104         if (pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020)
1105                 priv->errata |= GFAR_ERRATA_12;
1106 }
1107
1108 static void __gfar_detect_errata_85xx(struct gfar_private *priv)
1109 {
1110         unsigned int svr = mfspr(SPRN_SVR);
1111
1112         if ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20))
1113                 priv->errata |= GFAR_ERRATA_12;
1114         /* P2020/P1010 Rev 1; MPC8548 Rev 2 */
1115         if (((SVR_SOC_VER(svr) == SVR_P2020) && (SVR_REV(svr) < 0x20)) ||
1116             ((SVR_SOC_VER(svr) == SVR_P2010) && (SVR_REV(svr) < 0x20)) ||
1117             ((SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) < 0x31)))
1118                 priv->errata |= GFAR_ERRATA_76; /* aka eTSEC 20 */
1119 }
1120 #endif
1121
1122 static void gfar_detect_errata(struct gfar_private *priv)
1123 {
1124         struct device *dev = &priv->ofdev->dev;
1125
1126         /* no plans to fix */
1127         priv->errata |= GFAR_ERRATA_A002;
1128
1129 #ifdef CONFIG_PPC
1130         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2))
1131                 __gfar_detect_errata_85xx(priv);
1132         else /* non-mpc85xx parts, i.e. e300 core based */
1133                 __gfar_detect_errata_83xx(priv);
1134 #endif
1135
1136         if (priv->errata)
1137                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
1138                          priv->errata);
1139 }
1140
1141 void gfar_mac_reset(struct gfar_private *priv)
1142 {
1143         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1144         u32 tempval;
1145
1146         /* Reset MAC layer */
1147         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1148
1149         /* We need to delay at least 3 TX clocks */
1150         udelay(3);
1151
1152         /* the soft reset bit is not self-resetting, so we need to
1153          * clear it before resuming normal operation
1154          */
1155         gfar_write(&regs->maccfg1, 0);
1156
1157         udelay(3);
1158
1159         gfar_rx_offload_en(priv);
1160
1161         /* Initialize the max receive frame/buffer lengths */
1162         gfar_write(&regs->maxfrm, GFAR_JUMBO_FRAME_SIZE);
1163         gfar_write(&regs->mrblr, GFAR_RXB_SIZE);
1164
1165         /* Initialize the Minimum Frame Length Register */
1166         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1167
1168         /* Initialize MACCFG2. */
1169         tempval = MACCFG2_INIT_SETTINGS;
1170
1171         /* eTSEC74 erratum: Rx frames of length MAXFRM or MAXFRM-1
1172          * are marked as truncated.  Avoid this by MACCFG2[Huge Frame]=1,
1173          * and by checking RxBD[LG] and discarding larger than MAXFRM.
1174          */
1175         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1176                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1177
1178         gfar_write(&regs->maccfg2, tempval);
1179
1180         /* Clear mac addr hash registers */
1181         gfar_write(&regs->igaddr0, 0);
1182         gfar_write(&regs->igaddr1, 0);
1183         gfar_write(&regs->igaddr2, 0);
1184         gfar_write(&regs->igaddr3, 0);
1185         gfar_write(&regs->igaddr4, 0);
1186         gfar_write(&regs->igaddr5, 0);
1187         gfar_write(&regs->igaddr6, 0);
1188         gfar_write(&regs->igaddr7, 0);
1189
1190         gfar_write(&regs->gaddr0, 0);
1191         gfar_write(&regs->gaddr1, 0);
1192         gfar_write(&regs->gaddr2, 0);
1193         gfar_write(&regs->gaddr3, 0);
1194         gfar_write(&regs->gaddr4, 0);
1195         gfar_write(&regs->gaddr5, 0);
1196         gfar_write(&regs->gaddr6, 0);
1197         gfar_write(&regs->gaddr7, 0);
1198
1199         if (priv->extended_hash)
1200                 gfar_clear_exact_match(priv->ndev);
1201
1202         gfar_mac_rx_config(priv);
1203
1204         gfar_mac_tx_config(priv);
1205
1206         gfar_set_mac_address(priv->ndev);
1207
1208         gfar_set_multi(priv->ndev);
1209
1210         /* clear ievent and imask before configuring coalescing */
1211         gfar_ints_disable(priv);
1212
1213         /* Configure the coalescing support */
1214         gfar_configure_coalescing_all(priv);
1215 }
1216
1217 static void gfar_hw_init(struct gfar_private *priv)
1218 {
1219         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1220         u32 attrs;
1221
1222         /* Stop the DMA engine now, in case it was running before
1223          * (The firmware could have used it, and left it running).
1224          */
1225         gfar_halt(priv);
1226
1227         gfar_mac_reset(priv);
1228
1229         /* Zero out the rmon mib registers if it has them */
1230         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1231                 memset_io(&(regs->rmon), 0, sizeof(struct rmon_mib));
1232
1233                 /* Mask off the CAM interrupts */
1234                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1235                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1236         }
1237
1238         /* Initialize ECNTRL */
1239         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1240
1241         /* Set the extraction length and index */
1242         attrs = ATTRELI_EL(priv->rx_stash_size) |
1243                 ATTRELI_EI(priv->rx_stash_index);
1244
1245         gfar_write(&regs->attreli, attrs);
1246
1247         /* Start with defaults, and add stashing
1248          * depending on driver parameters
1249          */
1250         attrs = ATTR_INIT_SETTINGS;
1251
1252         if (priv->bd_stash_en)
1253                 attrs |= ATTR_BDSTASH;
1254
1255         if (priv->rx_stash_size != 0)
1256                 attrs |= ATTR_BUFSTASH;
1257
1258         gfar_write(&regs->attr, attrs);
1259
1260         /* FIFO configs */
1261         gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1262         gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1263         gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1264
1265         /* Program the interrupt steering regs, only for MG devices */
1266         if (priv->num_grps > 1)
1267                 gfar_write_isrg(priv);
1268 }
1269
1270 static void gfar_init_addr_hash_table(struct gfar_private *priv)
1271 {
1272         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1273
1274         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1275                 priv->extended_hash = 1;
1276                 priv->hash_width = 9;
1277
1278                 priv->hash_regs[0] = &regs->igaddr0;
1279                 priv->hash_regs[1] = &regs->igaddr1;
1280                 priv->hash_regs[2] = &regs->igaddr2;
1281                 priv->hash_regs[3] = &regs->igaddr3;
1282                 priv->hash_regs[4] = &regs->igaddr4;
1283                 priv->hash_regs[5] = &regs->igaddr5;
1284                 priv->hash_regs[6] = &regs->igaddr6;
1285                 priv->hash_regs[7] = &regs->igaddr7;
1286                 priv->hash_regs[8] = &regs->gaddr0;
1287                 priv->hash_regs[9] = &regs->gaddr1;
1288                 priv->hash_regs[10] = &regs->gaddr2;
1289                 priv->hash_regs[11] = &regs->gaddr3;
1290                 priv->hash_regs[12] = &regs->gaddr4;
1291                 priv->hash_regs[13] = &regs->gaddr5;
1292                 priv->hash_regs[14] = &regs->gaddr6;
1293                 priv->hash_regs[15] = &regs->gaddr7;
1294
1295         } else {
1296                 priv->extended_hash = 0;
1297                 priv->hash_width = 8;
1298
1299                 priv->hash_regs[0] = &regs->gaddr0;
1300                 priv->hash_regs[1] = &regs->gaddr1;
1301                 priv->hash_regs[2] = &regs->gaddr2;
1302                 priv->hash_regs[3] = &regs->gaddr3;
1303                 priv->hash_regs[4] = &regs->gaddr4;
1304                 priv->hash_regs[5] = &regs->gaddr5;
1305                 priv->hash_regs[6] = &regs->gaddr6;
1306                 priv->hash_regs[7] = &regs->gaddr7;
1307         }
1308 }
1309
1310 /* Set up the ethernet device structure, private data,
1311  * and anything else we need before we start
1312  */
1313 static int gfar_probe(struct platform_device *ofdev)
1314 {
1315         struct device_node *np = ofdev->dev.of_node;
1316         struct net_device *dev = NULL;
1317         struct gfar_private *priv = NULL;
1318         int err = 0, i;
1319
1320         err = gfar_of_init(ofdev, &dev);
1321
1322         if (err)
1323                 return err;
1324
1325         priv = netdev_priv(dev);
1326         priv->ndev = dev;
1327         priv->ofdev = ofdev;
1328         priv->dev = &ofdev->dev;
1329         SET_NETDEV_DEV(dev, &ofdev->dev);
1330
1331         INIT_WORK(&priv->reset_task, gfar_reset_task);
1332
1333         platform_set_drvdata(ofdev, priv);
1334
1335         gfar_detect_errata(priv);
1336
1337         /* Set the dev->base_addr to the gfar reg region */
1338         dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1339
1340         /* Fill in the dev structure */
1341         dev->watchdog_timeo = TX_TIMEOUT;
1342         dev->mtu = 1500;
1343         dev->netdev_ops = &gfar_netdev_ops;
1344         dev->ethtool_ops = &gfar_ethtool_ops;
1345
1346         /* Register for napi ...We are registering NAPI for each grp */
1347         for (i = 0; i < priv->num_grps; i++) {
1348                 if (priv->poll_mode == GFAR_SQ_POLLING) {
1349                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1350                                        gfar_poll_rx_sq, GFAR_DEV_WEIGHT);
1351                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1352                                        gfar_poll_tx_sq, 2);
1353                 } else {
1354                         netif_napi_add(dev, &priv->gfargrp[i].napi_rx,
1355                                        gfar_poll_rx, GFAR_DEV_WEIGHT);
1356                         netif_tx_napi_add(dev, &priv->gfargrp[i].napi_tx,
1357                                        gfar_poll_tx, 2);
1358                 }
1359         }
1360
1361         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1362                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1363                                    NETIF_F_RXCSUM;
1364                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1365                                  NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1366         }
1367
1368         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1369                 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1370                                     NETIF_F_HW_VLAN_CTAG_RX;
1371                 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1372         }
1373
1374         dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
1375
1376         gfar_init_addr_hash_table(priv);
1377
1378         /* Insert receive time stamps into padding alignment bytes */
1379         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1380                 priv->padding = 8;
1381
1382         if (dev->features & NETIF_F_IP_CSUM ||
1383             priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1384                 dev->needed_headroom = GMAC_FCB_LEN;
1385
1386         /* Initializing some of the rx/tx queue level parameters */
1387         for (i = 0; i < priv->num_tx_queues; i++) {
1388                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1389                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1390                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1391                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1392         }
1393
1394         for (i = 0; i < priv->num_rx_queues; i++) {
1395                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1396                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1397                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1398         }
1399
1400         /* Always enable rx filer if available */
1401         priv->rx_filer_enable =
1402             (priv->device_flags & FSL_GIANFAR_DEV_HAS_RX_FILER) ? 1 : 0;
1403         /* Enable most messages by default */
1404         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1405         /* use pritority h/w tx queue scheduling for single queue devices */
1406         if (priv->num_tx_queues == 1)
1407                 priv->prio_sched_en = 1;
1408
1409         set_bit(GFAR_DOWN, &priv->state);
1410
1411         gfar_hw_init(priv);
1412
1413         /* Carrier starts down, phylib will bring it up */
1414         netif_carrier_off(dev);
1415
1416         err = register_netdev(dev);
1417
1418         if (err) {
1419                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1420                 goto register_fail;
1421         }
1422
1423         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET)
1424                 priv->wol_supported |= GFAR_WOL_MAGIC;
1425
1426         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_WAKE_ON_FILER) &&
1427             priv->rx_filer_enable)
1428                 priv->wol_supported |= GFAR_WOL_FILER_UCAST;
1429
1430         device_set_wakeup_capable(&ofdev->dev, priv->wol_supported);
1431
1432         /* fill out IRQ number and name fields */
1433         for (i = 0; i < priv->num_grps; i++) {
1434                 struct gfar_priv_grp *grp = &priv->gfargrp[i];
1435                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1436                         sprintf(gfar_irq(grp, TX)->name, "%s%s%c%s",
1437                                 dev->name, "_g", '0' + i, "_tx");
1438                         sprintf(gfar_irq(grp, RX)->name, "%s%s%c%s",
1439                                 dev->name, "_g", '0' + i, "_rx");
1440                         sprintf(gfar_irq(grp, ER)->name, "%s%s%c%s",
1441                                 dev->name, "_g", '0' + i, "_er");
1442                 } else
1443                         strcpy(gfar_irq(grp, TX)->name, dev->name);
1444         }
1445
1446         /* Initialize the filer table */
1447         gfar_init_filer_table(priv);
1448
1449         /* Print out the device info */
1450         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1451
1452         /* Even more device info helps when determining which kernel
1453          * provided which set of benchmarks.
1454          */
1455         netdev_info(dev, "Running with NAPI enabled\n");
1456         for (i = 0; i < priv->num_rx_queues; i++)
1457                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1458                             i, priv->rx_queue[i]->rx_ring_size);
1459         for (i = 0; i < priv->num_tx_queues; i++)
1460                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1461                             i, priv->tx_queue[i]->tx_ring_size);
1462
1463         return 0;
1464
1465 register_fail:
1466         if (of_phy_is_fixed_link(np))
1467                 of_phy_deregister_fixed_link(np);
1468         unmap_group_regs(priv);
1469         gfar_free_rx_queues(priv);
1470         gfar_free_tx_queues(priv);
1471         of_node_put(priv->phy_node);
1472         of_node_put(priv->tbi_node);
1473         free_gfar_dev(priv);
1474         return err;
1475 }
1476
1477 static int gfar_remove(struct platform_device *ofdev)
1478 {
1479         struct gfar_private *priv = platform_get_drvdata(ofdev);
1480         struct device_node *np = ofdev->dev.of_node;
1481
1482         of_node_put(priv->phy_node);
1483         of_node_put(priv->tbi_node);
1484
1485         unregister_netdev(priv->ndev);
1486
1487         if (of_phy_is_fixed_link(np))
1488                 of_phy_deregister_fixed_link(np);
1489
1490         unmap_group_regs(priv);
1491         gfar_free_rx_queues(priv);
1492         gfar_free_tx_queues(priv);
1493         free_gfar_dev(priv);
1494
1495         return 0;
1496 }
1497
1498 #ifdef CONFIG_PM
1499
1500 static void __gfar_filer_disable(struct gfar_private *priv)
1501 {
1502         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1503         u32 temp;
1504
1505         temp = gfar_read(&regs->rctrl);
1506         temp &= ~(RCTRL_FILREN | RCTRL_PRSDEP_INIT);
1507         gfar_write(&regs->rctrl, temp);
1508 }
1509
1510 static void __gfar_filer_enable(struct gfar_private *priv)
1511 {
1512         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1513         u32 temp;
1514
1515         temp = gfar_read(&regs->rctrl);
1516         temp |= RCTRL_FILREN | RCTRL_PRSDEP_INIT;
1517         gfar_write(&regs->rctrl, temp);
1518 }
1519
1520 /* Filer rules implementing wol capabilities */
1521 static void gfar_filer_config_wol(struct gfar_private *priv)
1522 {
1523         unsigned int i;
1524         u32 rqfcr;
1525
1526         __gfar_filer_disable(priv);
1527
1528         /* clear the filer table, reject any packet by default */
1529         rqfcr = RQFCR_RJE | RQFCR_CMP_MATCH;
1530         for (i = 0; i <= MAX_FILER_IDX; i++)
1531                 gfar_write_filer(priv, i, rqfcr, 0);
1532
1533         i = 0;
1534         if (priv->wol_opts & GFAR_WOL_FILER_UCAST) {
1535                 /* unicast packet, accept it */
1536                 struct net_device *ndev = priv->ndev;
1537                 /* get the default rx queue index */
1538                 u8 qindex = (u8)priv->gfargrp[0].rx_queue->qindex;
1539                 u32 dest_mac_addr = (ndev->dev_addr[0] << 16) |
1540                                     (ndev->dev_addr[1] << 8) |
1541                                      ndev->dev_addr[2];
1542
1543                 rqfcr = (qindex << 10) | RQFCR_AND |
1544                         RQFCR_CMP_EXACT | RQFCR_PID_DAH;
1545
1546                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1547
1548                 dest_mac_addr = (ndev->dev_addr[3] << 16) |
1549                                 (ndev->dev_addr[4] << 8) |
1550                                  ndev->dev_addr[5];
1551                 rqfcr = (qindex << 10) | RQFCR_GPI |
1552                         RQFCR_CMP_EXACT | RQFCR_PID_DAL;
1553                 gfar_write_filer(priv, i++, rqfcr, dest_mac_addr);
1554         }
1555
1556         __gfar_filer_enable(priv);
1557 }
1558
1559 static void gfar_filer_restore_table(struct gfar_private *priv)
1560 {
1561         u32 rqfcr, rqfpr;
1562         unsigned int i;
1563
1564         __gfar_filer_disable(priv);
1565
1566         for (i = 0; i <= MAX_FILER_IDX; i++) {
1567                 rqfcr = priv->ftp_rqfcr[i];
1568                 rqfpr = priv->ftp_rqfpr[i];
1569                 gfar_write_filer(priv, i, rqfcr, rqfpr);
1570         }
1571
1572         __gfar_filer_enable(priv);
1573 }
1574
1575 /* gfar_start() for Rx only and with the FGPI filer interrupt enabled */
1576 static void gfar_start_wol_filer(struct gfar_private *priv)
1577 {
1578         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1579         u32 tempval;
1580         int i = 0;
1581
1582         /* Enable Rx hw queues */
1583         gfar_write(&regs->rqueue, priv->rqueue);
1584
1585         /* Initialize DMACTRL to have WWR and WOP */
1586         tempval = gfar_read(&regs->dmactrl);
1587         tempval |= DMACTRL_INIT_SETTINGS;
1588         gfar_write(&regs->dmactrl, tempval);
1589
1590         /* Make sure we aren't stopped */
1591         tempval = gfar_read(&regs->dmactrl);
1592         tempval &= ~DMACTRL_GRS;
1593         gfar_write(&regs->dmactrl, tempval);
1594
1595         for (i = 0; i < priv->num_grps; i++) {
1596                 regs = priv->gfargrp[i].regs;
1597                 /* Clear RHLT, so that the DMA starts polling now */
1598                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1599                 /* enable the Filer General Purpose Interrupt */
1600                 gfar_write(&regs->imask, IMASK_FGPI);
1601         }
1602
1603         /* Enable Rx DMA */
1604         tempval = gfar_read(&regs->maccfg1);
1605         tempval |= MACCFG1_RX_EN;
1606         gfar_write(&regs->maccfg1, tempval);
1607 }
1608
1609 static int gfar_suspend(struct device *dev)
1610 {
1611         struct gfar_private *priv = dev_get_drvdata(dev);
1612         struct net_device *ndev = priv->ndev;
1613         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1614         u32 tempval;
1615         u16 wol = priv->wol_opts;
1616
1617         if (!netif_running(ndev))
1618                 return 0;
1619
1620         disable_napi(priv);
1621         netif_tx_lock(ndev);
1622         netif_device_detach(ndev);
1623         netif_tx_unlock(ndev);
1624
1625         gfar_halt(priv);
1626
1627         if (wol & GFAR_WOL_MAGIC) {
1628                 /* Enable interrupt on Magic Packet */
1629                 gfar_write(&regs->imask, IMASK_MAG);
1630
1631                 /* Enable Magic Packet mode */
1632                 tempval = gfar_read(&regs->maccfg2);
1633                 tempval |= MACCFG2_MPEN;
1634                 gfar_write(&regs->maccfg2, tempval);
1635
1636                 /* re-enable the Rx block */
1637                 tempval = gfar_read(&regs->maccfg1);
1638                 tempval |= MACCFG1_RX_EN;
1639                 gfar_write(&regs->maccfg1, tempval);
1640
1641         } else if (wol & GFAR_WOL_FILER_UCAST) {
1642                 gfar_filer_config_wol(priv);
1643                 gfar_start_wol_filer(priv);
1644
1645         } else {
1646                 phy_stop(ndev->phydev);
1647         }
1648
1649         return 0;
1650 }
1651
1652 static int gfar_resume(struct device *dev)
1653 {
1654         struct gfar_private *priv = dev_get_drvdata(dev);
1655         struct net_device *ndev = priv->ndev;
1656         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1657         u32 tempval;
1658         u16 wol = priv->wol_opts;
1659
1660         if (!netif_running(ndev))
1661                 return 0;
1662
1663         if (wol & GFAR_WOL_MAGIC) {
1664                 /* Disable Magic Packet mode */
1665                 tempval = gfar_read(&regs->maccfg2);
1666                 tempval &= ~MACCFG2_MPEN;
1667                 gfar_write(&regs->maccfg2, tempval);
1668
1669         } else if (wol & GFAR_WOL_FILER_UCAST) {
1670                 /* need to stop rx only, tx is already down */
1671                 gfar_halt(priv);
1672                 gfar_filer_restore_table(priv);
1673
1674         } else {
1675                 phy_start(ndev->phydev);
1676         }
1677
1678         gfar_start(priv);
1679
1680         netif_device_attach(ndev);
1681         enable_napi(priv);
1682
1683         return 0;
1684 }
1685
1686 static int gfar_restore(struct device *dev)
1687 {
1688         struct gfar_private *priv = dev_get_drvdata(dev);
1689         struct net_device *ndev = priv->ndev;
1690
1691         if (!netif_running(ndev)) {
1692                 netif_device_attach(ndev);
1693
1694                 return 0;
1695         }
1696
1697         gfar_init_bds(ndev);
1698
1699         gfar_mac_reset(priv);
1700
1701         gfar_init_tx_rx_base(priv);
1702
1703         gfar_start(priv);
1704
1705         priv->oldlink = 0;
1706         priv->oldspeed = 0;
1707         priv->oldduplex = -1;
1708
1709         if (ndev->phydev)
1710                 phy_start(ndev->phydev);
1711
1712         netif_device_attach(ndev);
1713         enable_napi(priv);
1714
1715         return 0;
1716 }
1717
1718 static struct dev_pm_ops gfar_pm_ops = {
1719         .suspend = gfar_suspend,
1720         .resume = gfar_resume,
1721         .freeze = gfar_suspend,
1722         .thaw = gfar_resume,
1723         .restore = gfar_restore,
1724 };
1725
1726 #define GFAR_PM_OPS (&gfar_pm_ops)
1727
1728 #else
1729
1730 #define GFAR_PM_OPS NULL
1731
1732 #endif
1733
1734 /* Reads the controller's registers to determine what interface
1735  * connects it to the PHY.
1736  */
1737 static phy_interface_t gfar_get_interface(struct net_device *dev)
1738 {
1739         struct gfar_private *priv = netdev_priv(dev);
1740         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1741         u32 ecntrl;
1742
1743         ecntrl = gfar_read(&regs->ecntrl);
1744
1745         if (ecntrl & ECNTRL_SGMII_MODE)
1746                 return PHY_INTERFACE_MODE_SGMII;
1747
1748         if (ecntrl & ECNTRL_TBI_MODE) {
1749                 if (ecntrl & ECNTRL_REDUCED_MODE)
1750                         return PHY_INTERFACE_MODE_RTBI;
1751                 else
1752                         return PHY_INTERFACE_MODE_TBI;
1753         }
1754
1755         if (ecntrl & ECNTRL_REDUCED_MODE) {
1756                 if (ecntrl & ECNTRL_REDUCED_MII_MODE) {
1757                         return PHY_INTERFACE_MODE_RMII;
1758                 }
1759                 else {
1760                         phy_interface_t interface = priv->interface;
1761
1762                         /* This isn't autodetected right now, so it must
1763                          * be set by the device tree or platform code.
1764                          */
1765                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1766                                 return PHY_INTERFACE_MODE_RGMII_ID;
1767
1768                         return PHY_INTERFACE_MODE_RGMII;
1769                 }
1770         }
1771
1772         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1773                 return PHY_INTERFACE_MODE_GMII;
1774
1775         return PHY_INTERFACE_MODE_MII;
1776 }
1777
1778
1779 /* Initializes driver's PHY state, and attaches to the PHY.
1780  * Returns 0 on success.
1781  */
1782 static int init_phy(struct net_device *dev)
1783 {
1784         struct gfar_private *priv = netdev_priv(dev);
1785         uint gigabit_support =
1786                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1787                 GFAR_SUPPORTED_GBIT : 0;
1788         phy_interface_t interface;
1789         struct phy_device *phydev;
1790
1791         priv->oldlink = 0;
1792         priv->oldspeed = 0;
1793         priv->oldduplex = -1;
1794
1795         interface = gfar_get_interface(dev);
1796
1797         phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1798                                 interface);
1799         if (!phydev) {
1800                 dev_err(&dev->dev, "could not attach to PHY\n");
1801                 return -ENODEV;
1802         }
1803
1804         if (interface == PHY_INTERFACE_MODE_SGMII)
1805                 gfar_configure_serdes(dev);
1806
1807         /* Remove any features not supported by the controller */
1808         phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1809         phydev->advertising = phydev->supported;
1810
1811         /* Add support for flow control, but don't advertise it by default */
1812         phydev->supported |= (SUPPORTED_Pause | SUPPORTED_Asym_Pause);
1813
1814         return 0;
1815 }
1816
1817 /* Initialize TBI PHY interface for communicating with the
1818  * SERDES lynx PHY on the chip.  We communicate with this PHY
1819  * through the MDIO bus on each controller, treating it as a
1820  * "normal" PHY at the address found in the TBIPA register.  We assume
1821  * that the TBIPA register is valid.  Either the MDIO bus code will set
1822  * it to a value that doesn't conflict with other PHYs on the bus, or the
1823  * value doesn't matter, as there are no other PHYs on the bus.
1824  */
1825 static void gfar_configure_serdes(struct net_device *dev)
1826 {
1827         struct gfar_private *priv = netdev_priv(dev);
1828         struct phy_device *tbiphy;
1829
1830         if (!priv->tbi_node) {
1831                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1832                                     "device tree specify a tbi-handle\n");
1833                 return;
1834         }
1835
1836         tbiphy = of_phy_find_device(priv->tbi_node);
1837         if (!tbiphy) {
1838                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1839                 return;
1840         }
1841
1842         /* If the link is already up, we must already be ok, and don't need to
1843          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1844          * everything for us?  Resetting it takes the link down and requires
1845          * several seconds for it to come back.
1846          */
1847         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS) {
1848                 put_device(&tbiphy->mdio.dev);
1849                 return;
1850         }
1851
1852         /* Single clk mode, mii mode off(for serdes communication) */
1853         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1854
1855         phy_write(tbiphy, MII_ADVERTISE,
1856                   ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1857                   ADVERTISE_1000XPSE_ASYM);
1858
1859         phy_write(tbiphy, MII_BMCR,
1860                   BMCR_ANENABLE | BMCR_ANRESTART | BMCR_FULLDPLX |
1861                   BMCR_SPEED1000);
1862
1863         put_device(&tbiphy->mdio.dev);
1864 }
1865
1866 static int __gfar_is_rx_idle(struct gfar_private *priv)
1867 {
1868         u32 res;
1869
1870         /* Normaly TSEC should not hang on GRS commands, so we should
1871          * actually wait for IEVENT_GRSC flag.
1872          */
1873         if (!gfar_has_errata(priv, GFAR_ERRATA_A002))
1874                 return 0;
1875
1876         /* Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1877          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1878          * and the Rx can be safely reset.
1879          */
1880         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1881         res &= 0x7f807f80;
1882         if ((res & 0xffff) == (res >> 16))
1883                 return 1;
1884
1885         return 0;
1886 }
1887
1888 /* Halt the receive and transmit queues */
1889 static void gfar_halt_nodisable(struct gfar_private *priv)
1890 {
1891         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1892         u32 tempval;
1893         unsigned int timeout;
1894         int stopped;
1895
1896         gfar_ints_disable(priv);
1897
1898         if (gfar_is_dma_stopped(priv))
1899                 return;
1900
1901         /* Stop the DMA, and wait for it to stop */
1902         tempval = gfar_read(&regs->dmactrl);
1903         tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1904         gfar_write(&regs->dmactrl, tempval);
1905
1906 retry:
1907         timeout = 1000;
1908         while (!(stopped = gfar_is_dma_stopped(priv)) && timeout) {
1909                 cpu_relax();
1910                 timeout--;
1911         }
1912
1913         if (!timeout)
1914                 stopped = gfar_is_dma_stopped(priv);
1915
1916         if (!stopped && !gfar_is_rx_dma_stopped(priv) &&
1917             !__gfar_is_rx_idle(priv))
1918                 goto retry;
1919 }
1920
1921 /* Halt the receive and transmit queues */
1922 void gfar_halt(struct gfar_private *priv)
1923 {
1924         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1925         u32 tempval;
1926
1927         /* Dissable the Rx/Tx hw queues */
1928         gfar_write(&regs->rqueue, 0);
1929         gfar_write(&regs->tqueue, 0);
1930
1931         mdelay(10);
1932
1933         gfar_halt_nodisable(priv);
1934
1935         /* Disable Rx/Tx DMA */
1936         tempval = gfar_read(&regs->maccfg1);
1937         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1938         gfar_write(&regs->maccfg1, tempval);
1939 }
1940
1941 void stop_gfar(struct net_device *dev)
1942 {
1943         struct gfar_private *priv = netdev_priv(dev);
1944
1945         netif_tx_stop_all_queues(dev);
1946
1947         smp_mb__before_atomic();
1948         set_bit(GFAR_DOWN, &priv->state);
1949         smp_mb__after_atomic();
1950
1951         disable_napi(priv);
1952
1953         /* disable ints and gracefully shut down Rx/Tx DMA */
1954         gfar_halt(priv);
1955
1956         phy_stop(dev->phydev);
1957
1958         free_skb_resources(priv);
1959 }
1960
1961 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1962 {
1963         struct txbd8 *txbdp;
1964         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1965         int i, j;
1966
1967         txbdp = tx_queue->tx_bd_base;
1968
1969         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1970                 if (!tx_queue->tx_skbuff[i])
1971                         continue;
1972
1973                 dma_unmap_single(priv->dev, be32_to_cpu(txbdp->bufPtr),
1974                                  be16_to_cpu(txbdp->length), DMA_TO_DEVICE);
1975                 txbdp->lstatus = 0;
1976                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1977                      j++) {
1978                         txbdp++;
1979                         dma_unmap_page(priv->dev, be32_to_cpu(txbdp->bufPtr),
1980                                        be16_to_cpu(txbdp->length),
1981                                        DMA_TO_DEVICE);
1982                 }
1983                 txbdp++;
1984                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1985                 tx_queue->tx_skbuff[i] = NULL;
1986         }
1987         kfree(tx_queue->tx_skbuff);
1988         tx_queue->tx_skbuff = NULL;
1989 }
1990
1991 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1992 {
1993         int i;
1994
1995         struct rxbd8 *rxbdp = rx_queue->rx_bd_base;
1996
1997         if (rx_queue->skb)
1998                 dev_kfree_skb(rx_queue->skb);
1999
2000         for (i = 0; i < rx_queue->rx_ring_size; i++) {
2001                 struct  gfar_rx_buff *rxb = &rx_queue->rx_buff[i];
2002
2003                 rxbdp->lstatus = 0;
2004                 rxbdp->bufPtr = 0;
2005                 rxbdp++;
2006
2007                 if (!rxb->page)
2008                         continue;
2009
2010                 dma_unmap_single(rx_queue->dev, rxb->dma,
2011                                  PAGE_SIZE, DMA_FROM_DEVICE);
2012                 __free_page(rxb->page);
2013
2014                 rxb->page = NULL;
2015         }
2016
2017         kfree(rx_queue->rx_buff);
2018         rx_queue->rx_buff = NULL;
2019 }
2020
2021 /* If there are any tx skbs or rx skbs still around, free them.
2022  * Then free tx_skbuff and rx_skbuff
2023  */
2024 static void free_skb_resources(struct gfar_private *priv)
2025 {
2026         struct gfar_priv_tx_q *tx_queue = NULL;
2027         struct gfar_priv_rx_q *rx_queue = NULL;
2028         int i;
2029
2030         /* Go through all the buffer descriptors and free their data buffers */
2031         for (i = 0; i < priv->num_tx_queues; i++) {
2032                 struct netdev_queue *txq;
2033
2034                 tx_queue = priv->tx_queue[i];
2035                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
2036                 if (tx_queue->tx_skbuff)
2037                         free_skb_tx_queue(tx_queue);
2038                 netdev_tx_reset_queue(txq);
2039         }
2040
2041         for (i = 0; i < priv->num_rx_queues; i++) {
2042                 rx_queue = priv->rx_queue[i];
2043                 if (rx_queue->rx_buff)
2044                         free_skb_rx_queue(rx_queue);
2045         }
2046
2047         dma_free_coherent(priv->dev,
2048                           sizeof(struct txbd8) * priv->total_tx_ring_size +
2049                           sizeof(struct rxbd8) * priv->total_rx_ring_size,
2050                           priv->tx_queue[0]->tx_bd_base,
2051                           priv->tx_queue[0]->tx_bd_dma_base);
2052 }
2053
2054 void gfar_start(struct gfar_private *priv)
2055 {
2056         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2057         u32 tempval;
2058         int i = 0;
2059
2060         /* Enable Rx/Tx hw queues */
2061         gfar_write(&regs->rqueue, priv->rqueue);
2062         gfar_write(&regs->tqueue, priv->tqueue);
2063
2064         /* Initialize DMACTRL to have WWR and WOP */
2065         tempval = gfar_read(&regs->dmactrl);
2066         tempval |= DMACTRL_INIT_SETTINGS;
2067         gfar_write(&regs->dmactrl, tempval);
2068
2069         /* Make sure we aren't stopped */
2070         tempval = gfar_read(&regs->dmactrl);
2071         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
2072         gfar_write(&regs->dmactrl, tempval);
2073
2074         for (i = 0; i < priv->num_grps; i++) {
2075                 regs = priv->gfargrp[i].regs;
2076                 /* Clear THLT/RHLT, so that the DMA starts polling now */
2077                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
2078                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
2079         }
2080
2081         /* Enable Rx/Tx DMA */
2082         tempval = gfar_read(&regs->maccfg1);
2083         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
2084         gfar_write(&regs->maccfg1, tempval);
2085
2086         gfar_ints_enable(priv);
2087
2088         netif_trans_update(priv->ndev); /* prevent tx timeout */
2089 }
2090
2091 static void free_grp_irqs(struct gfar_priv_grp *grp)
2092 {
2093         free_irq(gfar_irq(grp, TX)->irq, grp);
2094         free_irq(gfar_irq(grp, RX)->irq, grp);
2095         free_irq(gfar_irq(grp, ER)->irq, grp);
2096 }
2097
2098 static int register_grp_irqs(struct gfar_priv_grp *grp)
2099 {
2100         struct gfar_private *priv = grp->priv;
2101         struct net_device *dev = priv->ndev;
2102         int err;
2103
2104         /* If the device has multiple interrupts, register for
2105          * them.  Otherwise, only register for the one
2106          */
2107         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2108                 /* Install our interrupt handlers for Error,
2109                  * Transmit, and Receive
2110                  */
2111                 err = request_irq(gfar_irq(grp, ER)->irq, gfar_error, 0,
2112                                   gfar_irq(grp, ER)->name, grp);
2113                 if (err < 0) {
2114                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2115                                   gfar_irq(grp, ER)->irq);
2116
2117                         goto err_irq_fail;
2118                 }
2119                 enable_irq_wake(gfar_irq(grp, ER)->irq);
2120
2121                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_transmit, 0,
2122                                   gfar_irq(grp, TX)->name, grp);
2123                 if (err < 0) {
2124                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2125                                   gfar_irq(grp, TX)->irq);
2126                         goto tx_irq_fail;
2127                 }
2128                 err = request_irq(gfar_irq(grp, RX)->irq, gfar_receive, 0,
2129                                   gfar_irq(grp, RX)->name, grp);
2130                 if (err < 0) {
2131                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2132                                   gfar_irq(grp, RX)->irq);
2133                         goto rx_irq_fail;
2134                 }
2135                 enable_irq_wake(gfar_irq(grp, RX)->irq);
2136
2137         } else {
2138                 err = request_irq(gfar_irq(grp, TX)->irq, gfar_interrupt, 0,
2139                                   gfar_irq(grp, TX)->name, grp);
2140                 if (err < 0) {
2141                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
2142                                   gfar_irq(grp, TX)->irq);
2143                         goto err_irq_fail;
2144                 }
2145                 enable_irq_wake(gfar_irq(grp, TX)->irq);
2146         }
2147
2148         return 0;
2149
2150 rx_irq_fail:
2151         free_irq(gfar_irq(grp, TX)->irq, grp);
2152 tx_irq_fail:
2153         free_irq(gfar_irq(grp, ER)->irq, grp);
2154 err_irq_fail:
2155         return err;
2156
2157 }
2158
2159 static void gfar_free_irq(struct gfar_private *priv)
2160 {
2161         int i;
2162
2163         /* Free the IRQs */
2164         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2165                 for (i = 0; i < priv->num_grps; i++)
2166                         free_grp_irqs(&priv->gfargrp[i]);
2167         } else {
2168                 for (i = 0; i < priv->num_grps; i++)
2169                         free_irq(gfar_irq(&priv->gfargrp[i], TX)->irq,
2170                                  &priv->gfargrp[i]);
2171         }
2172 }
2173
2174 static int gfar_request_irq(struct gfar_private *priv)
2175 {
2176         int err, i, j;
2177
2178         for (i = 0; i < priv->num_grps; i++) {
2179                 err = register_grp_irqs(&priv->gfargrp[i]);
2180                 if (err) {
2181                         for (j = 0; j < i; j++)
2182                                 free_grp_irqs(&priv->gfargrp[j]);
2183                         return err;
2184                 }
2185         }
2186
2187         return 0;
2188 }
2189
2190 /* Bring the controller up and running */
2191 int startup_gfar(struct net_device *ndev)
2192 {
2193         struct gfar_private *priv = netdev_priv(ndev);
2194         int err;
2195
2196         gfar_mac_reset(priv);
2197
2198         err = gfar_alloc_skb_resources(ndev);
2199         if (err)
2200                 return err;
2201
2202         gfar_init_tx_rx_base(priv);
2203
2204         smp_mb__before_atomic();
2205         clear_bit(GFAR_DOWN, &priv->state);
2206         smp_mb__after_atomic();
2207
2208         /* Start Rx/Tx DMA and enable the interrupts */
2209         gfar_start(priv);
2210
2211         /* force link state update after mac reset */
2212         priv->oldlink = 0;
2213         priv->oldspeed = 0;
2214         priv->oldduplex = -1;
2215
2216         phy_start(ndev->phydev);
2217
2218         enable_napi(priv);
2219
2220         netif_tx_wake_all_queues(ndev);
2221
2222         return 0;
2223 }
2224
2225 /* Called when something needs to use the ethernet device
2226  * Returns 0 for success.
2227  */
2228 static int gfar_enet_open(struct net_device *dev)
2229 {
2230         struct gfar_private *priv = netdev_priv(dev);
2231         int err;
2232
2233         err = init_phy(dev);
2234         if (err)
2235                 return err;
2236
2237         err = gfar_request_irq(priv);
2238         if (err)
2239                 return err;
2240
2241         err = startup_gfar(dev);
2242         if (err)
2243                 return err;
2244
2245         return err;
2246 }
2247
2248 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
2249 {
2250         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
2251
2252         memset(fcb, 0, GMAC_FCB_LEN);
2253
2254         return fcb;
2255 }
2256
2257 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
2258                                     int fcb_length)
2259 {
2260         /* If we're here, it's a IP packet with a TCP or UDP
2261          * payload.  We set it to checksum, using a pseudo-header
2262          * we provide
2263          */
2264         u8 flags = TXFCB_DEFAULT;
2265
2266         /* Tell the controller what the protocol is
2267          * And provide the already calculated phcs
2268          */
2269         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
2270                 flags |= TXFCB_UDP;
2271                 fcb->phcs = (__force __be16)(udp_hdr(skb)->check);
2272         } else
2273                 fcb->phcs = (__force __be16)(tcp_hdr(skb)->check);
2274
2275         /* l3os is the distance between the start of the
2276          * frame (skb->data) and the start of the IP hdr.
2277          * l4os is the distance between the start of the
2278          * l3 hdr and the l4 hdr
2279          */
2280         fcb->l3os = (u8)(skb_network_offset(skb) - fcb_length);
2281         fcb->l4os = skb_network_header_len(skb);
2282
2283         fcb->flags = flags;
2284 }
2285
2286 static inline void gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
2287 {
2288         fcb->flags |= TXFCB_VLN;
2289         fcb->vlctl = cpu_to_be16(skb_vlan_tag_get(skb));
2290 }
2291
2292 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
2293                                       struct txbd8 *base, int ring_size)
2294 {
2295         struct txbd8 *new_bd = bdp + stride;
2296
2297         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2298 }
2299
2300 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2301                                       int ring_size)
2302 {
2303         return skip_txbd(bdp, 1, base, ring_size);
2304 }
2305
2306 /* eTSEC12: csum generation not supported for some fcb offsets */
2307 static inline bool gfar_csum_errata_12(struct gfar_private *priv,
2308                                        unsigned long fcb_addr)
2309 {
2310         return (gfar_has_errata(priv, GFAR_ERRATA_12) &&
2311                (fcb_addr % 0x20) > 0x18);
2312 }
2313
2314 /* eTSEC76: csum generation for frames larger than 2500 may
2315  * cause excess delays before start of transmission
2316  */
2317 static inline bool gfar_csum_errata_76(struct gfar_private *priv,
2318                                        unsigned int len)
2319 {
2320         return (gfar_has_errata(priv, GFAR_ERRATA_76) &&
2321                (len > 2500));
2322 }
2323
2324 /* This is called by the kernel when a frame is ready for transmission.
2325  * It is pointed to by the dev->hard_start_xmit function pointer
2326  */
2327 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2328 {
2329         struct gfar_private *priv = netdev_priv(dev);
2330         struct gfar_priv_tx_q *tx_queue = NULL;
2331         struct netdev_queue *txq;
2332         struct gfar __iomem *regs = NULL;
2333         struct txfcb *fcb = NULL;
2334         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2335         u32 lstatus;
2336         skb_frag_t *frag;
2337         int i, rq = 0;
2338         int do_tstamp, do_csum, do_vlan;
2339         u32 bufaddr;
2340         unsigned int nr_frags, nr_txbds, bytes_sent, fcb_len = 0;
2341
2342         rq = skb->queue_mapping;
2343         tx_queue = priv->tx_queue[rq];
2344         txq = netdev_get_tx_queue(dev, rq);
2345         base = tx_queue->tx_bd_base;
2346         regs = tx_queue->grp->regs;
2347
2348         do_csum = (CHECKSUM_PARTIAL == skb->ip_summed);
2349         do_vlan = skb_vlan_tag_present(skb);
2350         do_tstamp = (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2351                     priv->hwts_tx_en;
2352
2353         if (do_csum || do_vlan)
2354                 fcb_len = GMAC_FCB_LEN;
2355
2356         /* check if time stamp should be generated */
2357         if (unlikely(do_tstamp))
2358                 fcb_len = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2359
2360         /* make space for additional header when fcb is needed */
2361         if (fcb_len && unlikely(skb_headroom(skb) < fcb_len)) {
2362                 struct sk_buff *skb_new;
2363
2364                 skb_new = skb_realloc_headroom(skb, fcb_len);
2365                 if (!skb_new) {
2366                         dev->stats.tx_errors++;
2367                         dev_kfree_skb_any(skb);
2368                         return NETDEV_TX_OK;
2369                 }
2370
2371                 if (skb->sk)
2372                         skb_set_owner_w(skb_new, skb->sk);
2373                 dev_consume_skb_any(skb);
2374                 skb = skb_new;
2375         }
2376
2377         /* total number of fragments in the SKB */
2378         nr_frags = skb_shinfo(skb)->nr_frags;
2379
2380         /* calculate the required number of TxBDs for this skb */
2381         if (unlikely(do_tstamp))
2382                 nr_txbds = nr_frags + 2;
2383         else
2384                 nr_txbds = nr_frags + 1;
2385
2386         /* check if there is space to queue this packet */
2387         if (nr_txbds > tx_queue->num_txbdfree) {
2388                 /* no space, stop the queue */
2389                 netif_tx_stop_queue(txq);
2390                 dev->stats.tx_fifo_errors++;
2391                 return NETDEV_TX_BUSY;
2392         }
2393
2394         /* Update transmit stats */
2395         bytes_sent = skb->len;
2396         tx_queue->stats.tx_bytes += bytes_sent;
2397         /* keep Tx bytes on wire for BQL accounting */
2398         GFAR_CB(skb)->bytes_sent = bytes_sent;
2399         tx_queue->stats.tx_packets++;
2400
2401         txbdp = txbdp_start = tx_queue->cur_tx;
2402         lstatus = be32_to_cpu(txbdp->lstatus);
2403
2404         /* Add TxPAL between FCB and frame if required */
2405         if (unlikely(do_tstamp)) {
2406                 skb_push(skb, GMAC_TXPAL_LEN);
2407                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2408         }
2409
2410         /* Add TxFCB if required */
2411         if (fcb_len) {
2412                 fcb = gfar_add_fcb(skb);
2413                 lstatus |= BD_LFLAG(TXBD_TOE);
2414         }
2415
2416         /* Set up checksumming */
2417         if (do_csum) {
2418                 gfar_tx_checksum(skb, fcb, fcb_len);
2419
2420                 if (unlikely(gfar_csum_errata_12(priv, (unsigned long)fcb)) ||
2421                     unlikely(gfar_csum_errata_76(priv, skb->len))) {
2422                         __skb_pull(skb, GMAC_FCB_LEN);
2423                         skb_checksum_help(skb);
2424                         if (do_vlan || do_tstamp) {
2425                                 /* put back a new fcb for vlan/tstamp TOE */
2426                                 fcb = gfar_add_fcb(skb);
2427                         } else {
2428                                 /* Tx TOE not used */
2429                                 lstatus &= ~(BD_LFLAG(TXBD_TOE));
2430                                 fcb = NULL;
2431                         }
2432                 }
2433         }
2434
2435         if (do_vlan)
2436                 gfar_tx_vlan(skb, fcb);
2437
2438         bufaddr = dma_map_single(priv->dev, skb->data, skb_headlen(skb),
2439                                  DMA_TO_DEVICE);
2440         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2441                 goto dma_map_err;
2442
2443         txbdp_start->bufPtr = cpu_to_be32(bufaddr);
2444
2445         /* Time stamp insertion requires one additional TxBD */
2446         if (unlikely(do_tstamp))
2447                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2448                                                  tx_queue->tx_ring_size);
2449
2450         if (likely(!nr_frags)) {
2451                 if (likely(!do_tstamp))
2452                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2453         } else {
2454                 u32 lstatus_start = lstatus;
2455
2456                 /* Place the fragment addresses and lengths into the TxBDs */
2457                 frag = &skb_shinfo(skb)->frags[0];
2458                 for (i = 0; i < nr_frags; i++, frag++) {
2459                         unsigned int size;
2460
2461                         /* Point at the next BD, wrapping as needed */
2462                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2463
2464                         size = skb_frag_size(frag);
2465
2466                         lstatus = be32_to_cpu(txbdp->lstatus) | size |
2467                                   BD_LFLAG(TXBD_READY);
2468
2469                         /* Handle the last BD specially */
2470                         if (i == nr_frags - 1)
2471                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2472
2473                         bufaddr = skb_frag_dma_map(priv->dev, frag, 0,
2474                                                    size, DMA_TO_DEVICE);
2475                         if (unlikely(dma_mapping_error(priv->dev, bufaddr)))
2476                                 goto dma_map_err;
2477
2478                         /* set the TxBD length and buffer pointer */
2479                         txbdp->bufPtr = cpu_to_be32(bufaddr);
2480                         txbdp->lstatus = cpu_to_be32(lstatus);
2481                 }
2482
2483                 lstatus = lstatus_start;
2484         }
2485
2486         /* If time stamping is requested one additional TxBD must be set up. The
2487          * first TxBD points to the FCB and must have a data length of
2488          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2489          * the full frame length.
2490          */
2491         if (unlikely(do_tstamp)) {
2492                 u32 lstatus_ts = be32_to_cpu(txbdp_tstamp->lstatus);
2493
2494                 bufaddr = be32_to_cpu(txbdp_start->bufPtr);
2495                 bufaddr += fcb_len;
2496
2497                 lstatus_ts |= BD_LFLAG(TXBD_READY) |
2498                               (skb_headlen(skb) - fcb_len);
2499                 if (!nr_frags)
2500                         lstatus_ts |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2501
2502                 txbdp_tstamp->bufPtr = cpu_to_be32(bufaddr);
2503                 txbdp_tstamp->lstatus = cpu_to_be32(lstatus_ts);
2504                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2505
2506                 /* Setup tx hardware time stamping */
2507                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2508                 fcb->ptp = 1;
2509         } else {
2510                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2511         }
2512
2513         netdev_tx_sent_queue(txq, bytes_sent);
2514
2515         gfar_wmb();
2516
2517         txbdp_start->lstatus = cpu_to_be32(lstatus);
2518
2519         gfar_wmb(); /* force lstatus write before tx_skbuff */
2520
2521         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2522
2523         /* Update the current skb pointer to the next entry we will use
2524          * (wrapping if necessary)
2525          */
2526         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2527                               TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2528
2529         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2530
2531         /* We can work in parallel with gfar_clean_tx_ring(), except
2532          * when modifying num_txbdfree. Note that we didn't grab the lock
2533          * when we were reading the num_txbdfree and checking for available
2534          * space, that's because outside of this function it can only grow.
2535          */
2536         spin_lock_bh(&tx_queue->txlock);
2537         /* reduce TxBD free count */
2538         tx_queue->num_txbdfree -= (nr_txbds);
2539         spin_unlock_bh(&tx_queue->txlock);
2540
2541         /* If the next BD still needs to be cleaned up, then the bds
2542          * are full.  We need to tell the kernel to stop sending us stuff.
2543          */
2544         if (!tx_queue->num_txbdfree) {
2545                 netif_tx_stop_queue(txq);
2546
2547                 dev->stats.tx_fifo_errors++;
2548         }
2549
2550         /* Tell the DMA to go go go */
2551         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2552
2553         return NETDEV_TX_OK;
2554
2555 dma_map_err:
2556         txbdp = next_txbd(txbdp_start, base, tx_queue->tx_ring_size);
2557         if (do_tstamp)
2558                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2559         for (i = 0; i < nr_frags; i++) {
2560                 lstatus = be32_to_cpu(txbdp->lstatus);
2561                 if (!(lstatus & BD_LFLAG(TXBD_READY)))
2562                         break;
2563
2564                 lstatus &= ~BD_LFLAG(TXBD_READY);
2565                 txbdp->lstatus = cpu_to_be32(lstatus);
2566                 bufaddr = be32_to_cpu(txbdp->bufPtr);
2567                 dma_unmap_page(priv->dev, bufaddr, be16_to_cpu(txbdp->length),
2568                                DMA_TO_DEVICE);
2569                 txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2570         }
2571         gfar_wmb();
2572         dev_kfree_skb_any(skb);
2573         return NETDEV_TX_OK;
2574 }
2575
2576 /* Stops the kernel queue, and halts the controller */
2577 static int gfar_close(struct net_device *dev)
2578 {
2579         struct gfar_private *priv = netdev_priv(dev);
2580
2581         cancel_work_sync(&priv->reset_task);
2582         stop_gfar(dev);
2583
2584         /* Disconnect from the PHY */
2585         phy_disconnect(dev->phydev);
2586
2587         gfar_free_irq(priv);
2588
2589         return 0;
2590 }
2591
2592 /* Changes the mac address if the controller is not running. */
2593 static int gfar_set_mac_address(struct net_device *dev)
2594 {
2595         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2596
2597         return 0;
2598 }
2599
2600 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2601 {
2602         struct gfar_private *priv = netdev_priv(dev);
2603         int frame_size = new_mtu + ETH_HLEN;
2604
2605         if ((frame_size < 64) || (frame_size > GFAR_JUMBO_FRAME_SIZE)) {
2606                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2607                 return -EINVAL;
2608         }
2609
2610         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2611                 cpu_relax();
2612
2613         if (dev->flags & IFF_UP)
2614                 stop_gfar(dev);
2615
2616         dev->mtu = new_mtu;
2617
2618         if (dev->flags & IFF_UP)
2619                 startup_gfar(dev);
2620
2621         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2622
2623         return 0;
2624 }
2625
2626 void reset_gfar(struct net_device *ndev)
2627 {
2628         struct gfar_private *priv = netdev_priv(ndev);
2629
2630         while (test_and_set_bit_lock(GFAR_RESETTING, &priv->state))
2631                 cpu_relax();
2632
2633         stop_gfar(ndev);
2634         startup_gfar(ndev);
2635
2636         clear_bit_unlock(GFAR_RESETTING, &priv->state);
2637 }
2638
2639 /* gfar_reset_task gets scheduled when a packet has not been
2640  * transmitted after a set amount of time.
2641  * For now, assume that clearing out all the structures, and
2642  * starting over will fix the problem.
2643  */
2644 static void gfar_reset_task(struct work_struct *work)
2645 {
2646         struct gfar_private *priv = container_of(work, struct gfar_private,
2647                                                  reset_task);
2648         reset_gfar(priv->ndev);
2649 }
2650
2651 static void gfar_timeout(struct net_device *dev)
2652 {
2653         struct gfar_private *priv = netdev_priv(dev);
2654
2655         dev->stats.tx_errors++;
2656         schedule_work(&priv->reset_task);
2657 }
2658
2659 /* Interrupt Handler for Transmit complete */
2660 static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2661 {
2662         struct net_device *dev = tx_queue->dev;
2663         struct netdev_queue *txq;
2664         struct gfar_private *priv = netdev_priv(dev);
2665         struct txbd8 *bdp, *next = NULL;
2666         struct txbd8 *lbdp = NULL;
2667         struct txbd8 *base = tx_queue->tx_bd_base;
2668         struct sk_buff *skb;
2669         int skb_dirtytx;
2670         int tx_ring_size = tx_queue->tx_ring_size;
2671         int frags = 0, nr_txbds = 0;
2672         int i;
2673         int howmany = 0;
2674         int tqi = tx_queue->qindex;
2675         unsigned int bytes_sent = 0;
2676         u32 lstatus;
2677         size_t buflen;
2678
2679         txq = netdev_get_tx_queue(dev, tqi);
2680         bdp = tx_queue->dirty_tx;
2681         skb_dirtytx = tx_queue->skb_dirtytx;
2682
2683         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2684
2685                 frags = skb_shinfo(skb)->nr_frags;
2686
2687                 /* When time stamping, one additional TxBD must be freed.
2688                  * Also, we need to dma_unmap_single() the TxPAL.
2689                  */
2690                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2691                         nr_txbds = frags + 2;
2692                 else
2693                         nr_txbds = frags + 1;
2694
2695                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2696
2697                 lstatus = be32_to_cpu(lbdp->lstatus);
2698
2699                 /* Only clean completed frames */
2700                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2701                     (lstatus & BD_LENGTH_MASK))
2702                         break;
2703
2704                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2705                         next = next_txbd(bdp, base, tx_ring_size);
2706                         buflen = be16_to_cpu(next->length) +
2707                                  GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2708                 } else
2709                         buflen = be16_to_cpu(bdp->length);
2710
2711                 dma_unmap_single(priv->dev, be32_to_cpu(bdp->bufPtr),
2712                                  buflen, DMA_TO_DEVICE);
2713
2714                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2715                         struct skb_shared_hwtstamps shhwtstamps;
2716                         u64 *ns = (u64 *)(((uintptr_t)skb->data + 0x10) &
2717                                           ~0x7UL);
2718
2719                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2720                         shhwtstamps.hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
2721                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2722                         skb_tstamp_tx(skb, &shhwtstamps);
2723                         gfar_clear_txbd_status(bdp);
2724                         bdp = next;
2725                 }
2726
2727                 gfar_clear_txbd_status(bdp);
2728                 bdp = next_txbd(bdp, base, tx_ring_size);
2729
2730                 for (i = 0; i < frags; i++) {
2731                         dma_unmap_page(priv->dev, be32_to_cpu(bdp->bufPtr),
2732                                        be16_to_cpu(bdp->length),
2733                                        DMA_TO_DEVICE);
2734                         gfar_clear_txbd_status(bdp);
2735                         bdp = next_txbd(bdp, base, tx_ring_size);
2736                 }
2737
2738                 bytes_sent += GFAR_CB(skb)->bytes_sent;
2739
2740                 dev_kfree_skb_any(skb);
2741
2742                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2743
2744                 skb_dirtytx = (skb_dirtytx + 1) &
2745                               TX_RING_MOD_MASK(tx_ring_size);
2746
2747                 howmany++;
2748                 spin_lock(&tx_queue->txlock);
2749                 tx_queue->num_txbdfree += nr_txbds;
2750                 spin_unlock(&tx_queue->txlock);
2751         }
2752
2753         /* If we freed a buffer, we can restart transmission, if necessary */
2754         if (tx_queue->num_txbdfree &&
2755             netif_tx_queue_stopped(txq) &&
2756             !(test_bit(GFAR_DOWN, &priv->state)))
2757                 netif_wake_subqueue(priv->ndev, tqi);
2758
2759         /* Update dirty indicators */
2760         tx_queue->skb_dirtytx = skb_dirtytx;
2761         tx_queue->dirty_tx = bdp;
2762
2763         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2764 }
2765
2766 static bool gfar_new_page(struct gfar_priv_rx_q *rxq, struct gfar_rx_buff *rxb)
2767 {
2768         struct page *page;
2769         dma_addr_t addr;
2770
2771         page = dev_alloc_page();
2772         if (unlikely(!page))
2773                 return false;
2774
2775         addr = dma_map_page(rxq->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
2776         if (unlikely(dma_mapping_error(rxq->dev, addr))) {
2777                 __free_page(page);
2778
2779                 return false;
2780         }
2781
2782         rxb->dma = addr;
2783         rxb->page = page;
2784         rxb->page_offset = 0;
2785
2786         return true;
2787 }
2788
2789 static void gfar_rx_alloc_err(struct gfar_priv_rx_q *rx_queue)
2790 {
2791         struct gfar_private *priv = netdev_priv(rx_queue->ndev);
2792         struct gfar_extra_stats *estats = &priv->extra_stats;
2793
2794         netdev_err(rx_queue->ndev, "Can't alloc RX buffers\n");
2795         atomic64_inc(&estats->rx_alloc_err);
2796 }
2797
2798 static void gfar_alloc_rx_buffs(struct gfar_priv_rx_q *rx_queue,
2799                                 int alloc_cnt)
2800 {
2801         struct rxbd8 *bdp;
2802         struct gfar_rx_buff *rxb;
2803         int i;
2804
2805         i = rx_queue->next_to_use;
2806         bdp = &rx_queue->rx_bd_base[i];
2807         rxb = &rx_queue->rx_buff[i];
2808
2809         while (alloc_cnt--) {
2810                 /* try reuse page */
2811                 if (unlikely(!rxb->page)) {
2812                         if (unlikely(!gfar_new_page(rx_queue, rxb))) {
2813                                 gfar_rx_alloc_err(rx_queue);
2814                                 break;
2815                         }
2816                 }
2817
2818                 /* Setup the new RxBD */
2819                 gfar_init_rxbdp(rx_queue, bdp,
2820                                 rxb->dma + rxb->page_offset + RXBUF_ALIGNMENT);
2821
2822                 /* Update to the next pointer */
2823                 bdp++;
2824                 rxb++;
2825
2826                 if (unlikely(++i == rx_queue->rx_ring_size)) {
2827                         i = 0;
2828                         bdp = rx_queue->rx_bd_base;
2829                         rxb = rx_queue->rx_buff;
2830                 }
2831         }
2832
2833         rx_queue->next_to_use = i;
2834         rx_queue->next_to_alloc = i;
2835 }
2836
2837 static void count_errors(u32 lstatus, struct net_device *ndev)
2838 {
2839         struct gfar_private *priv = netdev_priv(ndev);
2840         struct net_device_stats *stats = &ndev->stats;
2841         struct gfar_extra_stats *estats = &priv->extra_stats;
2842
2843         /* If the packet was truncated, none of the other errors matter */
2844         if (lstatus & BD_LFLAG(RXBD_TRUNCATED)) {
2845                 stats->rx_length_errors++;
2846
2847                 atomic64_inc(&estats->rx_trunc);
2848
2849                 return;
2850         }
2851         /* Count the errors, if there were any */
2852         if (lstatus & BD_LFLAG(RXBD_LARGE | RXBD_SHORT)) {
2853                 stats->rx_length_errors++;
2854
2855                 if (lstatus & BD_LFLAG(RXBD_LARGE))
2856                         atomic64_inc(&estats->rx_large);
2857                 else
2858                         atomic64_inc(&estats->rx_short);
2859         }
2860         if (lstatus & BD_LFLAG(RXBD_NONOCTET)) {
2861                 stats->rx_frame_errors++;
2862                 atomic64_inc(&estats->rx_nonoctet);
2863         }
2864         if (lstatus & BD_LFLAG(RXBD_CRCERR)) {
2865                 atomic64_inc(&estats->rx_crcerr);
2866                 stats->rx_crc_errors++;
2867         }
2868         if (lstatus & BD_LFLAG(RXBD_OVERRUN)) {
2869                 atomic64_inc(&estats->rx_overrun);
2870                 stats->rx_over_errors++;
2871         }
2872 }
2873
2874 irqreturn_t gfar_receive(int irq, void *grp_id)
2875 {
2876         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2877         unsigned long flags;
2878         u32 imask, ievent;
2879
2880         ievent = gfar_read(&grp->regs->ievent);
2881
2882         if (unlikely(ievent & IEVENT_FGPI)) {
2883                 gfar_write(&grp->regs->ievent, IEVENT_FGPI);
2884                 return IRQ_HANDLED;
2885         }
2886
2887         if (likely(napi_schedule_prep(&grp->napi_rx))) {
2888                 spin_lock_irqsave(&grp->grplock, flags);
2889                 imask = gfar_read(&grp->regs->imask);
2890                 imask &= IMASK_RX_DISABLED;
2891                 gfar_write(&grp->regs->imask, imask);
2892                 spin_unlock_irqrestore(&grp->grplock, flags);
2893                 __napi_schedule(&grp->napi_rx);
2894         } else {
2895                 /* Clear IEVENT, so interrupts aren't called again
2896                  * because of the packets that have already arrived.
2897                  */
2898                 gfar_write(&grp->regs->ievent, IEVENT_RX_MASK);
2899         }
2900
2901         return IRQ_HANDLED;
2902 }
2903
2904 /* Interrupt Handler for Transmit complete */
2905 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2906 {
2907         struct gfar_priv_grp *grp = (struct gfar_priv_grp *)grp_id;
2908         unsigned long flags;
2909         u32 imask;
2910
2911         if (likely(napi_schedule_prep(&grp->napi_tx))) {
2912                 spin_lock_irqsave(&grp->grplock, flags);
2913                 imask = gfar_read(&grp->regs->imask);
2914                 imask &= IMASK_TX_DISABLED;
2915                 gfar_write(&grp->regs->imask, imask);
2916                 spin_unlock_irqrestore(&grp->grplock, flags);
2917                 __napi_schedule(&grp->napi_tx);
2918         } else {
2919                 /* Clear IEVENT, so interrupts aren't called again
2920                  * because of the packets that have already arrived.
2921                  */
2922                 gfar_write(&grp->regs->ievent, IEVENT_TX_MASK);
2923         }
2924
2925         return IRQ_HANDLED;
2926 }
2927
2928 static bool gfar_add_rx_frag(struct gfar_rx_buff *rxb, u32 lstatus,
2929                              struct sk_buff *skb, bool first)
2930 {
2931         unsigned int size = lstatus & BD_LENGTH_MASK;
2932         struct page *page = rxb->page;
2933         bool last = !!(lstatus & BD_LFLAG(RXBD_LAST));
2934
2935         /* Remove the FCS from the packet length */
2936         if (last)
2937                 size -= ETH_FCS_LEN;
2938
2939         if (likely(first)) {
2940                 skb_put(skb, size);
2941         } else {
2942                 /* the last fragments' length contains the full frame length */
2943                 if (last)
2944                         size -= skb->len;
2945
2946                 /* in case the last fragment consisted only of the FCS */
2947                 if (size > 0)
2948                         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
2949                                         rxb->page_offset + RXBUF_ALIGNMENT,
2950                                         size, GFAR_RXB_TRUESIZE);
2951         }
2952
2953         /* try reuse page */
2954         if (unlikely(page_count(page) != 1))
2955                 return false;
2956
2957         /* change offset to the other half */
2958         rxb->page_offset ^= GFAR_RXB_TRUESIZE;
2959
2960         page_ref_inc(page);
2961
2962         return true;
2963 }
2964
2965 static void gfar_reuse_rx_page(struct gfar_priv_rx_q *rxq,
2966                                struct gfar_rx_buff *old_rxb)
2967 {
2968         struct gfar_rx_buff *new_rxb;
2969         u16 nta = rxq->next_to_alloc;
2970
2971         new_rxb = &rxq->rx_buff[nta];
2972
2973         /* find next buf that can reuse a page */
2974         nta++;
2975         rxq->next_to_alloc = (nta < rxq->rx_ring_size) ? nta : 0;
2976
2977         /* copy page reference */
2978         *new_rxb = *old_rxb;
2979
2980         /* sync for use by the device */
2981         dma_sync_single_range_for_device(rxq->dev, old_rxb->dma,
2982                                          old_rxb->page_offset,
2983                                          GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
2984 }
2985
2986 static struct sk_buff *gfar_get_next_rxbuff(struct gfar_priv_rx_q *rx_queue,
2987                                             u32 lstatus, struct sk_buff *skb)
2988 {
2989         struct gfar_rx_buff *rxb = &rx_queue->rx_buff[rx_queue->next_to_clean];
2990         struct page *page = rxb->page;
2991         bool first = false;
2992
2993         if (likely(!skb)) {
2994                 void *buff_addr = page_address(page) + rxb->page_offset;
2995
2996                 skb = build_skb(buff_addr, GFAR_SKBFRAG_SIZE);
2997                 if (unlikely(!skb)) {
2998                         gfar_rx_alloc_err(rx_queue);
2999                         return NULL;
3000                 }
3001                 skb_reserve(skb, RXBUF_ALIGNMENT);
3002                 first = true;
3003         }
3004
3005         dma_sync_single_range_for_cpu(rx_queue->dev, rxb->dma, rxb->page_offset,
3006                                       GFAR_RXB_TRUESIZE, DMA_FROM_DEVICE);
3007
3008         if (gfar_add_rx_frag(rxb, lstatus, skb, first)) {
3009                 /* reuse the free half of the page */
3010                 gfar_reuse_rx_page(rx_queue, rxb);
3011         } else {
3012                 /* page cannot be reused, unmap it */
3013                 dma_unmap_page(rx_queue->dev, rxb->dma,
3014                                PAGE_SIZE, DMA_FROM_DEVICE);
3015         }
3016
3017         /* clear rxb content */
3018         rxb->page = NULL;
3019
3020         return skb;
3021 }
3022
3023 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
3024 {
3025         /* If valid headers were found, and valid sums
3026          * were verified, then we tell the kernel that no
3027          * checksumming is necessary.  Otherwise, it is [FIXME]
3028          */
3029         if ((be16_to_cpu(fcb->flags) & RXFCB_CSUM_MASK) ==
3030             (RXFCB_CIP | RXFCB_CTU))
3031                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3032         else
3033                 skb_checksum_none_assert(skb);
3034 }
3035
3036 /* gfar_process_frame() -- handle one incoming packet if skb isn't NULL. */
3037 static void gfar_process_frame(struct net_device *ndev, struct sk_buff *skb)
3038 {
3039         struct gfar_private *priv = netdev_priv(ndev);
3040         struct rxfcb *fcb = NULL;
3041
3042         /* fcb is at the beginning if exists */
3043         fcb = (struct rxfcb *)skb->data;
3044
3045         /* Remove the FCB from the skb
3046          * Remove the padded bytes, if there are any
3047          */
3048         if (priv->uses_rxfcb)
3049                 skb_pull(skb, GMAC_FCB_LEN);
3050
3051         /* Get receive timestamp from the skb */
3052         if (priv->hwts_rx_en) {
3053                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
3054                 u64 *ns = (u64 *) skb->data;
3055
3056                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3057                 shhwtstamps->hwtstamp = ns_to_ktime(be64_to_cpu(*ns));
3058         }
3059
3060         if (priv->padding)
3061                 skb_pull(skb, priv->padding);
3062
3063         if (ndev->features & NETIF_F_RXCSUM)
3064                 gfar_rx_checksum(skb, fcb);
3065
3066         /* Tell the skb what kind of packet this is */
3067         skb->protocol = eth_type_trans(skb, ndev);
3068
3069         /* There's need to check for NETIF_F_HW_VLAN_CTAG_RX here.
3070          * Even if vlan rx accel is disabled, on some chips
3071          * RXFCB_VLN is pseudo randomly set.
3072          */
3073         if (ndev->features & NETIF_F_HW_VLAN_CTAG_RX &&
3074             be16_to_cpu(fcb->flags) & RXFCB_VLN)
3075                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
3076                                        be16_to_cpu(fcb->vlctl));
3077 }
3078
3079 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
3080  * until the budget/quota has been reached. Returns the number
3081  * of frames handled
3082  */
3083 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
3084 {
3085         struct net_device *ndev = rx_queue->ndev;
3086         struct gfar_private *priv = netdev_priv(ndev);
3087         struct rxbd8 *bdp;
3088         int i, howmany = 0;
3089         struct sk_buff *skb = rx_queue->skb;
3090         int cleaned_cnt = gfar_rxbd_unused(rx_queue);
3091         unsigned int total_bytes = 0, total_pkts = 0;
3092
3093         /* Get the first full descriptor */
3094         i = rx_queue->next_to_clean;
3095
3096         while (rx_work_limit--) {
3097                 u32 lstatus;
3098
3099                 if (cleaned_cnt >= GFAR_RX_BUFF_ALLOC) {
3100                         gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3101                         cleaned_cnt = 0;
3102                 }
3103
3104                 bdp = &rx_queue->rx_bd_base[i];
3105                 lstatus = be32_to_cpu(bdp->lstatus);
3106                 if (lstatus & BD_LFLAG(RXBD_EMPTY))
3107                         break;
3108
3109                 /* order rx buffer descriptor reads */
3110                 rmb();
3111
3112                 /* fetch next to clean buffer from the ring */
3113                 skb = gfar_get_next_rxbuff(rx_queue, lstatus, skb);
3114                 if (unlikely(!skb))
3115                         break;
3116
3117                 cleaned_cnt++;
3118                 howmany++;
3119
3120                 if (unlikely(++i == rx_queue->rx_ring_size))
3121                         i = 0;
3122
3123                 rx_queue->next_to_clean = i;
3124
3125                 /* fetch next buffer if not the last in frame */
3126                 if (!(lstatus & BD_LFLAG(RXBD_LAST)))
3127                         continue;
3128
3129                 if (unlikely(lstatus & BD_LFLAG(RXBD_ERR))) {
3130                         count_errors(lstatus, ndev);
3131
3132                         /* discard faulty buffer */
3133                         dev_kfree_skb(skb);
3134                         skb = NULL;
3135                         rx_queue->stats.rx_dropped++;
3136                         continue;
3137                 }
3138
3139                 /* Increment the number of packets */
3140                 total_pkts++;
3141                 total_bytes += skb->len;
3142
3143                 skb_record_rx_queue(skb, rx_queue->qindex);
3144
3145                 gfar_process_frame(ndev, skb);
3146
3147                 /* Send the packet up the stack */
3148                 napi_gro_receive(&rx_queue->grp->napi_rx, skb);
3149
3150                 skb = NULL;
3151         }
3152
3153         /* Store incomplete frames for completion */
3154         rx_queue->skb = skb;
3155
3156         rx_queue->stats.rx_packets += total_pkts;
3157         rx_queue->stats.rx_bytes += total_bytes;
3158
3159         if (cleaned_cnt)
3160                 gfar_alloc_rx_buffs(rx_queue, cleaned_cnt);
3161
3162         /* Update Last Free RxBD pointer for LFC */
3163         if (unlikely(priv->tx_actual_en)) {
3164                 u32 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3165
3166                 gfar_write(rx_queue->rfbptr, bdp_dma);
3167         }
3168
3169         return howmany;
3170 }
3171
3172 static int gfar_poll_rx_sq(struct napi_struct *napi, int budget)
3173 {
3174         struct gfar_priv_grp *gfargrp =
3175                 container_of(napi, struct gfar_priv_grp, napi_rx);
3176         struct gfar __iomem *regs = gfargrp->regs;
3177         struct gfar_priv_rx_q *rx_queue = gfargrp->rx_queue;
3178         int work_done = 0;
3179
3180         /* Clear IEVENT, so interrupts aren't called again
3181          * because of the packets that have already arrived
3182          */
3183         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3184
3185         work_done = gfar_clean_rx_ring(rx_queue, budget);
3186
3187         if (work_done < budget) {
3188                 u32 imask;
3189                 napi_complete(napi);
3190                 /* Clear the halt bit in RSTAT */
3191                 gfar_write(&regs->rstat, gfargrp->rstat);
3192
3193                 spin_lock_irq(&gfargrp->grplock);
3194                 imask = gfar_read(&regs->imask);
3195                 imask |= IMASK_RX_DEFAULT;
3196                 gfar_write(&regs->imask, imask);
3197                 spin_unlock_irq(&gfargrp->grplock);
3198         }
3199
3200         return work_done;
3201 }
3202
3203 static int gfar_poll_tx_sq(struct napi_struct *napi, int budget)
3204 {
3205         struct gfar_priv_grp *gfargrp =
3206                 container_of(napi, struct gfar_priv_grp, napi_tx);
3207         struct gfar __iomem *regs = gfargrp->regs;
3208         struct gfar_priv_tx_q *tx_queue = gfargrp->tx_queue;
3209         u32 imask;
3210
3211         /* Clear IEVENT, so interrupts aren't called again
3212          * because of the packets that have already arrived
3213          */
3214         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3215
3216         /* run Tx cleanup to completion */
3217         if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx])
3218                 gfar_clean_tx_ring(tx_queue);
3219
3220         napi_complete(napi);
3221
3222         spin_lock_irq(&gfargrp->grplock);
3223         imask = gfar_read(&regs->imask);
3224         imask |= IMASK_TX_DEFAULT;
3225         gfar_write(&regs->imask, imask);
3226         spin_unlock_irq(&gfargrp->grplock);
3227
3228         return 0;
3229 }
3230
3231 static int gfar_poll_rx(struct napi_struct *napi, int budget)
3232 {
3233         struct gfar_priv_grp *gfargrp =
3234                 container_of(napi, struct gfar_priv_grp, napi_rx);
3235         struct gfar_private *priv = gfargrp->priv;
3236         struct gfar __iomem *regs = gfargrp->regs;
3237         struct gfar_priv_rx_q *rx_queue = NULL;
3238         int work_done = 0, work_done_per_q = 0;
3239         int i, budget_per_q = 0;
3240         unsigned long rstat_rxf;
3241         int num_act_queues;
3242
3243         /* Clear IEVENT, so interrupts aren't called again
3244          * because of the packets that have already arrived
3245          */
3246         gfar_write(&regs->ievent, IEVENT_RX_MASK);
3247
3248         rstat_rxf = gfar_read(&regs->rstat) & RSTAT_RXF_MASK;
3249
3250         num_act_queues = bitmap_weight(&rstat_rxf, MAX_RX_QS);
3251         if (num_act_queues)
3252                 budget_per_q = budget/num_act_queues;
3253
3254         for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
3255                 /* skip queue if not active */
3256                 if (!(rstat_rxf & (RSTAT_CLEAR_RXF0 >> i)))
3257                         continue;
3258
3259                 rx_queue = priv->rx_queue[i];
3260                 work_done_per_q =
3261                         gfar_clean_rx_ring(rx_queue, budget_per_q);
3262                 work_done += work_done_per_q;
3263
3264                 /* finished processing this queue */
3265                 if (work_done_per_q < budget_per_q) {
3266                         /* clear active queue hw indication */
3267                         gfar_write(&regs->rstat,
3268                                    RSTAT_CLEAR_RXF0 >> i);
3269                         num_act_queues--;
3270
3271                         if (!num_act_queues)
3272                                 break;
3273                 }
3274         }
3275
3276         if (!num_act_queues) {
3277                 u32 imask;
3278                 napi_complete(napi);
3279
3280                 /* Clear the halt bit in RSTAT */
3281                 gfar_write(&regs->rstat, gfargrp->rstat);
3282
3283                 spin_lock_irq(&gfargrp->grplock);
3284                 imask = gfar_read(&regs->imask);
3285                 imask |= IMASK_RX_DEFAULT;
3286                 gfar_write(&regs->imask, imask);
3287                 spin_unlock_irq(&gfargrp->grplock);
3288         }
3289
3290         return work_done;
3291 }
3292
3293 static int gfar_poll_tx(struct napi_struct *napi, int budget)
3294 {
3295         struct gfar_priv_grp *gfargrp =
3296                 container_of(napi, struct gfar_priv_grp, napi_tx);
3297         struct gfar_private *priv = gfargrp->priv;
3298         struct gfar __iomem *regs = gfargrp->regs;
3299         struct gfar_priv_tx_q *tx_queue = NULL;
3300         int has_tx_work = 0;
3301         int i;
3302
3303         /* Clear IEVENT, so interrupts aren't called again
3304          * because of the packets that have already arrived
3305          */
3306         gfar_write(&regs->ievent, IEVENT_TX_MASK);
3307
3308         for_each_set_bit(i, &gfargrp->tx_bit_map, priv->num_tx_queues) {
3309                 tx_queue = priv->tx_queue[i];
3310                 /* run Tx cleanup to completion */
3311                 if (tx_queue->tx_skbuff[tx_queue->skb_dirtytx]) {
3312                         gfar_clean_tx_ring(tx_queue);
3313                         has_tx_work = 1;
3314                 }
3315         }
3316
3317         if (!has_tx_work) {
3318                 u32 imask;
3319                 napi_complete(napi);
3320
3321                 spin_lock_irq(&gfargrp->grplock);
3322                 imask = gfar_read(&regs->imask);
3323                 imask |= IMASK_TX_DEFAULT;
3324                 gfar_write(&regs->imask, imask);
3325                 spin_unlock_irq(&gfargrp->grplock);
3326         }
3327
3328         return 0;
3329 }
3330
3331
3332 #ifdef CONFIG_NET_POLL_CONTROLLER
3333 /* Polling 'interrupt' - used by things like netconsole to send skbs
3334  * without having to re-enable interrupts. It's not called while
3335  * the interrupt routine is executing.
3336  */
3337 static void gfar_netpoll(struct net_device *dev)
3338 {
3339         struct gfar_private *priv = netdev_priv(dev);
3340         int i;
3341
3342         /* If the device has multiple interrupts, run tx/rx */
3343         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
3344                 for (i = 0; i < priv->num_grps; i++) {
3345                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3346
3347                         disable_irq(gfar_irq(grp, TX)->irq);
3348                         disable_irq(gfar_irq(grp, RX)->irq);
3349                         disable_irq(gfar_irq(grp, ER)->irq);
3350                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3351                         enable_irq(gfar_irq(grp, ER)->irq);
3352                         enable_irq(gfar_irq(grp, RX)->irq);
3353                         enable_irq(gfar_irq(grp, TX)->irq);
3354                 }
3355         } else {
3356                 for (i = 0; i < priv->num_grps; i++) {
3357                         struct gfar_priv_grp *grp = &priv->gfargrp[i];
3358
3359                         disable_irq(gfar_irq(grp, TX)->irq);
3360                         gfar_interrupt(gfar_irq(grp, TX)->irq, grp);
3361                         enable_irq(gfar_irq(grp, TX)->irq);
3362                 }
3363         }
3364 }
3365 #endif
3366
3367 /* The interrupt handler for devices with one interrupt */
3368 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
3369 {
3370         struct gfar_priv_grp *gfargrp = grp_id;
3371
3372         /* Save ievent for future reference */
3373         u32 events = gfar_read(&gfargrp->regs->ievent);
3374
3375         /* Check for reception */
3376         if (events & IEVENT_RX_MASK)
3377                 gfar_receive(irq, grp_id);
3378
3379         /* Check for transmit completion */
3380         if (events & IEVENT_TX_MASK)
3381                 gfar_transmit(irq, grp_id);
3382
3383         /* Check for errors */
3384         if (events & IEVENT_ERR_MASK)
3385                 gfar_error(irq, grp_id);
3386
3387         return IRQ_HANDLED;
3388 }
3389
3390 /* Called every time the controller might need to be made
3391  * aware of new link state.  The PHY code conveys this
3392  * information through variables in the phydev structure, and this
3393  * function converts those variables into the appropriate
3394  * register values, and can bring down the device if needed.
3395  */
3396 static void adjust_link(struct net_device *dev)
3397 {
3398         struct gfar_private *priv = netdev_priv(dev);
3399         struct phy_device *phydev = dev->phydev;
3400
3401         if (unlikely(phydev->link != priv->oldlink ||
3402                      (phydev->link && (phydev->duplex != priv->oldduplex ||
3403                                        phydev->speed != priv->oldspeed))))
3404                 gfar_update_link_state(priv);
3405 }
3406
3407 /* Update the hash table based on the current list of multicast
3408  * addresses we subscribe to.  Also, change the promiscuity of
3409  * the device based on the flags (this function is called
3410  * whenever dev->flags is changed
3411  */
3412 static void gfar_set_multi(struct net_device *dev)
3413 {
3414         struct netdev_hw_addr *ha;
3415         struct gfar_private *priv = netdev_priv(dev);
3416         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3417         u32 tempval;
3418
3419         if (dev->flags & IFF_PROMISC) {
3420                 /* Set RCTRL to PROM */
3421                 tempval = gfar_read(&regs->rctrl);
3422                 tempval |= RCTRL_PROM;
3423                 gfar_write(&regs->rctrl, tempval);
3424         } else {
3425                 /* Set RCTRL to not PROM */
3426                 tempval = gfar_read(&regs->rctrl);
3427                 tempval &= ~(RCTRL_PROM);
3428                 gfar_write(&regs->rctrl, tempval);
3429         }
3430
3431         if (dev->flags & IFF_ALLMULTI) {
3432                 /* Set the hash to rx all multicast frames */
3433                 gfar_write(&regs->igaddr0, 0xffffffff);
3434                 gfar_write(&regs->igaddr1, 0xffffffff);
3435                 gfar_write(&regs->igaddr2, 0xffffffff);
3436                 gfar_write(&regs->igaddr3, 0xffffffff);
3437                 gfar_write(&regs->igaddr4, 0xffffffff);
3438                 gfar_write(&regs->igaddr5, 0xffffffff);
3439                 gfar_write(&regs->igaddr6, 0xffffffff);
3440                 gfar_write(&regs->igaddr7, 0xffffffff);
3441                 gfar_write(&regs->gaddr0, 0xffffffff);
3442                 gfar_write(&regs->gaddr1, 0xffffffff);
3443                 gfar_write(&regs->gaddr2, 0xffffffff);
3444                 gfar_write(&regs->gaddr3, 0xffffffff);
3445                 gfar_write(&regs->gaddr4, 0xffffffff);
3446                 gfar_write(&regs->gaddr5, 0xffffffff);
3447                 gfar_write(&regs->gaddr6, 0xffffffff);
3448                 gfar_write(&regs->gaddr7, 0xffffffff);
3449         } else {
3450                 int em_num;
3451                 int idx;
3452
3453                 /* zero out the hash */
3454                 gfar_write(&regs->igaddr0, 0x0);
3455                 gfar_write(&regs->igaddr1, 0x0);
3456                 gfar_write(&regs->igaddr2, 0x0);
3457                 gfar_write(&regs->igaddr3, 0x0);
3458                 gfar_write(&regs->igaddr4, 0x0);
3459                 gfar_write(&regs->igaddr5, 0x0);
3460                 gfar_write(&regs->igaddr6, 0x0);
3461                 gfar_write(&regs->igaddr7, 0x0);
3462                 gfar_write(&regs->gaddr0, 0x0);
3463                 gfar_write(&regs->gaddr1, 0x0);
3464                 gfar_write(&regs->gaddr2, 0x0);
3465                 gfar_write(&regs->gaddr3, 0x0);
3466                 gfar_write(&regs->gaddr4, 0x0);
3467                 gfar_write(&regs->gaddr5, 0x0);
3468                 gfar_write(&regs->gaddr6, 0x0);
3469                 gfar_write(&regs->gaddr7, 0x0);
3470
3471                 /* If we have extended hash tables, we need to
3472                  * clear the exact match registers to prepare for
3473                  * setting them
3474                  */
3475                 if (priv->extended_hash) {
3476                         em_num = GFAR_EM_NUM + 1;
3477                         gfar_clear_exact_match(dev);
3478                         idx = 1;
3479                 } else {
3480                         idx = 0;
3481                         em_num = 0;
3482                 }
3483
3484                 if (netdev_mc_empty(dev))
3485                         return;
3486
3487                 /* Parse the list, and set the appropriate bits */
3488                 netdev_for_each_mc_addr(ha, dev) {
3489                         if (idx < em_num) {
3490                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3491                                 idx++;
3492                         } else
3493                                 gfar_set_hash_for_addr(dev, ha->addr);
3494                 }
3495         }
3496 }
3497
3498
3499 /* Clears each of the exact match registers to zero, so they
3500  * don't interfere with normal reception
3501  */
3502 static void gfar_clear_exact_match(struct net_device *dev)
3503 {
3504         int idx;
3505         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3506
3507         for (idx = 1; idx < GFAR_EM_NUM + 1; idx++)
3508                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3509 }
3510
3511 /* Set the appropriate hash bit for the given addr */
3512 /* The algorithm works like so:
3513  * 1) Take the Destination Address (ie the multicast address), and
3514  * do a CRC on it (little endian), and reverse the bits of the
3515  * result.
3516  * 2) Use the 8 most significant bits as a hash into a 256-entry
3517  * table.  The table is controlled through 8 32-bit registers:
3518  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3519  * gaddr7.  This means that the 3 most significant bits in the
3520  * hash index which gaddr register to use, and the 5 other bits
3521  * indicate which bit (assuming an IBM numbering scheme, which
3522  * for PowerPC (tm) is usually the case) in the register holds
3523  * the entry.
3524  */
3525 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3526 {
3527         u32 tempval;
3528         struct gfar_private *priv = netdev_priv(dev);
3529         u32 result = ether_crc(ETH_ALEN, addr);
3530         int width = priv->hash_width;
3531         u8 whichbit = (result >> (32 - width)) & 0x1f;
3532         u8 whichreg = result >> (32 - width + 5);
3533         u32 value = (1 << (31-whichbit));
3534
3535         tempval = gfar_read(priv->hash_regs[whichreg]);
3536         tempval |= value;
3537         gfar_write(priv->hash_regs[whichreg], tempval);
3538 }
3539
3540
3541 /* There are multiple MAC Address register pairs on some controllers
3542  * This function sets the numth pair to a given address
3543  */
3544 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3545                                   const u8 *addr)
3546 {
3547         struct gfar_private *priv = netdev_priv(dev);
3548         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3549         u32 tempval;
3550         u32 __iomem *macptr = &regs->macstnaddr1;
3551
3552         macptr += num*2;
3553
3554         /* For a station address of 0x12345678ABCD in transmission
3555          * order (BE), MACnADDR1 is set to 0xCDAB7856 and
3556          * MACnADDR2 is set to 0x34120000.
3557          */
3558         tempval = (addr[5] << 24) | (addr[4] << 16) |
3559                   (addr[3] << 8)  |  addr[2];
3560
3561         gfar_write(macptr, tempval);
3562
3563         tempval = (addr[1] << 24) | (addr[0] << 16);
3564
3565         gfar_write(macptr+1, tempval);
3566 }
3567
3568 /* GFAR error interrupt handler */
3569 static irqreturn_t gfar_error(int irq, void *grp_id)
3570 {
3571         struct gfar_priv_grp *gfargrp = grp_id;
3572         struct gfar __iomem *regs = gfargrp->regs;
3573         struct gfar_private *priv= gfargrp->priv;
3574         struct net_device *dev = priv->ndev;
3575
3576         /* Save ievent for future reference */
3577         u32 events = gfar_read(&regs->ievent);
3578
3579         /* Clear IEVENT */
3580         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3581
3582         /* Magic Packet is not an error. */
3583         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3584             (events & IEVENT_MAG))
3585                 events &= ~IEVENT_MAG;
3586
3587         /* Hmm... */
3588         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3589                 netdev_dbg(dev,
3590                            "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3591                            events, gfar_read(&regs->imask));
3592
3593         /* Update the error counters */
3594         if (events & IEVENT_TXE) {
3595                 dev->stats.tx_errors++;
3596
3597                 if (events & IEVENT_LC)
3598                         dev->stats.tx_window_errors++;
3599                 if (events & IEVENT_CRL)
3600                         dev->stats.tx_aborted_errors++;
3601                 if (events & IEVENT_XFUN) {
3602                         netif_dbg(priv, tx_err, dev,
3603                                   "TX FIFO underrun, packet dropped\n");
3604                         dev->stats.tx_dropped++;
3605                         atomic64_inc(&priv->extra_stats.tx_underrun);
3606
3607                         schedule_work(&priv->reset_task);
3608                 }
3609                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3610         }
3611         if (events & IEVENT_BSY) {
3612                 dev->stats.rx_over_errors++;
3613                 atomic64_inc(&priv->extra_stats.rx_bsy);
3614
3615                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3616                           gfar_read(&regs->rstat));
3617         }
3618         if (events & IEVENT_BABR) {
3619                 dev->stats.rx_errors++;
3620                 atomic64_inc(&priv->extra_stats.rx_babr);
3621
3622                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3623         }
3624         if (events & IEVENT_EBERR) {
3625                 atomic64_inc(&priv->extra_stats.eberr);
3626                 netif_dbg(priv, rx_err, dev, "bus error\n");
3627         }
3628         if (events & IEVENT_RXC)
3629                 netif_dbg(priv, rx_status, dev, "control frame\n");
3630
3631         if (events & IEVENT_BABT) {
3632                 atomic64_inc(&priv->extra_stats.tx_babt);
3633                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3634         }
3635         return IRQ_HANDLED;
3636 }
3637
3638 static u32 gfar_get_flowctrl_cfg(struct gfar_private *priv)
3639 {
3640         struct net_device *ndev = priv->ndev;
3641         struct phy_device *phydev = ndev->phydev;
3642         u32 val = 0;
3643
3644         if (!phydev->duplex)
3645                 return val;
3646
3647         if (!priv->pause_aneg_en) {
3648                 if (priv->tx_pause_en)
3649                         val |= MACCFG1_TX_FLOW;
3650                 if (priv->rx_pause_en)
3651                         val |= MACCFG1_RX_FLOW;
3652         } else {
3653                 u16 lcl_adv, rmt_adv;
3654                 u8 flowctrl;
3655                 /* get link partner capabilities */
3656                 rmt_adv = 0;
3657                 if (phydev->pause)
3658                         rmt_adv = LPA_PAUSE_CAP;
3659                 if (phydev->asym_pause)
3660                         rmt_adv |= LPA_PAUSE_ASYM;
3661
3662                 lcl_adv = 0;
3663                 if (phydev->advertising & ADVERTISED_Pause)
3664                         lcl_adv |= ADVERTISE_PAUSE_CAP;
3665                 if (phydev->advertising & ADVERTISED_Asym_Pause)
3666                         lcl_adv |= ADVERTISE_PAUSE_ASYM;
3667
3668                 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
3669                 if (flowctrl & FLOW_CTRL_TX)
3670                         val |= MACCFG1_TX_FLOW;
3671                 if (flowctrl & FLOW_CTRL_RX)
3672                         val |= MACCFG1_RX_FLOW;
3673         }
3674
3675         return val;
3676 }
3677
3678 static noinline void gfar_update_link_state(struct gfar_private *priv)
3679 {
3680         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3681         struct net_device *ndev = priv->ndev;
3682         struct phy_device *phydev = ndev->phydev;
3683         struct gfar_priv_rx_q *rx_queue = NULL;
3684         int i;
3685
3686         if (unlikely(test_bit(GFAR_RESETTING, &priv->state)))
3687                 return;
3688
3689         if (phydev->link) {
3690                 u32 tempval1 = gfar_read(&regs->maccfg1);
3691                 u32 tempval = gfar_read(&regs->maccfg2);
3692                 u32 ecntrl = gfar_read(&regs->ecntrl);
3693                 u32 tx_flow_oldval = (tempval & MACCFG1_TX_FLOW);
3694
3695                 if (phydev->duplex != priv->oldduplex) {
3696                         if (!(phydev->duplex))
3697                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
3698                         else
3699                                 tempval |= MACCFG2_FULL_DUPLEX;
3700
3701                         priv->oldduplex = phydev->duplex;
3702                 }
3703
3704                 if (phydev->speed != priv->oldspeed) {
3705                         switch (phydev->speed) {
3706                         case 1000:
3707                                 tempval =
3708                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
3709
3710                                 ecntrl &= ~(ECNTRL_R100);
3711                                 break;
3712                         case 100:
3713                         case 10:
3714                                 tempval =
3715                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
3716
3717                                 /* Reduced mode distinguishes
3718                                  * between 10 and 100
3719                                  */
3720                                 if (phydev->speed == SPEED_100)
3721                                         ecntrl |= ECNTRL_R100;
3722                                 else
3723                                         ecntrl &= ~(ECNTRL_R100);
3724                                 break;
3725                         default:
3726                                 netif_warn(priv, link, priv->ndev,
3727                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
3728                                            phydev->speed);
3729                                 break;
3730                         }
3731
3732                         priv->oldspeed = phydev->speed;
3733                 }
3734
3735                 tempval1 &= ~(MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
3736                 tempval1 |= gfar_get_flowctrl_cfg(priv);
3737
3738                 /* Turn last free buffer recording on */
3739                 if ((tempval1 & MACCFG1_TX_FLOW) && !tx_flow_oldval) {
3740                         for (i = 0; i < priv->num_rx_queues; i++) {
3741                                 u32 bdp_dma;
3742
3743                                 rx_queue = priv->rx_queue[i];
3744                                 bdp_dma = gfar_rxbd_dma_lastfree(rx_queue);
3745                                 gfar_write(rx_queue->rfbptr, bdp_dma);
3746                         }
3747
3748                         priv->tx_actual_en = 1;
3749                 }
3750
3751                 if (unlikely(!(tempval1 & MACCFG1_TX_FLOW) && tx_flow_oldval))
3752                         priv->tx_actual_en = 0;
3753
3754                 gfar_write(&regs->maccfg1, tempval1);
3755                 gfar_write(&regs->maccfg2, tempval);
3756                 gfar_write(&regs->ecntrl, ecntrl);
3757
3758                 if (!priv->oldlink)
3759                         priv->oldlink = 1;
3760
3761         } else if (priv->oldlink) {
3762                 priv->oldlink = 0;
3763                 priv->oldspeed = 0;
3764                 priv->oldduplex = -1;
3765         }
3766
3767         if (netif_msg_link(priv))
3768                 phy_print_status(phydev);
3769 }
3770
3771 static const struct of_device_id gfar_match[] =
3772 {
3773         {
3774                 .type = "network",
3775                 .compatible = "gianfar",
3776         },
3777         {
3778                 .compatible = "fsl,etsec2",
3779         },
3780         {},
3781 };
3782 MODULE_DEVICE_TABLE(of, gfar_match);
3783
3784 /* Structure for a device driver */
3785 static struct platform_driver gfar_driver = {
3786         .driver = {
3787                 .name = "fsl-gianfar",
3788                 .pm = GFAR_PM_OPS,
3789                 .of_match_table = gfar_match,
3790         },
3791         .probe = gfar_probe,
3792         .remove = gfar_remove,
3793 };
3794
3795 module_platform_driver(gfar_driver);