2 * Copyright (c) 2014-2015 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include "hns_dsaf_mac.h"
11 #include "hns_dsaf_misc.h"
12 #include "hns_dsaf_ppe.h"
13 #include "hns_dsaf_reg.h"
16 HNS_OP_RESET_FUNC = 0x1,
17 HNS_OP_SERDES_LP_FUNC = 0x2,
18 HNS_OP_LED_SET_FUNC = 0x3,
19 HNS_OP_GET_PORT_TYPE_FUNC = 0x4,
20 HNS_OP_GET_SFP_STAT_FUNC = 0x5,
24 HNS_DSAF_RESET_FUNC = 0x1,
25 HNS_PPE_RESET_FUNC = 0x2,
26 HNS_XGE_RESET_FUNC = 0x4,
27 HNS_GE_RESET_FUNC = 0x5,
28 HNS_DSAF_CHN_RESET_FUNC = 0x6,
29 HNS_ROCE_RESET_FUNC = 0x7,
32 static const guid_t hns_dsaf_acpi_dsm_guid =
33 GUID_INIT(0x1A85AA1A, 0xE293, 0x415E,
34 0x8E, 0x28, 0x8D, 0x69, 0x0A, 0x0F, 0x82, 0x0A);
36 static void dsaf_write_sub(struct dsaf_device *dsaf_dev, u32 reg, u32 val)
38 if (dsaf_dev->sub_ctrl)
39 dsaf_write_syscon(dsaf_dev->sub_ctrl, reg, val);
41 dsaf_write_reg(dsaf_dev->sc_base, reg, val);
44 static u32 dsaf_read_sub(struct dsaf_device *dsaf_dev, u32 reg)
48 if (dsaf_dev->sub_ctrl)
49 ret = dsaf_read_syscon(dsaf_dev->sub_ctrl, reg);
51 ret = dsaf_read_reg(dsaf_dev->sc_base, reg);
56 static void hns_dsaf_acpi_ledctrl_by_port(struct hns_mac_cb *mac_cb, u8 op_type,
57 u32 link, u32 port, u32 act)
59 union acpi_object *obj;
60 union acpi_object obj_args[3], argv4;
62 obj_args[0].integer.type = ACPI_TYPE_INTEGER;
63 obj_args[0].integer.value = link;
64 obj_args[1].integer.type = ACPI_TYPE_INTEGER;
65 obj_args[1].integer.value = port;
66 obj_args[2].integer.type = ACPI_TYPE_INTEGER;
67 obj_args[2].integer.value = act;
69 argv4.type = ACPI_TYPE_PACKAGE;
70 argv4.package.count = 3;
71 argv4.package.elements = obj_args;
73 obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dev),
74 &hns_dsaf_acpi_dsm_guid, 0, op_type, &argv4);
76 dev_warn(mac_cb->dev, "ledctrl fail, link:%d port:%d act:%d!\n",
84 static void hns_cpld_set_led(struct hns_mac_cb *mac_cb, int link_status,
91 pr_err("sfp_led_opt mac_dev is null!\n");
94 if (!mac_cb->cpld_ctrl) {
95 dev_err(mac_cb->dev, "mac_id=%d, cpld syscon is null !\n",
100 if (speed == MAC_SPEED_10000)
103 value = mac_cb->cpld_led_value;
106 dsaf_set_bit(value, DSAF_LED_LINK_B, link_status);
107 dsaf_set_field(value, DSAF_LED_SPEED_M,
108 DSAF_LED_SPEED_S, speed_reg);
109 dsaf_set_bit(value, DSAF_LED_DATA_B, data);
111 if (value != mac_cb->cpld_led_value) {
112 dsaf_write_syscon(mac_cb->cpld_ctrl,
113 mac_cb->cpld_ctrl_reg, value);
114 mac_cb->cpld_led_value = value;
117 value = (mac_cb->cpld_led_value) & (0x1 << DSAF_LED_ANCHOR_B);
118 dsaf_write_syscon(mac_cb->cpld_ctrl,
119 mac_cb->cpld_ctrl_reg, value);
120 mac_cb->cpld_led_value = value;
124 static void hns_cpld_set_led_acpi(struct hns_mac_cb *mac_cb, int link_status,
128 pr_err("cpld_led_set mac_cb is null!\n");
132 hns_dsaf_acpi_ledctrl_by_port(mac_cb, HNS_OP_LED_SET_FUNC,
133 link_status, mac_cb->mac_id, data);
136 static void cpld_led_reset(struct hns_mac_cb *mac_cb)
138 if (!mac_cb || !mac_cb->cpld_ctrl)
141 dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
142 CPLD_LED_DEFAULT_VALUE);
143 mac_cb->cpld_led_value = CPLD_LED_DEFAULT_VALUE;
146 static void cpld_led_reset_acpi(struct hns_mac_cb *mac_cb)
149 pr_err("cpld_led_reset mac_cb is null!\n");
153 if (mac_cb->media_type != HNAE_MEDIA_TYPE_FIBER)
156 hns_dsaf_acpi_ledctrl_by_port(mac_cb, HNS_OP_LED_SET_FUNC,
157 0, mac_cb->mac_id, 0);
160 static int cpld_set_led_id(struct hns_mac_cb *mac_cb,
161 enum hnae_led_state status)
164 case HNAE_LED_ACTIVE:
165 mac_cb->cpld_led_value =
166 dsaf_read_syscon(mac_cb->cpld_ctrl,
167 mac_cb->cpld_ctrl_reg);
168 dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
170 dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
171 mac_cb->cpld_led_value);
173 case HNAE_LED_INACTIVE:
174 dsaf_set_bit(mac_cb->cpld_led_value, DSAF_LED_ANCHOR_B,
175 CPLD_LED_DEFAULT_VALUE);
176 dsaf_write_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg,
177 mac_cb->cpld_led_value);
180 dev_err(mac_cb->dev, "invalid led state: %d!", status);
187 #define RESET_REQ_OR_DREQ 1
189 static void hns_dsaf_acpi_srst_by_port(struct dsaf_device *dsaf_dev, u8 op_type,
190 u32 port_type, u32 port, u32 val)
192 union acpi_object *obj;
193 union acpi_object obj_args[3], argv4;
195 obj_args[0].integer.type = ACPI_TYPE_INTEGER;
196 obj_args[0].integer.value = port_type;
197 obj_args[1].integer.type = ACPI_TYPE_INTEGER;
198 obj_args[1].integer.value = port;
199 obj_args[2].integer.type = ACPI_TYPE_INTEGER;
200 obj_args[2].integer.value = val;
202 argv4.type = ACPI_TYPE_PACKAGE;
203 argv4.package.count = 3;
204 argv4.package.elements = obj_args;
206 obj = acpi_evaluate_dsm(ACPI_HANDLE(dsaf_dev->dev),
207 &hns_dsaf_acpi_dsm_guid, 0, op_type, &argv4);
209 dev_warn(dsaf_dev->dev, "reset port_type%d port%d fail!",
217 static void hns_dsaf_rst(struct dsaf_device *dsaf_dev, bool dereset)
223 xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_REQ_REG;
224 nt_reg_addr = DSAF_SUB_SC_NT_RESET_REQ_REG;
226 xbar_reg_addr = DSAF_SUB_SC_XBAR_RESET_DREQ_REG;
227 nt_reg_addr = DSAF_SUB_SC_NT_RESET_DREQ_REG;
230 dsaf_write_sub(dsaf_dev, xbar_reg_addr, RESET_REQ_OR_DREQ);
231 dsaf_write_sub(dsaf_dev, nt_reg_addr, RESET_REQ_OR_DREQ);
234 static void hns_dsaf_rst_acpi(struct dsaf_device *dsaf_dev, bool dereset)
236 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
241 static void hns_dsaf_xge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
247 if (port >= DSAF_XGE_NUM)
250 reg_val |= RESET_REQ_OR_DREQ;
251 reg_val |= 0x2082082 << dsaf_dev->mac_cb[port]->port_rst_off;
254 reg_addr = DSAF_SUB_SC_XGE_RESET_REQ_REG;
256 reg_addr = DSAF_SUB_SC_XGE_RESET_DREQ_REG;
258 dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
261 static void hns_dsaf_xge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
262 u32 port, bool dereset)
264 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
265 HNS_XGE_RESET_FUNC, port, dereset);
269 * hns_dsaf_srst_chns - reset dsaf channels
270 * @dsaf_dev: dsaf device struct pointer
271 * @msk: xbar channels mask value:
274 * bit12-17 for roce0-5
275 * bit18-19 for com/dfx
276 * @enable: false - request reset , true - drop reset
278 void hns_dsaf_srst_chns(struct dsaf_device *dsaf_dev, u32 msk, bool dereset)
283 reg_addr = DSAF_SUB_SC_DSAF_RESET_REQ_REG;
285 reg_addr = DSAF_SUB_SC_DSAF_RESET_DREQ_REG;
287 dsaf_write_sub(dsaf_dev, reg_addr, msk);
291 * hns_dsaf_srst_chns - reset dsaf channels
292 * @dsaf_dev: dsaf device struct pointer
293 * @msk: xbar channels mask value:
296 * bit12-17 for roce0-5
297 * bit18-19 for com/dfx
298 * @enable: false - request reset , true - drop reset
301 hns_dsaf_srst_chns_acpi(struct dsaf_device *dsaf_dev, u32 msk, bool dereset)
303 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
304 HNS_DSAF_CHN_RESET_FUNC,
308 void hns_dsaf_roce_srst(struct dsaf_device *dsaf_dev, bool dereset)
311 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_RESET_REQ_REG, 1);
313 dsaf_write_sub(dsaf_dev,
314 DSAF_SUB_SC_ROCEE_CLK_DIS_REG, 1);
315 dsaf_write_sub(dsaf_dev,
316 DSAF_SUB_SC_ROCEE_RESET_DREQ_REG, 1);
318 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_CLK_EN_REG, 1);
322 void hns_dsaf_roce_srst_acpi(struct dsaf_device *dsaf_dev, bool dereset)
324 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
325 HNS_ROCE_RESET_FUNC, 0, dereset);
328 static void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
335 if (port >= DSAF_GE_NUM)
338 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
339 reg_val_1 = 0x1 << port;
340 port_rst_off = dsaf_dev->mac_cb[port]->port_rst_off;
341 /* there is difference between V1 and V2 in register.*/
342 reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ?
343 0x1041041 : 0x2082082;
344 reg_val_2 <<= port_rst_off;
347 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
350 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ0_REG,
353 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ0_REG,
356 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
361 reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ? 0x100 : 0x40;
363 reg_val_1 <<= dsaf_dev->reset_offset;
364 reg_val_2 <<= dsaf_dev->reset_offset;
367 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_REQ1_REG,
370 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_REQ_REG,
373 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_GE_RESET_DREQ1_REG,
376 dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_PPE_RESET_DREQ_REG,
382 static void hns_dsaf_ge_srst_by_port_acpi(struct dsaf_device *dsaf_dev,
383 u32 port, bool dereset)
385 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
386 HNS_GE_RESET_FUNC, port, dereset);
389 static void hns_ppe_srst_by_port(struct dsaf_device *dsaf_dev, u32 port,
395 reg_val |= RESET_REQ_OR_DREQ << dsaf_dev->mac_cb[port]->port_rst_off;
398 reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
400 reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
402 dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
406 hns_ppe_srst_by_port_acpi(struct dsaf_device *dsaf_dev, u32 port, bool dereset)
408 hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC,
409 HNS_PPE_RESET_FUNC, port, dereset);
412 static void hns_ppe_com_srst(struct dsaf_device *dsaf_dev, bool dereset)
417 if (!(dev_of_node(dsaf_dev->dev)))
420 if (!HNS_DSAF_IS_DEBUG(dsaf_dev)) {
421 reg_val = RESET_REQ_OR_DREQ;
423 reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_REQ_REG;
425 reg_addr = DSAF_SUB_SC_RCB_PPE_COM_RESET_DREQ_REG;
428 reg_val = 0x100 << dsaf_dev->reset_offset;
431 reg_addr = DSAF_SUB_SC_PPE_RESET_REQ_REG;
433 reg_addr = DSAF_SUB_SC_PPE_RESET_DREQ_REG;
436 dsaf_write_sub(dsaf_dev, reg_addr, reg_val);
440 * hns_mac_get_sds_mode - get phy ifterface form serdes mode
441 * @mac_cb: mac control block
442 * retuen phy interface
444 static phy_interface_t hns_mac_get_phy_if(struct hns_mac_cb *mac_cb)
448 bool is_ver1 = AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver);
449 int mac_id = mac_cb->mac_id;
450 phy_interface_t phy_if;
453 if (HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev))
454 return PHY_INTERFACE_MODE_SGMII;
456 if (mac_id >= 0 && mac_id <= 3)
457 reg = HNS_MAC_HILINK4_REG;
459 reg = HNS_MAC_HILINK3_REG;
461 if (!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev) && mac_id <= 3)
462 reg = HNS_MAC_HILINK4V2_REG;
464 reg = HNS_MAC_HILINK3V2_REG;
467 mode = dsaf_read_sub(mac_cb->dsaf_dev, reg);
468 if (dsaf_get_bit(mode, mac_cb->port_mode_off))
469 phy_if = PHY_INTERFACE_MODE_XGMII;
471 phy_if = PHY_INTERFACE_MODE_SGMII;
476 static phy_interface_t hns_mac_get_phy_if_acpi(struct hns_mac_cb *mac_cb)
478 phy_interface_t phy_if = PHY_INTERFACE_MODE_NA;
479 union acpi_object *obj;
480 union acpi_object obj_args, argv4;
482 obj_args.integer.type = ACPI_TYPE_INTEGER;
483 obj_args.integer.value = mac_cb->mac_id;
485 argv4.type = ACPI_TYPE_PACKAGE,
486 argv4.package.count = 1,
487 argv4.package.elements = &obj_args,
489 obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dev),
490 &hns_dsaf_acpi_dsm_guid, 0,
491 HNS_OP_GET_PORT_TYPE_FUNC, &argv4);
493 if (!obj || obj->type != ACPI_TYPE_INTEGER)
496 phy_if = obj->integer.value ?
497 PHY_INTERFACE_MODE_XGMII : PHY_INTERFACE_MODE_SGMII;
499 dev_dbg(mac_cb->dev, "mac_id=%d, phy_if=%d\n", mac_cb->mac_id, phy_if);
506 int hns_mac_get_sfp_prsnt(struct hns_mac_cb *mac_cb, int *sfp_prsnt)
508 if (!mac_cb->cpld_ctrl)
511 *sfp_prsnt = !dsaf_read_syscon(mac_cb->cpld_ctrl, mac_cb->cpld_ctrl_reg
512 + MAC_SFP_PORT_OFFSET);
517 int hns_mac_get_sfp_prsnt_acpi(struct hns_mac_cb *mac_cb, int *sfp_prsnt)
519 union acpi_object *obj;
520 union acpi_object obj_args, argv4;
522 obj_args.integer.type = ACPI_TYPE_INTEGER;
523 obj_args.integer.value = mac_cb->mac_id;
525 argv4.type = ACPI_TYPE_PACKAGE,
526 argv4.package.count = 1,
527 argv4.package.elements = &obj_args,
529 obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dev),
530 &hns_dsaf_acpi_dsm_guid, 0,
531 HNS_OP_GET_SFP_STAT_FUNC, &argv4);
533 if (!obj || obj->type != ACPI_TYPE_INTEGER)
536 *sfp_prsnt = obj->integer.value;
544 * hns_mac_config_sds_loopback - set loop back for serdes
545 * @mac_cb: mac control block
546 * retuen 0 == success
548 static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en)
550 const u8 lane_id[] = {
551 0, /* mac 0 -> lane 0 */
552 1, /* mac 1 -> lane 1 */
553 2, /* mac 2 -> lane 2 */
554 3, /* mac 3 -> lane 3 */
555 2, /* mac 4 -> lane 2 */
556 3, /* mac 5 -> lane 3 */
557 0, /* mac 6 -> lane 0 */
558 1 /* mac 7 -> lane 1 */
560 #define RX_CSR(lane, reg) ((0x4080 + (reg) * 0x0002 + (lane) * 0x0200) * 2)
561 u64 reg_offset = RX_CSR(lane_id[mac_cb->mac_id], 0);
564 int ret = hns_mac_get_sfp_prsnt(mac_cb, &sfp_prsnt);
566 if (!mac_cb->phy_dev) {
568 pr_info("please confirm sfp is present or not\n");
571 pr_info("no sfp in this eth\n");
574 if (mac_cb->serdes_ctrl) {
577 if (!AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver)) {
578 #define HILINK_ACCESS_SEL_CFG 0x40008
579 /* hilink4 & hilink3 use the same xge training and
580 * xge u adaptor. There is a hilink access sel cfg
581 * register to select which one to be configed
583 if ((!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) &&
584 (mac_cb->mac_id <= 3))
585 dsaf_write_syscon(mac_cb->serdes_ctrl,
586 HILINK_ACCESS_SEL_CFG, 0);
588 dsaf_write_syscon(mac_cb->serdes_ctrl,
589 HILINK_ACCESS_SEL_CFG, 3);
592 origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);
594 dsaf_set_field(origin, 1ull << 10, 10, en);
595 dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
597 u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
598 (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
599 dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en);
606 hns_mac_config_sds_loopback_acpi(struct hns_mac_cb *mac_cb, bool en)
608 union acpi_object *obj;
609 union acpi_object obj_args[3], argv4;
611 obj_args[0].integer.type = ACPI_TYPE_INTEGER;
612 obj_args[0].integer.value = mac_cb->mac_id;
613 obj_args[1].integer.type = ACPI_TYPE_INTEGER;
614 obj_args[1].integer.value = !!en;
616 argv4.type = ACPI_TYPE_PACKAGE;
617 argv4.package.count = 2;
618 argv4.package.elements = obj_args;
620 obj = acpi_evaluate_dsm(ACPI_HANDLE(mac_cb->dsaf_dev->dev),
621 &hns_dsaf_acpi_dsm_guid, 0,
622 HNS_OP_SERDES_LP_FUNC, &argv4);
624 dev_warn(mac_cb->dsaf_dev->dev, "set port%d serdes lp fail!",
635 struct dsaf_misc_op *hns_misc_op_get(struct dsaf_device *dsaf_dev)
637 struct dsaf_misc_op *misc_op;
639 misc_op = devm_kzalloc(dsaf_dev->dev, sizeof(*misc_op), GFP_KERNEL);
643 if (dev_of_node(dsaf_dev->dev)) {
644 misc_op->cpld_set_led = hns_cpld_set_led;
645 misc_op->cpld_reset_led = cpld_led_reset;
646 misc_op->cpld_set_led_id = cpld_set_led_id;
648 misc_op->dsaf_reset = hns_dsaf_rst;
649 misc_op->xge_srst = hns_dsaf_xge_srst_by_port;
650 misc_op->ge_srst = hns_dsaf_ge_srst_by_port;
651 misc_op->ppe_srst = hns_ppe_srst_by_port;
652 misc_op->ppe_comm_srst = hns_ppe_com_srst;
653 misc_op->hns_dsaf_srst_chns = hns_dsaf_srst_chns;
654 misc_op->hns_dsaf_roce_srst = hns_dsaf_roce_srst;
656 misc_op->get_phy_if = hns_mac_get_phy_if;
657 misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt;
659 misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback;
660 } else if (is_acpi_node(dsaf_dev->dev->fwnode)) {
661 misc_op->cpld_set_led = hns_cpld_set_led_acpi;
662 misc_op->cpld_reset_led = cpld_led_reset_acpi;
663 misc_op->cpld_set_led_id = cpld_set_led_id;
665 misc_op->dsaf_reset = hns_dsaf_rst_acpi;
666 misc_op->xge_srst = hns_dsaf_xge_srst_by_port_acpi;
667 misc_op->ge_srst = hns_dsaf_ge_srst_by_port_acpi;
668 misc_op->ppe_srst = hns_ppe_srst_by_port_acpi;
669 misc_op->ppe_comm_srst = hns_ppe_com_srst;
670 misc_op->hns_dsaf_srst_chns = hns_dsaf_srst_chns_acpi;
671 misc_op->hns_dsaf_roce_srst = hns_dsaf_roce_srst_acpi;
673 misc_op->get_phy_if = hns_mac_get_phy_if_acpi;
674 misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt_acpi;
676 misc_op->cfg_serdes_loopback = hns_mac_config_sds_loopback_acpi;
678 devm_kfree(dsaf_dev->dev, (void *)misc_op);
682 return (void *)misc_op;
685 static int hns_dsaf_dev_match(struct device *dev, void *fwnode)
687 return dev->fwnode == fwnode;
691 platform_device *hns_dsaf_find_platform_device(struct fwnode_handle *fwnode)
695 dev = bus_find_device(&platform_bus_type, NULL,
696 fwnode, hns_dsaf_dev_match);
697 return dev ? to_platform_device(dev) : NULL;