1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
4 #include <linux/acpi.h>
5 #include <linux/device.h>
6 #include <linux/etherdevice.h>
7 #include <linux/init.h>
8 #include <linux/interrupt.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/netdevice.h>
12 #include <linux/pci.h>
13 #include <linux/platform_device.h>
14 #include <linux/if_vlan.h>
15 #include <net/rtnetlink.h>
16 #include "hclge_cmd.h"
17 #include "hclge_dcb.h"
18 #include "hclge_main.h"
19 #include "hclge_mbx.h"
20 #include "hclge_mdio.h"
24 #define HCLGE_NAME "hclge"
25 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
26 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
27 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
28 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
30 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
31 enum hclge_mta_dmac_sel_type mta_mac_sel,
33 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
34 static int hclge_init_vlan_config(struct hclge_dev *hdev);
35 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
37 static struct hnae3_ae_algo ae_algo;
39 static const struct pci_device_id ae_algo_pci_tbl[] = {
40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
47 /* required last entry */
51 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
53 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
55 "Serdes Loopback test",
59 static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
60 {"igu_rx_oversize_pkt",
61 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
62 {"igu_rx_undersize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
64 {"igu_rx_out_all_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
72 {"egu_tx_out_all_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
80 {"ssu_ppp_mac_key_num",
81 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
82 {"ssu_ppp_host_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
84 {"ppp_ssu_mac_rlt_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
86 {"ppp_ssu_host_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
98 static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
100 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
101 {"igu_rx_no_eof_pkt",
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
103 {"igu_rx_no_sof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
106 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
107 {"ssu_full_drop_num",
108 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
109 {"ssu_part_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
112 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
118 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
120 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
123 {"qcn_fb_invaild_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
125 {"rx_packet_tc0_in_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
127 {"rx_packet_tc1_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
129 {"rx_packet_tc2_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
131 {"rx_packet_tc3_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
133 {"rx_packet_tc4_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
135 {"rx_packet_tc5_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
137 {"rx_packet_tc6_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
139 {"rx_packet_tc7_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
141 {"rx_packet_tc0_out_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
143 {"rx_packet_tc1_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
145 {"rx_packet_tc2_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
147 {"rx_packet_tc3_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
149 {"rx_packet_tc4_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
151 {"rx_packet_tc5_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
153 {"rx_packet_tc6_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
155 {"rx_packet_tc7_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
157 {"tx_packet_tc0_in_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
159 {"tx_packet_tc1_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
161 {"tx_packet_tc2_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
163 {"tx_packet_tc3_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
165 {"tx_packet_tc4_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
167 {"tx_packet_tc5_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
169 {"tx_packet_tc6_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
171 {"tx_packet_tc7_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
173 {"tx_packet_tc0_out_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
175 {"tx_packet_tc1_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
177 {"tx_packet_tc2_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
179 {"tx_packet_tc3_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
181 {"tx_packet_tc4_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
183 {"tx_packet_tc5_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
185 {"tx_packet_tc6_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
187 {"tx_packet_tc7_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
189 {"pkt_curr_buf_tc0_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
191 {"pkt_curr_buf_tc1_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
193 {"pkt_curr_buf_tc2_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
195 {"pkt_curr_buf_tc3_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
197 {"pkt_curr_buf_tc4_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
199 {"pkt_curr_buf_tc5_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
201 {"pkt_curr_buf_tc6_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
203 {"pkt_curr_buf_tc7_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
206 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
207 {"lo_pri_unicast_rlt_drop_num",
208 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
209 {"hi_pri_multicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
211 {"lo_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
213 {"rx_oq_drop_pkt_cnt",
214 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
215 {"tx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
217 {"nic_l2_err_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
219 {"roc_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
223 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
224 {"mac_tx_mac_pause_num",
225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
226 {"mac_rx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
228 {"mac_tx_pfc_pri0_pkt_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
230 {"mac_tx_pfc_pri1_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
232 {"mac_tx_pfc_pri2_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
234 {"mac_tx_pfc_pri3_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
236 {"mac_tx_pfc_pri4_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
238 {"mac_tx_pfc_pri5_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
240 {"mac_tx_pfc_pri6_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
242 {"mac_tx_pfc_pri7_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
244 {"mac_rx_pfc_pri0_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
246 {"mac_rx_pfc_pri1_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
248 {"mac_rx_pfc_pri2_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
250 {"mac_rx_pfc_pri3_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
252 {"mac_rx_pfc_pri4_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
254 {"mac_rx_pfc_pri5_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
256 {"mac_rx_pfc_pri6_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
258 {"mac_rx_pfc_pri7_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
260 {"mac_tx_total_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
262 {"mac_tx_total_oct_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
264 {"mac_tx_good_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
266 {"mac_tx_bad_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
268 {"mac_tx_good_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
270 {"mac_tx_bad_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
272 {"mac_tx_uni_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
274 {"mac_tx_multi_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
276 {"mac_tx_broad_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
278 {"mac_tx_undersize_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
280 {"mac_tx_oversize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
282 {"mac_tx_64_oct_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
284 {"mac_tx_65_127_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
286 {"mac_tx_128_255_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
288 {"mac_tx_256_511_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
290 {"mac_tx_512_1023_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
292 {"mac_tx_1024_1518_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
294 {"mac_tx_1519_2047_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
296 {"mac_tx_2048_4095_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
298 {"mac_tx_4096_8191_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
300 {"mac_tx_8192_9216_oct_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
302 {"mac_tx_9217_12287_oct_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
304 {"mac_tx_12288_16383_oct_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
306 {"mac_tx_1519_max_good_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
308 {"mac_tx_1519_max_bad_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
310 {"mac_rx_total_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
312 {"mac_rx_total_oct_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
314 {"mac_rx_good_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
316 {"mac_rx_bad_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
318 {"mac_rx_good_oct_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
320 {"mac_rx_bad_oct_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
322 {"mac_rx_uni_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
324 {"mac_rx_multi_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
326 {"mac_rx_broad_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
328 {"mac_rx_undersize_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
330 {"mac_rx_oversize_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
332 {"mac_rx_64_oct_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
334 {"mac_rx_65_127_oct_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
336 {"mac_rx_128_255_oct_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
338 {"mac_rx_256_511_oct_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
340 {"mac_rx_512_1023_oct_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
342 {"mac_rx_1024_1518_oct_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
344 {"mac_rx_1519_2047_oct_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
346 {"mac_rx_2048_4095_oct_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
348 {"mac_rx_4096_8191_oct_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
350 {"mac_rx_8192_9216_oct_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
352 {"mac_rx_9217_12287_oct_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
354 {"mac_rx_12288_16383_oct_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
356 {"mac_rx_1519_max_good_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
358 {"mac_rx_1519_max_bad_pkt_num",
359 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
361 {"mac_tx_fragment_pkt_num",
362 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
363 {"mac_tx_undermin_pkt_num",
364 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
365 {"mac_tx_jabber_pkt_num",
366 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
367 {"mac_tx_err_all_pkt_num",
368 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
369 {"mac_tx_from_app_good_pkt_num",
370 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
371 {"mac_tx_from_app_bad_pkt_num",
372 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
373 {"mac_rx_fragment_pkt_num",
374 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
375 {"mac_rx_undermin_pkt_num",
376 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
377 {"mac_rx_jabber_pkt_num",
378 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
379 {"mac_rx_fcs_err_pkt_num",
380 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
381 {"mac_rx_send_app_good_pkt_num",
382 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
383 {"mac_rx_send_app_bad_pkt_num",
384 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
387 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
389 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
390 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
391 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
392 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
393 .i_port_bitmap = 0x1,
397 static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
399 #define HCLGE_64_BIT_CMD_NUM 5
400 #define HCLGE_64_BIT_RTN_DATANUM 4
401 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
402 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
407 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
408 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
410 dev_err(&hdev->pdev->dev,
411 "Get 64 bit pkt stats fail, status = %d.\n", ret);
415 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
416 if (unlikely(i == 0)) {
417 desc_data = (__le64 *)(&desc[i].data[0]);
418 n = HCLGE_64_BIT_RTN_DATANUM - 1;
420 desc_data = (__le64 *)(&desc[i]);
421 n = HCLGE_64_BIT_RTN_DATANUM;
423 for (k = 0; k < n; k++) {
424 *data++ += le64_to_cpu(*desc_data);
432 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
434 stats->pkt_curr_buf_cnt = 0;
435 stats->pkt_curr_buf_tc0_cnt = 0;
436 stats->pkt_curr_buf_tc1_cnt = 0;
437 stats->pkt_curr_buf_tc2_cnt = 0;
438 stats->pkt_curr_buf_tc3_cnt = 0;
439 stats->pkt_curr_buf_tc4_cnt = 0;
440 stats->pkt_curr_buf_tc5_cnt = 0;
441 stats->pkt_curr_buf_tc6_cnt = 0;
442 stats->pkt_curr_buf_tc7_cnt = 0;
445 static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
447 #define HCLGE_32_BIT_CMD_NUM 8
448 #define HCLGE_32_BIT_RTN_DATANUM 8
450 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
451 struct hclge_32_bit_stats *all_32_bit_stats;
457 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
458 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
460 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
461 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
463 dev_err(&hdev->pdev->dev,
464 "Get 32 bit pkt stats fail, status = %d.\n", ret);
469 hclge_reset_partial_32bit_counter(all_32_bit_stats);
470 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
471 if (unlikely(i == 0)) {
472 __le16 *desc_data_16bit;
474 all_32_bit_stats->igu_rx_err_pkt +=
475 le32_to_cpu(desc[i].data[0]);
477 desc_data_16bit = (__le16 *)&desc[i].data[1];
478 all_32_bit_stats->igu_rx_no_eof_pkt +=
479 le16_to_cpu(*desc_data_16bit);
482 all_32_bit_stats->igu_rx_no_sof_pkt +=
483 le16_to_cpu(*desc_data_16bit);
485 desc_data = &desc[i].data[2];
486 n = HCLGE_32_BIT_RTN_DATANUM - 4;
488 desc_data = (__le32 *)&desc[i];
489 n = HCLGE_32_BIT_RTN_DATANUM;
491 for (k = 0; k < n; k++) {
492 *data++ += le32_to_cpu(*desc_data);
500 static int hclge_mac_update_stats(struct hclge_dev *hdev)
502 #define HCLGE_MAC_CMD_NUM 21
503 #define HCLGE_RTN_DATA_NUM 4
505 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
506 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
511 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
512 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
514 dev_err(&hdev->pdev->dev,
515 "Get MAC pkt stats fail, status = %d.\n", ret);
520 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
521 if (unlikely(i == 0)) {
522 desc_data = (__le64 *)(&desc[i].data[0]);
523 n = HCLGE_RTN_DATA_NUM - 2;
525 desc_data = (__le64 *)(&desc[i]);
526 n = HCLGE_RTN_DATA_NUM;
528 for (k = 0; k < n; k++) {
529 *data++ += le64_to_cpu(*desc_data);
537 static int hclge_tqps_update_stats(struct hnae3_handle *handle)
539 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
540 struct hclge_vport *vport = hclge_get_vport(handle);
541 struct hclge_dev *hdev = vport->back;
542 struct hnae3_queue *queue;
543 struct hclge_desc desc[1];
544 struct hclge_tqp *tqp;
547 for (i = 0; i < kinfo->num_tqps; i++) {
548 queue = handle->kinfo.tqp[i];
549 tqp = container_of(queue, struct hclge_tqp, q);
550 /* command : HCLGE_OPC_QUERY_IGU_STAT */
551 hclge_cmd_setup_basic_desc(&desc[0],
552 HCLGE_OPC_QUERY_RX_STATUS,
555 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
556 ret = hclge_cmd_send(&hdev->hw, desc, 1);
558 dev_err(&hdev->pdev->dev,
559 "Query tqp stat fail, status = %d,queue = %d\n",
563 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
564 le32_to_cpu(desc[0].data[1]);
567 for (i = 0; i < kinfo->num_tqps; i++) {
568 queue = handle->kinfo.tqp[i];
569 tqp = container_of(queue, struct hclge_tqp, q);
570 /* command : HCLGE_OPC_QUERY_IGU_STAT */
571 hclge_cmd_setup_basic_desc(&desc[0],
572 HCLGE_OPC_QUERY_TX_STATUS,
575 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
576 ret = hclge_cmd_send(&hdev->hw, desc, 1);
578 dev_err(&hdev->pdev->dev,
579 "Query tqp stat fail, status = %d,queue = %d\n",
583 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
584 le32_to_cpu(desc[0].data[1]);
590 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
592 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
593 struct hclge_tqp *tqp;
597 for (i = 0; i < kinfo->num_tqps; i++) {
598 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
599 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
602 for (i = 0; i < kinfo->num_tqps; i++) {
603 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
604 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
610 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
612 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
614 return kinfo->num_tqps * (2);
617 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
619 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
623 for (i = 0; i < kinfo->num_tqps; i++) {
624 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
625 struct hclge_tqp, q);
626 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
628 buff = buff + ETH_GSTRING_LEN;
631 for (i = 0; i < kinfo->num_tqps; i++) {
632 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
633 struct hclge_tqp, q);
634 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
636 buff = buff + ETH_GSTRING_LEN;
642 static u64 *hclge_comm_get_stats(void *comm_stats,
643 const struct hclge_comm_stats_str strs[],
649 for (i = 0; i < size; i++)
650 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
655 static u8 *hclge_comm_get_strings(u32 stringset,
656 const struct hclge_comm_stats_str strs[],
659 char *buff = (char *)data;
662 if (stringset != ETH_SS_STATS)
665 for (i = 0; i < size; i++) {
666 snprintf(buff, ETH_GSTRING_LEN,
668 buff = buff + ETH_GSTRING_LEN;
674 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
675 struct net_device_stats *net_stats)
677 net_stats->tx_dropped = 0;
678 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
679 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
680 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
682 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
683 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
684 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
685 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
686 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
688 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
689 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
691 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
692 net_stats->rx_length_errors =
693 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
694 net_stats->rx_length_errors +=
695 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
696 net_stats->rx_over_errors =
697 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
700 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
702 struct hnae3_handle *handle;
705 handle = &hdev->vport[0].nic;
706 if (handle->client) {
707 status = hclge_tqps_update_stats(handle);
709 dev_err(&hdev->pdev->dev,
710 "Update TQPS stats fail, status = %d.\n",
715 status = hclge_mac_update_stats(hdev);
717 dev_err(&hdev->pdev->dev,
718 "Update MAC stats fail, status = %d.\n", status);
720 status = hclge_32_bit_update_stats(hdev);
722 dev_err(&hdev->pdev->dev,
723 "Update 32 bit stats fail, status = %d.\n",
726 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
729 static void hclge_update_stats(struct hnae3_handle *handle,
730 struct net_device_stats *net_stats)
732 struct hclge_vport *vport = hclge_get_vport(handle);
733 struct hclge_dev *hdev = vport->back;
734 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
737 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
740 status = hclge_mac_update_stats(hdev);
742 dev_err(&hdev->pdev->dev,
743 "Update MAC stats fail, status = %d.\n",
746 status = hclge_32_bit_update_stats(hdev);
748 dev_err(&hdev->pdev->dev,
749 "Update 32 bit stats fail, status = %d.\n",
752 status = hclge_64_bit_update_stats(hdev);
754 dev_err(&hdev->pdev->dev,
755 "Update 64 bit stats fail, status = %d.\n",
758 status = hclge_tqps_update_stats(handle);
760 dev_err(&hdev->pdev->dev,
761 "Update TQPS stats fail, status = %d.\n",
764 hclge_update_netstat(hw_stats, net_stats);
766 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
769 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
771 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
773 struct hclge_vport *vport = hclge_get_vport(handle);
774 struct hclge_dev *hdev = vport->back;
777 /* Loopback test support rules:
778 * mac: only GE mode support
779 * serdes: all mac mode will support include GE/XGE/LGE/CGE
780 * phy: only support when phy device exist on board
782 if (stringset == ETH_SS_TEST) {
783 /* clear loopback bit flags at first */
784 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
785 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
786 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
787 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
789 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
793 handle->flags |= HNAE3_SUPPORT_SERDES_LOOPBACK;
794 } else if (stringset == ETH_SS_STATS) {
795 count = ARRAY_SIZE(g_mac_stats_string) +
796 ARRAY_SIZE(g_all_32bit_stats_string) +
797 ARRAY_SIZE(g_all_64bit_stats_string) +
798 hclge_tqps_get_sset_count(handle, stringset);
804 static void hclge_get_strings(struct hnae3_handle *handle,
808 u8 *p = (char *)data;
811 if (stringset == ETH_SS_STATS) {
812 size = ARRAY_SIZE(g_mac_stats_string);
813 p = hclge_comm_get_strings(stringset,
817 size = ARRAY_SIZE(g_all_32bit_stats_string);
818 p = hclge_comm_get_strings(stringset,
819 g_all_32bit_stats_string,
822 size = ARRAY_SIZE(g_all_64bit_stats_string);
823 p = hclge_comm_get_strings(stringset,
824 g_all_64bit_stats_string,
827 p = hclge_tqps_get_strings(handle, p);
828 } else if (stringset == ETH_SS_TEST) {
829 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
831 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
833 p += ETH_GSTRING_LEN;
835 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
837 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
839 p += ETH_GSTRING_LEN;
841 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
843 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
845 p += ETH_GSTRING_LEN;
850 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
852 struct hclge_vport *vport = hclge_get_vport(handle);
853 struct hclge_dev *hdev = vport->back;
856 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
858 ARRAY_SIZE(g_mac_stats_string),
860 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
861 g_all_32bit_stats_string,
862 ARRAY_SIZE(g_all_32bit_stats_string),
864 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
865 g_all_64bit_stats_string,
866 ARRAY_SIZE(g_all_64bit_stats_string),
868 p = hclge_tqps_get_stats(handle, p);
871 static int hclge_parse_func_status(struct hclge_dev *hdev,
872 struct hclge_func_status_cmd *status)
874 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
877 /* Set the pf to main pf */
878 if (status->pf_state & HCLGE_PF_STATE_MAIN)
879 hdev->flag |= HCLGE_FLAG_MAIN;
881 hdev->flag &= ~HCLGE_FLAG_MAIN;
886 static int hclge_query_function_status(struct hclge_dev *hdev)
888 struct hclge_func_status_cmd *req;
889 struct hclge_desc desc;
893 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
894 req = (struct hclge_func_status_cmd *)desc.data;
897 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
899 dev_err(&hdev->pdev->dev,
900 "query function status failed %d.\n",
906 /* Check pf reset is done */
909 usleep_range(1000, 2000);
910 } while (timeout++ < 5);
912 ret = hclge_parse_func_status(hdev, req);
917 static int hclge_query_pf_resource(struct hclge_dev *hdev)
919 struct hclge_pf_res_cmd *req;
920 struct hclge_desc desc;
923 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
924 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
926 dev_err(&hdev->pdev->dev,
927 "query pf resource failed %d.\n", ret);
931 req = (struct hclge_pf_res_cmd *)desc.data;
932 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
933 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
935 if (hnae3_dev_roce_supported(hdev)) {
936 hdev->roce_base_msix_offset =
937 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
938 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
940 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
941 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
943 /* PF should have NIC vectors and Roce vectors,
944 * NIC vectors are queued before Roce vectors.
946 hdev->num_msi = hdev->num_roce_msi +
947 hdev->roce_base_msix_offset;
950 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
951 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
957 static int hclge_parse_speed(int speed_cmd, int *speed)
961 *speed = HCLGE_MAC_SPEED_10M;
964 *speed = HCLGE_MAC_SPEED_100M;
967 *speed = HCLGE_MAC_SPEED_1G;
970 *speed = HCLGE_MAC_SPEED_10G;
973 *speed = HCLGE_MAC_SPEED_25G;
976 *speed = HCLGE_MAC_SPEED_40G;
979 *speed = HCLGE_MAC_SPEED_50G;
982 *speed = HCLGE_MAC_SPEED_100G;
991 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
994 unsigned long *supported = hdev->hw.mac.supported;
996 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
997 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
1000 if (speed_ability & HCLGE_SUPPORT_10G_BIT)
1001 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
1004 if (speed_ability & HCLGE_SUPPORT_25G_BIT)
1005 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
1008 if (speed_ability & HCLGE_SUPPORT_50G_BIT)
1009 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
1012 if (speed_ability & HCLGE_SUPPORT_100G_BIT)
1013 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
1016 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
1017 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
1020 static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
1022 u8 media_type = hdev->hw.mac.media_type;
1024 if (media_type != HNAE3_MEDIA_TYPE_FIBER)
1027 hclge_parse_fiber_link_mode(hdev, speed_ability);
1030 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
1032 struct hclge_cfg_param_cmd *req;
1033 u64 mac_addr_tmp_high;
1037 req = (struct hclge_cfg_param_cmd *)desc[0].data;
1039 /* get the configuration */
1040 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1043 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1044 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
1045 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
1046 HCLGE_CFG_TQP_DESC_N_M,
1047 HCLGE_CFG_TQP_DESC_N_S);
1049 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
1050 HCLGE_CFG_PHY_ADDR_M,
1051 HCLGE_CFG_PHY_ADDR_S);
1052 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
1053 HCLGE_CFG_MEDIA_TP_M,
1054 HCLGE_CFG_MEDIA_TP_S);
1055 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
1056 HCLGE_CFG_RX_BUF_LEN_M,
1057 HCLGE_CFG_RX_BUF_LEN_S);
1058 /* get mac_address */
1059 mac_addr_tmp = __le32_to_cpu(req->param[2]);
1060 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
1061 HCLGE_CFG_MAC_ADDR_H_M,
1062 HCLGE_CFG_MAC_ADDR_H_S);
1064 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
1066 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
1067 HCLGE_CFG_DEFAULT_SPEED_M,
1068 HCLGE_CFG_DEFAULT_SPEED_S);
1069 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
1070 HCLGE_CFG_RSS_SIZE_M,
1071 HCLGE_CFG_RSS_SIZE_S);
1073 for (i = 0; i < ETH_ALEN; i++)
1074 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
1076 req = (struct hclge_cfg_param_cmd *)desc[1].data;
1077 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
1079 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
1080 HCLGE_CFG_SPEED_ABILITY_M,
1081 HCLGE_CFG_SPEED_ABILITY_S);
1084 /* hclge_get_cfg: query the static parameter from flash
1085 * @hdev: pointer to struct hclge_dev
1086 * @hcfg: the config structure to be getted
1088 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1090 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
1091 struct hclge_cfg_param_cmd *req;
1094 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
1097 req = (struct hclge_cfg_param_cmd *)desc[i].data;
1098 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1100 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
1101 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1102 /* Len should be united by 4 bytes when send to hardware */
1103 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1104 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1105 req->offset = cpu_to_le32(offset);
1108 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1110 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
1114 hclge_parse_cfg(hcfg, desc);
1119 static int hclge_get_cap(struct hclge_dev *hdev)
1123 ret = hclge_query_function_status(hdev);
1125 dev_err(&hdev->pdev->dev,
1126 "query function status error %d.\n", ret);
1130 /* get pf resource */
1131 ret = hclge_query_pf_resource(hdev);
1133 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
1138 static int hclge_configure(struct hclge_dev *hdev)
1140 struct hclge_cfg cfg;
1143 ret = hclge_get_cfg(hdev, &cfg);
1145 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1149 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1150 hdev->base_tqp_pid = 0;
1151 hdev->rss_size_max = cfg.rss_size_max;
1152 hdev->rx_buf_len = cfg.rx_buf_len;
1153 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
1154 hdev->hw.mac.media_type = cfg.media_type;
1155 hdev->hw.mac.phy_addr = cfg.phy_addr;
1156 hdev->num_desc = cfg.tqp_desc_num;
1157 hdev->tm_info.num_pg = 1;
1158 hdev->tc_max = cfg.tc_num;
1159 hdev->tm_info.hw_pfc_map = 0;
1161 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1163 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1167 hclge_parse_link_mode(hdev, cfg.speed_ability);
1169 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1170 (hdev->tc_max < 1)) {
1171 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
1176 /* Dev does not support DCB */
1177 if (!hnae3_dev_dcb_supported(hdev)) {
1181 hdev->pfc_max = hdev->tc_max;
1184 hdev->tm_info.num_tc = hdev->tc_max;
1186 /* Currently not support uncontiuous tc */
1187 for (i = 0; i < hdev->tm_info.num_tc; i++)
1188 hnae3_set_bit(hdev->hw_tc_map, i, 1);
1190 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1195 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1198 struct hclge_cfg_tso_status_cmd *req;
1199 struct hclge_desc desc;
1202 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1204 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
1207 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1208 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
1209 req->tso_mss_min = cpu_to_le16(tso_mss);
1212 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1213 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
1214 req->tso_mss_max = cpu_to_le16(tso_mss);
1216 return hclge_cmd_send(&hdev->hw, &desc, 1);
1219 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1221 struct hclge_tqp *tqp;
1224 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1225 sizeof(struct hclge_tqp), GFP_KERNEL);
1231 for (i = 0; i < hdev->num_tqps; i++) {
1232 tqp->dev = &hdev->pdev->dev;
1235 tqp->q.ae_algo = &ae_algo;
1236 tqp->q.buf_size = hdev->rx_buf_len;
1237 tqp->q.desc_num = hdev->num_desc;
1238 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1239 i * HCLGE_TQP_REG_SIZE;
1247 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1248 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1250 struct hclge_tqp_map_cmd *req;
1251 struct hclge_desc desc;
1254 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1256 req = (struct hclge_tqp_map_cmd *)desc.data;
1257 req->tqp_id = cpu_to_le16(tqp_pid);
1258 req->tqp_vf = func_id;
1259 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1260 1 << HCLGE_TQP_MAP_EN_B;
1261 req->tqp_vid = cpu_to_le16(tqp_vid);
1263 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1265 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
1270 static int hclge_assign_tqp(struct hclge_vport *vport)
1272 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1273 struct hclge_dev *hdev = vport->back;
1276 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1277 alloced < kinfo->num_tqps; i++) {
1278 if (!hdev->htqp[i].alloced) {
1279 hdev->htqp[i].q.handle = &vport->nic;
1280 hdev->htqp[i].q.tqp_index = alloced;
1281 hdev->htqp[i].q.desc_num = kinfo->num_desc;
1282 kinfo->tqp[alloced] = &hdev->htqp[i].q;
1283 hdev->htqp[i].alloced = true;
1287 vport->alloc_tqps = kinfo->num_tqps;
1292 static int hclge_knic_setup(struct hclge_vport *vport,
1293 u16 num_tqps, u16 num_desc)
1295 struct hnae3_handle *nic = &vport->nic;
1296 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1297 struct hclge_dev *hdev = vport->back;
1300 kinfo->num_desc = num_desc;
1301 kinfo->rx_buf_len = hdev->rx_buf_len;
1302 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1304 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1305 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1307 for (i = 0; i < HNAE3_MAX_TC; i++) {
1308 if (hdev->hw_tc_map & BIT(i)) {
1309 kinfo->tc_info[i].enable = true;
1310 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1311 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1312 kinfo->tc_info[i].tc = i;
1314 /* Set to default queue if TC is disable */
1315 kinfo->tc_info[i].enable = false;
1316 kinfo->tc_info[i].tqp_offset = 0;
1317 kinfo->tc_info[i].tqp_count = 1;
1318 kinfo->tc_info[i].tc = 0;
1322 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1323 sizeof(struct hnae3_queue *), GFP_KERNEL);
1327 ret = hclge_assign_tqp(vport);
1329 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1334 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1335 struct hclge_vport *vport)
1337 struct hnae3_handle *nic = &vport->nic;
1338 struct hnae3_knic_private_info *kinfo;
1341 kinfo = &nic->kinfo;
1342 for (i = 0; i < kinfo->num_tqps; i++) {
1343 struct hclge_tqp *q =
1344 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1348 is_pf = !(vport->vport_id);
1349 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1358 static int hclge_map_tqp(struct hclge_dev *hdev)
1360 struct hclge_vport *vport = hdev->vport;
1363 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1364 for (i = 0; i < num_vport; i++) {
1367 ret = hclge_map_tqp_to_vport(hdev, vport);
1377 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1379 /* this would be initialized later */
1382 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1384 struct hnae3_handle *nic = &vport->nic;
1385 struct hclge_dev *hdev = vport->back;
1388 nic->pdev = hdev->pdev;
1389 nic->ae_algo = &ae_algo;
1390 nic->numa_node_mask = hdev->numa_node_mask;
1392 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1393 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc);
1395 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1400 hclge_unic_setup(vport, num_tqps);
1406 static int hclge_alloc_vport(struct hclge_dev *hdev)
1408 struct pci_dev *pdev = hdev->pdev;
1409 struct hclge_vport *vport;
1415 /* We need to alloc a vport for main NIC of PF */
1416 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1418 if (hdev->num_tqps < num_vport) {
1419 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1420 hdev->num_tqps, num_vport);
1424 /* Alloc the same number of TQPs for every vport */
1425 tqp_per_vport = hdev->num_tqps / num_vport;
1426 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1428 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1433 hdev->vport = vport;
1434 hdev->num_alloc_vport = num_vport;
1436 if (IS_ENABLED(CONFIG_PCI_IOV))
1437 hdev->num_alloc_vfs = hdev->num_req_vfs;
1439 for (i = 0; i < num_vport; i++) {
1441 vport->vport_id = i;
1444 ret = hclge_vport_setup(vport, tqp_main_vport);
1446 ret = hclge_vport_setup(vport, tqp_per_vport);
1449 "vport setup failed for vport %d, %d\n",
1460 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1461 struct hclge_pkt_buf_alloc *buf_alloc)
1463 /* TX buffer size is unit by 128 byte */
1464 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1465 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1466 struct hclge_tx_buff_alloc_cmd *req;
1467 struct hclge_desc desc;
1471 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1473 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1474 for (i = 0; i < HCLGE_TC_NUM; i++) {
1475 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1477 req->tx_pkt_buff[i] =
1478 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1479 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1482 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1484 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1490 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1491 struct hclge_pkt_buf_alloc *buf_alloc)
1493 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1496 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
1501 static int hclge_get_tc_num(struct hclge_dev *hdev)
1505 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1506 if (hdev->hw_tc_map & BIT(i))
1511 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1515 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1516 if (hdev->hw_tc_map & BIT(i) &&
1517 hdev->tm_info.hw_pfc_map & BIT(i))
1522 /* Get the number of pfc enabled TCs, which have private buffer */
1523 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1524 struct hclge_pkt_buf_alloc *buf_alloc)
1526 struct hclge_priv_buf *priv;
1529 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1530 priv = &buf_alloc->priv_buf[i];
1531 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1539 /* Get the number of pfc disabled TCs, which have private buffer */
1540 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1541 struct hclge_pkt_buf_alloc *buf_alloc)
1543 struct hclge_priv_buf *priv;
1546 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1547 priv = &buf_alloc->priv_buf[i];
1548 if (hdev->hw_tc_map & BIT(i) &&
1549 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1557 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1559 struct hclge_priv_buf *priv;
1563 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1564 priv = &buf_alloc->priv_buf[i];
1566 rx_priv += priv->buf_size;
1571 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1573 u32 i, total_tx_size = 0;
1575 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1576 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1578 return total_tx_size;
1581 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1582 struct hclge_pkt_buf_alloc *buf_alloc,
1585 u32 shared_buf_min, shared_buf_tc, shared_std;
1586 int tc_num, pfc_enable_num;
1591 tc_num = hclge_get_tc_num(hdev);
1592 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1594 if (hnae3_dev_dcb_supported(hdev))
1595 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1597 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1599 shared_buf_tc = pfc_enable_num * hdev->mps +
1600 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1602 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1604 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
1605 if (rx_all <= rx_priv + shared_std)
1608 shared_buf = rx_all - rx_priv;
1609 buf_alloc->s_buf.buf_size = shared_buf;
1610 buf_alloc->s_buf.self.high = shared_buf;
1611 buf_alloc->s_buf.self.low = 2 * hdev->mps;
1613 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1614 if ((hdev->hw_tc_map & BIT(i)) &&
1615 (hdev->tm_info.hw_pfc_map & BIT(i))) {
1616 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1617 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
1619 buf_alloc->s_buf.tc_thrd[i].low = 0;
1620 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
1627 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1628 struct hclge_pkt_buf_alloc *buf_alloc)
1632 total_size = hdev->pkt_buf_size;
1634 /* alloc tx buffer for all enabled tc */
1635 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1636 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1638 if (total_size < HCLGE_DEFAULT_TX_BUF)
1641 if (hdev->hw_tc_map & BIT(i))
1642 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1644 priv->tx_buf_size = 0;
1646 total_size -= priv->tx_buf_size;
1652 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1653 * @hdev: pointer to struct hclge_dev
1654 * @buf_alloc: pointer to buffer calculation data
1655 * @return: 0: calculate sucessful, negative: fail
1657 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1658 struct hclge_pkt_buf_alloc *buf_alloc)
1660 u32 rx_all = hdev->pkt_buf_size;
1661 int no_pfc_priv_num, pfc_priv_num;
1662 struct hclge_priv_buf *priv;
1665 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
1667 /* When DCB is not supported, rx private
1668 * buffer is not allocated.
1670 if (!hnae3_dev_dcb_supported(hdev)) {
1671 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1677 /* step 1, try to alloc private buffer for all enabled tc */
1678 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1679 priv = &buf_alloc->priv_buf[i];
1680 if (hdev->hw_tc_map & BIT(i)) {
1682 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1683 priv->wl.low = hdev->mps;
1684 priv->wl.high = priv->wl.low + hdev->mps;
1685 priv->buf_size = priv->wl.high +
1689 priv->wl.high = 2 * hdev->mps;
1690 priv->buf_size = priv->wl.high;
1700 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1703 /* step 2, try to decrease the buffer size of
1704 * no pfc TC's private buffer
1706 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1707 priv = &buf_alloc->priv_buf[i];
1714 if (!(hdev->hw_tc_map & BIT(i)))
1719 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1721 priv->wl.high = priv->wl.low + hdev->mps;
1722 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1725 priv->wl.high = hdev->mps;
1726 priv->buf_size = priv->wl.high;
1730 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1733 /* step 3, try to reduce the number of pfc disabled TCs,
1734 * which have private buffer
1736 /* get the total no pfc enable TC number, which have private buffer */
1737 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
1739 /* let the last to be cleared first */
1740 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1741 priv = &buf_alloc->priv_buf[i];
1743 if (hdev->hw_tc_map & BIT(i) &&
1744 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1745 /* Clear the no pfc TC private buffer */
1753 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1754 no_pfc_priv_num == 0)
1758 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1761 /* step 4, try to reduce the number of pfc enabled TCs
1762 * which have private buffer.
1764 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
1766 /* let the last to be cleared first */
1767 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1768 priv = &buf_alloc->priv_buf[i];
1770 if (hdev->hw_tc_map & BIT(i) &&
1771 hdev->tm_info.hw_pfc_map & BIT(i)) {
1772 /* Reduce the number of pfc TC with private buffer */
1780 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1784 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1790 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1791 struct hclge_pkt_buf_alloc *buf_alloc)
1793 struct hclge_rx_priv_buff_cmd *req;
1794 struct hclge_desc desc;
1798 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1799 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
1801 /* Alloc private buffer TCs */
1802 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1803 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1806 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1808 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
1812 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
1813 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1815 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1817 dev_err(&hdev->pdev->dev,
1818 "rx private buffer alloc cmd failed %d\n", ret);
1823 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1824 struct hclge_pkt_buf_alloc *buf_alloc)
1826 struct hclge_rx_priv_wl_buf *req;
1827 struct hclge_priv_buf *priv;
1828 struct hclge_desc desc[2];
1832 for (i = 0; i < 2; i++) {
1833 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1835 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1837 /* The first descriptor set the NEXT bit to 1 */
1839 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1841 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1843 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1844 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1846 priv = &buf_alloc->priv_buf[idx];
1847 req->tc_wl[j].high =
1848 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1849 req->tc_wl[j].high |=
1850 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1852 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1853 req->tc_wl[j].low |=
1854 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1858 /* Send 2 descriptor at one time */
1859 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1861 dev_err(&hdev->pdev->dev,
1862 "rx private waterline config cmd failed %d\n",
1867 static int hclge_common_thrd_config(struct hclge_dev *hdev,
1868 struct hclge_pkt_buf_alloc *buf_alloc)
1870 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
1871 struct hclge_rx_com_thrd *req;
1872 struct hclge_desc desc[2];
1873 struct hclge_tc_thrd *tc;
1877 for (i = 0; i < 2; i++) {
1878 hclge_cmd_setup_basic_desc(&desc[i],
1879 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1880 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1882 /* The first descriptor set the NEXT bit to 1 */
1884 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1886 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1888 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1889 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1891 req->com_thrd[j].high =
1892 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1893 req->com_thrd[j].high |=
1894 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1895 req->com_thrd[j].low =
1896 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1897 req->com_thrd[j].low |=
1898 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1902 /* Send 2 descriptors at one time */
1903 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1905 dev_err(&hdev->pdev->dev,
1906 "common threshold config cmd failed %d\n", ret);
1910 static int hclge_common_wl_config(struct hclge_dev *hdev,
1911 struct hclge_pkt_buf_alloc *buf_alloc)
1913 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
1914 struct hclge_rx_com_wl *req;
1915 struct hclge_desc desc;
1918 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1920 req = (struct hclge_rx_com_wl *)desc.data;
1921 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1922 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1924 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1925 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1927 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1929 dev_err(&hdev->pdev->dev,
1930 "common waterline config cmd failed %d\n", ret);
1935 int hclge_buffer_alloc(struct hclge_dev *hdev)
1937 struct hclge_pkt_buf_alloc *pkt_buf;
1940 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1944 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
1946 dev_err(&hdev->pdev->dev,
1947 "could not calc tx buffer size for all TCs %d\n", ret);
1951 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
1953 dev_err(&hdev->pdev->dev,
1954 "could not alloc tx buffers %d\n", ret);
1958 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
1960 dev_err(&hdev->pdev->dev,
1961 "could not calc rx priv buffer size for all TCs %d\n",
1966 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
1968 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1973 if (hnae3_dev_dcb_supported(hdev)) {
1974 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
1976 dev_err(&hdev->pdev->dev,
1977 "could not configure rx private waterline %d\n",
1982 ret = hclge_common_thrd_config(hdev, pkt_buf);
1984 dev_err(&hdev->pdev->dev,
1985 "could not configure common threshold %d\n",
1991 ret = hclge_common_wl_config(hdev, pkt_buf);
1993 dev_err(&hdev->pdev->dev,
1994 "could not configure common waterline %d\n", ret);
2001 static int hclge_init_roce_base_info(struct hclge_vport *vport)
2003 struct hnae3_handle *roce = &vport->roce;
2004 struct hnae3_handle *nic = &vport->nic;
2006 roce->rinfo.num_vectors = vport->back->num_roce_msi;
2008 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
2009 vport->back->num_msi_left == 0)
2012 roce->rinfo.base_vector = vport->back->roce_base_vector;
2014 roce->rinfo.netdev = nic->kinfo.netdev;
2015 roce->rinfo.roce_io_base = vport->back->hw.io_base;
2017 roce->pdev = nic->pdev;
2018 roce->ae_algo = nic->ae_algo;
2019 roce->numa_node_mask = nic->numa_node_mask;
2024 static int hclge_init_msi(struct hclge_dev *hdev)
2026 struct pci_dev *pdev = hdev->pdev;
2030 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2031 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2034 "failed(%d) to allocate MSI/MSI-X vectors\n",
2038 if (vectors < hdev->num_msi)
2039 dev_warn(&hdev->pdev->dev,
2040 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2041 hdev->num_msi, vectors);
2043 hdev->num_msi = vectors;
2044 hdev->num_msi_left = vectors;
2045 hdev->base_msi_vector = pdev->irq;
2046 hdev->roce_base_vector = hdev->base_msi_vector +
2047 hdev->roce_base_msix_offset;
2049 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2050 sizeof(u16), GFP_KERNEL);
2051 if (!hdev->vector_status) {
2052 pci_free_irq_vectors(pdev);
2056 for (i = 0; i < hdev->num_msi; i++)
2057 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2059 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2060 sizeof(int), GFP_KERNEL);
2061 if (!hdev->vector_irq) {
2062 pci_free_irq_vectors(pdev);
2069 static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2071 struct hclge_mac *mac = &hdev->hw.mac;
2073 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2074 mac->duplex = (u8)duplex;
2076 mac->duplex = HCLGE_MAC_FULL;
2081 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2083 struct hclge_config_mac_speed_dup_cmd *req;
2084 struct hclge_desc desc;
2087 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
2089 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2091 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2094 case HCLGE_MAC_SPEED_10M:
2095 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2096 HCLGE_CFG_SPEED_S, 6);
2098 case HCLGE_MAC_SPEED_100M:
2099 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2100 HCLGE_CFG_SPEED_S, 7);
2102 case HCLGE_MAC_SPEED_1G:
2103 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2104 HCLGE_CFG_SPEED_S, 0);
2106 case HCLGE_MAC_SPEED_10G:
2107 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2108 HCLGE_CFG_SPEED_S, 1);
2110 case HCLGE_MAC_SPEED_25G:
2111 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2112 HCLGE_CFG_SPEED_S, 2);
2114 case HCLGE_MAC_SPEED_40G:
2115 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2116 HCLGE_CFG_SPEED_S, 3);
2118 case HCLGE_MAC_SPEED_50G:
2119 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2120 HCLGE_CFG_SPEED_S, 4);
2122 case HCLGE_MAC_SPEED_100G:
2123 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2124 HCLGE_CFG_SPEED_S, 5);
2127 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
2131 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2134 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2136 dev_err(&hdev->pdev->dev,
2137 "mac speed/duplex config cmd failed %d.\n", ret);
2141 hclge_check_speed_dup(hdev, duplex, speed);
2146 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2149 struct hclge_vport *vport = hclge_get_vport(handle);
2150 struct hclge_dev *hdev = vport->back;
2152 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2155 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2158 struct hclge_query_an_speed_dup_cmd *req;
2159 struct hclge_desc desc;
2163 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
2165 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2166 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2168 dev_err(&hdev->pdev->dev,
2169 "mac speed/autoneg/duplex query cmd failed %d\n",
2174 *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2175 speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2176 HCLGE_QUERY_SPEED_S);
2178 ret = hclge_parse_speed(speed_tmp, speed);
2180 dev_err(&hdev->pdev->dev,
2181 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2186 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2188 struct hclge_config_auto_neg_cmd *req;
2189 struct hclge_desc desc;
2193 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2195 req = (struct hclge_config_auto_neg_cmd *)desc.data;
2196 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2197 req->cfg_an_cmd_flag = cpu_to_le32(flag);
2199 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2201 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2207 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2209 struct hclge_vport *vport = hclge_get_vport(handle);
2210 struct hclge_dev *hdev = vport->back;
2212 return hclge_set_autoneg_en(hdev, enable);
2215 static int hclge_get_autoneg(struct hnae3_handle *handle)
2217 struct hclge_vport *vport = hclge_get_vport(handle);
2218 struct hclge_dev *hdev = vport->back;
2219 struct phy_device *phydev = hdev->hw.mac.phydev;
2222 return phydev->autoneg;
2224 return hdev->hw.mac.autoneg;
2227 static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2231 struct hclge_mac_vlan_mask_entry_cmd *req;
2232 struct hclge_desc desc;
2235 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2236 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2238 hnae3_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2240 ether_addr_copy(req->mac_mask, mac_mask);
2242 status = hclge_cmd_send(&hdev->hw, &desc, 1);
2244 dev_err(&hdev->pdev->dev,
2245 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2251 static int hclge_mac_init(struct hclge_dev *hdev)
2253 struct hnae3_handle *handle = &hdev->vport[0].nic;
2254 struct net_device *netdev = handle->kinfo.netdev;
2255 struct hclge_mac *mac = &hdev->hw.mac;
2256 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2257 struct hclge_vport *vport;
2262 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2264 dev_err(&hdev->pdev->dev,
2265 "Config mac speed dup fail ret=%d\n", ret);
2271 /* Initialize the MTA table work mode */
2272 hdev->enable_mta = true;
2273 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2275 ret = hclge_set_mta_filter_mode(hdev,
2276 hdev->mta_mac_sel_type,
2279 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2284 for (i = 0; i < hdev->num_alloc_vport; i++) {
2285 vport = &hdev->vport[i];
2286 vport->accept_mta_mc = false;
2288 memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow));
2289 ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false);
2291 dev_err(&hdev->pdev->dev,
2292 "set mta filter mode fail ret=%d\n", ret);
2297 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
2299 dev_err(&hdev->pdev->dev,
2300 "set default mac_vlan_mask fail ret=%d\n", ret);
2309 ret = hclge_set_mtu(handle, mtu);
2311 dev_err(&hdev->pdev->dev,
2312 "set mtu failed ret=%d\n", ret);
2317 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2319 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2320 schedule_work(&hdev->mbx_service_task);
2323 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2325 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2326 schedule_work(&hdev->rst_service_task);
2329 static void hclge_task_schedule(struct hclge_dev *hdev)
2331 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2332 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2333 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2334 (void)schedule_work(&hdev->service_task);
2337 static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2339 struct hclge_link_status_cmd *req;
2340 struct hclge_desc desc;
2344 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2345 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2347 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2352 req = (struct hclge_link_status_cmd *)desc.data;
2353 link_status = req->status & HCLGE_LINK_STATUS_UP_M;
2355 return !!link_status;
2358 static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2363 mac_state = hclge_get_mac_link_status(hdev);
2365 if (hdev->hw.mac.phydev) {
2366 if (!genphy_read_status(hdev->hw.mac.phydev))
2367 link_stat = mac_state &
2368 hdev->hw.mac.phydev->link;
2373 link_stat = mac_state;
2379 static void hclge_update_link_status(struct hclge_dev *hdev)
2381 struct hnae3_client *client = hdev->nic_client;
2382 struct hnae3_handle *handle;
2388 state = hclge_get_mac_phy_link(hdev);
2389 if (state != hdev->hw.mac.link) {
2390 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2391 handle = &hdev->vport[i].nic;
2392 client->ops->link_status_change(handle, state);
2394 hdev->hw.mac.link = state;
2398 static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2400 struct hclge_mac mac = hdev->hw.mac;
2405 /* get the speed and duplex as autoneg'result from mac cmd when phy
2408 if (mac.phydev || !mac.autoneg)
2411 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2413 dev_err(&hdev->pdev->dev,
2414 "mac autoneg/speed/duplex query failed %d\n", ret);
2418 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2419 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2421 dev_err(&hdev->pdev->dev,
2422 "mac speed/duplex config failed %d\n", ret);
2430 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2432 struct hclge_vport *vport = hclge_get_vport(handle);
2433 struct hclge_dev *hdev = vport->back;
2435 return hclge_update_speed_duplex(hdev);
2438 static int hclge_get_status(struct hnae3_handle *handle)
2440 struct hclge_vport *vport = hclge_get_vport(handle);
2441 struct hclge_dev *hdev = vport->back;
2443 hclge_update_link_status(hdev);
2445 return hdev->hw.mac.link;
2448 static void hclge_service_timer(struct timer_list *t)
2450 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
2452 mod_timer(&hdev->service_timer, jiffies + HZ);
2453 hdev->hw_stats.stats_timer++;
2454 hclge_task_schedule(hdev);
2457 static void hclge_service_complete(struct hclge_dev *hdev)
2459 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2461 /* Flush memory before next watchdog */
2462 smp_mb__before_atomic();
2463 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2466 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2471 /* fetch the events from their corresponding regs */
2472 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
2473 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2475 /* Assumption: If by any chance reset and mailbox events are reported
2476 * together then we will only process reset event in this go and will
2477 * defer the processing of the mailbox events. Since, we would have not
2478 * cleared RX CMDQ event this time we would receive again another
2479 * interrupt from H/W just for the mailbox.
2482 /* check for vector0 reset event sources */
2483 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2484 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2485 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2486 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2487 return HCLGE_VECTOR0_EVENT_RST;
2490 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2491 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2492 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2493 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2494 return HCLGE_VECTOR0_EVENT_RST;
2497 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2498 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2499 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2500 return HCLGE_VECTOR0_EVENT_RST;
2503 /* check for vector0 mailbox(=CMDQ RX) event source */
2504 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2505 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2506 *clearval = cmdq_src_reg;
2507 return HCLGE_VECTOR0_EVENT_MBX;
2510 return HCLGE_VECTOR0_EVENT_OTHER;
2513 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2516 switch (event_type) {
2517 case HCLGE_VECTOR0_EVENT_RST:
2518 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2520 case HCLGE_VECTOR0_EVENT_MBX:
2521 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2526 static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2528 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2529 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2530 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2531 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2532 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2535 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2537 writel(enable ? 1 : 0, vector->addr);
2540 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2542 struct hclge_dev *hdev = data;
2546 hclge_enable_vector(&hdev->misc_vector, false);
2547 event_cause = hclge_check_event_cause(hdev, &clearval);
2549 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2550 switch (event_cause) {
2551 case HCLGE_VECTOR0_EVENT_RST:
2552 hclge_reset_task_schedule(hdev);
2554 case HCLGE_VECTOR0_EVENT_MBX:
2555 /* If we are here then,
2556 * 1. Either we are not handling any mbx task and we are not
2559 * 2. We could be handling a mbx task but nothing more is
2561 * In both cases, we should schedule mbx task as there are more
2562 * mbx messages reported by this interrupt.
2564 hclge_mbx_task_schedule(hdev);
2567 dev_warn(&hdev->pdev->dev,
2568 "received unknown or unhandled event of vector0\n");
2572 /* clear the source of interrupt if it is not cause by reset */
2573 if (event_cause != HCLGE_VECTOR0_EVENT_RST) {
2574 hclge_clear_event_cause(hdev, event_cause, clearval);
2575 hclge_enable_vector(&hdev->misc_vector, true);
2581 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2583 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2584 dev_warn(&hdev->pdev->dev,
2585 "vector(vector_id %d) has been freed.\n", vector_id);
2589 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2590 hdev->num_msi_left += 1;
2591 hdev->num_msi_used -= 1;
2594 static void hclge_get_misc_vector(struct hclge_dev *hdev)
2596 struct hclge_misc_vector *vector = &hdev->misc_vector;
2598 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2600 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2601 hdev->vector_status[0] = 0;
2603 hdev->num_msi_left -= 1;
2604 hdev->num_msi_used += 1;
2607 static int hclge_misc_irq_init(struct hclge_dev *hdev)
2611 hclge_get_misc_vector(hdev);
2613 /* this would be explicitly freed in the end */
2614 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2615 0, "hclge_misc", hdev);
2617 hclge_free_vector(hdev, 0);
2618 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2619 hdev->misc_vector.vector_irq);
2625 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2627 free_irq(hdev->misc_vector.vector_irq, hdev);
2628 hclge_free_vector(hdev, 0);
2631 static int hclge_notify_client(struct hclge_dev *hdev,
2632 enum hnae3_reset_notify_type type)
2634 struct hnae3_client *client = hdev->nic_client;
2637 if (!client->ops->reset_notify)
2640 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2641 struct hnae3_handle *handle = &hdev->vport[i].nic;
2644 ret = client->ops->reset_notify(handle, type);
2652 static int hclge_reset_wait(struct hclge_dev *hdev)
2654 #define HCLGE_RESET_WATI_MS 100
2655 #define HCLGE_RESET_WAIT_CNT 5
2656 u32 val, reg, reg_bit;
2659 switch (hdev->reset_type) {
2660 case HNAE3_GLOBAL_RESET:
2661 reg = HCLGE_GLOBAL_RESET_REG;
2662 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2664 case HNAE3_CORE_RESET:
2665 reg = HCLGE_GLOBAL_RESET_REG;
2666 reg_bit = HCLGE_CORE_RESET_BIT;
2668 case HNAE3_FUNC_RESET:
2669 reg = HCLGE_FUN_RST_ING;
2670 reg_bit = HCLGE_FUN_RST_ING_B;
2673 dev_err(&hdev->pdev->dev,
2674 "Wait for unsupported reset type: %d\n",
2679 val = hclge_read_dev(&hdev->hw, reg);
2680 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2681 msleep(HCLGE_RESET_WATI_MS);
2682 val = hclge_read_dev(&hdev->hw, reg);
2686 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2687 dev_warn(&hdev->pdev->dev,
2688 "Wait for reset timeout: %d\n", hdev->reset_type);
2695 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2697 struct hclge_desc desc;
2698 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2701 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2702 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2703 req->fun_reset_vfid = func_id;
2705 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2707 dev_err(&hdev->pdev->dev,
2708 "send function reset cmd fail, status =%d\n", ret);
2713 static void hclge_do_reset(struct hclge_dev *hdev)
2715 struct pci_dev *pdev = hdev->pdev;
2718 switch (hdev->reset_type) {
2719 case HNAE3_GLOBAL_RESET:
2720 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2721 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2722 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2723 dev_info(&pdev->dev, "Global Reset requested\n");
2725 case HNAE3_CORE_RESET:
2726 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2727 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2728 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2729 dev_info(&pdev->dev, "Core Reset requested\n");
2731 case HNAE3_FUNC_RESET:
2732 dev_info(&pdev->dev, "PF Reset requested\n");
2733 hclge_func_reset_cmd(hdev, 0);
2734 /* schedule again to check later */
2735 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2736 hclge_reset_task_schedule(hdev);
2739 dev_warn(&pdev->dev,
2740 "Unsupported reset type: %d\n", hdev->reset_type);
2745 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2746 unsigned long *addr)
2748 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2750 /* return the highest priority reset level amongst all */
2751 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2752 rst_level = HNAE3_GLOBAL_RESET;
2753 else if (test_bit(HNAE3_CORE_RESET, addr))
2754 rst_level = HNAE3_CORE_RESET;
2755 else if (test_bit(HNAE3_IMP_RESET, addr))
2756 rst_level = HNAE3_IMP_RESET;
2757 else if (test_bit(HNAE3_FUNC_RESET, addr))
2758 rst_level = HNAE3_FUNC_RESET;
2760 /* now, clear all other resets */
2761 clear_bit(HNAE3_GLOBAL_RESET, addr);
2762 clear_bit(HNAE3_CORE_RESET, addr);
2763 clear_bit(HNAE3_IMP_RESET, addr);
2764 clear_bit(HNAE3_FUNC_RESET, addr);
2769 static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2773 switch (hdev->reset_type) {
2774 case HNAE3_IMP_RESET:
2775 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2777 case HNAE3_GLOBAL_RESET:
2778 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2780 case HNAE3_CORE_RESET:
2781 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2790 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2791 hclge_enable_vector(&hdev->misc_vector, true);
2794 static void hclge_reset(struct hclge_dev *hdev)
2796 struct hnae3_handle *handle;
2798 /* perform reset of the stack & ae device for a client */
2799 handle = &hdev->vport[0].nic;
2801 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2803 if (!hclge_reset_wait(hdev)) {
2804 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2805 hclge_reset_ae_dev(hdev->ae_dev);
2806 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2808 hclge_clear_reset_cause(hdev);
2810 /* schedule again to check pending resets later */
2811 set_bit(hdev->reset_type, &hdev->reset_pending);
2812 hclge_reset_task_schedule(hdev);
2815 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2816 handle->last_reset_time = jiffies;
2820 static void hclge_reset_event(struct hnae3_handle *handle)
2822 struct hclge_vport *vport = hclge_get_vport(handle);
2823 struct hclge_dev *hdev = vport->back;
2825 /* check if this is a new reset request and we are not here just because
2826 * last reset attempt did not succeed and watchdog hit us again. We will
2827 * know this if last reset request did not occur very recently (watchdog
2828 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2829 * In case of new request we reset the "reset level" to PF reset.
2830 * And if it is a repeat reset request of the most recent one then we
2831 * want to make sure we throttle the reset request. Therefore, we will
2832 * not allow it again before 3*HZ times.
2834 if (time_before(jiffies, (handle->last_reset_time + 3 * HZ)))
2836 else if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
2837 handle->reset_level = HNAE3_FUNC_RESET;
2839 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2840 handle->reset_level);
2842 /* request reset & schedule reset task */
2843 set_bit(handle->reset_level, &hdev->reset_request);
2844 hclge_reset_task_schedule(hdev);
2846 if (handle->reset_level < HNAE3_GLOBAL_RESET)
2847 handle->reset_level++;
2850 static void hclge_reset_subtask(struct hclge_dev *hdev)
2852 /* check if there is any ongoing reset in the hardware. This status can
2853 * be checked from reset_pending. If there is then, we need to wait for
2854 * hardware to complete reset.
2855 * a. If we are able to figure out in reasonable time that hardware
2856 * has fully resetted then, we can proceed with driver, client
2858 * b. else, we can come back later to check this status so re-sched
2861 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2862 if (hdev->reset_type != HNAE3_NONE_RESET)
2865 /* check if we got any *new* reset requests to be honored */
2866 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2867 if (hdev->reset_type != HNAE3_NONE_RESET)
2868 hclge_do_reset(hdev);
2870 hdev->reset_type = HNAE3_NONE_RESET;
2873 static void hclge_reset_service_task(struct work_struct *work)
2875 struct hclge_dev *hdev =
2876 container_of(work, struct hclge_dev, rst_service_task);
2878 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2881 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2883 hclge_reset_subtask(hdev);
2885 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
2888 static void hclge_mailbox_service_task(struct work_struct *work)
2890 struct hclge_dev *hdev =
2891 container_of(work, struct hclge_dev, mbx_service_task);
2893 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2896 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2898 hclge_mbx_handler(hdev);
2900 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2903 static void hclge_service_task(struct work_struct *work)
2905 struct hclge_dev *hdev =
2906 container_of(work, struct hclge_dev, service_task);
2908 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2909 hclge_update_stats_for_all(hdev);
2910 hdev->hw_stats.stats_timer = 0;
2913 hclge_update_speed_duplex(hdev);
2914 hclge_update_link_status(hdev);
2915 hclge_service_complete(hdev);
2918 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2920 /* VF handle has no client */
2921 if (!handle->client)
2922 return container_of(handle, struct hclge_vport, nic);
2923 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2924 return container_of(handle, struct hclge_vport, roce);
2926 return container_of(handle, struct hclge_vport, nic);
2929 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2930 struct hnae3_vector_info *vector_info)
2932 struct hclge_vport *vport = hclge_get_vport(handle);
2933 struct hnae3_vector_info *vector = vector_info;
2934 struct hclge_dev *hdev = vport->back;
2938 vector_num = min(hdev->num_msi_left, vector_num);
2940 for (j = 0; j < vector_num; j++) {
2941 for (i = 1; i < hdev->num_msi; i++) {
2942 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2943 vector->vector = pci_irq_vector(hdev->pdev, i);
2944 vector->io_addr = hdev->hw.io_base +
2945 HCLGE_VECTOR_REG_BASE +
2946 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2948 HCLGE_VECTOR_VF_OFFSET;
2949 hdev->vector_status[i] = vport->vport_id;
2950 hdev->vector_irq[i] = vector->vector;
2959 hdev->num_msi_left -= alloc;
2960 hdev->num_msi_used += alloc;
2965 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2969 for (i = 0; i < hdev->num_msi; i++)
2970 if (vector == hdev->vector_irq[i])
2976 static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2978 struct hclge_vport *vport = hclge_get_vport(handle);
2979 struct hclge_dev *hdev = vport->back;
2982 vector_id = hclge_get_vector_index(hdev, vector);
2983 if (vector_id < 0) {
2984 dev_err(&hdev->pdev->dev,
2985 "Get vector index fail. vector_id =%d\n", vector_id);
2989 hclge_free_vector(hdev, vector_id);
2994 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2996 return HCLGE_RSS_KEY_SIZE;
2999 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
3001 return HCLGE_RSS_IND_TBL_SIZE;
3004 static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
3005 const u8 hfunc, const u8 *key)
3007 struct hclge_rss_config_cmd *req;
3008 struct hclge_desc desc;
3013 req = (struct hclge_rss_config_cmd *)desc.data;
3015 for (key_offset = 0; key_offset < 3; key_offset++) {
3016 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
3019 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3020 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3022 if (key_offset == 2)
3024 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3026 key_size = HCLGE_RSS_HASH_KEY_NUM;
3028 memcpy(req->hash_key,
3029 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3031 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3033 dev_err(&hdev->pdev->dev,
3034 "Configure RSS config fail, status = %d\n",
3042 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
3044 struct hclge_rss_indirection_table_cmd *req;
3045 struct hclge_desc desc;
3049 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
3051 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3052 hclge_cmd_setup_basic_desc
3053 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3055 req->start_table_index =
3056 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3057 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
3059 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3060 req->rss_result[j] =
3061 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3063 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3065 dev_err(&hdev->pdev->dev,
3066 "Configure rss indir table fail,status = %d\n",
3074 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3075 u16 *tc_size, u16 *tc_offset)
3077 struct hclge_rss_tc_mode_cmd *req;
3078 struct hclge_desc desc;
3082 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
3083 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
3085 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3088 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3089 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3090 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3091 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3092 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
3094 req->rss_tc_mode[i] = cpu_to_le16(mode);
3097 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3099 dev_err(&hdev->pdev->dev,
3100 "Configure rss tc mode fail, status = %d\n", ret);
3105 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3107 struct hclge_rss_input_tuple_cmd *req;
3108 struct hclge_desc desc;
3111 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3113 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3115 /* Get the tuple cfg from pf */
3116 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3117 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3118 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3119 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3120 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3121 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3122 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3123 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
3124 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3126 dev_err(&hdev->pdev->dev,
3127 "Configure rss input fail, status = %d\n", ret);
3131 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3134 struct hclge_vport *vport = hclge_get_vport(handle);
3137 /* Get hash algorithm */
3139 *hfunc = vport->rss_algo;
3141 /* Get the RSS Key required by the user */
3143 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3145 /* Get indirect table */
3147 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3148 indir[i] = vport->rss_indirection_tbl[i];
3153 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3154 const u8 *key, const u8 hfunc)
3156 struct hclge_vport *vport = hclge_get_vport(handle);
3157 struct hclge_dev *hdev = vport->back;
3161 /* Set the RSS Hash Key if specififed by the user */
3164 if (hfunc == ETH_RSS_HASH_TOP ||
3165 hfunc == ETH_RSS_HASH_NO_CHANGE)
3166 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3169 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3173 /* Update the shadow RSS key with user specified qids */
3174 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3175 vport->rss_algo = hash_algo;
3178 /* Update the shadow RSS table with user specified qids */
3179 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3180 vport->rss_indirection_tbl[i] = indir[i];
3182 /* Update the hardware */
3183 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
3186 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3188 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3190 if (nfc->data & RXH_L4_B_2_3)
3191 hash_sets |= HCLGE_D_PORT_BIT;
3193 hash_sets &= ~HCLGE_D_PORT_BIT;
3195 if (nfc->data & RXH_IP_SRC)
3196 hash_sets |= HCLGE_S_IP_BIT;
3198 hash_sets &= ~HCLGE_S_IP_BIT;
3200 if (nfc->data & RXH_IP_DST)
3201 hash_sets |= HCLGE_D_IP_BIT;
3203 hash_sets &= ~HCLGE_D_IP_BIT;
3205 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3206 hash_sets |= HCLGE_V_TAG_BIT;
3211 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3212 struct ethtool_rxnfc *nfc)
3214 struct hclge_vport *vport = hclge_get_vport(handle);
3215 struct hclge_dev *hdev = vport->back;
3216 struct hclge_rss_input_tuple_cmd *req;
3217 struct hclge_desc desc;
3221 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3222 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3225 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3226 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3228 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3229 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3230 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3231 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3232 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3233 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3234 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3235 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
3237 tuple_sets = hclge_get_rss_hash_bits(nfc);
3238 switch (nfc->flow_type) {
3240 req->ipv4_tcp_en = tuple_sets;
3243 req->ipv6_tcp_en = tuple_sets;
3246 req->ipv4_udp_en = tuple_sets;
3249 req->ipv6_udp_en = tuple_sets;
3252 req->ipv4_sctp_en = tuple_sets;
3255 if ((nfc->data & RXH_L4_B_0_1) ||
3256 (nfc->data & RXH_L4_B_2_3))
3259 req->ipv6_sctp_en = tuple_sets;
3262 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3265 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3271 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3273 dev_err(&hdev->pdev->dev,
3274 "Set rss tuple fail, status = %d\n", ret);
3278 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3279 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3280 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3281 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3282 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3283 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3284 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3285 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3289 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3290 struct ethtool_rxnfc *nfc)
3292 struct hclge_vport *vport = hclge_get_vport(handle);
3297 switch (nfc->flow_type) {
3299 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
3302 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
3305 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
3308 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
3311 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
3314 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
3318 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3327 if (tuple_sets & HCLGE_D_PORT_BIT)
3328 nfc->data |= RXH_L4_B_2_3;
3329 if (tuple_sets & HCLGE_S_PORT_BIT)
3330 nfc->data |= RXH_L4_B_0_1;
3331 if (tuple_sets & HCLGE_D_IP_BIT)
3332 nfc->data |= RXH_IP_DST;
3333 if (tuple_sets & HCLGE_S_IP_BIT)
3334 nfc->data |= RXH_IP_SRC;
3339 static int hclge_get_tc_size(struct hnae3_handle *handle)
3341 struct hclge_vport *vport = hclge_get_vport(handle);
3342 struct hclge_dev *hdev = vport->back;
3344 return hdev->rss_size_max;
3347 int hclge_rss_init_hw(struct hclge_dev *hdev)
3349 struct hclge_vport *vport = hdev->vport;
3350 u8 *rss_indir = vport[0].rss_indirection_tbl;
3351 u16 rss_size = vport[0].alloc_rss_size;
3352 u8 *key = vport[0].rss_hash_key;
3353 u8 hfunc = vport[0].rss_algo;
3354 u16 tc_offset[HCLGE_MAX_TC_NUM];
3355 u16 tc_valid[HCLGE_MAX_TC_NUM];
3356 u16 tc_size[HCLGE_MAX_TC_NUM];
3360 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3364 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3368 ret = hclge_set_rss_input_tuple(hdev);
3372 /* Each TC have the same queue size, and tc_size set to hardware is
3373 * the log2 of roundup power of two of rss_size, the acutal queue
3374 * size is limited by indirection table.
3376 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3377 dev_err(&hdev->pdev->dev,
3378 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3383 roundup_size = roundup_pow_of_two(rss_size);
3384 roundup_size = ilog2(roundup_size);
3386 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3389 if (!(hdev->hw_tc_map & BIT(i)))
3393 tc_size[i] = roundup_size;
3394 tc_offset[i] = rss_size * i;
3397 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3400 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3402 struct hclge_vport *vport = hdev->vport;
3405 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3406 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3407 vport[j].rss_indirection_tbl[i] =
3408 i % vport[j].alloc_rss_size;
3412 static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3414 struct hclge_vport *vport = hdev->vport;
3417 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3418 vport[i].rss_tuple_sets.ipv4_tcp_en =
3419 HCLGE_RSS_INPUT_TUPLE_OTHER;
3420 vport[i].rss_tuple_sets.ipv4_udp_en =
3421 HCLGE_RSS_INPUT_TUPLE_OTHER;
3422 vport[i].rss_tuple_sets.ipv4_sctp_en =
3423 HCLGE_RSS_INPUT_TUPLE_SCTP;
3424 vport[i].rss_tuple_sets.ipv4_fragment_en =
3425 HCLGE_RSS_INPUT_TUPLE_OTHER;
3426 vport[i].rss_tuple_sets.ipv6_tcp_en =
3427 HCLGE_RSS_INPUT_TUPLE_OTHER;
3428 vport[i].rss_tuple_sets.ipv6_udp_en =
3429 HCLGE_RSS_INPUT_TUPLE_OTHER;
3430 vport[i].rss_tuple_sets.ipv6_sctp_en =
3431 HCLGE_RSS_INPUT_TUPLE_SCTP;
3432 vport[i].rss_tuple_sets.ipv6_fragment_en =
3433 HCLGE_RSS_INPUT_TUPLE_OTHER;
3435 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3437 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
3440 hclge_rss_indir_init_cfg(hdev);
3443 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3444 int vector_id, bool en,
3445 struct hnae3_ring_chain_node *ring_chain)
3447 struct hclge_dev *hdev = vport->back;
3448 struct hnae3_ring_chain_node *node;
3449 struct hclge_desc desc;
3450 struct hclge_ctrl_vector_chain_cmd *req
3451 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3452 enum hclge_cmd_status status;
3453 enum hclge_opcode_type op;
3454 u16 tqp_type_and_id;
3457 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3458 hclge_cmd_setup_basic_desc(&desc, op, false);
3459 req->int_vector_id = vector_id;
3462 for (node = ring_chain; node; node = node->next) {
3463 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3464 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3466 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3467 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3468 HCLGE_TQP_ID_S, node->tqp_index);
3469 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3471 hnae3_get_field(node->int_gl_idx,
3472 HNAE3_RING_GL_IDX_M,
3473 HNAE3_RING_GL_IDX_S));
3474 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
3475 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3476 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3477 req->vfid = vport->vport_id;
3479 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3481 dev_err(&hdev->pdev->dev,
3482 "Map TQP fail, status is %d.\n",
3488 hclge_cmd_setup_basic_desc(&desc,
3491 req->int_vector_id = vector_id;
3496 req->int_cause_num = i;
3497 req->vfid = vport->vport_id;
3498 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3500 dev_err(&hdev->pdev->dev,
3501 "Map TQP fail, status is %d.\n", status);
3509 static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3511 struct hnae3_ring_chain_node *ring_chain)
3513 struct hclge_vport *vport = hclge_get_vport(handle);
3514 struct hclge_dev *hdev = vport->back;
3517 vector_id = hclge_get_vector_index(hdev, vector);
3518 if (vector_id < 0) {
3519 dev_err(&hdev->pdev->dev,
3520 "Get vector index fail. vector_id =%d\n", vector_id);
3524 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
3527 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3529 struct hnae3_ring_chain_node *ring_chain)
3531 struct hclge_vport *vport = hclge_get_vport(handle);
3532 struct hclge_dev *hdev = vport->back;
3535 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3538 vector_id = hclge_get_vector_index(hdev, vector);
3539 if (vector_id < 0) {
3540 dev_err(&handle->pdev->dev,
3541 "Get vector index fail. ret =%d\n", vector_id);
3545 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
3547 dev_err(&handle->pdev->dev,
3548 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3555 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3556 struct hclge_promisc_param *param)
3558 struct hclge_promisc_cfg_cmd *req;
3559 struct hclge_desc desc;
3562 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3564 req = (struct hclge_promisc_cfg_cmd *)desc.data;
3565 req->vf_id = param->vf_id;
3567 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3568 * pdev revision(0x20), new revision support them. The
3569 * value of this two fields will not return error when driver
3570 * send command to fireware in revision(0x20).
3572 req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3573 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
3575 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3577 dev_err(&hdev->pdev->dev,
3578 "Set promisc mode fail, status is %d.\n", ret);
3583 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3584 bool en_mc, bool en_bc, int vport_id)
3589 memset(param, 0, sizeof(struct hclge_promisc_param));
3591 param->enable = HCLGE_PROMISC_EN_UC;
3593 param->enable |= HCLGE_PROMISC_EN_MC;
3595 param->enable |= HCLGE_PROMISC_EN_BC;
3596 param->vf_id = vport_id;
3599 static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3602 struct hclge_vport *vport = hclge_get_vport(handle);
3603 struct hclge_dev *hdev = vport->back;
3604 struct hclge_promisc_param param;
3606 hclge_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, true,
3608 hclge_cmd_set_promisc_mode(hdev, ¶m);
3611 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3613 struct hclge_desc desc;
3614 struct hclge_config_mac_mode_cmd *req =
3615 (struct hclge_config_mac_mode_cmd *)desc.data;
3619 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
3620 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3621 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3622 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3623 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3624 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3625 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3626 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3627 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3628 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3629 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3630 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3631 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3632 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3633 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3634 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3636 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3638 dev_err(&hdev->pdev->dev,
3639 "mac enable fail, ret =%d.\n", ret);
3642 static int hclge_set_mac_loopback(struct hclge_dev *hdev, bool en)
3644 struct hclge_config_mac_mode_cmd *req;
3645 struct hclge_desc desc;
3649 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3650 /* 1 Read out the MAC mode config at first */
3651 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
3652 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3654 dev_err(&hdev->pdev->dev,
3655 "mac loopback get fail, ret =%d.\n", ret);
3659 /* 2 Then setup the loopback flag */
3660 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3661 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
3663 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3665 /* 3 Config mac work mode with loopback flag
3666 * and its original configure parameters
3668 hclge_cmd_reuse_desc(&desc, false);
3669 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3671 dev_err(&hdev->pdev->dev,
3672 "mac loopback set fail, ret =%d.\n", ret);
3676 static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en)
3678 #define HCLGE_SERDES_RETRY_MS 10
3679 #define HCLGE_SERDES_RETRY_NUM 100
3680 struct hclge_serdes_lb_cmd *req;
3681 struct hclge_desc desc;
3684 req = (struct hclge_serdes_lb_cmd *)&desc.data[0];
3685 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
3688 req->enable = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3689 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3691 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3694 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3696 dev_err(&hdev->pdev->dev,
3697 "serdes loopback set fail, ret = %d\n", ret);
3702 msleep(HCLGE_SERDES_RETRY_MS);
3703 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
3705 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3707 dev_err(&hdev->pdev->dev,
3708 "serdes loopback get, ret = %d\n", ret);
3711 } while (++i < HCLGE_SERDES_RETRY_NUM &&
3712 !(req->result & HCLGE_CMD_SERDES_DONE_B));
3714 if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
3715 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
3717 } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
3718 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
3725 static int hclge_set_loopback(struct hnae3_handle *handle,
3726 enum hnae3_loop loop_mode, bool en)
3728 struct hclge_vport *vport = hclge_get_vport(handle);
3729 struct hclge_dev *hdev = vport->back;
3732 switch (loop_mode) {
3733 case HNAE3_MAC_INTER_LOOP_MAC:
3734 ret = hclge_set_mac_loopback(hdev, en);
3736 case HNAE3_MAC_INTER_LOOP_SERDES:
3737 ret = hclge_set_serdes_loopback(hdev, en);
3741 dev_err(&hdev->pdev->dev,
3742 "loop_mode %d is not supported\n", loop_mode);
3749 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3750 int stream_id, bool enable)
3752 struct hclge_desc desc;
3753 struct hclge_cfg_com_tqp_queue_cmd *req =
3754 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
3757 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3758 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3759 req->stream_id = cpu_to_le16(stream_id);
3760 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3762 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3764 dev_err(&hdev->pdev->dev,
3765 "Tqp enable fail, status =%d.\n", ret);
3769 static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3771 struct hclge_vport *vport = hclge_get_vport(handle);
3772 struct hnae3_queue *queue;
3773 struct hclge_tqp *tqp;
3776 for (i = 0; i < vport->alloc_tqps; i++) {
3777 queue = handle->kinfo.tqp[i];
3778 tqp = container_of(queue, struct hclge_tqp, q);
3779 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3783 static int hclge_ae_start(struct hnae3_handle *handle)
3785 struct hclge_vport *vport = hclge_get_vport(handle);
3786 struct hclge_dev *hdev = vport->back;
3789 for (i = 0; i < vport->alloc_tqps; i++)
3790 hclge_tqp_enable(hdev, i, 0, true);
3793 hclge_cfg_mac_mode(hdev, true);
3794 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
3795 mod_timer(&hdev->service_timer, jiffies + HZ);
3796 hdev->hw.mac.link = 0;
3798 /* reset tqp stats */
3799 hclge_reset_tqp_stats(handle);
3801 hclge_mac_start_phy(hdev);
3806 static void hclge_ae_stop(struct hnae3_handle *handle)
3808 struct hclge_vport *vport = hclge_get_vport(handle);
3809 struct hclge_dev *hdev = vport->back;
3812 del_timer_sync(&hdev->service_timer);
3813 cancel_work_sync(&hdev->service_task);
3814 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
3816 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
3817 hclge_mac_stop_phy(hdev);
3821 for (i = 0; i < vport->alloc_tqps; i++)
3822 hclge_tqp_enable(hdev, i, 0, false);
3825 hclge_cfg_mac_mode(hdev, false);
3827 hclge_mac_stop_phy(hdev);
3829 /* reset tqp stats */
3830 hclge_reset_tqp_stats(handle);
3831 del_timer_sync(&hdev->service_timer);
3832 cancel_work_sync(&hdev->service_task);
3833 hclge_update_link_status(hdev);
3836 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3837 u16 cmdq_resp, u8 resp_code,
3838 enum hclge_mac_vlan_tbl_opcode op)
3840 struct hclge_dev *hdev = vport->back;
3841 int return_status = -EIO;
3844 dev_err(&hdev->pdev->dev,
3845 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3850 if (op == HCLGE_MAC_VLAN_ADD) {
3851 if ((!resp_code) || (resp_code == 1)) {
3853 } else if (resp_code == 2) {
3854 return_status = -ENOSPC;
3855 dev_err(&hdev->pdev->dev,
3856 "add mac addr failed for uc_overflow.\n");
3857 } else if (resp_code == 3) {
3858 return_status = -ENOSPC;
3859 dev_err(&hdev->pdev->dev,
3860 "add mac addr failed for mc_overflow.\n");
3862 dev_err(&hdev->pdev->dev,
3863 "add mac addr failed for undefined, code=%d.\n",
3866 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3869 } else if (resp_code == 1) {
3870 return_status = -ENOENT;
3871 dev_dbg(&hdev->pdev->dev,
3872 "remove mac addr failed for miss.\n");
3874 dev_err(&hdev->pdev->dev,
3875 "remove mac addr failed for undefined, code=%d.\n",
3878 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3881 } else if (resp_code == 1) {
3882 return_status = -ENOENT;
3883 dev_dbg(&hdev->pdev->dev,
3884 "lookup mac addr failed for miss.\n");
3886 dev_err(&hdev->pdev->dev,
3887 "lookup mac addr failed for undefined, code=%d.\n",
3891 return_status = -EINVAL;
3892 dev_err(&hdev->pdev->dev,
3893 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3897 return return_status;
3900 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3905 if (vfid > 255 || vfid < 0)
3908 if (vfid >= 0 && vfid <= 191) {
3909 word_num = vfid / 32;
3910 bit_num = vfid % 32;
3912 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3914 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
3916 word_num = (vfid - 192) / 32;
3917 bit_num = vfid % 32;
3919 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3921 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
3927 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3929 #define HCLGE_DESC_NUMBER 3
3930 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3933 for (i = 1; i < HCLGE_DESC_NUMBER; i++)
3934 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3935 if (desc[i].data[j])
3941 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
3944 const unsigned char *mac_addr = addr;
3945 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3946 (mac_addr[0]) | (mac_addr[1] << 8);
3947 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3949 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3950 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3953 static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3956 u16 high_val = addr[1] | (addr[0] << 8);
3957 struct hclge_dev *hdev = vport->back;
3958 u32 rsh = 4 - hdev->mta_mac_sel_type;
3959 u16 ret_val = (high_val >> rsh) & 0xfff;
3964 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3965 enum hclge_mta_dmac_sel_type mta_mac_sel,
3968 struct hclge_mta_filter_mode_cmd *req;
3969 struct hclge_desc desc;
3972 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
3973 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3975 hnae3_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3977 hnae3_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3978 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3980 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3982 dev_err(&hdev->pdev->dev,
3983 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3989 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3993 struct hclge_cfg_func_mta_filter_cmd *req;
3994 struct hclge_desc desc;
3997 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
3998 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
4000 hnae3_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
4002 req->function_id = func_id;
4004 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4006 dev_err(&hdev->pdev->dev,
4007 "Config func_id enable failed for cmd_send, ret =%d.\n",
4013 static int hclge_set_mta_table_item(struct hclge_vport *vport,
4017 struct hclge_dev *hdev = vport->back;
4018 struct hclge_cfg_func_mta_item_cmd *req;
4019 struct hclge_desc desc;
4023 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
4024 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
4025 hnae3_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
4027 hnae3_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
4028 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
4029 req->item_idx = cpu_to_le16(item_idx);
4031 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4033 dev_err(&hdev->pdev->dev,
4034 "Config mta table item failed for cmd_send, ret =%d.\n",
4040 set_bit(idx, vport->mta_shadow);
4042 clear_bit(idx, vport->mta_shadow);
4047 static int hclge_update_mta_status(struct hnae3_handle *handle)
4049 unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)];
4050 struct hclge_vport *vport = hclge_get_vport(handle);
4051 struct net_device *netdev = handle->kinfo.netdev;
4052 struct netdev_hw_addr *ha;
4055 memset(mta_status, 0, sizeof(mta_status));
4057 /* update mta_status from mc addr list */
4058 netdev_for_each_mc_addr(ha, netdev) {
4059 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr);
4060 set_bit(tbl_idx, mta_status);
4063 return hclge_update_mta_status_common(vport, mta_status,
4064 0, HCLGE_MTA_TBL_SIZE, true);
4067 int hclge_update_mta_status_common(struct hclge_vport *vport,
4068 unsigned long *status,
4073 struct hclge_dev *hdev = vport->back;
4074 u16 update_max = idx + count;
4080 /* setup mta check range */
4081 if (update_filter) {
4083 check_max = HCLGE_MTA_TBL_SIZE;
4086 check_max = update_max;
4090 /* check and update all mta item */
4091 for (; i < check_max; i++) {
4092 /* ignore unused item */
4093 if (!test_bit(i, vport->mta_shadow))
4096 /* if i in update range then update it */
4097 if (i >= idx && i < update_max)
4098 if (!test_bit(i - idx, status))
4099 hclge_set_mta_table_item(vport, i, false);
4101 if (!used && test_bit(i, vport->mta_shadow))
4105 /* no longer use mta, disable it */
4106 if (vport->accept_mta_mc && update_filter && !used) {
4107 ret = hclge_cfg_func_mta_filter(hdev,
4111 dev_err(&hdev->pdev->dev,
4112 "disable func mta filter fail ret=%d\n",
4115 vport->accept_mta_mc = false;
4121 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
4122 struct hclge_mac_vlan_tbl_entry_cmd *req)
4124 struct hclge_dev *hdev = vport->back;
4125 struct hclge_desc desc;
4130 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
4132 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4134 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4136 dev_err(&hdev->pdev->dev,
4137 "del mac addr failed for cmd_send, ret =%d.\n",
4141 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4142 retval = le16_to_cpu(desc.retval);
4144 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
4145 HCLGE_MAC_VLAN_REMOVE);
4148 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
4149 struct hclge_mac_vlan_tbl_entry_cmd *req,
4150 struct hclge_desc *desc,
4153 struct hclge_dev *hdev = vport->back;
4158 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
4160 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4161 memcpy(desc[0].data,
4163 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4164 hclge_cmd_setup_basic_desc(&desc[1],
4165 HCLGE_OPC_MAC_VLAN_ADD,
4167 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4168 hclge_cmd_setup_basic_desc(&desc[2],
4169 HCLGE_OPC_MAC_VLAN_ADD,
4171 ret = hclge_cmd_send(&hdev->hw, desc, 3);
4173 memcpy(desc[0].data,
4175 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4176 ret = hclge_cmd_send(&hdev->hw, desc, 1);
4179 dev_err(&hdev->pdev->dev,
4180 "lookup mac addr failed for cmd_send, ret =%d.\n",
4184 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
4185 retval = le16_to_cpu(desc[0].retval);
4187 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
4188 HCLGE_MAC_VLAN_LKUP);
4191 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
4192 struct hclge_mac_vlan_tbl_entry_cmd *req,
4193 struct hclge_desc *mc_desc)
4195 struct hclge_dev *hdev = vport->back;
4202 struct hclge_desc desc;
4204 hclge_cmd_setup_basic_desc(&desc,
4205 HCLGE_OPC_MAC_VLAN_ADD,
4207 memcpy(desc.data, req,
4208 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4209 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4210 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4211 retval = le16_to_cpu(desc.retval);
4213 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
4215 HCLGE_MAC_VLAN_ADD);
4217 hclge_cmd_reuse_desc(&mc_desc[0], false);
4218 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4219 hclge_cmd_reuse_desc(&mc_desc[1], false);
4220 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4221 hclge_cmd_reuse_desc(&mc_desc[2], false);
4222 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
4223 memcpy(mc_desc[0].data, req,
4224 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4225 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
4226 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
4227 retval = le16_to_cpu(mc_desc[0].retval);
4229 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
4231 HCLGE_MAC_VLAN_ADD);
4235 dev_err(&hdev->pdev->dev,
4236 "add mac addr failed for cmd_send, ret =%d.\n",
4244 static int hclge_add_uc_addr(struct hnae3_handle *handle,
4245 const unsigned char *addr)
4247 struct hclge_vport *vport = hclge_get_vport(handle);
4249 return hclge_add_uc_addr_common(vport, addr);
4252 int hclge_add_uc_addr_common(struct hclge_vport *vport,
4253 const unsigned char *addr)
4255 struct hclge_dev *hdev = vport->back;
4256 struct hclge_mac_vlan_tbl_entry_cmd req;
4257 struct hclge_desc desc;
4258 u16 egress_port = 0;
4261 /* mac addr check */
4262 if (is_zero_ether_addr(addr) ||
4263 is_broadcast_ether_addr(addr) ||
4264 is_multicast_ether_addr(addr)) {
4265 dev_err(&hdev->pdev->dev,
4266 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4268 is_zero_ether_addr(addr),
4269 is_broadcast_ether_addr(addr),
4270 is_multicast_ether_addr(addr));
4274 memset(&req, 0, sizeof(req));
4275 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4277 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
4278 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
4280 req.egress_port = cpu_to_le16(egress_port);
4282 hclge_prepare_mac_addr(&req, addr);
4284 /* Lookup the mac address in the mac_vlan table, and add
4285 * it if the entry is inexistent. Repeated unicast entry
4286 * is not allowed in the mac vlan table.
4288 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
4290 return hclge_add_mac_vlan_tbl(vport, &req, NULL);
4292 /* check if we just hit the duplicate */
4296 dev_err(&hdev->pdev->dev,
4297 "PF failed to add unicast entry(%pM) in the MAC table\n",
4303 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4304 const unsigned char *addr)
4306 struct hclge_vport *vport = hclge_get_vport(handle);
4308 return hclge_rm_uc_addr_common(vport, addr);
4311 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4312 const unsigned char *addr)
4314 struct hclge_dev *hdev = vport->back;
4315 struct hclge_mac_vlan_tbl_entry_cmd req;
4318 /* mac addr check */
4319 if (is_zero_ether_addr(addr) ||
4320 is_broadcast_ether_addr(addr) ||
4321 is_multicast_ether_addr(addr)) {
4322 dev_dbg(&hdev->pdev->dev,
4323 "Remove mac err! invalid mac:%pM.\n",
4328 memset(&req, 0, sizeof(req));
4329 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4330 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4331 hclge_prepare_mac_addr(&req, addr);
4332 ret = hclge_remove_mac_vlan_tbl(vport, &req);
4337 static int hclge_add_mc_addr(struct hnae3_handle *handle,
4338 const unsigned char *addr)
4340 struct hclge_vport *vport = hclge_get_vport(handle);
4342 return hclge_add_mc_addr_common(vport, addr);
4345 int hclge_add_mc_addr_common(struct hclge_vport *vport,
4346 const unsigned char *addr)
4348 struct hclge_dev *hdev = vport->back;
4349 struct hclge_mac_vlan_tbl_entry_cmd req;
4350 struct hclge_desc desc[3];
4354 /* mac addr check */
4355 if (!is_multicast_ether_addr(addr)) {
4356 dev_err(&hdev->pdev->dev,
4357 "Add mc mac err! invalid mac:%pM.\n",
4361 memset(&req, 0, sizeof(req));
4362 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4363 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4364 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4365 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4366 hclge_prepare_mac_addr(&req, addr);
4367 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4369 /* This mac addr exist, update VFID for it */
4370 hclge_update_desc_vfid(desc, vport->vport_id, false);
4371 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4373 /* This mac addr do not exist, add new entry for it */
4374 memset(desc[0].data, 0, sizeof(desc[0].data));
4375 memset(desc[1].data, 0, sizeof(desc[0].data));
4376 memset(desc[2].data, 0, sizeof(desc[0].data));
4377 hclge_update_desc_vfid(desc, vport->vport_id, false);
4378 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4381 /* If mc mac vlan table is full, use MTA table */
4382 if (status == -ENOSPC) {
4383 if (!vport->accept_mta_mc) {
4384 status = hclge_cfg_func_mta_filter(hdev,
4388 dev_err(&hdev->pdev->dev,
4389 "set mta filter mode fail ret=%d\n",
4393 vport->accept_mta_mc = true;
4396 /* Set MTA table for this MAC address */
4397 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4398 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4404 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4405 const unsigned char *addr)
4407 struct hclge_vport *vport = hclge_get_vport(handle);
4409 return hclge_rm_mc_addr_common(vport, addr);
4412 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4413 const unsigned char *addr)
4415 struct hclge_dev *hdev = vport->back;
4416 struct hclge_mac_vlan_tbl_entry_cmd req;
4417 enum hclge_cmd_status status;
4418 struct hclge_desc desc[3];
4420 /* mac addr check */
4421 if (!is_multicast_ether_addr(addr)) {
4422 dev_dbg(&hdev->pdev->dev,
4423 "Remove mc mac err! invalid mac:%pM.\n",
4428 memset(&req, 0, sizeof(req));
4429 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4430 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4431 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4432 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4433 hclge_prepare_mac_addr(&req, addr);
4434 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4436 /* This mac addr exist, remove this handle's VFID for it */
4437 hclge_update_desc_vfid(desc, vport->vport_id, true);
4439 if (hclge_is_all_function_id_zero(desc))
4440 /* All the vfid is zero, so need to delete this entry */
4441 status = hclge_remove_mac_vlan_tbl(vport, &req);
4443 /* Not all the vfid is zero, update the vfid */
4444 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4447 /* Maybe this mac address is in mta table, but it cannot be
4448 * deleted here because an entry of mta represents an address
4449 * range rather than a specific address. the delete action to
4450 * all entries will take effect in update_mta_status called by
4451 * hns3_nic_set_rx_mode.
4459 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
4460 u16 cmdq_resp, u8 resp_code)
4462 #define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4463 #define HCLGE_ETHERTYPE_ALREADY_ADD 1
4464 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4465 #define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4470 dev_err(&hdev->pdev->dev,
4471 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4476 switch (resp_code) {
4477 case HCLGE_ETHERTYPE_SUCCESS_ADD:
4478 case HCLGE_ETHERTYPE_ALREADY_ADD:
4481 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
4482 dev_err(&hdev->pdev->dev,
4483 "add mac ethertype failed for manager table overflow.\n");
4484 return_status = -EIO;
4486 case HCLGE_ETHERTYPE_KEY_CONFLICT:
4487 dev_err(&hdev->pdev->dev,
4488 "add mac ethertype failed for key conflict.\n");
4489 return_status = -EIO;
4492 dev_err(&hdev->pdev->dev,
4493 "add mac ethertype failed for undefined, code=%d.\n",
4495 return_status = -EIO;
4498 return return_status;
4501 static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
4502 const struct hclge_mac_mgr_tbl_entry_cmd *req)
4504 struct hclge_desc desc;
4509 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
4510 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
4512 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4514 dev_err(&hdev->pdev->dev,
4515 "add mac ethertype failed for cmd_send, ret =%d.\n",
4520 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4521 retval = le16_to_cpu(desc.retval);
4523 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
4526 static int init_mgr_tbl(struct hclge_dev *hdev)
4531 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
4532 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
4534 dev_err(&hdev->pdev->dev,
4535 "add mac ethertype failed, ret =%d.\n",
4544 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4546 struct hclge_vport *vport = hclge_get_vport(handle);
4547 struct hclge_dev *hdev = vport->back;
4549 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4552 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
4555 const unsigned char *new_addr = (const unsigned char *)p;
4556 struct hclge_vport *vport = hclge_get_vport(handle);
4557 struct hclge_dev *hdev = vport->back;
4560 /* mac addr check */
4561 if (is_zero_ether_addr(new_addr) ||
4562 is_broadcast_ether_addr(new_addr) ||
4563 is_multicast_ether_addr(new_addr)) {
4564 dev_err(&hdev->pdev->dev,
4565 "Change uc mac err! invalid mac:%p.\n",
4570 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
4571 dev_warn(&hdev->pdev->dev,
4572 "remove old uc mac address fail.\n");
4574 ret = hclge_add_uc_addr(handle, new_addr);
4576 dev_err(&hdev->pdev->dev,
4577 "add uc mac address fail, ret =%d.\n",
4581 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
4582 dev_err(&hdev->pdev->dev,
4583 "restore uc mac address fail.\n");
4588 ret = hclge_pause_addr_cfg(hdev, new_addr);
4590 dev_err(&hdev->pdev->dev,
4591 "configure mac pause address fail, ret =%d.\n",
4596 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4601 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4604 struct hclge_vlan_filter_ctrl_cmd *req;
4605 struct hclge_desc desc;
4608 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4610 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
4611 req->vlan_type = vlan_type;
4612 req->vlan_fe = filter_en;
4614 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4616 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4622 #define HCLGE_FILTER_TYPE_VF 0
4623 #define HCLGE_FILTER_TYPE_PORT 1
4625 static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4627 struct hclge_vport *vport = hclge_get_vport(handle);
4628 struct hclge_dev *hdev = vport->back;
4630 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4633 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4634 bool is_kill, u16 vlan, u8 qos,
4637 #define HCLGE_MAX_VF_BYTES 16
4638 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4639 struct hclge_vlan_filter_vf_cfg_cmd *req1;
4640 struct hclge_desc desc[2];
4645 hclge_cmd_setup_basic_desc(&desc[0],
4646 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4647 hclge_cmd_setup_basic_desc(&desc[1],
4648 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4650 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4652 vf_byte_off = vfid / 8;
4653 vf_byte_val = 1 << (vfid % 8);
4655 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4656 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
4658 req0->vlan_id = cpu_to_le16(vlan);
4659 req0->vlan_cfg = is_kill;
4661 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4662 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4664 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4666 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4668 dev_err(&hdev->pdev->dev,
4669 "Send vf vlan command fail, ret =%d.\n",
4675 #define HCLGE_VF_VLAN_NO_ENTRY 2
4676 if (!req0->resp_code || req0->resp_code == 1)
4679 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
4680 dev_warn(&hdev->pdev->dev,
4681 "vf vlan table is full, vf vlan filter is disabled\n");
4685 dev_err(&hdev->pdev->dev,
4686 "Add vf vlan filter fail, ret =%d.\n",
4689 #define HCLGE_VF_VLAN_DEL_NO_FOUND 1
4690 if (!req0->resp_code)
4693 if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) {
4694 dev_warn(&hdev->pdev->dev,
4695 "vlan %d filter is not in vf vlan table\n",
4700 dev_err(&hdev->pdev->dev,
4701 "Kill vf vlan filter fail, ret =%d.\n",
4708 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
4709 u16 vlan_id, bool is_kill)
4711 struct hclge_vlan_filter_pf_cfg_cmd *req;
4712 struct hclge_desc desc;
4713 u8 vlan_offset_byte_val;
4714 u8 vlan_offset_byte;
4718 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4720 vlan_offset_160 = vlan_id / 160;
4721 vlan_offset_byte = (vlan_id % 160) / 8;
4722 vlan_offset_byte_val = 1 << (vlan_id % 8);
4724 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
4725 req->vlan_offset = vlan_offset_160;
4726 req->vlan_cfg = is_kill;
4727 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4729 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4731 dev_err(&hdev->pdev->dev,
4732 "port vlan command, send fail, ret =%d.\n", ret);
4736 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
4737 u16 vport_id, u16 vlan_id, u8 qos,
4740 u16 vport_idx, vport_num = 0;
4743 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
4746 dev_err(&hdev->pdev->dev,
4747 "Set %d vport vlan filter config fail, ret =%d.\n",
4752 /* vlan 0 may be added twice when 8021q module is enabled */
4753 if (!is_kill && !vlan_id &&
4754 test_bit(vport_id, hdev->vlan_table[vlan_id]))
4757 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
4758 dev_err(&hdev->pdev->dev,
4759 "Add port vlan failed, vport %d is already in vlan %d\n",
4765 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
4766 dev_err(&hdev->pdev->dev,
4767 "Delete port vlan failed, vport %d is not in vlan %d\n",
4772 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
4775 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
4776 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
4782 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
4783 u16 vlan_id, bool is_kill)
4785 struct hclge_vport *vport = hclge_get_vport(handle);
4786 struct hclge_dev *hdev = vport->back;
4788 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
4792 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4793 u16 vlan, u8 qos, __be16 proto)
4795 struct hclge_vport *vport = hclge_get_vport(handle);
4796 struct hclge_dev *hdev = vport->back;
4798 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4800 if (proto != htons(ETH_P_8021Q))
4801 return -EPROTONOSUPPORT;
4803 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
4806 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4808 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4809 struct hclge_vport_vtag_tx_cfg_cmd *req;
4810 struct hclge_dev *hdev = vport->back;
4811 struct hclge_desc desc;
4814 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4816 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4817 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4818 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
4819 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
4820 vcfg->accept_tag1 ? 1 : 0);
4821 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
4822 vcfg->accept_untag1 ? 1 : 0);
4823 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
4824 vcfg->accept_tag2 ? 1 : 0);
4825 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
4826 vcfg->accept_untag2 ? 1 : 0);
4827 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
4828 vcfg->insert_tag1_en ? 1 : 0);
4829 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
4830 vcfg->insert_tag2_en ? 1 : 0);
4831 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
4833 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4834 req->vf_bitmap[req->vf_offset] =
4835 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4837 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4839 dev_err(&hdev->pdev->dev,
4840 "Send port txvlan cfg command fail, ret =%d\n",
4846 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4848 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4849 struct hclge_vport_vtag_rx_cfg_cmd *req;
4850 struct hclge_dev *hdev = vport->back;
4851 struct hclge_desc desc;
4854 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4856 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
4857 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4858 vcfg->strip_tag1_en ? 1 : 0);
4859 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4860 vcfg->strip_tag2_en ? 1 : 0);
4861 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4862 vcfg->vlan1_vlan_prionly ? 1 : 0);
4863 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4864 vcfg->vlan2_vlan_prionly ? 1 : 0);
4866 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4867 req->vf_bitmap[req->vf_offset] =
4868 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4870 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4872 dev_err(&hdev->pdev->dev,
4873 "Send port rxvlan cfg command fail, ret =%d\n",
4879 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4881 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4882 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4883 struct hclge_desc desc;
4886 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4887 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4888 rx_req->ot_fst_vlan_type =
4889 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4890 rx_req->ot_sec_vlan_type =
4891 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4892 rx_req->in_fst_vlan_type =
4893 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4894 rx_req->in_sec_vlan_type =
4895 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4897 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4899 dev_err(&hdev->pdev->dev,
4900 "Send rxvlan protocol type command fail, ret =%d\n",
4905 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4907 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4908 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4909 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4911 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4913 dev_err(&hdev->pdev->dev,
4914 "Send txvlan protocol type command fail, ret =%d\n",
4920 static int hclge_init_vlan_config(struct hclge_dev *hdev)
4922 #define HCLGE_DEF_VLAN_TYPE 0x8100
4924 struct hnae3_handle *handle;
4925 struct hclge_vport *vport;
4929 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4933 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
4937 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4938 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4939 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4940 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4941 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4942 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4944 ret = hclge_set_vlan_protocol_type(hdev);
4948 for (i = 0; i < hdev->num_alloc_vport; i++) {
4949 vport = &hdev->vport[i];
4950 vport->txvlan_cfg.accept_tag1 = true;
4951 vport->txvlan_cfg.accept_untag1 = true;
4953 /* accept_tag2 and accept_untag2 are not supported on
4954 * pdev revision(0x20), new revision support them. The
4955 * value of this two fields will not return error when driver
4956 * send command to fireware in revision(0x20).
4957 * This two fields can not configured by user.
4959 vport->txvlan_cfg.accept_tag2 = true;
4960 vport->txvlan_cfg.accept_untag2 = true;
4962 vport->txvlan_cfg.insert_tag1_en = false;
4963 vport->txvlan_cfg.insert_tag2_en = false;
4964 vport->txvlan_cfg.default_tag1 = 0;
4965 vport->txvlan_cfg.default_tag2 = 0;
4967 ret = hclge_set_vlan_tx_offload_cfg(vport);
4971 vport->rxvlan_cfg.strip_tag1_en = false;
4972 vport->rxvlan_cfg.strip_tag2_en = true;
4973 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4974 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4976 ret = hclge_set_vlan_rx_offload_cfg(vport);
4981 handle = &hdev->vport[0].nic;
4982 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
4985 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
4987 struct hclge_vport *vport = hclge_get_vport(handle);
4989 vport->rxvlan_cfg.strip_tag1_en = false;
4990 vport->rxvlan_cfg.strip_tag2_en = enable;
4991 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4992 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4994 return hclge_set_vlan_rx_offload_cfg(vport);
4997 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
4999 struct hclge_config_max_frm_size_cmd *req;
5000 struct hclge_desc desc;
5004 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
5006 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
5007 max_frm_size > HCLGE_MAC_MAX_FRAME)
5010 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
5012 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
5014 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
5015 req->max_frm_size = cpu_to_le16(max_frm_size);
5016 req->min_frm_size = HCLGE_MAC_MIN_FRAME;
5018 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5020 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
5022 hdev->mps = max_frm_size;
5027 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
5029 struct hclge_vport *vport = hclge_get_vport(handle);
5030 struct hclge_dev *hdev = vport->back;
5033 ret = hclge_set_mac_mtu(hdev, new_mtu);
5035 dev_err(&hdev->pdev->dev,
5036 "Change mtu fail, ret =%d\n", ret);
5040 ret = hclge_buffer_alloc(hdev);
5042 dev_err(&hdev->pdev->dev,
5043 "Allocate buffer fail, ret =%d\n", ret);
5048 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
5051 struct hclge_reset_tqp_queue_cmd *req;
5052 struct hclge_desc desc;
5055 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
5057 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
5058 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
5059 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
5061 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5063 dev_err(&hdev->pdev->dev,
5064 "Send tqp reset cmd error, status =%d\n", ret);
5071 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
5073 struct hclge_reset_tqp_queue_cmd *req;
5074 struct hclge_desc desc;
5077 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
5079 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
5080 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
5082 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5084 dev_err(&hdev->pdev->dev,
5085 "Get reset status error, status =%d\n", ret);
5089 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
5092 static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
5095 struct hnae3_queue *queue;
5096 struct hclge_tqp *tqp;
5098 queue = handle->kinfo.tqp[queue_id];
5099 tqp = container_of(queue, struct hclge_tqp, q);
5104 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
5106 struct hclge_vport *vport = hclge_get_vport(handle);
5107 struct hclge_dev *hdev = vport->back;
5108 int reset_try_times = 0;
5113 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
5116 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
5118 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
5120 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
5124 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
5126 dev_warn(&hdev->pdev->dev,
5127 "Send reset tqp cmd fail, ret = %d\n", ret);
5131 reset_try_times = 0;
5132 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5133 /* Wait for tqp hw reset */
5135 reset_status = hclge_get_reset_status(hdev, queue_gid);
5140 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5141 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5145 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
5147 dev_warn(&hdev->pdev->dev,
5148 "Deassert the soft reset fail, ret = %d\n", ret);
5153 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
5155 struct hclge_dev *hdev = vport->back;
5156 int reset_try_times = 0;
5161 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
5163 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
5165 dev_warn(&hdev->pdev->dev,
5166 "Send reset tqp cmd fail, ret = %d\n", ret);
5170 reset_try_times = 0;
5171 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
5172 /* Wait for tqp hw reset */
5174 reset_status = hclge_get_reset_status(hdev, queue_gid);
5179 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
5180 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
5184 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
5186 dev_warn(&hdev->pdev->dev,
5187 "Deassert the soft reset fail, ret = %d\n", ret);
5190 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
5192 struct hclge_vport *vport = hclge_get_vport(handle);
5193 struct hclge_dev *hdev = vport->back;
5195 return hdev->fw_version;
5198 static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
5201 struct hclge_vport *vport = hclge_get_vport(handle);
5202 struct hclge_dev *hdev = vport->back;
5203 struct phy_device *phydev = hdev->hw.mac.phydev;
5208 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
5209 (phydev->advertising & ADVERTISED_Asym_Pause);
5212 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5214 struct phy_device *phydev = hdev->hw.mac.phydev;
5219 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
5222 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
5225 phydev->advertising ^= ADVERTISED_Asym_Pause;
5228 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
5233 hdev->fc_mode_last_time = HCLGE_FC_FULL;
5234 else if (rx_en && !tx_en)
5235 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
5236 else if (!rx_en && tx_en)
5237 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
5239 hdev->fc_mode_last_time = HCLGE_FC_NONE;
5241 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
5244 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
5246 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
5251 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
5256 int hclge_cfg_flowctrl(struct hclge_dev *hdev)
5258 struct phy_device *phydev = hdev->hw.mac.phydev;
5259 u16 remote_advertising = 0;
5260 u16 local_advertising = 0;
5261 u32 rx_pause, tx_pause;
5264 if (!phydev->link || !phydev->autoneg)
5267 if (phydev->advertising & ADVERTISED_Pause)
5268 local_advertising = ADVERTISE_PAUSE_CAP;
5270 if (phydev->advertising & ADVERTISED_Asym_Pause)
5271 local_advertising |= ADVERTISE_PAUSE_ASYM;
5274 remote_advertising = LPA_PAUSE_CAP;
5276 if (phydev->asym_pause)
5277 remote_advertising |= LPA_PAUSE_ASYM;
5279 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
5280 remote_advertising);
5281 tx_pause = flowctl & FLOW_CTRL_TX;
5282 rx_pause = flowctl & FLOW_CTRL_RX;
5284 if (phydev->duplex == HCLGE_MAC_HALF) {
5289 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
5292 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
5293 u32 *rx_en, u32 *tx_en)
5295 struct hclge_vport *vport = hclge_get_vport(handle);
5296 struct hclge_dev *hdev = vport->back;
5298 *auto_neg = hclge_get_autoneg(handle);
5300 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5306 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
5309 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
5312 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
5321 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5322 u32 rx_en, u32 tx_en)
5324 struct hclge_vport *vport = hclge_get_vport(handle);
5325 struct hclge_dev *hdev = vport->back;
5326 struct phy_device *phydev = hdev->hw.mac.phydev;
5329 fc_autoneg = hclge_get_autoneg(handle);
5330 if (auto_neg != fc_autoneg) {
5331 dev_info(&hdev->pdev->dev,
5332 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5336 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5337 dev_info(&hdev->pdev->dev,
5338 "Priority flow control enabled. Cannot set link flow control.\n");
5342 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
5345 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5347 /* Only support flow control negotiation for netdev with
5348 * phy attached for now.
5353 return phy_start_aneg(phydev);
5356 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
5357 u8 *auto_neg, u32 *speed, u8 *duplex)
5359 struct hclge_vport *vport = hclge_get_vport(handle);
5360 struct hclge_dev *hdev = vport->back;
5363 *speed = hdev->hw.mac.speed;
5365 *duplex = hdev->hw.mac.duplex;
5367 *auto_neg = hdev->hw.mac.autoneg;
5370 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
5372 struct hclge_vport *vport = hclge_get_vport(handle);
5373 struct hclge_dev *hdev = vport->back;
5376 *media_type = hdev->hw.mac.media_type;
5379 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5380 u8 *tp_mdix_ctrl, u8 *tp_mdix)
5382 struct hclge_vport *vport = hclge_get_vport(handle);
5383 struct hclge_dev *hdev = vport->back;
5384 struct phy_device *phydev = hdev->hw.mac.phydev;
5385 int mdix_ctrl, mdix, retval, is_resolved;
5388 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5389 *tp_mdix = ETH_TP_MDI_INVALID;
5393 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5395 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
5396 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5397 HCLGE_PHY_MDIX_CTRL_S);
5399 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
5400 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5401 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
5403 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5405 switch (mdix_ctrl) {
5407 *tp_mdix_ctrl = ETH_TP_MDI;
5410 *tp_mdix_ctrl = ETH_TP_MDI_X;
5413 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
5416 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5421 *tp_mdix = ETH_TP_MDI_INVALID;
5423 *tp_mdix = ETH_TP_MDI_X;
5425 *tp_mdix = ETH_TP_MDI;
5428 static int hclge_init_instance_hw(struct hclge_dev *hdev)
5430 return hclge_mac_connect_phy(hdev);
5433 static void hclge_uninit_instance_hw(struct hclge_dev *hdev)
5435 hclge_mac_disconnect_phy(hdev);
5438 static int hclge_init_client_instance(struct hnae3_client *client,
5439 struct hnae3_ae_dev *ae_dev)
5441 struct hclge_dev *hdev = ae_dev->priv;
5442 struct hclge_vport *vport;
5445 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5446 vport = &hdev->vport[i];
5448 switch (client->type) {
5449 case HNAE3_CLIENT_KNIC:
5451 hdev->nic_client = client;
5452 vport->nic.client = client;
5453 ret = client->ops->init_instance(&vport->nic);
5457 ret = hclge_init_instance_hw(hdev);
5459 client->ops->uninit_instance(&vport->nic,
5464 if (hdev->roce_client &&
5465 hnae3_dev_roce_supported(hdev)) {
5466 struct hnae3_client *rc = hdev->roce_client;
5468 ret = hclge_init_roce_base_info(vport);
5472 ret = rc->ops->init_instance(&vport->roce);
5478 case HNAE3_CLIENT_UNIC:
5479 hdev->nic_client = client;
5480 vport->nic.client = client;
5482 ret = client->ops->init_instance(&vport->nic);
5487 case HNAE3_CLIENT_ROCE:
5488 if (hnae3_dev_roce_supported(hdev)) {
5489 hdev->roce_client = client;
5490 vport->roce.client = client;
5493 if (hdev->roce_client && hdev->nic_client) {
5494 ret = hclge_init_roce_base_info(vport);
5498 ret = client->ops->init_instance(&vport->roce);
5508 static void hclge_uninit_client_instance(struct hnae3_client *client,
5509 struct hnae3_ae_dev *ae_dev)
5511 struct hclge_dev *hdev = ae_dev->priv;
5512 struct hclge_vport *vport;
5515 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5516 vport = &hdev->vport[i];
5517 if (hdev->roce_client) {
5518 hdev->roce_client->ops->uninit_instance(&vport->roce,
5520 hdev->roce_client = NULL;
5521 vport->roce.client = NULL;
5523 if (client->type == HNAE3_CLIENT_ROCE)
5525 if (client->ops->uninit_instance) {
5526 hclge_uninit_instance_hw(hdev);
5527 client->ops->uninit_instance(&vport->nic, 0);
5528 hdev->nic_client = NULL;
5529 vport->nic.client = NULL;
5534 static int hclge_pci_init(struct hclge_dev *hdev)
5536 struct pci_dev *pdev = hdev->pdev;
5537 struct hclge_hw *hw;
5540 ret = pci_enable_device(pdev);
5542 dev_err(&pdev->dev, "failed to enable PCI device\n");
5546 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5548 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5551 "can't set consistent PCI DMA");
5552 goto err_disable_device;
5554 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5557 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5559 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5560 goto err_disable_device;
5563 pci_set_master(pdev);
5565 hw->io_base = pcim_iomap(pdev, 2, 0);
5567 dev_err(&pdev->dev, "Can't map configuration register space\n");
5569 goto err_clr_master;
5572 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5576 pci_clear_master(pdev);
5577 pci_release_regions(pdev);
5579 pci_disable_device(pdev);
5584 static void hclge_pci_uninit(struct hclge_dev *hdev)
5586 struct pci_dev *pdev = hdev->pdev;
5588 pcim_iounmap(pdev, hdev->hw.io_base);
5589 pci_free_irq_vectors(pdev);
5590 pci_clear_master(pdev);
5591 pci_release_mem_regions(pdev);
5592 pci_disable_device(pdev);
5595 static void hclge_state_init(struct hclge_dev *hdev)
5597 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5598 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5599 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5600 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5601 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5602 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5605 static void hclge_state_uninit(struct hclge_dev *hdev)
5607 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5609 if (hdev->service_timer.function)
5610 del_timer_sync(&hdev->service_timer);
5611 if (hdev->service_task.func)
5612 cancel_work_sync(&hdev->service_task);
5613 if (hdev->rst_service_task.func)
5614 cancel_work_sync(&hdev->rst_service_task);
5615 if (hdev->mbx_service_task.func)
5616 cancel_work_sync(&hdev->mbx_service_task);
5619 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5621 struct pci_dev *pdev = ae_dev->pdev;
5622 struct hclge_dev *hdev;
5625 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5632 hdev->ae_dev = ae_dev;
5633 hdev->reset_type = HNAE3_NONE_RESET;
5634 ae_dev->priv = hdev;
5636 ret = hclge_pci_init(hdev);
5638 dev_err(&pdev->dev, "PCI init failed\n");
5642 /* Firmware command queue initialize */
5643 ret = hclge_cmd_queue_init(hdev);
5645 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
5646 goto err_pci_uninit;
5649 /* Firmware command initialize */
5650 ret = hclge_cmd_init(hdev);
5652 goto err_cmd_uninit;
5654 ret = hclge_get_cap(hdev);
5656 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5658 goto err_cmd_uninit;
5661 ret = hclge_configure(hdev);
5663 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5664 goto err_cmd_uninit;
5667 ret = hclge_init_msi(hdev);
5669 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
5670 goto err_cmd_uninit;
5673 ret = hclge_misc_irq_init(hdev);
5676 "Misc IRQ(vector0) init error, ret = %d.\n",
5678 goto err_msi_uninit;
5681 ret = hclge_alloc_tqps(hdev);
5683 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
5684 goto err_msi_irq_uninit;
5687 ret = hclge_alloc_vport(hdev);
5689 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
5690 goto err_msi_irq_uninit;
5693 ret = hclge_map_tqp(hdev);
5695 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5696 goto err_msi_irq_uninit;
5699 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
5700 ret = hclge_mac_mdio_config(hdev);
5702 dev_err(&hdev->pdev->dev,
5703 "mdio config fail ret=%d\n", ret);
5704 goto err_msi_irq_uninit;
5708 ret = hclge_mac_init(hdev);
5710 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5711 goto err_mdiobus_unreg;
5714 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5716 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5717 goto err_mdiobus_unreg;
5720 ret = hclge_init_vlan_config(hdev);
5722 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5723 goto err_mdiobus_unreg;
5726 ret = hclge_tm_schd_init(hdev);
5728 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5729 goto err_mdiobus_unreg;
5732 hclge_rss_init_cfg(hdev);
5733 ret = hclge_rss_init_hw(hdev);
5735 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5736 goto err_mdiobus_unreg;
5739 ret = init_mgr_tbl(hdev);
5741 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
5742 goto err_mdiobus_unreg;
5745 hclge_dcb_ops_set(hdev);
5747 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
5748 INIT_WORK(&hdev->service_task, hclge_service_task);
5749 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
5750 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
5752 hclge_clear_all_event_cause(hdev);
5754 /* Enable MISC vector(vector0) */
5755 hclge_enable_vector(&hdev->misc_vector, true);
5757 hclge_state_init(hdev);
5759 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5763 if (hdev->hw.mac.phydev)
5764 mdiobus_unregister(hdev->hw.mac.mdio_bus);
5766 hclge_misc_irq_uninit(hdev);
5768 pci_free_irq_vectors(pdev);
5770 hclge_destroy_cmd_queue(&hdev->hw);
5772 pcim_iounmap(pdev, hdev->hw.io_base);
5773 pci_clear_master(pdev);
5774 pci_release_regions(pdev);
5775 pci_disable_device(pdev);
5780 static void hclge_stats_clear(struct hclge_dev *hdev)
5782 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5785 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5787 struct hclge_dev *hdev = ae_dev->priv;
5788 struct pci_dev *pdev = ae_dev->pdev;
5791 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5793 hclge_stats_clear(hdev);
5794 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
5796 ret = hclge_cmd_init(hdev);
5798 dev_err(&pdev->dev, "Cmd queue init failed\n");
5802 ret = hclge_get_cap(hdev);
5804 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5809 ret = hclge_configure(hdev);
5811 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5815 ret = hclge_map_tqp(hdev);
5817 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5821 ret = hclge_mac_init(hdev);
5823 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5827 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5829 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5833 ret = hclge_init_vlan_config(hdev);
5835 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5839 ret = hclge_tm_init_hw(hdev);
5841 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
5845 ret = hclge_rss_init_hw(hdev);
5847 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5851 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5857 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5859 struct hclge_dev *hdev = ae_dev->priv;
5860 struct hclge_mac *mac = &hdev->hw.mac;
5862 hclge_state_uninit(hdev);
5865 mdiobus_unregister(mac->mdio_bus);
5867 /* Disable MISC vector(vector0) */
5868 hclge_enable_vector(&hdev->misc_vector, false);
5869 synchronize_irq(hdev->misc_vector.vector_irq);
5871 hclge_destroy_cmd_queue(&hdev->hw);
5872 hclge_misc_irq_uninit(hdev);
5873 hclge_pci_uninit(hdev);
5874 ae_dev->priv = NULL;
5877 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5879 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5880 struct hclge_vport *vport = hclge_get_vport(handle);
5881 struct hclge_dev *hdev = vport->back;
5883 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5886 static void hclge_get_channels(struct hnae3_handle *handle,
5887 struct ethtool_channels *ch)
5889 struct hclge_vport *vport = hclge_get_vport(handle);
5891 ch->max_combined = hclge_get_max_channels(handle);
5892 ch->other_count = 1;
5894 ch->combined_count = vport->alloc_tqps;
5897 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5898 u16 *free_tqps, u16 *max_rss_size)
5900 struct hclge_vport *vport = hclge_get_vport(handle);
5901 struct hclge_dev *hdev = vport->back;
5905 for (i = 0; i < hdev->num_tqps; i++) {
5906 if (!hdev->htqp[i].alloced)
5909 *free_tqps = temp_tqps;
5910 *max_rss_size = hdev->rss_size_max;
5913 static void hclge_release_tqp(struct hclge_vport *vport)
5915 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5916 struct hclge_dev *hdev = vport->back;
5919 for (i = 0; i < kinfo->num_tqps; i++) {
5920 struct hclge_tqp *tqp =
5921 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5923 tqp->q.handle = NULL;
5924 tqp->q.tqp_index = 0;
5925 tqp->alloced = false;
5928 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5932 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5934 struct hclge_vport *vport = hclge_get_vport(handle);
5935 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5936 struct hclge_dev *hdev = vport->back;
5937 int cur_rss_size = kinfo->rss_size;
5938 int cur_tqps = kinfo->num_tqps;
5939 u16 tc_offset[HCLGE_MAX_TC_NUM];
5940 u16 tc_valid[HCLGE_MAX_TC_NUM];
5941 u16 tc_size[HCLGE_MAX_TC_NUM];
5946 /* Free old tqps, and reallocate with new tqp number when nic setup */
5947 hclge_release_tqp(vport);
5949 ret = hclge_knic_setup(vport, new_tqps_num, kinfo->num_desc);
5951 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5955 ret = hclge_map_tqp_to_vport(hdev, vport);
5957 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5961 ret = hclge_tm_schd_init(hdev);
5963 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5967 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5968 roundup_size = ilog2(roundup_size);
5969 /* Set the RSS TC mode according to the new RSS size */
5970 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5973 if (!(hdev->hw_tc_map & BIT(i)))
5977 tc_size[i] = roundup_size;
5978 tc_offset[i] = kinfo->rss_size * i;
5980 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5984 /* Reinitializes the rss indirect table according to the new RSS size */
5985 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5989 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5990 rss_indir[i] = i % kinfo->rss_size;
5992 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5994 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
6000 dev_info(&hdev->pdev->dev,
6001 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
6002 cur_rss_size, kinfo->rss_size,
6003 cur_tqps, kinfo->rss_size * kinfo->num_tc);
6008 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
6009 u32 *regs_num_64_bit)
6011 struct hclge_desc desc;
6015 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
6016 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6018 dev_err(&hdev->pdev->dev,
6019 "Query register number cmd failed, ret = %d.\n", ret);
6023 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
6024 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
6026 total_num = *regs_num_32_bit + *regs_num_64_bit;
6033 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6036 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
6038 struct hclge_desc *desc;
6039 u32 *reg_val = data;
6048 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
6049 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6053 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
6054 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6056 dev_err(&hdev->pdev->dev,
6057 "Query 32 bit register cmd failed, ret = %d.\n", ret);
6062 for (i = 0; i < cmd_num; i++) {
6064 desc_data = (__le32 *)(&desc[i].data[0]);
6065 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
6067 desc_data = (__le32 *)(&desc[i]);
6068 n = HCLGE_32_BIT_REG_RTN_DATANUM;
6070 for (k = 0; k < n; k++) {
6071 *reg_val++ = le32_to_cpu(*desc_data++);
6083 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
6086 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
6088 struct hclge_desc *desc;
6089 u64 *reg_val = data;
6098 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
6099 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
6103 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
6104 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
6106 dev_err(&hdev->pdev->dev,
6107 "Query 64 bit register cmd failed, ret = %d.\n", ret);
6112 for (i = 0; i < cmd_num; i++) {
6114 desc_data = (__le64 *)(&desc[i].data[0]);
6115 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
6117 desc_data = (__le64 *)(&desc[i]);
6118 n = HCLGE_64_BIT_REG_RTN_DATANUM;
6120 for (k = 0; k < n; k++) {
6121 *reg_val++ = le64_to_cpu(*desc_data++);
6133 static int hclge_get_regs_len(struct hnae3_handle *handle)
6135 struct hclge_vport *vport = hclge_get_vport(handle);
6136 struct hclge_dev *hdev = vport->back;
6137 u32 regs_num_32_bit, regs_num_64_bit;
6140 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit);
6142 dev_err(&hdev->pdev->dev,
6143 "Get register number failed, ret = %d.\n", ret);
6147 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
6150 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
6153 struct hclge_vport *vport = hclge_get_vport(handle);
6154 struct hclge_dev *hdev = vport->back;
6155 u32 regs_num_32_bit, regs_num_64_bit;
6158 *version = hdev->fw_version;
6160 ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit);
6162 dev_err(&hdev->pdev->dev,
6163 "Get register number failed, ret = %d.\n", ret);
6167 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
6169 dev_err(&hdev->pdev->dev,
6170 "Get 32 bit register failed, ret = %d.\n", ret);
6174 data = (u32 *)data + regs_num_32_bit;
6175 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
6178 dev_err(&hdev->pdev->dev,
6179 "Get 64 bit register failed, ret = %d.\n", ret);
6182 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
6184 struct hclge_set_led_state_cmd *req;
6185 struct hclge_desc desc;
6188 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
6190 req = (struct hclge_set_led_state_cmd *)desc.data;
6191 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
6192 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
6194 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6196 dev_err(&hdev->pdev->dev,
6197 "Send set led state cmd error, ret =%d\n", ret);
6202 enum hclge_led_status {
6205 HCLGE_LED_NO_CHANGE = 0xFF,
6208 static int hclge_set_led_id(struct hnae3_handle *handle,
6209 enum ethtool_phys_id_state status)
6211 struct hclge_vport *vport = hclge_get_vport(handle);
6212 struct hclge_dev *hdev = vport->back;
6215 case ETHTOOL_ID_ACTIVE:
6216 return hclge_set_led_status(hdev, HCLGE_LED_ON);
6217 case ETHTOOL_ID_INACTIVE:
6218 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
6224 static void hclge_get_link_mode(struct hnae3_handle *handle,
6225 unsigned long *supported,
6226 unsigned long *advertising)
6228 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
6229 struct hclge_vport *vport = hclge_get_vport(handle);
6230 struct hclge_dev *hdev = vport->back;
6231 unsigned int idx = 0;
6233 for (; idx < size; idx++) {
6234 supported[idx] = hdev->hw.mac.supported[idx];
6235 advertising[idx] = hdev->hw.mac.advertising[idx];
6239 static void hclge_get_port_type(struct hnae3_handle *handle,
6242 struct hclge_vport *vport = hclge_get_vport(handle);
6243 struct hclge_dev *hdev = vport->back;
6244 u8 media_type = hdev->hw.mac.media_type;
6246 switch (media_type) {
6247 case HNAE3_MEDIA_TYPE_FIBER:
6248 *port_type = PORT_FIBRE;
6250 case HNAE3_MEDIA_TYPE_COPPER:
6251 *port_type = PORT_TP;
6253 case HNAE3_MEDIA_TYPE_UNKNOWN:
6255 *port_type = PORT_OTHER;
6260 static const struct hnae3_ae_ops hclge_ops = {
6261 .init_ae_dev = hclge_init_ae_dev,
6262 .uninit_ae_dev = hclge_uninit_ae_dev,
6263 .init_client_instance = hclge_init_client_instance,
6264 .uninit_client_instance = hclge_uninit_client_instance,
6265 .map_ring_to_vector = hclge_map_ring_to_vector,
6266 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
6267 .get_vector = hclge_get_vector,
6268 .put_vector = hclge_put_vector,
6269 .set_promisc_mode = hclge_set_promisc_mode,
6270 .set_loopback = hclge_set_loopback,
6271 .start = hclge_ae_start,
6272 .stop = hclge_ae_stop,
6273 .get_status = hclge_get_status,
6274 .get_ksettings_an_result = hclge_get_ksettings_an_result,
6275 .update_speed_duplex_h = hclge_update_speed_duplex_h,
6276 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
6277 .get_media_type = hclge_get_media_type,
6278 .get_rss_key_size = hclge_get_rss_key_size,
6279 .get_rss_indir_size = hclge_get_rss_indir_size,
6280 .get_rss = hclge_get_rss,
6281 .set_rss = hclge_set_rss,
6282 .set_rss_tuple = hclge_set_rss_tuple,
6283 .get_rss_tuple = hclge_get_rss_tuple,
6284 .get_tc_size = hclge_get_tc_size,
6285 .get_mac_addr = hclge_get_mac_addr,
6286 .set_mac_addr = hclge_set_mac_addr,
6287 .add_uc_addr = hclge_add_uc_addr,
6288 .rm_uc_addr = hclge_rm_uc_addr,
6289 .add_mc_addr = hclge_add_mc_addr,
6290 .rm_mc_addr = hclge_rm_mc_addr,
6291 .update_mta_status = hclge_update_mta_status,
6292 .set_autoneg = hclge_set_autoneg,
6293 .get_autoneg = hclge_get_autoneg,
6294 .get_pauseparam = hclge_get_pauseparam,
6295 .set_pauseparam = hclge_set_pauseparam,
6296 .set_mtu = hclge_set_mtu,
6297 .reset_queue = hclge_reset_tqp,
6298 .get_stats = hclge_get_stats,
6299 .update_stats = hclge_update_stats,
6300 .get_strings = hclge_get_strings,
6301 .get_sset_count = hclge_get_sset_count,
6302 .get_fw_version = hclge_get_fw_version,
6303 .get_mdix_mode = hclge_get_mdix_mode,
6304 .enable_vlan_filter = hclge_enable_vlan_filter,
6305 .set_vlan_filter = hclge_set_vlan_filter,
6306 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
6307 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
6308 .reset_event = hclge_reset_event,
6309 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
6310 .set_channels = hclge_set_channels,
6311 .get_channels = hclge_get_channels,
6312 .get_flowctrl_adv = hclge_get_flowctrl_adv,
6313 .get_regs_len = hclge_get_regs_len,
6314 .get_regs = hclge_get_regs,
6315 .set_led_id = hclge_set_led_id,
6316 .get_link_mode = hclge_get_link_mode,
6317 .get_port_type = hclge_get_port_type,
6320 static struct hnae3_ae_algo ae_algo = {
6322 .pdev_id_table = ae_algo_pci_tbl,
6325 static int hclge_init(void)
6327 pr_info("%s is initializing\n", HCLGE_NAME);
6329 hnae3_register_ae_algo(&ae_algo);
6334 static void hclge_exit(void)
6336 hnae3_unregister_ae_algo(&ae_algo);
6338 module_init(hclge_init);
6339 module_exit(hclge_exit);
6341 MODULE_LICENSE("GPL");
6342 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6343 MODULE_DESCRIPTION("HCLGE Driver");
6344 MODULE_VERSION(HCLGE_MOD_VERSION);