drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/acpi.h>
   5 #include <linux/device.h>
   6 #include <linux/etherdevice.h>
   7 #include <linux/init.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/pci.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/if_vlan.h>
  15 #include <net/rtnetlink.h>
  16 #include "hclge_cmd.h"
  17 #include "hclge_dcb.h"
  18 #include "hclge_main.h"
  19 #include "hclge_mbx.h"
  20 #include "hclge_mdio.h"
  21 #include "hclge_tm.h"
  22 #include "hclge_err.h"
  23 #include "hnae3.h"
  24
  25 #define HCLGE_NAME                      "hclge"
  26 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
  27 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
  28
  29 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
  30 static int hclge_init_vlan_config(struct hclge_dev *hdev);
  31 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
  32 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
  33                                u16 *allocated_size, bool is_alloc);
  34
  35 static struct hnae3_ae_algo ae_algo;
  36
  37 static const struct pci_device_id ae_algo_pci_tbl[] = {
  38         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
  39         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
  40         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
  41         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
  42         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
  43         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
  44         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
  45         /* required last entry */
  46         {0, }
  47 };
  48
  49 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
  50
  51 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
  52         "App    Loopback test",
  53         "Serdes serial Loopback test",
  54         "Serdes parallel Loopback test",
  55         "Phy    Loopback test"
  56 };
  57
  58 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
  59         {"mac_tx_mac_pause_num",
  60                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
  61         {"mac_rx_mac_pause_num",
  62                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
  63         {"mac_tx_pfc_pri0_pkt_num",
  64                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
  65         {"mac_tx_pfc_pri1_pkt_num",
  66                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
  67         {"mac_tx_pfc_pri2_pkt_num",
  68                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
  69         {"mac_tx_pfc_pri3_pkt_num",
  70                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
  71         {"mac_tx_pfc_pri4_pkt_num",
  72                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
  73         {"mac_tx_pfc_pri5_pkt_num",
  74                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
  75         {"mac_tx_pfc_pri6_pkt_num",
  76                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
  77         {"mac_tx_pfc_pri7_pkt_num",
  78                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
  79         {"mac_rx_pfc_pri0_pkt_num",
  80                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
  81         {"mac_rx_pfc_pri1_pkt_num",
  82                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
  83         {"mac_rx_pfc_pri2_pkt_num",
  84                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
  85         {"mac_rx_pfc_pri3_pkt_num",
  86                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
  87         {"mac_rx_pfc_pri4_pkt_num",
  88                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
  89         {"mac_rx_pfc_pri5_pkt_num",
  90                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
  91         {"mac_rx_pfc_pri6_pkt_num",
  92                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
  93         {"mac_rx_pfc_pri7_pkt_num",
  94                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
  95         {"mac_tx_total_pkt_num",
  96                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
  97         {"mac_tx_total_oct_num",
  98                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
  99         {"mac_tx_good_pkt_num",
 100                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
 101         {"mac_tx_bad_pkt_num",
 102                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
 103         {"mac_tx_good_oct_num",
 104                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
 105         {"mac_tx_bad_oct_num",
 106                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
 107         {"mac_tx_uni_pkt_num",
 108                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
 109         {"mac_tx_multi_pkt_num",
 110                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
 111         {"mac_tx_broad_pkt_num",
 112                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
 113         {"mac_tx_undersize_pkt_num",
 114                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
 115         {"mac_tx_oversize_pkt_num",
 116                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
 117         {"mac_tx_64_oct_pkt_num",
 118                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
 119         {"mac_tx_65_127_oct_pkt_num",
 120                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
 121         {"mac_tx_128_255_oct_pkt_num",
 122                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
 123         {"mac_tx_256_511_oct_pkt_num",
 124                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
 125         {"mac_tx_512_1023_oct_pkt_num",
 126                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
 127         {"mac_tx_1024_1518_oct_pkt_num",
 128                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
 129         {"mac_tx_1519_2047_oct_pkt_num",
 130                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
 131         {"mac_tx_2048_4095_oct_pkt_num",
 132                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
 133         {"mac_tx_4096_8191_oct_pkt_num",
 134                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
 135         {"mac_tx_8192_9216_oct_pkt_num",
 136                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
 137         {"mac_tx_9217_12287_oct_pkt_num",
 138                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
 139         {"mac_tx_12288_16383_oct_pkt_num",
 140                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
 141         {"mac_tx_1519_max_good_pkt_num",
 142                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
 143         {"mac_tx_1519_max_bad_pkt_num",
 144                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
 145         {"mac_rx_total_pkt_num",
 146                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
 147         {"mac_rx_total_oct_num",
 148                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
 149         {"mac_rx_good_pkt_num",
 150                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
 151         {"mac_rx_bad_pkt_num",
 152                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
 153         {"mac_rx_good_oct_num",
 154                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
 155         {"mac_rx_bad_oct_num",
 156                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
 157         {"mac_rx_uni_pkt_num",
 158                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
 159         {"mac_rx_multi_pkt_num",
 160                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
 161         {"mac_rx_broad_pkt_num",
 162                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
 163         {"mac_rx_undersize_pkt_num",
 164                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
 165         {"mac_rx_oversize_pkt_num",
 166                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
 167         {"mac_rx_64_oct_pkt_num",
 168                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
 169         {"mac_rx_65_127_oct_pkt_num",
 170                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
 171         {"mac_rx_128_255_oct_pkt_num",
 172                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
 173         {"mac_rx_256_511_oct_pkt_num",
 174                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
 175         {"mac_rx_512_1023_oct_pkt_num",
 176                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
 177         {"mac_rx_1024_1518_oct_pkt_num",
 178                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
 179         {"mac_rx_1519_2047_oct_pkt_num",
 180                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
 181         {"mac_rx_2048_4095_oct_pkt_num",
 182                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
 183         {"mac_rx_4096_8191_oct_pkt_num",
 184                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
 185         {"mac_rx_8192_9216_oct_pkt_num",
 186                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
 187         {"mac_rx_9217_12287_oct_pkt_num",
 188                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
 189         {"mac_rx_12288_16383_oct_pkt_num",
 190                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
 191         {"mac_rx_1519_max_good_pkt_num",
 192                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
 193         {"mac_rx_1519_max_bad_pkt_num",
 194                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
 195
 196         {"mac_tx_fragment_pkt_num",
 197                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
 198         {"mac_tx_undermin_pkt_num",
 199                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
 200         {"mac_tx_jabber_pkt_num",
 201                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
 202         {"mac_tx_err_all_pkt_num",
 203                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
 204         {"mac_tx_from_app_good_pkt_num",
 205                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
 206         {"mac_tx_from_app_bad_pkt_num",
 207                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
 208         {"mac_rx_fragment_pkt_num",
 209                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
 210         {"mac_rx_undermin_pkt_num",
 211                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
 212         {"mac_rx_jabber_pkt_num",
 213                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
 214         {"mac_rx_fcs_err_pkt_num",
 215                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
 216         {"mac_rx_send_app_good_pkt_num",
 217                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
 218         {"mac_rx_send_app_bad_pkt_num",
 219                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
 220 };
 221
 222 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
 223         {
 224                 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
 225                 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
 226                 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
 227                 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
 228                 .i_port_bitmap = 0x1,
 229         },
 230 };
 231
 232 static int hclge_mac_update_stats(struct hclge_dev *hdev)
 233 {
 234 #define HCLGE_MAC_CMD_NUM 21
 235 #define HCLGE_RTN_DATA_NUM 4
 236
 237         u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
 238         struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
 239         __le64 *desc_data;
 240         int i, k, n;
 241         int ret;
 242
 243         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
 244         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
 245         if (ret) {
 246                 dev_err(&hdev->pdev->dev,
 247                         "Get MAC pkt stats fail, status = %d.\n", ret);
 248
 249                 return ret;
 250         }
 251
 252         for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
 253                 if (unlikely(i == 0)) {
 254                         desc_data = (__le64 *)(&desc[i].data[0]);
 255                         n = HCLGE_RTN_DATA_NUM - 2;
 256                 } else {
 257                         desc_data = (__le64 *)(&desc[i]);
 258                         n = HCLGE_RTN_DATA_NUM;
 259                 }
 260                 for (k = 0; k < n; k++) {
 261                         *data++ += le64_to_cpu(*desc_data);
 262                         desc_data++;
 263                 }
 264         }
 265
 266         return 0;
 267 }
 268
 269 static int hclge_tqps_update_stats(struct hnae3_handle *handle)
 270 {
 271         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 272         struct hclge_vport *vport = hclge_get_vport(handle);
 273         struct hclge_dev *hdev = vport->back;
 274         struct hnae3_queue *queue;
 275         struct hclge_desc desc[1];
 276         struct hclge_tqp *tqp;
 277         int ret, i;
 278
 279         for (i = 0; i < kinfo->num_tqps; i++) {
 280                 queue = handle->kinfo.tqp[i];
 281                 tqp = container_of(queue, struct hclge_tqp, q);
 282                 /* command : HCLGE_OPC_QUERY_IGU_STAT */
 283                 hclge_cmd_setup_basic_desc(&desc[0],
 284                                            HCLGE_OPC_QUERY_RX_STATUS,
 285                                            true);
 286
 287                 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
 288                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
 289                 if (ret) {
 290                         dev_err(&hdev->pdev->dev,
 291                                 "Query tqp stat fail, status = %d,queue = %d\n",
 292                                 ret,    i);
 293                         return ret;
 294                 }
 295                 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
 296                         le32_to_cpu(desc[0].data[1]);
 297         }
 298
 299         for (i = 0; i < kinfo->num_tqps; i++) {
 300                 queue = handle->kinfo.tqp[i];
 301                 tqp = container_of(queue, struct hclge_tqp, q);
 302                 /* command : HCLGE_OPC_QUERY_IGU_STAT */
 303                 hclge_cmd_setup_basic_desc(&desc[0],
 304                                            HCLGE_OPC_QUERY_TX_STATUS,
 305                                            true);
 306
 307                 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
 308                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
 309                 if (ret) {
 310                         dev_err(&hdev->pdev->dev,
 311                                 "Query tqp stat fail, status = %d,queue = %d\n",
 312                                 ret, i);
 313                         return ret;
 314                 }
 315                 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
 316                         le32_to_cpu(desc[0].data[1]);
 317         }
 318
 319         return 0;
 320 }
 321
 322 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
 323 {
 324         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 325         struct hclge_tqp *tqp;
 326         u64 *buff = data;
 327         int i;
 328
 329         for (i = 0; i < kinfo->num_tqps; i++) {
 330                 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
 331                 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
 332         }
 333
 334         for (i = 0; i < kinfo->num_tqps; i++) {
 335                 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
 336                 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
 337         }
 338
 339         return buff;
 340 }
 341
 342 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
 343 {
 344         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 345
 346         return kinfo->num_tqps * (2);
 347 }
 348
 349 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
 350 {
 351         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 352         u8 *buff = data;
 353         int i = 0;
 354
 355         for (i = 0; i < kinfo->num_tqps; i++) {
 356                 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
 357                         struct hclge_tqp, q);
 358                 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
 359                          tqp->index);
 360                 buff = buff + ETH_GSTRING_LEN;
 361         }
 362
 363         for (i = 0; i < kinfo->num_tqps; i++) {
 364                 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
 365                         struct hclge_tqp, q);
 366                 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
 367                          tqp->index);
 368                 buff = buff + ETH_GSTRING_LEN;
 369         }
 370
 371         return buff;
 372 }
 373
 374 static u64 *hclge_comm_get_stats(void *comm_stats,
 375                                  const struct hclge_comm_stats_str strs[],
 376                                  int size, u64 *data)
 377 {
 378         u64 *buf = data;
 379         u32 i;
 380
 381         for (i = 0; i < size; i++)
 382                 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
 383
 384         return buf + size;
 385 }
 386
 387 static u8 *hclge_comm_get_strings(u32 stringset,
 388                                   const struct hclge_comm_stats_str strs[],
 389                                   int size, u8 *data)
 390 {
 391         char *buff = (char *)data;
 392         u32 i;
 393
 394         if (stringset != ETH_SS_STATS)
 395                 return buff;
 396
 397         for (i = 0; i < size; i++) {
 398                 snprintf(buff, ETH_GSTRING_LEN,
 399                          strs[i].desc);
 400                 buff = buff + ETH_GSTRING_LEN;
 401         }
 402
 403         return (u8 *)buff;
 404 }
 405
 406 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
 407                                  struct net_device_stats *net_stats)
 408 {
 409         net_stats->tx_dropped = 0;
 410         net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 411         net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
 412         net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
 413
 414         net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
 415         net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
 416
 417         net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
 418         net_stats->rx_length_errors =
 419                 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
 420         net_stats->rx_length_errors +=
 421                 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 422         net_stats->rx_over_errors =
 423                 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 424 }
 425
 426 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
 427 {
 428         struct hnae3_handle *handle;
 429         int status;
 430
 431         handle = &hdev->vport[0].nic;
 432         if (handle->client) {
 433                 status = hclge_tqps_update_stats(handle);
 434                 if (status) {
 435                         dev_err(&hdev->pdev->dev,
 436                                 "Update TQPS stats fail, status = %d.\n",
 437                                 status);
 438                 }
 439         }
 440
 441         status = hclge_mac_update_stats(hdev);
 442         if (status)
 443                 dev_err(&hdev->pdev->dev,
 444                         "Update MAC stats fail, status = %d.\n", status);
 445
 446         hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
 447 }
 448
 449 static void hclge_update_stats(struct hnae3_handle *handle,
 450                                struct net_device_stats *net_stats)
 451 {
 452         struct hclge_vport *vport = hclge_get_vport(handle);
 453         struct hclge_dev *hdev = vport->back;
 454         struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
 455         int status;
 456
 457         if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
 458                 return;
 459
 460         status = hclge_mac_update_stats(hdev);
 461         if (status)
 462                 dev_err(&hdev->pdev->dev,
 463                         "Update MAC stats fail, status = %d.\n",
 464                         status);
 465
 466         status = hclge_tqps_update_stats(handle);
 467         if (status)
 468                 dev_err(&hdev->pdev->dev,
 469                         "Update TQPS stats fail, status = %d.\n",
 470                         status);
 471
 472         hclge_update_netstat(hw_stats, net_stats);
 473
 474         clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
 475 }
 476
 477 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
 478 {
 479 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK |\
 480                 HNAE3_SUPPORT_PHY_LOOPBACK |\
 481                 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK |\
 482                 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK)
 483
 484         struct hclge_vport *vport = hclge_get_vport(handle);
 485         struct hclge_dev *hdev = vport->back;
 486         int count = 0;
 487
 488         /* Loopback test support rules:
 489          * mac: only GE mode support
 490          * serdes: all mac mode will support include GE/XGE/LGE/CGE
 491          * phy: only support when phy device exist on board
 492          */
 493         if (stringset == ETH_SS_TEST) {
 494                 /* clear loopback bit flags at first */
 495                 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
 496                 if (hdev->pdev->revision >= 0x21 ||
 497                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
 498                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
 499                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
 500                         count += 1;
 501                         handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
 502                 }
 503
 504                 count += 2;
 505                 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
 506                 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
 507         } else if (stringset == ETH_SS_STATS) {
 508                 count = ARRAY_SIZE(g_mac_stats_string) +
 509                         hclge_tqps_get_sset_count(handle, stringset);
 510         }
 511
 512         return count;
 513 }
 514
 515 static void hclge_get_strings(struct hnae3_handle *handle,
 516                               u32 stringset,
 517                               u8 *data)
 518 {
 519         u8 *p = (char *)data;
 520         int size;
 521
 522         if (stringset == ETH_SS_STATS) {
 523                 size = ARRAY_SIZE(g_mac_stats_string);
 524                 p = hclge_comm_get_strings(stringset,
 525                                            g_mac_stats_string,
 526                                            size,
 527                                            p);
 528                 p = hclge_tqps_get_strings(handle, p);
 529         } else if (stringset == ETH_SS_TEST) {
 530                 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
 531                         memcpy(p,
 532                                hns3_nic_test_strs[HNAE3_LOOP_APP],
 533                                ETH_GSTRING_LEN);
 534                         p += ETH_GSTRING_LEN;
 535                 }
 536                 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) {
 537                         memcpy(p,
 538                                hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES],
 539                                ETH_GSTRING_LEN);
 540                         p += ETH_GSTRING_LEN;
 541                 }
 542                 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) {
 543                         memcpy(p,
 544                                hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES],
 545                                ETH_GSTRING_LEN);
 546                         p += ETH_GSTRING_LEN;
 547                 }
 548                 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
 549                         memcpy(p,
 550                                hns3_nic_test_strs[HNAE3_LOOP_PHY],
 551                                ETH_GSTRING_LEN);
 552                         p += ETH_GSTRING_LEN;
 553                 }
 554         }
 555 }
 556
 557 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
 558 {
 559         struct hclge_vport *vport = hclge_get_vport(handle);
 560         struct hclge_dev *hdev = vport->back;
 561         u64 *p;
 562
 563         p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
 564                                  g_mac_stats_string,
 565                                  ARRAY_SIZE(g_mac_stats_string),
 566                                  data);
 567         p = hclge_tqps_get_stats(handle, p);
 568 }
 569
 570 static int hclge_parse_func_status(struct hclge_dev *hdev,
 571                                    struct hclge_func_status_cmd *status)
 572 {
 573         if (!(status->pf_state & HCLGE_PF_STATE_DONE))
 574                 return -EINVAL;
 575
 576         /* Set the pf to main pf */
 577         if (status->pf_state & HCLGE_PF_STATE_MAIN)
 578                 hdev->flag |= HCLGE_FLAG_MAIN;
 579         else
 580                 hdev->flag &= ~HCLGE_FLAG_MAIN;
 581
 582         return 0;
 583 }
 584
 585 static int hclge_query_function_status(struct hclge_dev *hdev)
 586 {
 587         struct hclge_func_status_cmd *req;
 588         struct hclge_desc desc;
 589         int timeout = 0;
 590         int ret;
 591
 592         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
 593         req = (struct hclge_func_status_cmd *)desc.data;
 594
 595         do {
 596                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 597                 if (ret) {
 598                         dev_err(&hdev->pdev->dev,
 599                                 "query function status failed %d.\n",
 600                                 ret);
 601
 602                         return ret;
 603                 }
 604
 605                 /* Check pf reset is done */
 606                 if (req->pf_state)
 607                         break;
 608                 usleep_range(1000, 2000);
 609         } while (timeout++ < 5);
 610
 611         ret = hclge_parse_func_status(hdev, req);
 612
 613         return ret;
 614 }
 615
 616 static int hclge_query_pf_resource(struct hclge_dev *hdev)
 617 {
 618         struct hclge_pf_res_cmd *req;
 619         struct hclge_desc desc;
 620         int ret;
 621
 622         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
 623         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 624         if (ret) {
 625                 dev_err(&hdev->pdev->dev,
 626                         "query pf resource failed %d.\n", ret);
 627                 return ret;
 628         }
 629
 630         req = (struct hclge_pf_res_cmd *)desc.data;
 631         hdev->num_tqps = __le16_to_cpu(req->tqp_num);
 632         hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
 633
 634         if (hnae3_dev_roce_supported(hdev)) {
 635                 hdev->roce_base_msix_offset =
 636                 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
 637                                 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
 638                 hdev->num_roce_msi =
 639                 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
 640                                 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
 641
 642                 /* PF should have NIC vectors and Roce vectors,
 643                  * NIC vectors are queued before Roce vectors.
 644                  */
 645                 hdev->num_msi = hdev->num_roce_msi  +
 646                                 hdev->roce_base_msix_offset;
 647         } else {
 648                 hdev->num_msi =
 649                 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
 650                                 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
 651         }
 652
 653         return 0;
 654 }
 655
 656 static int hclge_parse_speed(int speed_cmd, int *speed)
 657 {
 658         switch (speed_cmd) {
 659         case 6:
 660                 *speed = HCLGE_MAC_SPEED_10M;
 661                 break;
 662         case 7:
 663                 *speed = HCLGE_MAC_SPEED_100M;
 664                 break;
 665         case 0:
 666                 *speed = HCLGE_MAC_SPEED_1G;
 667                 break;
 668         case 1:
 669                 *speed = HCLGE_MAC_SPEED_10G;
 670                 break;
 671         case 2:
 672                 *speed = HCLGE_MAC_SPEED_25G;
 673                 break;
 674         case 3:
 675                 *speed = HCLGE_MAC_SPEED_40G;
 676                 break;
 677         case 4:
 678                 *speed = HCLGE_MAC_SPEED_50G;
 679                 break;
 680         case 5:
 681                 *speed = HCLGE_MAC_SPEED_100G;
 682                 break;
 683         default:
 684                 return -EINVAL;
 685         }
 686
 687         return 0;
 688 }
 689
 690 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
 691                                         u8 speed_ability)
 692 {
 693         unsigned long *supported = hdev->hw.mac.supported;
 694
 695         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
 696                 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
 697                         supported);
 698
 699         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
 700                 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
 701                         supported);
 702
 703         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
 704                 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
 705                         supported);
 706
 707         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
 708                 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
 709                         supported);
 710
 711         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
 712                 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
 713                         supported);
 714
 715         set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
 716         set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
 717 }
 718
 719 static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
 720 {
 721         u8 media_type = hdev->hw.mac.media_type;
 722
 723         if (media_type != HNAE3_MEDIA_TYPE_FIBER)
 724                 return;
 725
 726         hclge_parse_fiber_link_mode(hdev, speed_ability);
 727 }
 728
 729 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
 730 {
 731         struct hclge_cfg_param_cmd *req;
 732         u64 mac_addr_tmp_high;
 733         u64 mac_addr_tmp;
 734         int i;
 735
 736         req = (struct hclge_cfg_param_cmd *)desc[0].data;
 737
 738         /* get the configuration */
 739         cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
 740                                               HCLGE_CFG_VMDQ_M,
 741                                               HCLGE_CFG_VMDQ_S);
 742         cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
 743                                       HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
 744         cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
 745                                             HCLGE_CFG_TQP_DESC_N_M,
 746                                             HCLGE_CFG_TQP_DESC_N_S);
 747
 748         cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
 749                                         HCLGE_CFG_PHY_ADDR_M,
 750                                         HCLGE_CFG_PHY_ADDR_S);
 751         cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
 752                                           HCLGE_CFG_MEDIA_TP_M,
 753                                           HCLGE_CFG_MEDIA_TP_S);
 754         cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
 755                                           HCLGE_CFG_RX_BUF_LEN_M,
 756                                           HCLGE_CFG_RX_BUF_LEN_S);
 757         /* get mac_address */
 758         mac_addr_tmp = __le32_to_cpu(req->param[2]);
 759         mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
 760                                             HCLGE_CFG_MAC_ADDR_H_M,
 761                                             HCLGE_CFG_MAC_ADDR_H_S);
 762
 763         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
 764
 765         cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
 766                                              HCLGE_CFG_DEFAULT_SPEED_M,
 767                                              HCLGE_CFG_DEFAULT_SPEED_S);
 768         cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
 769                                             HCLGE_CFG_RSS_SIZE_M,
 770                                             HCLGE_CFG_RSS_SIZE_S);
 771
 772         for (i = 0; i < ETH_ALEN; i++)
 773                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
 774
 775         req = (struct hclge_cfg_param_cmd *)desc[1].data;
 776         cfg->numa_node_map = __le32_to_cpu(req->param[0]);
 777
 778         cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
 779                                              HCLGE_CFG_SPEED_ABILITY_M,
 780                                              HCLGE_CFG_SPEED_ABILITY_S);
 781         cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]),
 782                                          HCLGE_CFG_UMV_TBL_SPACE_M,
 783                                          HCLGE_CFG_UMV_TBL_SPACE_S);
 784         if (!cfg->umv_space)
 785                 cfg->umv_space = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
 786 }
 787
 788 /* hclge_get_cfg: query the static parameter from flash
 789  * @hdev: pointer to struct hclge_dev
 790  * @hcfg: the config structure to be getted
 791  */
 792 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
 793 {
 794         struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
 795         struct hclge_cfg_param_cmd *req;
 796         int i, ret;
 797
 798         for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
 799                 u32 offset = 0;
 800
 801                 req = (struct hclge_cfg_param_cmd *)desc[i].data;
 802                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
 803                                            true);
 804                 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
 805                                 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
 806                 /* Len should be united by 4 bytes when send to hardware */
 807                 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
 808                                 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
 809                 req->offset = cpu_to_le32(offset);
 810         }
 811
 812         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
 813         if (ret) {
 814                 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
 815                 return ret;
 816         }
 817
 818         hclge_parse_cfg(hcfg, desc);
 819
 820         return 0;
 821 }
 822
 823 static int hclge_get_cap(struct hclge_dev *hdev)
 824 {
 825         int ret;
 826
 827         ret = hclge_query_function_status(hdev);
 828         if (ret) {
 829                 dev_err(&hdev->pdev->dev,
 830                         "query function status error %d.\n", ret);
 831                 return ret;
 832         }
 833
 834         /* get pf resource */
 835         ret = hclge_query_pf_resource(hdev);
 836         if (ret)
 837                 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
 838
 839         return ret;
 840 }
 841
 842 static int hclge_configure(struct hclge_dev *hdev)
 843 {
 844         struct hclge_cfg cfg;
 845         int ret, i;
 846
 847         ret = hclge_get_cfg(hdev, &cfg);
 848         if (ret) {
 849                 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
 850                 return ret;
 851         }
 852
 853         hdev->num_vmdq_vport = cfg.vmdq_vport_num;
 854         hdev->base_tqp_pid = 0;
 855         hdev->rss_size_max = cfg.rss_size_max;
 856         hdev->rx_buf_len = cfg.rx_buf_len;
 857         ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
 858         hdev->hw.mac.media_type = cfg.media_type;
 859         hdev->hw.mac.phy_addr = cfg.phy_addr;
 860         hdev->num_desc = cfg.tqp_desc_num;
 861         hdev->tm_info.num_pg = 1;
 862         hdev->tc_max = cfg.tc_num;
 863         hdev->tm_info.hw_pfc_map = 0;
 864         hdev->wanted_umv_size = cfg.umv_space;
 865
 866         ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
 867         if (ret) {
 868                 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
 869                 return ret;
 870         }
 871
 872         hclge_parse_link_mode(hdev, cfg.speed_ability);
 873
 874         if ((hdev->tc_max > HNAE3_MAX_TC) ||
 875             (hdev->tc_max < 1)) {
 876                 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
 877                          hdev->tc_max);
 878                 hdev->tc_max = 1;
 879         }
 880
 881         /* Dev does not support DCB */
 882         if (!hnae3_dev_dcb_supported(hdev)) {
 883                 hdev->tc_max = 1;
 884                 hdev->pfc_max = 0;
 885         } else {
 886                 hdev->pfc_max = hdev->tc_max;
 887         }
 888
 889         hdev->tm_info.num_tc = hdev->tc_max;
 890
 891         /* Currently not support uncontiuous tc */
 892         for (i = 0; i < hdev->tm_info.num_tc; i++)
 893                 hnae3_set_bit(hdev->hw_tc_map, i, 1);
 894
 895         hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
 896
 897         return ret;
 898 }
 899
 900 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
 901                             int tso_mss_max)
 902 {
 903         struct hclge_cfg_tso_status_cmd *req;
 904         struct hclge_desc desc;
 905         u16 tso_mss;
 906
 907         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
 908
 909         req = (struct hclge_cfg_tso_status_cmd *)desc.data;
 910
 911         tso_mss = 0;
 912         hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
 913                         HCLGE_TSO_MSS_MIN_S, tso_mss_min);
 914         req->tso_mss_min = cpu_to_le16(tso_mss);
 915
 916         tso_mss = 0;
 917         hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
 918                         HCLGE_TSO_MSS_MIN_S, tso_mss_max);
 919         req->tso_mss_max = cpu_to_le16(tso_mss);
 920
 921         return hclge_cmd_send(&hdev->hw, &desc, 1);
 922 }
 923
 924 static int hclge_alloc_tqps(struct hclge_dev *hdev)
 925 {
 926         struct hclge_tqp *tqp;
 927         int i;
 928
 929         hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
 930                                   sizeof(struct hclge_tqp), GFP_KERNEL);
 931         if (!hdev->htqp)
 932                 return -ENOMEM;
 933
 934         tqp = hdev->htqp;
 935
 936         for (i = 0; i < hdev->num_tqps; i++) {
 937                 tqp->dev = &hdev->pdev->dev;
 938                 tqp->index = i;
 939
 940                 tqp->q.ae_algo = &ae_algo;
 941                 tqp->q.buf_size = hdev->rx_buf_len;
 942                 tqp->q.desc_num = hdev->num_desc;
 943                 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
 944                         i * HCLGE_TQP_REG_SIZE;
 945
 946                 tqp++;
 947         }
 948
 949         return 0;
 950 }
 951
 952 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
 953                                   u16 tqp_pid, u16 tqp_vid, bool is_pf)
 954 {
 955         struct hclge_tqp_map_cmd *req;
 956         struct hclge_desc desc;
 957         int ret;
 958
 959         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
 960
 961         req = (struct hclge_tqp_map_cmd *)desc.data;
 962         req->tqp_id = cpu_to_le16(tqp_pid);
 963         req->tqp_vf = func_id;
 964         req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
 965                         1 << HCLGE_TQP_MAP_EN_B;
 966         req->tqp_vid = cpu_to_le16(tqp_vid);
 967
 968         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 969         if (ret)
 970                 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
 971
 972         return ret;
 973 }
 974
 975 static int  hclge_assign_tqp(struct hclge_vport *vport)
 976 {
 977         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
 978         struct hclge_dev *hdev = vport->back;
 979         int i, alloced;
 980
 981         for (i = 0, alloced = 0; i < hdev->num_tqps &&
 982              alloced < kinfo->num_tqps; i++) {
 983                 if (!hdev->htqp[i].alloced) {
 984                         hdev->htqp[i].q.handle = &vport->nic;
 985                         hdev->htqp[i].q.tqp_index = alloced;
 986                         hdev->htqp[i].q.desc_num = kinfo->num_desc;
 987                         kinfo->tqp[alloced] = &hdev->htqp[i].q;
 988                         hdev->htqp[i].alloced = true;
 989                         alloced++;
 990                 }
 991         }
 992         vport->alloc_tqps = kinfo->num_tqps;
 993
 994         return 0;
 995 }
 996
 997 static int hclge_knic_setup(struct hclge_vport *vport,
 998                             u16 num_tqps, u16 num_desc)
 999 {
1000         struct hnae3_handle *nic = &vport->nic;
1001         struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1002         struct hclge_dev *hdev = vport->back;
1003         int i, ret;
1004
1005         kinfo->num_desc = num_desc;
1006         kinfo->rx_buf_len = hdev->rx_buf_len;
1007         kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1008         kinfo->rss_size
1009                 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1010         kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1011
1012         for (i = 0; i < HNAE3_MAX_TC; i++) {
1013                 if (hdev->hw_tc_map & BIT(i)) {
1014                         kinfo->tc_info[i].enable = true;
1015                         kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1016                         kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1017                         kinfo->tc_info[i].tc = i;
1018                 } else {
1019                         /* Set to default queue if TC is disable */
1020                         kinfo->tc_info[i].enable = false;
1021                         kinfo->tc_info[i].tqp_offset = 0;
1022                         kinfo->tc_info[i].tqp_count = 1;
1023                         kinfo->tc_info[i].tc = 0;
1024                 }
1025         }
1026
1027         kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1028                                   sizeof(struct hnae3_queue *), GFP_KERNEL);
1029         if (!kinfo->tqp)
1030                 return -ENOMEM;
1031
1032         ret = hclge_assign_tqp(vport);
1033         if (ret)
1034                 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1035
1036         return ret;
1037 }
1038
1039 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1040                                   struct hclge_vport *vport)
1041 {
1042         struct hnae3_handle *nic = &vport->nic;
1043         struct hnae3_knic_private_info *kinfo;
1044         u16 i;
1045
1046         kinfo = &nic->kinfo;
1047         for (i = 0; i < kinfo->num_tqps; i++) {
1048                 struct hclge_tqp *q =
1049                         container_of(kinfo->tqp[i], struct hclge_tqp, q);
1050                 bool is_pf;
1051                 int ret;
1052
1053                 is_pf = !(vport->vport_id);
1054                 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1055                                              i, is_pf);
1056                 if (ret)
1057                         return ret;
1058         }
1059
1060         return 0;
1061 }
1062
1063 static int hclge_map_tqp(struct hclge_dev *hdev)
1064 {
1065         struct hclge_vport *vport = hdev->vport;
1066         u16 i, num_vport;
1067
1068         num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1069         for (i = 0; i < num_vport; i++) {
1070                 int ret;
1071
1072                 ret = hclge_map_tqp_to_vport(hdev, vport);
1073                 if (ret)
1074                         return ret;
1075
1076                 vport++;
1077         }
1078
1079         return 0;
1080 }
1081
1082 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1083 {
1084         /* this would be initialized later */
1085 }
1086
1087 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1088 {
1089         struct hnae3_handle *nic = &vport->nic;
1090         struct hclge_dev *hdev = vport->back;
1091         int ret;
1092
1093         nic->pdev = hdev->pdev;
1094         nic->ae_algo = &ae_algo;
1095         nic->numa_node_mask = hdev->numa_node_mask;
1096
1097         if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1098                 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc);
1099                 if (ret) {
1100                         dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1101                                 ret);
1102                         return ret;
1103                 }
1104         } else {
1105                 hclge_unic_setup(vport, num_tqps);
1106         }
1107
1108         return 0;
1109 }
1110
1111 static int hclge_alloc_vport(struct hclge_dev *hdev)
1112 {
1113         struct pci_dev *pdev = hdev->pdev;
1114         struct hclge_vport *vport;
1115         u32 tqp_main_vport;
1116         u32 tqp_per_vport;
1117         int num_vport, i;
1118         int ret;
1119
1120         /* We need to alloc a vport for main NIC of PF */
1121         num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1122
1123         if (hdev->num_tqps < num_vport) {
1124                 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1125                         hdev->num_tqps, num_vport);
1126                 return -EINVAL;
1127         }
1128
1129         /* Alloc the same number of TQPs for every vport */
1130         tqp_per_vport = hdev->num_tqps / num_vport;
1131         tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1132
1133         vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1134                              GFP_KERNEL);
1135         if (!vport)
1136                 return -ENOMEM;
1137
1138         hdev->vport = vport;
1139         hdev->num_alloc_vport = num_vport;
1140
1141         if (IS_ENABLED(CONFIG_PCI_IOV))
1142                 hdev->num_alloc_vfs = hdev->num_req_vfs;
1143
1144         for (i = 0; i < num_vport; i++) {
1145                 vport->back = hdev;
1146                 vport->vport_id = i;
1147
1148                 if (i == 0)
1149                         ret = hclge_vport_setup(vport, tqp_main_vport);
1150                 else
1151                         ret = hclge_vport_setup(vport, tqp_per_vport);
1152                 if (ret) {
1153                         dev_err(&pdev->dev,
1154                                 "vport setup failed for vport %d, %d\n",
1155                                 i, ret);
1156                         return ret;
1157                 }
1158
1159                 vport++;
1160         }
1161
1162         return 0;
1163 }
1164
1165 static int  hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1166                                     struct hclge_pkt_buf_alloc *buf_alloc)
1167 {
1168 /* TX buffer size is unit by 128 byte */
1169 #define HCLGE_BUF_SIZE_UNIT_SHIFT       7
1170 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK    BIT(15)
1171         struct hclge_tx_buff_alloc_cmd *req;
1172         struct hclge_desc desc;
1173         int ret;
1174         u8 i;
1175
1176         req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1177
1178         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1179         for (i = 0; i < HCLGE_TC_NUM; i++) {
1180                 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1181
1182                 req->tx_pkt_buff[i] =
1183                         cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1184                                      HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1185         }
1186
1187         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1188         if (ret)
1189                 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1190                         ret);
1191
1192         return ret;
1193 }
1194
1195 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1196                                  struct hclge_pkt_buf_alloc *buf_alloc)
1197 {
1198         int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1199
1200         if (ret)
1201                 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
1202
1203         return ret;
1204 }
1205
1206 static int hclge_get_tc_num(struct hclge_dev *hdev)
1207 {
1208         int i, cnt = 0;
1209
1210         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1211                 if (hdev->hw_tc_map & BIT(i))
1212                         cnt++;
1213         return cnt;
1214 }
1215
1216 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1217 {
1218         int i, cnt = 0;
1219
1220         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1221                 if (hdev->hw_tc_map & BIT(i) &&
1222                     hdev->tm_info.hw_pfc_map & BIT(i))
1223                         cnt++;
1224         return cnt;
1225 }
1226
1227 /* Get the number of pfc enabled TCs, which have private buffer */
1228 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1229                                   struct hclge_pkt_buf_alloc *buf_alloc)
1230 {
1231         struct hclge_priv_buf *priv;
1232         int i, cnt = 0;
1233
1234         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1235                 priv = &buf_alloc->priv_buf[i];
1236                 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1237                     priv->enable)
1238                         cnt++;
1239         }
1240
1241         return cnt;
1242 }
1243
1244 /* Get the number of pfc disabled TCs, which have private buffer */
1245 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1246                                      struct hclge_pkt_buf_alloc *buf_alloc)
1247 {
1248         struct hclge_priv_buf *priv;
1249         int i, cnt = 0;
1250
1251         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1252                 priv = &buf_alloc->priv_buf[i];
1253                 if (hdev->hw_tc_map & BIT(i) &&
1254                     !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1255                     priv->enable)
1256                         cnt++;
1257         }
1258
1259         return cnt;
1260 }
1261
1262 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1263 {
1264         struct hclge_priv_buf *priv;
1265         u32 rx_priv = 0;
1266         int i;
1267
1268         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1269                 priv = &buf_alloc->priv_buf[i];
1270                 if (priv->enable)
1271                         rx_priv += priv->buf_size;
1272         }
1273         return rx_priv;
1274 }
1275
1276 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1277 {
1278         u32 i, total_tx_size = 0;
1279
1280         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1281                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1282
1283         return total_tx_size;
1284 }
1285
1286 static bool  hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1287                                 struct hclge_pkt_buf_alloc *buf_alloc,
1288                                 u32 rx_all)
1289 {
1290         u32 shared_buf_min, shared_buf_tc, shared_std;
1291         int tc_num, pfc_enable_num;
1292         u32 shared_buf;
1293         u32 rx_priv;
1294         int i;
1295
1296         tc_num = hclge_get_tc_num(hdev);
1297         pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1298
1299         if (hnae3_dev_dcb_supported(hdev))
1300                 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1301         else
1302                 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1303
1304         shared_buf_tc = pfc_enable_num * hdev->mps +
1305                         (tc_num - pfc_enable_num) * hdev->mps / 2 +
1306                         hdev->mps;
1307         shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1308
1309         rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
1310         if (rx_all <= rx_priv + shared_std)
1311                 return false;
1312
1313         shared_buf = rx_all - rx_priv;
1314         buf_alloc->s_buf.buf_size = shared_buf;
1315         buf_alloc->s_buf.self.high = shared_buf;
1316         buf_alloc->s_buf.self.low =  2 * hdev->mps;
1317
1318         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1319                 if ((hdev->hw_tc_map & BIT(i)) &&
1320                     (hdev->tm_info.hw_pfc_map & BIT(i))) {
1321                         buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1322                         buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
1323                 } else {
1324                         buf_alloc->s_buf.tc_thrd[i].low = 0;
1325                         buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
1326                 }
1327         }
1328
1329         return true;
1330 }
1331
1332 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1333                                 struct hclge_pkt_buf_alloc *buf_alloc)
1334 {
1335         u32 i, total_size;
1336
1337         total_size = hdev->pkt_buf_size;
1338
1339         /* alloc tx buffer for all enabled tc */
1340         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1341                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1342
1343                 if (total_size < HCLGE_DEFAULT_TX_BUF)
1344                         return -ENOMEM;
1345
1346                 if (hdev->hw_tc_map & BIT(i))
1347                         priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1348                 else
1349                         priv->tx_buf_size = 0;
1350
1351                 total_size -= priv->tx_buf_size;
1352         }
1353
1354         return 0;
1355 }
1356
1357 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1358  * @hdev: pointer to struct hclge_dev
1359  * @buf_alloc: pointer to buffer calculation data
1360  * @return: 0: calculate sucessful, negative: fail
1361  */
1362 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1363                                 struct hclge_pkt_buf_alloc *buf_alloc)
1364 {
1365 #define HCLGE_BUF_SIZE_UNIT     128
1366         u32 rx_all = hdev->pkt_buf_size, aligned_mps;
1367         int no_pfc_priv_num, pfc_priv_num;
1368         struct hclge_priv_buf *priv;
1369         int i;
1370
1371         aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT);
1372         rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
1373
1374         /* When DCB is not supported, rx private
1375          * buffer is not allocated.
1376          */
1377         if (!hnae3_dev_dcb_supported(hdev)) {
1378                 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1379                         return -ENOMEM;
1380
1381                 return 0;
1382         }
1383
1384         /* step 1, try to alloc private buffer for all enabled tc */
1385         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1386                 priv = &buf_alloc->priv_buf[i];
1387                 if (hdev->hw_tc_map & BIT(i)) {
1388                         priv->enable = 1;
1389                         if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1390                                 priv->wl.low = aligned_mps;
1391                                 priv->wl.high = priv->wl.low + aligned_mps;
1392                                 priv->buf_size = priv->wl.high +
1393                                                 HCLGE_DEFAULT_DV;
1394                         } else {
1395                                 priv->wl.low = 0;
1396                                 priv->wl.high = 2 * aligned_mps;
1397                                 priv->buf_size = priv->wl.high;
1398                         }
1399                 } else {
1400                         priv->enable = 0;
1401                         priv->wl.low = 0;
1402                         priv->wl.high = 0;
1403                         priv->buf_size = 0;
1404                 }
1405         }
1406
1407         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1408                 return 0;
1409
1410         /* step 2, try to decrease the buffer size of
1411          * no pfc TC's private buffer
1412          */
1413         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1414                 priv = &buf_alloc->priv_buf[i];
1415
1416                 priv->enable = 0;
1417                 priv->wl.low = 0;
1418                 priv->wl.high = 0;
1419                 priv->buf_size = 0;
1420
1421                 if (!(hdev->hw_tc_map & BIT(i)))
1422                         continue;
1423
1424                 priv->enable = 1;
1425
1426                 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1427                         priv->wl.low = 128;
1428                         priv->wl.high = priv->wl.low + aligned_mps;
1429                         priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1430                 } else {
1431                         priv->wl.low = 0;
1432                         priv->wl.high = aligned_mps;
1433                         priv->buf_size = priv->wl.high;
1434                 }
1435         }
1436
1437         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1438                 return 0;
1439
1440         /* step 3, try to reduce the number of pfc disabled TCs,
1441          * which have private buffer
1442          */
1443         /* get the total no pfc enable TC number, which have private buffer */
1444         no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
1445
1446         /* let the last to be cleared first */
1447         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1448                 priv = &buf_alloc->priv_buf[i];
1449
1450                 if (hdev->hw_tc_map & BIT(i) &&
1451                     !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1452                         /* Clear the no pfc TC private buffer */
1453                         priv->wl.low = 0;
1454                         priv->wl.high = 0;
1455                         priv->buf_size = 0;
1456                         priv->enable = 0;
1457                         no_pfc_priv_num--;
1458                 }
1459
1460                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1461                     no_pfc_priv_num == 0)
1462                         break;
1463         }
1464
1465         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1466                 return 0;
1467
1468         /* step 4, try to reduce the number of pfc enabled TCs
1469          * which have private buffer.
1470          */
1471         pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
1472
1473         /* let the last to be cleared first */
1474         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1475                 priv = &buf_alloc->priv_buf[i];
1476
1477                 if (hdev->hw_tc_map & BIT(i) &&
1478                     hdev->tm_info.hw_pfc_map & BIT(i)) {
1479                         /* Reduce the number of pfc TC with private buffer */
1480                         priv->wl.low = 0;
1481                         priv->enable = 0;
1482                         priv->wl.high = 0;
1483                         priv->buf_size = 0;
1484                         pfc_priv_num--;
1485                 }
1486
1487                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1488                     pfc_priv_num == 0)
1489                         break;
1490         }
1491         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1492                 return 0;
1493
1494         return -ENOMEM;
1495 }
1496
1497 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1498                                    struct hclge_pkt_buf_alloc *buf_alloc)
1499 {
1500         struct hclge_rx_priv_buff_cmd *req;
1501         struct hclge_desc desc;
1502         int ret;
1503         int i;
1504
1505         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1506         req = (struct hclge_rx_priv_buff_cmd *)desc.data;
1507
1508         /* Alloc private buffer TCs */
1509         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1510                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1511
1512                 req->buf_num[i] =
1513                         cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1514                 req->buf_num[i] |=
1515                         cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
1516         }
1517
1518         req->shared_buf =
1519                 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
1520                             (1 << HCLGE_TC0_PRI_BUF_EN_B));
1521
1522         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1523         if (ret)
1524                 dev_err(&hdev->pdev->dev,
1525                         "rx private buffer alloc cmd failed %d\n", ret);
1526
1527         return ret;
1528 }
1529
1530 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1531                                    struct hclge_pkt_buf_alloc *buf_alloc)
1532 {
1533         struct hclge_rx_priv_wl_buf *req;
1534         struct hclge_priv_buf *priv;
1535         struct hclge_desc desc[2];
1536         int i, j;
1537         int ret;
1538
1539         for (i = 0; i < 2; i++) {
1540                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1541                                            false);
1542                 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1543
1544                 /* The first descriptor set the NEXT bit to 1 */
1545                 if (i == 0)
1546                         desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1547                 else
1548                         desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1549
1550                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1551                         u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1552
1553                         priv = &buf_alloc->priv_buf[idx];
1554                         req->tc_wl[j].high =
1555                                 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1556                         req->tc_wl[j].high |=
1557                                 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1558                         req->tc_wl[j].low =
1559                                 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1560                         req->tc_wl[j].low |=
1561                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1562                 }
1563         }
1564
1565         /* Send 2 descriptor at one time */
1566         ret = hclge_cmd_send(&hdev->hw, desc, 2);
1567         if (ret)
1568                 dev_err(&hdev->pdev->dev,
1569                         "rx private waterline config cmd failed %d\n",
1570                         ret);
1571         return ret;
1572 }
1573
1574 static int hclge_common_thrd_config(struct hclge_dev *hdev,
1575                                     struct hclge_pkt_buf_alloc *buf_alloc)
1576 {
1577         struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
1578         struct hclge_rx_com_thrd *req;
1579         struct hclge_desc desc[2];
1580         struct hclge_tc_thrd *tc;
1581         int i, j;
1582         int ret;
1583
1584         for (i = 0; i < 2; i++) {
1585                 hclge_cmd_setup_basic_desc(&desc[i],
1586                                            HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1587                 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1588
1589                 /* The first descriptor set the NEXT bit to 1 */
1590                 if (i == 0)
1591                         desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1592                 else
1593                         desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1594
1595                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1596                         tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1597
1598                         req->com_thrd[j].high =
1599                                 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1600                         req->com_thrd[j].high |=
1601                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1602                         req->com_thrd[j].low =
1603                                 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1604                         req->com_thrd[j].low |=
1605                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1606                 }
1607         }
1608
1609         /* Send 2 descriptors at one time */
1610         ret = hclge_cmd_send(&hdev->hw, desc, 2);
1611         if (ret)
1612                 dev_err(&hdev->pdev->dev,
1613                         "common threshold config cmd failed %d\n", ret);
1614         return ret;
1615 }
1616
1617 static int hclge_common_wl_config(struct hclge_dev *hdev,
1618                                   struct hclge_pkt_buf_alloc *buf_alloc)
1619 {
1620         struct hclge_shared_buf *buf = &buf_alloc->s_buf;
1621         struct hclge_rx_com_wl *req;
1622         struct hclge_desc desc;
1623         int ret;
1624
1625         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1626
1627         req = (struct hclge_rx_com_wl *)desc.data;
1628         req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1629         req->com_wl.high |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1630
1631         req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1632         req->com_wl.low |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1633
1634         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1635         if (ret)
1636                 dev_err(&hdev->pdev->dev,
1637                         "common waterline config cmd failed %d\n", ret);
1638
1639         return ret;
1640 }
1641
1642 int hclge_buffer_alloc(struct hclge_dev *hdev)
1643 {
1644         struct hclge_pkt_buf_alloc *pkt_buf;
1645         int ret;
1646
1647         pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1648         if (!pkt_buf)
1649                 return -ENOMEM;
1650
1651         ret = hclge_tx_buffer_calc(hdev, pkt_buf);
1652         if (ret) {
1653                 dev_err(&hdev->pdev->dev,
1654                         "could not calc tx buffer size for all TCs %d\n", ret);
1655                 goto out;
1656         }
1657
1658         ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
1659         if (ret) {
1660                 dev_err(&hdev->pdev->dev,
1661                         "could not alloc tx buffers %d\n", ret);
1662                 goto out;
1663         }
1664
1665         ret = hclge_rx_buffer_calc(hdev, pkt_buf);
1666         if (ret) {
1667                 dev_err(&hdev->pdev->dev,
1668                         "could not calc rx priv buffer size for all TCs %d\n",
1669                         ret);
1670                 goto out;
1671         }
1672
1673         ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
1674         if (ret) {
1675                 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1676                         ret);
1677                 goto out;
1678         }
1679
1680         if (hnae3_dev_dcb_supported(hdev)) {
1681                 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
1682                 if (ret) {
1683                         dev_err(&hdev->pdev->dev,
1684                                 "could not configure rx private waterline %d\n",
1685                                 ret);
1686                         goto out;
1687                 }
1688
1689                 ret = hclge_common_thrd_config(hdev, pkt_buf);
1690                 if (ret) {
1691                         dev_err(&hdev->pdev->dev,
1692                                 "could not configure common threshold %d\n",
1693                                 ret);
1694                         goto out;
1695                 }
1696         }
1697
1698         ret = hclge_common_wl_config(hdev, pkt_buf);
1699         if (ret)
1700                 dev_err(&hdev->pdev->dev,
1701                         "could not configure common waterline %d\n", ret);
1702
1703 out:
1704         kfree(pkt_buf);
1705         return ret;
1706 }
1707
1708 static int hclge_init_roce_base_info(struct hclge_vport *vport)
1709 {
1710         struct hnae3_handle *roce = &vport->roce;
1711         struct hnae3_handle *nic = &vport->nic;
1712
1713         roce->rinfo.num_vectors = vport->back->num_roce_msi;
1714
1715         if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1716             vport->back->num_msi_left == 0)
1717                 return -EINVAL;
1718
1719         roce->rinfo.base_vector = vport->back->roce_base_vector;
1720
1721         roce->rinfo.netdev = nic->kinfo.netdev;
1722         roce->rinfo.roce_io_base = vport->back->hw.io_base;
1723
1724         roce->pdev = nic->pdev;
1725         roce->ae_algo = nic->ae_algo;
1726         roce->numa_node_mask = nic->numa_node_mask;
1727
1728         return 0;
1729 }
1730
1731 static int hclge_init_msi(struct hclge_dev *hdev)
1732 {
1733         struct pci_dev *pdev = hdev->pdev;
1734         int vectors;
1735         int i;
1736
1737         vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1738                                         PCI_IRQ_MSI | PCI_IRQ_MSIX);
1739         if (vectors < 0) {
1740                 dev_err(&pdev->dev,
1741                         "failed(%d) to allocate MSI/MSI-X vectors\n",
1742                         vectors);
1743                 return vectors;
1744         }
1745         if (vectors < hdev->num_msi)
1746                 dev_warn(&hdev->pdev->dev,
1747                          "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1748                          hdev->num_msi, vectors);
1749
1750         hdev->num_msi = vectors;
1751         hdev->num_msi_left = vectors;
1752         hdev->base_msi_vector = pdev->irq;
1753         hdev->roce_base_vector = hdev->base_msi_vector +
1754                                 hdev->roce_base_msix_offset;
1755
1756         hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1757                                            sizeof(u16), GFP_KERNEL);
1758         if (!hdev->vector_status) {
1759                 pci_free_irq_vectors(pdev);
1760                 return -ENOMEM;
1761         }
1762
1763         for (i = 0; i < hdev->num_msi; i++)
1764                 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1765
1766         hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1767                                         sizeof(int), GFP_KERNEL);
1768         if (!hdev->vector_irq) {
1769                 pci_free_irq_vectors(pdev);
1770                 return -ENOMEM;
1771         }
1772
1773         return 0;
1774 }
1775
1776 static u8 hclge_check_speed_dup(u8 duplex, int speed)
1777 {
1778
1779         if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
1780                 duplex = HCLGE_MAC_FULL;
1781
1782         return duplex;
1783 }
1784
1785 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
1786                                       u8 duplex)
1787 {
1788         struct hclge_config_mac_speed_dup_cmd *req;
1789         struct hclge_desc desc;
1790         int ret;
1791
1792         req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
1793
1794         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
1795
1796         hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
1797
1798         switch (speed) {
1799         case HCLGE_MAC_SPEED_10M:
1800                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1801                                 HCLGE_CFG_SPEED_S, 6);
1802                 break;
1803         case HCLGE_MAC_SPEED_100M:
1804                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1805                                 HCLGE_CFG_SPEED_S, 7);
1806                 break;
1807         case HCLGE_MAC_SPEED_1G:
1808                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1809                                 HCLGE_CFG_SPEED_S, 0);
1810                 break;
1811         case HCLGE_MAC_SPEED_10G:
1812                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1813                                 HCLGE_CFG_SPEED_S, 1);
1814                 break;
1815         case HCLGE_MAC_SPEED_25G:
1816                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1817                                 HCLGE_CFG_SPEED_S, 2);
1818                 break;
1819         case HCLGE_MAC_SPEED_40G:
1820                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1821                                 HCLGE_CFG_SPEED_S, 3);
1822                 break;
1823         case HCLGE_MAC_SPEED_50G:
1824                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1825                                 HCLGE_CFG_SPEED_S, 4);
1826                 break;
1827         case HCLGE_MAC_SPEED_100G:
1828                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1829                                 HCLGE_CFG_SPEED_S, 5);
1830                 break;
1831         default:
1832                 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
1833                 return -EINVAL;
1834         }
1835
1836         hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1837                       1);
1838
1839         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1840         if (ret) {
1841                 dev_err(&hdev->pdev->dev,
1842                         "mac speed/duplex config cmd failed %d.\n", ret);
1843                 return ret;
1844         }
1845
1846         return 0;
1847 }
1848
1849 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1850 {
1851         int ret;
1852
1853         duplex = hclge_check_speed_dup(duplex, speed);
1854         if (hdev->hw.mac.speed == speed && hdev->hw.mac.duplex == duplex)
1855                 return 0;
1856
1857         ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);
1858         if (ret)
1859                 return ret;
1860
1861         hdev->hw.mac.speed = speed;
1862         hdev->hw.mac.duplex = duplex;
1863
1864         return 0;
1865 }
1866
1867 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
1868                                      u8 duplex)
1869 {
1870         struct hclge_vport *vport = hclge_get_vport(handle);
1871         struct hclge_dev *hdev = vport->back;
1872
1873         return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
1874 }
1875
1876 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
1877                                         u8 *duplex)
1878 {
1879         struct hclge_query_an_speed_dup_cmd *req;
1880         struct hclge_desc desc;
1881         int speed_tmp;
1882         int ret;
1883
1884         req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
1885
1886         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
1887         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1888         if (ret) {
1889                 dev_err(&hdev->pdev->dev,
1890                         "mac speed/autoneg/duplex query cmd failed %d\n",
1891                         ret);
1892                 return ret;
1893         }
1894
1895         *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
1896         speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
1897                                     HCLGE_QUERY_SPEED_S);
1898
1899         ret = hclge_parse_speed(speed_tmp, speed);
1900         if (ret)
1901                 dev_err(&hdev->pdev->dev,
1902                         "could not parse speed(=%d), %d\n", speed_tmp, ret);
1903
1904         return ret;
1905 }
1906
1907 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
1908 {
1909         struct hclge_config_auto_neg_cmd *req;
1910         struct hclge_desc desc;
1911         u32 flag = 0;
1912         int ret;
1913
1914         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
1915
1916         req = (struct hclge_config_auto_neg_cmd *)desc.data;
1917         hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
1918         req->cfg_an_cmd_flag = cpu_to_le32(flag);
1919
1920         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1921         if (ret)
1922                 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
1923                         ret);
1924
1925         return ret;
1926 }
1927
1928 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
1929 {
1930         struct hclge_vport *vport = hclge_get_vport(handle);
1931         struct hclge_dev *hdev = vport->back;
1932
1933         return hclge_set_autoneg_en(hdev, enable);
1934 }
1935
1936 static int hclge_get_autoneg(struct hnae3_handle *handle)
1937 {
1938         struct hclge_vport *vport = hclge_get_vport(handle);
1939         struct hclge_dev *hdev = vport->back;
1940         struct phy_device *phydev = hdev->hw.mac.phydev;
1941
1942         if (phydev)
1943                 return phydev->autoneg;
1944
1945         return hdev->hw.mac.autoneg;
1946 }
1947
1948 static int hclge_mac_init(struct hclge_dev *hdev)
1949 {
1950         struct hnae3_handle *handle = &hdev->vport[0].nic;
1951         struct net_device *netdev = handle->kinfo.netdev;
1952         struct hclge_mac *mac = &hdev->hw.mac;
1953         int mtu;
1954         int ret;
1955
1956         hdev->hw.mac.duplex = HCLGE_MAC_FULL;
1957         ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
1958                                          hdev->hw.mac.duplex);
1959         if (ret) {
1960                 dev_err(&hdev->pdev->dev,
1961                         "Config mac speed dup fail ret=%d\n", ret);
1962                 return ret;
1963         }
1964
1965         mac->link = 0;
1966
1967         if (netdev)
1968                 mtu = netdev->mtu;
1969         else
1970                 mtu = ETH_DATA_LEN;
1971
1972         ret = hclge_set_mtu(handle, mtu);
1973         if (ret)
1974                 dev_err(&hdev->pdev->dev,
1975                         "set mtu failed ret=%d\n", ret);
1976
1977         return ret;
1978 }
1979
1980 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
1981 {
1982         if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
1983                 schedule_work(&hdev->mbx_service_task);
1984 }
1985
1986 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
1987 {
1988         if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
1989                 schedule_work(&hdev->rst_service_task);
1990 }
1991
1992 static void hclge_task_schedule(struct hclge_dev *hdev)
1993 {
1994         if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
1995             !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
1996             !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
1997                 (void)schedule_work(&hdev->service_task);
1998 }
1999
2000 static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2001 {
2002         struct hclge_link_status_cmd *req;
2003         struct hclge_desc desc;
2004         int link_status;
2005         int ret;
2006
2007         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2008         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2009         if (ret) {
2010                 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2011                         ret);
2012                 return ret;
2013         }
2014
2015         req = (struct hclge_link_status_cmd *)desc.data;
2016         link_status = req->status & HCLGE_LINK_STATUS_UP_M;
2017
2018         return !!link_status;
2019 }
2020
2021 static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2022 {
2023         int mac_state;
2024         int link_stat;
2025
2026         if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
2027                 return 0;
2028
2029         mac_state = hclge_get_mac_link_status(hdev);
2030
2031         if (hdev->hw.mac.phydev) {
2032                 if (hdev->hw.mac.phydev->state == PHY_RUNNING)
2033                         link_stat = mac_state &
2034                                 hdev->hw.mac.phydev->link;
2035                 else
2036                         link_stat = 0;
2037
2038         } else {
2039                 link_stat = mac_state;
2040         }
2041
2042         return !!link_stat;
2043 }
2044
2045 static void hclge_update_link_status(struct hclge_dev *hdev)
2046 {
2047         struct hnae3_client *client = hdev->nic_client;
2048         struct hnae3_handle *handle;
2049         int state;
2050         int i;
2051
2052         if (!client)
2053                 return;
2054         state = hclge_get_mac_phy_link(hdev);
2055         if (state != hdev->hw.mac.link) {
2056                 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2057                         handle = &hdev->vport[i].nic;
2058                         client->ops->link_status_change(handle, state);
2059                 }
2060                 hdev->hw.mac.link = state;
2061         }
2062 }
2063
2064 static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2065 {
2066         struct hclge_mac mac = hdev->hw.mac;
2067         u8 duplex;
2068         int speed;
2069         int ret;
2070
2071         /* get the speed and duplex as autoneg'result from mac cmd when phy
2072          * doesn't exit.
2073          */
2074         if (mac.phydev || !mac.autoneg)
2075                 return 0;
2076
2077         ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2078         if (ret) {
2079                 dev_err(&hdev->pdev->dev,
2080                         "mac autoneg/speed/duplex query failed %d\n", ret);
2081                 return ret;
2082         }
2083
2084         ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2085         if (ret) {
2086                 dev_err(&hdev->pdev->dev,
2087                         "mac speed/duplex config failed %d\n", ret);
2088                 return ret;
2089         }
2090
2091         return 0;
2092 }
2093
2094 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2095 {
2096         struct hclge_vport *vport = hclge_get_vport(handle);
2097         struct hclge_dev *hdev = vport->back;
2098
2099         return hclge_update_speed_duplex(hdev);
2100 }
2101
2102 static int hclge_get_status(struct hnae3_handle *handle)
2103 {
2104         struct hclge_vport *vport = hclge_get_vport(handle);
2105         struct hclge_dev *hdev = vport->back;
2106
2107         hclge_update_link_status(hdev);
2108
2109         return hdev->hw.mac.link;
2110 }
2111
2112 static void hclge_service_timer(struct timer_list *t)
2113 {
2114         struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
2115
2116         mod_timer(&hdev->service_timer, jiffies + HZ);
2117         hdev->hw_stats.stats_timer++;
2118         hclge_task_schedule(hdev);
2119 }
2120
2121 static void hclge_service_complete(struct hclge_dev *hdev)
2122 {
2123         WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2124
2125         /* Flush memory before next watchdog */
2126         smp_mb__before_atomic();
2127         clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2128 }
2129
2130 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2131 {
2132         u32 rst_src_reg;
2133         u32 cmdq_src_reg;
2134
2135         /* fetch the events from their corresponding regs */
2136         rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
2137         cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2138
2139         /* Assumption: If by any chance reset and mailbox events are reported
2140          * together then we will only process reset event in this go and will
2141          * defer the processing of the mailbox events. Since, we would have not
2142          * cleared RX CMDQ event this time we would receive again another
2143          * interrupt from H/W just for the mailbox.
2144          */
2145
2146         /* check for vector0 reset event sources */
2147         if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2148                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2149                 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2150                 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2151                 return HCLGE_VECTOR0_EVENT_RST;
2152         }
2153
2154         if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2155                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2156                 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2157                 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2158                 return HCLGE_VECTOR0_EVENT_RST;
2159         }
2160
2161         if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2162                 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2163                 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2164                 return HCLGE_VECTOR0_EVENT_RST;
2165         }
2166
2167         /* check for vector0 mailbox(=CMDQ RX) event source */
2168         if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2169                 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2170                 *clearval = cmdq_src_reg;
2171                 return HCLGE_VECTOR0_EVENT_MBX;
2172         }
2173
2174         return HCLGE_VECTOR0_EVENT_OTHER;
2175 }
2176
2177 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2178                                     u32 regclr)
2179 {
2180         switch (event_type) {
2181         case HCLGE_VECTOR0_EVENT_RST:
2182                 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2183                 break;
2184         case HCLGE_VECTOR0_EVENT_MBX:
2185                 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2186                 break;
2187         default:
2188                 break;
2189         }
2190 }
2191
2192 static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2193 {
2194         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2195                                 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2196                                 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2197                                 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2198         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2199 }
2200
2201 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2202 {
2203         writel(enable ? 1 : 0, vector->addr);
2204 }
2205
2206 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2207 {
2208         struct hclge_dev *hdev = data;
2209         u32 event_cause;
2210         u32 clearval;
2211
2212         hclge_enable_vector(&hdev->misc_vector, false);
2213         event_cause = hclge_check_event_cause(hdev, &clearval);
2214
2215         /* vector 0 interrupt is shared with reset and mailbox source events.*/
2216         switch (event_cause) {
2217         case HCLGE_VECTOR0_EVENT_RST:
2218                 hclge_reset_task_schedule(hdev);
2219                 break;
2220         case HCLGE_VECTOR0_EVENT_MBX:
2221                 /* If we are here then,
2222                  * 1. Either we are not handling any mbx task and we are not
2223                  *    scheduled as well
2224                  *                        OR
2225                  * 2. We could be handling a mbx task but nothing more is
2226                  *    scheduled.
2227                  * In both cases, we should schedule mbx task as there are more
2228                  * mbx messages reported by this interrupt.
2229                  */
2230                 hclge_mbx_task_schedule(hdev);
2231                 break;
2232         default:
2233                 dev_warn(&hdev->pdev->dev,
2234                          "received unknown or unhandled event of vector0\n");
2235                 break;
2236         }
2237
2238         /* clear the source of interrupt if it is not cause by reset */
2239         if (event_cause == HCLGE_VECTOR0_EVENT_MBX) {
2240                 hclge_clear_event_cause(hdev, event_cause, clearval);
2241                 hclge_enable_vector(&hdev->misc_vector, true);
2242         }
2243
2244         return IRQ_HANDLED;
2245 }
2246
2247 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2248 {
2249         if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2250                 dev_warn(&hdev->pdev->dev,
2251                          "vector(vector_id %d) has been freed.\n", vector_id);
2252                 return;
2253         }
2254
2255         hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2256         hdev->num_msi_left += 1;
2257         hdev->num_msi_used -= 1;
2258 }
2259
2260 static void hclge_get_misc_vector(struct hclge_dev *hdev)
2261 {
2262         struct hclge_misc_vector *vector = &hdev->misc_vector;
2263
2264         vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2265
2266         vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2267         hdev->vector_status[0] = 0;
2268
2269         hdev->num_msi_left -= 1;
2270         hdev->num_msi_used += 1;
2271 }
2272
2273 static int hclge_misc_irq_init(struct hclge_dev *hdev)
2274 {
2275         int ret;
2276
2277         hclge_get_misc_vector(hdev);
2278
2279         /* this would be explicitly freed in the end */
2280         ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2281                           0, "hclge_misc", hdev);
2282         if (ret) {
2283                 hclge_free_vector(hdev, 0);
2284                 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2285                         hdev->misc_vector.vector_irq);
2286         }
2287
2288         return ret;
2289 }
2290
2291 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2292 {
2293         free_irq(hdev->misc_vector.vector_irq, hdev);
2294         hclge_free_vector(hdev, 0);
2295 }
2296
2297 static int hclge_notify_client(struct hclge_dev *hdev,
2298                                enum hnae3_reset_notify_type type)
2299 {
2300         struct hnae3_client *client = hdev->nic_client;
2301         u16 i;
2302
2303         if (!client->ops->reset_notify)
2304                 return -EOPNOTSUPP;
2305
2306         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2307                 struct hnae3_handle *handle = &hdev->vport[i].nic;
2308                 int ret;
2309
2310                 ret = client->ops->reset_notify(handle, type);
2311                 if (ret)
2312                         return ret;
2313         }
2314
2315         return 0;
2316 }
2317
2318 static int hclge_reset_wait(struct hclge_dev *hdev)
2319 {
2320 #define HCLGE_RESET_WATI_MS     100
2321 #define HCLGE_RESET_WAIT_CNT    5
2322         u32 val, reg, reg_bit;
2323         u32 cnt = 0;
2324
2325         switch (hdev->reset_type) {
2326         case HNAE3_GLOBAL_RESET:
2327                 reg = HCLGE_GLOBAL_RESET_REG;
2328                 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2329                 break;
2330         case HNAE3_CORE_RESET:
2331                 reg = HCLGE_GLOBAL_RESET_REG;
2332                 reg_bit = HCLGE_CORE_RESET_BIT;
2333                 break;
2334         case HNAE3_FUNC_RESET:
2335                 reg = HCLGE_FUN_RST_ING;
2336                 reg_bit = HCLGE_FUN_RST_ING_B;
2337                 break;
2338         default:
2339                 dev_err(&hdev->pdev->dev,
2340                         "Wait for unsupported reset type: %d\n",
2341                         hdev->reset_type);
2342                 return -EINVAL;
2343         }
2344
2345         val = hclge_read_dev(&hdev->hw, reg);
2346         while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2347                 msleep(HCLGE_RESET_WATI_MS);
2348                 val = hclge_read_dev(&hdev->hw, reg);
2349                 cnt++;
2350         }
2351
2352         if (cnt >= HCLGE_RESET_WAIT_CNT) {
2353                 dev_warn(&hdev->pdev->dev,
2354                          "Wait for reset timeout: %d\n", hdev->reset_type);
2355                 return -EBUSY;
2356         }
2357
2358         return 0;
2359 }
2360
2361 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2362 {
2363         struct hclge_desc desc;
2364         struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2365         int ret;
2366
2367         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2368         hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2369         req->fun_reset_vfid = func_id;
2370
2371         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2372         if (ret)
2373                 dev_err(&hdev->pdev->dev,
2374                         "send function reset cmd fail, status =%d\n", ret);
2375
2376         return ret;
2377 }
2378
2379 static void hclge_do_reset(struct hclge_dev *hdev)
2380 {
2381         struct pci_dev *pdev = hdev->pdev;
2382         u32 val;
2383
2384         switch (hdev->reset_type) {
2385         case HNAE3_GLOBAL_RESET:
2386                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2387                 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2388                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2389                 dev_info(&pdev->dev, "Global Reset requested\n");
2390                 break;
2391         case HNAE3_CORE_RESET:
2392                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2393                 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2394                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2395                 dev_info(&pdev->dev, "Core Reset requested\n");
2396                 break;
2397         case HNAE3_FUNC_RESET:
2398                 dev_info(&pdev->dev, "PF Reset requested\n");
2399                 hclge_func_reset_cmd(hdev, 0);
2400                 /* schedule again to check later */
2401                 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2402                 hclge_reset_task_schedule(hdev);
2403                 break;
2404         default:
2405                 dev_warn(&pdev->dev,
2406                          "Unsupported reset type: %d\n", hdev->reset_type);
2407                 break;
2408         }
2409 }
2410
2411 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2412                                                    unsigned long *addr)
2413 {
2414         enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2415
2416         /* return the highest priority reset level amongst all */
2417         if (test_bit(HNAE3_IMP_RESET, addr)) {
2418                 rst_level = HNAE3_IMP_RESET;
2419                 clear_bit(HNAE3_IMP_RESET, addr);
2420                 clear_bit(HNAE3_GLOBAL_RESET, addr);
2421                 clear_bit(HNAE3_CORE_RESET, addr);
2422                 clear_bit(HNAE3_FUNC_RESET, addr);
2423         } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) {
2424                 rst_level = HNAE3_GLOBAL_RESET;
2425                 clear_bit(HNAE3_GLOBAL_RESET, addr);
2426                 clear_bit(HNAE3_CORE_RESET, addr);
2427                 clear_bit(HNAE3_FUNC_RESET, addr);
2428         } else if (test_bit(HNAE3_CORE_RESET, addr)) {
2429                 rst_level = HNAE3_CORE_RESET;
2430                 clear_bit(HNAE3_CORE_RESET, addr);
2431                 clear_bit(HNAE3_FUNC_RESET, addr);
2432         } else if (test_bit(HNAE3_FUNC_RESET, addr)) {
2433                 rst_level = HNAE3_FUNC_RESET;
2434                 clear_bit(HNAE3_FUNC_RESET, addr);
2435         }
2436
2437         return rst_level;
2438 }
2439
2440 static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2441 {
2442         u32 clearval = 0;
2443
2444         switch (hdev->reset_type) {
2445         case HNAE3_IMP_RESET:
2446                 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2447                 break;
2448         case HNAE3_GLOBAL_RESET:
2449                 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2450                 break;
2451         case HNAE3_CORE_RESET:
2452                 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2453                 break;
2454         default:
2455                 break;
2456         }
2457
2458         if (!clearval)
2459                 return;
2460
2461         hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2462         hclge_enable_vector(&hdev->misc_vector, true);
2463 }
2464
2465 static void hclge_reset(struct hclge_dev *hdev)
2466 {
2467         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
2468         struct hnae3_handle *handle;
2469
2470         /* Initialize ae_dev reset status as well, in case enet layer wants to
2471          * know if device is undergoing reset
2472          */
2473         ae_dev->reset_type = hdev->reset_type;
2474         hdev->reset_count++;
2475         /* perform reset of the stack & ae device for a client */
2476         handle = &hdev->vport[0].nic;
2477         rtnl_lock();
2478         hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2479         rtnl_unlock();
2480
2481         if (!hclge_reset_wait(hdev)) {
2482                 rtnl_lock();
2483                 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2484                 hclge_reset_ae_dev(hdev->ae_dev);
2485                 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2486
2487                 hclge_clear_reset_cause(hdev);
2488         } else {
2489                 rtnl_lock();
2490                 /* schedule again to check pending resets later */
2491                 set_bit(hdev->reset_type, &hdev->reset_pending);
2492                 hclge_reset_task_schedule(hdev);
2493         }
2494
2495         hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2496         handle->last_reset_time = jiffies;
2497         rtnl_unlock();
2498         ae_dev->reset_type = HNAE3_NONE_RESET;
2499 }
2500
2501 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
2502 {
2503         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2504         struct hclge_dev *hdev = ae_dev->priv;
2505
2506         /* We might end up getting called broadly because of 2 below cases:
2507          * 1. Recoverable error was conveyed through APEI and only way to bring
2508          *    normalcy is to reset.
2509          * 2. A new reset request from the stack due to timeout
2510          *
2511          * For the first case,error event might not have ae handle available.
2512          * check if this is a new reset request and we are not here just because
2513          * last reset attempt did not succeed and watchdog hit us again. We will
2514          * know this if last reset request did not occur very recently (watchdog
2515          * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2516          * In case of new request we reset the "reset level" to PF reset.
2517          * And if it is a repeat reset request of the most recent one then we
2518          * want to make sure we throttle the reset request. Therefore, we will
2519          * not allow it again before 3*HZ times.
2520          */
2521         if (!handle)
2522                 handle = &hdev->vport[0].nic;
2523
2524         if (time_before(jiffies, (handle->last_reset_time + 3 * HZ)))
2525                 return;
2526         else if (hdev->default_reset_request)
2527                 handle->reset_level =
2528                         hclge_get_reset_level(hdev,
2529                                               &hdev->default_reset_request);
2530         else if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
2531                 handle->reset_level = HNAE3_FUNC_RESET;
2532
2533         dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2534                  handle->reset_level);
2535
2536         /* request reset & schedule reset task */
2537         set_bit(handle->reset_level, &hdev->reset_request);
2538         hclge_reset_task_schedule(hdev);
2539
2540         if (handle->reset_level < HNAE3_GLOBAL_RESET)
2541                 handle->reset_level++;
2542 }
2543
2544 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
2545                                         enum hnae3_reset_type rst_type)
2546 {
2547         struct hclge_dev *hdev = ae_dev->priv;
2548
2549         set_bit(rst_type, &hdev->default_reset_request);
2550 }
2551
2552 static void hclge_reset_subtask(struct hclge_dev *hdev)
2553 {
2554         /* check if there is any ongoing reset in the hardware. This status can
2555          * be checked from reset_pending. If there is then, we need to wait for
2556          * hardware to complete reset.
2557          *    a. If we are able to figure out in reasonable time that hardware
2558          *       has fully resetted then, we can proceed with driver, client
2559          *       reset.
2560          *    b. else, we can come back later to check this status so re-sched
2561          *       now.
2562          */
2563         hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2564         if (hdev->reset_type != HNAE3_NONE_RESET)
2565                 hclge_reset(hdev);
2566
2567         /* check if we got any *new* reset requests to be honored */
2568         hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2569         if (hdev->reset_type != HNAE3_NONE_RESET)
2570                 hclge_do_reset(hdev);
2571
2572         hdev->reset_type = HNAE3_NONE_RESET;
2573 }
2574
2575 static void hclge_reset_service_task(struct work_struct *work)
2576 {
2577         struct hclge_dev *hdev =
2578                 container_of(work, struct hclge_dev, rst_service_task);
2579
2580         if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2581                 return;
2582
2583         clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2584
2585         hclge_reset_subtask(hdev);
2586
2587         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
2588 }
2589
2590 static void hclge_mailbox_service_task(struct work_struct *work)
2591 {
2592         struct hclge_dev *hdev =
2593                 container_of(work, struct hclge_dev, mbx_service_task);
2594
2595         if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2596                 return;
2597
2598         clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2599
2600         hclge_mbx_handler(hdev);
2601
2602         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2603 }
2604
2605 static void hclge_service_task(struct work_struct *work)
2606 {
2607         struct hclge_dev *hdev =
2608                 container_of(work, struct hclge_dev, service_task);
2609
2610         if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2611                 hclge_update_stats_for_all(hdev);
2612                 hdev->hw_stats.stats_timer = 0;
2613         }
2614
2615         hclge_update_speed_duplex(hdev);
2616         hclge_update_link_status(hdev);
2617         hclge_service_complete(hdev);
2618 }
2619
2620 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2621 {
2622         /* VF handle has no client */
2623         if (!handle->client)
2624                 return container_of(handle, struct hclge_vport, nic);
2625         else if (handle->client->type == HNAE3_CLIENT_ROCE)
2626                 return container_of(handle, struct hclge_vport, roce);
2627         else
2628                 return container_of(handle, struct hclge_vport, nic);
2629 }
2630
2631 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2632                             struct hnae3_vector_info *vector_info)
2633 {
2634         struct hclge_vport *vport = hclge_get_vport(handle);
2635         struct hnae3_vector_info *vector = vector_info;
2636         struct hclge_dev *hdev = vport->back;
2637         int alloc = 0;
2638         int i, j;
2639
2640         vector_num = min(hdev->num_msi_left, vector_num);
2641
2642         for (j = 0; j < vector_num; j++) {
2643                 for (i = 1; i < hdev->num_msi; i++) {
2644                         if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2645                                 vector->vector = pci_irq_vector(hdev->pdev, i);
2646                                 vector->io_addr = hdev->hw.io_base +
2647                                         HCLGE_VECTOR_REG_BASE +
2648                                         (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2649                                         vport->vport_id *
2650                                         HCLGE_VECTOR_VF_OFFSET;
2651                                 hdev->vector_status[i] = vport->vport_id;
2652                                 hdev->vector_irq[i] = vector->vector;
2653
2654                                 vector++;
2655                                 alloc++;
2656
2657                                 break;
2658                         }
2659                 }
2660         }
2661         hdev->num_msi_left -= alloc;
2662         hdev->num_msi_used += alloc;
2663
2664         return alloc;
2665 }
2666
2667 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2668 {
2669         int i;
2670
2671         for (i = 0; i < hdev->num_msi; i++)
2672                 if (vector == hdev->vector_irq[i])
2673                         return i;
2674
2675         return -EINVAL;
2676 }
2677
2678 static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2679 {
2680         struct hclge_vport *vport = hclge_get_vport(handle);
2681         struct hclge_dev *hdev = vport->back;
2682         int vector_id;
2683
2684         vector_id = hclge_get_vector_index(hdev, vector);
2685         if (vector_id < 0) {
2686                 dev_err(&hdev->pdev->dev,
2687                         "Get vector index fail. vector_id =%d\n", vector_id);
2688                 return vector_id;
2689         }
2690
2691         hclge_free_vector(hdev, vector_id);
2692
2693         return 0;
2694 }
2695
2696 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2697 {
2698         return HCLGE_RSS_KEY_SIZE;
2699 }
2700
2701 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2702 {
2703         return HCLGE_RSS_IND_TBL_SIZE;
2704 }
2705
2706 static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2707                                   const u8 hfunc, const u8 *key)
2708 {
2709         struct hclge_rss_config_cmd *req;
2710         struct hclge_desc desc;
2711         int key_offset;
2712         int key_size;
2713         int ret;
2714
2715         req = (struct hclge_rss_config_cmd *)desc.data;
2716
2717         for (key_offset = 0; key_offset < 3; key_offset++) {
2718                 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2719                                            false);
2720
2721                 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2722                 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2723
2724                 if (key_offset == 2)
2725                         key_size =
2726                         HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2727                 else
2728                         key_size = HCLGE_RSS_HASH_KEY_NUM;
2729
2730                 memcpy(req->hash_key,
2731                        key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2732
2733                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2734                 if (ret) {
2735                         dev_err(&hdev->pdev->dev,
2736                                 "Configure RSS config fail, status = %d\n",
2737                                 ret);
2738                         return ret;
2739                 }
2740         }
2741         return 0;
2742 }
2743
2744 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
2745 {
2746         struct hclge_rss_indirection_table_cmd *req;
2747         struct hclge_desc desc;
2748         int i, j;
2749         int ret;
2750
2751         req = (struct hclge_rss_indirection_table_cmd *)desc.data;
2752
2753         for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2754                 hclge_cmd_setup_basic_desc
2755                         (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2756
2757                 req->start_table_index =
2758                         cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
2759                 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
2760
2761                 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2762                         req->rss_result[j] =
2763                                 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2764
2765                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2766                 if (ret) {
2767                         dev_err(&hdev->pdev->dev,
2768                                 "Configure rss indir table fail,status = %d\n",
2769                                 ret);
2770                         return ret;
2771                 }
2772         }
2773         return 0;
2774 }
2775
2776 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2777                                  u16 *tc_size, u16 *tc_offset)
2778 {
2779         struct hclge_rss_tc_mode_cmd *req;
2780         struct hclge_desc desc;
2781         int ret;
2782         int i;
2783
2784         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
2785         req = (struct hclge_rss_tc_mode_cmd *)desc.data;
2786
2787         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2788                 u16 mode = 0;
2789
2790                 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
2791                 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
2792                                 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
2793                 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
2794                                 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
2795
2796                 req->rss_tc_mode[i] = cpu_to_le16(mode);
2797         }
2798
2799         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2800         if (ret)
2801                 dev_err(&hdev->pdev->dev,
2802                         "Configure rss tc mode fail, status = %d\n", ret);
2803
2804         return ret;
2805 }
2806
2807 static void hclge_get_rss_type(struct hclge_vport *vport)
2808 {
2809         if (vport->rss_tuple_sets.ipv4_tcp_en ||
2810             vport->rss_tuple_sets.ipv4_udp_en ||
2811             vport->rss_tuple_sets.ipv4_sctp_en ||
2812             vport->rss_tuple_sets.ipv6_tcp_en ||
2813             vport->rss_tuple_sets.ipv6_udp_en ||
2814             vport->rss_tuple_sets.ipv6_sctp_en)
2815                 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L4;
2816         else if (vport->rss_tuple_sets.ipv4_fragment_en ||
2817                  vport->rss_tuple_sets.ipv6_fragment_en)
2818                 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L3;
2819         else
2820                 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_NONE;
2821 }
2822
2823 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2824 {
2825         struct hclge_rss_input_tuple_cmd *req;
2826         struct hclge_desc desc;
2827         int ret;
2828
2829         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2830
2831         req = (struct hclge_rss_input_tuple_cmd *)desc.data;
2832
2833         /* Get the tuple cfg from pf */
2834         req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
2835         req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
2836         req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
2837         req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
2838         req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
2839         req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
2840         req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
2841         req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
2842         hclge_get_rss_type(&hdev->vport[0]);
2843         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2844         if (ret)
2845                 dev_err(&hdev->pdev->dev,
2846                         "Configure rss input fail, status = %d\n", ret);
2847         return ret;
2848 }
2849
2850 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
2851                          u8 *key, u8 *hfunc)
2852 {
2853         struct hclge_vport *vport = hclge_get_vport(handle);
2854         int i;
2855
2856         /* Get hash algorithm */
2857         if (hfunc) {
2858                 switch (vport->rss_algo) {
2859                 case HCLGE_RSS_HASH_ALGO_TOEPLITZ:
2860                         *hfunc = ETH_RSS_HASH_TOP;
2861                         break;
2862                 case HCLGE_RSS_HASH_ALGO_SIMPLE:
2863                         *hfunc = ETH_RSS_HASH_XOR;
2864                         break;
2865                 default:
2866                         *hfunc = ETH_RSS_HASH_UNKNOWN;
2867                         break;
2868                 }
2869         }
2870
2871         /* Get the RSS Key required by the user */
2872         if (key)
2873                 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
2874
2875         /* Get indirect table */
2876         if (indir)
2877                 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2878                         indir[i] =  vport->rss_indirection_tbl[i];
2879
2880         return 0;
2881 }
2882
2883 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
2884                          const  u8 *key, const  u8 hfunc)
2885 {
2886         struct hclge_vport *vport = hclge_get_vport(handle);
2887         struct hclge_dev *hdev = vport->back;
2888         u8 hash_algo;
2889         int ret, i;
2890
2891         /* Set the RSS Hash Key if specififed by the user */
2892         if (key) {
2893                 switch (hfunc) {
2894                 case ETH_RSS_HASH_TOP:
2895                         hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2896                         break;
2897                 case ETH_RSS_HASH_XOR:
2898                         hash_algo = HCLGE_RSS_HASH_ALGO_SIMPLE;
2899                         break;
2900                 case ETH_RSS_HASH_NO_CHANGE:
2901                         hash_algo = vport->rss_algo;
2902                         break;
2903                 default:
2904                         return -EINVAL;
2905                 }
2906
2907                 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
2908                 if (ret)
2909                         return ret;
2910
2911                 /* Update the shadow RSS key with user specified qids */
2912                 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
2913                 vport->rss_algo = hash_algo;
2914         }
2915
2916         /* Update the shadow RSS table with user specified qids */
2917         for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2918                 vport->rss_indirection_tbl[i] = indir[i];
2919
2920         /* Update the hardware */
2921         return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
2922 }
2923
2924 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
2925 {
2926         u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
2927
2928         if (nfc->data & RXH_L4_B_2_3)
2929                 hash_sets |= HCLGE_D_PORT_BIT;
2930         else
2931                 hash_sets &= ~HCLGE_D_PORT_BIT;
2932
2933         if (nfc->data & RXH_IP_SRC)
2934                 hash_sets |= HCLGE_S_IP_BIT;
2935         else
2936                 hash_sets &= ~HCLGE_S_IP_BIT;
2937
2938         if (nfc->data & RXH_IP_DST)
2939                 hash_sets |= HCLGE_D_IP_BIT;
2940         else
2941                 hash_sets &= ~HCLGE_D_IP_BIT;
2942
2943         if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
2944                 hash_sets |= HCLGE_V_TAG_BIT;
2945
2946         return hash_sets;
2947 }
2948
2949 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
2950                                struct ethtool_rxnfc *nfc)
2951 {
2952         struct hclge_vport *vport = hclge_get_vport(handle);
2953         struct hclge_dev *hdev = vport->back;
2954         struct hclge_rss_input_tuple_cmd *req;
2955         struct hclge_desc desc;
2956         u8 tuple_sets;
2957         int ret;
2958
2959         if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2960                           RXH_L4_B_0_1 | RXH_L4_B_2_3))
2961                 return -EINVAL;
2962
2963         req = (struct hclge_rss_input_tuple_cmd *)desc.data;
2964         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2965
2966         req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
2967         req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
2968         req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
2969         req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
2970         req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
2971         req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
2972         req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
2973         req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
2974
2975         tuple_sets = hclge_get_rss_hash_bits(nfc);
2976         switch (nfc->flow_type) {
2977         case TCP_V4_FLOW:
2978                 req->ipv4_tcp_en = tuple_sets;
2979                 break;
2980         case TCP_V6_FLOW:
2981                 req->ipv6_tcp_en = tuple_sets;
2982                 break;
2983         case UDP_V4_FLOW:
2984                 req->ipv4_udp_en = tuple_sets;
2985                 break;
2986         case UDP_V6_FLOW:
2987                 req->ipv6_udp_en = tuple_sets;
2988                 break;
2989         case SCTP_V4_FLOW:
2990                 req->ipv4_sctp_en = tuple_sets;
2991                 break;
2992         case SCTP_V6_FLOW:
2993                 if ((nfc->data & RXH_L4_B_0_1) ||
2994                     (nfc->data & RXH_L4_B_2_3))
2995                         return -EINVAL;
2996
2997                 req->ipv6_sctp_en = tuple_sets;
2998                 break;
2999         case IPV4_FLOW:
3000                 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3001                 break;
3002         case IPV6_FLOW:
3003                 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3004                 break;
3005         default:
3006                 return -EINVAL;
3007         }
3008
3009         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3010         if (ret) {
3011                 dev_err(&hdev->pdev->dev,
3012                         "Set rss tuple fail, status = %d\n", ret);
3013                 return ret;
3014         }
3015
3016         vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3017         vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3018         vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3019         vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3020         vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3021         vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3022         vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3023         vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3024         hclge_get_rss_type(vport);
3025         return 0;
3026 }
3027
3028 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3029                                struct ethtool_rxnfc *nfc)
3030 {
3031         struct hclge_vport *vport = hclge_get_vport(handle);
3032         u8 tuple_sets;
3033
3034         nfc->data = 0;
3035
3036         switch (nfc->flow_type) {
3037         case TCP_V4_FLOW:
3038                 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
3039                 break;
3040         case UDP_V4_FLOW:
3041                 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
3042                 break;
3043         case TCP_V6_FLOW:
3044                 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
3045                 break;
3046         case UDP_V6_FLOW:
3047                 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
3048                 break;
3049         case SCTP_V4_FLOW:
3050                 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
3051                 break;
3052         case SCTP_V6_FLOW:
3053                 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
3054                 break;
3055         case IPV4_FLOW:
3056         case IPV6_FLOW:
3057                 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3058                 break;
3059         default:
3060                 return -EINVAL;
3061         }
3062
3063         if (!tuple_sets)
3064                 return 0;
3065
3066         if (tuple_sets & HCLGE_D_PORT_BIT)
3067                 nfc->data |= RXH_L4_B_2_3;
3068         if (tuple_sets & HCLGE_S_PORT_BIT)
3069                 nfc->data |= RXH_L4_B_0_1;
3070         if (tuple_sets & HCLGE_D_IP_BIT)
3071                 nfc->data |= RXH_IP_DST;
3072         if (tuple_sets & HCLGE_S_IP_BIT)
3073                 nfc->data |= RXH_IP_SRC;
3074
3075         return 0;
3076 }
3077
3078 static int hclge_get_tc_size(struct hnae3_handle *handle)
3079 {
3080         struct hclge_vport *vport = hclge_get_vport(handle);
3081         struct hclge_dev *hdev = vport->back;
3082
3083         return hdev->rss_size_max;
3084 }
3085
3086 int hclge_rss_init_hw(struct hclge_dev *hdev)
3087 {
3088         struct hclge_vport *vport = hdev->vport;
3089         u8 *rss_indir = vport[0].rss_indirection_tbl;
3090         u16 rss_size = vport[0].alloc_rss_size;
3091         u8 *key = vport[0].rss_hash_key;
3092         u8 hfunc = vport[0].rss_algo;
3093         u16 tc_offset[HCLGE_MAX_TC_NUM];
3094         u16 tc_valid[HCLGE_MAX_TC_NUM];
3095         u16 tc_size[HCLGE_MAX_TC_NUM];
3096         u16 roundup_size;
3097         int i, ret;
3098
3099         ret = hclge_set_rss_indir_table(hdev, rss_indir);
3100         if (ret)
3101                 return ret;
3102
3103         ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3104         if (ret)
3105                 return ret;
3106
3107         ret = hclge_set_rss_input_tuple(hdev);
3108         if (ret)
3109                 return ret;
3110
3111         /* Each TC have the same queue size, and tc_size set to hardware is
3112          * the log2 of roundup power of two of rss_size, the acutal queue
3113          * size is limited by indirection table.
3114          */
3115         if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3116                 dev_err(&hdev->pdev->dev,
3117                         "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3118                         rss_size);
3119                 return -EINVAL;
3120         }
3121
3122         roundup_size = roundup_pow_of_two(rss_size);
3123         roundup_size = ilog2(roundup_size);
3124
3125         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3126                 tc_valid[i] = 0;
3127
3128                 if (!(hdev->hw_tc_map & BIT(i)))
3129                         continue;
3130
3131                 tc_valid[i] = 1;
3132                 tc_size[i] = roundup_size;
3133                 tc_offset[i] = rss_size * i;
3134         }
3135
3136         return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3137 }
3138
3139 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3140 {
3141         struct hclge_vport *vport = hdev->vport;
3142         int i, j;
3143
3144         for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3145                 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3146                         vport[j].rss_indirection_tbl[i] =
3147                                 i % vport[j].alloc_rss_size;
3148         }
3149 }
3150
3151 static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3152 {
3153         struct hclge_vport *vport = hdev->vport;
3154         int i;
3155
3156         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3157                 vport[i].rss_tuple_sets.ipv4_tcp_en =
3158                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3159                 vport[i].rss_tuple_sets.ipv4_udp_en =
3160                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3161                 vport[i].rss_tuple_sets.ipv4_sctp_en =
3162                         HCLGE_RSS_INPUT_TUPLE_SCTP;
3163                 vport[i].rss_tuple_sets.ipv4_fragment_en =
3164                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3165                 vport[i].rss_tuple_sets.ipv6_tcp_en =
3166                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3167                 vport[i].rss_tuple_sets.ipv6_udp_en =
3168                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3169                 vport[i].rss_tuple_sets.ipv6_sctp_en =
3170                         HCLGE_RSS_INPUT_TUPLE_SCTP;
3171                 vport[i].rss_tuple_sets.ipv6_fragment_en =
3172                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3173
3174                 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3175
3176                 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
3177         }
3178
3179         hclge_rss_indir_init_cfg(hdev);
3180 }
3181
3182 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3183                                 int vector_id, bool en,
3184                                 struct hnae3_ring_chain_node *ring_chain)
3185 {
3186         struct hclge_dev *hdev = vport->back;
3187         struct hnae3_ring_chain_node *node;
3188         struct hclge_desc desc;
3189         struct hclge_ctrl_vector_chain_cmd *req
3190                 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3191         enum hclge_cmd_status status;
3192         enum hclge_opcode_type op;
3193         u16 tqp_type_and_id;
3194         int i;
3195
3196         op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3197         hclge_cmd_setup_basic_desc(&desc, op, false);
3198         req->int_vector_id = vector_id;
3199
3200         i = 0;
3201         for (node = ring_chain; node; node = node->next) {
3202                 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3203                 hnae3_set_field(tqp_type_and_id,  HCLGE_INT_TYPE_M,
3204                                 HCLGE_INT_TYPE_S,
3205                                 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3206                 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3207                                 HCLGE_TQP_ID_S, node->tqp_index);
3208                 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3209                                 HCLGE_INT_GL_IDX_S,
3210                                 hnae3_get_field(node->int_gl_idx,
3211                                                 HNAE3_RING_GL_IDX_M,
3212                                                 HNAE3_RING_GL_IDX_S));
3213                 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
3214                 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3215                         req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3216                         req->vfid = vport->vport_id;
3217
3218                         status = hclge_cmd_send(&hdev->hw, &desc, 1);
3219                         if (status) {
3220                                 dev_err(&hdev->pdev->dev,
3221                                         "Map TQP fail, status is %d.\n",
3222                                         status);
3223                                 return -EIO;
3224                         }
3225                         i = 0;
3226
3227                         hclge_cmd_setup_basic_desc(&desc,
3228                                                    op,
3229                                                    false);
3230                         req->int_vector_id = vector_id;
3231                 }
3232         }
3233
3234         if (i > 0) {
3235                 req->int_cause_num = i;
3236                 req->vfid = vport->vport_id;
3237                 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3238                 if (status) {
3239                         dev_err(&hdev->pdev->dev,
3240                                 "Map TQP fail, status is %d.\n", status);
3241                         return -EIO;
3242                 }
3243         }
3244
3245         return 0;
3246 }
3247
3248 static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3249                                     int vector,
3250                                     struct hnae3_ring_chain_node *ring_chain)
3251 {
3252         struct hclge_vport *vport = hclge_get_vport(handle);
3253         struct hclge_dev *hdev = vport->back;
3254         int vector_id;
3255
3256         vector_id = hclge_get_vector_index(hdev, vector);
3257         if (vector_id < 0) {
3258                 dev_err(&hdev->pdev->dev,
3259                         "Get vector index fail. vector_id =%d\n", vector_id);
3260                 return vector_id;
3261         }
3262
3263         return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
3264 }
3265
3266 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3267                                        int vector,
3268                                        struct hnae3_ring_chain_node *ring_chain)
3269 {
3270         struct hclge_vport *vport = hclge_get_vport(handle);
3271         struct hclge_dev *hdev = vport->back;
3272         int vector_id, ret;
3273
3274         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3275                 return 0;
3276
3277         vector_id = hclge_get_vector_index(hdev, vector);
3278         if (vector_id < 0) {
3279                 dev_err(&handle->pdev->dev,
3280                         "Get vector index fail. ret =%d\n", vector_id);
3281                 return vector_id;
3282         }
3283
3284         ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
3285         if (ret)
3286                 dev_err(&handle->pdev->dev,
3287                         "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3288                         vector_id,
3289                         ret);
3290
3291         return ret;
3292 }
3293
3294 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3295                                struct hclge_promisc_param *param)
3296 {
3297         struct hclge_promisc_cfg_cmd *req;
3298         struct hclge_desc desc;
3299         int ret;
3300
3301         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3302
3303         req = (struct hclge_promisc_cfg_cmd *)desc.data;
3304         req->vf_id = param->vf_id;
3305
3306         /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3307          * pdev revision(0x20), new revision support them. The
3308          * value of this two fields will not return error when driver
3309          * send command to fireware in revision(0x20).
3310          */
3311         req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3312                 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
3313
3314         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3315         if (ret)
3316                 dev_err(&hdev->pdev->dev,
3317                         "Set promisc mode fail, status is %d.\n", ret);
3318
3319         return ret;
3320 }
3321
3322 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3323                               bool en_mc, bool en_bc, int vport_id)
3324 {
3325         if (!param)
3326                 return;
3327
3328         memset(param, 0, sizeof(struct hclge_promisc_param));
3329         if (en_uc)
3330                 param->enable = HCLGE_PROMISC_EN_UC;
3331         if (en_mc)
3332                 param->enable |= HCLGE_PROMISC_EN_MC;
3333         if (en_bc)
3334                 param->enable |= HCLGE_PROMISC_EN_BC;
3335         param->vf_id = vport_id;
3336 }
3337
3338 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3339                                   bool en_mc_pmc)
3340 {
3341         struct hclge_vport *vport = hclge_get_vport(handle);
3342         struct hclge_dev *hdev = vport->back;
3343         struct hclge_promisc_param param;
3344
3345         hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3346                                  vport->vport_id);
3347         return hclge_cmd_set_promisc_mode(hdev, &param);
3348 }
3349
3350 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
3351 {
3352         struct hclge_get_fd_mode_cmd *req;
3353         struct hclge_desc desc;
3354         int ret;
3355
3356         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true);
3357
3358         req = (struct hclge_get_fd_mode_cmd *)desc.data;
3359
3360         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3361         if (ret) {
3362                 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret);
3363                 return ret;
3364         }
3365
3366         *fd_mode = req->mode;
3367
3368         return ret;
3369 }
3370
3371 static int hclge_get_fd_allocation(struct hclge_dev *hdev,
3372                                    u32 *stage1_entry_num,
3373                                    u32 *stage2_entry_num,
3374                                    u16 *stage1_counter_num,
3375                                    u16 *stage2_counter_num)
3376 {
3377         struct hclge_get_fd_allocation_cmd *req;
3378         struct hclge_desc desc;
3379         int ret;
3380
3381         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true);
3382
3383         req = (struct hclge_get_fd_allocation_cmd *)desc.data;
3384
3385         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3386         if (ret) {
3387                 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n",
3388                         ret);
3389                 return ret;
3390         }
3391
3392         *stage1_entry_num = le32_to_cpu(req->stage1_entry_num);
3393         *stage2_entry_num = le32_to_cpu(req->stage2_entry_num);
3394         *stage1_counter_num = le16_to_cpu(req->stage1_counter_num);
3395         *stage2_counter_num = le16_to_cpu(req->stage2_counter_num);
3396
3397         return ret;
3398 }
3399
3400 static int hclge_set_fd_key_config(struct hclge_dev *hdev, int stage_num)
3401 {
3402         struct hclge_set_fd_key_config_cmd *req;
3403         struct hclge_fd_key_cfg *stage;
3404         struct hclge_desc desc;
3405         int ret;
3406
3407         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false);
3408
3409         req = (struct hclge_set_fd_key_config_cmd *)desc.data;
3410         stage = &hdev->fd_cfg.key_cfg[stage_num];
3411         req->stage = stage_num;
3412         req->key_select = stage->key_sel;
3413         req->inner_sipv6_word_en = stage->inner_sipv6_word_en;
3414         req->inner_dipv6_word_en = stage->inner_dipv6_word_en;
3415         req->outer_sipv6_word_en = stage->outer_sipv6_word_en;
3416         req->outer_dipv6_word_en = stage->outer_dipv6_word_en;
3417         req->tuple_mask = cpu_to_le32(~stage->tuple_active);
3418         req->meta_data_mask = cpu_to_le32(~stage->meta_data_active);
3419
3420         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3421         if (ret)
3422                 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret);
3423
3424         return ret;
3425 }
3426
3427 static int hclge_init_fd_config(struct hclge_dev *hdev)
3428 {
3429 #define LOW_2_WORDS             0x03
3430         struct hclge_fd_key_cfg *key_cfg;
3431         int ret;
3432
3433         if (!hnae3_dev_fd_supported(hdev))
3434                 return 0;
3435
3436         ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode);
3437         if (ret)
3438                 return ret;
3439
3440         switch (hdev->fd_cfg.fd_mode) {
3441         case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1:
3442                 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH;
3443                 break;
3444         case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1:
3445                 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2;
3446                 break;
3447         default:
3448                 dev_err(&hdev->pdev->dev,
3449                         "Unsupported flow director mode %d\n",
3450                         hdev->fd_cfg.fd_mode);
3451                 return -EOPNOTSUPP;
3452         }
3453
3454         hdev->fd_cfg.fd_en = true;
3455         hdev->fd_cfg.proto_support =
3456                 TCP_V4_FLOW | UDP_V4_FLOW | SCTP_V4_FLOW | TCP_V6_FLOW |
3457                 UDP_V6_FLOW | SCTP_V6_FLOW | IPV4_USER_FLOW | IPV6_USER_FLOW;
3458         key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1];
3459         key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE,
3460         key_cfg->inner_sipv6_word_en = LOW_2_WORDS;
3461         key_cfg->inner_dipv6_word_en = LOW_2_WORDS;
3462         key_cfg->outer_sipv6_word_en = 0;
3463         key_cfg->outer_dipv6_word_en = 0;
3464
3465         key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) |
3466                                 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) |
3467                                 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
3468                                 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
3469
3470         /* If use max 400bit key, we can support tuples for ether type */
3471         if (hdev->fd_cfg.max_key_length == MAX_KEY_LENGTH) {
3472                 hdev->fd_cfg.proto_support |= ETHER_FLOW;
3473                 key_cfg->tuple_active |=
3474                                 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
3475         }
3476
3477         /* roce_type is used to filter roce frames
3478          * dst_vport is used to specify the rule
3479          */
3480         key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT);
3481
3482         ret = hclge_get_fd_allocation(hdev,
3483                                       &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
3484                                       &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2],
3485                                       &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1],
3486                                       &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]);
3487         if (ret)
3488                 return ret;
3489
3490         return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
3491 }
3492
3493 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
3494                                 int loc, u8 *key, bool is_add)
3495 {
3496         struct hclge_fd_tcam_config_1_cmd *req1;
3497         struct hclge_fd_tcam_config_2_cmd *req2;
3498         struct hclge_fd_tcam_config_3_cmd *req3;
3499         struct hclge_desc desc[3];
3500         int ret;
3501
3502         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
3503         desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3504         hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
3505         desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3506         hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
3507
3508         req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
3509         req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
3510         req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
3511
3512         req1->stage = stage;
3513         req1->xy_sel = sel_x ? 1 : 0;
3514         hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0);
3515         req1->index = cpu_to_le32(loc);
3516         req1->entry_vld = sel_x ? is_add : 0;
3517
3518         if (key) {
3519                 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data));
3520                 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)],
3521                        sizeof(req2->tcam_data));
3522                 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) +
3523                        sizeof(req2->tcam_data)], sizeof(req3->tcam_data));
3524         }
3525
3526         ret = hclge_cmd_send(&hdev->hw, desc, 3);
3527         if (ret)
3528                 dev_err(&hdev->pdev->dev,
3529                         "config tcam key fail, ret=%d\n",
3530                         ret);
3531
3532         return ret;
3533 }
3534
3535 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
3536                               struct hclge_fd_ad_data *action)
3537 {
3538         struct hclge_fd_ad_config_cmd *req;
3539         struct hclge_desc desc;
3540         u64 ad_data = 0;
3541         int ret;
3542
3543         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false);
3544
3545         req = (struct hclge_fd_ad_config_cmd *)desc.data;
3546         req->index = cpu_to_le32(loc);
3547         req->stage = stage;
3548
3549         hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B,
3550                       action->write_rule_id_to_bd);
3551         hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S,
3552                         action->rule_id);
3553         ad_data <<= 32;
3554         hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
3555         hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
3556                       action->forward_to_direct_queue);
3557         hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,
3558                         action->queue_id);
3559         hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
3560         hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
3561                         HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);
3562         hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
3563         hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
3564                         action->counter_id);
3565
3566         req->ad_data = cpu_to_le64(ad_data);
3567         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3568         if (ret)
3569                 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret);
3570
3571         return ret;
3572 }
3573
3574 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
3575                                    struct hclge_fd_rule *rule)
3576 {
3577         u16 tmp_x_s, tmp_y_s;
3578         u32 tmp_x_l, tmp_y_l;
3579         int i;
3580
3581         if (rule->unused_tuple & tuple_bit)
3582                 return true;
3583
3584         switch (tuple_bit) {
3585         case 0:
3586                 return false;
3587         case BIT(INNER_DST_MAC):
3588                 for (i = 0; i < 6; i++) {
3589                         calc_x(key_x[5 - i], rule->tuples.dst_mac[i],
3590                                rule->tuples_mask.dst_mac[i]);
3591                         calc_y(key_y[5 - i], rule->tuples.dst_mac[i],
3592                                rule->tuples_mask.dst_mac[i]);
3593                 }
3594
3595                 return true;
3596         case BIT(INNER_SRC_MAC):
3597                 for (i = 0; i < 6; i++) {
3598                         calc_x(key_x[5 - i], rule->tuples.src_mac[i],
3599                                rule->tuples.src_mac[i]);
3600                         calc_y(key_y[5 - i], rule->tuples.src_mac[i],
3601                                rule->tuples.src_mac[i]);
3602                 }
3603
3604                 return true;
3605         case BIT(INNER_VLAN_TAG_FST):
3606                 calc_x(tmp_x_s, rule->tuples.vlan_tag1,
3607                        rule->tuples_mask.vlan_tag1);
3608                 calc_y(tmp_y_s, rule->tuples.vlan_tag1,
3609                        rule->tuples_mask.vlan_tag1);
3610                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3611                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3612
3613                 return true;
3614         case BIT(INNER_ETH_TYPE):
3615                 calc_x(tmp_x_s, rule->tuples.ether_proto,
3616                        rule->tuples_mask.ether_proto);
3617                 calc_y(tmp_y_s, rule->tuples.ether_proto,
3618                        rule->tuples_mask.ether_proto);
3619                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3620                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3621
3622                 return true;
3623         case BIT(INNER_IP_TOS):
3624                 calc_x(*key_x, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
3625                 calc_y(*key_y, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
3626
3627                 return true;
3628         case BIT(INNER_IP_PROTO):
3629                 calc_x(*key_x, rule->tuples.ip_proto,
3630                        rule->tuples_mask.ip_proto);
3631                 calc_y(*key_y, rule->tuples.ip_proto,
3632                        rule->tuples_mask.ip_proto);
3633
3634                 return true;
3635         case BIT(INNER_SRC_IP):
3636                 calc_x(tmp_x_l, rule->tuples.src_ip[3],
3637                        rule->tuples_mask.src_ip[3]);
3638                 calc_y(tmp_y_l, rule->tuples.src_ip[3],
3639                        rule->tuples_mask.src_ip[3]);
3640                 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
3641                 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
3642
3643                 return true;
3644         case BIT(INNER_DST_IP):
3645                 calc_x(tmp_x_l, rule->tuples.dst_ip[3],
3646                        rule->tuples_mask.dst_ip[3]);
3647                 calc_y(tmp_y_l, rule->tuples.dst_ip[3],
3648                        rule->tuples_mask.dst_ip[3]);
3649                 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
3650                 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
3651
3652                 return true;
3653         case BIT(INNER_SRC_PORT):
3654                 calc_x(tmp_x_s, rule->tuples.src_port,
3655                        rule->tuples_mask.src_port);
3656                 calc_y(tmp_y_s, rule->tuples.src_port,
3657                        rule->tuples_mask.src_port);
3658                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3659                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3660
3661                 return true;
3662         case BIT(INNER_DST_PORT):
3663                 calc_x(tmp_x_s, rule->tuples.dst_port,
3664                        rule->tuples_mask.dst_port);
3665                 calc_y(tmp_y_s, rule->tuples.dst_port,
3666                        rule->tuples_mask.dst_port);
3667                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3668                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3669
3670                 return true;
3671         default:
3672                 return false;
3673         }
3674 }
3675
3676 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id,
3677                                  u8 vf_id, u8 network_port_id)
3678 {
3679         u32 port_number = 0;
3680
3681         if (port_type == HOST_PORT) {
3682                 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S,
3683                                 pf_id);
3684                 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S,
3685                                 vf_id);
3686                 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT);
3687         } else {
3688                 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M,
3689                                 HCLGE_NETWORK_PORT_ID_S, network_port_id);
3690                 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT);
3691         }
3692
3693         return port_number;
3694 }
3695
3696 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg,
3697                                        __le32 *key_x, __le32 *key_y,
3698                                        struct hclge_fd_rule *rule)
3699 {
3700         u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number;
3701         u8 cur_pos = 0, tuple_size, shift_bits;
3702         int i;
3703
3704         for (i = 0; i < MAX_META_DATA; i++) {
3705                 tuple_size = meta_data_key_info[i].key_length;
3706                 tuple_bit = key_cfg->meta_data_active & BIT(i);
3707
3708                 switch (tuple_bit) {
3709                 case BIT(ROCE_TYPE):
3710                         hnae3_set_bit(meta_data, cur_pos, NIC_PACKET);
3711                         cur_pos += tuple_size;
3712                         break;
3713                 case BIT(DST_VPORT):
3714                         port_number = hclge_get_port_number(HOST_PORT, 0,
3715                                                             rule->vf_id, 0);
3716                         hnae3_set_field(meta_data,
3717                                         GENMASK(cur_pos + tuple_size, cur_pos),
3718                                         cur_pos, port_number);
3719                         cur_pos += tuple_size;
3720                         break;
3721                 default:
3722                         break;
3723                 }
3724         }
3725
3726         calc_x(tmp_x, meta_data, 0xFFFFFFFF);
3727         calc_y(tmp_y, meta_data, 0xFFFFFFFF);
3728         shift_bits = sizeof(meta_data) * 8 - cur_pos;
3729
3730         *key_x = cpu_to_le32(tmp_x << shift_bits);
3731         *key_y = cpu_to_le32(tmp_y << shift_bits);
3732 }
3733
3734 /* A complete key is combined with meta data key and tuple key.
3735  * Meta data key is stored at the MSB region, and tuple key is stored at
3736  * the LSB region, unused bits will be filled 0.
3737  */
3738 static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
3739                             struct hclge_fd_rule *rule)
3740 {
3741         struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage];
3742         u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES];
3743         u8 *cur_key_x, *cur_key_y;
3744         int i, ret, tuple_size;
3745         u8 meta_data_region;
3746
3747         memset(key_x, 0, sizeof(key_x));
3748         memset(key_y, 0, sizeof(key_y));
3749         cur_key_x = key_x;
3750         cur_key_y = key_y;
3751
3752         for (i = 0 ; i < MAX_TUPLE; i++) {
3753                 bool tuple_valid;
3754                 u32 check_tuple;
3755
3756                 tuple_size = tuple_key_info[i].key_length / 8;
3757                 check_tuple = key_cfg->tuple_active & BIT(i);
3758
3759                 tuple_valid = hclge_fd_convert_tuple(check_tuple, cur_key_x,
3760                                                      cur_key_y, rule);
3761                 if (tuple_valid) {
3762                         cur_key_x += tuple_size;
3763                         cur_key_y += tuple_size;
3764                 }
3765         }
3766
3767         meta_data_region = hdev->fd_cfg.max_key_length / 8 -
3768                         MAX_META_DATA_LENGTH / 8;
3769
3770         hclge_fd_convert_meta_data(key_cfg,
3771                                    (__le32 *)(key_x + meta_data_region),
3772                                    (__le32 *)(key_y + meta_data_region),
3773                                    rule);
3774
3775         ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y,
3776                                    true);
3777         if (ret) {
3778                 dev_err(&hdev->pdev->dev,
3779                         "fd key_y config fail, loc=%d, ret=%d\n",
3780                         rule->queue_id, ret);
3781                 return ret;
3782         }
3783
3784         ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x,
3785                                    true);
3786         if (ret)
3787                 dev_err(&hdev->pdev->dev,
3788                         "fd key_x config fail, loc=%d, ret=%d\n",
3789                         rule->queue_id, ret);
3790         return ret;
3791 }
3792
3793 static int hclge_config_action(struct hclge_dev *hdev, u8 stage,
3794                                struct hclge_fd_rule *rule)
3795 {
3796         struct hclge_fd_ad_data ad_data;
3797
3798         ad_data.ad_id = rule->location;
3799
3800         if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
3801                 ad_data.drop_packet = true;
3802                 ad_data.forward_to_direct_queue = false;
3803                 ad_data.queue_id = 0;
3804         } else {
3805                 ad_data.drop_packet = false;
3806                 ad_data.forward_to_direct_queue = true;
3807                 ad_data.queue_id = rule->queue_id;
3808         }
3809
3810         ad_data.use_counter = false;
3811         ad_data.counter_id = 0;
3812
3813         ad_data.use_next_stage = false;
3814         ad_data.next_input_key = 0;
3815
3816         ad_data.write_rule_id_to_bd = true;
3817         ad_data.rule_id = rule->location;
3818
3819         return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data);
3820 }
3821
3822 static int hclge_fd_check_spec(struct hclge_dev *hdev,
3823                                struct ethtool_rx_flow_spec *fs, u32 *unused)
3824 {
3825         struct ethtool_tcpip4_spec *tcp_ip4_spec;
3826         struct ethtool_usrip4_spec *usr_ip4_spec;
3827         struct ethtool_tcpip6_spec *tcp_ip6_spec;
3828         struct ethtool_usrip6_spec *usr_ip6_spec;
3829         struct ethhdr *ether_spec;
3830
3831         if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
3832                 return -EINVAL;
3833
3834         if (!(fs->flow_type & hdev->fd_cfg.proto_support))
3835                 return -EOPNOTSUPP;
3836
3837         if ((fs->flow_type & FLOW_EXT) &&
3838             (fs->h_ext.data[0] != 0 || fs->h_ext.data[1] != 0)) {
3839                 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n");
3840                 return -EOPNOTSUPP;
3841         }
3842
3843         switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
3844         case SCTP_V4_FLOW:
3845         case TCP_V4_FLOW:
3846         case UDP_V4_FLOW:
3847                 tcp_ip4_spec = &fs->h_u.tcp_ip4_spec;
3848                 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
3849
3850                 if (!tcp_ip4_spec->ip4src)
3851                         *unused |= BIT(INNER_SRC_IP);
3852
3853                 if (!tcp_ip4_spec->ip4dst)
3854                         *unused |= BIT(INNER_DST_IP);
3855
3856                 if (!tcp_ip4_spec->psrc)
3857                         *unused |= BIT(INNER_SRC_PORT);
3858
3859                 if (!tcp_ip4_spec->pdst)
3860                         *unused |= BIT(INNER_DST_PORT);
3861
3862                 if (!tcp_ip4_spec->tos)
3863                         *unused |= BIT(INNER_IP_TOS);
3864
3865                 break;
3866         case IP_USER_FLOW:
3867                 usr_ip4_spec = &fs->h_u.usr_ip4_spec;
3868                 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
3869                         BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
3870
3871                 if (!usr_ip4_spec->ip4src)
3872                         *unused |= BIT(INNER_SRC_IP);
3873
3874                 if (!usr_ip4_spec->ip4dst)
3875                         *unused |= BIT(INNER_DST_IP);
3876
3877                 if (!usr_ip4_spec->tos)
3878                         *unused |= BIT(INNER_IP_TOS);
3879
3880                 if (!usr_ip4_spec->proto)
3881                         *unused |= BIT(INNER_IP_PROTO);
3882
3883                 if (usr_ip4_spec->l4_4_bytes)
3884                         return -EOPNOTSUPP;
3885
3886                 if (usr_ip4_spec->ip_ver != ETH_RX_NFC_IP4)
3887                         return -EOPNOTSUPP;
3888
3889                 break;
3890         case SCTP_V6_FLOW:
3891         case TCP_V6_FLOW:
3892         case UDP_V6_FLOW:
3893                 tcp_ip6_spec = &fs->h_u.tcp_ip6_spec;
3894                 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
3895                         BIT(INNER_IP_TOS);
3896
3897                 if (!tcp_ip6_spec->ip6src[0] && !tcp_ip6_spec->ip6src[1] &&
3898                     !tcp_ip6_spec->ip6src[2] && !tcp_ip6_spec->ip6src[3])
3899                         *unused |= BIT(INNER_SRC_IP);
3900
3901                 if (!tcp_ip6_spec->ip6dst[0] && !tcp_ip6_spec->ip6dst[1] &&
3902                     !tcp_ip6_spec->ip6dst[2] && !tcp_ip6_spec->ip6dst[3])
3903                         *unused |= BIT(INNER_DST_IP);
3904
3905                 if (!tcp_ip6_spec->psrc)
3906                         *unused |= BIT(INNER_SRC_PORT);
3907
3908                 if (!tcp_ip6_spec->pdst)
3909                         *unused |= BIT(INNER_DST_PORT);
3910
3911                 if (tcp_ip6_spec->tclass)
3912                         return -EOPNOTSUPP;
3913
3914                 break;
3915         case IPV6_USER_FLOW:
3916                 usr_ip6_spec = &fs->h_u.usr_ip6_spec;
3917                 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
3918                         BIT(INNER_IP_TOS) | BIT(INNER_SRC_PORT) |
3919                         BIT(INNER_DST_PORT);
3920
3921                 if (!usr_ip6_spec->ip6src[0] && !usr_ip6_spec->ip6src[1] &&
3922                     !usr_ip6_spec->ip6src[2] && !usr_ip6_spec->ip6src[3])
3923                         *unused |= BIT(INNER_SRC_IP);
3924
3925                 if (!usr_ip6_spec->ip6dst[0] && !usr_ip6_spec->ip6dst[1] &&
3926                     !usr_ip6_spec->ip6dst[2] && !usr_ip6_spec->ip6dst[3])
3927                         *unused |= BIT(INNER_DST_IP);
3928
3929                 if (!usr_ip6_spec->l4_proto)
3930                         *unused |= BIT(INNER_IP_PROTO);
3931
3932                 if (usr_ip6_spec->tclass)
3933                         return -EOPNOTSUPP;
3934
3935                 if (usr_ip6_spec->l4_4_bytes)
3936                         return -EOPNOTSUPP;
3937
3938                 break;
3939         case ETHER_FLOW:
3940                 ether_spec = &fs->h_u.ether_spec;
3941                 *unused |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
3942                         BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) |
3943                         BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO);
3944
3945                 if (is_zero_ether_addr(ether_spec->h_source))
3946                         *unused |= BIT(INNER_SRC_MAC);
3947
3948                 if (is_zero_ether_addr(ether_spec->h_dest))
3949                         *unused |= BIT(INNER_DST_MAC);
3950
3951                 if (!ether_spec->h_proto)
3952                         *unused |= BIT(INNER_ETH_TYPE);
3953
3954                 break;
3955         default:
3956                 return -EOPNOTSUPP;
3957         }
3958
3959         if ((fs->flow_type & FLOW_EXT)) {
3960                 if (fs->h_ext.vlan_etype)
3961                         return -EOPNOTSUPP;
3962                 if (!fs->h_ext.vlan_tci)
3963                         *unused |= BIT(INNER_VLAN_TAG_FST);
3964
3965                 if (fs->m_ext.vlan_tci) {
3966                         if (be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID)
3967                                 return -EINVAL;
3968                 }
3969         } else {
3970                 *unused |= BIT(INNER_VLAN_TAG_FST);
3971         }
3972
3973         if (fs->flow_type & FLOW_MAC_EXT) {
3974                 if (!(hdev->fd_cfg.proto_support & ETHER_FLOW))
3975                         return -EOPNOTSUPP;
3976
3977                 if (is_zero_ether_addr(fs->h_ext.h_dest))
3978                         *unused |= BIT(INNER_DST_MAC);
3979                 else
3980                         *unused &= ~(BIT(INNER_DST_MAC));
3981         }
3982
3983         return 0;
3984 }
3985
3986 static bool hclge_fd_rule_exist(struct hclge_dev *hdev, u16 location)
3987 {
3988         struct hclge_fd_rule *rule = NULL;
3989         struct hlist_node *node2;
3990
3991         hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
3992                 if (rule->location >= location)
3993                         break;
3994         }
3995
3996         return  rule && rule->location == location;
3997 }
3998
3999 static int hclge_fd_update_rule_list(struct hclge_dev *hdev,
4000                                      struct hclge_fd_rule *new_rule,
4001                                      u16 location,
4002                                      bool is_add)
4003 {
4004         struct hclge_fd_rule *rule = NULL, *parent = NULL;
4005         struct hlist_node *node2;
4006
4007         if (is_add && !new_rule)
4008                 return -EINVAL;
4009
4010         hlist_for_each_entry_safe(rule, node2,
4011                                   &hdev->fd_rule_list, rule_node) {
4012                 if (rule->location >= location)
4013                         break;
4014                 parent = rule;
4015         }
4016
4017         if (rule && rule->location == location) {
4018                 hlist_del(&rule->rule_node);
4019                 kfree(rule);
4020                 hdev->hclge_fd_rule_num--;
4021
4022                 if (!is_add)
4023                         return 0;
4024
4025         } else if (!is_add) {
4026                 dev_err(&hdev->pdev->dev,
4027                         "delete fail, rule %d is inexistent\n",
4028                         location);
4029                 return -EINVAL;
4030         }
4031
4032         INIT_HLIST_NODE(&new_rule->rule_node);
4033
4034         if (parent)
4035                 hlist_add_behind(&new_rule->rule_node, &parent->rule_node);
4036         else
4037                 hlist_add_head(&new_rule->rule_node, &hdev->fd_rule_list);
4038
4039         hdev->hclge_fd_rule_num++;
4040
4041         return 0;
4042 }
4043
4044 static int hclge_fd_get_tuple(struct hclge_dev *hdev,
4045                               struct ethtool_rx_flow_spec *fs,
4046                               struct hclge_fd_rule *rule)
4047 {
4048         u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
4049
4050         switch (flow_type) {
4051         case SCTP_V4_FLOW:
4052         case TCP_V4_FLOW:
4053         case UDP_V4_FLOW:
4054                 rule->tuples.src_ip[3] =
4055                                 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src);
4056                 rule->tuples_mask.src_ip[3] =
4057                                 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src);
4058
4059                 rule->tuples.dst_ip[3] =
4060                                 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst);
4061                 rule->tuples_mask.dst_ip[3] =
4062                                 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst);
4063
4064                 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc);
4065                 rule->tuples_mask.src_port =
4066                                 be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc);
4067
4068                 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst);
4069                 rule->tuples_mask.dst_port =
4070                                 be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst);
4071
4072                 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos;
4073                 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos;
4074
4075                 rule->tuples.ether_proto = ETH_P_IP;
4076                 rule->tuples_mask.ether_proto = 0xFFFF;
4077
4078                 break;
4079         case IP_USER_FLOW:
4080                 rule->tuples.src_ip[3] =
4081                                 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src);
4082                 rule->tuples_mask.src_ip[3] =
4083                                 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src);
4084
4085                 rule->tuples.dst_ip[3] =
4086                                 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst);
4087                 rule->tuples_mask.dst_ip[3] =
4088                                 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst);
4089
4090                 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos;
4091                 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos;
4092
4093                 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto;
4094                 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto;
4095
4096                 rule->tuples.ether_proto = ETH_P_IP;
4097                 rule->tuples_mask.ether_proto = 0xFFFF;
4098
4099                 break;
4100         case SCTP_V6_FLOW:
4101         case TCP_V6_FLOW:
4102         case UDP_V6_FLOW:
4103                 be32_to_cpu_array(rule->tuples.src_ip,
4104                                   fs->h_u.tcp_ip6_spec.ip6src, 4);
4105                 be32_to_cpu_array(rule->tuples_mask.src_ip,
4106                                   fs->m_u.tcp_ip6_spec.ip6src, 4);
4107
4108                 be32_to_cpu_array(rule->tuples.dst_ip,
4109                                   fs->h_u.tcp_ip6_spec.ip6dst, 4);
4110                 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4111                                   fs->m_u.tcp_ip6_spec.ip6dst, 4);
4112
4113                 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc);
4114                 rule->tuples_mask.src_port =
4115                                 be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc);
4116
4117                 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst);
4118                 rule->tuples_mask.dst_port =
4119                                 be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst);
4120
4121                 rule->tuples.ether_proto = ETH_P_IPV6;
4122                 rule->tuples_mask.ether_proto = 0xFFFF;
4123
4124                 break;
4125         case IPV6_USER_FLOW:
4126                 be32_to_cpu_array(rule->tuples.src_ip,
4127                                   fs->h_u.usr_ip6_spec.ip6src, 4);
4128                 be32_to_cpu_array(rule->tuples_mask.src_ip,
4129                                   fs->m_u.usr_ip6_spec.ip6src, 4);
4130
4131                 be32_to_cpu_array(rule->tuples.dst_ip,
4132                                   fs->h_u.usr_ip6_spec.ip6dst, 4);
4133                 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4134                                   fs->m_u.usr_ip6_spec.ip6dst, 4);
4135
4136                 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto;
4137                 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto;
4138
4139                 rule->tuples.ether_proto = ETH_P_IPV6;
4140                 rule->tuples_mask.ether_proto = 0xFFFF;
4141
4142                 break;
4143         case ETHER_FLOW:
4144                 ether_addr_copy(rule->tuples.src_mac,
4145                                 fs->h_u.ether_spec.h_source);
4146                 ether_addr_copy(rule->tuples_mask.src_mac,
4147                                 fs->m_u.ether_spec.h_source);
4148
4149                 ether_addr_copy(rule->tuples.dst_mac,
4150                                 fs->h_u.ether_spec.h_dest);
4151                 ether_addr_copy(rule->tuples_mask.dst_mac,
4152                                 fs->m_u.ether_spec.h_dest);
4153
4154                 rule->tuples.ether_proto =
4155                                 be16_to_cpu(fs->h_u.ether_spec.h_proto);
4156                 rule->tuples_mask.ether_proto =
4157                                 be16_to_cpu(fs->m_u.ether_spec.h_proto);
4158
4159                 break;
4160         default:
4161                 return -EOPNOTSUPP;
4162         }
4163
4164         switch (flow_type) {
4165         case SCTP_V4_FLOW:
4166         case SCTP_V6_FLOW:
4167                 rule->tuples.ip_proto = IPPROTO_SCTP;
4168                 rule->tuples_mask.ip_proto = 0xFF;
4169                 break;
4170         case TCP_V4_FLOW:
4171         case TCP_V6_FLOW:
4172                 rule->tuples.ip_proto = IPPROTO_TCP;
4173                 rule->tuples_mask.ip_proto = 0xFF;
4174                 break;
4175         case UDP_V4_FLOW:
4176         case UDP_V6_FLOW:
4177                 rule->tuples.ip_proto = IPPROTO_UDP;
4178                 rule->tuples_mask.ip_proto = 0xFF;
4179                 break;
4180         default:
4181                 break;
4182         }
4183
4184         if ((fs->flow_type & FLOW_EXT)) {
4185                 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci);
4186                 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci);
4187         }
4188
4189         if (fs->flow_type & FLOW_MAC_EXT) {
4190                 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest);
4191                 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest);
4192         }
4193
4194         return 0;
4195 }
4196
4197 static int hclge_add_fd_entry(struct hnae3_handle *handle,
4198                               struct ethtool_rxnfc *cmd)
4199 {
4200         struct hclge_vport *vport = hclge_get_vport(handle);
4201         struct hclge_dev *hdev = vport->back;
4202         u16 dst_vport_id = 0, q_index = 0;
4203         struct ethtool_rx_flow_spec *fs;
4204         struct hclge_fd_rule *rule;
4205         u32 unused = 0;
4206         u8 action;
4207         int ret;
4208
4209         if (!hnae3_dev_fd_supported(hdev))
4210                 return -EOPNOTSUPP;
4211
4212         if (!hdev->fd_cfg.fd_en) {
4213                 dev_warn(&hdev->pdev->dev,
4214                          "Please enable flow director first\n");
4215                 return -EOPNOTSUPP;
4216         }
4217
4218         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4219
4220         ret = hclge_fd_check_spec(hdev, fs, &unused);
4221         if (ret) {
4222                 dev_err(&hdev->pdev->dev, "Check fd spec failed\n");
4223                 return ret;
4224         }
4225
4226         if (fs->ring_cookie == RX_CLS_FLOW_DISC) {
4227                 action = HCLGE_FD_ACTION_DROP_PACKET;
4228         } else {
4229                 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
4230                 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
4231                 u16 tqps;
4232
4233                 dst_vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id;
4234                 tqps = vf ? hdev->vport[vf].alloc_tqps : vport->alloc_tqps;
4235
4236                 if (ring >= tqps) {
4237                         dev_err(&hdev->pdev->dev,
4238                                 "Error: queue id (%d) > max tqp num (%d)\n",
4239                                 ring, tqps - 1);
4240                         return -EINVAL;
4241                 }
4242
4243                 if (vf > hdev->num_req_vfs) {
4244                         dev_err(&hdev->pdev->dev,
4245                                 "Error: vf id (%d) > max vf num (%d)\n",
4246                                 vf, hdev->num_req_vfs);
4247                         return -EINVAL;
4248                 }
4249
4250                 action = HCLGE_FD_ACTION_ACCEPT_PACKET;
4251                 q_index = ring;
4252         }
4253
4254         rule = kzalloc(sizeof(*rule), GFP_KERNEL);
4255         if (!rule)
4256                 return -ENOMEM;
4257
4258         ret = hclge_fd_get_tuple(hdev, fs, rule);
4259         if (ret)
4260                 goto free_rule;
4261
4262         rule->flow_type = fs->flow_type;
4263
4264         rule->location = fs->location;
4265         rule->unused_tuple = unused;
4266         rule->vf_id = dst_vport_id;
4267         rule->queue_id = q_index;
4268         rule->action = action;
4269
4270         ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4271         if (ret)
4272                 goto free_rule;
4273
4274         ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4275         if (ret)
4276                 goto free_rule;
4277
4278         ret = hclge_fd_update_rule_list(hdev, rule, fs->location, true);
4279         if (ret)
4280                 goto free_rule;
4281
4282         return ret;
4283
4284 free_rule:
4285         kfree(rule);
4286         return ret;
4287 }
4288
4289 static int hclge_del_fd_entry(struct hnae3_handle *handle,
4290                               struct ethtool_rxnfc *cmd)
4291 {
4292         struct hclge_vport *vport = hclge_get_vport(handle);
4293         struct hclge_dev *hdev = vport->back;
4294         struct ethtool_rx_flow_spec *fs;
4295         int ret;
4296
4297         if (!hnae3_dev_fd_supported(hdev))
4298                 return -EOPNOTSUPP;
4299
4300         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4301
4302         if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
4303                 return -EINVAL;
4304
4305         if (!hclge_fd_rule_exist(hdev, fs->location)) {
4306                 dev_err(&hdev->pdev->dev,
4307                         "Delete fail, rule %d is inexistent\n",
4308                         fs->location);
4309                 return -ENOENT;
4310         }
4311
4312         ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4313                                    fs->location, NULL, false);
4314         if (ret)
4315                 return ret;
4316
4317         return hclge_fd_update_rule_list(hdev, NULL, fs->location,
4318                                          false);
4319 }
4320
4321 static void hclge_del_all_fd_entries(struct hnae3_handle *handle,
4322                                      bool clear_list)
4323 {
4324         struct hclge_vport *vport = hclge_get_vport(handle);
4325         struct hclge_dev *hdev = vport->back;
4326         struct hclge_fd_rule *rule;
4327         struct hlist_node *node;
4328
4329         if (!hnae3_dev_fd_supported(hdev))
4330                 return;
4331
4332         if (clear_list) {
4333                 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4334                                           rule_node) {
4335                         hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4336                                              rule->location, NULL, false);
4337                         hlist_del(&rule->rule_node);
4338                         kfree(rule);
4339                         hdev->hclge_fd_rule_num--;
4340                 }
4341         } else {
4342                 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4343                                           rule_node)
4344                         hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4345                                              rule->location, NULL, false);
4346         }
4347 }
4348
4349 static int hclge_restore_fd_entries(struct hnae3_handle *handle)
4350 {
4351         struct hclge_vport *vport = hclge_get_vport(handle);
4352         struct hclge_dev *hdev = vport->back;
4353         struct hclge_fd_rule *rule;
4354         struct hlist_node *node;
4355         int ret;
4356
4357         if (!hnae3_dev_fd_supported(hdev))
4358                 return -EOPNOTSUPP;
4359
4360         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
4361                 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4362                 if (!ret)
4363                         ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4364
4365                 if (ret) {
4366                         dev_warn(&hdev->pdev->dev,
4367                                  "Restore rule %d failed, remove it\n",
4368                                  rule->location);
4369                         hlist_del(&rule->rule_node);
4370                         kfree(rule);
4371                         hdev->hclge_fd_rule_num--;
4372                 }
4373         }
4374         return 0;
4375 }
4376
4377 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle,
4378                                  struct ethtool_rxnfc *cmd)
4379 {
4380         struct hclge_vport *vport = hclge_get_vport(handle);
4381         struct hclge_dev *hdev = vport->back;
4382
4383         if (!hnae3_dev_fd_supported(hdev))
4384                 return -EOPNOTSUPP;
4385
4386         cmd->rule_cnt = hdev->hclge_fd_rule_num;
4387         cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
4388
4389         return 0;
4390 }
4391
4392 static int hclge_get_fd_rule_info(struct hnae3_handle *handle,
4393                                   struct ethtool_rxnfc *cmd)
4394 {
4395         struct hclge_vport *vport = hclge_get_vport(handle);
4396         struct hclge_fd_rule *rule = NULL;
4397         struct hclge_dev *hdev = vport->back;
4398         struct ethtool_rx_flow_spec *fs;
4399         struct hlist_node *node2;
4400
4401         if (!hnae3_dev_fd_supported(hdev))
4402                 return -EOPNOTSUPP;
4403
4404         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4405
4406         hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
4407                 if (rule->location >= fs->location)
4408                         break;
4409         }
4410
4411         if (!rule || fs->location != rule->location)
4412                 return -ENOENT;
4413
4414         fs->flow_type = rule->flow_type;
4415         switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
4416         case SCTP_V4_FLOW:
4417         case TCP_V4_FLOW:
4418         case UDP_V4_FLOW:
4419                 fs->h_u.tcp_ip4_spec.ip4src =
4420                                 cpu_to_be32(rule->tuples.src_ip[3]);
4421                 fs->m_u.tcp_ip4_spec.ip4src =
4422                                 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4423                                 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4424
4425                 fs->h_u.tcp_ip4_spec.ip4dst =
4426                                 cpu_to_be32(rule->tuples.dst_ip[3]);
4427                 fs->m_u.tcp_ip4_spec.ip4dst =
4428                                 rule->unused_tuple & BIT(INNER_DST_IP) ?
4429                                 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4430
4431                 fs->h_u.tcp_ip4_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4432                 fs->m_u.tcp_ip4_spec.psrc =
4433                                 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4434                                 0 : cpu_to_be16(rule->tuples_mask.src_port);
4435
4436                 fs->h_u.tcp_ip4_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4437                 fs->m_u.tcp_ip4_spec.pdst =
4438                                 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4439                                 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4440
4441                 fs->h_u.tcp_ip4_spec.tos = rule->tuples.ip_tos;
4442                 fs->m_u.tcp_ip4_spec.tos =
4443                                 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4444                                 0 : rule->tuples_mask.ip_tos;
4445
4446                 break;
4447         case IP_USER_FLOW:
4448                 fs->h_u.usr_ip4_spec.ip4src =
4449                                 cpu_to_be32(rule->tuples.src_ip[3]);
4450                 fs->m_u.tcp_ip4_spec.ip4src =
4451                                 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4452                                 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4453
4454                 fs->h_u.usr_ip4_spec.ip4dst =
4455                                 cpu_to_be32(rule->tuples.dst_ip[3]);
4456                 fs->m_u.usr_ip4_spec.ip4dst =
4457                                 rule->unused_tuple & BIT(INNER_DST_IP) ?
4458                                 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4459
4460                 fs->h_u.usr_ip4_spec.tos = rule->tuples.ip_tos;
4461                 fs->m_u.usr_ip4_spec.tos =
4462                                 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4463                                 0 : rule->tuples_mask.ip_tos;
4464
4465                 fs->h_u.usr_ip4_spec.proto = rule->tuples.ip_proto;
4466                 fs->m_u.usr_ip4_spec.proto =
4467                                 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4468                                 0 : rule->tuples_mask.ip_proto;
4469
4470                 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
4471
4472                 break;
4473         case SCTP_V6_FLOW:
4474         case TCP_V6_FLOW:
4475         case UDP_V6_FLOW:
4476                 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6src,
4477                                   rule->tuples.src_ip, 4);
4478                 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4479                         memset(fs->m_u.tcp_ip6_spec.ip6src, 0, sizeof(int) * 4);
4480                 else
4481                         cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6src,
4482                                           rule->tuples_mask.src_ip, 4);
4483
4484                 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6dst,
4485                                   rule->tuples.dst_ip, 4);
4486                 if (rule->unused_tuple & BIT(INNER_DST_IP))
4487                         memset(fs->m_u.tcp_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4488                 else
4489                         cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6dst,
4490                                           rule->tuples_mask.dst_ip, 4);
4491
4492                 fs->h_u.tcp_ip6_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4493                 fs->m_u.tcp_ip6_spec.psrc =
4494                                 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4495                                 0 : cpu_to_be16(rule->tuples_mask.src_port);
4496
4497                 fs->h_u.tcp_ip6_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4498                 fs->m_u.tcp_ip6_spec.pdst =
4499                                 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4500                                 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4501
4502                 break;
4503         case IPV6_USER_FLOW:
4504                 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6src,
4505                                   rule->tuples.src_ip, 4);
4506                 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4507                         memset(fs->m_u.usr_ip6_spec.ip6src, 0, sizeof(int) * 4);
4508                 else
4509                         cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6src,
4510                                           rule->tuples_mask.src_ip, 4);
4511
4512                 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6dst,
4513                                   rule->tuples.dst_ip, 4);
4514                 if (rule->unused_tuple & BIT(INNER_DST_IP))
4515                         memset(fs->m_u.usr_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4516                 else
4517                         cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6dst,
4518                                           rule->tuples_mask.dst_ip, 4);
4519
4520                 fs->h_u.usr_ip6_spec.l4_proto = rule->tuples.ip_proto;
4521                 fs->m_u.usr_ip6_spec.l4_proto =
4522                                 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4523                                 0 : rule->tuples_mask.ip_proto;
4524
4525                 break;
4526         case ETHER_FLOW:
4527                 ether_addr_copy(fs->h_u.ether_spec.h_source,
4528                                 rule->tuples.src_mac);
4529                 if (rule->unused_tuple & BIT(INNER_SRC_MAC))
4530                         eth_zero_addr(fs->m_u.ether_spec.h_source);
4531                 else
4532                         ether_addr_copy(fs->m_u.ether_spec.h_source,
4533                                         rule->tuples_mask.src_mac);
4534
4535                 ether_addr_copy(fs->h_u.ether_spec.h_dest,
4536                                 rule->tuples.dst_mac);
4537                 if (rule->unused_tuple & BIT(INNER_DST_MAC))
4538                         eth_zero_addr(fs->m_u.ether_spec.h_dest);
4539                 else
4540                         ether_addr_copy(fs->m_u.ether_spec.h_dest,
4541                                         rule->tuples_mask.dst_mac);
4542
4543                 fs->h_u.ether_spec.h_proto =
4544                                 cpu_to_be16(rule->tuples.ether_proto);
4545                 fs->m_u.ether_spec.h_proto =
4546                                 rule->unused_tuple & BIT(INNER_ETH_TYPE) ?
4547                                 0 : cpu_to_be16(rule->tuples_mask.ether_proto);
4548
4549                 break;
4550         default:
4551                 return -EOPNOTSUPP;
4552         }
4553
4554         if (fs->flow_type & FLOW_EXT) {
4555                 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1);
4556                 fs->m_ext.vlan_tci =
4557                                 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ?
4558                                 cpu_to_be16(VLAN_VID_MASK) :
4559                                 cpu_to_be16(rule->tuples_mask.vlan_tag1);
4560         }
4561
4562         if (fs->flow_type & FLOW_MAC_EXT) {
4563                 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac);
4564                 if (rule->unused_tuple & BIT(INNER_DST_MAC))
4565                         eth_zero_addr(fs->m_u.ether_spec.h_dest);
4566                 else
4567                         ether_addr_copy(fs->m_u.ether_spec.h_dest,
4568                                         rule->tuples_mask.dst_mac);
4569         }
4570
4571         if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
4572                 fs->ring_cookie = RX_CLS_FLOW_DISC;
4573         } else {
4574                 u64 vf_id;
4575
4576                 fs->ring_cookie = rule->queue_id;
4577                 vf_id = rule->vf_id;
4578                 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
4579                 fs->ring_cookie |= vf_id;
4580         }
4581
4582         return 0;
4583 }
4584
4585 static int hclge_get_all_rules(struct hnae3_handle *handle,
4586                                struct ethtool_rxnfc *cmd, u32 *rule_locs)
4587 {
4588         struct hclge_vport *vport = hclge_get_vport(handle);
4589         struct hclge_dev *hdev = vport->back;
4590         struct hclge_fd_rule *rule;
4591         struct hlist_node *node2;
4592         int cnt = 0;
4593
4594         if (!hnae3_dev_fd_supported(hdev))
4595                 return -EOPNOTSUPP;
4596
4597         cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
4598
4599         hlist_for_each_entry_safe(rule, node2,
4600                                   &hdev->fd_rule_list, rule_node) {
4601                 if (cnt == cmd->rule_cnt)
4602                         return -EMSGSIZE;
4603
4604                 rule_locs[cnt] = rule->location;
4605                 cnt++;
4606         }
4607
4608         cmd->rule_cnt = cnt;
4609
4610         return 0;
4611 }
4612
4613 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle)
4614 {
4615         struct hclge_vport *vport = hclge_get_vport(handle);
4616         struct hclge_dev *hdev = vport->back;
4617
4618         return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) ||
4619                hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING);
4620 }
4621
4622 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle)
4623 {
4624         struct hclge_vport *vport = hclge_get_vport(handle);
4625         struct hclge_dev *hdev = vport->back;
4626
4627         return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
4628 }
4629
4630 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle)
4631 {
4632         struct hclge_vport *vport = hclge_get_vport(handle);
4633         struct hclge_dev *hdev = vport->back;
4634
4635         return hdev->reset_count;
4636 }
4637
4638 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable)
4639 {
4640         struct hclge_vport *vport = hclge_get_vport(handle);
4641         struct hclge_dev *hdev = vport->back;
4642
4643         hdev->fd_cfg.fd_en = enable;
4644         if (!enable)
4645                 hclge_del_all_fd_entries(handle, false);
4646         else
4647                 hclge_restore_fd_entries(handle);
4648 }
4649
4650 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
4651 {
4652         struct hclge_desc desc;
4653         struct hclge_config_mac_mode_cmd *req =
4654                 (struct hclge_config_mac_mode_cmd *)desc.data;
4655         u32 loop_en = 0;
4656         int ret;
4657
4658         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
4659         hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
4660         hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
4661         hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
4662         hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
4663         hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
4664         hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
4665         hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
4666         hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
4667         hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
4668         hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
4669         hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
4670         hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
4671         hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
4672         hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
4673         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
4674
4675         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4676         if (ret)
4677                 dev_err(&hdev->pdev->dev,
4678                         "mac enable fail, ret =%d.\n", ret);
4679 }
4680
4681 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
4682 {
4683         struct hclge_config_mac_mode_cmd *req;
4684         struct hclge_desc desc;
4685         u32 loop_en;
4686         int ret;
4687
4688         req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
4689         /* 1 Read out the MAC mode config at first */
4690         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
4691         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4692         if (ret) {
4693                 dev_err(&hdev->pdev->dev,
4694                         "mac loopback get fail, ret =%d.\n", ret);
4695                 return ret;
4696         }
4697
4698         /* 2 Then setup the loopback flag */
4699         loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
4700         hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
4701         hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, en ? 1 : 0);
4702         hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, en ? 1 : 0);
4703
4704         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
4705
4706         /* 3 Config mac work mode with loopback flag
4707          * and its original configure parameters
4708          */
4709         hclge_cmd_reuse_desc(&desc, false);
4710         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4711         if (ret)
4712                 dev_err(&hdev->pdev->dev,
4713                         "mac loopback set fail, ret =%d.\n", ret);
4714         return ret;
4715 }
4716
4717 static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en,
4718                                      enum hnae3_loop loop_mode)
4719 {
4720 #define HCLGE_SERDES_RETRY_MS   10
4721 #define HCLGE_SERDES_RETRY_NUM  100
4722         struct hclge_serdes_lb_cmd *req;
4723         struct hclge_desc desc;
4724         int ret, i = 0;
4725         u8 loop_mode_b;
4726
4727         req = (struct hclge_serdes_lb_cmd *)desc.data;
4728         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
4729
4730         switch (loop_mode) {
4731         case HNAE3_LOOP_SERIAL_SERDES:
4732                 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
4733                 break;
4734         case HNAE3_LOOP_PARALLEL_SERDES:
4735                 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
4736                 break;
4737         default:
4738                 dev_err(&hdev->pdev->dev,
4739                         "unsupported serdes loopback mode %d\n", loop_mode);
4740                 return -ENOTSUPP;
4741         }
4742
4743         if (en) {
4744                 req->enable = loop_mode_b;
4745                 req->mask = loop_mode_b;
4746         } else {
4747                 req->mask = loop_mode_b;
4748         }
4749
4750         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4751         if (ret) {
4752                 dev_err(&hdev->pdev->dev,
4753                         "serdes loopback set fail, ret = %d\n", ret);
4754                 return ret;
4755         }
4756
4757         do {
4758                 msleep(HCLGE_SERDES_RETRY_MS);
4759                 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
4760                                            true);
4761                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4762                 if (ret) {
4763                         dev_err(&hdev->pdev->dev,
4764                                 "serdes loopback get, ret = %d\n", ret);
4765                         return ret;
4766                 }
4767         } while (++i < HCLGE_SERDES_RETRY_NUM &&
4768                  !(req->result & HCLGE_CMD_SERDES_DONE_B));
4769
4770         if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
4771                 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
4772                 return -EBUSY;
4773         } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
4774                 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
4775                 return -EIO;
4776         }
4777
4778         hclge_cfg_mac_mode(hdev, en);
4779         return 0;
4780 }
4781
4782 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
4783                             int stream_id, bool enable)
4784 {
4785         struct hclge_desc desc;
4786         struct hclge_cfg_com_tqp_queue_cmd *req =
4787                 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
4788         int ret;
4789
4790         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
4791         req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
4792         req->stream_id = cpu_to_le16(stream_id);
4793         req->enable |= enable << HCLGE_TQP_ENABLE_B;
4794
4795         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4796         if (ret)
4797                 dev_err(&hdev->pdev->dev,
4798                         "Tqp enable fail, status =%d.\n", ret);
4799         return ret;
4800 }
4801
4802 static int hclge_set_loopback(struct hnae3_handle *handle,
4803                               enum hnae3_loop loop_mode, bool en)
4804 {
4805         struct hclge_vport *vport = hclge_get_vport(handle);
4806         struct hclge_dev *hdev = vport->back;
4807         int i, ret;
4808
4809         switch (loop_mode) {
4810         case HNAE3_LOOP_APP:
4811                 ret = hclge_set_app_loopback(hdev, en);
4812                 break;
4813         case HNAE3_LOOP_SERIAL_SERDES:
4814         case HNAE3_LOOP_PARALLEL_SERDES:
4815                 ret = hclge_set_serdes_loopback(hdev, en, loop_mode);
4816                 break;
4817         default:
4818                 ret = -ENOTSUPP;
4819                 dev_err(&hdev->pdev->dev,
4820                         "loop_mode %d is not supported\n", loop_mode);
4821                 break;
4822         }
4823
4824         for (i = 0; i < vport->alloc_tqps; i++) {
4825                 ret = hclge_tqp_enable(hdev, i, 0, en);
4826                 if (ret)
4827                         return ret;
4828         }
4829
4830         return 0;
4831 }
4832
4833 static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
4834 {
4835         struct hclge_vport *vport = hclge_get_vport(handle);
4836         struct hnae3_queue *queue;
4837         struct hclge_tqp *tqp;
4838         int i;
4839
4840         for (i = 0; i < vport->alloc_tqps; i++) {
4841                 queue = handle->kinfo.tqp[i];
4842                 tqp = container_of(queue, struct hclge_tqp, q);
4843                 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
4844         }
4845 }
4846
4847 static int hclge_ae_start(struct hnae3_handle *handle)
4848 {
4849         struct hclge_vport *vport = hclge_get_vport(handle);
4850         struct hclge_dev *hdev = vport->back;
4851
4852         /* mac enable */
4853         hclge_cfg_mac_mode(hdev, true);
4854         clear_bit(HCLGE_STATE_DOWN, &hdev->state);
4855         mod_timer(&hdev->service_timer, jiffies + HZ);
4856         hdev->hw.mac.link = 0;
4857
4858         /* reset tqp stats */
4859         hclge_reset_tqp_stats(handle);
4860
4861         hclge_mac_start_phy(hdev);
4862
4863         return 0;
4864 }
4865
4866 static void hclge_ae_stop(struct hnae3_handle *handle)
4867 {
4868         struct hclge_vport *vport = hclge_get_vport(handle);
4869         struct hclge_dev *hdev = vport->back;
4870
4871         set_bit(HCLGE_STATE_DOWN, &hdev->state);
4872
4873         del_timer_sync(&hdev->service_timer);
4874         cancel_work_sync(&hdev->service_task);
4875         clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
4876
4877         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
4878                 hclge_mac_stop_phy(hdev);
4879                 return;
4880         }
4881
4882         /* Mac disable */
4883         hclge_cfg_mac_mode(hdev, false);
4884
4885         hclge_mac_stop_phy(hdev);
4886
4887         /* reset tqp stats */
4888         hclge_reset_tqp_stats(handle);
4889         del_timer_sync(&hdev->service_timer);
4890         cancel_work_sync(&hdev->service_task);
4891         hclge_update_link_status(hdev);
4892 }
4893
4894 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
4895                                          u16 cmdq_resp, u8  resp_code,
4896                                          enum hclge_mac_vlan_tbl_opcode op)
4897 {
4898         struct hclge_dev *hdev = vport->back;
4899         int return_status = -EIO;
4900
4901         if (cmdq_resp) {
4902                 dev_err(&hdev->pdev->dev,
4903                         "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
4904                         cmdq_resp);
4905                 return -EIO;
4906         }
4907
4908         if (op == HCLGE_MAC_VLAN_ADD) {
4909                 if ((!resp_code) || (resp_code == 1)) {
4910                         return_status = 0;
4911                 } else if (resp_code == 2) {
4912                         return_status = -ENOSPC;
4913                         dev_err(&hdev->pdev->dev,
4914                                 "add mac addr failed for uc_overflow.\n");
4915                 } else if (resp_code == 3) {
4916                         return_status = -ENOSPC;
4917                         dev_err(&hdev->pdev->dev,
4918                                 "add mac addr failed for mc_overflow.\n");
4919                 } else {
4920                         dev_err(&hdev->pdev->dev,
4921                                 "add mac addr failed for undefined, code=%d.\n",
4922                                 resp_code);
4923                 }
4924         } else if (op == HCLGE_MAC_VLAN_REMOVE) {
4925                 if (!resp_code) {
4926                         return_status = 0;
4927                 } else if (resp_code == 1) {
4928                         return_status = -ENOENT;
4929                         dev_dbg(&hdev->pdev->dev,
4930                                 "remove mac addr failed for miss.\n");
4931                 } else {
4932                         dev_err(&hdev->pdev->dev,
4933                                 "remove mac addr failed for undefined, code=%d.\n",
4934                                 resp_code);
4935                 }
4936         } else if (op == HCLGE_MAC_VLAN_LKUP) {
4937                 if (!resp_code) {
4938                         return_status = 0;
4939                 } else if (resp_code == 1) {
4940                         return_status = -ENOENT;
4941                         dev_dbg(&hdev->pdev->dev,
4942                                 "lookup mac addr failed for miss.\n");
4943                 } else {
4944                         dev_err(&hdev->pdev->dev,
4945                                 "lookup mac addr failed for undefined, code=%d.\n",
4946                                 resp_code);
4947                 }
4948         } else {
4949                 return_status = -EINVAL;
4950                 dev_err(&hdev->pdev->dev,
4951                         "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
4952                         op);
4953         }
4954
4955         return return_status;
4956 }
4957
4958 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
4959 {
4960         int word_num;
4961         int bit_num;
4962
4963         if (vfid > 255 || vfid < 0)
4964                 return -EIO;
4965
4966         if (vfid >= 0 && vfid <= 191) {
4967                 word_num = vfid / 32;
4968                 bit_num  = vfid % 32;
4969                 if (clr)
4970                         desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
4971                 else
4972                         desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
4973         } else {
4974                 word_num = (vfid - 192) / 32;
4975                 bit_num  = vfid % 32;
4976                 if (clr)
4977                         desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
4978                 else
4979                         desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
4980         }
4981
4982         return 0;
4983 }
4984
4985 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
4986 {
4987 #define HCLGE_DESC_NUMBER 3
4988 #define HCLGE_FUNC_NUMBER_PER_DESC 6
4989         int i, j;
4990
4991         for (i = 1; i < HCLGE_DESC_NUMBER; i++)
4992                 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
4993                         if (desc[i].data[j])
4994                                 return false;
4995
4996         return true;
4997 }
4998
4999 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
5000                                    const u8 *addr)
5001 {
5002         const unsigned char *mac_addr = addr;
5003         u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
5004                        (mac_addr[0]) | (mac_addr[1] << 8);
5005         u32 low_val  = mac_addr[4] | (mac_addr[5] << 8);
5006
5007         new_req->mac_addr_hi32 = cpu_to_le32(high_val);
5008         new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
5009 }
5010
5011 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
5012                                      struct hclge_mac_vlan_tbl_entry_cmd *req)
5013 {
5014         struct hclge_dev *hdev = vport->back;
5015         struct hclge_desc desc;
5016         u8 resp_code;
5017         u16 retval;
5018         int ret;
5019
5020         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
5021
5022         memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5023
5024         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5025         if (ret) {
5026                 dev_err(&hdev->pdev->dev,
5027                         "del mac addr failed for cmd_send, ret =%d.\n",
5028                         ret);
5029                 return ret;
5030         }
5031         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5032         retval = le16_to_cpu(desc.retval);
5033
5034         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
5035                                              HCLGE_MAC_VLAN_REMOVE);
5036 }
5037
5038 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
5039                                      struct hclge_mac_vlan_tbl_entry_cmd *req,
5040                                      struct hclge_desc *desc,
5041                                      bool is_mc)
5042 {
5043         struct hclge_dev *hdev = vport->back;
5044         u8 resp_code;
5045         u16 retval;
5046         int ret;
5047
5048         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
5049         if (is_mc) {
5050                 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5051                 memcpy(desc[0].data,
5052                        req,
5053                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5054                 hclge_cmd_setup_basic_desc(&desc[1],
5055                                            HCLGE_OPC_MAC_VLAN_ADD,
5056                                            true);
5057                 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5058                 hclge_cmd_setup_basic_desc(&desc[2],
5059                                            HCLGE_OPC_MAC_VLAN_ADD,
5060                                            true);
5061                 ret = hclge_cmd_send(&hdev->hw, desc, 3);
5062         } else {
5063                 memcpy(desc[0].data,
5064                        req,
5065                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5066                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
5067         }
5068         if (ret) {
5069                 dev_err(&hdev->pdev->dev,
5070                         "lookup mac addr failed for cmd_send, ret =%d.\n",
5071                         ret);
5072                 return ret;
5073         }
5074         resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
5075         retval = le16_to_cpu(desc[0].retval);
5076
5077         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
5078                                              HCLGE_MAC_VLAN_LKUP);
5079 }
5080
5081 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
5082                                   struct hclge_mac_vlan_tbl_entry_cmd *req,
5083                                   struct hclge_desc *mc_desc)
5084 {
5085         struct hclge_dev *hdev = vport->back;
5086         int cfg_status;
5087         u8 resp_code;
5088         u16 retval;
5089         int ret;
5090
5091         if (!mc_desc) {
5092                 struct hclge_desc desc;
5093
5094                 hclge_cmd_setup_basic_desc(&desc,
5095                                            HCLGE_OPC_MAC_VLAN_ADD,
5096                                            false);
5097                 memcpy(desc.data, req,
5098                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5099                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5100                 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5101                 retval = le16_to_cpu(desc.retval);
5102
5103                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
5104                                                            resp_code,
5105                                                            HCLGE_MAC_VLAN_ADD);
5106         } else {
5107                 hclge_cmd_reuse_desc(&mc_desc[0], false);
5108                 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5109                 hclge_cmd_reuse_desc(&mc_desc[1], false);
5110                 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5111                 hclge_cmd_reuse_desc(&mc_desc[2], false);
5112                 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
5113                 memcpy(mc_desc[0].data, req,
5114                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5115                 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
5116                 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
5117                 retval = le16_to_cpu(mc_desc[0].retval);
5118
5119                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
5120                                                            resp_code,
5121                                                            HCLGE_MAC_VLAN_ADD);
5122         }
5123
5124         if (ret) {
5125                 dev_err(&hdev->pdev->dev,
5126                         "add mac addr failed for cmd_send, ret =%d.\n",
5127                         ret);
5128                 return ret;
5129         }
5130
5131         return cfg_status;
5132 }
5133
5134 static int hclge_init_umv_space(struct hclge_dev *hdev)
5135 {
5136         u16 allocated_size = 0;
5137         int ret;
5138
5139         ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size,
5140                                   true);
5141         if (ret)
5142                 return ret;
5143
5144         if (allocated_size < hdev->wanted_umv_size)
5145                 dev_warn(&hdev->pdev->dev,
5146                          "Alloc umv space failed, want %d, get %d\n",
5147                          hdev->wanted_umv_size, allocated_size);
5148
5149         mutex_init(&hdev->umv_mutex);
5150         hdev->max_umv_size = allocated_size;
5151         hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_req_vfs + 2);
5152         hdev->share_umv_size = hdev->priv_umv_size +
5153                         hdev->max_umv_size % (hdev->num_req_vfs + 2);
5154
5155         return 0;
5156 }
5157
5158 static int hclge_uninit_umv_space(struct hclge_dev *hdev)
5159 {
5160         int ret;
5161
5162         if (hdev->max_umv_size > 0) {
5163                 ret = hclge_set_umv_space(hdev, hdev->max_umv_size, NULL,
5164                                           false);
5165                 if (ret)
5166                         return ret;
5167                 hdev->max_umv_size = 0;
5168         }
5169         mutex_destroy(&hdev->umv_mutex);
5170
5171         return 0;
5172 }
5173
5174 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
5175                                u16 *allocated_size, bool is_alloc)
5176 {
5177         struct hclge_umv_spc_alc_cmd *req;
5178         struct hclge_desc desc;
5179         int ret;
5180
5181         req = (struct hclge_umv_spc_alc_cmd *)desc.data;
5182         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false);
5183         hnae3_set_bit(req->allocate, HCLGE_UMV_SPC_ALC_B, !is_alloc);
5184         req->space_size = cpu_to_le32(space_size);
5185
5186         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5187         if (ret) {
5188                 dev_err(&hdev->pdev->dev,
5189                         "%s umv space failed for cmd_send, ret =%d\n",
5190                         is_alloc ? "allocate" : "free", ret);
5191                 return ret;
5192         }
5193
5194         if (is_alloc && allocated_size)
5195                 *allocated_size = le32_to_cpu(desc.data[1]);
5196
5197         return 0;
5198 }
5199
5200 static void hclge_reset_umv_space(struct hclge_dev *hdev)
5201 {
5202         struct hclge_vport *vport;
5203         int i;
5204
5205         for (i = 0; i < hdev->num_alloc_vport; i++) {
5206                 vport = &hdev->vport[i];
5207                 vport->used_umv_num = 0;
5208         }
5209
5210         mutex_lock(&hdev->umv_mutex);
5211         hdev->share_umv_size = hdev->priv_umv_size +
5212                         hdev->max_umv_size % (hdev->num_req_vfs + 2);
5213         mutex_unlock(&hdev->umv_mutex);
5214 }
5215
5216 static bool hclge_is_umv_space_full(struct hclge_vport *vport)
5217 {
5218         struct hclge_dev *hdev = vport->back;
5219         bool is_full;
5220
5221         mutex_lock(&hdev->umv_mutex);
5222         is_full = (vport->used_umv_num >= hdev->priv_umv_size &&
5223                    hdev->share_umv_size == 0);
5224         mutex_unlock(&hdev->umv_mutex);
5225
5226         return is_full;
5227 }
5228
5229 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free)
5230 {
5231         struct hclge_dev *hdev = vport->back;
5232
5233         mutex_lock(&hdev->umv_mutex);
5234         if (is_free) {
5235                 if (vport->used_umv_num > hdev->priv_umv_size)
5236                         hdev->share_umv_size++;
5237                 vport->used_umv_num--;
5238         } else {
5239                 if (vport->used_umv_num >= hdev->priv_umv_size)
5240                         hdev->share_umv_size--;
5241                 vport->used_umv_num++;
5242         }
5243         mutex_unlock(&hdev->umv_mutex);
5244 }
5245
5246 static int hclge_add_uc_addr(struct hnae3_handle *handle,
5247                              const unsigned char *addr)
5248 {
5249         struct hclge_vport *vport = hclge_get_vport(handle);
5250
5251         return hclge_add_uc_addr_common(vport, addr);
5252 }
5253
5254 int hclge_add_uc_addr_common(struct hclge_vport *vport,
5255                              const unsigned char *addr)
5256 {
5257         struct hclge_dev *hdev = vport->back;
5258         struct hclge_mac_vlan_tbl_entry_cmd req;
5259         struct hclge_desc desc;
5260         u16 egress_port = 0;
5261         int ret;
5262
5263         /* mac addr check */
5264         if (is_zero_ether_addr(addr) ||
5265             is_broadcast_ether_addr(addr) ||
5266             is_multicast_ether_addr(addr)) {
5267                 dev_err(&hdev->pdev->dev,
5268                         "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
5269                          addr,
5270                          is_zero_ether_addr(addr),
5271                          is_broadcast_ether_addr(addr),
5272                          is_multicast_ether_addr(addr));
5273                 return -EINVAL;
5274         }
5275
5276         memset(&req, 0, sizeof(req));
5277         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5278
5279         hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
5280                         HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
5281
5282         req.egress_port = cpu_to_le16(egress_port);
5283
5284         hclge_prepare_mac_addr(&req, addr);
5285
5286         /* Lookup the mac address in the mac_vlan table, and add
5287          * it if the entry is inexistent. Repeated unicast entry
5288          * is not allowed in the mac vlan table.
5289          */
5290         ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
5291         if (ret == -ENOENT) {
5292                 if (!hclge_is_umv_space_full(vport)) {
5293                         ret = hclge_add_mac_vlan_tbl(vport, &req, NULL);
5294                         if (!ret)
5295                                 hclge_update_umv_space(vport, false);
5296                         return ret;
5297                 }
5298
5299                 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n",
5300                         hdev->priv_umv_size);
5301
5302                 return -ENOSPC;
5303         }
5304
5305         /* check if we just hit the duplicate */
5306         if (!ret)
5307                 ret = -EINVAL;
5308
5309         dev_err(&hdev->pdev->dev,
5310                 "PF failed to add unicast entry(%pM) in the MAC table\n",
5311                 addr);
5312
5313         return ret;
5314 }
5315
5316 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
5317                             const unsigned char *addr)
5318 {
5319         struct hclge_vport *vport = hclge_get_vport(handle);
5320
5321         return hclge_rm_uc_addr_common(vport, addr);
5322 }
5323
5324 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
5325                             const unsigned char *addr)
5326 {
5327         struct hclge_dev *hdev = vport->back;
5328         struct hclge_mac_vlan_tbl_entry_cmd req;
5329         int ret;
5330
5331         /* mac addr check */
5332         if (is_zero_ether_addr(addr) ||
5333             is_broadcast_ether_addr(addr) ||
5334             is_multicast_ether_addr(addr)) {
5335                 dev_dbg(&hdev->pdev->dev,
5336                         "Remove mac err! invalid mac:%pM.\n",
5337                          addr);
5338                 return -EINVAL;
5339         }
5340
5341         memset(&req, 0, sizeof(req));
5342         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5343         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5344         hclge_prepare_mac_addr(&req, addr);
5345         ret = hclge_remove_mac_vlan_tbl(vport, &req);
5346         if (!ret)
5347                 hclge_update_umv_space(vport, true);
5348
5349         return ret;
5350 }
5351
5352 static int hclge_add_mc_addr(struct hnae3_handle *handle,
5353                              const unsigned char *addr)
5354 {
5355         struct hclge_vport *vport = hclge_get_vport(handle);
5356
5357         return hclge_add_mc_addr_common(vport, addr);
5358 }
5359
5360 int hclge_add_mc_addr_common(struct hclge_vport *vport,
5361                              const unsigned char *addr)
5362 {
5363         struct hclge_dev *hdev = vport->back;
5364         struct hclge_mac_vlan_tbl_entry_cmd req;
5365         struct hclge_desc desc[3];
5366         int status;
5367
5368         /* mac addr check */
5369         if (!is_multicast_ether_addr(addr)) {
5370                 dev_err(&hdev->pdev->dev,
5371                         "Add mc mac err! invalid mac:%pM.\n",
5372                          addr);
5373                 return -EINVAL;
5374         }
5375         memset(&req, 0, sizeof(req));
5376         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5377         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5378         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
5379         hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5380         hclge_prepare_mac_addr(&req, addr);
5381         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
5382         if (!status) {
5383                 /* This mac addr exist, update VFID for it */
5384                 hclge_update_desc_vfid(desc, vport->vport_id, false);
5385                 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5386         } else {
5387                 /* This mac addr do not exist, add new entry for it */
5388                 memset(desc[0].data, 0, sizeof(desc[0].data));
5389                 memset(desc[1].data, 0, sizeof(desc[0].data));
5390                 memset(desc[2].data, 0, sizeof(desc[0].data));
5391                 hclge_update_desc_vfid(desc, vport->vport_id, false);
5392                 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5393         }
5394
5395         if (status == -ENOSPC)
5396                 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n");
5397
5398         return status;
5399 }
5400
5401 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
5402                             const unsigned char *addr)
5403 {
5404         struct hclge_vport *vport = hclge_get_vport(handle);
5405
5406         return hclge_rm_mc_addr_common(vport, addr);
5407 }
5408
5409 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
5410                             const unsigned char *addr)
5411 {
5412         struct hclge_dev *hdev = vport->back;
5413         struct hclge_mac_vlan_tbl_entry_cmd req;
5414         enum hclge_cmd_status status;
5415         struct hclge_desc desc[3];
5416
5417         /* mac addr check */
5418         if (!is_multicast_ether_addr(addr)) {
5419                 dev_dbg(&hdev->pdev->dev,
5420                         "Remove mc mac err! invalid mac:%pM.\n",
5421                          addr);
5422                 return -EINVAL;
5423         }
5424
5425         memset(&req, 0, sizeof(req));
5426         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5427         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5428         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
5429         hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5430         hclge_prepare_mac_addr(&req, addr);
5431         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
5432         if (!status) {
5433                 /* This mac addr exist, remove this handle's VFID for it */
5434                 hclge_update_desc_vfid(desc, vport->vport_id, true);
5435
5436                 if (hclge_is_all_function_id_zero(desc))
5437                         /* All the vfid is zero, so need to delete this entry */
5438                         status = hclge_remove_mac_vlan_tbl(vport, &req);
5439                 else
5440                         /* Not all the vfid is zero, update the vfid */
5441                         status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5442
5443         } else {
5444                 /* Maybe this mac address is in mta table, but it cannot be
5445                  * deleted here because an entry of mta represents an address
5446                  * range rather than a specific address. the delete action to
5447                  * all entries will take effect in update_mta_status called by
5448                  * hns3_nic_set_rx_mode.
5449                  */
5450                 status = 0;
5451         }
5452
5453         return status;
5454 }
5455
5456 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
5457                                               u16 cmdq_resp, u8 resp_code)
5458 {
5459 #define HCLGE_ETHERTYPE_SUCCESS_ADD             0
5460 #define HCLGE_ETHERTYPE_ALREADY_ADD             1
5461 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW        2
5462 #define HCLGE_ETHERTYPE_KEY_CONFLICT            3
5463
5464         int return_status;
5465
5466         if (cmdq_resp) {
5467                 dev_err(&hdev->pdev->dev,
5468                         "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
5469                         cmdq_resp);
5470                 return -EIO;
5471         }
5472
5473         switch (resp_code) {
5474         case HCLGE_ETHERTYPE_SUCCESS_ADD:
5475         case HCLGE_ETHERTYPE_ALREADY_ADD:
5476                 return_status = 0;
5477                 break;
5478         case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
5479                 dev_err(&hdev->pdev->dev,
5480                         "add mac ethertype failed for manager table overflow.\n");
5481                 return_status = -EIO;
5482                 break;
5483         case HCLGE_ETHERTYPE_KEY_CONFLICT:
5484                 dev_err(&hdev->pdev->dev,
5485                         "add mac ethertype failed for key conflict.\n");
5486                 return_status = -EIO;
5487                 break;
5488         default:
5489                 dev_err(&hdev->pdev->dev,
5490                         "add mac ethertype failed for undefined, code=%d.\n",
5491                         resp_code);
5492                 return_status = -EIO;
5493         }
5494
5495         return return_status;
5496 }
5497
5498 static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
5499                              const struct hclge_mac_mgr_tbl_entry_cmd *req)
5500 {
5501         struct hclge_desc desc;
5502         u8 resp_code;
5503         u16 retval;
5504         int ret;
5505
5506         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
5507         memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
5508
5509         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5510         if (ret) {
5511                 dev_err(&hdev->pdev->dev,
5512                         "add mac ethertype failed for cmd_send, ret =%d.\n",
5513                         ret);
5514                 return ret;
5515         }
5516
5517         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5518         retval = le16_to_cpu(desc.retval);
5519
5520         return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
5521 }
5522
5523 static int init_mgr_tbl(struct hclge_dev *hdev)
5524 {
5525         int ret;
5526         int i;
5527
5528         for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
5529                 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
5530                 if (ret) {
5531                         dev_err(&hdev->pdev->dev,
5532                                 "add mac ethertype failed, ret =%d.\n",
5533                                 ret);
5534                         return ret;
5535                 }
5536         }
5537
5538         return 0;
5539 }
5540
5541 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
5542 {
5543         struct hclge_vport *vport = hclge_get_vport(handle);
5544         struct hclge_dev *hdev = vport->back;
5545
5546         ether_addr_copy(p, hdev->hw.mac.mac_addr);
5547 }
5548
5549 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
5550                               bool is_first)
5551 {
5552         const unsigned char *new_addr = (const unsigned char *)p;
5553         struct hclge_vport *vport = hclge_get_vport(handle);
5554         struct hclge_dev *hdev = vport->back;
5555         int ret;
5556
5557         /* mac addr check */
5558         if (is_zero_ether_addr(new_addr) ||
5559             is_broadcast_ether_addr(new_addr) ||
5560             is_multicast_ether_addr(new_addr)) {
5561                 dev_err(&hdev->pdev->dev,
5562                         "Change uc mac err! invalid mac:%p.\n",
5563                          new_addr);
5564                 return -EINVAL;
5565         }
5566
5567         if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
5568                 dev_warn(&hdev->pdev->dev,
5569                          "remove old uc mac address fail.\n");
5570
5571         ret = hclge_add_uc_addr(handle, new_addr);
5572         if (ret) {
5573                 dev_err(&hdev->pdev->dev,
5574                         "add uc mac address fail, ret =%d.\n",
5575                         ret);
5576
5577                 if (!is_first &&
5578                     hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
5579                         dev_err(&hdev->pdev->dev,
5580                                 "restore uc mac address fail.\n");
5581
5582                 return -EIO;
5583         }
5584
5585         ret = hclge_pause_addr_cfg(hdev, new_addr);
5586         if (ret) {
5587                 dev_err(&hdev->pdev->dev,
5588                         "configure mac pause address fail, ret =%d.\n",
5589                         ret);
5590                 return -EIO;
5591         }
5592
5593         ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
5594
5595         return 0;
5596 }
5597
5598 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
5599                           int cmd)
5600 {
5601         struct hclge_vport *vport = hclge_get_vport(handle);
5602         struct hclge_dev *hdev = vport->back;
5603
5604         if (!hdev->hw.mac.phydev)
5605                 return -EOPNOTSUPP;
5606
5607         return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
5608 }
5609
5610 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
5611                                       u8 fe_type, bool filter_en)
5612 {
5613         struct hclge_vlan_filter_ctrl_cmd *req;
5614         struct hclge_desc desc;
5615         int ret;
5616
5617         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
5618
5619         req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
5620         req->vlan_type = vlan_type;
5621         req->vlan_fe = filter_en ? fe_type : 0;
5622
5623         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5624         if (ret)
5625                 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
5626                         ret);
5627
5628         return ret;
5629 }
5630
5631 #define HCLGE_FILTER_TYPE_VF            0
5632 #define HCLGE_FILTER_TYPE_PORT          1
5633 #define HCLGE_FILTER_FE_EGRESS_V1_B     BIT(0)
5634 #define HCLGE_FILTER_FE_NIC_INGRESS_B   BIT(0)
5635 #define HCLGE_FILTER_FE_NIC_EGRESS_B    BIT(1)
5636 #define HCLGE_FILTER_FE_ROCE_INGRESS_B  BIT(2)
5637 #define HCLGE_FILTER_FE_ROCE_EGRESS_B   BIT(3)
5638 #define HCLGE_FILTER_FE_EGRESS          (HCLGE_FILTER_FE_NIC_EGRESS_B \
5639                                         | HCLGE_FILTER_FE_ROCE_EGRESS_B)
5640 #define HCLGE_FILTER_FE_INGRESS         (HCLGE_FILTER_FE_NIC_INGRESS_B \
5641                                         | HCLGE_FILTER_FE_ROCE_INGRESS_B)
5642
5643 static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
5644 {
5645         struct hclge_vport *vport = hclge_get_vport(handle);
5646         struct hclge_dev *hdev = vport->back;
5647
5648         if (hdev->pdev->revision >= 0x21) {
5649                 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5650                                            HCLGE_FILTER_FE_EGRESS, enable);
5651                 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
5652                                            HCLGE_FILTER_FE_INGRESS, enable);
5653         } else {
5654                 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5655                                            HCLGE_FILTER_FE_EGRESS_V1_B, enable);
5656         }
5657         if (enable)
5658                 handle->netdev_flags |= HNAE3_VLAN_FLTR;
5659         else
5660                 handle->netdev_flags &= ~HNAE3_VLAN_FLTR;
5661 }
5662
5663 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
5664                                     bool is_kill, u16 vlan, u8 qos,
5665                                     __be16 proto)
5666 {
5667 #define HCLGE_MAX_VF_BYTES  16
5668         struct hclge_vlan_filter_vf_cfg_cmd *req0;
5669         struct hclge_vlan_filter_vf_cfg_cmd *req1;
5670         struct hclge_desc desc[2];
5671         u8 vf_byte_val;
5672         u8 vf_byte_off;
5673         int ret;
5674
5675         hclge_cmd_setup_basic_desc(&desc[0],
5676                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
5677         hclge_cmd_setup_basic_desc(&desc[1],
5678                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
5679
5680         desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5681
5682         vf_byte_off = vfid / 8;
5683         vf_byte_val = 1 << (vfid % 8);
5684
5685         req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
5686         req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
5687
5688         req0->vlan_id  = cpu_to_le16(vlan);
5689         req0->vlan_cfg = is_kill;
5690
5691         if (vf_byte_off < HCLGE_MAX_VF_BYTES)
5692                 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
5693         else
5694                 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
5695
5696         ret = hclge_cmd_send(&hdev->hw, desc, 2);
5697         if (ret) {
5698                 dev_err(&hdev->pdev->dev,
5699                         "Send vf vlan command fail, ret =%d.\n",
5700                         ret);
5701                 return ret;
5702         }
5703
5704         if (!is_kill) {
5705 #define HCLGE_VF_VLAN_NO_ENTRY  2
5706                 if (!req0->resp_code || req0->resp_code == 1)
5707                         return 0;
5708
5709                 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
5710                         dev_warn(&hdev->pdev->dev,
5711                                  "vf vlan table is full, vf vlan filter is disabled\n");
5712                         return 0;
5713                 }
5714
5715                 dev_err(&hdev->pdev->dev,
5716                         "Add vf vlan filter fail, ret =%d.\n",
5717                         req0->resp_code);
5718         } else {
5719 #define HCLGE_VF_VLAN_DEL_NO_FOUND      1
5720                 if (!req0->resp_code)
5721                         return 0;
5722
5723                 if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) {
5724                         dev_warn(&hdev->pdev->dev,
5725                                  "vlan %d filter is not in vf vlan table\n",
5726                                  vlan);
5727                         return 0;
5728                 }
5729
5730                 dev_err(&hdev->pdev->dev,
5731                         "Kill vf vlan filter fail, ret =%d.\n",
5732                         req0->resp_code);
5733         }
5734
5735         return -EIO;
5736 }
5737
5738 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
5739                                       u16 vlan_id, bool is_kill)
5740 {
5741         struct hclge_vlan_filter_pf_cfg_cmd *req;
5742         struct hclge_desc desc;
5743         u8 vlan_offset_byte_val;
5744         u8 vlan_offset_byte;
5745         u8 vlan_offset_160;
5746         int ret;
5747
5748         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
5749
5750         vlan_offset_160 = vlan_id / 160;
5751         vlan_offset_byte = (vlan_id % 160) / 8;
5752         vlan_offset_byte_val = 1 << (vlan_id % 8);
5753
5754         req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
5755         req->vlan_offset = vlan_offset_160;
5756         req->vlan_cfg = is_kill;
5757         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
5758
5759         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5760         if (ret)
5761                 dev_err(&hdev->pdev->dev,
5762                         "port vlan command, send fail, ret =%d.\n", ret);
5763         return ret;
5764 }
5765
5766 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
5767                                     u16 vport_id, u16 vlan_id, u8 qos,
5768                                     bool is_kill)
5769 {
5770         u16 vport_idx, vport_num = 0;
5771         int ret;
5772
5773         if (is_kill && !vlan_id)
5774                 return 0;
5775
5776         ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
5777                                        0, proto);
5778         if (ret) {
5779                 dev_err(&hdev->pdev->dev,
5780                         "Set %d vport vlan filter config fail, ret =%d.\n",
5781                         vport_id, ret);
5782                 return ret;
5783         }
5784
5785         /* vlan 0 may be added twice when 8021q module is enabled */
5786         if (!is_kill && !vlan_id &&
5787             test_bit(vport_id, hdev->vlan_table[vlan_id]))
5788                 return 0;
5789
5790         if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
5791                 dev_err(&hdev->pdev->dev,
5792                         "Add port vlan failed, vport %d is already in vlan %d\n",
5793                         vport_id, vlan_id);
5794                 return -EINVAL;
5795         }
5796
5797         if (is_kill &&
5798             !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
5799                 dev_err(&hdev->pdev->dev,
5800                         "Delete port vlan failed, vport %d is not in vlan %d\n",
5801                         vport_id, vlan_id);
5802                 return -EINVAL;
5803         }
5804
5805         for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
5806                 vport_num++;
5807
5808         if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
5809                 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
5810                                                  is_kill);
5811
5812         return ret;
5813 }
5814
5815 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
5816                           u16 vlan_id, bool is_kill)
5817 {
5818         struct hclge_vport *vport = hclge_get_vport(handle);
5819         struct hclge_dev *hdev = vport->back;
5820
5821         return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
5822                                         0, is_kill);
5823 }
5824
5825 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
5826                                     u16 vlan, u8 qos, __be16 proto)
5827 {
5828         struct hclge_vport *vport = hclge_get_vport(handle);
5829         struct hclge_dev *hdev = vport->back;
5830
5831         if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
5832                 return -EINVAL;
5833         if (proto != htons(ETH_P_8021Q))
5834                 return -EPROTONOSUPPORT;
5835
5836         return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
5837 }
5838
5839 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
5840 {
5841         struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
5842         struct hclge_vport_vtag_tx_cfg_cmd *req;
5843         struct hclge_dev *hdev = vport->back;
5844         struct hclge_desc desc;
5845         int status;
5846
5847         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
5848
5849         req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
5850         req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
5851         req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
5852         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
5853                       vcfg->accept_tag1 ? 1 : 0);
5854         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
5855                       vcfg->accept_untag1 ? 1 : 0);
5856         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
5857                       vcfg->accept_tag2 ? 1 : 0);
5858         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
5859                       vcfg->accept_untag2 ? 1 : 0);
5860         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
5861                       vcfg->insert_tag1_en ? 1 : 0);
5862         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
5863                       vcfg->insert_tag2_en ? 1 : 0);
5864         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
5865
5866         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
5867         req->vf_bitmap[req->vf_offset] =
5868                 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
5869
5870         status = hclge_cmd_send(&hdev->hw, &desc, 1);
5871         if (status)
5872                 dev_err(&hdev->pdev->dev,
5873                         "Send port txvlan cfg command fail, ret =%d\n",
5874                         status);
5875
5876         return status;
5877 }
5878
5879 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
5880 {
5881         struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
5882         struct hclge_vport_vtag_rx_cfg_cmd *req;
5883         struct hclge_dev *hdev = vport->back;
5884         struct hclge_desc desc;
5885         int status;
5886
5887         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
5888
5889         req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
5890         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
5891                       vcfg->strip_tag1_en ? 1 : 0);
5892         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
5893                       vcfg->strip_tag2_en ? 1 : 0);
5894         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
5895                       vcfg->vlan1_vlan_prionly ? 1 : 0);
5896         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
5897                       vcfg->vlan2_vlan_prionly ? 1 : 0);
5898
5899         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
5900         req->vf_bitmap[req->vf_offset] =
5901                 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
5902
5903         status = hclge_cmd_send(&hdev->hw, &desc, 1);
5904         if (status)
5905                 dev_err(&hdev->pdev->dev,
5906                         "Send port rxvlan cfg command fail, ret =%d\n",
5907                         status);
5908
5909         return status;
5910 }
5911
5912 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
5913 {
5914         struct hclge_rx_vlan_type_cfg_cmd *rx_req;
5915         struct hclge_tx_vlan_type_cfg_cmd *tx_req;
5916         struct hclge_desc desc;
5917         int status;
5918
5919         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
5920         rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
5921         rx_req->ot_fst_vlan_type =
5922                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
5923         rx_req->ot_sec_vlan_type =
5924                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
5925         rx_req->in_fst_vlan_type =
5926                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
5927         rx_req->in_sec_vlan_type =
5928                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
5929
5930         status = hclge_cmd_send(&hdev->hw, &desc, 1);
5931         if (status) {
5932                 dev_err(&hdev->pdev->dev,
5933                         "Send rxvlan protocol type command fail, ret =%d\n",
5934                         status);
5935                 return status;
5936         }
5937
5938         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
5939
5940         tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data;
5941         tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
5942         tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
5943
5944         status = hclge_cmd_send(&hdev->hw, &desc, 1);
5945         if (status)
5946                 dev_err(&hdev->pdev->dev,
5947                         "Send txvlan protocol type command fail, ret =%d\n",
5948                         status);
5949
5950         return status;
5951 }
5952
5953 static int hclge_init_vlan_config(struct hclge_dev *hdev)
5954 {
5955 #define HCLGE_DEF_VLAN_TYPE             0x8100
5956
5957         struct hnae3_handle *handle = &hdev->vport[0].nic;
5958         struct hclge_vport *vport;
5959         int ret;
5960         int i;
5961
5962         if (hdev->pdev->revision >= 0x21) {
5963                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5964                                                  HCLGE_FILTER_FE_EGRESS, true);
5965                 if (ret)
5966                         return ret;
5967
5968                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
5969                                                  HCLGE_FILTER_FE_INGRESS, true);
5970                 if (ret)
5971                         return ret;
5972         } else {
5973                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5974                                                  HCLGE_FILTER_FE_EGRESS_V1_B,
5975                                                  true);
5976                 if (ret)
5977                         return ret;
5978         }
5979
5980         handle->netdev_flags |= HNAE3_VLAN_FLTR;
5981
5982         hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
5983         hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
5984         hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
5985         hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
5986         hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
5987         hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
5988
5989         ret = hclge_set_vlan_protocol_type(hdev);
5990         if (ret)
5991                 return ret;
5992
5993         for (i = 0; i < hdev->num_alloc_vport; i++) {
5994                 vport = &hdev->vport[i];
5995                 vport->txvlan_cfg.accept_tag1 = true;
5996                 vport->txvlan_cfg.accept_untag1 = true;
5997
5998                 /* accept_tag2 and accept_untag2 are not supported on
5999                  * pdev revision(0x20), new revision support them. The
6000                  * value of this two fields will not return error when driver
6001                  * send command to fireware in revision(0x20).
6002                  * This two fields can not configured by user.
6003                  */
6004                 vport->txvlan_cfg.accept_tag2 = true;
6005                 vport->txvlan_cfg.accept_untag2 = true;
6006
6007                 vport->txvlan_cfg.insert_tag1_en = false;
6008                 vport->txvlan_cfg.insert_tag2_en = false;
6009                 vport->txvlan_cfg.default_tag1 = 0;
6010                 vport->txvlan_cfg.default_tag2 = 0;
6011
6012                 ret = hclge_set_vlan_tx_offload_cfg(vport);
6013                 if (ret)
6014                         return ret;
6015
6016                 vport->rxvlan_cfg.strip_tag1_en = false;
6017                 vport->rxvlan_cfg.strip_tag2_en = true;
6018                 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
6019                 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
6020
6021                 ret = hclge_set_vlan_rx_offload_cfg(vport);
6022                 if (ret)
6023                         return ret;
6024         }
6025
6026         return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
6027 }
6028
6029 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
6030 {
6031         struct hclge_vport *vport = hclge_get_vport(handle);
6032
6033         vport->rxvlan_cfg.strip_tag1_en = false;
6034         vport->rxvlan_cfg.strip_tag2_en = enable;
6035         vport->rxvlan_cfg.vlan1_vlan_prionly = false;
6036         vport->rxvlan_cfg.vlan2_vlan_prionly = false;
6037
6038         return hclge_set_vlan_rx_offload_cfg(vport);
6039 }
6040
6041 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
6042 {
6043         struct hclge_config_max_frm_size_cmd *req;
6044         struct hclge_desc desc;
6045         int max_frm_size;
6046         int ret;
6047
6048         max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
6049
6050         if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
6051             max_frm_size > HCLGE_MAC_MAX_FRAME)
6052                 return -EINVAL;
6053
6054         max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
6055
6056         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
6057
6058         req = (struct hclge_config_max_frm_size_cmd *)desc.data;
6059         req->max_frm_size = cpu_to_le16(max_frm_size);
6060         req->min_frm_size = HCLGE_MAC_MIN_FRAME;
6061
6062         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6063         if (ret)
6064                 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
6065         else
6066                 hdev->mps = max_frm_size;
6067
6068         return ret;
6069 }
6070
6071 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
6072 {
6073         struct hclge_vport *vport = hclge_get_vport(handle);
6074         struct hclge_dev *hdev = vport->back;
6075         int ret;
6076
6077         ret = hclge_set_mac_mtu(hdev, new_mtu);
6078         if (ret) {
6079                 dev_err(&hdev->pdev->dev,
6080                         "Change mtu fail, ret =%d\n", ret);
6081                 return ret;
6082         }
6083
6084         ret = hclge_buffer_alloc(hdev);
6085         if (ret)
6086                 dev_err(&hdev->pdev->dev,
6087                         "Allocate buffer fail, ret =%d\n", ret);
6088
6089         return ret;
6090 }
6091
6092 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
6093                                     bool enable)
6094 {
6095         struct hclge_reset_tqp_queue_cmd *req;
6096         struct hclge_desc desc;
6097         int ret;
6098
6099         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
6100
6101         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
6102         req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
6103         hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
6104
6105         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6106         if (ret) {
6107                 dev_err(&hdev->pdev->dev,
6108                         "Send tqp reset cmd error, status =%d\n", ret);
6109                 return ret;
6110         }
6111
6112         return 0;
6113 }
6114
6115 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
6116 {
6117         struct hclge_reset_tqp_queue_cmd *req;
6118         struct hclge_desc desc;
6119         int ret;
6120
6121         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
6122
6123         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
6124         req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
6125
6126         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6127         if (ret) {
6128                 dev_err(&hdev->pdev->dev,
6129                         "Get reset status error, status =%d\n", ret);
6130                 return ret;
6131         }
6132
6133         return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
6134 }
6135
6136 static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
6137                                           u16 queue_id)
6138 {
6139         struct hnae3_queue *queue;
6140         struct hclge_tqp *tqp;
6141
6142         queue = handle->kinfo.tqp[queue_id];
6143         tqp = container_of(queue, struct hclge_tqp, q);
6144
6145         return tqp->index;
6146 }
6147
6148 int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
6149 {
6150         struct hclge_vport *vport = hclge_get_vport(handle);
6151         struct hclge_dev *hdev = vport->back;
6152         int reset_try_times = 0;
6153         int reset_status;
6154         u16 queue_gid;
6155         int ret = 0;
6156
6157         queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
6158
6159         ret = hclge_tqp_enable(hdev, queue_id, 0, false);
6160         if (ret) {
6161                 dev_err(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
6162                 return ret;
6163         }
6164
6165         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
6166         if (ret) {
6167                 dev_err(&hdev->pdev->dev,
6168                         "Send reset tqp cmd fail, ret = %d\n", ret);
6169                 return ret;
6170         }
6171
6172         reset_try_times = 0;
6173         while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
6174                 /* Wait for tqp hw reset */
6175                 msleep(20);
6176                 reset_status = hclge_get_reset_status(hdev, queue_gid);
6177                 if (reset_status)
6178                         break;
6179         }
6180
6181         if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
6182                 dev_err(&hdev->pdev->dev, "Reset TQP fail\n");
6183                 return ret;
6184         }
6185
6186         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
6187         if (ret)
6188                 dev_err(&hdev->pdev->dev,
6189                         "Deassert the soft reset fail, ret = %d\n", ret);
6190
6191         return ret;
6192 }
6193
6194 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
6195 {
6196         struct hclge_dev *hdev = vport->back;
6197         int reset_try_times = 0;
6198         int reset_status;
6199         u16 queue_gid;
6200         int ret;
6201
6202         queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
6203
6204         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
6205         if (ret) {
6206                 dev_warn(&hdev->pdev->dev,
6207                          "Send reset tqp cmd fail, ret = %d\n", ret);
6208                 return;
6209         }
6210
6211         reset_try_times = 0;
6212         while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
6213                 /* Wait for tqp hw reset */
6214                 msleep(20);
6215                 reset_status = hclge_get_reset_status(hdev, queue_gid);
6216                 if (reset_status)
6217                         break;
6218         }
6219
6220         if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
6221                 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
6222                 return;
6223         }
6224
6225         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
6226         if (ret)
6227                 dev_warn(&hdev->pdev->dev,
6228                          "Deassert the soft reset fail, ret = %d\n", ret);
6229 }
6230
6231 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
6232 {
6233         struct hclge_vport *vport = hclge_get_vport(handle);
6234         struct hclge_dev *hdev = vport->back;
6235
6236         return hdev->fw_version;
6237 }
6238
6239 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
6240 {
6241         struct phy_device *phydev = hdev->hw.mac.phydev;
6242
6243         if (!phydev)
6244                 return;
6245
6246         phy_set_asym_pause(phydev, rx_en, tx_en);
6247 }
6248
6249 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
6250 {
6251         int ret;
6252
6253         if (rx_en && tx_en)
6254                 hdev->fc_mode_last_time = HCLGE_FC_FULL;
6255         else if (rx_en && !tx_en)
6256                 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
6257         else if (!rx_en && tx_en)
6258                 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
6259         else
6260                 hdev->fc_mode_last_time = HCLGE_FC_NONE;
6261
6262         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
6263                 return 0;
6264
6265         ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
6266         if (ret) {
6267                 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
6268                         ret);
6269                 return ret;
6270         }
6271
6272         hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
6273
6274         return 0;
6275 }
6276
6277 int hclge_cfg_flowctrl(struct hclge_dev *hdev)
6278 {
6279         struct phy_device *phydev = hdev->hw.mac.phydev;
6280         u16 remote_advertising = 0;
6281         u16 local_advertising = 0;
6282         u32 rx_pause, tx_pause;
6283         u8 flowctl;
6284
6285         if (!phydev->link || !phydev->autoneg)
6286                 return 0;
6287
6288         local_advertising = ethtool_adv_to_lcl_adv_t(phydev->advertising);
6289
6290         if (phydev->pause)
6291                 remote_advertising = LPA_PAUSE_CAP;
6292
6293         if (phydev->asym_pause)
6294                 remote_advertising |= LPA_PAUSE_ASYM;
6295
6296         flowctl = mii_resolve_flowctrl_fdx(local_advertising,
6297                                            remote_advertising);
6298         tx_pause = flowctl & FLOW_CTRL_TX;
6299         rx_pause = flowctl & FLOW_CTRL_RX;
6300
6301         if (phydev->duplex == HCLGE_MAC_HALF) {
6302                 tx_pause = 0;
6303                 rx_pause = 0;
6304         }
6305
6306         return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
6307 }
6308
6309 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
6310                                  u32 *rx_en, u32 *tx_en)
6311 {
6312         struct hclge_vport *vport = hclge_get_vport(handle);
6313         struct hclge_dev *hdev = vport->back;
6314
6315         *auto_neg = hclge_get_autoneg(handle);
6316
6317         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
6318                 *rx_en = 0;
6319                 *tx_en = 0;
6320                 return;
6321         }
6322
6323         if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
6324                 *rx_en = 1;
6325                 *tx_en = 0;
6326         } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
6327                 *tx_en = 1;
6328                 *rx_en = 0;
6329         } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
6330                 *rx_en = 1;
6331                 *tx_en = 1;
6332         } else {
6333                 *rx_en = 0;
6334                 *tx_en = 0;
6335         }
6336 }
6337
6338 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
6339                                 u32 rx_en, u32 tx_en)
6340 {
6341         struct hclge_vport *vport = hclge_get_vport(handle);
6342         struct hclge_dev *hdev = vport->back;
6343         struct phy_device *phydev = hdev->hw.mac.phydev;
6344         u32 fc_autoneg;
6345
6346         fc_autoneg = hclge_get_autoneg(handle);
6347         if (auto_neg != fc_autoneg) {
6348                 dev_info(&hdev->pdev->dev,
6349                          "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
6350                 return -EOPNOTSUPP;
6351         }
6352
6353         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
6354                 dev_info(&hdev->pdev->dev,
6355                          "Priority flow control enabled. Cannot set link flow control.\n");
6356                 return -EOPNOTSUPP;
6357         }
6358
6359         hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
6360
6361         if (!fc_autoneg)
6362                 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
6363
6364         /* Only support flow control negotiation for netdev with
6365          * phy attached for now.
6366          */
6367         if (!phydev)
6368                 return -EOPNOTSUPP;
6369
6370         return phy_start_aneg(phydev);
6371 }
6372
6373 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
6374                                           u8 *auto_neg, u32 *speed, u8 *duplex)
6375 {
6376         struct hclge_vport *vport = hclge_get_vport(handle);
6377         struct hclge_dev *hdev = vport->back;
6378
6379         if (speed)
6380                 *speed = hdev->hw.mac.speed;
6381         if (duplex)
6382                 *duplex = hdev->hw.mac.duplex;
6383         if (auto_neg)
6384                 *auto_neg = hdev->hw.mac.autoneg;
6385 }
6386
6387 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
6388 {
6389         struct hclge_vport *vport = hclge_get_vport(handle);
6390         struct hclge_dev *hdev = vport->back;
6391
6392         if (media_type)
6393                 *media_type = hdev->hw.mac.media_type;
6394 }
6395
6396 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
6397                                 u8 *tp_mdix_ctrl, u8 *tp_mdix)
6398 {
6399         struct hclge_vport *vport = hclge_get_vport(handle);
6400         struct hclge_dev *hdev = vport->back;
6401         struct phy_device *phydev = hdev->hw.mac.phydev;
6402         int mdix_ctrl, mdix, retval, is_resolved;
6403
6404         if (!phydev) {
6405                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
6406                 *tp_mdix = ETH_TP_MDI_INVALID;
6407                 return;
6408         }
6409
6410         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
6411
6412         retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
6413         mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
6414                                     HCLGE_PHY_MDIX_CTRL_S);
6415
6416         retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
6417         mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
6418         is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
6419
6420         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
6421
6422         switch (mdix_ctrl) {
6423         case 0x0:
6424                 *tp_mdix_ctrl = ETH_TP_MDI;
6425                 break;
6426         case 0x1:
6427                 *tp_mdix_ctrl = ETH_TP_MDI_X;
6428                 break;
6429         case 0x3:
6430                 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
6431                 break;
6432         default:
6433                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
6434                 break;
6435         }
6436
6437         if (!is_resolved)
6438                 *tp_mdix = ETH_TP_MDI_INVALID;
6439         else if (mdix)
6440                 *tp_mdix = ETH_TP_MDI_X;
6441         else
6442                 *tp_mdix = ETH_TP_MDI;
6443 }
6444
6445 static int hclge_init_instance_hw(struct hclge_dev *hdev)
6446 {
6447         return hclge_mac_connect_phy(hdev);
6448 }
6449
6450 static void hclge_uninit_instance_hw(struct hclge_dev *hdev)
6451 {
6452         hclge_mac_disconnect_phy(hdev);
6453 }
6454
6455 static int hclge_init_client_instance(struct hnae3_client *client,
6456                                       struct hnae3_ae_dev *ae_dev)
6457 {
6458         struct hclge_dev *hdev = ae_dev->priv;
6459         struct hclge_vport *vport;
6460         int i, ret;
6461
6462         for (i = 0; i <  hdev->num_vmdq_vport + 1; i++) {
6463                 vport = &hdev->vport[i];
6464
6465                 switch (client->type) {
6466                 case HNAE3_CLIENT_KNIC:
6467
6468                         hdev->nic_client = client;
6469                         vport->nic.client = client;
6470                         ret = client->ops->init_instance(&vport->nic);
6471                         if (ret)
6472                                 goto clear_nic;
6473
6474                         ret = hclge_init_instance_hw(hdev);
6475                         if (ret) {
6476                                 client->ops->uninit_instance(&vport->nic,
6477                                                              0);
6478                                 goto clear_nic;
6479                         }
6480
6481                         hnae3_set_client_init_flag(client, ae_dev, 1);
6482
6483                         if (hdev->roce_client &&
6484                             hnae3_dev_roce_supported(hdev)) {
6485                                 struct hnae3_client *rc = hdev->roce_client;
6486
6487                                 ret = hclge_init_roce_base_info(vport);
6488                                 if (ret)
6489                                         goto clear_roce;
6490
6491                                 ret = rc->ops->init_instance(&vport->roce);
6492                                 if (ret)
6493                                         goto clear_roce;
6494
6495                                 hnae3_set_client_init_flag(hdev->roce_client,
6496                                                            ae_dev, 1);
6497                         }
6498
6499                         break;
6500                 case HNAE3_CLIENT_UNIC:
6501                         hdev->nic_client = client;
6502                         vport->nic.client = client;
6503
6504                         ret = client->ops->init_instance(&vport->nic);
6505                         if (ret)
6506                                 goto clear_nic;
6507
6508                         hnae3_set_client_init_flag(client, ae_dev, 1);
6509
6510                         break;
6511                 case HNAE3_CLIENT_ROCE:
6512                         if (hnae3_dev_roce_supported(hdev)) {
6513                                 hdev->roce_client = client;
6514                                 vport->roce.client = client;
6515                         }
6516
6517                         if (hdev->roce_client && hdev->nic_client) {
6518                                 ret = hclge_init_roce_base_info(vport);
6519                                 if (ret)
6520                                         goto clear_roce;
6521
6522                                 ret = client->ops->init_instance(&vport->roce);
6523                                 if (ret)
6524                                         goto clear_roce;
6525
6526                                 hnae3_set_client_init_flag(client, ae_dev, 1);
6527                         }
6528
6529                         break;
6530                 default:
6531                         return -EINVAL;
6532                 }
6533         }
6534
6535         return 0;
6536
6537 clear_nic:
6538         hdev->nic_client = NULL;
6539         vport->nic.client = NULL;
6540         return ret;
6541 clear_roce:
6542         hdev->roce_client = NULL;
6543         vport->roce.client = NULL;
6544         return ret;
6545 }
6546
6547 static void hclge_uninit_client_instance(struct hnae3_client *client,
6548                                          struct hnae3_ae_dev *ae_dev)
6549 {
6550         struct hclge_dev *hdev = ae_dev->priv;
6551         struct hclge_vport *vport;
6552         int i;
6553
6554         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
6555                 vport = &hdev->vport[i];
6556                 if (hdev->roce_client) {
6557                         hdev->roce_client->ops->uninit_instance(&vport->roce,
6558                                                                 0);
6559                         hdev->roce_client = NULL;
6560                         vport->roce.client = NULL;
6561                 }
6562                 if (client->type == HNAE3_CLIENT_ROCE)
6563                         return;
6564                 if (hdev->nic_client && client->ops->uninit_instance) {
6565                         hclge_uninit_instance_hw(hdev);
6566                         client->ops->uninit_instance(&vport->nic, 0);
6567                         hdev->nic_client = NULL;
6568                         vport->nic.client = NULL;
6569                 }
6570         }
6571 }
6572
6573 static int hclge_pci_init(struct hclge_dev *hdev)
6574 {
6575         struct pci_dev *pdev = hdev->pdev;
6576         struct hclge_hw *hw;
6577         int ret;
6578
6579         ret = pci_enable_device(pdev);
6580         if (ret) {
6581                 dev_err(&pdev->dev, "failed to enable PCI device\n");
6582                 return ret;
6583         }
6584
6585         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6586         if (ret) {
6587                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
6588                 if (ret) {
6589                         dev_err(&pdev->dev,
6590                                 "can't set consistent PCI DMA");
6591                         goto err_disable_device;
6592                 }
6593                 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
6594         }
6595
6596         ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
6597         if (ret) {
6598                 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
6599                 goto err_disable_device;
6600         }
6601
6602         pci_set_master(pdev);
6603         hw = &hdev->hw;
6604         hw->io_base = pcim_iomap(pdev, 2, 0);
6605         if (!hw->io_base) {
6606                 dev_err(&pdev->dev, "Can't map configuration register space\n");
6607                 ret = -ENOMEM;
6608                 goto err_clr_master;
6609         }
6610
6611         hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
6612
6613         return 0;
6614 err_clr_master:
6615         pci_clear_master(pdev);
6616         pci_release_regions(pdev);
6617 err_disable_device:
6618         pci_disable_device(pdev);
6619
6620         return ret;
6621 }
6622
6623 static void hclge_pci_uninit(struct hclge_dev *hdev)
6624 {
6625         struct pci_dev *pdev = hdev->pdev;
6626
6627         pcim_iounmap(pdev, hdev->hw.io_base);
6628         pci_free_irq_vectors(pdev);
6629         pci_clear_master(pdev);
6630         pci_release_mem_regions(pdev);
6631         pci_disable_device(pdev);
6632 }
6633
6634 static void hclge_state_init(struct hclge_dev *hdev)
6635 {
6636         set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
6637         set_bit(HCLGE_STATE_DOWN, &hdev->state);
6638         clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
6639         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
6640         clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
6641         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
6642 }
6643
6644 static void hclge_state_uninit(struct hclge_dev *hdev)
6645 {
6646         set_bit(HCLGE_STATE_DOWN, &hdev->state);
6647
6648         if (hdev->service_timer.function)
6649                 del_timer_sync(&hdev->service_timer);
6650         if (hdev->service_task.func)
6651                 cancel_work_sync(&hdev->service_task);
6652         if (hdev->rst_service_task.func)
6653                 cancel_work_sync(&hdev->rst_service_task);
6654         if (hdev->mbx_service_task.func)
6655                 cancel_work_sync(&hdev->mbx_service_task);
6656 }
6657
6658 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
6659 {
6660         struct pci_dev *pdev = ae_dev->pdev;
6661         struct hclge_dev *hdev;
6662         int ret;
6663
6664         hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
6665         if (!hdev) {
6666                 ret = -ENOMEM;
6667                 goto out;
6668         }
6669
6670         hdev->pdev = pdev;
6671         hdev->ae_dev = ae_dev;
6672         hdev->reset_type = HNAE3_NONE_RESET;
6673         ae_dev->priv = hdev;
6674
6675         ret = hclge_pci_init(hdev);
6676         if (ret) {
6677                 dev_err(&pdev->dev, "PCI init failed\n");
6678                 goto out;
6679         }
6680
6681         /* Firmware command queue initialize */
6682         ret = hclge_cmd_queue_init(hdev);
6683         if (ret) {
6684                 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
6685                 goto err_pci_uninit;
6686         }
6687
6688         /* Firmware command initialize */
6689         ret = hclge_cmd_init(hdev);
6690         if (ret)
6691                 goto err_cmd_uninit;
6692
6693         ret = hclge_get_cap(hdev);
6694         if (ret) {
6695                 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
6696                         ret);
6697                 goto err_cmd_uninit;
6698         }
6699
6700         ret = hclge_configure(hdev);
6701         if (ret) {
6702                 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
6703                 goto err_cmd_uninit;
6704         }
6705
6706         ret = hclge_init_msi(hdev);
6707         if (ret) {
6708                 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
6709                 goto err_cmd_uninit;
6710         }
6711
6712         ret = hclge_misc_irq_init(hdev);
6713         if (ret) {
6714                 dev_err(&pdev->dev,
6715                         "Misc IRQ(vector0) init error, ret = %d.\n",
6716                         ret);
6717                 goto err_msi_uninit;
6718         }
6719
6720         ret = hclge_alloc_tqps(hdev);
6721         if (ret) {
6722                 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
6723                 goto err_msi_irq_uninit;
6724         }
6725
6726         ret = hclge_alloc_vport(hdev);
6727         if (ret) {
6728                 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
6729                 goto err_msi_irq_uninit;
6730         }
6731
6732         ret = hclge_map_tqp(hdev);
6733         if (ret) {
6734                 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
6735                 goto err_msi_irq_uninit;
6736         }
6737
6738         if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
6739                 ret = hclge_mac_mdio_config(hdev);
6740                 if (ret) {
6741                         dev_err(&hdev->pdev->dev,
6742                                 "mdio config fail ret=%d\n", ret);
6743                         goto err_msi_irq_uninit;
6744                 }
6745         }
6746
6747         ret = hclge_init_umv_space(hdev);
6748         if (ret) {
6749                 dev_err(&pdev->dev, "umv space init error, ret=%d.\n", ret);
6750                 goto err_msi_irq_uninit;
6751         }
6752
6753         ret = hclge_mac_init(hdev);
6754         if (ret) {
6755                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
6756                 goto err_mdiobus_unreg;
6757         }
6758
6759         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
6760         if (ret) {
6761                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
6762                 goto err_mdiobus_unreg;
6763         }
6764
6765         ret = hclge_init_vlan_config(hdev);
6766         if (ret) {
6767                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
6768                 goto err_mdiobus_unreg;
6769         }
6770
6771         ret = hclge_tm_schd_init(hdev);
6772         if (ret) {
6773                 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
6774                 goto err_mdiobus_unreg;
6775         }
6776
6777         hclge_rss_init_cfg(hdev);
6778         ret = hclge_rss_init_hw(hdev);
6779         if (ret) {
6780                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
6781                 goto err_mdiobus_unreg;
6782         }
6783
6784         ret = init_mgr_tbl(hdev);
6785         if (ret) {
6786                 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
6787                 goto err_mdiobus_unreg;
6788         }
6789
6790         ret = hclge_init_fd_config(hdev);
6791         if (ret) {
6792                 dev_err(&pdev->dev,
6793                         "fd table init fail, ret=%d\n", ret);
6794                 goto err_mdiobus_unreg;
6795         }
6796
6797         ret = hclge_hw_error_set_state(hdev, true);
6798         if (ret) {
6799                 dev_err(&pdev->dev,
6800                         "hw error interrupts enable failed, ret =%d\n", ret);
6801                 goto err_mdiobus_unreg;
6802         }
6803
6804         hclge_dcb_ops_set(hdev);
6805
6806         timer_setup(&hdev->service_timer, hclge_service_timer, 0);
6807         INIT_WORK(&hdev->service_task, hclge_service_task);
6808         INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
6809         INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
6810
6811         hclge_clear_all_event_cause(hdev);
6812
6813         /* Enable MISC vector(vector0) */
6814         hclge_enable_vector(&hdev->misc_vector, true);
6815
6816         hclge_state_init(hdev);
6817
6818         pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
6819         return 0;
6820
6821 err_mdiobus_unreg:
6822         if (hdev->hw.mac.phydev)
6823                 mdiobus_unregister(hdev->hw.mac.mdio_bus);
6824 err_msi_irq_uninit:
6825         hclge_misc_irq_uninit(hdev);
6826 err_msi_uninit:
6827         pci_free_irq_vectors(pdev);
6828 err_cmd_uninit:
6829         hclge_destroy_cmd_queue(&hdev->hw);
6830 err_pci_uninit:
6831         pcim_iounmap(pdev, hdev->hw.io_base);
6832         pci_clear_master(pdev);
6833         pci_release_regions(pdev);
6834         pci_disable_device(pdev);
6835 out:
6836         return ret;
6837 }
6838
6839 static void hclge_stats_clear(struct hclge_dev *hdev)
6840 {
6841         memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
6842 }
6843
6844 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
6845 {
6846         struct hclge_dev *hdev = ae_dev->priv;
6847         struct pci_dev *pdev = ae_dev->pdev;
6848         int ret;
6849
6850         set_bit(HCLGE_STATE_DOWN, &hdev->state);
6851
6852         hclge_stats_clear(hdev);
6853         memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
6854
6855         ret = hclge_cmd_init(hdev);
6856         if (ret) {
6857                 dev_err(&pdev->dev, "Cmd queue init failed\n");
6858                 return ret;
6859         }
6860
6861         ret = hclge_get_cap(hdev);
6862         if (ret) {
6863                 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
6864                         ret);
6865                 return ret;
6866         }
6867
6868         ret = hclge_configure(hdev);
6869         if (ret) {
6870                 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
6871                 return ret;
6872         }
6873
6874         ret = hclge_map_tqp(hdev);
6875         if (ret) {
6876                 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
6877                 return ret;
6878         }
6879
6880         hclge_reset_umv_space(hdev);
6881
6882         ret = hclge_mac_init(hdev);
6883         if (ret) {
6884                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
6885                 return ret;
6886         }
6887
6888         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
6889         if (ret) {
6890                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
6891                 return ret;
6892         }
6893
6894         ret = hclge_init_vlan_config(hdev);
6895         if (ret) {
6896                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
6897                 return ret;
6898         }
6899
6900         ret = hclge_tm_init_hw(hdev);
6901         if (ret) {
6902                 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
6903                 return ret;
6904         }
6905
6906         ret = hclge_rss_init_hw(hdev);
6907         if (ret) {
6908                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
6909                 return ret;
6910         }
6911
6912         ret = hclge_init_fd_config(hdev);
6913         if (ret) {
6914                 dev_err(&pdev->dev,
6915                         "fd table init fail, ret=%d\n", ret);
6916                 return ret;
6917         }
6918
6919         /* Re-enable the TM hw error interrupts because
6920          * they get disabled on core/global reset.
6921          */
6922         if (hclge_enable_tm_hw_error(hdev, true))
6923                 dev_err(&pdev->dev, "failed to enable TM hw error interrupts\n");
6924
6925         dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
6926                  HCLGE_DRIVER_NAME);
6927
6928         return 0;
6929 }
6930
6931 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
6932 {
6933         struct hclge_dev *hdev = ae_dev->priv;
6934         struct hclge_mac *mac = &hdev->hw.mac;
6935
6936         hclge_state_uninit(hdev);
6937
6938         if (mac->phydev)
6939                 mdiobus_unregister(mac->mdio_bus);
6940
6941         hclge_uninit_umv_space(hdev);
6942
6943         /* Disable MISC vector(vector0) */
6944         hclge_enable_vector(&hdev->misc_vector, false);
6945         synchronize_irq(hdev->misc_vector.vector_irq);
6946
6947         hclge_hw_error_set_state(hdev, false);
6948         hclge_destroy_cmd_queue(&hdev->hw);
6949         hclge_misc_irq_uninit(hdev);
6950         hclge_pci_uninit(hdev);
6951         ae_dev->priv = NULL;
6952 }
6953
6954 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
6955 {
6956         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
6957         struct hclge_vport *vport = hclge_get_vport(handle);
6958         struct hclge_dev *hdev = vport->back;
6959
6960         return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
6961 }
6962
6963 static void hclge_get_channels(struct hnae3_handle *handle,
6964                                struct ethtool_channels *ch)
6965 {
6966         struct hclge_vport *vport = hclge_get_vport(handle);
6967
6968         ch->max_combined = hclge_get_max_channels(handle);
6969         ch->other_count = 1;
6970         ch->max_other = 1;
6971         ch->combined_count = vport->alloc_tqps;
6972 }
6973
6974 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
6975                                         u16 *alloc_tqps, u16 *max_rss_size)
6976 {
6977         struct hclge_vport *vport = hclge_get_vport(handle);
6978         struct hclge_dev *hdev = vport->back;
6979
6980         *alloc_tqps = vport->alloc_tqps;
6981         *max_rss_size = hdev->rss_size_max;
6982 }
6983
6984 static void hclge_release_tqp(struct hclge_vport *vport)
6985 {
6986         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
6987         struct hclge_dev *hdev = vport->back;
6988         int i;
6989
6990         for (i = 0; i < kinfo->num_tqps; i++) {
6991                 struct hclge_tqp *tqp =
6992                         container_of(kinfo->tqp[i], struct hclge_tqp, q);
6993
6994                 tqp->q.handle = NULL;
6995                 tqp->q.tqp_index = 0;
6996                 tqp->alloced = false;
6997         }
6998
6999         devm_kfree(&hdev->pdev->dev, kinfo->tqp);
7000         kinfo->tqp = NULL;
7001 }
7002
7003 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
7004 {
7005         struct hclge_vport *vport = hclge_get_vport(handle);
7006         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
7007         struct hclge_dev *hdev = vport->back;
7008         int cur_rss_size = kinfo->rss_size;
7009         int cur_tqps = kinfo->num_tqps;
7010         u16 tc_offset[HCLGE_MAX_TC_NUM];
7011         u16 tc_valid[HCLGE_MAX_TC_NUM];
7012         u16 tc_size[HCLGE_MAX_TC_NUM];
7013         u16 roundup_size;
7014         u32 *rss_indir;
7015         int ret, i;
7016
7017         /* Free old tqps, and reallocate with new tqp number when nic setup */
7018         hclge_release_tqp(vport);
7019
7020         ret = hclge_knic_setup(vport, new_tqps_num, kinfo->num_desc);
7021         if (ret) {
7022                 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
7023                 return ret;
7024         }
7025
7026         ret = hclge_map_tqp_to_vport(hdev, vport);
7027         if (ret) {
7028                 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
7029                 return ret;
7030         }
7031
7032         ret = hclge_tm_schd_init(hdev);
7033         if (ret) {
7034                 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
7035                 return ret;
7036         }
7037
7038         roundup_size = roundup_pow_of_two(kinfo->rss_size);
7039         roundup_size = ilog2(roundup_size);
7040         /* Set the RSS TC mode according to the new RSS size */
7041         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
7042                 tc_valid[i] = 0;
7043
7044                 if (!(hdev->hw_tc_map & BIT(i)))
7045                         continue;
7046
7047                 tc_valid[i] = 1;
7048                 tc_size[i] = roundup_size;
7049                 tc_offset[i] = kinfo->rss_size * i;
7050         }
7051         ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
7052         if (ret)
7053                 return ret;
7054
7055         /* Reinitializes the rss indirect table according to the new RSS size */
7056         rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
7057         if (!rss_indir)
7058                 return -ENOMEM;
7059
7060         for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
7061                 rss_indir[i] = i % kinfo->rss_size;
7062
7063         ret = hclge_set_rss(handle, rss_indir, NULL, 0);
7064         if (ret)
7065                 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
7066                         ret);
7067
7068         kfree(rss_indir);
7069
7070         if (!ret)
7071                 dev_info(&hdev->pdev->dev,
7072                          "Channels changed, rss_size from %d to %d, tqps from %d to %d",
7073                          cur_rss_size, kinfo->rss_size,
7074                          cur_tqps, kinfo->rss_size * kinfo->num_tc);
7075
7076         return ret;
7077 }
7078
7079 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
7080                               u32 *regs_num_64_bit)
7081 {
7082         struct hclge_desc desc;
7083         u32 total_num;
7084         int ret;
7085
7086         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
7087         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7088         if (ret) {
7089                 dev_err(&hdev->pdev->dev,
7090                         "Query register number cmd failed, ret = %d.\n", ret);
7091                 return ret;
7092         }
7093
7094         *regs_num_32_bit = le32_to_cpu(desc.data[0]);
7095         *regs_num_64_bit = le32_to_cpu(desc.data[1]);
7096
7097         total_num = *regs_num_32_bit + *regs_num_64_bit;
7098         if (!total_num)
7099                 return -EINVAL;
7100
7101         return 0;
7102 }
7103
7104 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
7105                                  void *data)
7106 {
7107 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
7108
7109         struct hclge_desc *desc;
7110         u32 *reg_val = data;
7111         __le32 *desc_data;
7112         int cmd_num;
7113         int i, k, n;
7114         int ret;
7115
7116         if (regs_num == 0)
7117                 return 0;
7118
7119         cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
7120         desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
7121         if (!desc)
7122                 return -ENOMEM;
7123
7124         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
7125         ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
7126         if (ret) {
7127                 dev_err(&hdev->pdev->dev,
7128                         "Query 32 bit register cmd failed, ret = %d.\n", ret);
7129                 kfree(desc);
7130                 return ret;
7131         }
7132
7133         for (i = 0; i < cmd_num; i++) {
7134                 if (i == 0) {
7135                         desc_data = (__le32 *)(&desc[i].data[0]);
7136                         n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
7137                 } else {
7138                         desc_data = (__le32 *)(&desc[i]);
7139                         n = HCLGE_32_BIT_REG_RTN_DATANUM;
7140                 }
7141                 for (k = 0; k < n; k++) {
7142                         *reg_val++ = le32_to_cpu(*desc_data++);
7143
7144                         regs_num--;
7145                         if (!regs_num)
7146                                 break;
7147                 }
7148         }
7149
7150         kfree(desc);
7151         return 0;
7152 }
7153
7154 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
7155                                  void *data)
7156 {
7157 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
7158
7159         struct hclge_desc *desc;
7160         u64 *reg_val = data;
7161         __le64 *desc_data;
7162         int cmd_num;
7163         int i, k, n;
7164         int ret;
7165
7166         if (regs_num == 0)
7167                 return 0;
7168
7169         cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
7170         desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
7171         if (!desc)
7172                 return -ENOMEM;
7173
7174         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
7175         ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
7176         if (ret) {
7177                 dev_err(&hdev->pdev->dev,
7178                         "Query 64 bit register cmd failed, ret = %d.\n", ret);
7179                 kfree(desc);
7180                 return ret;
7181         }
7182
7183         for (i = 0; i < cmd_num; i++) {
7184                 if (i == 0) {
7185                         desc_data = (__le64 *)(&desc[i].data[0]);
7186                         n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
7187                 } else {
7188                         desc_data = (__le64 *)(&desc[i]);
7189                         n = HCLGE_64_BIT_REG_RTN_DATANUM;
7190                 }
7191                 for (k = 0; k < n; k++) {
7192                         *reg_val++ = le64_to_cpu(*desc_data++);
7193
7194                         regs_num--;
7195                         if (!regs_num)
7196                                 break;
7197                 }
7198         }
7199
7200         kfree(desc);
7201         return 0;
7202 }
7203
7204 static int hclge_get_regs_len(struct hnae3_handle *handle)
7205 {
7206         struct hclge_vport *vport = hclge_get_vport(handle);
7207         struct hclge_dev *hdev = vport->back;
7208         u32 regs_num_32_bit, regs_num_64_bit;
7209         int ret;
7210
7211         ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
7212         if (ret) {
7213                 dev_err(&hdev->pdev->dev,
7214                         "Get register number failed, ret = %d.\n", ret);
7215                 return -EOPNOTSUPP;
7216         }
7217
7218         return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
7219 }
7220
7221 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
7222                            void *data)
7223 {
7224         struct hclge_vport *vport = hclge_get_vport(handle);
7225         struct hclge_dev *hdev = vport->back;
7226         u32 regs_num_32_bit, regs_num_64_bit;
7227         int ret;
7228
7229         *version = hdev->fw_version;
7230
7231         ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
7232         if (ret) {
7233                 dev_err(&hdev->pdev->dev,
7234                         "Get register number failed, ret = %d.\n", ret);
7235                 return;
7236         }
7237
7238         ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
7239         if (ret) {
7240                 dev_err(&hdev->pdev->dev,
7241                         "Get 32 bit register failed, ret = %d.\n", ret);
7242                 return;
7243         }
7244
7245         data = (u32 *)data + regs_num_32_bit;
7246         ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
7247                                     data);
7248         if (ret)
7249                 dev_err(&hdev->pdev->dev,
7250                         "Get 64 bit register failed, ret = %d.\n", ret);
7251 }
7252
7253 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
7254 {
7255         struct hclge_set_led_state_cmd *req;
7256         struct hclge_desc desc;
7257         int ret;
7258
7259         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
7260
7261         req = (struct hclge_set_led_state_cmd *)desc.data;
7262         hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
7263                         HCLGE_LED_LOCATE_STATE_S, locate_led_status);
7264
7265         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7266         if (ret)
7267                 dev_err(&hdev->pdev->dev,
7268                         "Send set led state cmd error, ret =%d\n", ret);
7269
7270         return ret;
7271 }
7272
7273 enum hclge_led_status {
7274         HCLGE_LED_OFF,
7275         HCLGE_LED_ON,
7276         HCLGE_LED_NO_CHANGE = 0xFF,
7277 };
7278
7279 static int hclge_set_led_id(struct hnae3_handle *handle,
7280                             enum ethtool_phys_id_state status)
7281 {
7282         struct hclge_vport *vport = hclge_get_vport(handle);
7283         struct hclge_dev *hdev = vport->back;
7284
7285         switch (status) {
7286         case ETHTOOL_ID_ACTIVE:
7287                 return hclge_set_led_status(hdev, HCLGE_LED_ON);
7288         case ETHTOOL_ID_INACTIVE:
7289                 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
7290         default:
7291                 return -EINVAL;
7292         }
7293 }
7294
7295 static void hclge_get_link_mode(struct hnae3_handle *handle,
7296                                 unsigned long *supported,
7297                                 unsigned long *advertising)
7298 {
7299         unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
7300         struct hclge_vport *vport = hclge_get_vport(handle);
7301         struct hclge_dev *hdev = vport->back;
7302         unsigned int idx = 0;
7303
7304         for (; idx < size; idx++) {
7305                 supported[idx] = hdev->hw.mac.supported[idx];
7306                 advertising[idx] = hdev->hw.mac.advertising[idx];
7307         }
7308 }
7309
7310 static const struct hnae3_ae_ops hclge_ops = {
7311         .init_ae_dev = hclge_init_ae_dev,
7312         .uninit_ae_dev = hclge_uninit_ae_dev,
7313         .init_client_instance = hclge_init_client_instance,
7314         .uninit_client_instance = hclge_uninit_client_instance,
7315         .map_ring_to_vector = hclge_map_ring_to_vector,
7316         .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
7317         .get_vector = hclge_get_vector,
7318         .put_vector = hclge_put_vector,
7319         .set_promisc_mode = hclge_set_promisc_mode,
7320         .set_loopback = hclge_set_loopback,
7321         .start = hclge_ae_start,
7322         .stop = hclge_ae_stop,
7323         .get_status = hclge_get_status,
7324         .get_ksettings_an_result = hclge_get_ksettings_an_result,
7325         .update_speed_duplex_h = hclge_update_speed_duplex_h,
7326         .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
7327         .get_media_type = hclge_get_media_type,
7328         .get_rss_key_size = hclge_get_rss_key_size,
7329         .get_rss_indir_size = hclge_get_rss_indir_size,
7330         .get_rss = hclge_get_rss,
7331         .set_rss = hclge_set_rss,
7332         .set_rss_tuple = hclge_set_rss_tuple,
7333         .get_rss_tuple = hclge_get_rss_tuple,
7334         .get_tc_size = hclge_get_tc_size,
7335         .get_mac_addr = hclge_get_mac_addr,
7336         .set_mac_addr = hclge_set_mac_addr,
7337         .do_ioctl = hclge_do_ioctl,
7338         .add_uc_addr = hclge_add_uc_addr,
7339         .rm_uc_addr = hclge_rm_uc_addr,
7340         .add_mc_addr = hclge_add_mc_addr,
7341         .rm_mc_addr = hclge_rm_mc_addr,
7342         .set_autoneg = hclge_set_autoneg,
7343         .get_autoneg = hclge_get_autoneg,
7344         .get_pauseparam = hclge_get_pauseparam,
7345         .set_pauseparam = hclge_set_pauseparam,
7346         .set_mtu = hclge_set_mtu,
7347         .reset_queue = hclge_reset_tqp,
7348         .get_stats = hclge_get_stats,
7349         .update_stats = hclge_update_stats,
7350         .get_strings = hclge_get_strings,
7351         .get_sset_count = hclge_get_sset_count,
7352         .get_fw_version = hclge_get_fw_version,
7353         .get_mdix_mode = hclge_get_mdix_mode,
7354         .enable_vlan_filter = hclge_enable_vlan_filter,
7355         .set_vlan_filter = hclge_set_vlan_filter,
7356         .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
7357         .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
7358         .reset_event = hclge_reset_event,
7359         .set_default_reset_request = hclge_set_def_reset_request,
7360         .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
7361         .set_channels = hclge_set_channels,
7362         .get_channels = hclge_get_channels,
7363         .get_regs_len = hclge_get_regs_len,
7364         .get_regs = hclge_get_regs,
7365         .set_led_id = hclge_set_led_id,
7366         .get_link_mode = hclge_get_link_mode,
7367         .add_fd_entry = hclge_add_fd_entry,
7368         .del_fd_entry = hclge_del_fd_entry,
7369         .del_all_fd_entries = hclge_del_all_fd_entries,
7370         .get_fd_rule_cnt = hclge_get_fd_rule_cnt,
7371         .get_fd_rule_info = hclge_get_fd_rule_info,
7372         .get_fd_all_rules = hclge_get_all_rules,
7373         .restore_fd_rules = hclge_restore_fd_entries,
7374         .enable_fd = hclge_enable_fd,
7375         .process_hw_error = hclge_process_ras_hw_error,
7376         .get_hw_reset_stat = hclge_get_hw_reset_stat,
7377         .ae_dev_resetting = hclge_ae_dev_resetting,
7378         .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt,
7379 };
7380
7381 static struct hnae3_ae_algo ae_algo = {
7382         .ops = &hclge_ops,
7383         .pdev_id_table = ae_algo_pci_tbl,
7384 };
7385
7386 static int hclge_init(void)
7387 {
7388         pr_info("%s is initializing\n", HCLGE_NAME);
7389
7390         hnae3_register_ae_algo(&ae_algo);
7391
7392         return 0;
7393 }
7394
7395 static void hclge_exit(void)
7396 {
7397         hnae3_unregister_ae_algo(&ae_algo);
7398 }
7399 module_init(hclge_init);
7400 module_exit(hclge_exit);
7401
7402 MODULE_LICENSE("GPL");
7403 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
7404 MODULE_DESCRIPTION("HCLGE Driver");
7405 MODULE_VERSION(HCLGE_MOD_VERSION);