drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/acpi.h>
   5 #include <linux/device.h>
   6 #include <linux/etherdevice.h>
   7 #include <linux/init.h>
   8 #include <linux/interrupt.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/pci.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/if_vlan.h>
  15 #include <net/rtnetlink.h>
  16 #include "hclge_cmd.h"
  17 #include "hclge_dcb.h"
  18 #include "hclge_main.h"
  19 #include "hclge_mbx.h"
  20 #include "hclge_mdio.h"
  21 #include "hclge_tm.h"
  22 #include "hclge_err.h"
  23 #include "hnae3.h"
  24
  25 #define HCLGE_NAME                      "hclge"
  26 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
  27 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
  28
  29 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
  30 static int hclge_init_vlan_config(struct hclge_dev *hdev);
  31 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
  32 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
  33                                u16 *allocated_size, bool is_alloc);
  34
  35 static struct hnae3_ae_algo ae_algo;
  36
  37 static const struct pci_device_id ae_algo_pci_tbl[] = {
  38         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
  39         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
  40         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
  41         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
  42         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
  43         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
  44         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
  45         /* required last entry */
  46         {0, }
  47 };
  48
  49 MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
  50
  51 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
  52         "App    Loopback test",
  53         "Serdes serial Loopback test",
  54         "Serdes parallel Loopback test",
  55         "Phy    Loopback test"
  56 };
  57
  58 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
  59         {"mac_tx_mac_pause_num",
  60                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
  61         {"mac_rx_mac_pause_num",
  62                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
  63         {"mac_tx_pfc_pri0_pkt_num",
  64                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
  65         {"mac_tx_pfc_pri1_pkt_num",
  66                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
  67         {"mac_tx_pfc_pri2_pkt_num",
  68                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
  69         {"mac_tx_pfc_pri3_pkt_num",
  70                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
  71         {"mac_tx_pfc_pri4_pkt_num",
  72                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
  73         {"mac_tx_pfc_pri5_pkt_num",
  74                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
  75         {"mac_tx_pfc_pri6_pkt_num",
  76                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
  77         {"mac_tx_pfc_pri7_pkt_num",
  78                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
  79         {"mac_rx_pfc_pri0_pkt_num",
  80                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
  81         {"mac_rx_pfc_pri1_pkt_num",
  82                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
  83         {"mac_rx_pfc_pri2_pkt_num",
  84                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
  85         {"mac_rx_pfc_pri3_pkt_num",
  86                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
  87         {"mac_rx_pfc_pri4_pkt_num",
  88                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
  89         {"mac_rx_pfc_pri5_pkt_num",
  90                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
  91         {"mac_rx_pfc_pri6_pkt_num",
  92                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
  93         {"mac_rx_pfc_pri7_pkt_num",
  94                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
  95         {"mac_tx_total_pkt_num",
  96                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
  97         {"mac_tx_total_oct_num",
  98                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
  99         {"mac_tx_good_pkt_num",
 100                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
 101         {"mac_tx_bad_pkt_num",
 102                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
 103         {"mac_tx_good_oct_num",
 104                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
 105         {"mac_tx_bad_oct_num",
 106                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
 107         {"mac_tx_uni_pkt_num",
 108                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
 109         {"mac_tx_multi_pkt_num",
 110                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
 111         {"mac_tx_broad_pkt_num",
 112                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
 113         {"mac_tx_undersize_pkt_num",
 114                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
 115         {"mac_tx_oversize_pkt_num",
 116                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
 117         {"mac_tx_64_oct_pkt_num",
 118                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
 119         {"mac_tx_65_127_oct_pkt_num",
 120                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
 121         {"mac_tx_128_255_oct_pkt_num",
 122                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
 123         {"mac_tx_256_511_oct_pkt_num",
 124                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
 125         {"mac_tx_512_1023_oct_pkt_num",
 126                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
 127         {"mac_tx_1024_1518_oct_pkt_num",
 128                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
 129         {"mac_tx_1519_2047_oct_pkt_num",
 130                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
 131         {"mac_tx_2048_4095_oct_pkt_num",
 132                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
 133         {"mac_tx_4096_8191_oct_pkt_num",
 134                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
 135         {"mac_tx_8192_9216_oct_pkt_num",
 136                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
 137         {"mac_tx_9217_12287_oct_pkt_num",
 138                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
 139         {"mac_tx_12288_16383_oct_pkt_num",
 140                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
 141         {"mac_tx_1519_max_good_pkt_num",
 142                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
 143         {"mac_tx_1519_max_bad_pkt_num",
 144                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
 145         {"mac_rx_total_pkt_num",
 146                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
 147         {"mac_rx_total_oct_num",
 148                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
 149         {"mac_rx_good_pkt_num",
 150                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
 151         {"mac_rx_bad_pkt_num",
 152                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
 153         {"mac_rx_good_oct_num",
 154                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
 155         {"mac_rx_bad_oct_num",
 156                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
 157         {"mac_rx_uni_pkt_num",
 158                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
 159         {"mac_rx_multi_pkt_num",
 160                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
 161         {"mac_rx_broad_pkt_num",
 162                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
 163         {"mac_rx_undersize_pkt_num",
 164                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
 165         {"mac_rx_oversize_pkt_num",
 166                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
 167         {"mac_rx_64_oct_pkt_num",
 168                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
 169         {"mac_rx_65_127_oct_pkt_num",
 170                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
 171         {"mac_rx_128_255_oct_pkt_num",
 172                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
 173         {"mac_rx_256_511_oct_pkt_num",
 174                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
 175         {"mac_rx_512_1023_oct_pkt_num",
 176                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
 177         {"mac_rx_1024_1518_oct_pkt_num",
 178                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
 179         {"mac_rx_1519_2047_oct_pkt_num",
 180                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
 181         {"mac_rx_2048_4095_oct_pkt_num",
 182                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
 183         {"mac_rx_4096_8191_oct_pkt_num",
 184                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
 185         {"mac_rx_8192_9216_oct_pkt_num",
 186                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
 187         {"mac_rx_9217_12287_oct_pkt_num",
 188                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
 189         {"mac_rx_12288_16383_oct_pkt_num",
 190                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
 191         {"mac_rx_1519_max_good_pkt_num",
 192                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
 193         {"mac_rx_1519_max_bad_pkt_num",
 194                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
 195
 196         {"mac_tx_fragment_pkt_num",
 197                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
 198         {"mac_tx_undermin_pkt_num",
 199                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
 200         {"mac_tx_jabber_pkt_num",
 201                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
 202         {"mac_tx_err_all_pkt_num",
 203                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
 204         {"mac_tx_from_app_good_pkt_num",
 205                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
 206         {"mac_tx_from_app_bad_pkt_num",
 207                 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
 208         {"mac_rx_fragment_pkt_num",
 209                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
 210         {"mac_rx_undermin_pkt_num",
 211                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
 212         {"mac_rx_jabber_pkt_num",
 213                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
 214         {"mac_rx_fcs_err_pkt_num",
 215                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
 216         {"mac_rx_send_app_good_pkt_num",
 217                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
 218         {"mac_rx_send_app_bad_pkt_num",
 219                 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
 220 };
 221
 222 static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
 223         {
 224                 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
 225                 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
 226                 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
 227                 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
 228                 .i_port_bitmap = 0x1,
 229         },
 230 };
 231
 232 static int hclge_mac_update_stats(struct hclge_dev *hdev)
 233 {
 234 #define HCLGE_MAC_CMD_NUM 21
 235 #define HCLGE_RTN_DATA_NUM 4
 236
 237         u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
 238         struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
 239         __le64 *desc_data;
 240         int i, k, n;
 241         int ret;
 242
 243         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
 244         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
 245         if (ret) {
 246                 dev_err(&hdev->pdev->dev,
 247                         "Get MAC pkt stats fail, status = %d.\n", ret);
 248
 249                 return ret;
 250         }
 251
 252         for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
 253                 if (unlikely(i == 0)) {
 254                         desc_data = (__le64 *)(&desc[i].data[0]);
 255                         n = HCLGE_RTN_DATA_NUM - 2;
 256                 } else {
 257                         desc_data = (__le64 *)(&desc[i]);
 258                         n = HCLGE_RTN_DATA_NUM;
 259                 }
 260                 for (k = 0; k < n; k++) {
 261                         *data++ += le64_to_cpu(*desc_data);
 262                         desc_data++;
 263                 }
 264         }
 265
 266         return 0;
 267 }
 268
 269 static int hclge_tqps_update_stats(struct hnae3_handle *handle)
 270 {
 271         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 272         struct hclge_vport *vport = hclge_get_vport(handle);
 273         struct hclge_dev *hdev = vport->back;
 274         struct hnae3_queue *queue;
 275         struct hclge_desc desc[1];
 276         struct hclge_tqp *tqp;
 277         int ret, i;
 278
 279         for (i = 0; i < kinfo->num_tqps; i++) {
 280                 queue = handle->kinfo.tqp[i];
 281                 tqp = container_of(queue, struct hclge_tqp, q);
 282                 /* command : HCLGE_OPC_QUERY_IGU_STAT */
 283                 hclge_cmd_setup_basic_desc(&desc[0],
 284                                            HCLGE_OPC_QUERY_RX_STATUS,
 285                                            true);
 286
 287                 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
 288                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
 289                 if (ret) {
 290                         dev_err(&hdev->pdev->dev,
 291                                 "Query tqp stat fail, status = %d,queue = %d\n",
 292                                 ret,    i);
 293                         return ret;
 294                 }
 295                 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
 296                         le32_to_cpu(desc[0].data[1]);
 297         }
 298
 299         for (i = 0; i < kinfo->num_tqps; i++) {
 300                 queue = handle->kinfo.tqp[i];
 301                 tqp = container_of(queue, struct hclge_tqp, q);
 302                 /* command : HCLGE_OPC_QUERY_IGU_STAT */
 303                 hclge_cmd_setup_basic_desc(&desc[0],
 304                                            HCLGE_OPC_QUERY_TX_STATUS,
 305                                            true);
 306
 307                 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
 308                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
 309                 if (ret) {
 310                         dev_err(&hdev->pdev->dev,
 311                                 "Query tqp stat fail, status = %d,queue = %d\n",
 312                                 ret, i);
 313                         return ret;
 314                 }
 315                 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
 316                         le32_to_cpu(desc[0].data[1]);
 317         }
 318
 319         return 0;
 320 }
 321
 322 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
 323 {
 324         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 325         struct hclge_tqp *tqp;
 326         u64 *buff = data;
 327         int i;
 328
 329         for (i = 0; i < kinfo->num_tqps; i++) {
 330                 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
 331                 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
 332         }
 333
 334         for (i = 0; i < kinfo->num_tqps; i++) {
 335                 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
 336                 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
 337         }
 338
 339         return buff;
 340 }
 341
 342 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
 343 {
 344         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 345
 346         return kinfo->num_tqps * (2);
 347 }
 348
 349 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
 350 {
 351         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 352         u8 *buff = data;
 353         int i = 0;
 354
 355         for (i = 0; i < kinfo->num_tqps; i++) {
 356                 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
 357                         struct hclge_tqp, q);
 358                 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
 359                          tqp->index);
 360                 buff = buff + ETH_GSTRING_LEN;
 361         }
 362
 363         for (i = 0; i < kinfo->num_tqps; i++) {
 364                 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
 365                         struct hclge_tqp, q);
 366                 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
 367                          tqp->index);
 368                 buff = buff + ETH_GSTRING_LEN;
 369         }
 370
 371         return buff;
 372 }
 373
 374 static u64 *hclge_comm_get_stats(void *comm_stats,
 375                                  const struct hclge_comm_stats_str strs[],
 376                                  int size, u64 *data)
 377 {
 378         u64 *buf = data;
 379         u32 i;
 380
 381         for (i = 0; i < size; i++)
 382                 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
 383
 384         return buf + size;
 385 }
 386
 387 static u8 *hclge_comm_get_strings(u32 stringset,
 388                                   const struct hclge_comm_stats_str strs[],
 389                                   int size, u8 *data)
 390 {
 391         char *buff = (char *)data;
 392         u32 i;
 393
 394         if (stringset != ETH_SS_STATS)
 395                 return buff;
 396
 397         for (i = 0; i < size; i++) {
 398                 snprintf(buff, ETH_GSTRING_LEN,
 399                          strs[i].desc);
 400                 buff = buff + ETH_GSTRING_LEN;
 401         }
 402
 403         return (u8 *)buff;
 404 }
 405
 406 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
 407                                  struct net_device_stats *net_stats)
 408 {
 409         net_stats->tx_dropped = 0;
 410         net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 411         net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
 412         net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
 413
 414         net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
 415         net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
 416
 417         net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
 418         net_stats->rx_length_errors =
 419                 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
 420         net_stats->rx_length_errors +=
 421                 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 422         net_stats->rx_over_errors =
 423                 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
 424 }
 425
 426 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
 427 {
 428         struct hnae3_handle *handle;
 429         int status;
 430
 431         handle = &hdev->vport[0].nic;
 432         if (handle->client) {
 433                 status = hclge_tqps_update_stats(handle);
 434                 if (status) {
 435                         dev_err(&hdev->pdev->dev,
 436                                 "Update TQPS stats fail, status = %d.\n",
 437                                 status);
 438                 }
 439         }
 440
 441         status = hclge_mac_update_stats(hdev);
 442         if (status)
 443                 dev_err(&hdev->pdev->dev,
 444                         "Update MAC stats fail, status = %d.\n", status);
 445
 446         hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
 447 }
 448
 449 static void hclge_update_stats(struct hnae3_handle *handle,
 450                                struct net_device_stats *net_stats)
 451 {
 452         struct hclge_vport *vport = hclge_get_vport(handle);
 453         struct hclge_dev *hdev = vport->back;
 454         struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
 455         int status;
 456
 457         if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
 458                 return;
 459
 460         status = hclge_mac_update_stats(hdev);
 461         if (status)
 462                 dev_err(&hdev->pdev->dev,
 463                         "Update MAC stats fail, status = %d.\n",
 464                         status);
 465
 466         status = hclge_tqps_update_stats(handle);
 467         if (status)
 468                 dev_err(&hdev->pdev->dev,
 469                         "Update TQPS stats fail, status = %d.\n",
 470                         status);
 471
 472         hclge_update_netstat(hw_stats, net_stats);
 473
 474         clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
 475 }
 476
 477 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
 478 {
 479 #define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK |\
 480                 HNAE3_SUPPORT_PHY_LOOPBACK |\
 481                 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK |\
 482                 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK)
 483
 484         struct hclge_vport *vport = hclge_get_vport(handle);
 485         struct hclge_dev *hdev = vport->back;
 486         int count = 0;
 487
 488         /* Loopback test support rules:
 489          * mac: only GE mode support
 490          * serdes: all mac mode will support include GE/XGE/LGE/CGE
 491          * phy: only support when phy device exist on board
 492          */
 493         if (stringset == ETH_SS_TEST) {
 494                 /* clear loopback bit flags at first */
 495                 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
 496                 if (hdev->pdev->revision >= 0x21 ||
 497                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
 498                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
 499                     hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
 500                         count += 1;
 501                         handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
 502                 }
 503
 504                 count += 2;
 505                 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
 506                 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
 507         } else if (stringset == ETH_SS_STATS) {
 508                 count = ARRAY_SIZE(g_mac_stats_string) +
 509                         hclge_tqps_get_sset_count(handle, stringset);
 510         }
 511
 512         return count;
 513 }
 514
 515 static void hclge_get_strings(struct hnae3_handle *handle,
 516                               u32 stringset,
 517                               u8 *data)
 518 {
 519         u8 *p = (char *)data;
 520         int size;
 521
 522         if (stringset == ETH_SS_STATS) {
 523                 size = ARRAY_SIZE(g_mac_stats_string);
 524                 p = hclge_comm_get_strings(stringset,
 525                                            g_mac_stats_string,
 526                                            size,
 527                                            p);
 528                 p = hclge_tqps_get_strings(handle, p);
 529         } else if (stringset == ETH_SS_TEST) {
 530                 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
 531                         memcpy(p,
 532                                hns3_nic_test_strs[HNAE3_LOOP_APP],
 533                                ETH_GSTRING_LEN);
 534                         p += ETH_GSTRING_LEN;
 535                 }
 536                 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) {
 537                         memcpy(p,
 538                                hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES],
 539                                ETH_GSTRING_LEN);
 540                         p += ETH_GSTRING_LEN;
 541                 }
 542                 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) {
 543                         memcpy(p,
 544                                hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES],
 545                                ETH_GSTRING_LEN);
 546                         p += ETH_GSTRING_LEN;
 547                 }
 548                 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
 549                         memcpy(p,
 550                                hns3_nic_test_strs[HNAE3_LOOP_PHY],
 551                                ETH_GSTRING_LEN);
 552                         p += ETH_GSTRING_LEN;
 553                 }
 554         }
 555 }
 556
 557 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
 558 {
 559         struct hclge_vport *vport = hclge_get_vport(handle);
 560         struct hclge_dev *hdev = vport->back;
 561         u64 *p;
 562
 563         p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
 564                                  g_mac_stats_string,
 565                                  ARRAY_SIZE(g_mac_stats_string),
 566                                  data);
 567         p = hclge_tqps_get_stats(handle, p);
 568 }
 569
 570 static int hclge_parse_func_status(struct hclge_dev *hdev,
 571                                    struct hclge_func_status_cmd *status)
 572 {
 573         if (!(status->pf_state & HCLGE_PF_STATE_DONE))
 574                 return -EINVAL;
 575
 576         /* Set the pf to main pf */
 577         if (status->pf_state & HCLGE_PF_STATE_MAIN)
 578                 hdev->flag |= HCLGE_FLAG_MAIN;
 579         else
 580                 hdev->flag &= ~HCLGE_FLAG_MAIN;
 581
 582         return 0;
 583 }
 584
 585 static int hclge_query_function_status(struct hclge_dev *hdev)
 586 {
 587         struct hclge_func_status_cmd *req;
 588         struct hclge_desc desc;
 589         int timeout = 0;
 590         int ret;
 591
 592         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
 593         req = (struct hclge_func_status_cmd *)desc.data;
 594
 595         do {
 596                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 597                 if (ret) {
 598                         dev_err(&hdev->pdev->dev,
 599                                 "query function status failed %d.\n",
 600                                 ret);
 601
 602                         return ret;
 603                 }
 604
 605                 /* Check pf reset is done */
 606                 if (req->pf_state)
 607                         break;
 608                 usleep_range(1000, 2000);
 609         } while (timeout++ < 5);
 610
 611         ret = hclge_parse_func_status(hdev, req);
 612
 613         return ret;
 614 }
 615
 616 static int hclge_query_pf_resource(struct hclge_dev *hdev)
 617 {
 618         struct hclge_pf_res_cmd *req;
 619         struct hclge_desc desc;
 620         int ret;
 621
 622         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
 623         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 624         if (ret) {
 625                 dev_err(&hdev->pdev->dev,
 626                         "query pf resource failed %d.\n", ret);
 627                 return ret;
 628         }
 629
 630         req = (struct hclge_pf_res_cmd *)desc.data;
 631         hdev->num_tqps = __le16_to_cpu(req->tqp_num);
 632         hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
 633
 634         if (hnae3_dev_roce_supported(hdev)) {
 635                 hdev->roce_base_msix_offset =
 636                 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
 637                                 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
 638                 hdev->num_roce_msi =
 639                 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
 640                                 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
 641
 642                 /* PF should have NIC vectors and Roce vectors,
 643                  * NIC vectors are queued before Roce vectors.
 644                  */
 645                 hdev->num_msi = hdev->num_roce_msi  +
 646                                 hdev->roce_base_msix_offset;
 647         } else {
 648                 hdev->num_msi =
 649                 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
 650                                 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
 651         }
 652
 653         return 0;
 654 }
 655
 656 static int hclge_parse_speed(int speed_cmd, int *speed)
 657 {
 658         switch (speed_cmd) {
 659         case 6:
 660                 *speed = HCLGE_MAC_SPEED_10M;
 661                 break;
 662         case 7:
 663                 *speed = HCLGE_MAC_SPEED_100M;
 664                 break;
 665         case 0:
 666                 *speed = HCLGE_MAC_SPEED_1G;
 667                 break;
 668         case 1:
 669                 *speed = HCLGE_MAC_SPEED_10G;
 670                 break;
 671         case 2:
 672                 *speed = HCLGE_MAC_SPEED_25G;
 673                 break;
 674         case 3:
 675                 *speed = HCLGE_MAC_SPEED_40G;
 676                 break;
 677         case 4:
 678                 *speed = HCLGE_MAC_SPEED_50G;
 679                 break;
 680         case 5:
 681                 *speed = HCLGE_MAC_SPEED_100G;
 682                 break;
 683         default:
 684                 return -EINVAL;
 685         }
 686
 687         return 0;
 688 }
 689
 690 static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
 691                                         u8 speed_ability)
 692 {
 693         unsigned long *supported = hdev->hw.mac.supported;
 694
 695         if (speed_ability & HCLGE_SUPPORT_1G_BIT)
 696                 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
 697                         supported);
 698
 699         if (speed_ability & HCLGE_SUPPORT_10G_BIT)
 700                 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
 701                         supported);
 702
 703         if (speed_ability & HCLGE_SUPPORT_25G_BIT)
 704                 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
 705                         supported);
 706
 707         if (speed_ability & HCLGE_SUPPORT_50G_BIT)
 708                 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
 709                         supported);
 710
 711         if (speed_ability & HCLGE_SUPPORT_100G_BIT)
 712                 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
 713                         supported);
 714
 715         set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
 716         set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
 717 }
 718
 719 static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
 720 {
 721         u8 media_type = hdev->hw.mac.media_type;
 722
 723         if (media_type != HNAE3_MEDIA_TYPE_FIBER)
 724                 return;
 725
 726         hclge_parse_fiber_link_mode(hdev, speed_ability);
 727 }
 728
 729 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
 730 {
 731         struct hclge_cfg_param_cmd *req;
 732         u64 mac_addr_tmp_high;
 733         u64 mac_addr_tmp;
 734         int i;
 735
 736         req = (struct hclge_cfg_param_cmd *)desc[0].data;
 737
 738         /* get the configuration */
 739         cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
 740                                               HCLGE_CFG_VMDQ_M,
 741                                               HCLGE_CFG_VMDQ_S);
 742         cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
 743                                       HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
 744         cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
 745                                             HCLGE_CFG_TQP_DESC_N_M,
 746                                             HCLGE_CFG_TQP_DESC_N_S);
 747
 748         cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
 749                                         HCLGE_CFG_PHY_ADDR_M,
 750                                         HCLGE_CFG_PHY_ADDR_S);
 751         cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
 752                                           HCLGE_CFG_MEDIA_TP_M,
 753                                           HCLGE_CFG_MEDIA_TP_S);
 754         cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
 755                                           HCLGE_CFG_RX_BUF_LEN_M,
 756                                           HCLGE_CFG_RX_BUF_LEN_S);
 757         /* get mac_address */
 758         mac_addr_tmp = __le32_to_cpu(req->param[2]);
 759         mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
 760                                             HCLGE_CFG_MAC_ADDR_H_M,
 761                                             HCLGE_CFG_MAC_ADDR_H_S);
 762
 763         mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
 764
 765         cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
 766                                              HCLGE_CFG_DEFAULT_SPEED_M,
 767                                              HCLGE_CFG_DEFAULT_SPEED_S);
 768         cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
 769                                             HCLGE_CFG_RSS_SIZE_M,
 770                                             HCLGE_CFG_RSS_SIZE_S);
 771
 772         for (i = 0; i < ETH_ALEN; i++)
 773                 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
 774
 775         req = (struct hclge_cfg_param_cmd *)desc[1].data;
 776         cfg->numa_node_map = __le32_to_cpu(req->param[0]);
 777
 778         cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
 779                                              HCLGE_CFG_SPEED_ABILITY_M,
 780                                              HCLGE_CFG_SPEED_ABILITY_S);
 781         cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]),
 782                                          HCLGE_CFG_UMV_TBL_SPACE_M,
 783                                          HCLGE_CFG_UMV_TBL_SPACE_S);
 784         if (!cfg->umv_space)
 785                 cfg->umv_space = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
 786 }
 787
 788 /* hclge_get_cfg: query the static parameter from flash
 789  * @hdev: pointer to struct hclge_dev
 790  * @hcfg: the config structure to be getted
 791  */
 792 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
 793 {
 794         struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
 795         struct hclge_cfg_param_cmd *req;
 796         int i, ret;
 797
 798         for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
 799                 u32 offset = 0;
 800
 801                 req = (struct hclge_cfg_param_cmd *)desc[i].data;
 802                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
 803                                            true);
 804                 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
 805                                 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
 806                 /* Len should be united by 4 bytes when send to hardware */
 807                 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
 808                                 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
 809                 req->offset = cpu_to_le32(offset);
 810         }
 811
 812         ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
 813         if (ret) {
 814                 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
 815                 return ret;
 816         }
 817
 818         hclge_parse_cfg(hcfg, desc);
 819
 820         return 0;
 821 }
 822
 823 static int hclge_get_cap(struct hclge_dev *hdev)
 824 {
 825         int ret;
 826
 827         ret = hclge_query_function_status(hdev);
 828         if (ret) {
 829                 dev_err(&hdev->pdev->dev,
 830                         "query function status error %d.\n", ret);
 831                 return ret;
 832         }
 833
 834         /* get pf resource */
 835         ret = hclge_query_pf_resource(hdev);
 836         if (ret)
 837                 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
 838
 839         return ret;
 840 }
 841
 842 static int hclge_configure(struct hclge_dev *hdev)
 843 {
 844         struct hclge_cfg cfg;
 845         int ret, i;
 846
 847         ret = hclge_get_cfg(hdev, &cfg);
 848         if (ret) {
 849                 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
 850                 return ret;
 851         }
 852
 853         hdev->num_vmdq_vport = cfg.vmdq_vport_num;
 854         hdev->base_tqp_pid = 0;
 855         hdev->rss_size_max = cfg.rss_size_max;
 856         hdev->rx_buf_len = cfg.rx_buf_len;
 857         ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
 858         hdev->hw.mac.media_type = cfg.media_type;
 859         hdev->hw.mac.phy_addr = cfg.phy_addr;
 860         hdev->num_desc = cfg.tqp_desc_num;
 861         hdev->tm_info.num_pg = 1;
 862         hdev->tc_max = cfg.tc_num;
 863         hdev->tm_info.hw_pfc_map = 0;
 864         hdev->wanted_umv_size = cfg.umv_space;
 865
 866         ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
 867         if (ret) {
 868                 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
 869                 return ret;
 870         }
 871
 872         hclge_parse_link_mode(hdev, cfg.speed_ability);
 873
 874         if ((hdev->tc_max > HNAE3_MAX_TC) ||
 875             (hdev->tc_max < 1)) {
 876                 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
 877                          hdev->tc_max);
 878                 hdev->tc_max = 1;
 879         }
 880
 881         /* Dev does not support DCB */
 882         if (!hnae3_dev_dcb_supported(hdev)) {
 883                 hdev->tc_max = 1;
 884                 hdev->pfc_max = 0;
 885         } else {
 886                 hdev->pfc_max = hdev->tc_max;
 887         }
 888
 889         hdev->tm_info.num_tc = hdev->tc_max;
 890
 891         /* Currently not support uncontiuous tc */
 892         for (i = 0; i < hdev->tm_info.num_tc; i++)
 893                 hnae3_set_bit(hdev->hw_tc_map, i, 1);
 894
 895         hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
 896
 897         return ret;
 898 }
 899
 900 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
 901                             int tso_mss_max)
 902 {
 903         struct hclge_cfg_tso_status_cmd *req;
 904         struct hclge_desc desc;
 905         u16 tso_mss;
 906
 907         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
 908
 909         req = (struct hclge_cfg_tso_status_cmd *)desc.data;
 910
 911         tso_mss = 0;
 912         hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
 913                         HCLGE_TSO_MSS_MIN_S, tso_mss_min);
 914         req->tso_mss_min = cpu_to_le16(tso_mss);
 915
 916         tso_mss = 0;
 917         hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
 918                         HCLGE_TSO_MSS_MIN_S, tso_mss_max);
 919         req->tso_mss_max = cpu_to_le16(tso_mss);
 920
 921         return hclge_cmd_send(&hdev->hw, &desc, 1);
 922 }
 923
 924 static int hclge_alloc_tqps(struct hclge_dev *hdev)
 925 {
 926         struct hclge_tqp *tqp;
 927         int i;
 928
 929         hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
 930                                   sizeof(struct hclge_tqp), GFP_KERNEL);
 931         if (!hdev->htqp)
 932                 return -ENOMEM;
 933
 934         tqp = hdev->htqp;
 935
 936         for (i = 0; i < hdev->num_tqps; i++) {
 937                 tqp->dev = &hdev->pdev->dev;
 938                 tqp->index = i;
 939
 940                 tqp->q.ae_algo = &ae_algo;
 941                 tqp->q.buf_size = hdev->rx_buf_len;
 942                 tqp->q.desc_num = hdev->num_desc;
 943                 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
 944                         i * HCLGE_TQP_REG_SIZE;
 945
 946                 tqp++;
 947         }
 948
 949         return 0;
 950 }
 951
 952 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
 953                                   u16 tqp_pid, u16 tqp_vid, bool is_pf)
 954 {
 955         struct hclge_tqp_map_cmd *req;
 956         struct hclge_desc desc;
 957         int ret;
 958
 959         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
 960
 961         req = (struct hclge_tqp_map_cmd *)desc.data;
 962         req->tqp_id = cpu_to_le16(tqp_pid);
 963         req->tqp_vf = func_id;
 964         req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
 965                         1 << HCLGE_TQP_MAP_EN_B;
 966         req->tqp_vid = cpu_to_le16(tqp_vid);
 967
 968         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
 969         if (ret)
 970                 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
 971
 972         return ret;
 973 }
 974
 975 static int  hclge_assign_tqp(struct hclge_vport *vport)
 976 {
 977         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
 978         struct hclge_dev *hdev = vport->back;
 979         int i, alloced;
 980
 981         for (i = 0, alloced = 0; i < hdev->num_tqps &&
 982              alloced < kinfo->num_tqps; i++) {
 983                 if (!hdev->htqp[i].alloced) {
 984                         hdev->htqp[i].q.handle = &vport->nic;
 985                         hdev->htqp[i].q.tqp_index = alloced;
 986                         hdev->htqp[i].q.desc_num = kinfo->num_desc;
 987                         kinfo->tqp[alloced] = &hdev->htqp[i].q;
 988                         hdev->htqp[i].alloced = true;
 989                         alloced++;
 990                 }
 991         }
 992         vport->alloc_tqps = kinfo->num_tqps;
 993
 994         return 0;
 995 }
 996
 997 static int hclge_knic_setup(struct hclge_vport *vport,
 998                             u16 num_tqps, u16 num_desc)
 999 {
1000         struct hnae3_handle *nic = &vport->nic;
1001         struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1002         struct hclge_dev *hdev = vport->back;
1003         int i, ret;
1004
1005         kinfo->num_desc = num_desc;
1006         kinfo->rx_buf_len = hdev->rx_buf_len;
1007         kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1008         kinfo->rss_size
1009                 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1010         kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1011
1012         for (i = 0; i < HNAE3_MAX_TC; i++) {
1013                 if (hdev->hw_tc_map & BIT(i)) {
1014                         kinfo->tc_info[i].enable = true;
1015                         kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1016                         kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1017                         kinfo->tc_info[i].tc = i;
1018                 } else {
1019                         /* Set to default queue if TC is disable */
1020                         kinfo->tc_info[i].enable = false;
1021                         kinfo->tc_info[i].tqp_offset = 0;
1022                         kinfo->tc_info[i].tqp_count = 1;
1023                         kinfo->tc_info[i].tc = 0;
1024                 }
1025         }
1026
1027         kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1028                                   sizeof(struct hnae3_queue *), GFP_KERNEL);
1029         if (!kinfo->tqp)
1030                 return -ENOMEM;
1031
1032         ret = hclge_assign_tqp(vport);
1033         if (ret)
1034                 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1035
1036         return ret;
1037 }
1038
1039 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1040                                   struct hclge_vport *vport)
1041 {
1042         struct hnae3_handle *nic = &vport->nic;
1043         struct hnae3_knic_private_info *kinfo;
1044         u16 i;
1045
1046         kinfo = &nic->kinfo;
1047         for (i = 0; i < kinfo->num_tqps; i++) {
1048                 struct hclge_tqp *q =
1049                         container_of(kinfo->tqp[i], struct hclge_tqp, q);
1050                 bool is_pf;
1051                 int ret;
1052
1053                 is_pf = !(vport->vport_id);
1054                 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1055                                              i, is_pf);
1056                 if (ret)
1057                         return ret;
1058         }
1059
1060         return 0;
1061 }
1062
1063 static int hclge_map_tqp(struct hclge_dev *hdev)
1064 {
1065         struct hclge_vport *vport = hdev->vport;
1066         u16 i, num_vport;
1067
1068         num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1069         for (i = 0; i < num_vport; i++) {
1070                 int ret;
1071
1072                 ret = hclge_map_tqp_to_vport(hdev, vport);
1073                 if (ret)
1074                         return ret;
1075
1076                 vport++;
1077         }
1078
1079         return 0;
1080 }
1081
1082 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1083 {
1084         /* this would be initialized later */
1085 }
1086
1087 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1088 {
1089         struct hnae3_handle *nic = &vport->nic;
1090         struct hclge_dev *hdev = vport->back;
1091         int ret;
1092
1093         nic->pdev = hdev->pdev;
1094         nic->ae_algo = &ae_algo;
1095         nic->numa_node_mask = hdev->numa_node_mask;
1096
1097         if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1098                 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc);
1099                 if (ret) {
1100                         dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1101                                 ret);
1102                         return ret;
1103                 }
1104         } else {
1105                 hclge_unic_setup(vport, num_tqps);
1106         }
1107
1108         return 0;
1109 }
1110
1111 static int hclge_alloc_vport(struct hclge_dev *hdev)
1112 {
1113         struct pci_dev *pdev = hdev->pdev;
1114         struct hclge_vport *vport;
1115         u32 tqp_main_vport;
1116         u32 tqp_per_vport;
1117         int num_vport, i;
1118         int ret;
1119
1120         /* We need to alloc a vport for main NIC of PF */
1121         num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1122
1123         if (hdev->num_tqps < num_vport) {
1124                 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1125                         hdev->num_tqps, num_vport);
1126                 return -EINVAL;
1127         }
1128
1129         /* Alloc the same number of TQPs for every vport */
1130         tqp_per_vport = hdev->num_tqps / num_vport;
1131         tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1132
1133         vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1134                              GFP_KERNEL);
1135         if (!vport)
1136                 return -ENOMEM;
1137
1138         hdev->vport = vport;
1139         hdev->num_alloc_vport = num_vport;
1140
1141         if (IS_ENABLED(CONFIG_PCI_IOV))
1142                 hdev->num_alloc_vfs = hdev->num_req_vfs;
1143
1144         for (i = 0; i < num_vport; i++) {
1145                 vport->back = hdev;
1146                 vport->vport_id = i;
1147
1148                 if (i == 0)
1149                         ret = hclge_vport_setup(vport, tqp_main_vport);
1150                 else
1151                         ret = hclge_vport_setup(vport, tqp_per_vport);
1152                 if (ret) {
1153                         dev_err(&pdev->dev,
1154                                 "vport setup failed for vport %d, %d\n",
1155                                 i, ret);
1156                         return ret;
1157                 }
1158
1159                 vport++;
1160         }
1161
1162         return 0;
1163 }
1164
1165 static int  hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1166                                     struct hclge_pkt_buf_alloc *buf_alloc)
1167 {
1168 /* TX buffer size is unit by 128 byte */
1169 #define HCLGE_BUF_SIZE_UNIT_SHIFT       7
1170 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK    BIT(15)
1171         struct hclge_tx_buff_alloc_cmd *req;
1172         struct hclge_desc desc;
1173         int ret;
1174         u8 i;
1175
1176         req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1177
1178         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1179         for (i = 0; i < HCLGE_TC_NUM; i++) {
1180                 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1181
1182                 req->tx_pkt_buff[i] =
1183                         cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1184                                      HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1185         }
1186
1187         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1188         if (ret)
1189                 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1190                         ret);
1191
1192         return ret;
1193 }
1194
1195 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1196                                  struct hclge_pkt_buf_alloc *buf_alloc)
1197 {
1198         int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1199
1200         if (ret)
1201                 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
1202
1203         return ret;
1204 }
1205
1206 static int hclge_get_tc_num(struct hclge_dev *hdev)
1207 {
1208         int i, cnt = 0;
1209
1210         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1211                 if (hdev->hw_tc_map & BIT(i))
1212                         cnt++;
1213         return cnt;
1214 }
1215
1216 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1217 {
1218         int i, cnt = 0;
1219
1220         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1221                 if (hdev->hw_tc_map & BIT(i) &&
1222                     hdev->tm_info.hw_pfc_map & BIT(i))
1223                         cnt++;
1224         return cnt;
1225 }
1226
1227 /* Get the number of pfc enabled TCs, which have private buffer */
1228 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1229                                   struct hclge_pkt_buf_alloc *buf_alloc)
1230 {
1231         struct hclge_priv_buf *priv;
1232         int i, cnt = 0;
1233
1234         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1235                 priv = &buf_alloc->priv_buf[i];
1236                 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1237                     priv->enable)
1238                         cnt++;
1239         }
1240
1241         return cnt;
1242 }
1243
1244 /* Get the number of pfc disabled TCs, which have private buffer */
1245 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1246                                      struct hclge_pkt_buf_alloc *buf_alloc)
1247 {
1248         struct hclge_priv_buf *priv;
1249         int i, cnt = 0;
1250
1251         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1252                 priv = &buf_alloc->priv_buf[i];
1253                 if (hdev->hw_tc_map & BIT(i) &&
1254                     !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1255                     priv->enable)
1256                         cnt++;
1257         }
1258
1259         return cnt;
1260 }
1261
1262 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1263 {
1264         struct hclge_priv_buf *priv;
1265         u32 rx_priv = 0;
1266         int i;
1267
1268         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1269                 priv = &buf_alloc->priv_buf[i];
1270                 if (priv->enable)
1271                         rx_priv += priv->buf_size;
1272         }
1273         return rx_priv;
1274 }
1275
1276 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1277 {
1278         u32 i, total_tx_size = 0;
1279
1280         for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1281                 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1282
1283         return total_tx_size;
1284 }
1285
1286 static bool  hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1287                                 struct hclge_pkt_buf_alloc *buf_alloc,
1288                                 u32 rx_all)
1289 {
1290         u32 shared_buf_min, shared_buf_tc, shared_std;
1291         int tc_num, pfc_enable_num;
1292         u32 shared_buf;
1293         u32 rx_priv;
1294         int i;
1295
1296         tc_num = hclge_get_tc_num(hdev);
1297         pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1298
1299         if (hnae3_dev_dcb_supported(hdev))
1300                 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1301         else
1302                 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1303
1304         shared_buf_tc = pfc_enable_num * hdev->mps +
1305                         (tc_num - pfc_enable_num) * hdev->mps / 2 +
1306                         hdev->mps;
1307         shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1308
1309         rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
1310         if (rx_all <= rx_priv + shared_std)
1311                 return false;
1312
1313         shared_buf = rx_all - rx_priv;
1314         buf_alloc->s_buf.buf_size = shared_buf;
1315         buf_alloc->s_buf.self.high = shared_buf;
1316         buf_alloc->s_buf.self.low =  2 * hdev->mps;
1317
1318         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1319                 if ((hdev->hw_tc_map & BIT(i)) &&
1320                     (hdev->tm_info.hw_pfc_map & BIT(i))) {
1321                         buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1322                         buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
1323                 } else {
1324                         buf_alloc->s_buf.tc_thrd[i].low = 0;
1325                         buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
1326                 }
1327         }
1328
1329         return true;
1330 }
1331
1332 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1333                                 struct hclge_pkt_buf_alloc *buf_alloc)
1334 {
1335         u32 i, total_size;
1336
1337         total_size = hdev->pkt_buf_size;
1338
1339         /* alloc tx buffer for all enabled tc */
1340         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1341                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1342
1343                 if (total_size < HCLGE_DEFAULT_TX_BUF)
1344                         return -ENOMEM;
1345
1346                 if (hdev->hw_tc_map & BIT(i))
1347                         priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1348                 else
1349                         priv->tx_buf_size = 0;
1350
1351                 total_size -= priv->tx_buf_size;
1352         }
1353
1354         return 0;
1355 }
1356
1357 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1358  * @hdev: pointer to struct hclge_dev
1359  * @buf_alloc: pointer to buffer calculation data
1360  * @return: 0: calculate sucessful, negative: fail
1361  */
1362 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1363                                 struct hclge_pkt_buf_alloc *buf_alloc)
1364 {
1365 #define HCLGE_BUF_SIZE_UNIT     128
1366         u32 rx_all = hdev->pkt_buf_size, aligned_mps;
1367         int no_pfc_priv_num, pfc_priv_num;
1368         struct hclge_priv_buf *priv;
1369         int i;
1370
1371         aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT);
1372         rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
1373
1374         /* When DCB is not supported, rx private
1375          * buffer is not allocated.
1376          */
1377         if (!hnae3_dev_dcb_supported(hdev)) {
1378                 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1379                         return -ENOMEM;
1380
1381                 return 0;
1382         }
1383
1384         /* step 1, try to alloc private buffer for all enabled tc */
1385         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1386                 priv = &buf_alloc->priv_buf[i];
1387                 if (hdev->hw_tc_map & BIT(i)) {
1388                         priv->enable = 1;
1389                         if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1390                                 priv->wl.low = aligned_mps;
1391                                 priv->wl.high = priv->wl.low + aligned_mps;
1392                                 priv->buf_size = priv->wl.high +
1393                                                 HCLGE_DEFAULT_DV;
1394                         } else {
1395                                 priv->wl.low = 0;
1396                                 priv->wl.high = 2 * aligned_mps;
1397                                 priv->buf_size = priv->wl.high;
1398                         }
1399                 } else {
1400                         priv->enable = 0;
1401                         priv->wl.low = 0;
1402                         priv->wl.high = 0;
1403                         priv->buf_size = 0;
1404                 }
1405         }
1406
1407         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1408                 return 0;
1409
1410         /* step 2, try to decrease the buffer size of
1411          * no pfc TC's private buffer
1412          */
1413         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1414                 priv = &buf_alloc->priv_buf[i];
1415
1416                 priv->enable = 0;
1417                 priv->wl.low = 0;
1418                 priv->wl.high = 0;
1419                 priv->buf_size = 0;
1420
1421                 if (!(hdev->hw_tc_map & BIT(i)))
1422                         continue;
1423
1424                 priv->enable = 1;
1425
1426                 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1427                         priv->wl.low = 128;
1428                         priv->wl.high = priv->wl.low + aligned_mps;
1429                         priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1430                 } else {
1431                         priv->wl.low = 0;
1432                         priv->wl.high = aligned_mps;
1433                         priv->buf_size = priv->wl.high;
1434                 }
1435         }
1436
1437         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1438                 return 0;
1439
1440         /* step 3, try to reduce the number of pfc disabled TCs,
1441          * which have private buffer
1442          */
1443         /* get the total no pfc enable TC number, which have private buffer */
1444         no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
1445
1446         /* let the last to be cleared first */
1447         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1448                 priv = &buf_alloc->priv_buf[i];
1449
1450                 if (hdev->hw_tc_map & BIT(i) &&
1451                     !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1452                         /* Clear the no pfc TC private buffer */
1453                         priv->wl.low = 0;
1454                         priv->wl.high = 0;
1455                         priv->buf_size = 0;
1456                         priv->enable = 0;
1457                         no_pfc_priv_num--;
1458                 }
1459
1460                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1461                     no_pfc_priv_num == 0)
1462                         break;
1463         }
1464
1465         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1466                 return 0;
1467
1468         /* step 4, try to reduce the number of pfc enabled TCs
1469          * which have private buffer.
1470          */
1471         pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
1472
1473         /* let the last to be cleared first */
1474         for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1475                 priv = &buf_alloc->priv_buf[i];
1476
1477                 if (hdev->hw_tc_map & BIT(i) &&
1478                     hdev->tm_info.hw_pfc_map & BIT(i)) {
1479                         /* Reduce the number of pfc TC with private buffer */
1480                         priv->wl.low = 0;
1481                         priv->enable = 0;
1482                         priv->wl.high = 0;
1483                         priv->buf_size = 0;
1484                         pfc_priv_num--;
1485                 }
1486
1487                 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1488                     pfc_priv_num == 0)
1489                         break;
1490         }
1491         if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1492                 return 0;
1493
1494         return -ENOMEM;
1495 }
1496
1497 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1498                                    struct hclge_pkt_buf_alloc *buf_alloc)
1499 {
1500         struct hclge_rx_priv_buff_cmd *req;
1501         struct hclge_desc desc;
1502         int ret;
1503         int i;
1504
1505         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1506         req = (struct hclge_rx_priv_buff_cmd *)desc.data;
1507
1508         /* Alloc private buffer TCs */
1509         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1510                 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1511
1512                 req->buf_num[i] =
1513                         cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1514                 req->buf_num[i] |=
1515                         cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
1516         }
1517
1518         req->shared_buf =
1519                 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
1520                             (1 << HCLGE_TC0_PRI_BUF_EN_B));
1521
1522         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1523         if (ret)
1524                 dev_err(&hdev->pdev->dev,
1525                         "rx private buffer alloc cmd failed %d\n", ret);
1526
1527         return ret;
1528 }
1529
1530 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1531                                    struct hclge_pkt_buf_alloc *buf_alloc)
1532 {
1533         struct hclge_rx_priv_wl_buf *req;
1534         struct hclge_priv_buf *priv;
1535         struct hclge_desc desc[2];
1536         int i, j;
1537         int ret;
1538
1539         for (i = 0; i < 2; i++) {
1540                 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1541                                            false);
1542                 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1543
1544                 /* The first descriptor set the NEXT bit to 1 */
1545                 if (i == 0)
1546                         desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1547                 else
1548                         desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1549
1550                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1551                         u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1552
1553                         priv = &buf_alloc->priv_buf[idx];
1554                         req->tc_wl[j].high =
1555                                 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1556                         req->tc_wl[j].high |=
1557                                 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1558                         req->tc_wl[j].low =
1559                                 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1560                         req->tc_wl[j].low |=
1561                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1562                 }
1563         }
1564
1565         /* Send 2 descriptor at one time */
1566         ret = hclge_cmd_send(&hdev->hw, desc, 2);
1567         if (ret)
1568                 dev_err(&hdev->pdev->dev,
1569                         "rx private waterline config cmd failed %d\n",
1570                         ret);
1571         return ret;
1572 }
1573
1574 static int hclge_common_thrd_config(struct hclge_dev *hdev,
1575                                     struct hclge_pkt_buf_alloc *buf_alloc)
1576 {
1577         struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
1578         struct hclge_rx_com_thrd *req;
1579         struct hclge_desc desc[2];
1580         struct hclge_tc_thrd *tc;
1581         int i, j;
1582         int ret;
1583
1584         for (i = 0; i < 2; i++) {
1585                 hclge_cmd_setup_basic_desc(&desc[i],
1586                                            HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1587                 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1588
1589                 /* The first descriptor set the NEXT bit to 1 */
1590                 if (i == 0)
1591                         desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1592                 else
1593                         desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1594
1595                 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1596                         tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1597
1598                         req->com_thrd[j].high =
1599                                 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1600                         req->com_thrd[j].high |=
1601                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1602                         req->com_thrd[j].low =
1603                                 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1604                         req->com_thrd[j].low |=
1605                                  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1606                 }
1607         }
1608
1609         /* Send 2 descriptors at one time */
1610         ret = hclge_cmd_send(&hdev->hw, desc, 2);
1611         if (ret)
1612                 dev_err(&hdev->pdev->dev,
1613                         "common threshold config cmd failed %d\n", ret);
1614         return ret;
1615 }
1616
1617 static int hclge_common_wl_config(struct hclge_dev *hdev,
1618                                   struct hclge_pkt_buf_alloc *buf_alloc)
1619 {
1620         struct hclge_shared_buf *buf = &buf_alloc->s_buf;
1621         struct hclge_rx_com_wl *req;
1622         struct hclge_desc desc;
1623         int ret;
1624
1625         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1626
1627         req = (struct hclge_rx_com_wl *)desc.data;
1628         req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1629         req->com_wl.high |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1630
1631         req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1632         req->com_wl.low |=  cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
1633
1634         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1635         if (ret)
1636                 dev_err(&hdev->pdev->dev,
1637                         "common waterline config cmd failed %d\n", ret);
1638
1639         return ret;
1640 }
1641
1642 int hclge_buffer_alloc(struct hclge_dev *hdev)
1643 {
1644         struct hclge_pkt_buf_alloc *pkt_buf;
1645         int ret;
1646
1647         pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1648         if (!pkt_buf)
1649                 return -ENOMEM;
1650
1651         ret = hclge_tx_buffer_calc(hdev, pkt_buf);
1652         if (ret) {
1653                 dev_err(&hdev->pdev->dev,
1654                         "could not calc tx buffer size for all TCs %d\n", ret);
1655                 goto out;
1656         }
1657
1658         ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
1659         if (ret) {
1660                 dev_err(&hdev->pdev->dev,
1661                         "could not alloc tx buffers %d\n", ret);
1662                 goto out;
1663         }
1664
1665         ret = hclge_rx_buffer_calc(hdev, pkt_buf);
1666         if (ret) {
1667                 dev_err(&hdev->pdev->dev,
1668                         "could not calc rx priv buffer size for all TCs %d\n",
1669                         ret);
1670                 goto out;
1671         }
1672
1673         ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
1674         if (ret) {
1675                 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1676                         ret);
1677                 goto out;
1678         }
1679
1680         if (hnae3_dev_dcb_supported(hdev)) {
1681                 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
1682                 if (ret) {
1683                         dev_err(&hdev->pdev->dev,
1684                                 "could not configure rx private waterline %d\n",
1685                                 ret);
1686                         goto out;
1687                 }
1688
1689                 ret = hclge_common_thrd_config(hdev, pkt_buf);
1690                 if (ret) {
1691                         dev_err(&hdev->pdev->dev,
1692                                 "could not configure common threshold %d\n",
1693                                 ret);
1694                         goto out;
1695                 }
1696         }
1697
1698         ret = hclge_common_wl_config(hdev, pkt_buf);
1699         if (ret)
1700                 dev_err(&hdev->pdev->dev,
1701                         "could not configure common waterline %d\n", ret);
1702
1703 out:
1704         kfree(pkt_buf);
1705         return ret;
1706 }
1707
1708 static int hclge_init_roce_base_info(struct hclge_vport *vport)
1709 {
1710         struct hnae3_handle *roce = &vport->roce;
1711         struct hnae3_handle *nic = &vport->nic;
1712
1713         roce->rinfo.num_vectors = vport->back->num_roce_msi;
1714
1715         if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1716             vport->back->num_msi_left == 0)
1717                 return -EINVAL;
1718
1719         roce->rinfo.base_vector = vport->back->roce_base_vector;
1720
1721         roce->rinfo.netdev = nic->kinfo.netdev;
1722         roce->rinfo.roce_io_base = vport->back->hw.io_base;
1723
1724         roce->pdev = nic->pdev;
1725         roce->ae_algo = nic->ae_algo;
1726         roce->numa_node_mask = nic->numa_node_mask;
1727
1728         return 0;
1729 }
1730
1731 static int hclge_init_msi(struct hclge_dev *hdev)
1732 {
1733         struct pci_dev *pdev = hdev->pdev;
1734         int vectors;
1735         int i;
1736
1737         vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1738                                         PCI_IRQ_MSI | PCI_IRQ_MSIX);
1739         if (vectors < 0) {
1740                 dev_err(&pdev->dev,
1741                         "failed(%d) to allocate MSI/MSI-X vectors\n",
1742                         vectors);
1743                 return vectors;
1744         }
1745         if (vectors < hdev->num_msi)
1746                 dev_warn(&hdev->pdev->dev,
1747                          "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1748                          hdev->num_msi, vectors);
1749
1750         hdev->num_msi = vectors;
1751         hdev->num_msi_left = vectors;
1752         hdev->base_msi_vector = pdev->irq;
1753         hdev->roce_base_vector = hdev->base_msi_vector +
1754                                 hdev->roce_base_msix_offset;
1755
1756         hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1757                                            sizeof(u16), GFP_KERNEL);
1758         if (!hdev->vector_status) {
1759                 pci_free_irq_vectors(pdev);
1760                 return -ENOMEM;
1761         }
1762
1763         for (i = 0; i < hdev->num_msi; i++)
1764                 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1765
1766         hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1767                                         sizeof(int), GFP_KERNEL);
1768         if (!hdev->vector_irq) {
1769                 pci_free_irq_vectors(pdev);
1770                 return -ENOMEM;
1771         }
1772
1773         return 0;
1774 }
1775
1776 static u8 hclge_check_speed_dup(u8 duplex, int speed)
1777 {
1778
1779         if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
1780                 duplex = HCLGE_MAC_FULL;
1781
1782         return duplex;
1783 }
1784
1785 static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
1786                                       u8 duplex)
1787 {
1788         struct hclge_config_mac_speed_dup_cmd *req;
1789         struct hclge_desc desc;
1790         int ret;
1791
1792         req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
1793
1794         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
1795
1796         hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
1797
1798         switch (speed) {
1799         case HCLGE_MAC_SPEED_10M:
1800                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1801                                 HCLGE_CFG_SPEED_S, 6);
1802                 break;
1803         case HCLGE_MAC_SPEED_100M:
1804                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1805                                 HCLGE_CFG_SPEED_S, 7);
1806                 break;
1807         case HCLGE_MAC_SPEED_1G:
1808                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1809                                 HCLGE_CFG_SPEED_S, 0);
1810                 break;
1811         case HCLGE_MAC_SPEED_10G:
1812                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1813                                 HCLGE_CFG_SPEED_S, 1);
1814                 break;
1815         case HCLGE_MAC_SPEED_25G:
1816                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1817                                 HCLGE_CFG_SPEED_S, 2);
1818                 break;
1819         case HCLGE_MAC_SPEED_40G:
1820                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1821                                 HCLGE_CFG_SPEED_S, 3);
1822                 break;
1823         case HCLGE_MAC_SPEED_50G:
1824                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1825                                 HCLGE_CFG_SPEED_S, 4);
1826                 break;
1827         case HCLGE_MAC_SPEED_100G:
1828                 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1829                                 HCLGE_CFG_SPEED_S, 5);
1830                 break;
1831         default:
1832                 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
1833                 return -EINVAL;
1834         }
1835
1836         hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1837                       1);
1838
1839         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1840         if (ret) {
1841                 dev_err(&hdev->pdev->dev,
1842                         "mac speed/duplex config cmd failed %d.\n", ret);
1843                 return ret;
1844         }
1845
1846         return 0;
1847 }
1848
1849 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1850 {
1851         int ret;
1852
1853         duplex = hclge_check_speed_dup(duplex, speed);
1854         if (hdev->hw.mac.speed == speed && hdev->hw.mac.duplex == duplex)
1855                 return 0;
1856
1857         ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);
1858         if (ret)
1859                 return ret;
1860
1861         hdev->hw.mac.speed = speed;
1862         hdev->hw.mac.duplex = duplex;
1863
1864         return 0;
1865 }
1866
1867 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
1868                                      u8 duplex)
1869 {
1870         struct hclge_vport *vport = hclge_get_vport(handle);
1871         struct hclge_dev *hdev = vport->back;
1872
1873         return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
1874 }
1875
1876 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
1877                                         u8 *duplex)
1878 {
1879         struct hclge_query_an_speed_dup_cmd *req;
1880         struct hclge_desc desc;
1881         int speed_tmp;
1882         int ret;
1883
1884         req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
1885
1886         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
1887         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1888         if (ret) {
1889                 dev_err(&hdev->pdev->dev,
1890                         "mac speed/autoneg/duplex query cmd failed %d\n",
1891                         ret);
1892                 return ret;
1893         }
1894
1895         *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
1896         speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
1897                                     HCLGE_QUERY_SPEED_S);
1898
1899         ret = hclge_parse_speed(speed_tmp, speed);
1900         if (ret)
1901                 dev_err(&hdev->pdev->dev,
1902                         "could not parse speed(=%d), %d\n", speed_tmp, ret);
1903
1904         return ret;
1905 }
1906
1907 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
1908 {
1909         struct hclge_config_auto_neg_cmd *req;
1910         struct hclge_desc desc;
1911         u32 flag = 0;
1912         int ret;
1913
1914         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
1915
1916         req = (struct hclge_config_auto_neg_cmd *)desc.data;
1917         hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
1918         req->cfg_an_cmd_flag = cpu_to_le32(flag);
1919
1920         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1921         if (ret)
1922                 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
1923                         ret);
1924
1925         return ret;
1926 }
1927
1928 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
1929 {
1930         struct hclge_vport *vport = hclge_get_vport(handle);
1931         struct hclge_dev *hdev = vport->back;
1932
1933         return hclge_set_autoneg_en(hdev, enable);
1934 }
1935
1936 static int hclge_get_autoneg(struct hnae3_handle *handle)
1937 {
1938         struct hclge_vport *vport = hclge_get_vport(handle);
1939         struct hclge_dev *hdev = vport->back;
1940         struct phy_device *phydev = hdev->hw.mac.phydev;
1941
1942         if (phydev)
1943                 return phydev->autoneg;
1944
1945         return hdev->hw.mac.autoneg;
1946 }
1947
1948 static int hclge_mac_init(struct hclge_dev *hdev)
1949 {
1950         struct hnae3_handle *handle = &hdev->vport[0].nic;
1951         struct net_device *netdev = handle->kinfo.netdev;
1952         struct hclge_mac *mac = &hdev->hw.mac;
1953         int mtu;
1954         int ret;
1955
1956         hdev->hw.mac.duplex = HCLGE_MAC_FULL;
1957         ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
1958                                          hdev->hw.mac.duplex);
1959         if (ret) {
1960                 dev_err(&hdev->pdev->dev,
1961                         "Config mac speed dup fail ret=%d\n", ret);
1962                 return ret;
1963         }
1964
1965         mac->link = 0;
1966
1967         if (netdev)
1968                 mtu = netdev->mtu;
1969         else
1970                 mtu = ETH_DATA_LEN;
1971
1972         ret = hclge_set_mtu(handle, mtu);
1973         if (ret)
1974                 dev_err(&hdev->pdev->dev,
1975                         "set mtu failed ret=%d\n", ret);
1976
1977         return ret;
1978 }
1979
1980 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
1981 {
1982         if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
1983                 schedule_work(&hdev->mbx_service_task);
1984 }
1985
1986 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
1987 {
1988         if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
1989                 schedule_work(&hdev->rst_service_task);
1990 }
1991
1992 static void hclge_task_schedule(struct hclge_dev *hdev)
1993 {
1994         if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
1995             !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
1996             !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
1997                 (void)schedule_work(&hdev->service_task);
1998 }
1999
2000 static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2001 {
2002         struct hclge_link_status_cmd *req;
2003         struct hclge_desc desc;
2004         int link_status;
2005         int ret;
2006
2007         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2008         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2009         if (ret) {
2010                 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2011                         ret);
2012                 return ret;
2013         }
2014
2015         req = (struct hclge_link_status_cmd *)desc.data;
2016         link_status = req->status & HCLGE_LINK_STATUS_UP_M;
2017
2018         return !!link_status;
2019 }
2020
2021 static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2022 {
2023         int mac_state;
2024         int link_stat;
2025
2026         if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
2027                 return 0;
2028
2029         mac_state = hclge_get_mac_link_status(hdev);
2030
2031         if (hdev->hw.mac.phydev) {
2032                 if (hdev->hw.mac.phydev->state == PHY_RUNNING)
2033                         link_stat = mac_state &
2034                                 hdev->hw.mac.phydev->link;
2035                 else
2036                         link_stat = 0;
2037
2038         } else {
2039                 link_stat = mac_state;
2040         }
2041
2042         return !!link_stat;
2043 }
2044
2045 static void hclge_update_link_status(struct hclge_dev *hdev)
2046 {
2047         struct hnae3_client *client = hdev->nic_client;
2048         struct hnae3_handle *handle;
2049         int state;
2050         int i;
2051
2052         if (!client)
2053                 return;
2054         state = hclge_get_mac_phy_link(hdev);
2055         if (state != hdev->hw.mac.link) {
2056                 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2057                         handle = &hdev->vport[i].nic;
2058                         client->ops->link_status_change(handle, state);
2059                 }
2060                 hdev->hw.mac.link = state;
2061         }
2062 }
2063
2064 static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2065 {
2066         struct hclge_mac mac = hdev->hw.mac;
2067         u8 duplex;
2068         int speed;
2069         int ret;
2070
2071         /* get the speed and duplex as autoneg'result from mac cmd when phy
2072          * doesn't exit.
2073          */
2074         if (mac.phydev || !mac.autoneg)
2075                 return 0;
2076
2077         ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2078         if (ret) {
2079                 dev_err(&hdev->pdev->dev,
2080                         "mac autoneg/speed/duplex query failed %d\n", ret);
2081                 return ret;
2082         }
2083
2084         ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2085         if (ret) {
2086                 dev_err(&hdev->pdev->dev,
2087                         "mac speed/duplex config failed %d\n", ret);
2088                 return ret;
2089         }
2090
2091         return 0;
2092 }
2093
2094 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2095 {
2096         struct hclge_vport *vport = hclge_get_vport(handle);
2097         struct hclge_dev *hdev = vport->back;
2098
2099         return hclge_update_speed_duplex(hdev);
2100 }
2101
2102 static int hclge_get_status(struct hnae3_handle *handle)
2103 {
2104         struct hclge_vport *vport = hclge_get_vport(handle);
2105         struct hclge_dev *hdev = vport->back;
2106
2107         hclge_update_link_status(hdev);
2108
2109         return hdev->hw.mac.link;
2110 }
2111
2112 static void hclge_service_timer(struct timer_list *t)
2113 {
2114         struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
2115
2116         mod_timer(&hdev->service_timer, jiffies + HZ);
2117         hdev->hw_stats.stats_timer++;
2118         hclge_task_schedule(hdev);
2119 }
2120
2121 static void hclge_service_complete(struct hclge_dev *hdev)
2122 {
2123         WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2124
2125         /* Flush memory before next watchdog */
2126         smp_mb__before_atomic();
2127         clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2128 }
2129
2130 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2131 {
2132         u32 rst_src_reg;
2133         u32 cmdq_src_reg;
2134
2135         /* fetch the events from their corresponding regs */
2136         rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
2137         cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2138
2139         /* Assumption: If by any chance reset and mailbox events are reported
2140          * together then we will only process reset event in this go and will
2141          * defer the processing of the mailbox events. Since, we would have not
2142          * cleared RX CMDQ event this time we would receive again another
2143          * interrupt from H/W just for the mailbox.
2144          */
2145
2146         /* check for vector0 reset event sources */
2147         if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2148                 dev_info(&hdev->pdev->dev, "global reset interrupt\n");
2149                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2150                 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2151                 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2152                 return HCLGE_VECTOR0_EVENT_RST;
2153         }
2154
2155         if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2156                 dev_info(&hdev->pdev->dev, "core reset interrupt\n");
2157                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2158                 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2159                 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2160                 return HCLGE_VECTOR0_EVENT_RST;
2161         }
2162
2163         if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2164                 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
2165                 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2166                 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2167                 return HCLGE_VECTOR0_EVENT_RST;
2168         }
2169
2170         /* check for vector0 mailbox(=CMDQ RX) event source */
2171         if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2172                 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2173                 *clearval = cmdq_src_reg;
2174                 return HCLGE_VECTOR0_EVENT_MBX;
2175         }
2176
2177         return HCLGE_VECTOR0_EVENT_OTHER;
2178 }
2179
2180 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2181                                     u32 regclr)
2182 {
2183         switch (event_type) {
2184         case HCLGE_VECTOR0_EVENT_RST:
2185                 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2186                 break;
2187         case HCLGE_VECTOR0_EVENT_MBX:
2188                 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2189                 break;
2190         default:
2191                 break;
2192         }
2193 }
2194
2195 static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2196 {
2197         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2198                                 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2199                                 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2200                                 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2201         hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2202 }
2203
2204 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2205 {
2206         writel(enable ? 1 : 0, vector->addr);
2207 }
2208
2209 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2210 {
2211         struct hclge_dev *hdev = data;
2212         u32 event_cause;
2213         u32 clearval;
2214
2215         hclge_enable_vector(&hdev->misc_vector, false);
2216         event_cause = hclge_check_event_cause(hdev, &clearval);
2217
2218         /* vector 0 interrupt is shared with reset and mailbox source events.*/
2219         switch (event_cause) {
2220         case HCLGE_VECTOR0_EVENT_RST:
2221                 hclge_reset_task_schedule(hdev);
2222                 break;
2223         case HCLGE_VECTOR0_EVENT_MBX:
2224                 /* If we are here then,
2225                  * 1. Either we are not handling any mbx task and we are not
2226                  *    scheduled as well
2227                  *                        OR
2228                  * 2. We could be handling a mbx task but nothing more is
2229                  *    scheduled.
2230                  * In both cases, we should schedule mbx task as there are more
2231                  * mbx messages reported by this interrupt.
2232                  */
2233                 hclge_mbx_task_schedule(hdev);
2234                 break;
2235         default:
2236                 dev_warn(&hdev->pdev->dev,
2237                          "received unknown or unhandled event of vector0\n");
2238                 break;
2239         }
2240
2241         /* clear the source of interrupt if it is not cause by reset */
2242         if (event_cause == HCLGE_VECTOR0_EVENT_MBX) {
2243                 hclge_clear_event_cause(hdev, event_cause, clearval);
2244                 hclge_enable_vector(&hdev->misc_vector, true);
2245         }
2246
2247         return IRQ_HANDLED;
2248 }
2249
2250 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2251 {
2252         if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2253                 dev_warn(&hdev->pdev->dev,
2254                          "vector(vector_id %d) has been freed.\n", vector_id);
2255                 return;
2256         }
2257
2258         hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2259         hdev->num_msi_left += 1;
2260         hdev->num_msi_used -= 1;
2261 }
2262
2263 static void hclge_get_misc_vector(struct hclge_dev *hdev)
2264 {
2265         struct hclge_misc_vector *vector = &hdev->misc_vector;
2266
2267         vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2268
2269         vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2270         hdev->vector_status[0] = 0;
2271
2272         hdev->num_msi_left -= 1;
2273         hdev->num_msi_used += 1;
2274 }
2275
2276 static int hclge_misc_irq_init(struct hclge_dev *hdev)
2277 {
2278         int ret;
2279
2280         hclge_get_misc_vector(hdev);
2281
2282         /* this would be explicitly freed in the end */
2283         ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2284                           0, "hclge_misc", hdev);
2285         if (ret) {
2286                 hclge_free_vector(hdev, 0);
2287                 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2288                         hdev->misc_vector.vector_irq);
2289         }
2290
2291         return ret;
2292 }
2293
2294 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2295 {
2296         free_irq(hdev->misc_vector.vector_irq, hdev);
2297         hclge_free_vector(hdev, 0);
2298 }
2299
2300 static int hclge_notify_client(struct hclge_dev *hdev,
2301                                enum hnae3_reset_notify_type type)
2302 {
2303         struct hnae3_client *client = hdev->nic_client;
2304         u16 i;
2305
2306         if (!client->ops->reset_notify)
2307                 return -EOPNOTSUPP;
2308
2309         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2310                 struct hnae3_handle *handle = &hdev->vport[i].nic;
2311                 int ret;
2312
2313                 ret = client->ops->reset_notify(handle, type);
2314                 if (ret) {
2315                         dev_err(&hdev->pdev->dev,
2316                                 "notify nic client failed %d(%d)\n", type, ret);
2317                         return ret;
2318                 }
2319         }
2320
2321         return 0;
2322 }
2323
2324 static int hclge_notify_roce_client(struct hclge_dev *hdev,
2325                                     enum hnae3_reset_notify_type type)
2326 {
2327         struct hnae3_client *client = hdev->roce_client;
2328         int ret = 0;
2329         u16 i;
2330
2331         if (!client)
2332                 return 0;
2333
2334         if (!client->ops->reset_notify)
2335                 return -EOPNOTSUPP;
2336
2337         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2338                 struct hnae3_handle *handle = &hdev->vport[i].roce;
2339
2340                 ret = client->ops->reset_notify(handle, type);
2341                 if (ret) {
2342                         dev_err(&hdev->pdev->dev,
2343                                 "notify roce client failed %d(%d)",
2344                                 type, ret);
2345                         return ret;
2346                 }
2347         }
2348
2349         return ret;
2350 }
2351
2352 static int hclge_reset_wait(struct hclge_dev *hdev)
2353 {
2354 #define HCLGE_RESET_WATI_MS     100
2355 #define HCLGE_RESET_WAIT_CNT    5
2356         u32 val, reg, reg_bit;
2357         u32 cnt = 0;
2358
2359         switch (hdev->reset_type) {
2360         case HNAE3_GLOBAL_RESET:
2361                 reg = HCLGE_GLOBAL_RESET_REG;
2362                 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2363                 break;
2364         case HNAE3_CORE_RESET:
2365                 reg = HCLGE_GLOBAL_RESET_REG;
2366                 reg_bit = HCLGE_CORE_RESET_BIT;
2367                 break;
2368         case HNAE3_FUNC_RESET:
2369                 reg = HCLGE_FUN_RST_ING;
2370                 reg_bit = HCLGE_FUN_RST_ING_B;
2371                 break;
2372         default:
2373                 dev_err(&hdev->pdev->dev,
2374                         "Wait for unsupported reset type: %d\n",
2375                         hdev->reset_type);
2376                 return -EINVAL;
2377         }
2378
2379         val = hclge_read_dev(&hdev->hw, reg);
2380         while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2381                 msleep(HCLGE_RESET_WATI_MS);
2382                 val = hclge_read_dev(&hdev->hw, reg);
2383                 cnt++;
2384         }
2385
2386         if (cnt >= HCLGE_RESET_WAIT_CNT) {
2387                 dev_warn(&hdev->pdev->dev,
2388                          "Wait for reset timeout: %d\n", hdev->reset_type);
2389                 return -EBUSY;
2390         }
2391
2392         return 0;
2393 }
2394
2395 static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset)
2396 {
2397         struct hclge_vf_rst_cmd *req;
2398         struct hclge_desc desc;
2399
2400         req = (struct hclge_vf_rst_cmd *)desc.data;
2401         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false);
2402         req->dest_vfid = func_id;
2403
2404         if (reset)
2405                 req->vf_rst = 0x1;
2406
2407         return hclge_cmd_send(&hdev->hw, &desc, 1);
2408 }
2409
2410 int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
2411 {
2412         int i;
2413
2414         for (i = hdev->num_vmdq_vport + 1; i < hdev->num_alloc_vport; i++) {
2415                 struct hclge_vport *vport = &hdev->vport[i];
2416                 int ret;
2417
2418                 /* Send cmd to set/clear VF's FUNC_RST_ING */
2419                 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset);
2420                 if (ret) {
2421                         dev_err(&hdev->pdev->dev,
2422                                 "set vf(%d) rst failded %d!\n",
2423                                 vport->vport_id, ret);
2424                         return ret;
2425                 }
2426
2427                 if (!reset)
2428                         continue;
2429
2430                 /* Inform VF to process the reset.
2431                  * hclge_inform_reset_assert_to_vf may fail if VF
2432                  * driver is not loaded.
2433                  */
2434                 ret = hclge_inform_reset_assert_to_vf(vport);
2435                 if (ret)
2436                         dev_warn(&hdev->pdev->dev,
2437                                  "inform reset to vf(%d) failded %d!\n",
2438                                  vport->vport_id, ret);
2439         }
2440
2441         return 0;
2442 }
2443
2444 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2445 {
2446         struct hclge_desc desc;
2447         struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2448         int ret;
2449
2450         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2451         hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2452         req->fun_reset_vfid = func_id;
2453
2454         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2455         if (ret)
2456                 dev_err(&hdev->pdev->dev,
2457                         "send function reset cmd fail, status =%d\n", ret);
2458
2459         return ret;
2460 }
2461
2462 static void hclge_do_reset(struct hclge_dev *hdev)
2463 {
2464         struct pci_dev *pdev = hdev->pdev;
2465         u32 val;
2466
2467         switch (hdev->reset_type) {
2468         case HNAE3_GLOBAL_RESET:
2469                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2470                 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2471                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2472                 dev_info(&pdev->dev, "Global Reset requested\n");
2473                 break;
2474         case HNAE3_CORE_RESET:
2475                 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2476                 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2477                 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2478                 dev_info(&pdev->dev, "Core Reset requested\n");
2479                 break;
2480         case HNAE3_FUNC_RESET:
2481                 dev_info(&pdev->dev, "PF Reset requested\n");
2482                 /* schedule again to check later */
2483                 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2484                 hclge_reset_task_schedule(hdev);
2485                 break;
2486         default:
2487                 dev_warn(&pdev->dev,
2488                          "Unsupported reset type: %d\n", hdev->reset_type);
2489                 break;
2490         }
2491 }
2492
2493 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2494                                                    unsigned long *addr)
2495 {
2496         enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2497
2498         /* return the highest priority reset level amongst all */
2499         if (test_bit(HNAE3_IMP_RESET, addr)) {
2500                 rst_level = HNAE3_IMP_RESET;
2501                 clear_bit(HNAE3_IMP_RESET, addr);
2502                 clear_bit(HNAE3_GLOBAL_RESET, addr);
2503                 clear_bit(HNAE3_CORE_RESET, addr);
2504                 clear_bit(HNAE3_FUNC_RESET, addr);
2505         } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) {
2506                 rst_level = HNAE3_GLOBAL_RESET;
2507                 clear_bit(HNAE3_GLOBAL_RESET, addr);
2508                 clear_bit(HNAE3_CORE_RESET, addr);
2509                 clear_bit(HNAE3_FUNC_RESET, addr);
2510         } else if (test_bit(HNAE3_CORE_RESET, addr)) {
2511                 rst_level = HNAE3_CORE_RESET;
2512                 clear_bit(HNAE3_CORE_RESET, addr);
2513                 clear_bit(HNAE3_FUNC_RESET, addr);
2514         } else if (test_bit(HNAE3_FUNC_RESET, addr)) {
2515                 rst_level = HNAE3_FUNC_RESET;
2516                 clear_bit(HNAE3_FUNC_RESET, addr);
2517         }
2518
2519         return rst_level;
2520 }
2521
2522 static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2523 {
2524         u32 clearval = 0;
2525
2526         switch (hdev->reset_type) {
2527         case HNAE3_IMP_RESET:
2528                 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2529                 break;
2530         case HNAE3_GLOBAL_RESET:
2531                 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2532                 break;
2533         case HNAE3_CORE_RESET:
2534                 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2535                 break;
2536         default:
2537                 break;
2538         }
2539
2540         if (!clearval)
2541                 return;
2542
2543         hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2544         hclge_enable_vector(&hdev->misc_vector, true);
2545 }
2546
2547 static int hclge_reset_prepare_down(struct hclge_dev *hdev)
2548 {
2549         int ret = 0;
2550
2551         switch (hdev->reset_type) {
2552         case HNAE3_FUNC_RESET:
2553                 ret = hclge_set_all_vf_rst(hdev, true);
2554                 break;
2555         default:
2556                 break;
2557         }
2558
2559         return ret;
2560 }
2561
2562 static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
2563 {
2564         int ret = 0;
2565
2566         switch (hdev->reset_type) {
2567         case HNAE3_FUNC_RESET:
2568                 /* There is no mechanism for PF to know if VF has stopped IO
2569                  * for now, just wait 100 ms for VF to stop IO
2570                  */
2571                 msleep(100);
2572                 ret = hclge_func_reset_cmd(hdev, 0);
2573                 if (ret) {
2574                         dev_err(&hdev->pdev->dev,
2575                                 "asserting function reset fail %d!\n", ret);
2576                         return ret;
2577                 }
2578
2579                 /* After performaning pf reset, it is not necessary to do the
2580                  * mailbox handling or send any command to firmware, because
2581                  * any mailbox handling or command to firmware is only valid
2582                  * after hclge_cmd_init is called.
2583                  */
2584                 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2585                 break;
2586         default:
2587                 break;
2588         }
2589
2590         dev_info(&hdev->pdev->dev, "prepare wait ok\n");
2591
2592         return ret;
2593 }
2594
2595 static bool hclge_reset_err_handle(struct hclge_dev *hdev, bool is_timeout)
2596 {
2597 #define MAX_RESET_FAIL_CNT 5
2598 #define RESET_UPGRADE_DELAY_SEC 10
2599
2600         if (hdev->reset_pending) {
2601                 dev_info(&hdev->pdev->dev, "Reset pending %lu\n",
2602                          hdev->reset_pending);
2603                 return true;
2604         } else if ((hdev->reset_type != HNAE3_IMP_RESET) &&
2605                    (hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) &
2606                     BIT(HCLGE_IMP_RESET_BIT))) {
2607                 dev_info(&hdev->pdev->dev,
2608                          "reset failed because IMP Reset is pending\n");
2609                 hclge_clear_reset_cause(hdev);
2610                 return false;
2611         } else if (hdev->reset_fail_cnt < MAX_RESET_FAIL_CNT) {
2612                 hdev->reset_fail_cnt++;
2613                 if (is_timeout) {
2614                         set_bit(hdev->reset_type, &hdev->reset_pending);
2615                         dev_info(&hdev->pdev->dev,
2616                                  "re-schedule to wait for hw reset done\n");
2617                         return true;
2618                 }
2619
2620                 dev_info(&hdev->pdev->dev, "Upgrade reset level\n");
2621                 hclge_clear_reset_cause(hdev);
2622                 mod_timer(&hdev->reset_timer,
2623                           jiffies + RESET_UPGRADE_DELAY_SEC * HZ);
2624
2625                 return false;
2626         }
2627
2628         hclge_clear_reset_cause(hdev);
2629         dev_err(&hdev->pdev->dev, "Reset fail!\n");
2630         return false;
2631 }
2632
2633 static int hclge_reset_prepare_up(struct hclge_dev *hdev)
2634 {
2635         int ret = 0;
2636
2637         switch (hdev->reset_type) {
2638         case HNAE3_FUNC_RESET:
2639                 ret = hclge_set_all_vf_rst(hdev, false);
2640                 break;
2641         default:
2642                 break;
2643         }
2644
2645         return ret;
2646 }
2647
2648 static void hclge_reset(struct hclge_dev *hdev)
2649 {
2650         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
2651         bool is_timeout = false;
2652         int ret;
2653
2654         /* Initialize ae_dev reset status as well, in case enet layer wants to
2655          * know if device is undergoing reset
2656          */
2657         ae_dev->reset_type = hdev->reset_type;
2658         hdev->reset_count++;
2659         hdev->last_reset_time = jiffies;
2660         /* perform reset of the stack & ae device for a client */
2661         ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
2662         if (ret)
2663                 goto err_reset;
2664
2665         ret = hclge_reset_prepare_down(hdev);
2666         if (ret)
2667                 goto err_reset;
2668
2669         rtnl_lock();
2670         ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2671         if (ret)
2672                 goto err_reset_lock;
2673
2674         rtnl_unlock();
2675
2676         ret = hclge_reset_prepare_wait(hdev);
2677         if (ret)
2678                 goto err_reset;
2679
2680         if (hclge_reset_wait(hdev)) {
2681                 is_timeout = true;
2682                 goto err_reset;
2683         }
2684
2685         ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
2686         if (ret)
2687                 goto err_reset;
2688
2689         rtnl_lock();
2690         ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2691         if (ret)
2692                 goto err_reset_lock;
2693
2694         ret = hclge_reset_ae_dev(hdev->ae_dev);
2695         if (ret)
2696                 goto err_reset_lock;
2697
2698         ret = hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2699         if (ret)
2700                 goto err_reset_lock;
2701
2702         hclge_clear_reset_cause(hdev);
2703
2704         ret = hclge_reset_prepare_up(hdev);
2705         if (ret)
2706                 goto err_reset_lock;
2707
2708         ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2709         if (ret)
2710                 goto err_reset_lock;
2711
2712         rtnl_unlock();
2713
2714         ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
2715         if (ret)
2716                 goto err_reset;
2717
2718         ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT);
2719         if (ret)
2720                 goto err_reset;
2721
2722         return;
2723
2724 err_reset_lock:
2725         rtnl_unlock();
2726 err_reset:
2727         if (hclge_reset_err_handle(hdev, is_timeout))
2728                 hclge_reset_task_schedule(hdev);
2729 }
2730
2731 static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
2732 {
2733         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2734         struct hclge_dev *hdev = ae_dev->priv;
2735
2736         /* We might end up getting called broadly because of 2 below cases:
2737          * 1. Recoverable error was conveyed through APEI and only way to bring
2738          *    normalcy is to reset.
2739          * 2. A new reset request from the stack due to timeout
2740          *
2741          * For the first case,error event might not have ae handle available.
2742          * check if this is a new reset request and we are not here just because
2743          * last reset attempt did not succeed and watchdog hit us again. We will
2744          * know this if last reset request did not occur very recently (watchdog
2745          * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2746          * In case of new request we reset the "reset level" to PF reset.
2747          * And if it is a repeat reset request of the most recent one then we
2748          * want to make sure we throttle the reset request. Therefore, we will
2749          * not allow it again before 3*HZ times.
2750          */
2751         if (!handle)
2752                 handle = &hdev->vport[0].nic;
2753
2754         if (time_before(jiffies, (hdev->last_reset_time + 3 * HZ)))
2755                 return;
2756         else if (hdev->default_reset_request)
2757                 hdev->reset_level =
2758                         hclge_get_reset_level(hdev,
2759                                               &hdev->default_reset_request);
2760         else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ)))
2761                 hdev->reset_level = HNAE3_FUNC_RESET;
2762
2763         dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2764                  hdev->reset_level);
2765
2766         /* request reset & schedule reset task */
2767         set_bit(hdev->reset_level, &hdev->reset_request);
2768         hclge_reset_task_schedule(hdev);
2769
2770         if (hdev->reset_level < HNAE3_GLOBAL_RESET)
2771                 hdev->reset_level++;
2772 }
2773
2774 static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
2775                                         enum hnae3_reset_type rst_type)
2776 {
2777         struct hclge_dev *hdev = ae_dev->priv;
2778
2779         set_bit(rst_type, &hdev->default_reset_request);
2780 }
2781
2782 static void hclge_reset_timer(struct timer_list *t)
2783 {
2784         struct hclge_dev *hdev = from_timer(hdev, t, reset_timer);
2785
2786         dev_info(&hdev->pdev->dev,
2787                  "triggering global reset in reset timer\n");
2788         set_bit(HNAE3_GLOBAL_RESET, &hdev->default_reset_request);
2789         hclge_reset_event(hdev->pdev, NULL);
2790 }
2791
2792 static void hclge_reset_subtask(struct hclge_dev *hdev)
2793 {
2794         /* check if there is any ongoing reset in the hardware. This status can
2795          * be checked from reset_pending. If there is then, we need to wait for
2796          * hardware to complete reset.
2797          *    a. If we are able to figure out in reasonable time that hardware
2798          *       has fully resetted then, we can proceed with driver, client
2799          *       reset.
2800          *    b. else, we can come back later to check this status so re-sched
2801          *       now.
2802          */
2803         hdev->last_reset_time = jiffies;
2804         hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2805         if (hdev->reset_type != HNAE3_NONE_RESET)
2806                 hclge_reset(hdev);
2807
2808         /* check if we got any *new* reset requests to be honored */
2809         hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2810         if (hdev->reset_type != HNAE3_NONE_RESET)
2811                 hclge_do_reset(hdev);
2812
2813         hdev->reset_type = HNAE3_NONE_RESET;
2814 }
2815
2816 static void hclge_reset_service_task(struct work_struct *work)
2817 {
2818         struct hclge_dev *hdev =
2819                 container_of(work, struct hclge_dev, rst_service_task);
2820
2821         if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2822                 return;
2823
2824         clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2825
2826         hclge_reset_subtask(hdev);
2827
2828         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
2829 }
2830
2831 static void hclge_mailbox_service_task(struct work_struct *work)
2832 {
2833         struct hclge_dev *hdev =
2834                 container_of(work, struct hclge_dev, mbx_service_task);
2835
2836         if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2837                 return;
2838
2839         clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2840
2841         hclge_mbx_handler(hdev);
2842
2843         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2844 }
2845
2846 static void hclge_service_task(struct work_struct *work)
2847 {
2848         struct hclge_dev *hdev =
2849                 container_of(work, struct hclge_dev, service_task);
2850
2851         if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2852                 hclge_update_stats_for_all(hdev);
2853                 hdev->hw_stats.stats_timer = 0;
2854         }
2855
2856         hclge_update_speed_duplex(hdev);
2857         hclge_update_link_status(hdev);
2858         hclge_service_complete(hdev);
2859 }
2860
2861 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2862 {
2863         /* VF handle has no client */
2864         if (!handle->client)
2865                 return container_of(handle, struct hclge_vport, nic);
2866         else if (handle->client->type == HNAE3_CLIENT_ROCE)
2867                 return container_of(handle, struct hclge_vport, roce);
2868         else
2869                 return container_of(handle, struct hclge_vport, nic);
2870 }
2871
2872 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2873                             struct hnae3_vector_info *vector_info)
2874 {
2875         struct hclge_vport *vport = hclge_get_vport(handle);
2876         struct hnae3_vector_info *vector = vector_info;
2877         struct hclge_dev *hdev = vport->back;
2878         int alloc = 0;
2879         int i, j;
2880
2881         vector_num = min(hdev->num_msi_left, vector_num);
2882
2883         for (j = 0; j < vector_num; j++) {
2884                 for (i = 1; i < hdev->num_msi; i++) {
2885                         if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2886                                 vector->vector = pci_irq_vector(hdev->pdev, i);
2887                                 vector->io_addr = hdev->hw.io_base +
2888                                         HCLGE_VECTOR_REG_BASE +
2889                                         (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2890                                         vport->vport_id *
2891                                         HCLGE_VECTOR_VF_OFFSET;
2892                                 hdev->vector_status[i] = vport->vport_id;
2893                                 hdev->vector_irq[i] = vector->vector;
2894
2895                                 vector++;
2896                                 alloc++;
2897
2898                                 break;
2899                         }
2900                 }
2901         }
2902         hdev->num_msi_left -= alloc;
2903         hdev->num_msi_used += alloc;
2904
2905         return alloc;
2906 }
2907
2908 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2909 {
2910         int i;
2911
2912         for (i = 0; i < hdev->num_msi; i++)
2913                 if (vector == hdev->vector_irq[i])
2914                         return i;
2915
2916         return -EINVAL;
2917 }
2918
2919 static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2920 {
2921         struct hclge_vport *vport = hclge_get_vport(handle);
2922         struct hclge_dev *hdev = vport->back;
2923         int vector_id;
2924
2925         vector_id = hclge_get_vector_index(hdev, vector);
2926         if (vector_id < 0) {
2927                 dev_err(&hdev->pdev->dev,
2928                         "Get vector index fail. vector_id =%d\n", vector_id);
2929                 return vector_id;
2930         }
2931
2932         hclge_free_vector(hdev, vector_id);
2933
2934         return 0;
2935 }
2936
2937 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2938 {
2939         return HCLGE_RSS_KEY_SIZE;
2940 }
2941
2942 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2943 {
2944         return HCLGE_RSS_IND_TBL_SIZE;
2945 }
2946
2947 static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2948                                   const u8 hfunc, const u8 *key)
2949 {
2950         struct hclge_rss_config_cmd *req;
2951         struct hclge_desc desc;
2952         int key_offset;
2953         int key_size;
2954         int ret;
2955
2956         req = (struct hclge_rss_config_cmd *)desc.data;
2957
2958         for (key_offset = 0; key_offset < 3; key_offset++) {
2959                 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2960                                            false);
2961
2962                 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2963                 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2964
2965                 if (key_offset == 2)
2966                         key_size =
2967                         HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2968                 else
2969                         key_size = HCLGE_RSS_HASH_KEY_NUM;
2970
2971                 memcpy(req->hash_key,
2972                        key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2973
2974                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2975                 if (ret) {
2976                         dev_err(&hdev->pdev->dev,
2977                                 "Configure RSS config fail, status = %d\n",
2978                                 ret);
2979                         return ret;
2980                 }
2981         }
2982         return 0;
2983 }
2984
2985 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
2986 {
2987         struct hclge_rss_indirection_table_cmd *req;
2988         struct hclge_desc desc;
2989         int i, j;
2990         int ret;
2991
2992         req = (struct hclge_rss_indirection_table_cmd *)desc.data;
2993
2994         for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2995                 hclge_cmd_setup_basic_desc
2996                         (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2997
2998                 req->start_table_index =
2999                         cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3000                 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
3001
3002                 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3003                         req->rss_result[j] =
3004                                 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3005
3006                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3007                 if (ret) {
3008                         dev_err(&hdev->pdev->dev,
3009                                 "Configure rss indir table fail,status = %d\n",
3010                                 ret);
3011                         return ret;
3012                 }
3013         }
3014         return 0;
3015 }
3016
3017 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3018                                  u16 *tc_size, u16 *tc_offset)
3019 {
3020         struct hclge_rss_tc_mode_cmd *req;
3021         struct hclge_desc desc;
3022         int ret;
3023         int i;
3024
3025         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
3026         req = (struct hclge_rss_tc_mode_cmd *)desc.data;
3027
3028         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3029                 u16 mode = 0;
3030
3031                 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3032                 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3033                                 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3034                 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3035                                 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
3036
3037                 req->rss_tc_mode[i] = cpu_to_le16(mode);
3038         }
3039
3040         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3041         if (ret)
3042                 dev_err(&hdev->pdev->dev,
3043                         "Configure rss tc mode fail, status = %d\n", ret);
3044
3045         return ret;
3046 }
3047
3048 static void hclge_get_rss_type(struct hclge_vport *vport)
3049 {
3050         if (vport->rss_tuple_sets.ipv4_tcp_en ||
3051             vport->rss_tuple_sets.ipv4_udp_en ||
3052             vport->rss_tuple_sets.ipv4_sctp_en ||
3053             vport->rss_tuple_sets.ipv6_tcp_en ||
3054             vport->rss_tuple_sets.ipv6_udp_en ||
3055             vport->rss_tuple_sets.ipv6_sctp_en)
3056                 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L4;
3057         else if (vport->rss_tuple_sets.ipv4_fragment_en ||
3058                  vport->rss_tuple_sets.ipv6_fragment_en)
3059                 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L3;
3060         else
3061                 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_NONE;
3062 }
3063
3064 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3065 {
3066         struct hclge_rss_input_tuple_cmd *req;
3067         struct hclge_desc desc;
3068         int ret;
3069
3070         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3071
3072         req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3073
3074         /* Get the tuple cfg from pf */
3075         req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3076         req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3077         req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3078         req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3079         req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3080         req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3081         req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3082         req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
3083         hclge_get_rss_type(&hdev->vport[0]);
3084         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3085         if (ret)
3086                 dev_err(&hdev->pdev->dev,
3087                         "Configure rss input fail, status = %d\n", ret);
3088         return ret;
3089 }
3090
3091 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3092                          u8 *key, u8 *hfunc)
3093 {
3094         struct hclge_vport *vport = hclge_get_vport(handle);
3095         int i;
3096
3097         /* Get hash algorithm */
3098         if (hfunc) {
3099                 switch (vport->rss_algo) {
3100                 case HCLGE_RSS_HASH_ALGO_TOEPLITZ:
3101                         *hfunc = ETH_RSS_HASH_TOP;
3102                         break;
3103                 case HCLGE_RSS_HASH_ALGO_SIMPLE:
3104                         *hfunc = ETH_RSS_HASH_XOR;
3105                         break;
3106                 default:
3107                         *hfunc = ETH_RSS_HASH_UNKNOWN;
3108                         break;
3109                 }
3110         }
3111
3112         /* Get the RSS Key required by the user */
3113         if (key)
3114                 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3115
3116         /* Get indirect table */
3117         if (indir)
3118                 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3119                         indir[i] =  vport->rss_indirection_tbl[i];
3120
3121         return 0;
3122 }
3123
3124 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3125                          const  u8 *key, const  u8 hfunc)
3126 {
3127         struct hclge_vport *vport = hclge_get_vport(handle);
3128         struct hclge_dev *hdev = vport->back;
3129         u8 hash_algo;
3130         int ret, i;
3131
3132         /* Set the RSS Hash Key if specififed by the user */
3133         if (key) {
3134                 switch (hfunc) {
3135                 case ETH_RSS_HASH_TOP:
3136                         hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3137                         break;
3138                 case ETH_RSS_HASH_XOR:
3139                         hash_algo = HCLGE_RSS_HASH_ALGO_SIMPLE;
3140                         break;
3141                 case ETH_RSS_HASH_NO_CHANGE:
3142                         hash_algo = vport->rss_algo;
3143                         break;
3144                 default:
3145                         return -EINVAL;
3146                 }
3147
3148                 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3149                 if (ret)
3150                         return ret;
3151
3152                 /* Update the shadow RSS key with user specified qids */
3153                 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3154                 vport->rss_algo = hash_algo;
3155         }
3156
3157         /* Update the shadow RSS table with user specified qids */
3158         for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3159                 vport->rss_indirection_tbl[i] = indir[i];
3160
3161         /* Update the hardware */
3162         return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
3163 }
3164
3165 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3166 {
3167         u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3168
3169         if (nfc->data & RXH_L4_B_2_3)
3170                 hash_sets |= HCLGE_D_PORT_BIT;
3171         else
3172                 hash_sets &= ~HCLGE_D_PORT_BIT;
3173
3174         if (nfc->data & RXH_IP_SRC)
3175                 hash_sets |= HCLGE_S_IP_BIT;
3176         else
3177                 hash_sets &= ~HCLGE_S_IP_BIT;
3178
3179         if (nfc->data & RXH_IP_DST)
3180                 hash_sets |= HCLGE_D_IP_BIT;
3181         else
3182                 hash_sets &= ~HCLGE_D_IP_BIT;
3183
3184         if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3185                 hash_sets |= HCLGE_V_TAG_BIT;
3186
3187         return hash_sets;
3188 }
3189
3190 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3191                                struct ethtool_rxnfc *nfc)
3192 {
3193         struct hclge_vport *vport = hclge_get_vport(handle);
3194         struct hclge_dev *hdev = vport->back;
3195         struct hclge_rss_input_tuple_cmd *req;
3196         struct hclge_desc desc;
3197         u8 tuple_sets;
3198         int ret;
3199
3200         if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3201                           RXH_L4_B_0_1 | RXH_L4_B_2_3))
3202                 return -EINVAL;
3203
3204         req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3205         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3206
3207         req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3208         req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3209         req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3210         req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3211         req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3212         req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3213         req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3214         req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
3215
3216         tuple_sets = hclge_get_rss_hash_bits(nfc);
3217         switch (nfc->flow_type) {
3218         case TCP_V4_FLOW:
3219                 req->ipv4_tcp_en = tuple_sets;
3220                 break;
3221         case TCP_V6_FLOW:
3222                 req->ipv6_tcp_en = tuple_sets;
3223                 break;
3224         case UDP_V4_FLOW:
3225                 req->ipv4_udp_en = tuple_sets;
3226                 break;
3227         case UDP_V6_FLOW:
3228                 req->ipv6_udp_en = tuple_sets;
3229                 break;
3230         case SCTP_V4_FLOW:
3231                 req->ipv4_sctp_en = tuple_sets;
3232                 break;
3233         case SCTP_V6_FLOW:
3234                 if ((nfc->data & RXH_L4_B_0_1) ||
3235                     (nfc->data & RXH_L4_B_2_3))
3236                         return -EINVAL;
3237
3238                 req->ipv6_sctp_en = tuple_sets;
3239                 break;
3240         case IPV4_FLOW:
3241                 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3242                 break;
3243         case IPV6_FLOW:
3244                 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3245                 break;
3246         default:
3247                 return -EINVAL;
3248         }
3249
3250         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3251         if (ret) {
3252                 dev_err(&hdev->pdev->dev,
3253                         "Set rss tuple fail, status = %d\n", ret);
3254                 return ret;
3255         }
3256
3257         vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3258         vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3259         vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3260         vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3261         vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3262         vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3263         vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3264         vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3265         hclge_get_rss_type(vport);
3266         return 0;
3267 }
3268
3269 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3270                                struct ethtool_rxnfc *nfc)
3271 {
3272         struct hclge_vport *vport = hclge_get_vport(handle);
3273         u8 tuple_sets;
3274
3275         nfc->data = 0;
3276
3277         switch (nfc->flow_type) {
3278         case TCP_V4_FLOW:
3279                 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
3280                 break;
3281         case UDP_V4_FLOW:
3282                 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
3283                 break;
3284         case TCP_V6_FLOW:
3285                 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
3286                 break;
3287         case UDP_V6_FLOW:
3288                 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
3289                 break;
3290         case SCTP_V4_FLOW:
3291                 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
3292                 break;
3293         case SCTP_V6_FLOW:
3294                 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
3295                 break;
3296         case IPV4_FLOW:
3297         case IPV6_FLOW:
3298                 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3299                 break;
3300         default:
3301                 return -EINVAL;
3302         }
3303
3304         if (!tuple_sets)
3305                 return 0;
3306
3307         if (tuple_sets & HCLGE_D_PORT_BIT)
3308                 nfc->data |= RXH_L4_B_2_3;
3309         if (tuple_sets & HCLGE_S_PORT_BIT)
3310                 nfc->data |= RXH_L4_B_0_1;
3311         if (tuple_sets & HCLGE_D_IP_BIT)
3312                 nfc->data |= RXH_IP_DST;
3313         if (tuple_sets & HCLGE_S_IP_BIT)
3314                 nfc->data |= RXH_IP_SRC;
3315
3316         return 0;
3317 }
3318
3319 static int hclge_get_tc_size(struct hnae3_handle *handle)
3320 {
3321         struct hclge_vport *vport = hclge_get_vport(handle);
3322         struct hclge_dev *hdev = vport->back;
3323
3324         return hdev->rss_size_max;
3325 }
3326
3327 int hclge_rss_init_hw(struct hclge_dev *hdev)
3328 {
3329         struct hclge_vport *vport = hdev->vport;
3330         u8 *rss_indir = vport[0].rss_indirection_tbl;
3331         u16 rss_size = vport[0].alloc_rss_size;
3332         u8 *key = vport[0].rss_hash_key;
3333         u8 hfunc = vport[0].rss_algo;
3334         u16 tc_offset[HCLGE_MAX_TC_NUM];
3335         u16 tc_valid[HCLGE_MAX_TC_NUM];
3336         u16 tc_size[HCLGE_MAX_TC_NUM];
3337         u16 roundup_size;
3338         int i, ret;
3339
3340         ret = hclge_set_rss_indir_table(hdev, rss_indir);
3341         if (ret)
3342                 return ret;
3343
3344         ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3345         if (ret)
3346                 return ret;
3347
3348         ret = hclge_set_rss_input_tuple(hdev);
3349         if (ret)
3350                 return ret;
3351
3352         /* Each TC have the same queue size, and tc_size set to hardware is
3353          * the log2 of roundup power of two of rss_size, the acutal queue
3354          * size is limited by indirection table.
3355          */
3356         if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3357                 dev_err(&hdev->pdev->dev,
3358                         "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3359                         rss_size);
3360                 return -EINVAL;
3361         }
3362
3363         roundup_size = roundup_pow_of_two(rss_size);
3364         roundup_size = ilog2(roundup_size);
3365
3366         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3367                 tc_valid[i] = 0;
3368
3369                 if (!(hdev->hw_tc_map & BIT(i)))
3370                         continue;
3371
3372                 tc_valid[i] = 1;
3373                 tc_size[i] = roundup_size;
3374                 tc_offset[i] = rss_size * i;
3375         }
3376
3377         return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3378 }
3379
3380 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3381 {
3382         struct hclge_vport *vport = hdev->vport;
3383         int i, j;
3384
3385         for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3386                 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3387                         vport[j].rss_indirection_tbl[i] =
3388                                 i % vport[j].alloc_rss_size;
3389         }
3390 }
3391
3392 static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3393 {
3394         struct hclge_vport *vport = hdev->vport;
3395         int i;
3396
3397         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3398                 vport[i].rss_tuple_sets.ipv4_tcp_en =
3399                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3400                 vport[i].rss_tuple_sets.ipv4_udp_en =
3401                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3402                 vport[i].rss_tuple_sets.ipv4_sctp_en =
3403                         HCLGE_RSS_INPUT_TUPLE_SCTP;
3404                 vport[i].rss_tuple_sets.ipv4_fragment_en =
3405                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3406                 vport[i].rss_tuple_sets.ipv6_tcp_en =
3407                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3408                 vport[i].rss_tuple_sets.ipv6_udp_en =
3409                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3410                 vport[i].rss_tuple_sets.ipv6_sctp_en =
3411                         HCLGE_RSS_INPUT_TUPLE_SCTP;
3412                 vport[i].rss_tuple_sets.ipv6_fragment_en =
3413                         HCLGE_RSS_INPUT_TUPLE_OTHER;
3414
3415                 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3416
3417                 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
3418         }
3419
3420         hclge_rss_indir_init_cfg(hdev);
3421 }
3422
3423 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3424                                 int vector_id, bool en,
3425                                 struct hnae3_ring_chain_node *ring_chain)
3426 {
3427         struct hclge_dev *hdev = vport->back;
3428         struct hnae3_ring_chain_node *node;
3429         struct hclge_desc desc;
3430         struct hclge_ctrl_vector_chain_cmd *req
3431                 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3432         enum hclge_cmd_status status;
3433         enum hclge_opcode_type op;
3434         u16 tqp_type_and_id;
3435         int i;
3436
3437         op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3438         hclge_cmd_setup_basic_desc(&desc, op, false);
3439         req->int_vector_id = vector_id;
3440
3441         i = 0;
3442         for (node = ring_chain; node; node = node->next) {
3443                 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3444                 hnae3_set_field(tqp_type_and_id,  HCLGE_INT_TYPE_M,
3445                                 HCLGE_INT_TYPE_S,
3446                                 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3447                 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3448                                 HCLGE_TQP_ID_S, node->tqp_index);
3449                 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3450                                 HCLGE_INT_GL_IDX_S,
3451                                 hnae3_get_field(node->int_gl_idx,
3452                                                 HNAE3_RING_GL_IDX_M,
3453                                                 HNAE3_RING_GL_IDX_S));
3454                 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
3455                 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3456                         req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3457                         req->vfid = vport->vport_id;
3458
3459                         status = hclge_cmd_send(&hdev->hw, &desc, 1);
3460                         if (status) {
3461                                 dev_err(&hdev->pdev->dev,
3462                                         "Map TQP fail, status is %d.\n",
3463                                         status);
3464                                 return -EIO;
3465                         }
3466                         i = 0;
3467
3468                         hclge_cmd_setup_basic_desc(&desc,
3469                                                    op,
3470                                                    false);
3471                         req->int_vector_id = vector_id;
3472                 }
3473         }
3474
3475         if (i > 0) {
3476                 req->int_cause_num = i;
3477                 req->vfid = vport->vport_id;
3478                 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3479                 if (status) {
3480                         dev_err(&hdev->pdev->dev,
3481                                 "Map TQP fail, status is %d.\n", status);
3482                         return -EIO;
3483                 }
3484         }
3485
3486         return 0;
3487 }
3488
3489 static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3490                                     int vector,
3491                                     struct hnae3_ring_chain_node *ring_chain)
3492 {
3493         struct hclge_vport *vport = hclge_get_vport(handle);
3494         struct hclge_dev *hdev = vport->back;
3495         int vector_id;
3496
3497         vector_id = hclge_get_vector_index(hdev, vector);
3498         if (vector_id < 0) {
3499                 dev_err(&hdev->pdev->dev,
3500                         "Get vector index fail. vector_id =%d\n", vector_id);
3501                 return vector_id;
3502         }
3503
3504         return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
3505 }
3506
3507 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3508                                        int vector,
3509                                        struct hnae3_ring_chain_node *ring_chain)
3510 {
3511         struct hclge_vport *vport = hclge_get_vport(handle);
3512         struct hclge_dev *hdev = vport->back;
3513         int vector_id, ret;
3514
3515         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3516                 return 0;
3517
3518         vector_id = hclge_get_vector_index(hdev, vector);
3519         if (vector_id < 0) {
3520                 dev_err(&handle->pdev->dev,
3521                         "Get vector index fail. ret =%d\n", vector_id);
3522                 return vector_id;
3523         }
3524
3525         ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
3526         if (ret)
3527                 dev_err(&handle->pdev->dev,
3528                         "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3529                         vector_id,
3530                         ret);
3531
3532         return ret;
3533 }
3534
3535 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3536                                struct hclge_promisc_param *param)
3537 {
3538         struct hclge_promisc_cfg_cmd *req;
3539         struct hclge_desc desc;
3540         int ret;
3541
3542         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3543
3544         req = (struct hclge_promisc_cfg_cmd *)desc.data;
3545         req->vf_id = param->vf_id;
3546
3547         /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3548          * pdev revision(0x20), new revision support them. The
3549          * value of this two fields will not return error when driver
3550          * send command to fireware in revision(0x20).
3551          */
3552         req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3553                 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
3554
3555         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3556         if (ret)
3557                 dev_err(&hdev->pdev->dev,
3558                         "Set promisc mode fail, status is %d.\n", ret);
3559
3560         return ret;
3561 }
3562
3563 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3564                               bool en_mc, bool en_bc, int vport_id)
3565 {
3566         if (!param)
3567                 return;
3568
3569         memset(param, 0, sizeof(struct hclge_promisc_param));
3570         if (en_uc)
3571                 param->enable = HCLGE_PROMISC_EN_UC;
3572         if (en_mc)
3573                 param->enable |= HCLGE_PROMISC_EN_MC;
3574         if (en_bc)
3575                 param->enable |= HCLGE_PROMISC_EN_BC;
3576         param->vf_id = vport_id;
3577 }
3578
3579 static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3580                                   bool en_mc_pmc)
3581 {
3582         struct hclge_vport *vport = hclge_get_vport(handle);
3583         struct hclge_dev *hdev = vport->back;
3584         struct hclge_promisc_param param;
3585
3586         hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3587                                  vport->vport_id);
3588         return hclge_cmd_set_promisc_mode(hdev, &param);
3589 }
3590
3591 static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
3592 {
3593         struct hclge_get_fd_mode_cmd *req;
3594         struct hclge_desc desc;
3595         int ret;
3596
3597         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true);
3598
3599         req = (struct hclge_get_fd_mode_cmd *)desc.data;
3600
3601         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3602         if (ret) {
3603                 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret);
3604                 return ret;
3605         }
3606
3607         *fd_mode = req->mode;
3608
3609         return ret;
3610 }
3611
3612 static int hclge_get_fd_allocation(struct hclge_dev *hdev,
3613                                    u32 *stage1_entry_num,
3614                                    u32 *stage2_entry_num,
3615                                    u16 *stage1_counter_num,
3616                                    u16 *stage2_counter_num)
3617 {
3618         struct hclge_get_fd_allocation_cmd *req;
3619         struct hclge_desc desc;
3620         int ret;
3621
3622         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true);
3623
3624         req = (struct hclge_get_fd_allocation_cmd *)desc.data;
3625
3626         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3627         if (ret) {
3628                 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n",
3629                         ret);
3630                 return ret;
3631         }
3632
3633         *stage1_entry_num = le32_to_cpu(req->stage1_entry_num);
3634         *stage2_entry_num = le32_to_cpu(req->stage2_entry_num);
3635         *stage1_counter_num = le16_to_cpu(req->stage1_counter_num);
3636         *stage2_counter_num = le16_to_cpu(req->stage2_counter_num);
3637
3638         return ret;
3639 }
3640
3641 static int hclge_set_fd_key_config(struct hclge_dev *hdev, int stage_num)
3642 {
3643         struct hclge_set_fd_key_config_cmd *req;
3644         struct hclge_fd_key_cfg *stage;
3645         struct hclge_desc desc;
3646         int ret;
3647
3648         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false);
3649
3650         req = (struct hclge_set_fd_key_config_cmd *)desc.data;
3651         stage = &hdev->fd_cfg.key_cfg[stage_num];
3652         req->stage = stage_num;
3653         req->key_select = stage->key_sel;
3654         req->inner_sipv6_word_en = stage->inner_sipv6_word_en;
3655         req->inner_dipv6_word_en = stage->inner_dipv6_word_en;
3656         req->outer_sipv6_word_en = stage->outer_sipv6_word_en;
3657         req->outer_dipv6_word_en = stage->outer_dipv6_word_en;
3658         req->tuple_mask = cpu_to_le32(~stage->tuple_active);
3659         req->meta_data_mask = cpu_to_le32(~stage->meta_data_active);
3660
3661         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3662         if (ret)
3663                 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret);
3664
3665         return ret;
3666 }
3667
3668 static int hclge_init_fd_config(struct hclge_dev *hdev)
3669 {
3670 #define LOW_2_WORDS             0x03
3671         struct hclge_fd_key_cfg *key_cfg;
3672         int ret;
3673
3674         if (!hnae3_dev_fd_supported(hdev))
3675                 return 0;
3676
3677         ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode);
3678         if (ret)
3679                 return ret;
3680
3681         switch (hdev->fd_cfg.fd_mode) {
3682         case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1:
3683                 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH;
3684                 break;
3685         case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1:
3686                 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2;
3687                 break;
3688         default:
3689                 dev_err(&hdev->pdev->dev,
3690                         "Unsupported flow director mode %d\n",
3691                         hdev->fd_cfg.fd_mode);
3692                 return -EOPNOTSUPP;
3693         }
3694
3695         hdev->fd_cfg.fd_en = true;
3696         hdev->fd_cfg.proto_support =
3697                 TCP_V4_FLOW | UDP_V4_FLOW | SCTP_V4_FLOW | TCP_V6_FLOW |
3698                 UDP_V6_FLOW | SCTP_V6_FLOW | IPV4_USER_FLOW | IPV6_USER_FLOW;
3699         key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1];
3700         key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE,
3701         key_cfg->inner_sipv6_word_en = LOW_2_WORDS;
3702         key_cfg->inner_dipv6_word_en = LOW_2_WORDS;
3703         key_cfg->outer_sipv6_word_en = 0;
3704         key_cfg->outer_dipv6_word_en = 0;
3705
3706         key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) |
3707                                 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) |
3708                                 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
3709                                 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
3710
3711         /* If use max 400bit key, we can support tuples for ether type */
3712         if (hdev->fd_cfg.max_key_length == MAX_KEY_LENGTH) {
3713                 hdev->fd_cfg.proto_support |= ETHER_FLOW;
3714                 key_cfg->tuple_active |=
3715                                 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
3716         }
3717
3718         /* roce_type is used to filter roce frames
3719          * dst_vport is used to specify the rule
3720          */
3721         key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT);
3722
3723         ret = hclge_get_fd_allocation(hdev,
3724                                       &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
3725                                       &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2],
3726                                       &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1],
3727                                       &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]);
3728         if (ret)
3729                 return ret;
3730
3731         return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
3732 }
3733
3734 static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
3735                                 int loc, u8 *key, bool is_add)
3736 {
3737         struct hclge_fd_tcam_config_1_cmd *req1;
3738         struct hclge_fd_tcam_config_2_cmd *req2;
3739         struct hclge_fd_tcam_config_3_cmd *req3;
3740         struct hclge_desc desc[3];
3741         int ret;
3742
3743         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
3744         desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3745         hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
3746         desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3747         hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
3748
3749         req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
3750         req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
3751         req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
3752
3753         req1->stage = stage;
3754         req1->xy_sel = sel_x ? 1 : 0;
3755         hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0);
3756         req1->index = cpu_to_le32(loc);
3757         req1->entry_vld = sel_x ? is_add : 0;
3758
3759         if (key) {
3760                 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data));
3761                 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)],
3762                        sizeof(req2->tcam_data));
3763                 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) +
3764                        sizeof(req2->tcam_data)], sizeof(req3->tcam_data));
3765         }
3766
3767         ret = hclge_cmd_send(&hdev->hw, desc, 3);
3768         if (ret)
3769                 dev_err(&hdev->pdev->dev,
3770                         "config tcam key fail, ret=%d\n",
3771                         ret);
3772
3773         return ret;
3774 }
3775
3776 static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
3777                               struct hclge_fd_ad_data *action)
3778 {
3779         struct hclge_fd_ad_config_cmd *req;
3780         struct hclge_desc desc;
3781         u64 ad_data = 0;
3782         int ret;
3783
3784         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false);
3785
3786         req = (struct hclge_fd_ad_config_cmd *)desc.data;
3787         req->index = cpu_to_le32(loc);
3788         req->stage = stage;
3789
3790         hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B,
3791                       action->write_rule_id_to_bd);
3792         hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S,
3793                         action->rule_id);
3794         ad_data <<= 32;
3795         hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
3796         hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
3797                       action->forward_to_direct_queue);
3798         hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,
3799                         action->queue_id);
3800         hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
3801         hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
3802                         HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);
3803         hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
3804         hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
3805                         action->counter_id);
3806
3807         req->ad_data = cpu_to_le64(ad_data);
3808         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3809         if (ret)
3810                 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret);
3811
3812         return ret;
3813 }
3814
3815 static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
3816                                    struct hclge_fd_rule *rule)
3817 {
3818         u16 tmp_x_s, tmp_y_s;
3819         u32 tmp_x_l, tmp_y_l;
3820         int i;
3821
3822         if (rule->unused_tuple & tuple_bit)
3823                 return true;
3824
3825         switch (tuple_bit) {
3826         case 0:
3827                 return false;
3828         case BIT(INNER_DST_MAC):
3829                 for (i = 0; i < 6; i++) {
3830                         calc_x(key_x[5 - i], rule->tuples.dst_mac[i],
3831                                rule->tuples_mask.dst_mac[i]);
3832                         calc_y(key_y[5 - i], rule->tuples.dst_mac[i],
3833                                rule->tuples_mask.dst_mac[i]);
3834                 }
3835
3836                 return true;
3837         case BIT(INNER_SRC_MAC):
3838                 for (i = 0; i < 6; i++) {
3839                         calc_x(key_x[5 - i], rule->tuples.src_mac[i],
3840                                rule->tuples.src_mac[i]);
3841                         calc_y(key_y[5 - i], rule->tuples.src_mac[i],
3842                                rule->tuples.src_mac[i]);
3843                 }
3844
3845                 return true;
3846         case BIT(INNER_VLAN_TAG_FST):
3847                 calc_x(tmp_x_s, rule->tuples.vlan_tag1,
3848                        rule->tuples_mask.vlan_tag1);
3849                 calc_y(tmp_y_s, rule->tuples.vlan_tag1,
3850                        rule->tuples_mask.vlan_tag1);
3851                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3852                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3853
3854                 return true;
3855         case BIT(INNER_ETH_TYPE):
3856                 calc_x(tmp_x_s, rule->tuples.ether_proto,
3857                        rule->tuples_mask.ether_proto);
3858                 calc_y(tmp_y_s, rule->tuples.ether_proto,
3859                        rule->tuples_mask.ether_proto);
3860                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3861                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3862
3863                 return true;
3864         case BIT(INNER_IP_TOS):
3865                 calc_x(*key_x, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
3866                 calc_y(*key_y, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
3867
3868                 return true;
3869         case BIT(INNER_IP_PROTO):
3870                 calc_x(*key_x, rule->tuples.ip_proto,
3871                        rule->tuples_mask.ip_proto);
3872                 calc_y(*key_y, rule->tuples.ip_proto,
3873                        rule->tuples_mask.ip_proto);
3874
3875                 return true;
3876         case BIT(INNER_SRC_IP):
3877                 calc_x(tmp_x_l, rule->tuples.src_ip[3],
3878                        rule->tuples_mask.src_ip[3]);
3879                 calc_y(tmp_y_l, rule->tuples.src_ip[3],
3880                        rule->tuples_mask.src_ip[3]);
3881                 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
3882                 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
3883
3884                 return true;
3885         case BIT(INNER_DST_IP):
3886                 calc_x(tmp_x_l, rule->tuples.dst_ip[3],
3887                        rule->tuples_mask.dst_ip[3]);
3888                 calc_y(tmp_y_l, rule->tuples.dst_ip[3],
3889                        rule->tuples_mask.dst_ip[3]);
3890                 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
3891                 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
3892
3893                 return true;
3894         case BIT(INNER_SRC_PORT):
3895                 calc_x(tmp_x_s, rule->tuples.src_port,
3896                        rule->tuples_mask.src_port);
3897                 calc_y(tmp_y_s, rule->tuples.src_port,
3898                        rule->tuples_mask.src_port);
3899                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3900                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3901
3902                 return true;
3903         case BIT(INNER_DST_PORT):
3904                 calc_x(tmp_x_s, rule->tuples.dst_port,
3905                        rule->tuples_mask.dst_port);
3906                 calc_y(tmp_y_s, rule->tuples.dst_port,
3907                        rule->tuples_mask.dst_port);
3908                 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3909                 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3910
3911                 return true;
3912         default:
3913                 return false;
3914         }
3915 }
3916
3917 static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id,
3918                                  u8 vf_id, u8 network_port_id)
3919 {
3920         u32 port_number = 0;
3921
3922         if (port_type == HOST_PORT) {
3923                 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S,
3924                                 pf_id);
3925                 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S,
3926                                 vf_id);
3927                 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT);
3928         } else {
3929                 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M,
3930                                 HCLGE_NETWORK_PORT_ID_S, network_port_id);
3931                 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT);
3932         }
3933
3934         return port_number;
3935 }
3936
3937 static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg,
3938                                        __le32 *key_x, __le32 *key_y,
3939                                        struct hclge_fd_rule *rule)
3940 {
3941         u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number;
3942         u8 cur_pos = 0, tuple_size, shift_bits;
3943         int i;
3944
3945         for (i = 0; i < MAX_META_DATA; i++) {
3946                 tuple_size = meta_data_key_info[i].key_length;
3947                 tuple_bit = key_cfg->meta_data_active & BIT(i);
3948
3949                 switch (tuple_bit) {
3950                 case BIT(ROCE_TYPE):
3951                         hnae3_set_bit(meta_data, cur_pos, NIC_PACKET);
3952                         cur_pos += tuple_size;
3953                         break;
3954                 case BIT(DST_VPORT):
3955                         port_number = hclge_get_port_number(HOST_PORT, 0,
3956                                                             rule->vf_id, 0);
3957                         hnae3_set_field(meta_data,
3958                                         GENMASK(cur_pos + tuple_size, cur_pos),
3959                                         cur_pos, port_number);
3960                         cur_pos += tuple_size;
3961                         break;
3962                 default:
3963                         break;
3964                 }
3965         }
3966
3967         calc_x(tmp_x, meta_data, 0xFFFFFFFF);
3968         calc_y(tmp_y, meta_data, 0xFFFFFFFF);
3969         shift_bits = sizeof(meta_data) * 8 - cur_pos;
3970
3971         *key_x = cpu_to_le32(tmp_x << shift_bits);
3972         *key_y = cpu_to_le32(tmp_y << shift_bits);
3973 }
3974
3975 /* A complete key is combined with meta data key and tuple key.
3976  * Meta data key is stored at the MSB region, and tuple key is stored at
3977  * the LSB region, unused bits will be filled 0.
3978  */
3979 static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
3980                             struct hclge_fd_rule *rule)
3981 {
3982         struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage];
3983         u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES];
3984         u8 *cur_key_x, *cur_key_y;
3985         int i, ret, tuple_size;
3986         u8 meta_data_region;
3987
3988         memset(key_x, 0, sizeof(key_x));
3989         memset(key_y, 0, sizeof(key_y));
3990         cur_key_x = key_x;
3991         cur_key_y = key_y;
3992
3993         for (i = 0 ; i < MAX_TUPLE; i++) {
3994                 bool tuple_valid;
3995                 u32 check_tuple;
3996
3997                 tuple_size = tuple_key_info[i].key_length / 8;
3998                 check_tuple = key_cfg->tuple_active & BIT(i);
3999
4000                 tuple_valid = hclge_fd_convert_tuple(check_tuple, cur_key_x,
4001                                                      cur_key_y, rule);
4002                 if (tuple_valid) {
4003                         cur_key_x += tuple_size;
4004                         cur_key_y += tuple_size;
4005                 }
4006         }
4007
4008         meta_data_region = hdev->fd_cfg.max_key_length / 8 -
4009                         MAX_META_DATA_LENGTH / 8;
4010
4011         hclge_fd_convert_meta_data(key_cfg,
4012                                    (__le32 *)(key_x + meta_data_region),
4013                                    (__le32 *)(key_y + meta_data_region),
4014                                    rule);
4015
4016         ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y,
4017                                    true);
4018         if (ret) {
4019                 dev_err(&hdev->pdev->dev,
4020                         "fd key_y config fail, loc=%d, ret=%d\n",
4021                         rule->queue_id, ret);
4022                 return ret;
4023         }
4024
4025         ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x,
4026                                    true);
4027         if (ret)
4028                 dev_err(&hdev->pdev->dev,
4029                         "fd key_x config fail, loc=%d, ret=%d\n",
4030                         rule->queue_id, ret);
4031         return ret;
4032 }
4033
4034 static int hclge_config_action(struct hclge_dev *hdev, u8 stage,
4035                                struct hclge_fd_rule *rule)
4036 {
4037         struct hclge_fd_ad_data ad_data;
4038
4039         ad_data.ad_id = rule->location;
4040
4041         if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
4042                 ad_data.drop_packet = true;
4043                 ad_data.forward_to_direct_queue = false;
4044                 ad_data.queue_id = 0;
4045         } else {
4046                 ad_data.drop_packet = false;
4047                 ad_data.forward_to_direct_queue = true;
4048                 ad_data.queue_id = rule->queue_id;
4049         }
4050
4051         ad_data.use_counter = false;
4052         ad_data.counter_id = 0;
4053
4054         ad_data.use_next_stage = false;
4055         ad_data.next_input_key = 0;
4056
4057         ad_data.write_rule_id_to_bd = true;
4058         ad_data.rule_id = rule->location;
4059
4060         return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data);
4061 }
4062
4063 static int hclge_fd_check_spec(struct hclge_dev *hdev,
4064                                struct ethtool_rx_flow_spec *fs, u32 *unused)
4065 {
4066         struct ethtool_tcpip4_spec *tcp_ip4_spec;
4067         struct ethtool_usrip4_spec *usr_ip4_spec;
4068         struct ethtool_tcpip6_spec *tcp_ip6_spec;
4069         struct ethtool_usrip6_spec *usr_ip6_spec;
4070         struct ethhdr *ether_spec;
4071
4072         if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
4073                 return -EINVAL;
4074
4075         if (!(fs->flow_type & hdev->fd_cfg.proto_support))
4076                 return -EOPNOTSUPP;
4077
4078         if ((fs->flow_type & FLOW_EXT) &&
4079             (fs->h_ext.data[0] != 0 || fs->h_ext.data[1] != 0)) {
4080                 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n");
4081                 return -EOPNOTSUPP;
4082         }
4083
4084         switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
4085         case SCTP_V4_FLOW:
4086         case TCP_V4_FLOW:
4087         case UDP_V4_FLOW:
4088                 tcp_ip4_spec = &fs->h_u.tcp_ip4_spec;
4089                 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
4090
4091                 if (!tcp_ip4_spec->ip4src)
4092                         *unused |= BIT(INNER_SRC_IP);
4093
4094                 if (!tcp_ip4_spec->ip4dst)
4095                         *unused |= BIT(INNER_DST_IP);
4096
4097                 if (!tcp_ip4_spec->psrc)
4098                         *unused |= BIT(INNER_SRC_PORT);
4099
4100                 if (!tcp_ip4_spec->pdst)
4101                         *unused |= BIT(INNER_DST_PORT);
4102
4103                 if (!tcp_ip4_spec->tos)
4104                         *unused |= BIT(INNER_IP_TOS);
4105
4106                 break;
4107         case IP_USER_FLOW:
4108                 usr_ip4_spec = &fs->h_u.usr_ip4_spec;
4109                 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4110                         BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
4111
4112                 if (!usr_ip4_spec->ip4src)
4113                         *unused |= BIT(INNER_SRC_IP);
4114
4115                 if (!usr_ip4_spec->ip4dst)
4116                         *unused |= BIT(INNER_DST_IP);
4117
4118                 if (!usr_ip4_spec->tos)
4119                         *unused |= BIT(INNER_IP_TOS);
4120
4121                 if (!usr_ip4_spec->proto)
4122                         *unused |= BIT(INNER_IP_PROTO);
4123
4124                 if (usr_ip4_spec->l4_4_bytes)
4125                         return -EOPNOTSUPP;
4126
4127                 if (usr_ip4_spec->ip_ver != ETH_RX_NFC_IP4)
4128                         return -EOPNOTSUPP;
4129
4130                 break;
4131         case SCTP_V6_FLOW:
4132         case TCP_V6_FLOW:
4133         case UDP_V6_FLOW:
4134                 tcp_ip6_spec = &fs->h_u.tcp_ip6_spec;
4135                 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4136                         BIT(INNER_IP_TOS);
4137
4138                 if (!tcp_ip6_spec->ip6src[0] && !tcp_ip6_spec->ip6src[1] &&
4139                     !tcp_ip6_spec->ip6src[2] && !tcp_ip6_spec->ip6src[3])
4140                         *unused |= BIT(INNER_SRC_IP);
4141
4142                 if (!tcp_ip6_spec->ip6dst[0] && !tcp_ip6_spec->ip6dst[1] &&
4143                     !tcp_ip6_spec->ip6dst[2] && !tcp_ip6_spec->ip6dst[3])
4144                         *unused |= BIT(INNER_DST_IP);
4145
4146                 if (!tcp_ip6_spec->psrc)
4147                         *unused |= BIT(INNER_SRC_PORT);
4148
4149                 if (!tcp_ip6_spec->pdst)
4150                         *unused |= BIT(INNER_DST_PORT);
4151
4152                 if (tcp_ip6_spec->tclass)
4153                         return -EOPNOTSUPP;
4154
4155                 break;
4156         case IPV6_USER_FLOW:
4157                 usr_ip6_spec = &fs->h_u.usr_ip6_spec;
4158                 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4159                         BIT(INNER_IP_TOS) | BIT(INNER_SRC_PORT) |
4160                         BIT(INNER_DST_PORT);
4161
4162                 if (!usr_ip6_spec->ip6src[0] && !usr_ip6_spec->ip6src[1] &&
4163                     !usr_ip6_spec->ip6src[2] && !usr_ip6_spec->ip6src[3])
4164                         *unused |= BIT(INNER_SRC_IP);
4165
4166                 if (!usr_ip6_spec->ip6dst[0] && !usr_ip6_spec->ip6dst[1] &&
4167                     !usr_ip6_spec->ip6dst[2] && !usr_ip6_spec->ip6dst[3])
4168                         *unused |= BIT(INNER_DST_IP);
4169
4170                 if (!usr_ip6_spec->l4_proto)
4171                         *unused |= BIT(INNER_IP_PROTO);
4172
4173                 if (usr_ip6_spec->tclass)
4174                         return -EOPNOTSUPP;
4175
4176                 if (usr_ip6_spec->l4_4_bytes)
4177                         return -EOPNOTSUPP;
4178
4179                 break;
4180         case ETHER_FLOW:
4181                 ether_spec = &fs->h_u.ether_spec;
4182                 *unused |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
4183                         BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) |
4184                         BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO);
4185
4186                 if (is_zero_ether_addr(ether_spec->h_source))
4187                         *unused |= BIT(INNER_SRC_MAC);
4188
4189                 if (is_zero_ether_addr(ether_spec->h_dest))
4190                         *unused |= BIT(INNER_DST_MAC);
4191
4192                 if (!ether_spec->h_proto)
4193                         *unused |= BIT(INNER_ETH_TYPE);
4194
4195                 break;
4196         default:
4197                 return -EOPNOTSUPP;
4198         }
4199
4200         if ((fs->flow_type & FLOW_EXT)) {
4201                 if (fs->h_ext.vlan_etype)
4202                         return -EOPNOTSUPP;
4203                 if (!fs->h_ext.vlan_tci)
4204                         *unused |= BIT(INNER_VLAN_TAG_FST);
4205
4206                 if (fs->m_ext.vlan_tci) {
4207                         if (be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID)
4208                                 return -EINVAL;
4209                 }
4210         } else {
4211                 *unused |= BIT(INNER_VLAN_TAG_FST);
4212         }
4213
4214         if (fs->flow_type & FLOW_MAC_EXT) {
4215                 if (!(hdev->fd_cfg.proto_support & ETHER_FLOW))
4216                         return -EOPNOTSUPP;
4217
4218                 if (is_zero_ether_addr(fs->h_ext.h_dest))
4219                         *unused |= BIT(INNER_DST_MAC);
4220                 else
4221                         *unused &= ~(BIT(INNER_DST_MAC));
4222         }
4223
4224         return 0;
4225 }
4226
4227 static bool hclge_fd_rule_exist(struct hclge_dev *hdev, u16 location)
4228 {
4229         struct hclge_fd_rule *rule = NULL;
4230         struct hlist_node *node2;
4231
4232         hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
4233                 if (rule->location >= location)
4234                         break;
4235         }
4236
4237         return  rule && rule->location == location;
4238 }
4239
4240 static int hclge_fd_update_rule_list(struct hclge_dev *hdev,
4241                                      struct hclge_fd_rule *new_rule,
4242                                      u16 location,
4243                                      bool is_add)
4244 {
4245         struct hclge_fd_rule *rule = NULL, *parent = NULL;
4246         struct hlist_node *node2;
4247
4248         if (is_add && !new_rule)
4249                 return -EINVAL;
4250
4251         hlist_for_each_entry_safe(rule, node2,
4252                                   &hdev->fd_rule_list, rule_node) {
4253                 if (rule->location >= location)
4254                         break;
4255                 parent = rule;
4256         }
4257
4258         if (rule && rule->location == location) {
4259                 hlist_del(&rule->rule_node);
4260                 kfree(rule);
4261                 hdev->hclge_fd_rule_num--;
4262
4263                 if (!is_add)
4264                         return 0;
4265
4266         } else if (!is_add) {
4267                 dev_err(&hdev->pdev->dev,
4268                         "delete fail, rule %d is inexistent\n",
4269                         location);
4270                 return -EINVAL;
4271         }
4272
4273         INIT_HLIST_NODE(&new_rule->rule_node);
4274
4275         if (parent)
4276                 hlist_add_behind(&new_rule->rule_node, &parent->rule_node);
4277         else
4278                 hlist_add_head(&new_rule->rule_node, &hdev->fd_rule_list);
4279
4280         hdev->hclge_fd_rule_num++;
4281
4282         return 0;
4283 }
4284
4285 static int hclge_fd_get_tuple(struct hclge_dev *hdev,
4286                               struct ethtool_rx_flow_spec *fs,
4287                               struct hclge_fd_rule *rule)
4288 {
4289         u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
4290
4291         switch (flow_type) {
4292         case SCTP_V4_FLOW:
4293         case TCP_V4_FLOW:
4294         case UDP_V4_FLOW:
4295                 rule->tuples.src_ip[3] =
4296                                 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src);
4297                 rule->tuples_mask.src_ip[3] =
4298                                 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src);
4299
4300                 rule->tuples.dst_ip[3] =
4301                                 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst);
4302                 rule->tuples_mask.dst_ip[3] =
4303                                 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst);
4304
4305                 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc);
4306                 rule->tuples_mask.src_port =
4307                                 be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc);
4308
4309                 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst);
4310                 rule->tuples_mask.dst_port =
4311                                 be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst);
4312
4313                 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos;
4314                 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos;
4315
4316                 rule->tuples.ether_proto = ETH_P_IP;
4317                 rule->tuples_mask.ether_proto = 0xFFFF;
4318
4319                 break;
4320         case IP_USER_FLOW:
4321                 rule->tuples.src_ip[3] =
4322                                 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src);
4323                 rule->tuples_mask.src_ip[3] =
4324                                 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src);
4325
4326                 rule->tuples.dst_ip[3] =
4327                                 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst);
4328                 rule->tuples_mask.dst_ip[3] =
4329                                 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst);
4330
4331                 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos;
4332                 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos;
4333
4334                 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto;
4335                 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto;
4336
4337                 rule->tuples.ether_proto = ETH_P_IP;
4338                 rule->tuples_mask.ether_proto = 0xFFFF;
4339
4340                 break;
4341         case SCTP_V6_FLOW:
4342         case TCP_V6_FLOW:
4343         case UDP_V6_FLOW:
4344                 be32_to_cpu_array(rule->tuples.src_ip,
4345                                   fs->h_u.tcp_ip6_spec.ip6src, 4);
4346                 be32_to_cpu_array(rule->tuples_mask.src_ip,
4347                                   fs->m_u.tcp_ip6_spec.ip6src, 4);
4348
4349                 be32_to_cpu_array(rule->tuples.dst_ip,
4350                                   fs->h_u.tcp_ip6_spec.ip6dst, 4);
4351                 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4352                                   fs->m_u.tcp_ip6_spec.ip6dst, 4);
4353
4354                 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc);
4355                 rule->tuples_mask.src_port =
4356                                 be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc);
4357
4358                 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst);
4359                 rule->tuples_mask.dst_port =
4360                                 be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst);
4361
4362                 rule->tuples.ether_proto = ETH_P_IPV6;
4363                 rule->tuples_mask.ether_proto = 0xFFFF;
4364
4365                 break;
4366         case IPV6_USER_FLOW:
4367                 be32_to_cpu_array(rule->tuples.src_ip,
4368                                   fs->h_u.usr_ip6_spec.ip6src, 4);
4369                 be32_to_cpu_array(rule->tuples_mask.src_ip,
4370                                   fs->m_u.usr_ip6_spec.ip6src, 4);
4371
4372                 be32_to_cpu_array(rule->tuples.dst_ip,
4373                                   fs->h_u.usr_ip6_spec.ip6dst, 4);
4374                 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4375                                   fs->m_u.usr_ip6_spec.ip6dst, 4);
4376
4377                 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto;
4378                 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto;
4379
4380                 rule->tuples.ether_proto = ETH_P_IPV6;
4381                 rule->tuples_mask.ether_proto = 0xFFFF;
4382
4383                 break;
4384         case ETHER_FLOW:
4385                 ether_addr_copy(rule->tuples.src_mac,
4386                                 fs->h_u.ether_spec.h_source);
4387                 ether_addr_copy(rule->tuples_mask.src_mac,
4388                                 fs->m_u.ether_spec.h_source);
4389
4390                 ether_addr_copy(rule->tuples.dst_mac,
4391                                 fs->h_u.ether_spec.h_dest);
4392                 ether_addr_copy(rule->tuples_mask.dst_mac,
4393                                 fs->m_u.ether_spec.h_dest);
4394
4395                 rule->tuples.ether_proto =
4396                                 be16_to_cpu(fs->h_u.ether_spec.h_proto);
4397                 rule->tuples_mask.ether_proto =
4398                                 be16_to_cpu(fs->m_u.ether_spec.h_proto);
4399
4400                 break;
4401         default:
4402                 return -EOPNOTSUPP;
4403         }
4404
4405         switch (flow_type) {
4406         case SCTP_V4_FLOW:
4407         case SCTP_V6_FLOW:
4408                 rule->tuples.ip_proto = IPPROTO_SCTP;
4409                 rule->tuples_mask.ip_proto = 0xFF;
4410                 break;
4411         case TCP_V4_FLOW:
4412         case TCP_V6_FLOW:
4413                 rule->tuples.ip_proto = IPPROTO_TCP;
4414                 rule->tuples_mask.ip_proto = 0xFF;
4415                 break;
4416         case UDP_V4_FLOW:
4417         case UDP_V6_FLOW:
4418                 rule->tuples.ip_proto = IPPROTO_UDP;
4419                 rule->tuples_mask.ip_proto = 0xFF;
4420                 break;
4421         default:
4422                 break;
4423         }
4424
4425         if ((fs->flow_type & FLOW_EXT)) {
4426                 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci);
4427                 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci);
4428         }
4429
4430         if (fs->flow_type & FLOW_MAC_EXT) {
4431                 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest);
4432                 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest);
4433         }
4434
4435         return 0;
4436 }
4437
4438 static int hclge_add_fd_entry(struct hnae3_handle *handle,
4439                               struct ethtool_rxnfc *cmd)
4440 {
4441         struct hclge_vport *vport = hclge_get_vport(handle);
4442         struct hclge_dev *hdev = vport->back;
4443         u16 dst_vport_id = 0, q_index = 0;
4444         struct ethtool_rx_flow_spec *fs;
4445         struct hclge_fd_rule *rule;
4446         u32 unused = 0;
4447         u8 action;
4448         int ret;
4449
4450         if (!hnae3_dev_fd_supported(hdev))
4451                 return -EOPNOTSUPP;
4452
4453         if (!hdev->fd_cfg.fd_en) {
4454                 dev_warn(&hdev->pdev->dev,
4455                          "Please enable flow director first\n");
4456                 return -EOPNOTSUPP;
4457         }
4458
4459         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4460
4461         ret = hclge_fd_check_spec(hdev, fs, &unused);
4462         if (ret) {
4463                 dev_err(&hdev->pdev->dev, "Check fd spec failed\n");
4464                 return ret;
4465         }
4466
4467         if (fs->ring_cookie == RX_CLS_FLOW_DISC) {
4468                 action = HCLGE_FD_ACTION_DROP_PACKET;
4469         } else {
4470                 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
4471                 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
4472                 u16 tqps;
4473
4474                 dst_vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id;
4475                 tqps = vf ? hdev->vport[vf].alloc_tqps : vport->alloc_tqps;
4476
4477                 if (ring >= tqps) {
4478                         dev_err(&hdev->pdev->dev,
4479                                 "Error: queue id (%d) > max tqp num (%d)\n",
4480                                 ring, tqps - 1);
4481                         return -EINVAL;
4482                 }
4483
4484                 if (vf > hdev->num_req_vfs) {
4485                         dev_err(&hdev->pdev->dev,
4486                                 "Error: vf id (%d) > max vf num (%d)\n",
4487                                 vf, hdev->num_req_vfs);
4488                         return -EINVAL;
4489                 }
4490
4491                 action = HCLGE_FD_ACTION_ACCEPT_PACKET;
4492                 q_index = ring;
4493         }
4494
4495         rule = kzalloc(sizeof(*rule), GFP_KERNEL);
4496         if (!rule)
4497                 return -ENOMEM;
4498
4499         ret = hclge_fd_get_tuple(hdev, fs, rule);
4500         if (ret)
4501                 goto free_rule;
4502
4503         rule->flow_type = fs->flow_type;
4504
4505         rule->location = fs->location;
4506         rule->unused_tuple = unused;
4507         rule->vf_id = dst_vport_id;
4508         rule->queue_id = q_index;
4509         rule->action = action;
4510
4511         ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4512         if (ret)
4513                 goto free_rule;
4514
4515         ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4516         if (ret)
4517                 goto free_rule;
4518
4519         ret = hclge_fd_update_rule_list(hdev, rule, fs->location, true);
4520         if (ret)
4521                 goto free_rule;
4522
4523         return ret;
4524
4525 free_rule:
4526         kfree(rule);
4527         return ret;
4528 }
4529
4530 static int hclge_del_fd_entry(struct hnae3_handle *handle,
4531                               struct ethtool_rxnfc *cmd)
4532 {
4533         struct hclge_vport *vport = hclge_get_vport(handle);
4534         struct hclge_dev *hdev = vport->back;
4535         struct ethtool_rx_flow_spec *fs;
4536         int ret;
4537
4538         if (!hnae3_dev_fd_supported(hdev))
4539                 return -EOPNOTSUPP;
4540
4541         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4542
4543         if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
4544                 return -EINVAL;
4545
4546         if (!hclge_fd_rule_exist(hdev, fs->location)) {
4547                 dev_err(&hdev->pdev->dev,
4548                         "Delete fail, rule %d is inexistent\n",
4549                         fs->location);
4550                 return -ENOENT;
4551         }
4552
4553         ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4554                                    fs->location, NULL, false);
4555         if (ret)
4556                 return ret;
4557
4558         return hclge_fd_update_rule_list(hdev, NULL, fs->location,
4559                                          false);
4560 }
4561
4562 static void hclge_del_all_fd_entries(struct hnae3_handle *handle,
4563                                      bool clear_list)
4564 {
4565         struct hclge_vport *vport = hclge_get_vport(handle);
4566         struct hclge_dev *hdev = vport->back;
4567         struct hclge_fd_rule *rule;
4568         struct hlist_node *node;
4569
4570         if (!hnae3_dev_fd_supported(hdev))
4571                 return;
4572
4573         if (clear_list) {
4574                 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4575                                           rule_node) {
4576                         hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4577                                              rule->location, NULL, false);
4578                         hlist_del(&rule->rule_node);
4579                         kfree(rule);
4580                         hdev->hclge_fd_rule_num--;
4581                 }
4582         } else {
4583                 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4584                                           rule_node)
4585                         hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4586                                              rule->location, NULL, false);
4587         }
4588 }
4589
4590 static int hclge_restore_fd_entries(struct hnae3_handle *handle)
4591 {
4592         struct hclge_vport *vport = hclge_get_vport(handle);
4593         struct hclge_dev *hdev = vport->back;
4594         struct hclge_fd_rule *rule;
4595         struct hlist_node *node;
4596         int ret;
4597
4598         /* Return ok here, because reset error handling will check this
4599          * return value. If error is returned here, the reset process will
4600          * fail.
4601          */
4602         if (!hnae3_dev_fd_supported(hdev))
4603                 return 0;
4604
4605         hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
4606                 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4607                 if (!ret)
4608                         ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4609
4610                 if (ret) {
4611                         dev_warn(&hdev->pdev->dev,
4612                                  "Restore rule %d failed, remove it\n",
4613                                  rule->location);
4614                         hlist_del(&rule->rule_node);
4615                         kfree(rule);
4616                         hdev->hclge_fd_rule_num--;
4617                 }
4618         }
4619         return 0;
4620 }
4621
4622 static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle,
4623                                  struct ethtool_rxnfc *cmd)
4624 {
4625         struct hclge_vport *vport = hclge_get_vport(handle);
4626         struct hclge_dev *hdev = vport->back;
4627
4628         if (!hnae3_dev_fd_supported(hdev))
4629                 return -EOPNOTSUPP;
4630
4631         cmd->rule_cnt = hdev->hclge_fd_rule_num;
4632         cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
4633
4634         return 0;
4635 }
4636
4637 static int hclge_get_fd_rule_info(struct hnae3_handle *handle,
4638                                   struct ethtool_rxnfc *cmd)
4639 {
4640         struct hclge_vport *vport = hclge_get_vport(handle);
4641         struct hclge_fd_rule *rule = NULL;
4642         struct hclge_dev *hdev = vport->back;
4643         struct ethtool_rx_flow_spec *fs;
4644         struct hlist_node *node2;
4645
4646         if (!hnae3_dev_fd_supported(hdev))
4647                 return -EOPNOTSUPP;
4648
4649         fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4650
4651         hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
4652                 if (rule->location >= fs->location)
4653                         break;
4654         }
4655
4656         if (!rule || fs->location != rule->location)
4657                 return -ENOENT;
4658
4659         fs->flow_type = rule->flow_type;
4660         switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
4661         case SCTP_V4_FLOW:
4662         case TCP_V4_FLOW:
4663         case UDP_V4_FLOW:
4664                 fs->h_u.tcp_ip4_spec.ip4src =
4665                                 cpu_to_be32(rule->tuples.src_ip[3]);
4666                 fs->m_u.tcp_ip4_spec.ip4src =
4667                                 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4668                                 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4669
4670                 fs->h_u.tcp_ip4_spec.ip4dst =
4671                                 cpu_to_be32(rule->tuples.dst_ip[3]);
4672                 fs->m_u.tcp_ip4_spec.ip4dst =
4673                                 rule->unused_tuple & BIT(INNER_DST_IP) ?
4674                                 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4675
4676                 fs->h_u.tcp_ip4_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4677                 fs->m_u.tcp_ip4_spec.psrc =
4678                                 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4679                                 0 : cpu_to_be16(rule->tuples_mask.src_port);
4680
4681                 fs->h_u.tcp_ip4_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4682                 fs->m_u.tcp_ip4_spec.pdst =
4683                                 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4684                                 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4685
4686                 fs->h_u.tcp_ip4_spec.tos = rule->tuples.ip_tos;
4687                 fs->m_u.tcp_ip4_spec.tos =
4688                                 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4689                                 0 : rule->tuples_mask.ip_tos;
4690
4691                 break;
4692         case IP_USER_FLOW:
4693                 fs->h_u.usr_ip4_spec.ip4src =
4694                                 cpu_to_be32(rule->tuples.src_ip[3]);
4695                 fs->m_u.tcp_ip4_spec.ip4src =
4696                                 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4697                                 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4698
4699                 fs->h_u.usr_ip4_spec.ip4dst =
4700                                 cpu_to_be32(rule->tuples.dst_ip[3]);
4701                 fs->m_u.usr_ip4_spec.ip4dst =
4702                                 rule->unused_tuple & BIT(INNER_DST_IP) ?
4703                                 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4704
4705                 fs->h_u.usr_ip4_spec.tos = rule->tuples.ip_tos;
4706                 fs->m_u.usr_ip4_spec.tos =
4707                                 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4708                                 0 : rule->tuples_mask.ip_tos;
4709
4710                 fs->h_u.usr_ip4_spec.proto = rule->tuples.ip_proto;
4711                 fs->m_u.usr_ip4_spec.proto =
4712                                 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4713                                 0 : rule->tuples_mask.ip_proto;
4714
4715                 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
4716
4717                 break;
4718         case SCTP_V6_FLOW:
4719         case TCP_V6_FLOW:
4720         case UDP_V6_FLOW:
4721                 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6src,
4722                                   rule->tuples.src_ip, 4);
4723                 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4724                         memset(fs->m_u.tcp_ip6_spec.ip6src, 0, sizeof(int) * 4);
4725                 else
4726                         cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6src,
4727                                           rule->tuples_mask.src_ip, 4);
4728
4729                 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6dst,
4730                                   rule->tuples.dst_ip, 4);
4731                 if (rule->unused_tuple & BIT(INNER_DST_IP))
4732                         memset(fs->m_u.tcp_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4733                 else
4734                         cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6dst,
4735                                           rule->tuples_mask.dst_ip, 4);
4736
4737                 fs->h_u.tcp_ip6_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4738                 fs->m_u.tcp_ip6_spec.psrc =
4739                                 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4740                                 0 : cpu_to_be16(rule->tuples_mask.src_port);
4741
4742                 fs->h_u.tcp_ip6_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4743                 fs->m_u.tcp_ip6_spec.pdst =
4744                                 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4745                                 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4746
4747                 break;
4748         case IPV6_USER_FLOW:
4749                 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6src,
4750                                   rule->tuples.src_ip, 4);
4751                 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4752                         memset(fs->m_u.usr_ip6_spec.ip6src, 0, sizeof(int) * 4);
4753                 else
4754                         cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6src,
4755                                           rule->tuples_mask.src_ip, 4);
4756
4757                 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6dst,
4758                                   rule->tuples.dst_ip, 4);
4759                 if (rule->unused_tuple & BIT(INNER_DST_IP))
4760                         memset(fs->m_u.usr_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4761                 else
4762                         cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6dst,
4763                                           rule->tuples_mask.dst_ip, 4);
4764
4765                 fs->h_u.usr_ip6_spec.l4_proto = rule->tuples.ip_proto;
4766                 fs->m_u.usr_ip6_spec.l4_proto =
4767                                 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4768                                 0 : rule->tuples_mask.ip_proto;
4769
4770                 break;
4771         case ETHER_FLOW:
4772                 ether_addr_copy(fs->h_u.ether_spec.h_source,
4773                                 rule->tuples.src_mac);
4774                 if (rule->unused_tuple & BIT(INNER_SRC_MAC))
4775                         eth_zero_addr(fs->m_u.ether_spec.h_source);
4776                 else
4777                         ether_addr_copy(fs->m_u.ether_spec.h_source,
4778                                         rule->tuples_mask.src_mac);
4779
4780                 ether_addr_copy(fs->h_u.ether_spec.h_dest,
4781                                 rule->tuples.dst_mac);
4782                 if (rule->unused_tuple & BIT(INNER_DST_MAC))
4783                         eth_zero_addr(fs->m_u.ether_spec.h_dest);
4784                 else
4785                         ether_addr_copy(fs->m_u.ether_spec.h_dest,
4786                                         rule->tuples_mask.dst_mac);
4787
4788                 fs->h_u.ether_spec.h_proto =
4789                                 cpu_to_be16(rule->tuples.ether_proto);
4790                 fs->m_u.ether_spec.h_proto =
4791                                 rule->unused_tuple & BIT(INNER_ETH_TYPE) ?
4792                                 0 : cpu_to_be16(rule->tuples_mask.ether_proto);
4793
4794                 break;
4795         default:
4796                 return -EOPNOTSUPP;
4797         }
4798
4799         if (fs->flow_type & FLOW_EXT) {
4800                 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1);
4801                 fs->m_ext.vlan_tci =
4802                                 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ?
4803                                 cpu_to_be16(VLAN_VID_MASK) :
4804                                 cpu_to_be16(rule->tuples_mask.vlan_tag1);
4805         }
4806
4807         if (fs->flow_type & FLOW_MAC_EXT) {
4808                 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac);
4809                 if (rule->unused_tuple & BIT(INNER_DST_MAC))
4810                         eth_zero_addr(fs->m_u.ether_spec.h_dest);
4811                 else
4812                         ether_addr_copy(fs->m_u.ether_spec.h_dest,
4813                                         rule->tuples_mask.dst_mac);
4814         }
4815
4816         if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
4817                 fs->ring_cookie = RX_CLS_FLOW_DISC;
4818         } else {
4819                 u64 vf_id;
4820
4821                 fs->ring_cookie = rule->queue_id;
4822                 vf_id = rule->vf_id;
4823                 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
4824                 fs->ring_cookie |= vf_id;
4825         }
4826
4827         return 0;
4828 }
4829
4830 static int hclge_get_all_rules(struct hnae3_handle *handle,
4831                                struct ethtool_rxnfc *cmd, u32 *rule_locs)
4832 {
4833         struct hclge_vport *vport = hclge_get_vport(handle);
4834         struct hclge_dev *hdev = vport->back;
4835         struct hclge_fd_rule *rule;
4836         struct hlist_node *node2;
4837         int cnt = 0;
4838
4839         if (!hnae3_dev_fd_supported(hdev))
4840                 return -EOPNOTSUPP;
4841
4842         cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
4843
4844         hlist_for_each_entry_safe(rule, node2,
4845                                   &hdev->fd_rule_list, rule_node) {
4846                 if (cnt == cmd->rule_cnt)
4847                         return -EMSGSIZE;
4848
4849                 rule_locs[cnt] = rule->location;
4850                 cnt++;
4851         }
4852
4853         cmd->rule_cnt = cnt;
4854
4855         return 0;
4856 }
4857
4858 static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle)
4859 {
4860         struct hclge_vport *vport = hclge_get_vport(handle);
4861         struct hclge_dev *hdev = vport->back;
4862
4863         return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) ||
4864                hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING);
4865 }
4866
4867 static bool hclge_ae_dev_resetting(struct hnae3_handle *handle)
4868 {
4869         struct hclge_vport *vport = hclge_get_vport(handle);
4870         struct hclge_dev *hdev = vport->back;
4871
4872         return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
4873 }
4874
4875 static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle)
4876 {
4877         struct hclge_vport *vport = hclge_get_vport(handle);
4878         struct hclge_dev *hdev = vport->back;
4879
4880         return hdev->reset_count;
4881 }
4882
4883 static void hclge_enable_fd(struct hnae3_handle *handle, bool enable)
4884 {
4885         struct hclge_vport *vport = hclge_get_vport(handle);
4886         struct hclge_dev *hdev = vport->back;
4887
4888         hdev->fd_cfg.fd_en = enable;
4889         if (!enable)
4890                 hclge_del_all_fd_entries(handle, false);
4891         else
4892                 hclge_restore_fd_entries(handle);
4893 }
4894
4895 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
4896 {
4897         struct hclge_desc desc;
4898         struct hclge_config_mac_mode_cmd *req =
4899                 (struct hclge_config_mac_mode_cmd *)desc.data;
4900         u32 loop_en = 0;
4901         int ret;
4902
4903         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
4904         hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
4905         hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
4906         hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
4907         hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
4908         hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
4909         hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
4910         hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
4911         hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
4912         hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
4913         hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
4914         hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
4915         hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
4916         hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
4917         hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
4918         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
4919
4920         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4921         if (ret)
4922                 dev_err(&hdev->pdev->dev,
4923                         "mac enable fail, ret =%d.\n", ret);
4924 }
4925
4926 static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
4927 {
4928         struct hclge_config_mac_mode_cmd *req;
4929         struct hclge_desc desc;
4930         u32 loop_en;
4931         int ret;
4932
4933         req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
4934         /* 1 Read out the MAC mode config at first */
4935         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
4936         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4937         if (ret) {
4938                 dev_err(&hdev->pdev->dev,
4939                         "mac loopback get fail, ret =%d.\n", ret);
4940                 return ret;
4941         }
4942
4943         /* 2 Then setup the loopback flag */
4944         loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
4945         hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
4946         hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, en ? 1 : 0);
4947         hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, en ? 1 : 0);
4948
4949         req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
4950
4951         /* 3 Config mac work mode with loopback flag
4952          * and its original configure parameters
4953          */
4954         hclge_cmd_reuse_desc(&desc, false);
4955         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4956         if (ret)
4957                 dev_err(&hdev->pdev->dev,
4958                         "mac loopback set fail, ret =%d.\n", ret);
4959         return ret;
4960 }
4961
4962 static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en,
4963                                      enum hnae3_loop loop_mode)
4964 {
4965 #define HCLGE_SERDES_RETRY_MS   10
4966 #define HCLGE_SERDES_RETRY_NUM  100
4967         struct hclge_serdes_lb_cmd *req;
4968         struct hclge_desc desc;
4969         int ret, i = 0;
4970         u8 loop_mode_b;
4971
4972         req = (struct hclge_serdes_lb_cmd *)desc.data;
4973         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
4974
4975         switch (loop_mode) {
4976         case HNAE3_LOOP_SERIAL_SERDES:
4977                 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
4978                 break;
4979         case HNAE3_LOOP_PARALLEL_SERDES:
4980                 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
4981                 break;
4982         default:
4983                 dev_err(&hdev->pdev->dev,
4984                         "unsupported serdes loopback mode %d\n", loop_mode);
4985                 return -ENOTSUPP;
4986         }
4987
4988         if (en) {
4989                 req->enable = loop_mode_b;
4990                 req->mask = loop_mode_b;
4991         } else {
4992                 req->mask = loop_mode_b;
4993         }
4994
4995         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4996         if (ret) {
4997                 dev_err(&hdev->pdev->dev,
4998                         "serdes loopback set fail, ret = %d\n", ret);
4999                 return ret;
5000         }
5001
5002         do {
5003                 msleep(HCLGE_SERDES_RETRY_MS);
5004                 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
5005                                            true);
5006                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5007                 if (ret) {
5008                         dev_err(&hdev->pdev->dev,
5009                                 "serdes loopback get, ret = %d\n", ret);
5010                         return ret;
5011                 }
5012         } while (++i < HCLGE_SERDES_RETRY_NUM &&
5013                  !(req->result & HCLGE_CMD_SERDES_DONE_B));
5014
5015         if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
5016                 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
5017                 return -EBUSY;
5018         } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
5019                 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
5020                 return -EIO;
5021         }
5022
5023         hclge_cfg_mac_mode(hdev, en);
5024         return 0;
5025 }
5026
5027 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
5028                             int stream_id, bool enable)
5029 {
5030         struct hclge_desc desc;
5031         struct hclge_cfg_com_tqp_queue_cmd *req =
5032                 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
5033         int ret;
5034
5035         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
5036         req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
5037         req->stream_id = cpu_to_le16(stream_id);
5038         req->enable |= enable << HCLGE_TQP_ENABLE_B;
5039
5040         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5041         if (ret)
5042                 dev_err(&hdev->pdev->dev,
5043                         "Tqp enable fail, status =%d.\n", ret);
5044         return ret;
5045 }
5046
5047 static int hclge_set_loopback(struct hnae3_handle *handle,
5048                               enum hnae3_loop loop_mode, bool en)
5049 {
5050         struct hclge_vport *vport = hclge_get_vport(handle);
5051         struct hclge_dev *hdev = vport->back;
5052         int i, ret;
5053
5054         switch (loop_mode) {
5055         case HNAE3_LOOP_APP:
5056                 ret = hclge_set_app_loopback(hdev, en);
5057                 break;
5058         case HNAE3_LOOP_SERIAL_SERDES:
5059         case HNAE3_LOOP_PARALLEL_SERDES:
5060                 ret = hclge_set_serdes_loopback(hdev, en, loop_mode);
5061                 break;
5062         default:
5063                 ret = -ENOTSUPP;
5064                 dev_err(&hdev->pdev->dev,
5065                         "loop_mode %d is not supported\n", loop_mode);
5066                 break;
5067         }
5068
5069         for (i = 0; i < vport->alloc_tqps; i++) {
5070                 ret = hclge_tqp_enable(hdev, i, 0, en);
5071                 if (ret)
5072                         return ret;
5073         }
5074
5075         return 0;
5076 }
5077
5078 static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
5079 {
5080         struct hclge_vport *vport = hclge_get_vport(handle);
5081         struct hnae3_queue *queue;
5082         struct hclge_tqp *tqp;
5083         int i;
5084
5085         for (i = 0; i < vport->alloc_tqps; i++) {
5086                 queue = handle->kinfo.tqp[i];
5087                 tqp = container_of(queue, struct hclge_tqp, q);
5088                 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
5089         }
5090 }
5091
5092 static int hclge_ae_start(struct hnae3_handle *handle)
5093 {
5094         struct hclge_vport *vport = hclge_get_vport(handle);
5095         struct hclge_dev *hdev = vport->back;
5096
5097         /* mac enable */
5098         hclge_cfg_mac_mode(hdev, true);
5099         clear_bit(HCLGE_STATE_DOWN, &hdev->state);
5100         mod_timer(&hdev->service_timer, jiffies + HZ);
5101         hdev->hw.mac.link = 0;
5102
5103         /* reset tqp stats */
5104         hclge_reset_tqp_stats(handle);
5105
5106         hclge_mac_start_phy(hdev);
5107
5108         return 0;
5109 }
5110
5111 static void hclge_ae_stop(struct hnae3_handle *handle)
5112 {
5113         struct hclge_vport *vport = hclge_get_vport(handle);
5114         struct hclge_dev *hdev = vport->back;
5115
5116         set_bit(HCLGE_STATE_DOWN, &hdev->state);
5117
5118         del_timer_sync(&hdev->service_timer);
5119         cancel_work_sync(&hdev->service_task);
5120         clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
5121
5122         /* If it is not PF reset, the firmware will disable the MAC,
5123          * so it only need to stop phy here.
5124          */
5125         if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) &&
5126             hdev->reset_type != HNAE3_FUNC_RESET) {
5127                 hclge_mac_stop_phy(hdev);
5128                 return;
5129         }
5130
5131         /* Mac disable */
5132         hclge_cfg_mac_mode(hdev, false);
5133
5134         hclge_mac_stop_phy(hdev);
5135
5136         /* reset tqp stats */
5137         hclge_reset_tqp_stats(handle);
5138         del_timer_sync(&hdev->service_timer);
5139         cancel_work_sync(&hdev->service_task);
5140         hclge_update_link_status(hdev);
5141 }
5142
5143 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
5144                                          u16 cmdq_resp, u8  resp_code,
5145                                          enum hclge_mac_vlan_tbl_opcode op)
5146 {
5147         struct hclge_dev *hdev = vport->back;
5148         int return_status = -EIO;
5149
5150         if (cmdq_resp) {
5151                 dev_err(&hdev->pdev->dev,
5152                         "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
5153                         cmdq_resp);
5154                 return -EIO;
5155         }
5156
5157         if (op == HCLGE_MAC_VLAN_ADD) {
5158                 if ((!resp_code) || (resp_code == 1)) {
5159                         return_status = 0;
5160                 } else if (resp_code == 2) {
5161                         return_status = -ENOSPC;
5162                         dev_err(&hdev->pdev->dev,
5163                                 "add mac addr failed for uc_overflow.\n");
5164                 } else if (resp_code == 3) {
5165                         return_status = -ENOSPC;
5166                         dev_err(&hdev->pdev->dev,
5167                                 "add mac addr failed for mc_overflow.\n");
5168                 } else {
5169                         dev_err(&hdev->pdev->dev,
5170                                 "add mac addr failed for undefined, code=%d.\n",
5171                                 resp_code);
5172                 }
5173         } else if (op == HCLGE_MAC_VLAN_REMOVE) {
5174                 if (!resp_code) {
5175                         return_status = 0;
5176                 } else if (resp_code == 1) {
5177                         return_status = -ENOENT;
5178                         dev_dbg(&hdev->pdev->dev,
5179                                 "remove mac addr failed for miss.\n");
5180                 } else {
5181                         dev_err(&hdev->pdev->dev,
5182                                 "remove mac addr failed for undefined, code=%d.\n",
5183                                 resp_code);
5184                 }
5185         } else if (op == HCLGE_MAC_VLAN_LKUP) {
5186                 if (!resp_code) {
5187                         return_status = 0;
5188                 } else if (resp_code == 1) {
5189                         return_status = -ENOENT;
5190                         dev_dbg(&hdev->pdev->dev,
5191                                 "lookup mac addr failed for miss.\n");
5192                 } else {
5193                         dev_err(&hdev->pdev->dev,
5194                                 "lookup mac addr failed for undefined, code=%d.\n",
5195                                 resp_code);
5196                 }
5197         } else {
5198                 return_status = -EINVAL;
5199                 dev_err(&hdev->pdev->dev,
5200                         "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
5201                         op);
5202         }
5203
5204         return return_status;
5205 }
5206
5207 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
5208 {
5209         int word_num;
5210         int bit_num;
5211
5212         if (vfid > 255 || vfid < 0)
5213                 return -EIO;
5214
5215         if (vfid >= 0 && vfid <= 191) {
5216                 word_num = vfid / 32;
5217                 bit_num  = vfid % 32;
5218                 if (clr)
5219                         desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
5220                 else
5221                         desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
5222         } else {
5223                 word_num = (vfid - 192) / 32;
5224                 bit_num  = vfid % 32;
5225                 if (clr)
5226                         desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
5227                 else
5228                         desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
5229         }
5230
5231         return 0;
5232 }
5233
5234 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
5235 {
5236 #define HCLGE_DESC_NUMBER 3
5237 #define HCLGE_FUNC_NUMBER_PER_DESC 6
5238         int i, j;
5239
5240         for (i = 1; i < HCLGE_DESC_NUMBER; i++)
5241                 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
5242                         if (desc[i].data[j])
5243                                 return false;
5244
5245         return true;
5246 }
5247
5248 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
5249                                    const u8 *addr)
5250 {
5251         const unsigned char *mac_addr = addr;
5252         u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
5253                        (mac_addr[0]) | (mac_addr[1] << 8);
5254         u32 low_val  = mac_addr[4] | (mac_addr[5] << 8);
5255
5256         new_req->mac_addr_hi32 = cpu_to_le32(high_val);
5257         new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
5258 }
5259
5260 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
5261                                      struct hclge_mac_vlan_tbl_entry_cmd *req)
5262 {
5263         struct hclge_dev *hdev = vport->back;
5264         struct hclge_desc desc;
5265         u8 resp_code;
5266         u16 retval;
5267         int ret;
5268
5269         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
5270
5271         memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5272
5273         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5274         if (ret) {
5275                 dev_err(&hdev->pdev->dev,
5276                         "del mac addr failed for cmd_send, ret =%d.\n",
5277                         ret);
5278                 return ret;
5279         }
5280         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5281         retval = le16_to_cpu(desc.retval);
5282
5283         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
5284                                              HCLGE_MAC_VLAN_REMOVE);
5285 }
5286
5287 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
5288                                      struct hclge_mac_vlan_tbl_entry_cmd *req,
5289                                      struct hclge_desc *desc,
5290                                      bool is_mc)
5291 {
5292         struct hclge_dev *hdev = vport->back;
5293         u8 resp_code;
5294         u16 retval;
5295         int ret;
5296
5297         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
5298         if (is_mc) {
5299                 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5300                 memcpy(desc[0].data,
5301                        req,
5302                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5303                 hclge_cmd_setup_basic_desc(&desc[1],
5304                                            HCLGE_OPC_MAC_VLAN_ADD,
5305                                            true);
5306                 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5307                 hclge_cmd_setup_basic_desc(&desc[2],
5308                                            HCLGE_OPC_MAC_VLAN_ADD,
5309                                            true);
5310                 ret = hclge_cmd_send(&hdev->hw, desc, 3);
5311         } else {
5312                 memcpy(desc[0].data,
5313                        req,
5314                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5315                 ret = hclge_cmd_send(&hdev->hw, desc, 1);
5316         }
5317         if (ret) {
5318                 dev_err(&hdev->pdev->dev,
5319                         "lookup mac addr failed for cmd_send, ret =%d.\n",
5320                         ret);
5321                 return ret;
5322         }
5323         resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
5324         retval = le16_to_cpu(desc[0].retval);
5325
5326         return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
5327                                              HCLGE_MAC_VLAN_LKUP);
5328 }
5329
5330 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
5331                                   struct hclge_mac_vlan_tbl_entry_cmd *req,
5332                                   struct hclge_desc *mc_desc)
5333 {
5334         struct hclge_dev *hdev = vport->back;
5335         int cfg_status;
5336         u8 resp_code;
5337         u16 retval;
5338         int ret;
5339
5340         if (!mc_desc) {
5341                 struct hclge_desc desc;
5342
5343                 hclge_cmd_setup_basic_desc(&desc,
5344                                            HCLGE_OPC_MAC_VLAN_ADD,
5345                                            false);
5346                 memcpy(desc.data, req,
5347                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5348                 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5349                 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5350                 retval = le16_to_cpu(desc.retval);
5351
5352                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
5353                                                            resp_code,
5354                                                            HCLGE_MAC_VLAN_ADD);
5355         } else {
5356                 hclge_cmd_reuse_desc(&mc_desc[0], false);
5357                 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5358                 hclge_cmd_reuse_desc(&mc_desc[1], false);
5359                 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5360                 hclge_cmd_reuse_desc(&mc_desc[2], false);
5361                 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
5362                 memcpy(mc_desc[0].data, req,
5363                        sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
5364                 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
5365                 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
5366                 retval = le16_to_cpu(mc_desc[0].retval);
5367
5368                 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
5369                                                            resp_code,
5370                                                            HCLGE_MAC_VLAN_ADD);
5371         }
5372
5373         if (ret) {
5374                 dev_err(&hdev->pdev->dev,
5375                         "add mac addr failed for cmd_send, ret =%d.\n",
5376                         ret);
5377                 return ret;
5378         }
5379
5380         return cfg_status;
5381 }
5382
5383 static int hclge_init_umv_space(struct hclge_dev *hdev)
5384 {
5385         u16 allocated_size = 0;
5386         int ret;
5387
5388         ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size,
5389                                   true);
5390         if (ret)
5391                 return ret;
5392
5393         if (allocated_size < hdev->wanted_umv_size)
5394                 dev_warn(&hdev->pdev->dev,
5395                          "Alloc umv space failed, want %d, get %d\n",
5396                          hdev->wanted_umv_size, allocated_size);
5397
5398         mutex_init(&hdev->umv_mutex);
5399         hdev->max_umv_size = allocated_size;
5400         hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_req_vfs + 2);
5401         hdev->share_umv_size = hdev->priv_umv_size +
5402                         hdev->max_umv_size % (hdev->num_req_vfs + 2);
5403
5404         return 0;
5405 }
5406
5407 static int hclge_uninit_umv_space(struct hclge_dev *hdev)
5408 {
5409         int ret;
5410
5411         if (hdev->max_umv_size > 0) {
5412                 ret = hclge_set_umv_space(hdev, hdev->max_umv_size, NULL,
5413                                           false);
5414                 if (ret)
5415                         return ret;
5416                 hdev->max_umv_size = 0;
5417         }
5418         mutex_destroy(&hdev->umv_mutex);
5419
5420         return 0;
5421 }
5422
5423 static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
5424                                u16 *allocated_size, bool is_alloc)
5425 {
5426         struct hclge_umv_spc_alc_cmd *req;
5427         struct hclge_desc desc;
5428         int ret;
5429
5430         req = (struct hclge_umv_spc_alc_cmd *)desc.data;
5431         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false);
5432         hnae3_set_bit(req->allocate, HCLGE_UMV_SPC_ALC_B, !is_alloc);
5433         req->space_size = cpu_to_le32(space_size);
5434
5435         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5436         if (ret) {
5437                 dev_err(&hdev->pdev->dev,
5438                         "%s umv space failed for cmd_send, ret =%d\n",
5439                         is_alloc ? "allocate" : "free", ret);
5440                 return ret;
5441         }
5442
5443         if (is_alloc && allocated_size)
5444                 *allocated_size = le32_to_cpu(desc.data[1]);
5445
5446         return 0;
5447 }
5448
5449 static void hclge_reset_umv_space(struct hclge_dev *hdev)
5450 {
5451         struct hclge_vport *vport;
5452         int i;
5453
5454         for (i = 0; i < hdev->num_alloc_vport; i++) {
5455                 vport = &hdev->vport[i];
5456                 vport->used_umv_num = 0;
5457         }
5458
5459         mutex_lock(&hdev->umv_mutex);
5460         hdev->share_umv_size = hdev->priv_umv_size +
5461                         hdev->max_umv_size % (hdev->num_req_vfs + 2);
5462         mutex_unlock(&hdev->umv_mutex);
5463 }
5464
5465 static bool hclge_is_umv_space_full(struct hclge_vport *vport)
5466 {
5467         struct hclge_dev *hdev = vport->back;
5468         bool is_full;
5469
5470         mutex_lock(&hdev->umv_mutex);
5471         is_full = (vport->used_umv_num >= hdev->priv_umv_size &&
5472                    hdev->share_umv_size == 0);
5473         mutex_unlock(&hdev->umv_mutex);
5474
5475         return is_full;
5476 }
5477
5478 static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free)
5479 {
5480         struct hclge_dev *hdev = vport->back;
5481
5482         mutex_lock(&hdev->umv_mutex);
5483         if (is_free) {
5484                 if (vport->used_umv_num > hdev->priv_umv_size)
5485                         hdev->share_umv_size++;
5486                 vport->used_umv_num--;
5487         } else {
5488                 if (vport->used_umv_num >= hdev->priv_umv_size)
5489                         hdev->share_umv_size--;
5490                 vport->used_umv_num++;
5491         }
5492         mutex_unlock(&hdev->umv_mutex);
5493 }
5494
5495 static int hclge_add_uc_addr(struct hnae3_handle *handle,
5496                              const unsigned char *addr)
5497 {
5498         struct hclge_vport *vport = hclge_get_vport(handle);
5499
5500         return hclge_add_uc_addr_common(vport, addr);
5501 }
5502
5503 int hclge_add_uc_addr_common(struct hclge_vport *vport,
5504                              const unsigned char *addr)
5505 {
5506         struct hclge_dev *hdev = vport->back;
5507         struct hclge_mac_vlan_tbl_entry_cmd req;
5508         struct hclge_desc desc;
5509         u16 egress_port = 0;
5510         int ret;
5511
5512         /* mac addr check */
5513         if (is_zero_ether_addr(addr) ||
5514             is_broadcast_ether_addr(addr) ||
5515             is_multicast_ether_addr(addr)) {
5516                 dev_err(&hdev->pdev->dev,
5517                         "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
5518                          addr,
5519                          is_zero_ether_addr(addr),
5520                          is_broadcast_ether_addr(addr),
5521                          is_multicast_ether_addr(addr));
5522                 return -EINVAL;
5523         }
5524
5525         memset(&req, 0, sizeof(req));
5526         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5527
5528         hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
5529                         HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
5530
5531         req.egress_port = cpu_to_le16(egress_port);
5532
5533         hclge_prepare_mac_addr(&req, addr);
5534
5535         /* Lookup the mac address in the mac_vlan table, and add
5536          * it if the entry is inexistent. Repeated unicast entry
5537          * is not allowed in the mac vlan table.
5538          */
5539         ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
5540         if (ret == -ENOENT) {
5541                 if (!hclge_is_umv_space_full(vport)) {
5542                         ret = hclge_add_mac_vlan_tbl(vport, &req, NULL);
5543                         if (!ret)
5544                                 hclge_update_umv_space(vport, false);
5545                         return ret;
5546                 }
5547
5548                 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n",
5549                         hdev->priv_umv_size);
5550
5551                 return -ENOSPC;
5552         }
5553
5554         /* check if we just hit the duplicate */
5555         if (!ret)
5556                 ret = -EINVAL;
5557
5558         dev_err(&hdev->pdev->dev,
5559                 "PF failed to add unicast entry(%pM) in the MAC table\n",
5560                 addr);
5561
5562         return ret;
5563 }
5564
5565 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
5566                             const unsigned char *addr)
5567 {
5568         struct hclge_vport *vport = hclge_get_vport(handle);
5569
5570         return hclge_rm_uc_addr_common(vport, addr);
5571 }
5572
5573 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
5574                             const unsigned char *addr)
5575 {
5576         struct hclge_dev *hdev = vport->back;
5577         struct hclge_mac_vlan_tbl_entry_cmd req;
5578         int ret;
5579
5580         /* mac addr check */
5581         if (is_zero_ether_addr(addr) ||
5582             is_broadcast_ether_addr(addr) ||
5583             is_multicast_ether_addr(addr)) {
5584                 dev_dbg(&hdev->pdev->dev,
5585                         "Remove mac err! invalid mac:%pM.\n",
5586                          addr);
5587                 return -EINVAL;
5588         }
5589
5590         memset(&req, 0, sizeof(req));
5591         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5592         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5593         hclge_prepare_mac_addr(&req, addr);
5594         ret = hclge_remove_mac_vlan_tbl(vport, &req);
5595         if (!ret)
5596                 hclge_update_umv_space(vport, true);
5597
5598         return ret;
5599 }
5600
5601 static int hclge_add_mc_addr(struct hnae3_handle *handle,
5602                              const unsigned char *addr)
5603 {
5604         struct hclge_vport *vport = hclge_get_vport(handle);
5605
5606         return hclge_add_mc_addr_common(vport, addr);
5607 }
5608
5609 int hclge_add_mc_addr_common(struct hclge_vport *vport,
5610                              const unsigned char *addr)
5611 {
5612         struct hclge_dev *hdev = vport->back;
5613         struct hclge_mac_vlan_tbl_entry_cmd req;
5614         struct hclge_desc desc[3];
5615         int status;
5616
5617         /* mac addr check */
5618         if (!is_multicast_ether_addr(addr)) {
5619                 dev_err(&hdev->pdev->dev,
5620                         "Add mc mac err! invalid mac:%pM.\n",
5621                          addr);
5622                 return -EINVAL;
5623         }
5624         memset(&req, 0, sizeof(req));
5625         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5626         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5627         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
5628         hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5629         hclge_prepare_mac_addr(&req, addr);
5630         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
5631         if (!status) {
5632                 /* This mac addr exist, update VFID for it */
5633                 hclge_update_desc_vfid(desc, vport->vport_id, false);
5634                 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5635         } else {
5636                 /* This mac addr do not exist, add new entry for it */
5637                 memset(desc[0].data, 0, sizeof(desc[0].data));
5638                 memset(desc[1].data, 0, sizeof(desc[0].data));
5639                 memset(desc[2].data, 0, sizeof(desc[0].data));
5640                 hclge_update_desc_vfid(desc, vport->vport_id, false);
5641                 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5642         }
5643
5644         if (status == -ENOSPC)
5645                 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n");
5646
5647         return status;
5648 }
5649
5650 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
5651                             const unsigned char *addr)
5652 {
5653         struct hclge_vport *vport = hclge_get_vport(handle);
5654
5655         return hclge_rm_mc_addr_common(vport, addr);
5656 }
5657
5658 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
5659                             const unsigned char *addr)
5660 {
5661         struct hclge_dev *hdev = vport->back;
5662         struct hclge_mac_vlan_tbl_entry_cmd req;
5663         enum hclge_cmd_status status;
5664         struct hclge_desc desc[3];
5665
5666         /* mac addr check */
5667         if (!is_multicast_ether_addr(addr)) {
5668                 dev_dbg(&hdev->pdev->dev,
5669                         "Remove mc mac err! invalid mac:%pM.\n",
5670                          addr);
5671                 return -EINVAL;
5672         }
5673
5674         memset(&req, 0, sizeof(req));
5675         hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5676         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5677         hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
5678         hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5679         hclge_prepare_mac_addr(&req, addr);
5680         status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
5681         if (!status) {
5682                 /* This mac addr exist, remove this handle's VFID for it */
5683                 hclge_update_desc_vfid(desc, vport->vport_id, true);
5684
5685                 if (hclge_is_all_function_id_zero(desc))
5686                         /* All the vfid is zero, so need to delete this entry */
5687                         status = hclge_remove_mac_vlan_tbl(vport, &req);
5688                 else
5689                         /* Not all the vfid is zero, update the vfid */
5690                         status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5691
5692         } else {
5693                 /* Maybe this mac address is in mta table, but it cannot be
5694                  * deleted here because an entry of mta represents an address
5695                  * range rather than a specific address. the delete action to
5696                  * all entries will take effect in update_mta_status called by
5697                  * hns3_nic_set_rx_mode.
5698                  */
5699                 status = 0;
5700         }
5701
5702         return status;
5703 }
5704
5705 static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
5706                                               u16 cmdq_resp, u8 resp_code)
5707 {
5708 #define HCLGE_ETHERTYPE_SUCCESS_ADD             0
5709 #define HCLGE_ETHERTYPE_ALREADY_ADD             1
5710 #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW        2
5711 #define HCLGE_ETHERTYPE_KEY_CONFLICT            3
5712
5713         int return_status;
5714
5715         if (cmdq_resp) {
5716                 dev_err(&hdev->pdev->dev,
5717                         "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
5718                         cmdq_resp);
5719                 return -EIO;
5720         }
5721
5722         switch (resp_code) {
5723         case HCLGE_ETHERTYPE_SUCCESS_ADD:
5724         case HCLGE_ETHERTYPE_ALREADY_ADD:
5725                 return_status = 0;
5726                 break;
5727         case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
5728                 dev_err(&hdev->pdev->dev,
5729                         "add mac ethertype failed for manager table overflow.\n");
5730                 return_status = -EIO;
5731                 break;
5732         case HCLGE_ETHERTYPE_KEY_CONFLICT:
5733                 dev_err(&hdev->pdev->dev,
5734                         "add mac ethertype failed for key conflict.\n");
5735                 return_status = -EIO;
5736                 break;
5737         default:
5738                 dev_err(&hdev->pdev->dev,
5739                         "add mac ethertype failed for undefined, code=%d.\n",
5740                         resp_code);
5741                 return_status = -EIO;
5742         }
5743
5744         return return_status;
5745 }
5746
5747 static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
5748                              const struct hclge_mac_mgr_tbl_entry_cmd *req)
5749 {
5750         struct hclge_desc desc;
5751         u8 resp_code;
5752         u16 retval;
5753         int ret;
5754
5755         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
5756         memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
5757
5758         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5759         if (ret) {
5760                 dev_err(&hdev->pdev->dev,
5761                         "add mac ethertype failed for cmd_send, ret =%d.\n",
5762                         ret);
5763                 return ret;
5764         }
5765
5766         resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5767         retval = le16_to_cpu(desc.retval);
5768
5769         return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
5770 }
5771
5772 static int init_mgr_tbl(struct hclge_dev *hdev)
5773 {
5774         int ret;
5775         int i;
5776
5777         for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
5778                 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
5779                 if (ret) {
5780                         dev_err(&hdev->pdev->dev,
5781                                 "add mac ethertype failed, ret =%d.\n",
5782                                 ret);
5783                         return ret;
5784                 }
5785         }
5786
5787         return 0;
5788 }
5789
5790 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
5791 {
5792         struct hclge_vport *vport = hclge_get_vport(handle);
5793         struct hclge_dev *hdev = vport->back;
5794
5795         ether_addr_copy(p, hdev->hw.mac.mac_addr);
5796 }
5797
5798 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
5799                               bool is_first)
5800 {
5801         const unsigned char *new_addr = (const unsigned char *)p;
5802         struct hclge_vport *vport = hclge_get_vport(handle);
5803         struct hclge_dev *hdev = vport->back;
5804         int ret;
5805
5806         /* mac addr check */
5807         if (is_zero_ether_addr(new_addr) ||
5808             is_broadcast_ether_addr(new_addr) ||
5809             is_multicast_ether_addr(new_addr)) {
5810                 dev_err(&hdev->pdev->dev,
5811                         "Change uc mac err! invalid mac:%p.\n",
5812                          new_addr);
5813                 return -EINVAL;
5814         }
5815
5816         if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
5817                 dev_warn(&hdev->pdev->dev,
5818                          "remove old uc mac address fail.\n");
5819
5820         ret = hclge_add_uc_addr(handle, new_addr);
5821         if (ret) {
5822                 dev_err(&hdev->pdev->dev,
5823                         "add uc mac address fail, ret =%d.\n",
5824                         ret);
5825
5826                 if (!is_first &&
5827                     hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
5828                         dev_err(&hdev->pdev->dev,
5829                                 "restore uc mac address fail.\n");
5830
5831                 return -EIO;
5832         }
5833
5834         ret = hclge_pause_addr_cfg(hdev, new_addr);
5835         if (ret) {
5836                 dev_err(&hdev->pdev->dev,
5837                         "configure mac pause address fail, ret =%d.\n",
5838                         ret);
5839                 return -EIO;
5840         }
5841
5842         ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
5843
5844         return 0;
5845 }
5846
5847 static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
5848                           int cmd)
5849 {
5850         struct hclge_vport *vport = hclge_get_vport(handle);
5851         struct hclge_dev *hdev = vport->back;
5852
5853         if (!hdev->hw.mac.phydev)
5854                 return -EOPNOTSUPP;
5855
5856         return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
5857 }
5858
5859 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
5860                                       u8 fe_type, bool filter_en)
5861 {
5862         struct hclge_vlan_filter_ctrl_cmd *req;
5863         struct hclge_desc desc;
5864         int ret;
5865
5866         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
5867
5868         req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
5869         req->vlan_type = vlan_type;
5870         req->vlan_fe = filter_en ? fe_type : 0;
5871
5872         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5873         if (ret)
5874                 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
5875                         ret);
5876
5877         return ret;
5878 }
5879
5880 #define HCLGE_FILTER_TYPE_VF            0
5881 #define HCLGE_FILTER_TYPE_PORT          1
5882 #define HCLGE_FILTER_FE_EGRESS_V1_B     BIT(0)
5883 #define HCLGE_FILTER_FE_NIC_INGRESS_B   BIT(0)
5884 #define HCLGE_FILTER_FE_NIC_EGRESS_B    BIT(1)
5885 #define HCLGE_FILTER_FE_ROCE_INGRESS_B  BIT(2)
5886 #define HCLGE_FILTER_FE_ROCE_EGRESS_B   BIT(3)
5887 #define HCLGE_FILTER_FE_EGRESS          (HCLGE_FILTER_FE_NIC_EGRESS_B \
5888                                         | HCLGE_FILTER_FE_ROCE_EGRESS_B)
5889 #define HCLGE_FILTER_FE_INGRESS         (HCLGE_FILTER_FE_NIC_INGRESS_B \
5890                                         | HCLGE_FILTER_FE_ROCE_INGRESS_B)
5891
5892 static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
5893 {
5894         struct hclge_vport *vport = hclge_get_vport(handle);
5895         struct hclge_dev *hdev = vport->back;
5896
5897         if (hdev->pdev->revision >= 0x21) {
5898                 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5899                                            HCLGE_FILTER_FE_EGRESS, enable);
5900                 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
5901                                            HCLGE_FILTER_FE_INGRESS, enable);
5902         } else {
5903                 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5904                                            HCLGE_FILTER_FE_EGRESS_V1_B, enable);
5905         }
5906         if (enable)
5907                 handle->netdev_flags |= HNAE3_VLAN_FLTR;
5908         else
5909                 handle->netdev_flags &= ~HNAE3_VLAN_FLTR;
5910 }
5911
5912 static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
5913                                     bool is_kill, u16 vlan, u8 qos,
5914                                     __be16 proto)
5915 {
5916 #define HCLGE_MAX_VF_BYTES  16
5917         struct hclge_vlan_filter_vf_cfg_cmd *req0;
5918         struct hclge_vlan_filter_vf_cfg_cmd *req1;
5919         struct hclge_desc desc[2];
5920         u8 vf_byte_val;
5921         u8 vf_byte_off;
5922         int ret;
5923
5924         hclge_cmd_setup_basic_desc(&desc[0],
5925                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
5926         hclge_cmd_setup_basic_desc(&desc[1],
5927                                    HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
5928
5929         desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5930
5931         vf_byte_off = vfid / 8;
5932         vf_byte_val = 1 << (vfid % 8);
5933
5934         req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
5935         req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
5936
5937         req0->vlan_id  = cpu_to_le16(vlan);
5938         req0->vlan_cfg = is_kill;
5939
5940         if (vf_byte_off < HCLGE_MAX_VF_BYTES)
5941                 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
5942         else
5943                 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
5944
5945         ret = hclge_cmd_send(&hdev->hw, desc, 2);
5946         if (ret) {
5947                 dev_err(&hdev->pdev->dev,
5948                         "Send vf vlan command fail, ret =%d.\n",
5949                         ret);
5950                 return ret;
5951         }
5952
5953         if (!is_kill) {
5954 #define HCLGE_VF_VLAN_NO_ENTRY  2
5955                 if (!req0->resp_code || req0->resp_code == 1)
5956                         return 0;
5957
5958                 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
5959                         dev_warn(&hdev->pdev->dev,
5960                                  "vf vlan table is full, vf vlan filter is disabled\n");
5961                         return 0;
5962                 }
5963
5964                 dev_err(&hdev->pdev->dev,
5965                         "Add vf vlan filter fail, ret =%d.\n",
5966                         req0->resp_code);
5967         } else {
5968 #define HCLGE_VF_VLAN_DEL_NO_FOUND      1
5969                 if (!req0->resp_code)
5970                         return 0;
5971
5972                 if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) {
5973                         dev_warn(&hdev->pdev->dev,
5974                                  "vlan %d filter is not in vf vlan table\n",
5975                                  vlan);
5976                         return 0;
5977                 }
5978
5979                 dev_err(&hdev->pdev->dev,
5980                         "Kill vf vlan filter fail, ret =%d.\n",
5981                         req0->resp_code);
5982         }
5983
5984         return -EIO;
5985 }
5986
5987 static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
5988                                       u16 vlan_id, bool is_kill)
5989 {
5990         struct hclge_vlan_filter_pf_cfg_cmd *req;
5991         struct hclge_desc desc;
5992         u8 vlan_offset_byte_val;
5993         u8 vlan_offset_byte;
5994         u8 vlan_offset_160;
5995         int ret;
5996
5997         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
5998
5999         vlan_offset_160 = vlan_id / 160;
6000         vlan_offset_byte = (vlan_id % 160) / 8;
6001         vlan_offset_byte_val = 1 << (vlan_id % 8);
6002
6003         req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
6004         req->vlan_offset = vlan_offset_160;
6005         req->vlan_cfg = is_kill;
6006         req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
6007
6008         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6009         if (ret)
6010                 dev_err(&hdev->pdev->dev,
6011                         "port vlan command, send fail, ret =%d.\n", ret);
6012         return ret;
6013 }
6014
6015 static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
6016                                     u16 vport_id, u16 vlan_id, u8 qos,
6017                                     bool is_kill)
6018 {
6019         u16 vport_idx, vport_num = 0;
6020         int ret;
6021
6022         if (is_kill && !vlan_id)
6023                 return 0;
6024
6025         ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
6026                                        0, proto);
6027         if (ret) {
6028                 dev_err(&hdev->pdev->dev,
6029                         "Set %d vport vlan filter config fail, ret =%d.\n",
6030                         vport_id, ret);
6031                 return ret;
6032         }
6033
6034         /* vlan 0 may be added twice when 8021q module is enabled */
6035         if (!is_kill && !vlan_id &&
6036             test_bit(vport_id, hdev->vlan_table[vlan_id]))
6037                 return 0;
6038
6039         if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
6040                 dev_err(&hdev->pdev->dev,
6041                         "Add port vlan failed, vport %d is already in vlan %d\n",
6042                         vport_id, vlan_id);
6043                 return -EINVAL;
6044         }
6045
6046         if (is_kill &&
6047             !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
6048                 dev_err(&hdev->pdev->dev,
6049                         "Delete port vlan failed, vport %d is not in vlan %d\n",
6050                         vport_id, vlan_id);
6051                 return -EINVAL;
6052         }
6053
6054         for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
6055                 vport_num++;
6056
6057         if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
6058                 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
6059                                                  is_kill);
6060
6061         return ret;
6062 }
6063
6064 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
6065                           u16 vlan_id, bool is_kill)
6066 {
6067         struct hclge_vport *vport = hclge_get_vport(handle);
6068         struct hclge_dev *hdev = vport->back;
6069
6070         return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
6071                                         0, is_kill);
6072 }
6073
6074 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
6075                                     u16 vlan, u8 qos, __be16 proto)
6076 {
6077         struct hclge_vport *vport = hclge_get_vport(handle);
6078         struct hclge_dev *hdev = vport->back;
6079
6080         if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
6081                 return -EINVAL;
6082         if (proto != htons(ETH_P_8021Q))
6083                 return -EPROTONOSUPPORT;
6084
6085         return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
6086 }
6087
6088 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
6089 {
6090         struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
6091         struct hclge_vport_vtag_tx_cfg_cmd *req;
6092         struct hclge_dev *hdev = vport->back;
6093         struct hclge_desc desc;
6094         int status;
6095
6096         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
6097
6098         req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
6099         req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
6100         req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
6101         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
6102                       vcfg->accept_tag1 ? 1 : 0);
6103         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
6104                       vcfg->accept_untag1 ? 1 : 0);
6105         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
6106                       vcfg->accept_tag2 ? 1 : 0);
6107         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
6108                       vcfg->accept_untag2 ? 1 : 0);
6109         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
6110                       vcfg->insert_tag1_en ? 1 : 0);
6111         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
6112                       vcfg->insert_tag2_en ? 1 : 0);
6113         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
6114
6115         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
6116         req->vf_bitmap[req->vf_offset] =
6117                 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
6118
6119         status = hclge_cmd_send(&hdev->hw, &desc, 1);
6120         if (status)
6121                 dev_err(&hdev->pdev->dev,
6122                         "Send port txvlan cfg command fail, ret =%d\n",
6123                         status);
6124
6125         return status;
6126 }
6127
6128 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
6129 {
6130         struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
6131         struct hclge_vport_vtag_rx_cfg_cmd *req;
6132         struct hclge_dev *hdev = vport->back;
6133         struct hclge_desc desc;
6134         int status;
6135
6136         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
6137
6138         req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
6139         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
6140                       vcfg->strip_tag1_en ? 1 : 0);
6141         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
6142                       vcfg->strip_tag2_en ? 1 : 0);
6143         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
6144                       vcfg->vlan1_vlan_prionly ? 1 : 0);
6145         hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
6146                       vcfg->vlan2_vlan_prionly ? 1 : 0);
6147
6148         req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
6149         req->vf_bitmap[req->vf_offset] =
6150                 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
6151
6152         status = hclge_cmd_send(&hdev->hw, &desc, 1);
6153         if (status)
6154                 dev_err(&hdev->pdev->dev,
6155                         "Send port rxvlan cfg command fail, ret =%d\n",
6156                         status);
6157
6158         return status;
6159 }
6160
6161 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
6162 {
6163         struct hclge_rx_vlan_type_cfg_cmd *rx_req;
6164         struct hclge_tx_vlan_type_cfg_cmd *tx_req;
6165         struct hclge_desc desc;
6166         int status;
6167
6168         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
6169         rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
6170         rx_req->ot_fst_vlan_type =
6171                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
6172         rx_req->ot_sec_vlan_type =
6173                 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
6174         rx_req->in_fst_vlan_type =
6175                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
6176         rx_req->in_sec_vlan_type =
6177                 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
6178
6179         status = hclge_cmd_send(&hdev->hw, &desc, 1);
6180         if (status) {
6181                 dev_err(&hdev->pdev->dev,
6182                         "Send rxvlan protocol type command fail, ret =%d\n",
6183                         status);
6184                 return status;
6185         }
6186
6187         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
6188
6189         tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data;
6190         tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
6191         tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
6192
6193         status = hclge_cmd_send(&hdev->hw, &desc, 1);
6194         if (status)
6195                 dev_err(&hdev->pdev->dev,
6196                         "Send txvlan protocol type command fail, ret =%d\n",
6197                         status);
6198
6199         return status;
6200 }
6201
6202 static int hclge_init_vlan_config(struct hclge_dev *hdev)
6203 {
6204 #define HCLGE_DEF_VLAN_TYPE             0x8100
6205
6206         struct hnae3_handle *handle = &hdev->vport[0].nic;
6207         struct hclge_vport *vport;
6208         int ret;
6209         int i;
6210
6211         if (hdev->pdev->revision >= 0x21) {
6212                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6213                                                  HCLGE_FILTER_FE_EGRESS, true);
6214                 if (ret)
6215                         return ret;
6216
6217                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
6218                                                  HCLGE_FILTER_FE_INGRESS, true);
6219                 if (ret)
6220                         return ret;
6221         } else {
6222                 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6223                                                  HCLGE_FILTER_FE_EGRESS_V1_B,
6224                                                  true);
6225                 if (ret)
6226                         return ret;
6227         }
6228
6229         handle->netdev_flags |= HNAE3_VLAN_FLTR;
6230
6231         hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
6232         hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
6233         hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
6234         hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
6235         hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
6236         hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
6237
6238         ret = hclge_set_vlan_protocol_type(hdev);
6239         if (ret)
6240                 return ret;
6241
6242         for (i = 0; i < hdev->num_alloc_vport; i++) {
6243                 vport = &hdev->vport[i];
6244                 vport->txvlan_cfg.accept_tag1 = true;
6245                 vport->txvlan_cfg.accept_untag1 = true;
6246
6247                 /* accept_tag2 and accept_untag2 are not supported on
6248                  * pdev revision(0x20), new revision support them. The
6249                  * value of this two fields will not return error when driver
6250                  * send command to fireware in revision(0x20).
6251                  * This two fields can not configured by user.
6252                  */
6253                 vport->txvlan_cfg.accept_tag2 = true;
6254                 vport->txvlan_cfg.accept_untag2 = true;
6255
6256                 vport->txvlan_cfg.insert_tag1_en = false;
6257                 vport->txvlan_cfg.insert_tag2_en = false;
6258                 vport->txvlan_cfg.default_tag1 = 0;
6259                 vport->txvlan_cfg.default_tag2 = 0;
6260
6261                 ret = hclge_set_vlan_tx_offload_cfg(vport);
6262                 if (ret)
6263                         return ret;
6264
6265                 vport->rxvlan_cfg.strip_tag1_en = false;
6266                 vport->rxvlan_cfg.strip_tag2_en = true;
6267                 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
6268                 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
6269
6270                 ret = hclge_set_vlan_rx_offload_cfg(vport);
6271                 if (ret)
6272                         return ret;
6273         }
6274
6275         return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
6276 }
6277
6278 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
6279 {
6280         struct hclge_vport *vport = hclge_get_vport(handle);
6281
6282         vport->rxvlan_cfg.strip_tag1_en = false;
6283         vport->rxvlan_cfg.strip_tag2_en = enable;
6284         vport->rxvlan_cfg.vlan1_vlan_prionly = false;
6285         vport->rxvlan_cfg.vlan2_vlan_prionly = false;
6286
6287         return hclge_set_vlan_rx_offload_cfg(vport);
6288 }
6289
6290 static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
6291 {
6292         struct hclge_config_max_frm_size_cmd *req;
6293         struct hclge_desc desc;
6294         int max_frm_size;
6295         int ret;
6296
6297         max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
6298
6299         if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
6300             max_frm_size > HCLGE_MAC_MAX_FRAME)
6301                 return -EINVAL;
6302
6303         max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
6304
6305         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
6306
6307         req = (struct hclge_config_max_frm_size_cmd *)desc.data;
6308         req->max_frm_size = cpu_to_le16(max_frm_size);
6309         req->min_frm_size = HCLGE_MAC_MIN_FRAME;
6310
6311         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6312         if (ret)
6313                 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
6314         else
6315                 hdev->mps = max_frm_size;
6316
6317         return ret;
6318 }
6319
6320 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
6321 {
6322         struct hclge_vport *vport = hclge_get_vport(handle);
6323         struct hclge_dev *hdev = vport->back;
6324         int ret;
6325
6326         ret = hclge_set_mac_mtu(hdev, new_mtu);
6327         if (ret) {
6328                 dev_err(&hdev->pdev->dev,
6329                         "Change mtu fail, ret =%d\n", ret);
6330                 return ret;
6331         }
6332
6333         ret = hclge_buffer_alloc(hdev);
6334         if (ret)
6335                 dev_err(&hdev->pdev->dev,
6336                         "Allocate buffer fail, ret =%d\n", ret);
6337
6338         return ret;
6339 }
6340
6341 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
6342                                     bool enable)
6343 {
6344         struct hclge_reset_tqp_queue_cmd *req;
6345         struct hclge_desc desc;
6346         int ret;
6347
6348         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
6349
6350         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
6351         req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
6352         hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
6353
6354         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6355         if (ret) {
6356                 dev_err(&hdev->pdev->dev,
6357                         "Send tqp reset cmd error, status =%d\n", ret);
6358                 return ret;
6359         }
6360
6361         return 0;
6362 }
6363
6364 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
6365 {
6366         struct hclge_reset_tqp_queue_cmd *req;
6367         struct hclge_desc desc;
6368         int ret;
6369
6370         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
6371
6372         req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
6373         req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
6374
6375         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6376         if (ret) {
6377                 dev_err(&hdev->pdev->dev,
6378                         "Get reset status error, status =%d\n", ret);
6379                 return ret;
6380         }
6381
6382         return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
6383 }
6384
6385 static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
6386                                           u16 queue_id)
6387 {
6388         struct hnae3_queue *queue;
6389         struct hclge_tqp *tqp;
6390
6391         queue = handle->kinfo.tqp[queue_id];
6392         tqp = container_of(queue, struct hclge_tqp, q);
6393
6394         return tqp->index;
6395 }
6396
6397 int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
6398 {
6399         struct hclge_vport *vport = hclge_get_vport(handle);
6400         struct hclge_dev *hdev = vport->back;
6401         int reset_try_times = 0;
6402         int reset_status;
6403         u16 queue_gid;
6404         int ret = 0;
6405
6406         queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
6407
6408         ret = hclge_tqp_enable(hdev, queue_id, 0, false);
6409         if (ret) {
6410                 dev_err(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
6411                 return ret;
6412         }
6413
6414         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
6415         if (ret) {
6416                 dev_err(&hdev->pdev->dev,
6417                         "Send reset tqp cmd fail, ret = %d\n", ret);
6418                 return ret;
6419         }
6420
6421         reset_try_times = 0;
6422         while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
6423                 /* Wait for tqp hw reset */
6424                 msleep(20);
6425                 reset_status = hclge_get_reset_status(hdev, queue_gid);
6426                 if (reset_status)
6427                         break;
6428         }
6429
6430         if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
6431                 dev_err(&hdev->pdev->dev, "Reset TQP fail\n");
6432                 return ret;
6433         }
6434
6435         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
6436         if (ret)
6437                 dev_err(&hdev->pdev->dev,
6438                         "Deassert the soft reset fail, ret = %d\n", ret);
6439
6440         return ret;
6441 }
6442
6443 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
6444 {
6445         struct hclge_dev *hdev = vport->back;
6446         int reset_try_times = 0;
6447         int reset_status;
6448         u16 queue_gid;
6449         int ret;
6450
6451         queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
6452
6453         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
6454         if (ret) {
6455                 dev_warn(&hdev->pdev->dev,
6456                          "Send reset tqp cmd fail, ret = %d\n", ret);
6457                 return;
6458         }
6459
6460         reset_try_times = 0;
6461         while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
6462                 /* Wait for tqp hw reset */
6463                 msleep(20);
6464                 reset_status = hclge_get_reset_status(hdev, queue_gid);
6465                 if (reset_status)
6466                         break;
6467         }
6468
6469         if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
6470                 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
6471                 return;
6472         }
6473
6474         ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
6475         if (ret)
6476                 dev_warn(&hdev->pdev->dev,
6477                          "Deassert the soft reset fail, ret = %d\n", ret);
6478 }
6479
6480 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
6481 {
6482         struct hclge_vport *vport = hclge_get_vport(handle);
6483         struct hclge_dev *hdev = vport->back;
6484
6485         return hdev->fw_version;
6486 }
6487
6488 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
6489 {
6490         struct phy_device *phydev = hdev->hw.mac.phydev;
6491
6492         if (!phydev)
6493                 return;
6494
6495         phy_set_asym_pause(phydev, rx_en, tx_en);
6496 }
6497
6498 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
6499 {
6500         int ret;
6501
6502         if (rx_en && tx_en)
6503                 hdev->fc_mode_last_time = HCLGE_FC_FULL;
6504         else if (rx_en && !tx_en)
6505                 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
6506         else if (!rx_en && tx_en)
6507                 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
6508         else
6509                 hdev->fc_mode_last_time = HCLGE_FC_NONE;
6510
6511         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
6512                 return 0;
6513
6514         ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
6515         if (ret) {
6516                 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
6517                         ret);
6518                 return ret;
6519         }
6520
6521         hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
6522
6523         return 0;
6524 }
6525
6526 int hclge_cfg_flowctrl(struct hclge_dev *hdev)
6527 {
6528         struct phy_device *phydev = hdev->hw.mac.phydev;
6529         u16 remote_advertising = 0;
6530         u16 local_advertising = 0;
6531         u32 rx_pause, tx_pause;
6532         u8 flowctl;
6533
6534         if (!phydev->link || !phydev->autoneg)
6535                 return 0;
6536
6537         local_advertising = ethtool_adv_to_lcl_adv_t(phydev->advertising);
6538
6539         if (phydev->pause)
6540                 remote_advertising = LPA_PAUSE_CAP;
6541
6542         if (phydev->asym_pause)
6543                 remote_advertising |= LPA_PAUSE_ASYM;
6544
6545         flowctl = mii_resolve_flowctrl_fdx(local_advertising,
6546                                            remote_advertising);
6547         tx_pause = flowctl & FLOW_CTRL_TX;
6548         rx_pause = flowctl & FLOW_CTRL_RX;
6549
6550         if (phydev->duplex == HCLGE_MAC_HALF) {
6551                 tx_pause = 0;
6552                 rx_pause = 0;
6553         }
6554
6555         return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
6556 }
6557
6558 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
6559                                  u32 *rx_en, u32 *tx_en)
6560 {
6561         struct hclge_vport *vport = hclge_get_vport(handle);
6562         struct hclge_dev *hdev = vport->back;
6563
6564         *auto_neg = hclge_get_autoneg(handle);
6565
6566         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
6567                 *rx_en = 0;
6568                 *tx_en = 0;
6569                 return;
6570         }
6571
6572         if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
6573                 *rx_en = 1;
6574                 *tx_en = 0;
6575         } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
6576                 *tx_en = 1;
6577                 *rx_en = 0;
6578         } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
6579                 *rx_en = 1;
6580                 *tx_en = 1;
6581         } else {
6582                 *rx_en = 0;
6583                 *tx_en = 0;
6584         }
6585 }
6586
6587 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
6588                                 u32 rx_en, u32 tx_en)
6589 {
6590         struct hclge_vport *vport = hclge_get_vport(handle);
6591         struct hclge_dev *hdev = vport->back;
6592         struct phy_device *phydev = hdev->hw.mac.phydev;
6593         u32 fc_autoneg;
6594
6595         fc_autoneg = hclge_get_autoneg(handle);
6596         if (auto_neg != fc_autoneg) {
6597                 dev_info(&hdev->pdev->dev,
6598                          "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
6599                 return -EOPNOTSUPP;
6600         }
6601
6602         if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
6603                 dev_info(&hdev->pdev->dev,
6604                          "Priority flow control enabled. Cannot set link flow control.\n");
6605                 return -EOPNOTSUPP;
6606         }
6607
6608         hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
6609
6610         if (!fc_autoneg)
6611                 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
6612
6613         /* Only support flow control negotiation for netdev with
6614          * phy attached for now.
6615          */
6616         if (!phydev)
6617                 return -EOPNOTSUPP;
6618
6619         return phy_start_aneg(phydev);
6620 }
6621
6622 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
6623                                           u8 *auto_neg, u32 *speed, u8 *duplex)
6624 {
6625         struct hclge_vport *vport = hclge_get_vport(handle);
6626         struct hclge_dev *hdev = vport->back;
6627
6628         if (speed)
6629                 *speed = hdev->hw.mac.speed;
6630         if (duplex)
6631                 *duplex = hdev->hw.mac.duplex;
6632         if (auto_neg)
6633                 *auto_neg = hdev->hw.mac.autoneg;
6634 }
6635
6636 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
6637 {
6638         struct hclge_vport *vport = hclge_get_vport(handle);
6639         struct hclge_dev *hdev = vport->back;
6640
6641         if (media_type)
6642                 *media_type = hdev->hw.mac.media_type;
6643 }
6644
6645 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
6646                                 u8 *tp_mdix_ctrl, u8 *tp_mdix)
6647 {
6648         struct hclge_vport *vport = hclge_get_vport(handle);
6649         struct hclge_dev *hdev = vport->back;
6650         struct phy_device *phydev = hdev->hw.mac.phydev;
6651         int mdix_ctrl, mdix, retval, is_resolved;
6652
6653         if (!phydev) {
6654                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
6655                 *tp_mdix = ETH_TP_MDI_INVALID;
6656                 return;
6657         }
6658
6659         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
6660
6661         retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
6662         mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
6663                                     HCLGE_PHY_MDIX_CTRL_S);
6664
6665         retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
6666         mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
6667         is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
6668
6669         phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
6670
6671         switch (mdix_ctrl) {
6672         case 0x0:
6673                 *tp_mdix_ctrl = ETH_TP_MDI;
6674                 break;
6675         case 0x1:
6676                 *tp_mdix_ctrl = ETH_TP_MDI_X;
6677                 break;
6678         case 0x3:
6679                 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
6680                 break;
6681         default:
6682                 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
6683                 break;
6684         }
6685
6686         if (!is_resolved)
6687                 *tp_mdix = ETH_TP_MDI_INVALID;
6688         else if (mdix)
6689                 *tp_mdix = ETH_TP_MDI_X;
6690         else
6691                 *tp_mdix = ETH_TP_MDI;
6692 }
6693
6694 static int hclge_init_instance_hw(struct hclge_dev *hdev)
6695 {
6696         return hclge_mac_connect_phy(hdev);
6697 }
6698
6699 static void hclge_uninit_instance_hw(struct hclge_dev *hdev)
6700 {
6701         hclge_mac_disconnect_phy(hdev);
6702 }
6703
6704 static int hclge_init_client_instance(struct hnae3_client *client,
6705                                       struct hnae3_ae_dev *ae_dev)
6706 {
6707         struct hclge_dev *hdev = ae_dev->priv;
6708         struct hclge_vport *vport;
6709         int i, ret;
6710
6711         for (i = 0; i <  hdev->num_vmdq_vport + 1; i++) {
6712                 vport = &hdev->vport[i];
6713
6714                 switch (client->type) {
6715                 case HNAE3_CLIENT_KNIC:
6716
6717                         hdev->nic_client = client;
6718                         vport->nic.client = client;
6719                         ret = client->ops->init_instance(&vport->nic);
6720                         if (ret)
6721                                 goto clear_nic;
6722
6723                         ret = hclge_init_instance_hw(hdev);
6724                         if (ret) {
6725                                 client->ops->uninit_instance(&vport->nic,
6726                                                              0);
6727                                 goto clear_nic;
6728                         }
6729
6730                         hnae3_set_client_init_flag(client, ae_dev, 1);
6731
6732                         if (hdev->roce_client &&
6733                             hnae3_dev_roce_supported(hdev)) {
6734                                 struct hnae3_client *rc = hdev->roce_client;
6735
6736                                 ret = hclge_init_roce_base_info(vport);
6737                                 if (ret)
6738                                         goto clear_roce;
6739
6740                                 ret = rc->ops->init_instance(&vport->roce);
6741                                 if (ret)
6742                                         goto clear_roce;
6743
6744                                 hnae3_set_client_init_flag(hdev->roce_client,
6745                                                            ae_dev, 1);
6746                         }
6747
6748                         break;
6749                 case HNAE3_CLIENT_UNIC:
6750                         hdev->nic_client = client;
6751                         vport->nic.client = client;
6752
6753                         ret = client->ops->init_instance(&vport->nic);
6754                         if (ret)
6755                                 goto clear_nic;
6756
6757                         hnae3_set_client_init_flag(client, ae_dev, 1);
6758
6759                         break;
6760                 case HNAE3_CLIENT_ROCE:
6761                         if (hnae3_dev_roce_supported(hdev)) {
6762                                 hdev->roce_client = client;
6763                                 vport->roce.client = client;
6764                         }
6765
6766                         if (hdev->roce_client && hdev->nic_client) {
6767                                 ret = hclge_init_roce_base_info(vport);
6768                                 if (ret)
6769                                         goto clear_roce;
6770
6771                                 ret = client->ops->init_instance(&vport->roce);
6772                                 if (ret)
6773                                         goto clear_roce;
6774
6775                                 hnae3_set_client_init_flag(client, ae_dev, 1);
6776                         }
6777
6778                         break;
6779                 default:
6780                         return -EINVAL;
6781                 }
6782         }
6783
6784         return 0;
6785
6786 clear_nic:
6787         hdev->nic_client = NULL;
6788         vport->nic.client = NULL;
6789         return ret;
6790 clear_roce:
6791         hdev->roce_client = NULL;
6792         vport->roce.client = NULL;
6793         return ret;
6794 }
6795
6796 static void hclge_uninit_client_instance(struct hnae3_client *client,
6797                                          struct hnae3_ae_dev *ae_dev)
6798 {
6799         struct hclge_dev *hdev = ae_dev->priv;
6800         struct hclge_vport *vport;
6801         int i;
6802
6803         for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
6804                 vport = &hdev->vport[i];
6805                 if (hdev->roce_client) {
6806                         hdev->roce_client->ops->uninit_instance(&vport->roce,
6807                                                                 0);
6808                         hdev->roce_client = NULL;
6809                         vport->roce.client = NULL;
6810                 }
6811                 if (client->type == HNAE3_CLIENT_ROCE)
6812                         return;
6813                 if (hdev->nic_client && client->ops->uninit_instance) {
6814                         hclge_uninit_instance_hw(hdev);
6815                         client->ops->uninit_instance(&vport->nic, 0);
6816                         hdev->nic_client = NULL;
6817                         vport->nic.client = NULL;
6818                 }
6819         }
6820 }
6821
6822 static int hclge_pci_init(struct hclge_dev *hdev)
6823 {
6824         struct pci_dev *pdev = hdev->pdev;
6825         struct hclge_hw *hw;
6826         int ret;
6827
6828         ret = pci_enable_device(pdev);
6829         if (ret) {
6830                 dev_err(&pdev->dev, "failed to enable PCI device\n");
6831                 return ret;
6832         }
6833
6834         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6835         if (ret) {
6836                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
6837                 if (ret) {
6838                         dev_err(&pdev->dev,
6839                                 "can't set consistent PCI DMA");
6840                         goto err_disable_device;
6841                 }
6842                 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
6843         }
6844
6845         ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
6846         if (ret) {
6847                 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
6848                 goto err_disable_device;
6849         }
6850
6851         pci_set_master(pdev);
6852         hw = &hdev->hw;
6853         hw->io_base = pcim_iomap(pdev, 2, 0);
6854         if (!hw->io_base) {
6855                 dev_err(&pdev->dev, "Can't map configuration register space\n");
6856                 ret = -ENOMEM;
6857                 goto err_clr_master;
6858         }
6859
6860         hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
6861
6862         return 0;
6863 err_clr_master:
6864         pci_clear_master(pdev);
6865         pci_release_regions(pdev);
6866 err_disable_device:
6867         pci_disable_device(pdev);
6868
6869         return ret;
6870 }
6871
6872 static void hclge_pci_uninit(struct hclge_dev *hdev)
6873 {
6874         struct pci_dev *pdev = hdev->pdev;
6875
6876         pcim_iounmap(pdev, hdev->hw.io_base);
6877         pci_free_irq_vectors(pdev);
6878         pci_clear_master(pdev);
6879         pci_release_mem_regions(pdev);
6880         pci_disable_device(pdev);
6881 }
6882
6883 static void hclge_state_init(struct hclge_dev *hdev)
6884 {
6885         set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
6886         set_bit(HCLGE_STATE_DOWN, &hdev->state);
6887         clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
6888         clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
6889         clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
6890         clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
6891 }
6892
6893 static void hclge_state_uninit(struct hclge_dev *hdev)
6894 {
6895         set_bit(HCLGE_STATE_DOWN, &hdev->state);
6896
6897         if (hdev->service_timer.function)
6898                 del_timer_sync(&hdev->service_timer);
6899         if (hdev->reset_timer.function)
6900                 del_timer_sync(&hdev->reset_timer);
6901         if (hdev->service_task.func)
6902                 cancel_work_sync(&hdev->service_task);
6903         if (hdev->rst_service_task.func)
6904                 cancel_work_sync(&hdev->rst_service_task);
6905         if (hdev->mbx_service_task.func)
6906                 cancel_work_sync(&hdev->mbx_service_task);
6907 }
6908
6909 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
6910 {
6911         struct pci_dev *pdev = ae_dev->pdev;
6912         struct hclge_dev *hdev;
6913         int ret;
6914
6915         hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
6916         if (!hdev) {
6917                 ret = -ENOMEM;
6918                 goto out;
6919         }
6920
6921         hdev->pdev = pdev;
6922         hdev->ae_dev = ae_dev;
6923         hdev->reset_type = HNAE3_NONE_RESET;
6924         hdev->reset_level = HNAE3_FUNC_RESET;
6925         ae_dev->priv = hdev;
6926
6927         ret = hclge_pci_init(hdev);
6928         if (ret) {
6929                 dev_err(&pdev->dev, "PCI init failed\n");
6930                 goto out;
6931         }
6932
6933         /* Firmware command queue initialize */
6934         ret = hclge_cmd_queue_init(hdev);
6935         if (ret) {
6936                 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
6937                 goto err_pci_uninit;
6938         }
6939
6940         /* Firmware command initialize */
6941         ret = hclge_cmd_init(hdev);
6942         if (ret)
6943                 goto err_cmd_uninit;
6944
6945         ret = hclge_get_cap(hdev);
6946         if (ret) {
6947                 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
6948                         ret);
6949                 goto err_cmd_uninit;
6950         }
6951
6952         ret = hclge_configure(hdev);
6953         if (ret) {
6954                 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
6955                 goto err_cmd_uninit;
6956         }
6957
6958         ret = hclge_init_msi(hdev);
6959         if (ret) {
6960                 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
6961                 goto err_cmd_uninit;
6962         }
6963
6964         ret = hclge_misc_irq_init(hdev);
6965         if (ret) {
6966                 dev_err(&pdev->dev,
6967                         "Misc IRQ(vector0) init error, ret = %d.\n",
6968                         ret);
6969                 goto err_msi_uninit;
6970         }
6971
6972         ret = hclge_alloc_tqps(hdev);
6973         if (ret) {
6974                 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
6975                 goto err_msi_irq_uninit;
6976         }
6977
6978         ret = hclge_alloc_vport(hdev);
6979         if (ret) {
6980                 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
6981                 goto err_msi_irq_uninit;
6982         }
6983
6984         ret = hclge_map_tqp(hdev);
6985         if (ret) {
6986                 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
6987                 goto err_msi_irq_uninit;
6988         }
6989
6990         if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
6991                 ret = hclge_mac_mdio_config(hdev);
6992                 if (ret) {
6993                         dev_err(&hdev->pdev->dev,
6994                                 "mdio config fail ret=%d\n", ret);
6995                         goto err_msi_irq_uninit;
6996                 }
6997         }
6998
6999         ret = hclge_init_umv_space(hdev);
7000         if (ret) {
7001                 dev_err(&pdev->dev, "umv space init error, ret=%d.\n", ret);
7002                 goto err_msi_irq_uninit;
7003         }
7004
7005         ret = hclge_mac_init(hdev);
7006         if (ret) {
7007                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
7008                 goto err_mdiobus_unreg;
7009         }
7010
7011         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
7012         if (ret) {
7013                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
7014                 goto err_mdiobus_unreg;
7015         }
7016
7017         ret = hclge_init_vlan_config(hdev);
7018         if (ret) {
7019                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
7020                 goto err_mdiobus_unreg;
7021         }
7022
7023         ret = hclge_tm_schd_init(hdev);
7024         if (ret) {
7025                 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
7026                 goto err_mdiobus_unreg;
7027         }
7028
7029         hclge_rss_init_cfg(hdev);
7030         ret = hclge_rss_init_hw(hdev);
7031         if (ret) {
7032                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
7033                 goto err_mdiobus_unreg;
7034         }
7035
7036         ret = init_mgr_tbl(hdev);
7037         if (ret) {
7038                 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
7039                 goto err_mdiobus_unreg;
7040         }
7041
7042         ret = hclge_init_fd_config(hdev);
7043         if (ret) {
7044                 dev_err(&pdev->dev,
7045                         "fd table init fail, ret=%d\n", ret);
7046                 goto err_mdiobus_unreg;
7047         }
7048
7049         ret = hclge_hw_error_set_state(hdev, true);
7050         if (ret) {
7051                 dev_err(&pdev->dev,
7052                         "hw error interrupts enable failed, ret =%d\n", ret);
7053                 goto err_mdiobus_unreg;
7054         }
7055
7056         hclge_dcb_ops_set(hdev);
7057
7058         timer_setup(&hdev->service_timer, hclge_service_timer, 0);
7059         timer_setup(&hdev->reset_timer, hclge_reset_timer, 0);
7060         INIT_WORK(&hdev->service_task, hclge_service_task);
7061         INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
7062         INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
7063
7064         hclge_clear_all_event_cause(hdev);
7065
7066         /* Enable MISC vector(vector0) */
7067         hclge_enable_vector(&hdev->misc_vector, true);
7068
7069         hclge_state_init(hdev);
7070         hdev->last_reset_time = jiffies;
7071
7072         pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
7073         return 0;
7074
7075 err_mdiobus_unreg:
7076         if (hdev->hw.mac.phydev)
7077                 mdiobus_unregister(hdev->hw.mac.mdio_bus);
7078 err_msi_irq_uninit:
7079         hclge_misc_irq_uninit(hdev);
7080 err_msi_uninit:
7081         pci_free_irq_vectors(pdev);
7082 err_cmd_uninit:
7083         hclge_destroy_cmd_queue(&hdev->hw);
7084 err_pci_uninit:
7085         pcim_iounmap(pdev, hdev->hw.io_base);
7086         pci_clear_master(pdev);
7087         pci_release_regions(pdev);
7088         pci_disable_device(pdev);
7089 out:
7090         return ret;
7091 }
7092
7093 static void hclge_stats_clear(struct hclge_dev *hdev)
7094 {
7095         memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
7096 }
7097
7098 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
7099 {
7100         struct hclge_dev *hdev = ae_dev->priv;
7101         struct pci_dev *pdev = ae_dev->pdev;
7102         int ret;
7103
7104         set_bit(HCLGE_STATE_DOWN, &hdev->state);
7105
7106         hclge_stats_clear(hdev);
7107         memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
7108
7109         ret = hclge_cmd_init(hdev);
7110         if (ret) {
7111                 dev_err(&pdev->dev, "Cmd queue init failed\n");
7112                 return ret;
7113         }
7114
7115         ret = hclge_get_cap(hdev);
7116         if (ret) {
7117                 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
7118                         ret);
7119                 return ret;
7120         }
7121
7122         ret = hclge_configure(hdev);
7123         if (ret) {
7124                 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
7125                 return ret;
7126         }
7127
7128         ret = hclge_map_tqp(hdev);
7129         if (ret) {
7130                 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
7131                 return ret;
7132         }
7133
7134         hclge_reset_umv_space(hdev);
7135
7136         ret = hclge_mac_init(hdev);
7137         if (ret) {
7138                 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
7139                 return ret;
7140         }
7141
7142         ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
7143         if (ret) {
7144                 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
7145                 return ret;
7146         }
7147
7148         ret = hclge_init_vlan_config(hdev);
7149         if (ret) {
7150                 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
7151                 return ret;
7152         }
7153
7154         ret = hclge_tm_init_hw(hdev);
7155         if (ret) {
7156                 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
7157                 return ret;
7158         }
7159
7160         ret = hclge_rss_init_hw(hdev);
7161         if (ret) {
7162                 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
7163                 return ret;
7164         }
7165
7166         ret = hclge_init_fd_config(hdev);
7167         if (ret) {
7168                 dev_err(&pdev->dev,
7169                         "fd table init fail, ret=%d\n", ret);
7170                 return ret;
7171         }
7172
7173         /* Re-enable the TM hw error interrupts because
7174          * they get disabled on core/global reset.
7175          */
7176         if (hclge_enable_tm_hw_error(hdev, true))
7177                 dev_err(&pdev->dev, "failed to enable TM hw error interrupts\n");
7178
7179         dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
7180                  HCLGE_DRIVER_NAME);
7181
7182         return 0;
7183 }
7184
7185 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
7186 {
7187         struct hclge_dev *hdev = ae_dev->priv;
7188         struct hclge_mac *mac = &hdev->hw.mac;
7189
7190         hclge_state_uninit(hdev);
7191
7192         if (mac->phydev)
7193                 mdiobus_unregister(mac->mdio_bus);
7194
7195         hclge_uninit_umv_space(hdev);
7196
7197         /* Disable MISC vector(vector0) */
7198         hclge_enable_vector(&hdev->misc_vector, false);
7199         synchronize_irq(hdev->misc_vector.vector_irq);
7200
7201         hclge_hw_error_set_state(hdev, false);
7202         hclge_destroy_cmd_queue(&hdev->hw);
7203         hclge_misc_irq_uninit(hdev);
7204         hclge_pci_uninit(hdev);
7205         ae_dev->priv = NULL;
7206 }
7207
7208 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
7209 {
7210         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
7211         struct hclge_vport *vport = hclge_get_vport(handle);
7212         struct hclge_dev *hdev = vport->back;
7213
7214         return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
7215 }
7216
7217 static void hclge_get_channels(struct hnae3_handle *handle,
7218                                struct ethtool_channels *ch)
7219 {
7220         struct hclge_vport *vport = hclge_get_vport(handle);
7221
7222         ch->max_combined = hclge_get_max_channels(handle);
7223         ch->other_count = 1;
7224         ch->max_other = 1;
7225         ch->combined_count = vport->alloc_tqps;
7226 }
7227
7228 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
7229                                         u16 *alloc_tqps, u16 *max_rss_size)
7230 {
7231         struct hclge_vport *vport = hclge_get_vport(handle);
7232         struct hclge_dev *hdev = vport->back;
7233
7234         *alloc_tqps = vport->alloc_tqps;
7235         *max_rss_size = hdev->rss_size_max;
7236 }
7237
7238 static void hclge_release_tqp(struct hclge_vport *vport)
7239 {
7240         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
7241         struct hclge_dev *hdev = vport->back;
7242         int i;
7243
7244         for (i = 0; i < kinfo->num_tqps; i++) {
7245                 struct hclge_tqp *tqp =
7246                         container_of(kinfo->tqp[i], struct hclge_tqp, q);
7247
7248                 tqp->q.handle = NULL;
7249                 tqp->q.tqp_index = 0;
7250                 tqp->alloced = false;
7251         }
7252
7253         devm_kfree(&hdev->pdev->dev, kinfo->tqp);
7254         kinfo->tqp = NULL;
7255 }
7256
7257 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
7258 {
7259         struct hclge_vport *vport = hclge_get_vport(handle);
7260         struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
7261         struct hclge_dev *hdev = vport->back;
7262         int cur_rss_size = kinfo->rss_size;
7263         int cur_tqps = kinfo->num_tqps;
7264         u16 tc_offset[HCLGE_MAX_TC_NUM];
7265         u16 tc_valid[HCLGE_MAX_TC_NUM];
7266         u16 tc_size[HCLGE_MAX_TC_NUM];
7267         u16 roundup_size;
7268         u32 *rss_indir;
7269         int ret, i;
7270
7271         /* Free old tqps, and reallocate with new tqp number when nic setup */
7272         hclge_release_tqp(vport);
7273
7274         ret = hclge_knic_setup(vport, new_tqps_num, kinfo->num_desc);
7275         if (ret) {
7276                 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
7277                 return ret;
7278         }
7279
7280         ret = hclge_map_tqp_to_vport(hdev, vport);
7281         if (ret) {
7282                 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
7283                 return ret;
7284         }
7285
7286         ret = hclge_tm_schd_init(hdev);
7287         if (ret) {
7288                 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
7289                 return ret;
7290         }
7291
7292         roundup_size = roundup_pow_of_two(kinfo->rss_size);
7293         roundup_size = ilog2(roundup_size);
7294         /* Set the RSS TC mode according to the new RSS size */
7295         for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
7296                 tc_valid[i] = 0;
7297
7298                 if (!(hdev->hw_tc_map & BIT(i)))
7299                         continue;
7300
7301                 tc_valid[i] = 1;
7302                 tc_size[i] = roundup_size;
7303                 tc_offset[i] = kinfo->rss_size * i;
7304         }
7305         ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
7306         if (ret)
7307                 return ret;
7308
7309         /* Reinitializes the rss indirect table according to the new RSS size */
7310         rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
7311         if (!rss_indir)
7312                 return -ENOMEM;
7313
7314         for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
7315                 rss_indir[i] = i % kinfo->rss_size;
7316
7317         ret = hclge_set_rss(handle, rss_indir, NULL, 0);
7318         if (ret)
7319                 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
7320                         ret);
7321
7322         kfree(rss_indir);
7323
7324         if (!ret)
7325                 dev_info(&hdev->pdev->dev,
7326                          "Channels changed, rss_size from %d to %d, tqps from %d to %d",
7327                          cur_rss_size, kinfo->rss_size,
7328                          cur_tqps, kinfo->rss_size * kinfo->num_tc);
7329
7330         return ret;
7331 }
7332
7333 static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
7334                               u32 *regs_num_64_bit)
7335 {
7336         struct hclge_desc desc;
7337         u32 total_num;
7338         int ret;
7339
7340         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
7341         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7342         if (ret) {
7343                 dev_err(&hdev->pdev->dev,
7344                         "Query register number cmd failed, ret = %d.\n", ret);
7345                 return ret;
7346         }
7347
7348         *regs_num_32_bit = le32_to_cpu(desc.data[0]);
7349         *regs_num_64_bit = le32_to_cpu(desc.data[1]);
7350
7351         total_num = *regs_num_32_bit + *regs_num_64_bit;
7352         if (!total_num)
7353                 return -EINVAL;
7354
7355         return 0;
7356 }
7357
7358 static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
7359                                  void *data)
7360 {
7361 #define HCLGE_32_BIT_REG_RTN_DATANUM 8
7362
7363         struct hclge_desc *desc;
7364         u32 *reg_val = data;
7365         __le32 *desc_data;
7366         int cmd_num;
7367         int i, k, n;
7368         int ret;
7369
7370         if (regs_num == 0)
7371                 return 0;
7372
7373         cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
7374         desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
7375         if (!desc)
7376                 return -ENOMEM;
7377
7378         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
7379         ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
7380         if (ret) {
7381                 dev_err(&hdev->pdev->dev,
7382                         "Query 32 bit register cmd failed, ret = %d.\n", ret);
7383                 kfree(desc);
7384                 return ret;
7385         }
7386
7387         for (i = 0; i < cmd_num; i++) {
7388                 if (i == 0) {
7389                         desc_data = (__le32 *)(&desc[i].data[0]);
7390                         n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
7391                 } else {
7392                         desc_data = (__le32 *)(&desc[i]);
7393                         n = HCLGE_32_BIT_REG_RTN_DATANUM;
7394                 }
7395                 for (k = 0; k < n; k++) {
7396                         *reg_val++ = le32_to_cpu(*desc_data++);
7397
7398                         regs_num--;
7399                         if (!regs_num)
7400                                 break;
7401                 }
7402         }
7403
7404         kfree(desc);
7405         return 0;
7406 }
7407
7408 static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
7409                                  void *data)
7410 {
7411 #define HCLGE_64_BIT_REG_RTN_DATANUM 4
7412
7413         struct hclge_desc *desc;
7414         u64 *reg_val = data;
7415         __le64 *desc_data;
7416         int cmd_num;
7417         int i, k, n;
7418         int ret;
7419
7420         if (regs_num == 0)
7421                 return 0;
7422
7423         cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
7424         desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
7425         if (!desc)
7426                 return -ENOMEM;
7427
7428         hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
7429         ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
7430         if (ret) {
7431                 dev_err(&hdev->pdev->dev,
7432                         "Query 64 bit register cmd failed, ret = %d.\n", ret);
7433                 kfree(desc);
7434                 return ret;
7435         }
7436
7437         for (i = 0; i < cmd_num; i++) {
7438                 if (i == 0) {
7439                         desc_data = (__le64 *)(&desc[i].data[0]);
7440                         n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
7441                 } else {
7442                         desc_data = (__le64 *)(&desc[i]);
7443                         n = HCLGE_64_BIT_REG_RTN_DATANUM;
7444                 }
7445                 for (k = 0; k < n; k++) {
7446                         *reg_val++ = le64_to_cpu(*desc_data++);
7447
7448                         regs_num--;
7449                         if (!regs_num)
7450                                 break;
7451                 }
7452         }
7453
7454         kfree(desc);
7455         return 0;
7456 }
7457
7458 static int hclge_get_regs_len(struct hnae3_handle *handle)
7459 {
7460         struct hclge_vport *vport = hclge_get_vport(handle);
7461         struct hclge_dev *hdev = vport->back;
7462         u32 regs_num_32_bit, regs_num_64_bit;
7463         int ret;
7464
7465         ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
7466         if (ret) {
7467                 dev_err(&hdev->pdev->dev,
7468                         "Get register number failed, ret = %d.\n", ret);
7469                 return -EOPNOTSUPP;
7470         }
7471
7472         return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
7473 }
7474
7475 static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
7476                            void *data)
7477 {
7478         struct hclge_vport *vport = hclge_get_vport(handle);
7479         struct hclge_dev *hdev = vport->back;
7480         u32 regs_num_32_bit, regs_num_64_bit;
7481         int ret;
7482
7483         *version = hdev->fw_version;
7484
7485         ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
7486         if (ret) {
7487                 dev_err(&hdev->pdev->dev,
7488                         "Get register number failed, ret = %d.\n", ret);
7489                 return;
7490         }
7491
7492         ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
7493         if (ret) {
7494                 dev_err(&hdev->pdev->dev,
7495                         "Get 32 bit register failed, ret = %d.\n", ret);
7496                 return;
7497         }
7498
7499         data = (u32 *)data + regs_num_32_bit;
7500         ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
7501                                     data);
7502         if (ret)
7503                 dev_err(&hdev->pdev->dev,
7504                         "Get 64 bit register failed, ret = %d.\n", ret);
7505 }
7506
7507 static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
7508 {
7509         struct hclge_set_led_state_cmd *req;
7510         struct hclge_desc desc;
7511         int ret;
7512
7513         hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
7514
7515         req = (struct hclge_set_led_state_cmd *)desc.data;
7516         hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
7517                         HCLGE_LED_LOCATE_STATE_S, locate_led_status);
7518
7519         ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7520         if (ret)
7521                 dev_err(&hdev->pdev->dev,
7522                         "Send set led state cmd error, ret =%d\n", ret);
7523
7524         return ret;
7525 }
7526
7527 enum hclge_led_status {
7528         HCLGE_LED_OFF,
7529         HCLGE_LED_ON,
7530         HCLGE_LED_NO_CHANGE = 0xFF,
7531 };
7532
7533 static int hclge_set_led_id(struct hnae3_handle *handle,
7534                             enum ethtool_phys_id_state status)
7535 {
7536         struct hclge_vport *vport = hclge_get_vport(handle);
7537         struct hclge_dev *hdev = vport->back;
7538
7539         switch (status) {
7540         case ETHTOOL_ID_ACTIVE:
7541                 return hclge_set_led_status(hdev, HCLGE_LED_ON);
7542         case ETHTOOL_ID_INACTIVE:
7543                 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
7544         default:
7545                 return -EINVAL;
7546         }
7547 }
7548
7549 static void hclge_get_link_mode(struct hnae3_handle *handle,
7550                                 unsigned long *supported,
7551                                 unsigned long *advertising)
7552 {
7553         unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
7554         struct hclge_vport *vport = hclge_get_vport(handle);
7555         struct hclge_dev *hdev = vport->back;
7556         unsigned int idx = 0;
7557
7558         for (; idx < size; idx++) {
7559                 supported[idx] = hdev->hw.mac.supported[idx];
7560                 advertising[idx] = hdev->hw.mac.advertising[idx];
7561         }
7562 }
7563
7564 static const struct hnae3_ae_ops hclge_ops = {
7565         .init_ae_dev = hclge_init_ae_dev,
7566         .uninit_ae_dev = hclge_uninit_ae_dev,
7567         .init_client_instance = hclge_init_client_instance,
7568         .uninit_client_instance = hclge_uninit_client_instance,
7569         .map_ring_to_vector = hclge_map_ring_to_vector,
7570         .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
7571         .get_vector = hclge_get_vector,
7572         .put_vector = hclge_put_vector,
7573         .set_promisc_mode = hclge_set_promisc_mode,
7574         .set_loopback = hclge_set_loopback,
7575         .start = hclge_ae_start,
7576         .stop = hclge_ae_stop,
7577         .get_status = hclge_get_status,
7578         .get_ksettings_an_result = hclge_get_ksettings_an_result,
7579         .update_speed_duplex_h = hclge_update_speed_duplex_h,
7580         .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
7581         .get_media_type = hclge_get_media_type,
7582         .get_rss_key_size = hclge_get_rss_key_size,
7583         .get_rss_indir_size = hclge_get_rss_indir_size,
7584         .get_rss = hclge_get_rss,
7585         .set_rss = hclge_set_rss,
7586         .set_rss_tuple = hclge_set_rss_tuple,
7587         .get_rss_tuple = hclge_get_rss_tuple,
7588         .get_tc_size = hclge_get_tc_size,
7589         .get_mac_addr = hclge_get_mac_addr,
7590         .set_mac_addr = hclge_set_mac_addr,
7591         .do_ioctl = hclge_do_ioctl,
7592         .add_uc_addr = hclge_add_uc_addr,
7593         .rm_uc_addr = hclge_rm_uc_addr,
7594         .add_mc_addr = hclge_add_mc_addr,
7595         .rm_mc_addr = hclge_rm_mc_addr,
7596         .set_autoneg = hclge_set_autoneg,
7597         .get_autoneg = hclge_get_autoneg,
7598         .get_pauseparam = hclge_get_pauseparam,
7599         .set_pauseparam = hclge_set_pauseparam,
7600         .set_mtu = hclge_set_mtu,
7601         .reset_queue = hclge_reset_tqp,
7602         .get_stats = hclge_get_stats,
7603         .update_stats = hclge_update_stats,
7604         .get_strings = hclge_get_strings,
7605         .get_sset_count = hclge_get_sset_count,
7606         .get_fw_version = hclge_get_fw_version,
7607         .get_mdix_mode = hclge_get_mdix_mode,
7608         .enable_vlan_filter = hclge_enable_vlan_filter,
7609         .set_vlan_filter = hclge_set_vlan_filter,
7610         .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
7611         .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
7612         .reset_event = hclge_reset_event,
7613         .set_default_reset_request = hclge_set_def_reset_request,
7614         .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
7615         .set_channels = hclge_set_channels,
7616         .get_channels = hclge_get_channels,
7617         .get_regs_len = hclge_get_regs_len,
7618         .get_regs = hclge_get_regs,
7619         .set_led_id = hclge_set_led_id,
7620         .get_link_mode = hclge_get_link_mode,
7621         .add_fd_entry = hclge_add_fd_entry,
7622         .del_fd_entry = hclge_del_fd_entry,
7623         .del_all_fd_entries = hclge_del_all_fd_entries,
7624         .get_fd_rule_cnt = hclge_get_fd_rule_cnt,
7625         .get_fd_rule_info = hclge_get_fd_rule_info,
7626         .get_fd_all_rules = hclge_get_all_rules,
7627         .restore_fd_rules = hclge_restore_fd_entries,
7628         .enable_fd = hclge_enable_fd,
7629         .process_hw_error = hclge_process_ras_hw_error,
7630         .get_hw_reset_stat = hclge_get_hw_reset_stat,
7631         .ae_dev_resetting = hclge_ae_dev_resetting,
7632         .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt,
7633 };
7634
7635 static struct hnae3_ae_algo ae_algo = {
7636         .ops = &hclge_ops,
7637         .pdev_id_table = ae_algo_pci_tbl,
7638 };
7639
7640 static int hclge_init(void)
7641 {
7642         pr_info("%s is initializing\n", HCLGE_NAME);
7643
7644         hnae3_register_ae_algo(&ae_algo);
7645
7646         return 0;
7647 }
7648
7649 static void hclge_exit(void)
7650 {
7651         hnae3_unregister_ae_algo(&ae_algo);
7652 }
7653 module_init(hclge_init);
7654 module_exit(hclge_exit);
7655
7656 MODULE_LICENSE("GPL");
7657 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
7658 MODULE_DESCRIPTION("HCLGE Driver");
7659 MODULE_VERSION(HCLGE_MOD_VERSION);