drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/etherdevice.h>
   5 #include <linux/iopoll.h>
   6 #include <net/rtnetlink.h>
   7 #include "hclgevf_cmd.h"
   8 #include "hclgevf_main.h"
   9 #include "hclge_mbx.h"
  10 #include "hnae3.h"
  11
  12 #define HCLGEVF_NAME    "hclgevf"
  13
  14 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev);
  15 static struct hnae3_ae_algo ae_algovf;
  16
  17 static const struct pci_device_id ae_algovf_pci_tbl[] = {
  18         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
  19         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0},
  20         /* required last entry */
  21         {0, }
  22 };
  23
  24 static const u8 hclgevf_hash_key[] = {
  25         0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
  26         0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
  27         0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
  28         0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
  29         0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA
  30 };
  31
  32 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
  33
  34 static const u32 cmdq_reg_addr_list[] = {HCLGEVF_CMDQ_TX_ADDR_L_REG,
  35                                          HCLGEVF_CMDQ_TX_ADDR_H_REG,
  36                                          HCLGEVF_CMDQ_TX_DEPTH_REG,
  37                                          HCLGEVF_CMDQ_TX_TAIL_REG,
  38                                          HCLGEVF_CMDQ_TX_HEAD_REG,
  39                                          HCLGEVF_CMDQ_RX_ADDR_L_REG,
  40                                          HCLGEVF_CMDQ_RX_ADDR_H_REG,
  41                                          HCLGEVF_CMDQ_RX_DEPTH_REG,
  42                                          HCLGEVF_CMDQ_RX_TAIL_REG,
  43                                          HCLGEVF_CMDQ_RX_HEAD_REG,
  44                                          HCLGEVF_VECTOR0_CMDQ_SRC_REG,
  45                                          HCLGEVF_CMDQ_INTR_STS_REG,
  46                                          HCLGEVF_CMDQ_INTR_EN_REG,
  47                                          HCLGEVF_CMDQ_INTR_GEN_REG};
  48
  49 static const u32 common_reg_addr_list[] = {HCLGEVF_MISC_VECTOR_REG_BASE,
  50                                            HCLGEVF_RST_ING,
  51                                            HCLGEVF_GRO_EN_REG};
  52
  53 static const u32 ring_reg_addr_list[] = {HCLGEVF_RING_RX_ADDR_L_REG,
  54                                          HCLGEVF_RING_RX_ADDR_H_REG,
  55                                          HCLGEVF_RING_RX_BD_NUM_REG,
  56                                          HCLGEVF_RING_RX_BD_LENGTH_REG,
  57                                          HCLGEVF_RING_RX_MERGE_EN_REG,
  58                                          HCLGEVF_RING_RX_TAIL_REG,
  59                                          HCLGEVF_RING_RX_HEAD_REG,
  60                                          HCLGEVF_RING_RX_FBD_NUM_REG,
  61                                          HCLGEVF_RING_RX_OFFSET_REG,
  62                                          HCLGEVF_RING_RX_FBD_OFFSET_REG,
  63                                          HCLGEVF_RING_RX_STASH_REG,
  64                                          HCLGEVF_RING_RX_BD_ERR_REG,
  65                                          HCLGEVF_RING_TX_ADDR_L_REG,
  66                                          HCLGEVF_RING_TX_ADDR_H_REG,
  67                                          HCLGEVF_RING_TX_BD_NUM_REG,
  68                                          HCLGEVF_RING_TX_PRIORITY_REG,
  69                                          HCLGEVF_RING_TX_TC_REG,
  70                                          HCLGEVF_RING_TX_MERGE_EN_REG,
  71                                          HCLGEVF_RING_TX_TAIL_REG,
  72                                          HCLGEVF_RING_TX_HEAD_REG,
  73                                          HCLGEVF_RING_TX_FBD_NUM_REG,
  74                                          HCLGEVF_RING_TX_OFFSET_REG,
  75                                          HCLGEVF_RING_TX_EBD_NUM_REG,
  76                                          HCLGEVF_RING_TX_EBD_OFFSET_REG,
  77                                          HCLGEVF_RING_TX_BD_ERR_REG,
  78                                          HCLGEVF_RING_EN_REG};
  79
  80 static const u32 tqp_intr_reg_addr_list[] = {HCLGEVF_TQP_INTR_CTRL_REG,
  81                                              HCLGEVF_TQP_INTR_GL0_REG,
  82                                              HCLGEVF_TQP_INTR_GL1_REG,
  83                                              HCLGEVF_TQP_INTR_GL2_REG,
  84                                              HCLGEVF_TQP_INTR_RL_REG};
  85
  86 static inline struct hclgevf_dev *hclgevf_ae_get_hdev(
  87         struct hnae3_handle *handle)
  88 {
  89         if (!handle->client)
  90                 return container_of(handle, struct hclgevf_dev, nic);
  91         else if (handle->client->type == HNAE3_CLIENT_ROCE)
  92                 return container_of(handle, struct hclgevf_dev, roce);
  93         else
  94                 return container_of(handle, struct hclgevf_dev, nic);
  95 }
  96
  97 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle)
  98 {
  99         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 100         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 101         struct hclgevf_desc desc;
 102         struct hclgevf_tqp *tqp;
 103         int status;
 104         int i;
 105
 106         for (i = 0; i < kinfo->num_tqps; i++) {
 107                 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
 108                 hclgevf_cmd_setup_basic_desc(&desc,
 109                                              HCLGEVF_OPC_QUERY_RX_STATUS,
 110                                              true);
 111
 112                 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
 113                 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 114                 if (status) {
 115                         dev_err(&hdev->pdev->dev,
 116                                 "Query tqp stat fail, status = %d,queue = %d\n",
 117                                 status, i);
 118                         return status;
 119                 }
 120                 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
 121                         le32_to_cpu(desc.data[1]);
 122
 123                 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS,
 124                                              true);
 125
 126                 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
 127                 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 128                 if (status) {
 129                         dev_err(&hdev->pdev->dev,
 130                                 "Query tqp stat fail, status = %d,queue = %d\n",
 131                                 status, i);
 132                         return status;
 133                 }
 134                 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
 135                         le32_to_cpu(desc.data[1]);
 136         }
 137
 138         return 0;
 139 }
 140
 141 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
 142 {
 143         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 144         struct hclgevf_tqp *tqp;
 145         u64 *buff = data;
 146         int i;
 147
 148         for (i = 0; i < kinfo->num_tqps; i++) {
 149                 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
 150                 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
 151         }
 152         for (i = 0; i < kinfo->num_tqps; i++) {
 153                 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
 154                 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
 155         }
 156
 157         return buff;
 158 }
 159
 160 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset)
 161 {
 162         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 163
 164         return kinfo->num_tqps * 2;
 165 }
 166
 167 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
 168 {
 169         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 170         u8 *buff = data;
 171         int i = 0;
 172
 173         for (i = 0; i < kinfo->num_tqps; i++) {
 174                 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
 175                                                        struct hclgevf_tqp, q);
 176                 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
 177                          tqp->index);
 178                 buff += ETH_GSTRING_LEN;
 179         }
 180
 181         for (i = 0; i < kinfo->num_tqps; i++) {
 182                 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
 183                                                        struct hclgevf_tqp, q);
 184                 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
 185                          tqp->index);
 186                 buff += ETH_GSTRING_LEN;
 187         }
 188
 189         return buff;
 190 }
 191
 192 static void hclgevf_update_stats(struct hnae3_handle *handle,
 193                                  struct net_device_stats *net_stats)
 194 {
 195         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 196         int status;
 197
 198         status = hclgevf_tqps_update_stats(handle);
 199         if (status)
 200                 dev_err(&hdev->pdev->dev,
 201                         "VF update of TQPS stats fail, status = %d.\n",
 202                         status);
 203 }
 204
 205 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset)
 206 {
 207         if (strset == ETH_SS_TEST)
 208                 return -EOPNOTSUPP;
 209         else if (strset == ETH_SS_STATS)
 210                 return hclgevf_tqps_get_sset_count(handle, strset);
 211
 212         return 0;
 213 }
 214
 215 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset,
 216                                 u8 *data)
 217 {
 218         u8 *p = (char *)data;
 219
 220         if (strset == ETH_SS_STATS)
 221                 p = hclgevf_tqps_get_strings(handle, p);
 222 }
 223
 224 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data)
 225 {
 226         hclgevf_tqps_get_stats(handle, data);
 227 }
 228
 229 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev)
 230 {
 231         u8 resp_msg;
 232         int status;
 233
 234         status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0,
 235                                       true, &resp_msg, sizeof(u8));
 236         if (status) {
 237                 dev_err(&hdev->pdev->dev,
 238                         "VF request to get TC info from PF failed %d",
 239                         status);
 240                 return status;
 241         }
 242
 243         hdev->hw_tc_map = resp_msg;
 244
 245         return 0;
 246 }
 247
 248 static int hclgevf_get_port_base_vlan_filter_state(struct hclgevf_dev *hdev)
 249 {
 250         struct hnae3_handle *nic = &hdev->nic;
 251         u8 resp_msg;
 252         int ret;
 253
 254         ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN,
 255                                    HCLGE_MBX_GET_PORT_BASE_VLAN_STATE,
 256                                    NULL, 0, true, &resp_msg, sizeof(u8));
 257         if (ret) {
 258                 dev_err(&hdev->pdev->dev,
 259                         "VF request to get port based vlan state failed %d",
 260                         ret);
 261                 return ret;
 262         }
 263
 264         nic->port_base_vlan_state = resp_msg;
 265
 266         return 0;
 267 }
 268
 269 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev)
 270 {
 271 #define HCLGEVF_TQPS_RSS_INFO_LEN       6
 272         u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN];
 273         int status;
 274
 275         status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0,
 276                                       true, resp_msg,
 277                                       HCLGEVF_TQPS_RSS_INFO_LEN);
 278         if (status) {
 279                 dev_err(&hdev->pdev->dev,
 280                         "VF request to get tqp info from PF failed %d",
 281                         status);
 282                 return status;
 283         }
 284
 285         memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16));
 286         memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16));
 287         memcpy(&hdev->rx_buf_len, &resp_msg[4], sizeof(u16));
 288
 289         return 0;
 290 }
 291
 292 static int hclgevf_get_queue_depth(struct hclgevf_dev *hdev)
 293 {
 294 #define HCLGEVF_TQPS_DEPTH_INFO_LEN     4
 295         u8 resp_msg[HCLGEVF_TQPS_DEPTH_INFO_LEN];
 296         int ret;
 297
 298         ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QDEPTH, 0, NULL, 0,
 299                                    true, resp_msg,
 300                                    HCLGEVF_TQPS_DEPTH_INFO_LEN);
 301         if (ret) {
 302                 dev_err(&hdev->pdev->dev,
 303                         "VF request to get tqp depth info from PF failed %d",
 304                         ret);
 305                 return ret;
 306         }
 307
 308         memcpy(&hdev->num_tx_desc, &resp_msg[0], sizeof(u16));
 309         memcpy(&hdev->num_rx_desc, &resp_msg[2], sizeof(u16));
 310
 311         return 0;
 312 }
 313
 314 static u16 hclgevf_get_qid_global(struct hnae3_handle *handle, u16 queue_id)
 315 {
 316         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 317         u8 msg_data[2], resp_data[2];
 318         u16 qid_in_pf = 0;
 319         int ret;
 320
 321         memcpy(&msg_data[0], &queue_id, sizeof(queue_id));
 322
 323         ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QID_IN_PF, 0, msg_data,
 324                                    2, true, resp_data, 2);
 325         if (!ret)
 326                 qid_in_pf = *(u16 *)resp_data;
 327
 328         return qid_in_pf;
 329 }
 330
 331 static int hclgevf_get_pf_media_type(struct hclgevf_dev *hdev)
 332 {
 333         u8 resp_msg;
 334         int ret;
 335
 336         ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_MEDIA_TYPE, 0, NULL, 0,
 337                                    true, &resp_msg, sizeof(resp_msg));
 338         if (ret) {
 339                 dev_err(&hdev->pdev->dev,
 340                         "VF request to get the pf port media type failed %d",
 341                         ret);
 342                 return ret;
 343         }
 344
 345         hdev->hw.mac.media_type = resp_msg;
 346
 347         return 0;
 348 }
 349
 350 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
 351 {
 352         struct hclgevf_tqp *tqp;
 353         int i;
 354
 355         hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
 356                                   sizeof(struct hclgevf_tqp), GFP_KERNEL);
 357         if (!hdev->htqp)
 358                 return -ENOMEM;
 359
 360         tqp = hdev->htqp;
 361
 362         for (i = 0; i < hdev->num_tqps; i++) {
 363                 tqp->dev = &hdev->pdev->dev;
 364                 tqp->index = i;
 365
 366                 tqp->q.ae_algo = &ae_algovf;
 367                 tqp->q.buf_size = hdev->rx_buf_len;
 368                 tqp->q.tx_desc_num = hdev->num_tx_desc;
 369                 tqp->q.rx_desc_num = hdev->num_rx_desc;
 370                 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET +
 371                         i * HCLGEVF_TQP_REG_SIZE;
 372
 373                 tqp++;
 374         }
 375
 376         return 0;
 377 }
 378
 379 static int hclgevf_knic_setup(struct hclgevf_dev *hdev)
 380 {
 381         struct hnae3_handle *nic = &hdev->nic;
 382         struct hnae3_knic_private_info *kinfo;
 383         u16 new_tqps = hdev->num_tqps;
 384         int i;
 385
 386         kinfo = &nic->kinfo;
 387         kinfo->num_tc = 0;
 388         kinfo->num_tx_desc = hdev->num_tx_desc;
 389         kinfo->num_rx_desc = hdev->num_rx_desc;
 390         kinfo->rx_buf_len = hdev->rx_buf_len;
 391         for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++)
 392                 if (hdev->hw_tc_map & BIT(i))
 393                         kinfo->num_tc++;
 394
 395         kinfo->rss_size
 396                 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc);
 397         new_tqps = kinfo->rss_size * kinfo->num_tc;
 398         kinfo->num_tqps = min(new_tqps, hdev->num_tqps);
 399
 400         kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
 401                                   sizeof(struct hnae3_queue *), GFP_KERNEL);
 402         if (!kinfo->tqp)
 403                 return -ENOMEM;
 404
 405         for (i = 0; i < kinfo->num_tqps; i++) {
 406                 hdev->htqp[i].q.handle = &hdev->nic;
 407                 hdev->htqp[i].q.tqp_index = i;
 408                 kinfo->tqp[i] = &hdev->htqp[i].q;
 409         }
 410
 411         return 0;
 412 }
 413
 414 static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
 415 {
 416         int status;
 417         u8 resp_msg;
 418
 419         status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL,
 420                                       0, false, &resp_msg, sizeof(u8));
 421         if (status)
 422                 dev_err(&hdev->pdev->dev,
 423                         "VF failed to fetch link status(%d) from PF", status);
 424 }
 425
 426 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
 427 {
 428         struct hnae3_handle *rhandle = &hdev->roce;
 429         struct hnae3_handle *handle = &hdev->nic;
 430         struct hnae3_client *rclient;
 431         struct hnae3_client *client;
 432
 433         client = handle->client;
 434         rclient = hdev->roce_client;
 435
 436         link_state =
 437                 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state;
 438
 439         if (link_state != hdev->hw.mac.link) {
 440                 client->ops->link_status_change(handle, !!link_state);
 441                 if (rclient && rclient->ops->link_status_change)
 442                         rclient->ops->link_status_change(rhandle, !!link_state);
 443                 hdev->hw.mac.link = link_state;
 444         }
 445 }
 446
 447 static void hclgevf_update_link_mode(struct hclgevf_dev *hdev)
 448 {
 449 #define HCLGEVF_ADVERTISING 0
 450 #define HCLGEVF_SUPPORTED   1
 451         u8 send_msg;
 452         u8 resp_msg;
 453
 454         send_msg = HCLGEVF_ADVERTISING;
 455         hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg,
 456                              sizeof(u8), false, &resp_msg, sizeof(u8));
 457         send_msg = HCLGEVF_SUPPORTED;
 458         hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_MODE, 0, &send_msg,
 459                              sizeof(u8), false, &resp_msg, sizeof(u8));
 460 }
 461
 462 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev)
 463 {
 464         struct hnae3_handle *nic = &hdev->nic;
 465         int ret;
 466
 467         nic->ae_algo = &ae_algovf;
 468         nic->pdev = hdev->pdev;
 469         nic->numa_node_mask = hdev->numa_node_mask;
 470         nic->flags |= HNAE3_SUPPORT_VF;
 471
 472         if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) {
 473                 dev_err(&hdev->pdev->dev, "unsupported device type %d\n",
 474                         hdev->ae_dev->dev_type);
 475                 return -EINVAL;
 476         }
 477
 478         ret = hclgevf_knic_setup(hdev);
 479         if (ret)
 480                 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n",
 481                         ret);
 482         return ret;
 483 }
 484
 485 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id)
 486 {
 487         if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) {
 488                 dev_warn(&hdev->pdev->dev,
 489                          "vector(vector_id %d) has been freed.\n", vector_id);
 490                 return;
 491         }
 492
 493         hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT;
 494         hdev->num_msi_left += 1;
 495         hdev->num_msi_used -= 1;
 496 }
 497
 498 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,
 499                               struct hnae3_vector_info *vector_info)
 500 {
 501         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 502         struct hnae3_vector_info *vector = vector_info;
 503         int alloc = 0;
 504         int i, j;
 505
 506         vector_num = min(hdev->num_msi_left, vector_num);
 507
 508         for (j = 0; j < vector_num; j++) {
 509                 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {
 510                         if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {
 511                                 vector->vector = pci_irq_vector(hdev->pdev, i);
 512                                 vector->io_addr = hdev->hw.io_base +
 513                                         HCLGEVF_VECTOR_REG_BASE +
 514                                         (i - 1) * HCLGEVF_VECTOR_REG_OFFSET;
 515                                 hdev->vector_status[i] = 0;
 516                                 hdev->vector_irq[i] = vector->vector;
 517
 518                                 vector++;
 519                                 alloc++;
 520
 521                                 break;
 522                         }
 523                 }
 524         }
 525         hdev->num_msi_left -= alloc;
 526         hdev->num_msi_used += alloc;
 527
 528         return alloc;
 529 }
 530
 531 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector)
 532 {
 533         int i;
 534
 535         for (i = 0; i < hdev->num_msi; i++)
 536                 if (vector == hdev->vector_irq[i])
 537                         return i;
 538
 539         return -EINVAL;
 540 }
 541
 542 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev,
 543                                     const u8 hfunc, const u8 *key)
 544 {
 545         struct hclgevf_rss_config_cmd *req;
 546         struct hclgevf_desc desc;
 547         int key_offset;
 548         int key_size;
 549         int ret;
 550
 551         req = (struct hclgevf_rss_config_cmd *)desc.data;
 552
 553         for (key_offset = 0; key_offset < 3; key_offset++) {
 554                 hclgevf_cmd_setup_basic_desc(&desc,
 555                                              HCLGEVF_OPC_RSS_GENERIC_CONFIG,
 556                                              false);
 557
 558                 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK);
 559                 req->hash_config |=
 560                         (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B);
 561
 562                 if (key_offset == 2)
 563                         key_size =
 564                         HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2;
 565                 else
 566                         key_size = HCLGEVF_RSS_HASH_KEY_NUM;
 567
 568                 memcpy(req->hash_key,
 569                        key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size);
 570
 571                 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 572                 if (ret) {
 573                         dev_err(&hdev->pdev->dev,
 574                                 "Configure RSS config fail, status = %d\n",
 575                                 ret);
 576                         return ret;
 577                 }
 578         }
 579
 580         return 0;
 581 }
 582
 583 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle)
 584 {
 585         return HCLGEVF_RSS_KEY_SIZE;
 586 }
 587
 588 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle)
 589 {
 590         return HCLGEVF_RSS_IND_TBL_SIZE;
 591 }
 592
 593 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev)
 594 {
 595         const u8 *indir = hdev->rss_cfg.rss_indirection_tbl;
 596         struct hclgevf_rss_indirection_table_cmd *req;
 597         struct hclgevf_desc desc;
 598         int status;
 599         int i, j;
 600
 601         req = (struct hclgevf_rss_indirection_table_cmd *)desc.data;
 602
 603         for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) {
 604                 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE,
 605                                              false);
 606                 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE;
 607                 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK;
 608                 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++)
 609                         req->rss_result[j] =
 610                                 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j];
 611
 612                 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 613                 if (status) {
 614                         dev_err(&hdev->pdev->dev,
 615                                 "VF failed(=%d) to set RSS indirection table\n",
 616                                 status);
 617                         return status;
 618                 }
 619         }
 620
 621         return 0;
 622 }
 623
 624 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev,  u16 rss_size)
 625 {
 626         struct hclgevf_rss_tc_mode_cmd *req;
 627         u16 tc_offset[HCLGEVF_MAX_TC_NUM];
 628         u16 tc_valid[HCLGEVF_MAX_TC_NUM];
 629         u16 tc_size[HCLGEVF_MAX_TC_NUM];
 630         struct hclgevf_desc desc;
 631         u16 roundup_size;
 632         int status;
 633         int i;
 634
 635         req = (struct hclgevf_rss_tc_mode_cmd *)desc.data;
 636
 637         roundup_size = roundup_pow_of_two(rss_size);
 638         roundup_size = ilog2(roundup_size);
 639
 640         for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
 641                 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i));
 642                 tc_size[i] = roundup_size;
 643                 tc_offset[i] = rss_size * i;
 644         }
 645
 646         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false);
 647         for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
 648                 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B,
 649                               (tc_valid[i] & 0x1));
 650                 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M,
 651                                 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]);
 652                 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M,
 653                                 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]);
 654         }
 655         status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 656         if (status)
 657                 dev_err(&hdev->pdev->dev,
 658                         "VF failed(=%d) to set rss tc mode\n", status);
 659
 660         return status;
 661 }
 662
 663 /* for revision 0x20, vf shared the same rss config with pf */
 664 static int hclgevf_get_rss_hash_key(struct hclgevf_dev *hdev)
 665 {
 666 #define HCLGEVF_RSS_MBX_RESP_LEN        8
 667
 668         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
 669         u8 resp_msg[HCLGEVF_RSS_MBX_RESP_LEN];
 670         u16 msg_num, hash_key_index;
 671         u8 index;
 672         int ret;
 673
 674         msg_num = (HCLGEVF_RSS_KEY_SIZE + HCLGEVF_RSS_MBX_RESP_LEN - 1) /
 675                         HCLGEVF_RSS_MBX_RESP_LEN;
 676         for (index = 0; index < msg_num; index++) {
 677                 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_RSS_KEY, 0,
 678                                            &index, sizeof(index),
 679                                            true, resp_msg,
 680                                            HCLGEVF_RSS_MBX_RESP_LEN);
 681                 if (ret) {
 682                         dev_err(&hdev->pdev->dev,
 683                                 "VF get rss hash key from PF failed, ret=%d",
 684                                 ret);
 685                         return ret;
 686                 }
 687
 688                 hash_key_index = HCLGEVF_RSS_MBX_RESP_LEN * index;
 689                 if (index == msg_num - 1)
 690                         memcpy(&rss_cfg->rss_hash_key[hash_key_index],
 691                                &resp_msg[0],
 692                                HCLGEVF_RSS_KEY_SIZE - hash_key_index);
 693                 else
 694                         memcpy(&rss_cfg->rss_hash_key[hash_key_index],
 695                                &resp_msg[0], HCLGEVF_RSS_MBX_RESP_LEN);
 696         }
 697
 698         return 0;
 699 }
 700
 701 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,
 702                            u8 *hfunc)
 703 {
 704         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 705         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
 706         int i, ret;
 707
 708         if (handle->pdev->revision >= 0x21) {
 709                 /* Get hash algorithm */
 710                 if (hfunc) {
 711                         switch (rss_cfg->hash_algo) {
 712                         case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ:
 713                                 *hfunc = ETH_RSS_HASH_TOP;
 714                                 break;
 715                         case HCLGEVF_RSS_HASH_ALGO_SIMPLE:
 716                                 *hfunc = ETH_RSS_HASH_XOR;
 717                                 break;
 718                         default:
 719                                 *hfunc = ETH_RSS_HASH_UNKNOWN;
 720                                 break;
 721                         }
 722                 }
 723
 724                 /* Get the RSS Key required by the user */
 725                 if (key)
 726                         memcpy(key, rss_cfg->rss_hash_key,
 727                                HCLGEVF_RSS_KEY_SIZE);
 728         } else {
 729                 if (hfunc)
 730                         *hfunc = ETH_RSS_HASH_TOP;
 731                 if (key) {
 732                         ret = hclgevf_get_rss_hash_key(hdev);
 733                         if (ret)
 734                                 return ret;
 735                         memcpy(key, rss_cfg->rss_hash_key,
 736                                HCLGEVF_RSS_KEY_SIZE);
 737                 }
 738         }
 739
 740         if (indir)
 741                 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
 742                         indir[i] = rss_cfg->rss_indirection_tbl[i];
 743
 744         return 0;
 745 }
 746
 747 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
 748                            const  u8 *key, const  u8 hfunc)
 749 {
 750         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 751         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
 752         int ret, i;
 753
 754         if (handle->pdev->revision >= 0x21) {
 755                 /* Set the RSS Hash Key if specififed by the user */
 756                 if (key) {
 757                         switch (hfunc) {
 758                         case ETH_RSS_HASH_TOP:
 759                                 rss_cfg->hash_algo =
 760                                         HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
 761                                 break;
 762                         case ETH_RSS_HASH_XOR:
 763                                 rss_cfg->hash_algo =
 764                                         HCLGEVF_RSS_HASH_ALGO_SIMPLE;
 765                                 break;
 766                         case ETH_RSS_HASH_NO_CHANGE:
 767                                 break;
 768                         default:
 769                                 return -EINVAL;
 770                         }
 771
 772                         ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
 773                                                        key);
 774                         if (ret)
 775                                 return ret;
 776
 777                         /* Update the shadow RSS key with user specified qids */
 778                         memcpy(rss_cfg->rss_hash_key, key,
 779                                HCLGEVF_RSS_KEY_SIZE);
 780                 }
 781         }
 782
 783         /* update the shadow RSS table with user specified qids */
 784         for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
 785                 rss_cfg->rss_indirection_tbl[i] = indir[i];
 786
 787         /* update the hardware */
 788         return hclgevf_set_rss_indir_table(hdev);
 789 }
 790
 791 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
 792 {
 793         u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0;
 794
 795         if (nfc->data & RXH_L4_B_2_3)
 796                 hash_sets |= HCLGEVF_D_PORT_BIT;
 797         else
 798                 hash_sets &= ~HCLGEVF_D_PORT_BIT;
 799
 800         if (nfc->data & RXH_IP_SRC)
 801                 hash_sets |= HCLGEVF_S_IP_BIT;
 802         else
 803                 hash_sets &= ~HCLGEVF_S_IP_BIT;
 804
 805         if (nfc->data & RXH_IP_DST)
 806                 hash_sets |= HCLGEVF_D_IP_BIT;
 807         else
 808                 hash_sets &= ~HCLGEVF_D_IP_BIT;
 809
 810         if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
 811                 hash_sets |= HCLGEVF_V_TAG_BIT;
 812
 813         return hash_sets;
 814 }
 815
 816 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle,
 817                                  struct ethtool_rxnfc *nfc)
 818 {
 819         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 820         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
 821         struct hclgevf_rss_input_tuple_cmd *req;
 822         struct hclgevf_desc desc;
 823         u8 tuple_sets;
 824         int ret;
 825
 826         if (handle->pdev->revision == 0x20)
 827                 return -EOPNOTSUPP;
 828
 829         if (nfc->data &
 830             ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3))
 831                 return -EINVAL;
 832
 833         req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
 834         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
 835
 836         req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
 837         req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
 838         req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
 839         req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
 840         req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
 841         req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
 842         req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
 843         req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
 844
 845         tuple_sets = hclgevf_get_rss_hash_bits(nfc);
 846         switch (nfc->flow_type) {
 847         case TCP_V4_FLOW:
 848                 req->ipv4_tcp_en = tuple_sets;
 849                 break;
 850         case TCP_V6_FLOW:
 851                 req->ipv6_tcp_en = tuple_sets;
 852                 break;
 853         case UDP_V4_FLOW:
 854                 req->ipv4_udp_en = tuple_sets;
 855                 break;
 856         case UDP_V6_FLOW:
 857                 req->ipv6_udp_en = tuple_sets;
 858                 break;
 859         case SCTP_V4_FLOW:
 860                 req->ipv4_sctp_en = tuple_sets;
 861                 break;
 862         case SCTP_V6_FLOW:
 863                 if ((nfc->data & RXH_L4_B_0_1) ||
 864                     (nfc->data & RXH_L4_B_2_3))
 865                         return -EINVAL;
 866
 867                 req->ipv6_sctp_en = tuple_sets;
 868                 break;
 869         case IPV4_FLOW:
 870                 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
 871                 break;
 872         case IPV6_FLOW:
 873                 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
 874                 break;
 875         default:
 876                 return -EINVAL;
 877         }
 878
 879         ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 880         if (ret) {
 881                 dev_err(&hdev->pdev->dev,
 882                         "Set rss tuple fail, status = %d\n", ret);
 883                 return ret;
 884         }
 885
 886         rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
 887         rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
 888         rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
 889         rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
 890         rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
 891         rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
 892         rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
 893         rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
 894         return 0;
 895 }
 896
 897 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle,
 898                                  struct ethtool_rxnfc *nfc)
 899 {
 900         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 901         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
 902         u8 tuple_sets;
 903
 904         if (handle->pdev->revision == 0x20)
 905                 return -EOPNOTSUPP;
 906
 907         nfc->data = 0;
 908
 909         switch (nfc->flow_type) {
 910         case TCP_V4_FLOW:
 911                 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
 912                 break;
 913         case UDP_V4_FLOW:
 914                 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en;
 915                 break;
 916         case TCP_V6_FLOW:
 917                 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
 918                 break;
 919         case UDP_V6_FLOW:
 920                 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en;
 921                 break;
 922         case SCTP_V4_FLOW:
 923                 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
 924                 break;
 925         case SCTP_V6_FLOW:
 926                 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
 927                 break;
 928         case IPV4_FLOW:
 929         case IPV6_FLOW:
 930                 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT;
 931                 break;
 932         default:
 933                 return -EINVAL;
 934         }
 935
 936         if (!tuple_sets)
 937                 return 0;
 938
 939         if (tuple_sets & HCLGEVF_D_PORT_BIT)
 940                 nfc->data |= RXH_L4_B_2_3;
 941         if (tuple_sets & HCLGEVF_S_PORT_BIT)
 942                 nfc->data |= RXH_L4_B_0_1;
 943         if (tuple_sets & HCLGEVF_D_IP_BIT)
 944                 nfc->data |= RXH_IP_DST;
 945         if (tuple_sets & HCLGEVF_S_IP_BIT)
 946                 nfc->data |= RXH_IP_SRC;
 947
 948         return 0;
 949 }
 950
 951 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev,
 952                                        struct hclgevf_rss_cfg *rss_cfg)
 953 {
 954         struct hclgevf_rss_input_tuple_cmd *req;
 955         struct hclgevf_desc desc;
 956         int ret;
 957
 958         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
 959
 960         req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
 961
 962         req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
 963         req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
 964         req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
 965         req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
 966         req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
 967         req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
 968         req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
 969         req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
 970
 971         ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 972         if (ret)
 973                 dev_err(&hdev->pdev->dev,
 974                         "Configure rss input fail, status = %d\n", ret);
 975         return ret;
 976 }
 977
 978 static int hclgevf_get_tc_size(struct hnae3_handle *handle)
 979 {
 980         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 981         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
 982
 983         return rss_cfg->rss_size;
 984 }
 985
 986 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en,
 987                                        int vector_id,
 988                                        struct hnae3_ring_chain_node *ring_chain)
 989 {
 990         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 991         struct hnae3_ring_chain_node *node;
 992         struct hclge_mbx_vf_to_pf_cmd *req;
 993         struct hclgevf_desc desc;
 994         int i = 0;
 995         int status;
 996         u8 type;
 997
 998         req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data;
 999
1000         for (node = ring_chain; node; node = node->next) {
1001                 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM +
1002                                         HCLGE_MBX_RING_NODE_VARIABLE_NUM * i;
1003
1004                 if (i == 0) {
1005                         hclgevf_cmd_setup_basic_desc(&desc,
1006                                                      HCLGEVF_OPC_MBX_VF_TO_PF,
1007                                                      false);
1008                         type = en ?
1009                                 HCLGE_MBX_MAP_RING_TO_VECTOR :
1010                                 HCLGE_MBX_UNMAP_RING_TO_VECTOR;
1011                         req->msg[0] = type;
1012                         req->msg[1] = vector_id;
1013                 }
1014
1015                 req->msg[idx_offset] =
1016                                 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B);
1017                 req->msg[idx_offset + 1] = node->tqp_index;
1018                 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx,
1019                                                            HNAE3_RING_GL_IDX_M,
1020                                                            HNAE3_RING_GL_IDX_S);
1021
1022                 i++;
1023                 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM -
1024                      HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) /
1025                      HCLGE_MBX_RING_NODE_VARIABLE_NUM) ||
1026                     !node->next) {
1027                         req->msg[2] = i;
1028
1029                         status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
1030                         if (status) {
1031                                 dev_err(&hdev->pdev->dev,
1032                                         "Map TQP fail, status is %d.\n",
1033                                         status);
1034                                 return status;
1035                         }
1036                         i = 0;
1037                         hclgevf_cmd_setup_basic_desc(&desc,
1038                                                      HCLGEVF_OPC_MBX_VF_TO_PF,
1039                                                      false);
1040                         req->msg[0] = type;
1041                         req->msg[1] = vector_id;
1042                 }
1043         }
1044
1045         return 0;
1046 }
1047
1048 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector,
1049                                       struct hnae3_ring_chain_node *ring_chain)
1050 {
1051         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1052         int vector_id;
1053
1054         vector_id = hclgevf_get_vector_index(hdev, vector);
1055         if (vector_id < 0) {
1056                 dev_err(&handle->pdev->dev,
1057                         "Get vector index fail. ret =%d\n", vector_id);
1058                 return vector_id;
1059         }
1060
1061         return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain);
1062 }
1063
1064 static int hclgevf_unmap_ring_from_vector(
1065                                 struct hnae3_handle *handle,
1066                                 int vector,
1067                                 struct hnae3_ring_chain_node *ring_chain)
1068 {
1069         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1070         int ret, vector_id;
1071
1072         if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
1073                 return 0;
1074
1075         vector_id = hclgevf_get_vector_index(hdev, vector);
1076         if (vector_id < 0) {
1077                 dev_err(&handle->pdev->dev,
1078                         "Get vector index fail. ret =%d\n", vector_id);
1079                 return vector_id;
1080         }
1081
1082         ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain);
1083         if (ret)
1084                 dev_err(&handle->pdev->dev,
1085                         "Unmap ring from vector fail. vector=%d, ret =%d\n",
1086                         vector_id,
1087                         ret);
1088
1089         return ret;
1090 }
1091
1092 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)
1093 {
1094         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1095         int vector_id;
1096
1097         vector_id = hclgevf_get_vector_index(hdev, vector);
1098         if (vector_id < 0) {
1099                 dev_err(&handle->pdev->dev,
1100                         "hclgevf_put_vector get vector index fail. ret =%d\n",
1101                         vector_id);
1102                 return vector_id;
1103         }
1104
1105         hclgevf_free_vector(hdev, vector_id);
1106
1107         return 0;
1108 }
1109
1110 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
1111                                         bool en_bc_pmc)
1112 {
1113         struct hclge_mbx_vf_to_pf_cmd *req;
1114         struct hclgevf_desc desc;
1115         int ret;
1116
1117         req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data;
1118
1119         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false);
1120         req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE;
1121         req->msg[1] = en_bc_pmc ? 1 : 0;
1122
1123         ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
1124         if (ret)
1125                 dev_err(&hdev->pdev->dev,
1126                         "Set promisc mode fail, status is %d.\n", ret);
1127
1128         return ret;
1129 }
1130
1131 static int hclgevf_set_promisc_mode(struct hclgevf_dev *hdev, bool en_bc_pmc)
1132 {
1133         return hclgevf_cmd_set_promisc_mode(hdev, en_bc_pmc);
1134 }
1135
1136 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id,
1137                               int stream_id, bool enable)
1138 {
1139         struct hclgevf_cfg_com_tqp_queue_cmd *req;
1140         struct hclgevf_desc desc;
1141         int status;
1142
1143         req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;
1144
1145         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE,
1146                                      false);
1147         req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK);
1148         req->stream_id = cpu_to_le16(stream_id);
1149         req->enable |= enable << HCLGEVF_TQP_ENABLE_B;
1150
1151         status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
1152         if (status)
1153                 dev_err(&hdev->pdev->dev,
1154                         "TQP enable fail, status =%d.\n", status);
1155
1156         return status;
1157 }
1158
1159 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle)
1160 {
1161         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
1162         struct hclgevf_tqp *tqp;
1163         int i;
1164
1165         for (i = 0; i < kinfo->num_tqps; i++) {
1166                 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
1167                 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
1168         }
1169 }
1170
1171 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p)
1172 {
1173         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1174
1175         ether_addr_copy(p, hdev->hw.mac.mac_addr);
1176 }
1177
1178 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p,
1179                                 bool is_first)
1180 {
1181         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1182         u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr;
1183         u8 *new_mac_addr = (u8 *)p;
1184         u8 msg_data[ETH_ALEN * 2];
1185         u16 subcode;
1186         int status;
1187
1188         ether_addr_copy(msg_data, new_mac_addr);
1189         ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr);
1190
1191         subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD :
1192                         HCLGE_MBX_MAC_VLAN_UC_MODIFY;
1193
1194         status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
1195                                       subcode, msg_data, ETH_ALEN * 2,
1196                                       true, NULL, 0);
1197         if (!status)
1198                 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr);
1199
1200         return status;
1201 }
1202
1203 static int hclgevf_add_uc_addr(struct hnae3_handle *handle,
1204                                const unsigned char *addr)
1205 {
1206         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1207
1208         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
1209                                     HCLGE_MBX_MAC_VLAN_UC_ADD,
1210                                     addr, ETH_ALEN, false, NULL, 0);
1211 }
1212
1213 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle,
1214                               const unsigned char *addr)
1215 {
1216         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1217
1218         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
1219                                     HCLGE_MBX_MAC_VLAN_UC_REMOVE,
1220                                     addr, ETH_ALEN, false, NULL, 0);
1221 }
1222
1223 static int hclgevf_add_mc_addr(struct hnae3_handle *handle,
1224                                const unsigned char *addr)
1225 {
1226         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1227
1228         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
1229                                     HCLGE_MBX_MAC_VLAN_MC_ADD,
1230                                     addr, ETH_ALEN, false, NULL, 0);
1231 }
1232
1233 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle,
1234                               const unsigned char *addr)
1235 {
1236         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1237
1238         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
1239                                     HCLGE_MBX_MAC_VLAN_MC_REMOVE,
1240                                     addr, ETH_ALEN, false, NULL, 0);
1241 }
1242
1243 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle,
1244                                    __be16 proto, u16 vlan_id,
1245                                    bool is_kill)
1246 {
1247 #define HCLGEVF_VLAN_MBX_MSG_LEN 5
1248         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1249         u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN];
1250
1251         if (vlan_id > 4095)
1252                 return -EINVAL;
1253
1254         if (proto != htons(ETH_P_8021Q))
1255                 return -EPROTONOSUPPORT;
1256
1257         msg_data[0] = is_kill;
1258         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1259         memcpy(&msg_data[3], &proto, sizeof(proto));
1260         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN,
1261                                     HCLGE_MBX_VLAN_FILTER, msg_data,
1262                                     HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0);
1263 }
1264
1265 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
1266 {
1267         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1268         u8 msg_data;
1269
1270         msg_data = enable ? 1 : 0;
1271         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN,
1272                                     HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data,
1273                                     1, false, NULL, 0);
1274 }
1275
1276 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
1277 {
1278         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1279         u8 msg_data[2];
1280         int ret;
1281
1282         memcpy(&msg_data[0], &queue_id, sizeof(queue_id));
1283
1284         /* disable vf queue before send queue reset msg to PF */
1285         ret = hclgevf_tqp_enable(hdev, queue_id, 0, false);
1286         if (ret)
1287                 return ret;
1288
1289         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data,
1290                                     2, true, NULL, 0);
1291 }
1292
1293 static int hclgevf_set_mtu(struct hnae3_handle *handle, int new_mtu)
1294 {
1295         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1296
1297         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MTU, 0, (u8 *)&new_mtu,
1298                                     sizeof(new_mtu), true, NULL, 0);
1299 }
1300
1301 static int hclgevf_notify_client(struct hclgevf_dev *hdev,
1302                                  enum hnae3_reset_notify_type type)
1303 {
1304         struct hnae3_client *client = hdev->nic_client;
1305         struct hnae3_handle *handle = &hdev->nic;
1306         int ret;
1307
1308         if (!client->ops->reset_notify)
1309                 return -EOPNOTSUPP;
1310
1311         ret = client->ops->reset_notify(handle, type);
1312         if (ret)
1313                 dev_err(&hdev->pdev->dev, "notify nic client failed %d(%d)\n",
1314                         type, ret);
1315
1316         return ret;
1317 }
1318
1319 static void hclgevf_flr_done(struct hnae3_ae_dev *ae_dev)
1320 {
1321         struct hclgevf_dev *hdev = ae_dev->priv;
1322
1323         set_bit(HNAE3_FLR_DONE, &hdev->flr_state);
1324 }
1325
1326 static int hclgevf_flr_poll_timeout(struct hclgevf_dev *hdev,
1327                                     unsigned long delay_us,
1328                                     unsigned long wait_cnt)
1329 {
1330         unsigned long cnt = 0;
1331
1332         while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) &&
1333                cnt++ < wait_cnt)
1334                 usleep_range(delay_us, delay_us * 2);
1335
1336         if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) {
1337                 dev_err(&hdev->pdev->dev,
1338                         "flr wait timeout\n");
1339                 return -ETIMEDOUT;
1340         }
1341
1342         return 0;
1343 }
1344
1345 static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
1346 {
1347 #define HCLGEVF_RESET_WAIT_US   20000
1348 #define HCLGEVF_RESET_WAIT_CNT  2000
1349 #define HCLGEVF_RESET_WAIT_TIMEOUT_US   \
1350         (HCLGEVF_RESET_WAIT_US * HCLGEVF_RESET_WAIT_CNT)
1351
1352         u32 val;
1353         int ret;
1354
1355         /* wait to check the hardware reset completion status */
1356         val = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
1357         dev_info(&hdev->pdev->dev, "checking vf resetting status: %x\n", val);
1358
1359         if (hdev->reset_type == HNAE3_FLR_RESET)
1360                 return hclgevf_flr_poll_timeout(hdev,
1361                                                 HCLGEVF_RESET_WAIT_US,
1362                                                 HCLGEVF_RESET_WAIT_CNT);
1363
1364         ret = readl_poll_timeout(hdev->hw.io_base + HCLGEVF_RST_ING, val,
1365                                  !(val & HCLGEVF_RST_ING_BITS),
1366                                  HCLGEVF_RESET_WAIT_US,
1367                                  HCLGEVF_RESET_WAIT_TIMEOUT_US);
1368
1369         /* hardware completion status should be available by this time */
1370         if (ret) {
1371                 dev_err(&hdev->pdev->dev,
1372                         "could'nt get reset done status from h/w, timeout!\n");
1373                 return ret;
1374         }
1375
1376         /* we will wait a bit more to let reset of the stack to complete. This
1377          * might happen in case reset assertion was made by PF. Yes, this also
1378          * means we might end up waiting bit more even for VF reset.
1379          */
1380         msleep(5000);
1381
1382         return 0;
1383 }
1384
1385 static int hclgevf_reset_stack(struct hclgevf_dev *hdev)
1386 {
1387         int ret;
1388
1389         /* uninitialize the nic client */
1390         ret = hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1391         if (ret)
1392                 return ret;
1393
1394         /* re-initialize the hclge device */
1395         ret = hclgevf_reset_hdev(hdev);
1396         if (ret) {
1397                 dev_err(&hdev->pdev->dev,
1398                         "hclge device re-init failed, VF is disabled!\n");
1399                 return ret;
1400         }
1401
1402         /* bring up the nic client again */
1403         ret = hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT);
1404         if (ret)
1405                 return ret;
1406
1407         return hclgevf_notify_client(hdev, HNAE3_RESTORE_CLIENT);
1408 }
1409
1410 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)
1411 {
1412         int ret = 0;
1413
1414         switch (hdev->reset_type) {
1415         case HNAE3_VF_FUNC_RESET:
1416                 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL,
1417                                            0, true, NULL, sizeof(u8));
1418                 hdev->rst_stats.vf_func_rst_cnt++;
1419                 break;
1420         case HNAE3_FLR_RESET:
1421                 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
1422                 hdev->rst_stats.flr_rst_cnt++;
1423                 break;
1424         default:
1425                 break;
1426         }
1427
1428         set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
1429
1430         dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n",
1431                  hdev->reset_type, ret);
1432
1433         return ret;
1434 }
1435
1436 static int hclgevf_reset(struct hclgevf_dev *hdev)
1437 {
1438         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1439         int ret;
1440
1441         /* Initialize ae_dev reset status as well, in case enet layer wants to
1442          * know if device is undergoing reset
1443          */
1444         ae_dev->reset_type = hdev->reset_type;
1445         hdev->rst_stats.rst_cnt++;
1446         rtnl_lock();
1447
1448         /* bring down the nic to stop any ongoing TX/RX */
1449         ret = hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
1450         if (ret)
1451                 goto err_reset_lock;
1452
1453         rtnl_unlock();
1454
1455         ret = hclgevf_reset_prepare_wait(hdev);
1456         if (ret)
1457                 goto err_reset;
1458
1459         /* check if VF could successfully fetch the hardware reset completion
1460          * status from the hardware
1461          */
1462         ret = hclgevf_reset_wait(hdev);
1463         if (ret) {
1464                 /* can't do much in this situation, will disable VF */
1465                 dev_err(&hdev->pdev->dev,
1466                         "VF failed(=%d) to fetch H/W reset completion status\n",
1467                         ret);
1468                 goto err_reset;
1469         }
1470
1471         hdev->rst_stats.hw_rst_done_cnt++;
1472
1473         rtnl_lock();
1474
1475         /* now, re-initialize the nic client and ae device*/
1476         ret = hclgevf_reset_stack(hdev);
1477         if (ret) {
1478                 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");
1479                 goto err_reset_lock;
1480         }
1481
1482         /* bring up the nic to enable TX/RX again */
1483         ret = hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
1484         if (ret)
1485                 goto err_reset_lock;
1486
1487         rtnl_unlock();
1488
1489         hdev->last_reset_time = jiffies;
1490         ae_dev->reset_type = HNAE3_NONE_RESET;
1491         hdev->rst_stats.rst_done_cnt++;
1492
1493         return ret;
1494 err_reset_lock:
1495         rtnl_unlock();
1496 err_reset:
1497         /* When VF reset failed, only the higher level reset asserted by PF
1498          * can restore it, so re-initialize the command queue to receive
1499          * this higher reset event.
1500          */
1501         hclgevf_cmd_init(hdev);
1502         dev_err(&hdev->pdev->dev, "failed to reset VF\n");
1503         if (hclgevf_is_reset_pending(hdev))
1504                 hclgevf_reset_task_schedule(hdev);
1505
1506         return ret;
1507 }
1508
1509 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev,
1510                                                      unsigned long *addr)
1511 {
1512         enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
1513
1514         /* return the highest priority reset level amongst all */
1515         if (test_bit(HNAE3_VF_RESET, addr)) {
1516                 rst_level = HNAE3_VF_RESET;
1517                 clear_bit(HNAE3_VF_RESET, addr);
1518                 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
1519                 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1520         } else if (test_bit(HNAE3_VF_FULL_RESET, addr)) {
1521                 rst_level = HNAE3_VF_FULL_RESET;
1522                 clear_bit(HNAE3_VF_FULL_RESET, addr);
1523                 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1524         } else if (test_bit(HNAE3_VF_PF_FUNC_RESET, addr)) {
1525                 rst_level = HNAE3_VF_PF_FUNC_RESET;
1526                 clear_bit(HNAE3_VF_PF_FUNC_RESET, addr);
1527                 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1528         } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) {
1529                 rst_level = HNAE3_VF_FUNC_RESET;
1530                 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1531         } else if (test_bit(HNAE3_FLR_RESET, addr)) {
1532                 rst_level = HNAE3_FLR_RESET;
1533                 clear_bit(HNAE3_FLR_RESET, addr);
1534         }
1535
1536         return rst_level;
1537 }
1538
1539 static void hclgevf_reset_event(struct pci_dev *pdev,
1540                                 struct hnae3_handle *handle)
1541 {
1542         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
1543         struct hclgevf_dev *hdev = ae_dev->priv;
1544
1545         dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
1546
1547         if (hdev->default_reset_request)
1548                 hdev->reset_level =
1549                         hclgevf_get_reset_level(hdev,
1550                                                 &hdev->default_reset_request);
1551         else
1552                 hdev->reset_level = HNAE3_VF_FUNC_RESET;
1553
1554         /* reset of this VF requested */
1555         set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
1556         hclgevf_reset_task_schedule(hdev);
1557
1558         hdev->last_reset_time = jiffies;
1559 }
1560
1561 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
1562                                           enum hnae3_reset_type rst_type)
1563 {
1564         struct hclgevf_dev *hdev = ae_dev->priv;
1565
1566         set_bit(rst_type, &hdev->default_reset_request);
1567 }
1568
1569 static void hclgevf_flr_prepare(struct hnae3_ae_dev *ae_dev)
1570 {
1571 #define HCLGEVF_FLR_WAIT_MS     100
1572 #define HCLGEVF_FLR_WAIT_CNT    50
1573         struct hclgevf_dev *hdev = ae_dev->priv;
1574         int cnt = 0;
1575
1576         clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
1577         clear_bit(HNAE3_FLR_DONE, &hdev->flr_state);
1578         set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request);
1579         hclgevf_reset_event(hdev->pdev, NULL);
1580
1581         while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) &&
1582                cnt++ < HCLGEVF_FLR_WAIT_CNT)
1583                 msleep(HCLGEVF_FLR_WAIT_MS);
1584
1585         if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state))
1586                 dev_err(&hdev->pdev->dev,
1587                         "flr wait down timeout: %d\n", cnt);
1588 }
1589
1590 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)
1591 {
1592         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1593
1594         return hdev->fw_version;
1595 }
1596
1597 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)
1598 {
1599         struct hclgevf_misc_vector *vector = &hdev->misc_vector;
1600
1601         vector->vector_irq = pci_irq_vector(hdev->pdev,
1602                                             HCLGEVF_MISC_VECTOR_NUM);
1603         vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
1604         /* vector status always valid for Vector 0 */
1605         hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;
1606         hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;
1607
1608         hdev->num_msi_left -= 1;
1609         hdev->num_msi_used += 1;
1610 }
1611
1612 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev)
1613 {
1614         if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state)) {
1615                 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state);
1616                 schedule_work(&hdev->rst_service_task);
1617         }
1618 }
1619
1620 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev)
1621 {
1622         if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) &&
1623             !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) {
1624                 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1625                 schedule_work(&hdev->mbx_service_task);
1626         }
1627 }
1628
1629 static void hclgevf_task_schedule(struct hclgevf_dev *hdev)
1630 {
1631         if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state)  &&
1632             !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state))
1633                 schedule_work(&hdev->service_task);
1634 }
1635
1636 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev)
1637 {
1638         /* if we have any pending mailbox event then schedule the mbx task */
1639         if (hdev->mbx_event_pending)
1640                 hclgevf_mbx_task_schedule(hdev);
1641
1642         if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state))
1643                 hclgevf_reset_task_schedule(hdev);
1644 }
1645
1646 static void hclgevf_service_timer(struct timer_list *t)
1647 {
1648         struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer);
1649
1650         mod_timer(&hdev->service_timer, jiffies + 5 * HZ);
1651
1652         hdev->stats_timer++;
1653         hclgevf_task_schedule(hdev);
1654 }
1655
1656 static void hclgevf_reset_service_task(struct work_struct *work)
1657 {
1658         struct hclgevf_dev *hdev =
1659                 container_of(work, struct hclgevf_dev, rst_service_task);
1660         int ret;
1661
1662         if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
1663                 return;
1664
1665         clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state);
1666
1667         if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
1668                                &hdev->reset_state)) {
1669                 /* PF has initmated that it is about to reset the hardware.
1670                  * We now have to poll & check if harware has actually completed
1671                  * the reset sequence. On hardware reset completion, VF needs to
1672                  * reset the client and ae device.
1673                  */
1674                 hdev->reset_attempts = 0;
1675
1676                 hdev->last_reset_time = jiffies;
1677                 while ((hdev->reset_type =
1678                         hclgevf_get_reset_level(hdev, &hdev->reset_pending))
1679                        != HNAE3_NONE_RESET) {
1680                         ret = hclgevf_reset(hdev);
1681                         if (ret)
1682                                 dev_err(&hdev->pdev->dev,
1683                                         "VF stack reset failed %d.\n", ret);
1684                 }
1685         } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,
1686                                       &hdev->reset_state)) {
1687                 /* we could be here when either of below happens:
1688                  * 1. reset was initiated due to watchdog timeout due to
1689                  *    a. IMP was earlier reset and our TX got choked down and
1690                  *       which resulted in watchdog reacting and inducing VF
1691                  *       reset. This also means our cmdq would be unreliable.
1692                  *    b. problem in TX due to other lower layer(example link
1693                  *       layer not functioning properly etc.)
1694                  * 2. VF reset might have been initiated due to some config
1695                  *    change.
1696                  *
1697                  * NOTE: Theres no clear way to detect above cases than to react
1698                  * to the response of PF for this reset request. PF will ack the
1699                  * 1b and 2. cases but we will not get any intimation about 1a
1700                  * from PF as cmdq would be in unreliable state i.e. mailbox
1701                  * communication between PF and VF would be broken.
1702                  */
1703
1704                 /* if we are never geting into pending state it means either:
1705                  * 1. PF is not receiving our request which could be due to IMP
1706                  *    reset
1707                  * 2. PF is screwed
1708                  * We cannot do much for 2. but to check first we can try reset
1709                  * our PCIe + stack and see if it alleviates the problem.
1710                  */
1711                 if (hdev->reset_attempts > 3) {
1712                         /* prepare for full reset of stack + pcie interface */
1713                         set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending);
1714
1715                         /* "defer" schedule the reset task again */
1716                         set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1717                 } else {
1718                         hdev->reset_attempts++;
1719
1720                         set_bit(hdev->reset_level, &hdev->reset_pending);
1721                         set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1722                 }
1723                 hclgevf_reset_task_schedule(hdev);
1724         }
1725
1726         clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
1727 }
1728
1729 static void hclgevf_mailbox_service_task(struct work_struct *work)
1730 {
1731         struct hclgevf_dev *hdev;
1732
1733         hdev = container_of(work, struct hclgevf_dev, mbx_service_task);
1734
1735         if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state))
1736                 return;
1737
1738         clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1739
1740         hclgevf_mbx_async_handler(hdev);
1741
1742         clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
1743 }
1744
1745 static void hclgevf_keep_alive_timer(struct timer_list *t)
1746 {
1747         struct hclgevf_dev *hdev = from_timer(hdev, t, keep_alive_timer);
1748
1749         schedule_work(&hdev->keep_alive_task);
1750         mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ);
1751 }
1752
1753 static void hclgevf_keep_alive_task(struct work_struct *work)
1754 {
1755         struct hclgevf_dev *hdev;
1756         u8 respmsg;
1757         int ret;
1758
1759         hdev = container_of(work, struct hclgevf_dev, keep_alive_task);
1760
1761         if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state))
1762                 return;
1763
1764         ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_KEEP_ALIVE, 0, NULL,
1765                                    0, false, &respmsg, sizeof(u8));
1766         if (ret)
1767                 dev_err(&hdev->pdev->dev,
1768                         "VF sends keep alive cmd failed(=%d)\n", ret);
1769 }
1770
1771 static void hclgevf_service_task(struct work_struct *work)
1772 {
1773         struct hnae3_handle *handle;
1774         struct hclgevf_dev *hdev;
1775
1776         hdev = container_of(work, struct hclgevf_dev, service_task);
1777         handle = &hdev->nic;
1778
1779         if (hdev->stats_timer >= HCLGEVF_STATS_TIMER_INTERVAL) {
1780                 hclgevf_tqps_update_stats(handle);
1781                 hdev->stats_timer = 0;
1782         }
1783
1784         /* request the link status from the PF. PF would be able to tell VF
1785          * about such updates in future so we might remove this later
1786          */
1787         hclgevf_request_link_info(hdev);
1788
1789         hclgevf_update_link_mode(hdev);
1790
1791         hclgevf_deferred_task_schedule(hdev);
1792
1793         clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
1794 }
1795
1796 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)
1797 {
1798         hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr);
1799 }
1800
1801 static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
1802                                                       u32 *clearval)
1803 {
1804         u32 cmdq_src_reg, rst_ing_reg;
1805
1806         /* fetch the events from their corresponding regs */
1807         cmdq_src_reg = hclgevf_read_dev(&hdev->hw,
1808                                         HCLGEVF_VECTOR0_CMDQ_SRC_REG);
1809
1810         if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) {
1811                 rst_ing_reg = hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
1812                 dev_info(&hdev->pdev->dev,
1813                          "receive reset interrupt 0x%x!\n", rst_ing_reg);
1814                 set_bit(HNAE3_VF_RESET, &hdev->reset_pending);
1815                 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1816                 set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
1817                 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B);
1818                 *clearval = cmdq_src_reg;
1819                 hdev->rst_stats.vf_rst_cnt++;
1820                 return HCLGEVF_VECTOR0_EVENT_RST;
1821         }
1822
1823         /* check for vector0 mailbox(=CMDQ RX) event source */
1824         if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
1825                 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
1826                 *clearval = cmdq_src_reg;
1827                 return HCLGEVF_VECTOR0_EVENT_MBX;
1828         }
1829
1830         dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n");
1831
1832         return HCLGEVF_VECTOR0_EVENT_OTHER;
1833 }
1834
1835 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
1836 {
1837         writel(en ? 1 : 0, vector->addr);
1838 }
1839
1840 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
1841 {
1842         enum hclgevf_evt_cause event_cause;
1843         struct hclgevf_dev *hdev = data;
1844         u32 clearval;
1845
1846         hclgevf_enable_vector(&hdev->misc_vector, false);
1847         event_cause = hclgevf_check_evt_cause(hdev, &clearval);
1848
1849         switch (event_cause) {
1850         case HCLGEVF_VECTOR0_EVENT_RST:
1851                 hclgevf_reset_task_schedule(hdev);
1852                 break;
1853         case HCLGEVF_VECTOR0_EVENT_MBX:
1854                 hclgevf_mbx_handler(hdev);
1855                 break;
1856         default:
1857                 break;
1858         }
1859
1860         if (event_cause != HCLGEVF_VECTOR0_EVENT_OTHER) {
1861                 hclgevf_clear_event_cause(hdev, clearval);
1862                 hclgevf_enable_vector(&hdev->misc_vector, true);
1863         }
1864
1865         return IRQ_HANDLED;
1866 }
1867
1868 static int hclgevf_configure(struct hclgevf_dev *hdev)
1869 {
1870         int ret;
1871
1872         /* get current port based vlan state from PF */
1873         ret = hclgevf_get_port_base_vlan_filter_state(hdev);
1874         if (ret)
1875                 return ret;
1876
1877         /* get queue configuration from PF */
1878         ret = hclgevf_get_queue_info(hdev);
1879         if (ret)
1880                 return ret;
1881
1882         /* get queue depth info from PF */
1883         ret = hclgevf_get_queue_depth(hdev);
1884         if (ret)
1885                 return ret;
1886
1887         ret = hclgevf_get_pf_media_type(hdev);
1888         if (ret)
1889                 return ret;
1890
1891         /* get tc configuration from PF */
1892         return hclgevf_get_tc_info(hdev);
1893 }
1894
1895 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev)
1896 {
1897         struct pci_dev *pdev = ae_dev->pdev;
1898         struct hclgevf_dev *hdev;
1899
1900         hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
1901         if (!hdev)
1902                 return -ENOMEM;
1903
1904         hdev->pdev = pdev;
1905         hdev->ae_dev = ae_dev;
1906         ae_dev->priv = hdev;
1907
1908         return 0;
1909 }
1910
1911 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
1912 {
1913         struct hnae3_handle *roce = &hdev->roce;
1914         struct hnae3_handle *nic = &hdev->nic;
1915
1916         roce->rinfo.num_vectors = hdev->num_roce_msix;
1917
1918         if (hdev->num_msi_left < roce->rinfo.num_vectors ||
1919             hdev->num_msi_left == 0)
1920                 return -EINVAL;
1921
1922         roce->rinfo.base_vector = hdev->roce_base_vector;
1923
1924         roce->rinfo.netdev = nic->kinfo.netdev;
1925         roce->rinfo.roce_io_base = hdev->hw.io_base;
1926
1927         roce->pdev = nic->pdev;
1928         roce->ae_algo = nic->ae_algo;
1929         roce->numa_node_mask = nic->numa_node_mask;
1930
1931         return 0;
1932 }
1933
1934 static int hclgevf_config_gro(struct hclgevf_dev *hdev, bool en)
1935 {
1936         struct hclgevf_cfg_gro_status_cmd *req;
1937         struct hclgevf_desc desc;
1938         int ret;
1939
1940         if (!hnae3_dev_gro_supported(hdev))
1941                 return 0;
1942
1943         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_GRO_GENERIC_CONFIG,
1944                                      false);
1945         req = (struct hclgevf_cfg_gro_status_cmd *)desc.data;
1946
1947         req->gro_en = cpu_to_le16(en ? 1 : 0);
1948
1949         ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
1950         if (ret)
1951                 dev_err(&hdev->pdev->dev,
1952                         "VF GRO hardware config cmd failed, ret = %d.\n", ret);
1953
1954         return ret;
1955 }
1956
1957 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
1958 {
1959         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
1960         int i, ret;
1961
1962         rss_cfg->rss_size = hdev->rss_size_max;
1963
1964         if (hdev->pdev->revision >= 0x21) {
1965                 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_SIMPLE;
1966                 memcpy(rss_cfg->rss_hash_key, hclgevf_hash_key,
1967                        HCLGEVF_RSS_KEY_SIZE);
1968
1969                 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
1970                                                rss_cfg->rss_hash_key);
1971                 if (ret)
1972                         return ret;
1973
1974                 rss_cfg->rss_tuple_sets.ipv4_tcp_en =
1975                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1976                 rss_cfg->rss_tuple_sets.ipv4_udp_en =
1977                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1978                 rss_cfg->rss_tuple_sets.ipv4_sctp_en =
1979                                         HCLGEVF_RSS_INPUT_TUPLE_SCTP;
1980                 rss_cfg->rss_tuple_sets.ipv4_fragment_en =
1981                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1982                 rss_cfg->rss_tuple_sets.ipv6_tcp_en =
1983                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1984                 rss_cfg->rss_tuple_sets.ipv6_udp_en =
1985                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1986                 rss_cfg->rss_tuple_sets.ipv6_sctp_en =
1987                                         HCLGEVF_RSS_INPUT_TUPLE_SCTP;
1988                 rss_cfg->rss_tuple_sets.ipv6_fragment_en =
1989                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1990
1991                 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg);
1992                 if (ret)
1993                         return ret;
1994
1995         }
1996
1997         /* Initialize RSS indirect table for each vport */
1998         for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
1999                 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max;
2000
2001         ret = hclgevf_set_rss_indir_table(hdev);
2002         if (ret)
2003                 return ret;
2004
2005         return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max);
2006 }
2007
2008 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)
2009 {
2010         /* other vlan config(like, VLAN TX/RX offload) would also be added
2011          * here later
2012          */
2013         return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
2014                                        false);
2015 }
2016
2017 static void hclgevf_set_timer_task(struct hnae3_handle *handle, bool enable)
2018 {
2019         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2020
2021         if (enable) {
2022                 mod_timer(&hdev->service_timer, jiffies + HZ);
2023         } else {
2024                 del_timer_sync(&hdev->service_timer);
2025                 cancel_work_sync(&hdev->service_task);
2026                 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
2027         }
2028 }
2029
2030 static int hclgevf_ae_start(struct hnae3_handle *handle)
2031 {
2032         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2033
2034         /* reset tqp stats */
2035         hclgevf_reset_tqp_stats(handle);
2036
2037         hclgevf_request_link_info(hdev);
2038
2039         hclgevf_update_link_mode(hdev);
2040
2041         clear_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2042
2043         return 0;
2044 }
2045
2046 static void hclgevf_ae_stop(struct hnae3_handle *handle)
2047 {
2048         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2049         int i;
2050
2051         set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2052
2053         for (i = 0; i < handle->kinfo.num_tqps; i++)
2054                 hclgevf_reset_tqp(handle, i);
2055
2056         /* reset tqp stats */
2057         hclgevf_reset_tqp_stats(handle);
2058         hclgevf_update_link_status(hdev, 0);
2059 }
2060
2061 static int hclgevf_set_alive(struct hnae3_handle *handle, bool alive)
2062 {
2063         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2064         u8 msg_data;
2065
2066         msg_data = alive ? 1 : 0;
2067         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_ALIVE,
2068                                     0, &msg_data, 1, false, NULL, 0);
2069 }
2070
2071 static int hclgevf_client_start(struct hnae3_handle *handle)
2072 {
2073         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2074         int ret;
2075
2076         ret = hclgevf_set_alive(handle, true);
2077         if (ret)
2078                 return ret;
2079
2080         mod_timer(&hdev->keep_alive_timer, jiffies + 2 * HZ);
2081
2082         return 0;
2083 }
2084
2085 static void hclgevf_client_stop(struct hnae3_handle *handle)
2086 {
2087         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2088         int ret;
2089
2090         ret = hclgevf_set_alive(handle, false);
2091         if (ret)
2092                 dev_warn(&hdev->pdev->dev,
2093                          "%s failed %d\n", __func__, ret);
2094
2095         del_timer_sync(&hdev->keep_alive_timer);
2096         cancel_work_sync(&hdev->keep_alive_task);
2097 }
2098
2099 static void hclgevf_state_init(struct hclgevf_dev *hdev)
2100 {
2101         /* setup tasks for the MBX */
2102         INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task);
2103         clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
2104         clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
2105
2106         /* setup tasks for service timer */
2107         timer_setup(&hdev->service_timer, hclgevf_service_timer, 0);
2108
2109         INIT_WORK(&hdev->service_task, hclgevf_service_task);
2110         clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
2111
2112         INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task);
2113
2114         mutex_init(&hdev->mbx_resp.mbx_mutex);
2115
2116         /* bring the device down */
2117         set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2118 }
2119
2120 static void hclgevf_state_uninit(struct hclgevf_dev *hdev)
2121 {
2122         set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
2123
2124         if (hdev->keep_alive_timer.function)
2125                 del_timer_sync(&hdev->keep_alive_timer);
2126         if (hdev->keep_alive_task.func)
2127                 cancel_work_sync(&hdev->keep_alive_task);
2128         if (hdev->service_timer.function)
2129                 del_timer_sync(&hdev->service_timer);
2130         if (hdev->service_task.func)
2131                 cancel_work_sync(&hdev->service_task);
2132         if (hdev->mbx_service_task.func)
2133                 cancel_work_sync(&hdev->mbx_service_task);
2134         if (hdev->rst_service_task.func)
2135                 cancel_work_sync(&hdev->rst_service_task);
2136
2137         mutex_destroy(&hdev->mbx_resp.mbx_mutex);
2138 }
2139
2140 static int hclgevf_init_msi(struct hclgevf_dev *hdev)
2141 {
2142         struct pci_dev *pdev = hdev->pdev;
2143         int vectors;
2144         int i;
2145
2146         if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B))
2147                 vectors = pci_alloc_irq_vectors(pdev,
2148                                                 hdev->roce_base_msix_offset + 1,
2149                                                 hdev->num_msi,
2150                                                 PCI_IRQ_MSIX);
2151         else
2152                 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
2153                                                 PCI_IRQ_MSI | PCI_IRQ_MSIX);
2154
2155         if (vectors < 0) {
2156                 dev_err(&pdev->dev,
2157                         "failed(%d) to allocate MSI/MSI-X vectors\n",
2158                         vectors);
2159                 return vectors;
2160         }
2161         if (vectors < hdev->num_msi)
2162                 dev_warn(&hdev->pdev->dev,
2163                          "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
2164                          hdev->num_msi, vectors);
2165
2166         hdev->num_msi = vectors;
2167         hdev->num_msi_left = vectors;
2168         hdev->base_msi_vector = pdev->irq;
2169         hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset;
2170
2171         hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2172                                            sizeof(u16), GFP_KERNEL);
2173         if (!hdev->vector_status) {
2174                 pci_free_irq_vectors(pdev);
2175                 return -ENOMEM;
2176         }
2177
2178         for (i = 0; i < hdev->num_msi; i++)
2179                 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT;
2180
2181         hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2182                                         sizeof(int), GFP_KERNEL);
2183         if (!hdev->vector_irq) {
2184                 devm_kfree(&pdev->dev, hdev->vector_status);
2185                 pci_free_irq_vectors(pdev);
2186                 return -ENOMEM;
2187         }
2188
2189         return 0;
2190 }
2191
2192 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev)
2193 {
2194         struct pci_dev *pdev = hdev->pdev;
2195
2196         devm_kfree(&pdev->dev, hdev->vector_status);
2197         devm_kfree(&pdev->dev, hdev->vector_irq);
2198         pci_free_irq_vectors(pdev);
2199 }
2200
2201 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev)
2202 {
2203         int ret = 0;
2204
2205         hclgevf_get_misc_vector(hdev);
2206
2207         ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle,
2208                           0, "hclgevf_cmd", hdev);
2209         if (ret) {
2210                 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n",
2211                         hdev->misc_vector.vector_irq);
2212                 return ret;
2213         }
2214
2215         hclgevf_clear_event_cause(hdev, 0);
2216
2217         /* enable misc. vector(vector 0) */
2218         hclgevf_enable_vector(&hdev->misc_vector, true);
2219
2220         return ret;
2221 }
2222
2223 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev)
2224 {
2225         /* disable misc vector(vector 0) */
2226         hclgevf_enable_vector(&hdev->misc_vector, false);
2227         synchronize_irq(hdev->misc_vector.vector_irq);
2228         free_irq(hdev->misc_vector.vector_irq, hdev);
2229         hclgevf_free_vector(hdev, 0);
2230 }
2231
2232 static void hclgevf_info_show(struct hclgevf_dev *hdev)
2233 {
2234         struct device *dev = &hdev->pdev->dev;
2235
2236         dev_info(dev, "VF info begin:\n");
2237
2238         dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps);
2239         dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc);
2240         dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc);
2241         dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport);
2242         dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map);
2243         dev_info(dev, "PF media type of this VF: %d\n",
2244                  hdev->hw.mac.media_type);
2245
2246         dev_info(dev, "VF info end.\n");
2247 }
2248
2249 static int hclgevf_init_client_instance(struct hnae3_client *client,
2250                                         struct hnae3_ae_dev *ae_dev)
2251 {
2252         struct hclgevf_dev *hdev = ae_dev->priv;
2253         int ret;
2254
2255         switch (client->type) {
2256         case HNAE3_CLIENT_KNIC:
2257                 hdev->nic_client = client;
2258                 hdev->nic.client = client;
2259
2260                 ret = client->ops->init_instance(&hdev->nic);
2261                 if (ret)
2262                         goto clear_nic;
2263
2264                 hnae3_set_client_init_flag(client, ae_dev, 1);
2265
2266                 if (netif_msg_drv(&hdev->nic))
2267                         hclgevf_info_show(hdev);
2268
2269                 if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) {
2270                         struct hnae3_client *rc = hdev->roce_client;
2271
2272                         ret = hclgevf_init_roce_base_info(hdev);
2273                         if (ret)
2274                                 goto clear_roce;
2275                         ret = rc->ops->init_instance(&hdev->roce);
2276                         if (ret)
2277                                 goto clear_roce;
2278
2279                         hnae3_set_client_init_flag(hdev->roce_client, ae_dev,
2280                                                    1);
2281                 }
2282                 break;
2283         case HNAE3_CLIENT_UNIC:
2284                 hdev->nic_client = client;
2285                 hdev->nic.client = client;
2286
2287                 ret = client->ops->init_instance(&hdev->nic);
2288                 if (ret)
2289                         goto clear_nic;
2290
2291                 hnae3_set_client_init_flag(client, ae_dev, 1);
2292                 break;
2293         case HNAE3_CLIENT_ROCE:
2294                 if (hnae3_dev_roce_supported(hdev)) {
2295                         hdev->roce_client = client;
2296                         hdev->roce.client = client;
2297                 }
2298
2299                 if (hdev->roce_client && hdev->nic_client) {
2300                         ret = hclgevf_init_roce_base_info(hdev);
2301                         if (ret)
2302                                 goto clear_roce;
2303
2304                         ret = client->ops->init_instance(&hdev->roce);
2305                         if (ret)
2306                                 goto clear_roce;
2307                 }
2308
2309                 hnae3_set_client_init_flag(client, ae_dev, 1);
2310                 break;
2311         default:
2312                 return -EINVAL;
2313         }
2314
2315         return 0;
2316
2317 clear_nic:
2318         hdev->nic_client = NULL;
2319         hdev->nic.client = NULL;
2320         return ret;
2321 clear_roce:
2322         hdev->roce_client = NULL;
2323         hdev->roce.client = NULL;
2324         return ret;
2325 }
2326
2327 static void hclgevf_uninit_client_instance(struct hnae3_client *client,
2328                                            struct hnae3_ae_dev *ae_dev)
2329 {
2330         struct hclgevf_dev *hdev = ae_dev->priv;
2331
2332         /* un-init roce, if it exists */
2333         if (hdev->roce_client) {
2334                 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);
2335                 hdev->roce_client = NULL;
2336                 hdev->roce.client = NULL;
2337         }
2338
2339         /* un-init nic/unic, if this was not called by roce client */
2340         if (client->ops->uninit_instance && hdev->nic_client &&
2341             client->type != HNAE3_CLIENT_ROCE) {
2342                 client->ops->uninit_instance(&hdev->nic, 0);
2343                 hdev->nic_client = NULL;
2344                 hdev->nic.client = NULL;
2345         }
2346 }
2347
2348 static int hclgevf_pci_init(struct hclgevf_dev *hdev)
2349 {
2350         struct pci_dev *pdev = hdev->pdev;
2351         struct hclgevf_hw *hw;
2352         int ret;
2353
2354         ret = pci_enable_device(pdev);
2355         if (ret) {
2356                 dev_err(&pdev->dev, "failed to enable PCI device\n");
2357                 return ret;
2358         }
2359
2360         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2361         if (ret) {
2362                 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");
2363                 goto err_disable_device;
2364         }
2365
2366         ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME);
2367         if (ret) {
2368                 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
2369                 goto err_disable_device;
2370         }
2371
2372         pci_set_master(pdev);
2373         hw = &hdev->hw;
2374         hw->hdev = hdev;
2375         hw->io_base = pci_iomap(pdev, 2, 0);
2376         if (!hw->io_base) {
2377                 dev_err(&pdev->dev, "can't map configuration register space\n");
2378                 ret = -ENOMEM;
2379                 goto err_clr_master;
2380         }
2381
2382         return 0;
2383
2384 err_clr_master:
2385         pci_clear_master(pdev);
2386         pci_release_regions(pdev);
2387 err_disable_device:
2388         pci_disable_device(pdev);
2389
2390         return ret;
2391 }
2392
2393 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
2394 {
2395         struct pci_dev *pdev = hdev->pdev;
2396
2397         pci_iounmap(pdev, hdev->hw.io_base);
2398         pci_clear_master(pdev);
2399         pci_release_regions(pdev);
2400         pci_disable_device(pdev);
2401 }
2402
2403 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)
2404 {
2405         struct hclgevf_query_res_cmd *req;
2406         struct hclgevf_desc desc;
2407         int ret;
2408
2409         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true);
2410         ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
2411         if (ret) {
2412                 dev_err(&hdev->pdev->dev,
2413                         "query vf resource failed, ret = %d.\n", ret);
2414                 return ret;
2415         }
2416
2417         req = (struct hclgevf_query_res_cmd *)desc.data;
2418
2419         if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) {
2420                 hdev->roce_base_msix_offset =
2421                 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
2422                                 HCLGEVF_MSIX_OFT_ROCEE_M,
2423                                 HCLGEVF_MSIX_OFT_ROCEE_S);
2424                 hdev->num_roce_msix =
2425                 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),
2426                                 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
2427
2428                 /* VF should have NIC vectors and Roce vectors, NIC vectors
2429                  * are queued before Roce vectors. The offset is fixed to 64.
2430                  */
2431                 hdev->num_msi = hdev->num_roce_msix +
2432                                 hdev->roce_base_msix_offset;
2433         } else {
2434                 hdev->num_msi =
2435                 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),
2436                                 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
2437         }
2438
2439         return 0;
2440 }
2441
2442 static int hclgevf_pci_reset(struct hclgevf_dev *hdev)
2443 {
2444         struct pci_dev *pdev = hdev->pdev;
2445         int ret = 0;
2446
2447         if (hdev->reset_type == HNAE3_VF_FULL_RESET &&
2448             test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
2449                 hclgevf_misc_irq_uninit(hdev);
2450                 hclgevf_uninit_msi(hdev);
2451                 clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2452         }
2453
2454         if (!test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
2455                 pci_set_master(pdev);
2456                 ret = hclgevf_init_msi(hdev);
2457                 if (ret) {
2458                         dev_err(&pdev->dev,
2459                                 "failed(%d) to init MSI/MSI-X\n", ret);
2460                         return ret;
2461                 }
2462
2463                 ret = hclgevf_misc_irq_init(hdev);
2464                 if (ret) {
2465                         hclgevf_uninit_msi(hdev);
2466                         dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
2467                                 ret);
2468                         return ret;
2469                 }
2470
2471                 set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2472         }
2473
2474         return ret;
2475 }
2476
2477 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev)
2478 {
2479         struct pci_dev *pdev = hdev->pdev;
2480         int ret;
2481
2482         ret = hclgevf_pci_reset(hdev);
2483         if (ret) {
2484                 dev_err(&pdev->dev, "pci reset failed %d\n", ret);
2485                 return ret;
2486         }
2487
2488         ret = hclgevf_cmd_init(hdev);
2489         if (ret) {
2490                 dev_err(&pdev->dev, "cmd failed %d\n", ret);
2491                 return ret;
2492         }
2493
2494         ret = hclgevf_rss_init_hw(hdev);
2495         if (ret) {
2496                 dev_err(&hdev->pdev->dev,
2497                         "failed(%d) to initialize RSS\n", ret);
2498                 return ret;
2499         }
2500
2501         ret = hclgevf_config_gro(hdev, true);
2502         if (ret)
2503                 return ret;
2504
2505         ret = hclgevf_init_vlan_config(hdev);
2506         if (ret) {
2507                 dev_err(&hdev->pdev->dev,
2508                         "failed(%d) to initialize VLAN config\n", ret);
2509                 return ret;
2510         }
2511
2512         dev_info(&hdev->pdev->dev, "Reset done\n");
2513
2514         return 0;
2515 }
2516
2517 static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
2518 {
2519         struct pci_dev *pdev = hdev->pdev;
2520         int ret;
2521
2522         ret = hclgevf_pci_init(hdev);
2523         if (ret) {
2524                 dev_err(&pdev->dev, "PCI initialization failed\n");
2525                 return ret;
2526         }
2527
2528         ret = hclgevf_cmd_queue_init(hdev);
2529         if (ret) {
2530                 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret);
2531                 goto err_cmd_queue_init;
2532         }
2533
2534         ret = hclgevf_cmd_init(hdev);
2535         if (ret)
2536                 goto err_cmd_init;
2537
2538         /* Get vf resource */
2539         ret = hclgevf_query_vf_resource(hdev);
2540         if (ret) {
2541                 dev_err(&hdev->pdev->dev,
2542                         "Query vf status error, ret = %d.\n", ret);
2543                 goto err_cmd_init;
2544         }
2545
2546         ret = hclgevf_init_msi(hdev);
2547         if (ret) {
2548                 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
2549                 goto err_cmd_init;
2550         }
2551
2552         hclgevf_state_init(hdev);
2553         hdev->reset_level = HNAE3_VF_FUNC_RESET;
2554
2555         ret = hclgevf_misc_irq_init(hdev);
2556         if (ret) {
2557                 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
2558                         ret);
2559                 goto err_misc_irq_init;
2560         }
2561
2562         set_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2563
2564         ret = hclgevf_configure(hdev);
2565         if (ret) {
2566                 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret);
2567                 goto err_config;
2568         }
2569
2570         ret = hclgevf_alloc_tqps(hdev);
2571         if (ret) {
2572                 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);
2573                 goto err_config;
2574         }
2575
2576         ret = hclgevf_set_handle_info(hdev);
2577         if (ret) {
2578                 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret);
2579                 goto err_config;
2580         }
2581
2582         ret = hclgevf_config_gro(hdev, true);
2583         if (ret)
2584                 goto err_config;
2585
2586         /* vf is not allowed to enable unicast/multicast promisc mode.
2587          * For revision 0x20, default to disable broadcast promisc mode,
2588          * firmware makes sure broadcast packets can be accepted.
2589          * For revision 0x21, default to enable broadcast promisc mode.
2590          */
2591         ret = hclgevf_set_promisc_mode(hdev, true);
2592         if (ret)
2593                 goto err_config;
2594
2595         /* Initialize RSS for this VF */
2596         ret = hclgevf_rss_init_hw(hdev);
2597         if (ret) {
2598                 dev_err(&hdev->pdev->dev,
2599                         "failed(%d) to initialize RSS\n", ret);
2600                 goto err_config;
2601         }
2602
2603         ret = hclgevf_init_vlan_config(hdev);
2604         if (ret) {
2605                 dev_err(&hdev->pdev->dev,
2606                         "failed(%d) to initialize VLAN config\n", ret);
2607                 goto err_config;
2608         }
2609
2610         hdev->last_reset_time = jiffies;
2611         pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME);
2612
2613         return 0;
2614
2615 err_config:
2616         hclgevf_misc_irq_uninit(hdev);
2617 err_misc_irq_init:
2618         hclgevf_state_uninit(hdev);
2619         hclgevf_uninit_msi(hdev);
2620 err_cmd_init:
2621         hclgevf_cmd_uninit(hdev);
2622 err_cmd_queue_init:
2623         hclgevf_pci_uninit(hdev);
2624         clear_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state);
2625         return ret;
2626 }
2627
2628 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
2629 {
2630         hclgevf_state_uninit(hdev);
2631
2632         if (test_bit(HCLGEVF_STATE_IRQ_INITED, &hdev->state)) {
2633                 hclgevf_misc_irq_uninit(hdev);
2634                 hclgevf_uninit_msi(hdev);
2635         }
2636
2637         hclgevf_pci_uninit(hdev);
2638         hclgevf_cmd_uninit(hdev);
2639 }
2640
2641 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev)
2642 {
2643         struct pci_dev *pdev = ae_dev->pdev;
2644         struct hclgevf_dev *hdev;
2645         int ret;
2646
2647         ret = hclgevf_alloc_hdev(ae_dev);
2648         if (ret) {
2649                 dev_err(&pdev->dev, "hclge device allocation failed\n");
2650                 return ret;
2651         }
2652
2653         ret = hclgevf_init_hdev(ae_dev->priv);
2654         if (ret) {
2655                 dev_err(&pdev->dev, "hclge device initialization failed\n");
2656                 return ret;
2657         }
2658
2659         hdev = ae_dev->priv;
2660         timer_setup(&hdev->keep_alive_timer, hclgevf_keep_alive_timer, 0);
2661         INIT_WORK(&hdev->keep_alive_task, hclgevf_keep_alive_task);
2662
2663         return 0;
2664 }
2665
2666 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
2667 {
2668         struct hclgevf_dev *hdev = ae_dev->priv;
2669
2670         hclgevf_uninit_hdev(hdev);
2671         ae_dev->priv = NULL;
2672 }
2673
2674 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)
2675 {
2676         struct hnae3_handle *nic = &hdev->nic;
2677         struct hnae3_knic_private_info *kinfo = &nic->kinfo;
2678
2679         return min_t(u32, hdev->rss_size_max,
2680                      hdev->num_tqps / kinfo->num_tc);
2681 }
2682
2683 /**
2684  * hclgevf_get_channels - Get the current channels enabled and max supported.
2685  * @handle: hardware information for network interface
2686  * @ch: ethtool channels structure
2687  *
2688  * We don't support separate tx and rx queues as channels. The other count
2689  * represents how many queues are being used for control. max_combined counts
2690  * how many queue pairs we can support. They may not be mapped 1 to 1 with
2691  * q_vectors since we support a lot more queue pairs than q_vectors.
2692  **/
2693 static void hclgevf_get_channels(struct hnae3_handle *handle,
2694                                  struct ethtool_channels *ch)
2695 {
2696         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2697
2698         ch->max_combined = hclgevf_get_max_channels(hdev);
2699         ch->other_count = 0;
2700         ch->max_other = 0;
2701         ch->combined_count = handle->kinfo.rss_size;
2702 }
2703
2704 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,
2705                                           u16 *alloc_tqps, u16 *max_rss_size)
2706 {
2707         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2708
2709         *alloc_tqps = hdev->num_tqps;
2710         *max_rss_size = hdev->rss_size_max;
2711 }
2712
2713 static int hclgevf_get_status(struct hnae3_handle *handle)
2714 {
2715         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2716
2717         return hdev->hw.mac.link;
2718 }
2719
2720 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
2721                                             u8 *auto_neg, u32 *speed,
2722                                             u8 *duplex)
2723 {
2724         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2725
2726         if (speed)
2727                 *speed = hdev->hw.mac.speed;
2728         if (duplex)
2729                 *duplex = hdev->hw.mac.duplex;
2730         if (auto_neg)
2731                 *auto_neg = AUTONEG_DISABLE;
2732 }
2733
2734 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
2735                                  u8 duplex)
2736 {
2737         hdev->hw.mac.speed = speed;
2738         hdev->hw.mac.duplex = duplex;
2739 }
2740
2741 static int hclgevf_gro_en(struct hnae3_handle *handle, bool enable)
2742 {
2743         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2744
2745         return hclgevf_config_gro(hdev, enable);
2746 }
2747
2748 static void hclgevf_get_media_type(struct hnae3_handle *handle,
2749                                   u8 *media_type)
2750 {
2751         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2752         if (media_type)
2753                 *media_type = hdev->hw.mac.media_type;
2754 }
2755
2756 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle)
2757 {
2758         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2759
2760         return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING);
2761 }
2762
2763 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle)
2764 {
2765         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2766
2767         return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2768 }
2769
2770 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle)
2771 {
2772         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2773
2774         return hdev->rst_stats.hw_rst_done_cnt;
2775 }
2776
2777 static void hclgevf_get_link_mode(struct hnae3_handle *handle,
2778                                   unsigned long *supported,
2779                                   unsigned long *advertising)
2780 {
2781         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2782
2783         *supported = hdev->hw.mac.supported;
2784         *advertising = hdev->hw.mac.advertising;
2785 }
2786
2787 #define MAX_SEPARATE_NUM        4
2788 #define SEPARATOR_VALUE         0xFFFFFFFF
2789 #define REG_NUM_PER_LINE        4
2790 #define REG_LEN_PER_LINE        (REG_NUM_PER_LINE * sizeof(u32))
2791
2792 static int hclgevf_get_regs_len(struct hnae3_handle *handle)
2793 {
2794         int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
2795         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2796
2797         cmdq_lines = sizeof(cmdq_reg_addr_list) / REG_LEN_PER_LINE + 1;
2798         common_lines = sizeof(common_reg_addr_list) / REG_LEN_PER_LINE + 1;
2799         ring_lines = sizeof(ring_reg_addr_list) / REG_LEN_PER_LINE + 1;
2800         tqp_intr_lines = sizeof(tqp_intr_reg_addr_list) / REG_LEN_PER_LINE + 1;
2801
2802         return (cmdq_lines + common_lines + ring_lines * hdev->num_tqps +
2803                 tqp_intr_lines * (hdev->num_msi_used - 1)) * REG_LEN_PER_LINE;
2804 }
2805
2806 static void hclgevf_get_regs(struct hnae3_handle *handle, u32 *version,
2807                              void *data)
2808 {
2809         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2810         int i, j, reg_um, separator_num;
2811         u32 *reg = data;
2812
2813         *version = hdev->fw_version;
2814
2815         /* fetching per-VF registers values from VF PCIe register space */
2816         reg_um = sizeof(cmdq_reg_addr_list) / sizeof(u32);
2817         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
2818         for (i = 0; i < reg_um; i++)
2819                 *reg++ = hclgevf_read_dev(&hdev->hw, cmdq_reg_addr_list[i]);
2820         for (i = 0; i < separator_num; i++)
2821                 *reg++ = SEPARATOR_VALUE;
2822
2823         reg_um = sizeof(common_reg_addr_list) / sizeof(u32);
2824         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
2825         for (i = 0; i < reg_um; i++)
2826                 *reg++ = hclgevf_read_dev(&hdev->hw, common_reg_addr_list[i]);
2827         for (i = 0; i < separator_num; i++)
2828                 *reg++ = SEPARATOR_VALUE;
2829
2830         reg_um = sizeof(ring_reg_addr_list) / sizeof(u32);
2831         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
2832         for (j = 0; j < hdev->num_tqps; j++) {
2833                 for (i = 0; i < reg_um; i++)
2834                         *reg++ = hclgevf_read_dev(&hdev->hw,
2835                                                   ring_reg_addr_list[i] +
2836                                                   0x200 * j);
2837                 for (i = 0; i < separator_num; i++)
2838                         *reg++ = SEPARATOR_VALUE;
2839         }
2840
2841         reg_um = sizeof(tqp_intr_reg_addr_list) / sizeof(u32);
2842         separator_num = MAX_SEPARATE_NUM - reg_um % REG_NUM_PER_LINE;
2843         for (j = 0; j < hdev->num_msi_used - 1; j++) {
2844                 for (i = 0; i < reg_um; i++)
2845                         *reg++ = hclgevf_read_dev(&hdev->hw,
2846                                                   tqp_intr_reg_addr_list[i] +
2847                                                   4 * j);
2848                 for (i = 0; i < separator_num; i++)
2849                         *reg++ = SEPARATOR_VALUE;
2850         }
2851 }
2852
2853 void hclgevf_update_port_base_vlan_info(struct hclgevf_dev *hdev, u16 state,
2854                                         u8 *port_base_vlan_info, u8 data_size)
2855 {
2856         struct hnae3_handle *nic = &hdev->nic;
2857
2858         rtnl_lock();
2859         hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
2860         rtnl_unlock();
2861
2862         /* send msg to PF and wait update port based vlan info */
2863         hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN,
2864                              HCLGE_MBX_PORT_BASE_VLAN_CFG,
2865                              port_base_vlan_info, data_size,
2866                              false, NULL, 0);
2867
2868         if (state == HNAE3_PORT_BASE_VLAN_DISABLE)
2869                 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_DISABLE;
2870         else
2871                 nic->port_base_vlan_state = HNAE3_PORT_BASE_VLAN_ENABLE;
2872
2873         rtnl_lock();
2874         hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
2875         rtnl_unlock();
2876 }
2877
2878 static const struct hnae3_ae_ops hclgevf_ops = {
2879         .init_ae_dev = hclgevf_init_ae_dev,
2880         .uninit_ae_dev = hclgevf_uninit_ae_dev,
2881         .flr_prepare = hclgevf_flr_prepare,
2882         .flr_done = hclgevf_flr_done,
2883         .init_client_instance = hclgevf_init_client_instance,
2884         .uninit_client_instance = hclgevf_uninit_client_instance,
2885         .start = hclgevf_ae_start,
2886         .stop = hclgevf_ae_stop,
2887         .client_start = hclgevf_client_start,
2888         .client_stop = hclgevf_client_stop,
2889         .map_ring_to_vector = hclgevf_map_ring_to_vector,
2890         .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector,
2891         .get_vector = hclgevf_get_vector,
2892         .put_vector = hclgevf_put_vector,
2893         .reset_queue = hclgevf_reset_tqp,
2894         .get_mac_addr = hclgevf_get_mac_addr,
2895         .set_mac_addr = hclgevf_set_mac_addr,
2896         .add_uc_addr = hclgevf_add_uc_addr,
2897         .rm_uc_addr = hclgevf_rm_uc_addr,
2898         .add_mc_addr = hclgevf_add_mc_addr,
2899         .rm_mc_addr = hclgevf_rm_mc_addr,
2900         .get_stats = hclgevf_get_stats,
2901         .update_stats = hclgevf_update_stats,
2902         .get_strings = hclgevf_get_strings,
2903         .get_sset_count = hclgevf_get_sset_count,
2904         .get_rss_key_size = hclgevf_get_rss_key_size,
2905         .get_rss_indir_size = hclgevf_get_rss_indir_size,
2906         .get_rss = hclgevf_get_rss,
2907         .set_rss = hclgevf_set_rss,
2908         .get_rss_tuple = hclgevf_get_rss_tuple,
2909         .set_rss_tuple = hclgevf_set_rss_tuple,
2910         .get_tc_size = hclgevf_get_tc_size,
2911         .get_fw_version = hclgevf_get_fw_version,
2912         .set_vlan_filter = hclgevf_set_vlan_filter,
2913         .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag,
2914         .reset_event = hclgevf_reset_event,
2915         .set_default_reset_request = hclgevf_set_def_reset_request,
2916         .get_channels = hclgevf_get_channels,
2917         .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
2918         .get_regs_len = hclgevf_get_regs_len,
2919         .get_regs = hclgevf_get_regs,
2920         .get_status = hclgevf_get_status,
2921         .get_ksettings_an_result = hclgevf_get_ksettings_an_result,
2922         .get_media_type = hclgevf_get_media_type,
2923         .get_hw_reset_stat = hclgevf_get_hw_reset_stat,
2924         .ae_dev_resetting = hclgevf_ae_dev_resetting,
2925         .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt,
2926         .set_gro_en = hclgevf_gro_en,
2927         .set_mtu = hclgevf_set_mtu,
2928         .get_global_queue_id = hclgevf_get_qid_global,
2929         .set_timer_task = hclgevf_set_timer_task,
2930         .get_link_mode = hclgevf_get_link_mode,
2931 };
2932
2933 static struct hnae3_ae_algo ae_algovf = {
2934         .ops = &hclgevf_ops,
2935         .pdev_id_table = ae_algovf_pci_tbl,
2936 };
2937
2938 static int hclgevf_init(void)
2939 {
2940         pr_info("%s is initializing\n", HCLGEVF_NAME);
2941
2942         hnae3_register_ae_algo(&ae_algovf);
2943
2944         return 0;
2945 }
2946
2947 static void hclgevf_exit(void)
2948 {
2949         hnae3_unregister_ae_algo(&ae_algovf);
2950 }
2951 module_init(hclgevf_init);
2952 module_exit(hclgevf_exit);
2953
2954 MODULE_LICENSE("GPL");
2955 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
2956 MODULE_DESCRIPTION("HCLGEVF Driver");
2957 MODULE_VERSION(HCLGEVF_MOD_VERSION);