drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4 #include <linux/etherdevice.h>
   5 #include <net/rtnetlink.h>
   6 #include "hclgevf_cmd.h"
   7 #include "hclgevf_main.h"
   8 #include "hclge_mbx.h"
   9 #include "hnae3.h"
  10
  11 #define HCLGEVF_NAME    "hclgevf"
  12
  13 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev);
  14 static struct hnae3_ae_algo ae_algovf;
  15
  16 static const struct pci_device_id ae_algovf_pci_tbl[] = {
  17         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
  18         {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0},
  19         /* required last entry */
  20         {0, }
  21 };
  22
  23 MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
  24
  25 static inline struct hclgevf_dev *hclgevf_ae_get_hdev(
  26         struct hnae3_handle *handle)
  27 {
  28         return container_of(handle, struct hclgevf_dev, nic);
  29 }
  30
  31 static int hclgevf_tqps_update_stats(struct hnae3_handle *handle)
  32 {
  33         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
  34         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
  35         struct hclgevf_desc desc;
  36         struct hclgevf_tqp *tqp;
  37         int status;
  38         int i;
  39
  40         for (i = 0; i < kinfo->num_tqps; i++) {
  41                 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
  42                 hclgevf_cmd_setup_basic_desc(&desc,
  43                                              HCLGEVF_OPC_QUERY_RX_STATUS,
  44                                              true);
  45
  46                 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
  47                 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
  48                 if (status) {
  49                         dev_err(&hdev->pdev->dev,
  50                                 "Query tqp stat fail, status = %d,queue = %d\n",
  51                                 status, i);
  52                         return status;
  53                 }
  54                 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
  55                         le32_to_cpu(desc.data[1]);
  56
  57                 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS,
  58                                              true);
  59
  60                 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
  61                 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
  62                 if (status) {
  63                         dev_err(&hdev->pdev->dev,
  64                                 "Query tqp stat fail, status = %d,queue = %d\n",
  65                                 status, i);
  66                         return status;
  67                 }
  68                 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
  69                         le32_to_cpu(desc.data[1]);
  70         }
  71
  72         return 0;
  73 }
  74
  75 static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
  76 {
  77         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
  78         struct hclgevf_tqp *tqp;
  79         u64 *buff = data;
  80         int i;
  81
  82         for (i = 0; i < kinfo->num_tqps; i++) {
  83                 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
  84                 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
  85         }
  86         for (i = 0; i < kinfo->num_tqps; i++) {
  87                 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
  88                 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
  89         }
  90
  91         return buff;
  92 }
  93
  94 static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset)
  95 {
  96         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
  97
  98         return kinfo->num_tqps * 2;
  99 }
 100
 101 static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
 102 {
 103         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 104         u8 *buff = data;
 105         int i = 0;
 106
 107         for (i = 0; i < kinfo->num_tqps; i++) {
 108                 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
 109                                                        struct hclgevf_tqp, q);
 110                 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
 111                          tqp->index);
 112                 buff += ETH_GSTRING_LEN;
 113         }
 114
 115         for (i = 0; i < kinfo->num_tqps; i++) {
 116                 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
 117                                                        struct hclgevf_tqp, q);
 118                 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
 119                          tqp->index);
 120                 buff += ETH_GSTRING_LEN;
 121         }
 122
 123         return buff;
 124 }
 125
 126 static void hclgevf_update_stats(struct hnae3_handle *handle,
 127                                  struct net_device_stats *net_stats)
 128 {
 129         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 130         int status;
 131
 132         status = hclgevf_tqps_update_stats(handle);
 133         if (status)
 134                 dev_err(&hdev->pdev->dev,
 135                         "VF update of TQPS stats fail, status = %d.\n",
 136                         status);
 137 }
 138
 139 static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset)
 140 {
 141         if (strset == ETH_SS_TEST)
 142                 return -EOPNOTSUPP;
 143         else if (strset == ETH_SS_STATS)
 144                 return hclgevf_tqps_get_sset_count(handle, strset);
 145
 146         return 0;
 147 }
 148
 149 static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset,
 150                                 u8 *data)
 151 {
 152         u8 *p = (char *)data;
 153
 154         if (strset == ETH_SS_STATS)
 155                 p = hclgevf_tqps_get_strings(handle, p);
 156 }
 157
 158 static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data)
 159 {
 160         hclgevf_tqps_get_stats(handle, data);
 161 }
 162
 163 static int hclgevf_get_tc_info(struct hclgevf_dev *hdev)
 164 {
 165         u8 resp_msg;
 166         int status;
 167
 168         status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0,
 169                                       true, &resp_msg, sizeof(u8));
 170         if (status) {
 171                 dev_err(&hdev->pdev->dev,
 172                         "VF request to get TC info from PF failed %d",
 173                         status);
 174                 return status;
 175         }
 176
 177         hdev->hw_tc_map = resp_msg;
 178
 179         return 0;
 180 }
 181
 182 static int hclgevf_get_queue_info(struct hclgevf_dev *hdev)
 183 {
 184 #define HCLGEVF_TQPS_RSS_INFO_LEN       8
 185         u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN];
 186         int status;
 187
 188         status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0,
 189                                       true, resp_msg,
 190                                       HCLGEVF_TQPS_RSS_INFO_LEN);
 191         if (status) {
 192                 dev_err(&hdev->pdev->dev,
 193                         "VF request to get tqp info from PF failed %d",
 194                         status);
 195                 return status;
 196         }
 197
 198         memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16));
 199         memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16));
 200         memcpy(&hdev->num_desc, &resp_msg[4], sizeof(u16));
 201         memcpy(&hdev->rx_buf_len, &resp_msg[6], sizeof(u16));
 202
 203         return 0;
 204 }
 205
 206 static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
 207 {
 208         struct hclgevf_tqp *tqp;
 209         int i;
 210
 211         hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
 212                                   sizeof(struct hclgevf_tqp), GFP_KERNEL);
 213         if (!hdev->htqp)
 214                 return -ENOMEM;
 215
 216         tqp = hdev->htqp;
 217
 218         for (i = 0; i < hdev->num_tqps; i++) {
 219                 tqp->dev = &hdev->pdev->dev;
 220                 tqp->index = i;
 221
 222                 tqp->q.ae_algo = &ae_algovf;
 223                 tqp->q.buf_size = hdev->rx_buf_len;
 224                 tqp->q.desc_num = hdev->num_desc;
 225                 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET +
 226                         i * HCLGEVF_TQP_REG_SIZE;
 227
 228                 tqp++;
 229         }
 230
 231         return 0;
 232 }
 233
 234 static int hclgevf_knic_setup(struct hclgevf_dev *hdev)
 235 {
 236         struct hnae3_handle *nic = &hdev->nic;
 237         struct hnae3_knic_private_info *kinfo;
 238         u16 new_tqps = hdev->num_tqps;
 239         int i;
 240
 241         kinfo = &nic->kinfo;
 242         kinfo->num_tc = 0;
 243         kinfo->num_desc = hdev->num_desc;
 244         kinfo->rx_buf_len = hdev->rx_buf_len;
 245         for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++)
 246                 if (hdev->hw_tc_map & BIT(i))
 247                         kinfo->num_tc++;
 248
 249         kinfo->rss_size
 250                 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc);
 251         new_tqps = kinfo->rss_size * kinfo->num_tc;
 252         kinfo->num_tqps = min(new_tqps, hdev->num_tqps);
 253
 254         kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
 255                                   sizeof(struct hnae3_queue *), GFP_KERNEL);
 256         if (!kinfo->tqp)
 257                 return -ENOMEM;
 258
 259         for (i = 0; i < kinfo->num_tqps; i++) {
 260                 hdev->htqp[i].q.handle = &hdev->nic;
 261                 hdev->htqp[i].q.tqp_index = i;
 262                 kinfo->tqp[i] = &hdev->htqp[i].q;
 263         }
 264
 265         return 0;
 266 }
 267
 268 static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
 269 {
 270         int status;
 271         u8 resp_msg;
 272
 273         status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL,
 274                                       0, false, &resp_msg, sizeof(u8));
 275         if (status)
 276                 dev_err(&hdev->pdev->dev,
 277                         "VF failed to fetch link status(%d) from PF", status);
 278 }
 279
 280 void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
 281 {
 282         struct hnae3_handle *handle = &hdev->nic;
 283         struct hnae3_client *client;
 284
 285         client = handle->client;
 286
 287         link_state =
 288                 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state;
 289
 290         if (link_state != hdev->hw.mac.link) {
 291                 client->ops->link_status_change(handle, !!link_state);
 292                 hdev->hw.mac.link = link_state;
 293         }
 294 }
 295
 296 static int hclgevf_set_handle_info(struct hclgevf_dev *hdev)
 297 {
 298         struct hnae3_handle *nic = &hdev->nic;
 299         int ret;
 300
 301         nic->ae_algo = &ae_algovf;
 302         nic->pdev = hdev->pdev;
 303         nic->numa_node_mask = hdev->numa_node_mask;
 304         nic->flags |= HNAE3_SUPPORT_VF;
 305
 306         if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) {
 307                 dev_err(&hdev->pdev->dev, "unsupported device type %d\n",
 308                         hdev->ae_dev->dev_type);
 309                 return -EINVAL;
 310         }
 311
 312         ret = hclgevf_knic_setup(hdev);
 313         if (ret)
 314                 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n",
 315                         ret);
 316         return ret;
 317 }
 318
 319 static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id)
 320 {
 321         if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) {
 322                 dev_warn(&hdev->pdev->dev,
 323                          "vector(vector_id %d) has been freed.\n", vector_id);
 324                 return;
 325         }
 326
 327         hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT;
 328         hdev->num_msi_left += 1;
 329         hdev->num_msi_used -= 1;
 330 }
 331
 332 static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,
 333                               struct hnae3_vector_info *vector_info)
 334 {
 335         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 336         struct hnae3_vector_info *vector = vector_info;
 337         int alloc = 0;
 338         int i, j;
 339
 340         vector_num = min(hdev->num_msi_left, vector_num);
 341
 342         for (j = 0; j < vector_num; j++) {
 343                 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {
 344                         if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {
 345                                 vector->vector = pci_irq_vector(hdev->pdev, i);
 346                                 vector->io_addr = hdev->hw.io_base +
 347                                         HCLGEVF_VECTOR_REG_BASE +
 348                                         (i - 1) * HCLGEVF_VECTOR_REG_OFFSET;
 349                                 hdev->vector_status[i] = 0;
 350                                 hdev->vector_irq[i] = vector->vector;
 351
 352                                 vector++;
 353                                 alloc++;
 354
 355                                 break;
 356                         }
 357                 }
 358         }
 359         hdev->num_msi_left -= alloc;
 360         hdev->num_msi_used += alloc;
 361
 362         return alloc;
 363 }
 364
 365 static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector)
 366 {
 367         int i;
 368
 369         for (i = 0; i < hdev->num_msi; i++)
 370                 if (vector == hdev->vector_irq[i])
 371                         return i;
 372
 373         return -EINVAL;
 374 }
 375
 376 static int hclgevf_set_rss_algo_key(struct hclgevf_dev *hdev,
 377                                     const u8 hfunc, const u8 *key)
 378 {
 379         struct hclgevf_rss_config_cmd *req;
 380         struct hclgevf_desc desc;
 381         int key_offset;
 382         int key_size;
 383         int ret;
 384
 385         req = (struct hclgevf_rss_config_cmd *)desc.data;
 386
 387         for (key_offset = 0; key_offset < 3; key_offset++) {
 388                 hclgevf_cmd_setup_basic_desc(&desc,
 389                                              HCLGEVF_OPC_RSS_GENERIC_CONFIG,
 390                                              false);
 391
 392                 req->hash_config |= (hfunc & HCLGEVF_RSS_HASH_ALGO_MASK);
 393                 req->hash_config |=
 394                         (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET_B);
 395
 396                 if (key_offset == 2)
 397                         key_size =
 398                         HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2;
 399                 else
 400                         key_size = HCLGEVF_RSS_HASH_KEY_NUM;
 401
 402                 memcpy(req->hash_key,
 403                        key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM, key_size);
 404
 405                 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 406                 if (ret) {
 407                         dev_err(&hdev->pdev->dev,
 408                                 "Configure RSS config fail, status = %d\n",
 409                                 ret);
 410                         return ret;
 411                 }
 412         }
 413
 414         return 0;
 415 }
 416
 417 static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle)
 418 {
 419         return HCLGEVF_RSS_KEY_SIZE;
 420 }
 421
 422 static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle)
 423 {
 424         return HCLGEVF_RSS_IND_TBL_SIZE;
 425 }
 426
 427 static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev)
 428 {
 429         const u8 *indir = hdev->rss_cfg.rss_indirection_tbl;
 430         struct hclgevf_rss_indirection_table_cmd *req;
 431         struct hclgevf_desc desc;
 432         int status;
 433         int i, j;
 434
 435         req = (struct hclgevf_rss_indirection_table_cmd *)desc.data;
 436
 437         for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) {
 438                 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE,
 439                                              false);
 440                 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE;
 441                 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK;
 442                 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++)
 443                         req->rss_result[j] =
 444                                 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j];
 445
 446                 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 447                 if (status) {
 448                         dev_err(&hdev->pdev->dev,
 449                                 "VF failed(=%d) to set RSS indirection table\n",
 450                                 status);
 451                         return status;
 452                 }
 453         }
 454
 455         return 0;
 456 }
 457
 458 static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev,  u16 rss_size)
 459 {
 460         struct hclgevf_rss_tc_mode_cmd *req;
 461         u16 tc_offset[HCLGEVF_MAX_TC_NUM];
 462         u16 tc_valid[HCLGEVF_MAX_TC_NUM];
 463         u16 tc_size[HCLGEVF_MAX_TC_NUM];
 464         struct hclgevf_desc desc;
 465         u16 roundup_size;
 466         int status;
 467         int i;
 468
 469         req = (struct hclgevf_rss_tc_mode_cmd *)desc.data;
 470
 471         roundup_size = roundup_pow_of_two(rss_size);
 472         roundup_size = ilog2(roundup_size);
 473
 474         for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
 475                 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i));
 476                 tc_size[i] = roundup_size;
 477                 tc_offset[i] = rss_size * i;
 478         }
 479
 480         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false);
 481         for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
 482                 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B,
 483                               (tc_valid[i] & 0x1));
 484                 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M,
 485                                 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]);
 486                 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M,
 487                                 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]);
 488         }
 489         status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 490         if (status)
 491                 dev_err(&hdev->pdev->dev,
 492                         "VF failed(=%d) to set rss tc mode\n", status);
 493
 494         return status;
 495 }
 496
 497 static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,
 498                            u8 *hfunc)
 499 {
 500         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 501         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
 502         int i;
 503
 504         if (handle->pdev->revision >= 0x21) {
 505                 /* Get hash algorithm */
 506                 if (hfunc) {
 507                         switch (rss_cfg->hash_algo) {
 508                         case HCLGEVF_RSS_HASH_ALGO_TOEPLITZ:
 509                                 *hfunc = ETH_RSS_HASH_TOP;
 510                                 break;
 511                         case HCLGEVF_RSS_HASH_ALGO_SIMPLE:
 512                                 *hfunc = ETH_RSS_HASH_XOR;
 513                                 break;
 514                         default:
 515                                 *hfunc = ETH_RSS_HASH_UNKNOWN;
 516                                 break;
 517                         }
 518                 }
 519
 520                 /* Get the RSS Key required by the user */
 521                 if (key)
 522                         memcpy(key, rss_cfg->rss_hash_key,
 523                                HCLGEVF_RSS_KEY_SIZE);
 524         }
 525
 526         if (indir)
 527                 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
 528                         indir[i] = rss_cfg->rss_indirection_tbl[i];
 529
 530         return 0;
 531 }
 532
 533 static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
 534                            const  u8 *key, const  u8 hfunc)
 535 {
 536         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 537         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
 538         int ret, i;
 539
 540         if (handle->pdev->revision >= 0x21) {
 541                 /* Set the RSS Hash Key if specififed by the user */
 542                 if (key) {
 543                         switch (hfunc) {
 544                         case ETH_RSS_HASH_TOP:
 545                                 rss_cfg->hash_algo =
 546                                         HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
 547                                 break;
 548                         case ETH_RSS_HASH_XOR:
 549                                 rss_cfg->hash_algo =
 550                                         HCLGEVF_RSS_HASH_ALGO_SIMPLE;
 551                                 break;
 552                         case ETH_RSS_HASH_NO_CHANGE:
 553                                 break;
 554                         default:
 555                                 return -EINVAL;
 556                         }
 557
 558                         ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
 559                                                        key);
 560                         if (ret)
 561                                 return ret;
 562
 563                         /* Update the shadow RSS key with user specified qids */
 564                         memcpy(rss_cfg->rss_hash_key, key,
 565                                HCLGEVF_RSS_KEY_SIZE);
 566                 }
 567         }
 568
 569         /* update the shadow RSS table with user specified qids */
 570         for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
 571                 rss_cfg->rss_indirection_tbl[i] = indir[i];
 572
 573         /* update the hardware */
 574         return hclgevf_set_rss_indir_table(hdev);
 575 }
 576
 577 static u8 hclgevf_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
 578 {
 579         u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGEVF_S_PORT_BIT : 0;
 580
 581         if (nfc->data & RXH_L4_B_2_3)
 582                 hash_sets |= HCLGEVF_D_PORT_BIT;
 583         else
 584                 hash_sets &= ~HCLGEVF_D_PORT_BIT;
 585
 586         if (nfc->data & RXH_IP_SRC)
 587                 hash_sets |= HCLGEVF_S_IP_BIT;
 588         else
 589                 hash_sets &= ~HCLGEVF_S_IP_BIT;
 590
 591         if (nfc->data & RXH_IP_DST)
 592                 hash_sets |= HCLGEVF_D_IP_BIT;
 593         else
 594                 hash_sets &= ~HCLGEVF_D_IP_BIT;
 595
 596         if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
 597                 hash_sets |= HCLGEVF_V_TAG_BIT;
 598
 599         return hash_sets;
 600 }
 601
 602 static int hclgevf_set_rss_tuple(struct hnae3_handle *handle,
 603                                  struct ethtool_rxnfc *nfc)
 604 {
 605         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 606         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
 607         struct hclgevf_rss_input_tuple_cmd *req;
 608         struct hclgevf_desc desc;
 609         u8 tuple_sets;
 610         int ret;
 611
 612         if (handle->pdev->revision == 0x20)
 613                 return -EOPNOTSUPP;
 614
 615         if (nfc->data &
 616             ~(RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 | RXH_L4_B_2_3))
 617                 return -EINVAL;
 618
 619         req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
 620         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
 621
 622         req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
 623         req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
 624         req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
 625         req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
 626         req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
 627         req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
 628         req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
 629         req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
 630
 631         tuple_sets = hclgevf_get_rss_hash_bits(nfc);
 632         switch (nfc->flow_type) {
 633         case TCP_V4_FLOW:
 634                 req->ipv4_tcp_en = tuple_sets;
 635                 break;
 636         case TCP_V6_FLOW:
 637                 req->ipv6_tcp_en = tuple_sets;
 638                 break;
 639         case UDP_V4_FLOW:
 640                 req->ipv4_udp_en = tuple_sets;
 641                 break;
 642         case UDP_V6_FLOW:
 643                 req->ipv6_udp_en = tuple_sets;
 644                 break;
 645         case SCTP_V4_FLOW:
 646                 req->ipv4_sctp_en = tuple_sets;
 647                 break;
 648         case SCTP_V6_FLOW:
 649                 if ((nfc->data & RXH_L4_B_0_1) ||
 650                     (nfc->data & RXH_L4_B_2_3))
 651                         return -EINVAL;
 652
 653                 req->ipv6_sctp_en = tuple_sets;
 654                 break;
 655         case IPV4_FLOW:
 656                 req->ipv4_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
 657                 break;
 658         case IPV6_FLOW:
 659                 req->ipv6_fragment_en = HCLGEVF_RSS_INPUT_TUPLE_OTHER;
 660                 break;
 661         default:
 662                 return -EINVAL;
 663         }
 664
 665         ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 666         if (ret) {
 667                 dev_err(&hdev->pdev->dev,
 668                         "Set rss tuple fail, status = %d\n", ret);
 669                 return ret;
 670         }
 671
 672         rss_cfg->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
 673         rss_cfg->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
 674         rss_cfg->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
 675         rss_cfg->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
 676         rss_cfg->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
 677         rss_cfg->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
 678         rss_cfg->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
 679         rss_cfg->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
 680         return 0;
 681 }
 682
 683 static int hclgevf_get_rss_tuple(struct hnae3_handle *handle,
 684                                  struct ethtool_rxnfc *nfc)
 685 {
 686         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 687         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
 688         u8 tuple_sets;
 689
 690         if (handle->pdev->revision == 0x20)
 691                 return -EOPNOTSUPP;
 692
 693         nfc->data = 0;
 694
 695         switch (nfc->flow_type) {
 696         case TCP_V4_FLOW:
 697                 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
 698                 break;
 699         case UDP_V4_FLOW:
 700                 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_udp_en;
 701                 break;
 702         case TCP_V6_FLOW:
 703                 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
 704                 break;
 705         case UDP_V6_FLOW:
 706                 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_udp_en;
 707                 break;
 708         case SCTP_V4_FLOW:
 709                 tuple_sets = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
 710                 break;
 711         case SCTP_V6_FLOW:
 712                 tuple_sets = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
 713                 break;
 714         case IPV4_FLOW:
 715         case IPV6_FLOW:
 716                 tuple_sets = HCLGEVF_S_IP_BIT | HCLGEVF_D_IP_BIT;
 717                 break;
 718         default:
 719                 return -EINVAL;
 720         }
 721
 722         if (!tuple_sets)
 723                 return 0;
 724
 725         if (tuple_sets & HCLGEVF_D_PORT_BIT)
 726                 nfc->data |= RXH_L4_B_2_3;
 727         if (tuple_sets & HCLGEVF_S_PORT_BIT)
 728                 nfc->data |= RXH_L4_B_0_1;
 729         if (tuple_sets & HCLGEVF_D_IP_BIT)
 730                 nfc->data |= RXH_IP_DST;
 731         if (tuple_sets & HCLGEVF_S_IP_BIT)
 732                 nfc->data |= RXH_IP_SRC;
 733
 734         return 0;
 735 }
 736
 737 static int hclgevf_set_rss_input_tuple(struct hclgevf_dev *hdev,
 738                                        struct hclgevf_rss_cfg *rss_cfg)
 739 {
 740         struct hclgevf_rss_input_tuple_cmd *req;
 741         struct hclgevf_desc desc;
 742         int ret;
 743
 744         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INPUT_TUPLE, false);
 745
 746         req = (struct hclgevf_rss_input_tuple_cmd *)desc.data;
 747
 748         req->ipv4_tcp_en = rss_cfg->rss_tuple_sets.ipv4_tcp_en;
 749         req->ipv4_udp_en = rss_cfg->rss_tuple_sets.ipv4_udp_en;
 750         req->ipv4_sctp_en = rss_cfg->rss_tuple_sets.ipv4_sctp_en;
 751         req->ipv4_fragment_en = rss_cfg->rss_tuple_sets.ipv4_fragment_en;
 752         req->ipv6_tcp_en = rss_cfg->rss_tuple_sets.ipv6_tcp_en;
 753         req->ipv6_udp_en = rss_cfg->rss_tuple_sets.ipv6_udp_en;
 754         req->ipv6_sctp_en = rss_cfg->rss_tuple_sets.ipv6_sctp_en;
 755         req->ipv6_fragment_en = rss_cfg->rss_tuple_sets.ipv6_fragment_en;
 756
 757         ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 758         if (ret)
 759                 dev_err(&hdev->pdev->dev,
 760                         "Configure rss input fail, status = %d\n", ret);
 761         return ret;
 762 }
 763
 764 static int hclgevf_get_tc_size(struct hnae3_handle *handle)
 765 {
 766         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 767         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
 768
 769         return rss_cfg->rss_size;
 770 }
 771
 772 static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en,
 773                                        int vector_id,
 774                                        struct hnae3_ring_chain_node *ring_chain)
 775 {
 776         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 777         struct hnae3_ring_chain_node *node;
 778         struct hclge_mbx_vf_to_pf_cmd *req;
 779         struct hclgevf_desc desc;
 780         int i = 0;
 781         int status;
 782         u8 type;
 783
 784         req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data;
 785
 786         for (node = ring_chain; node; node = node->next) {
 787                 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM +
 788                                         HCLGE_MBX_RING_NODE_VARIABLE_NUM * i;
 789
 790                 if (i == 0) {
 791                         hclgevf_cmd_setup_basic_desc(&desc,
 792                                                      HCLGEVF_OPC_MBX_VF_TO_PF,
 793                                                      false);
 794                         type = en ?
 795                                 HCLGE_MBX_MAP_RING_TO_VECTOR :
 796                                 HCLGE_MBX_UNMAP_RING_TO_VECTOR;
 797                         req->msg[0] = type;
 798                         req->msg[1] = vector_id;
 799                 }
 800
 801                 req->msg[idx_offset] =
 802                                 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B);
 803                 req->msg[idx_offset + 1] = node->tqp_index;
 804                 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx,
 805                                                            HNAE3_RING_GL_IDX_M,
 806                                                            HNAE3_RING_GL_IDX_S);
 807
 808                 i++;
 809                 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM -
 810                      HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) /
 811                      HCLGE_MBX_RING_NODE_VARIABLE_NUM) ||
 812                     !node->next) {
 813                         req->msg[2] = i;
 814
 815                         status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 816                         if (status) {
 817                                 dev_err(&hdev->pdev->dev,
 818                                         "Map TQP fail, status is %d.\n",
 819                                         status);
 820                                 return status;
 821                         }
 822                         i = 0;
 823                         hclgevf_cmd_setup_basic_desc(&desc,
 824                                                      HCLGEVF_OPC_MBX_VF_TO_PF,
 825                                                      false);
 826                         req->msg[0] = type;
 827                         req->msg[1] = vector_id;
 828                 }
 829         }
 830
 831         return 0;
 832 }
 833
 834 static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector,
 835                                       struct hnae3_ring_chain_node *ring_chain)
 836 {
 837         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 838         int vector_id;
 839
 840         vector_id = hclgevf_get_vector_index(hdev, vector);
 841         if (vector_id < 0) {
 842                 dev_err(&handle->pdev->dev,
 843                         "Get vector index fail. ret =%d\n", vector_id);
 844                 return vector_id;
 845         }
 846
 847         return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain);
 848 }
 849
 850 static int hclgevf_unmap_ring_from_vector(
 851                                 struct hnae3_handle *handle,
 852                                 int vector,
 853                                 struct hnae3_ring_chain_node *ring_chain)
 854 {
 855         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 856         int ret, vector_id;
 857
 858         if (test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
 859                 return 0;
 860
 861         vector_id = hclgevf_get_vector_index(hdev, vector);
 862         if (vector_id < 0) {
 863                 dev_err(&handle->pdev->dev,
 864                         "Get vector index fail. ret =%d\n", vector_id);
 865                 return vector_id;
 866         }
 867
 868         ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain);
 869         if (ret)
 870                 dev_err(&handle->pdev->dev,
 871                         "Unmap ring from vector fail. vector=%d, ret =%d\n",
 872                         vector_id,
 873                         ret);
 874
 875         return ret;
 876 }
 877
 878 static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)
 879 {
 880         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 881         int vector_id;
 882
 883         vector_id = hclgevf_get_vector_index(hdev, vector);
 884         if (vector_id < 0) {
 885                 dev_err(&handle->pdev->dev,
 886                         "hclgevf_put_vector get vector index fail. ret =%d\n",
 887                         vector_id);
 888                 return vector_id;
 889         }
 890
 891         hclgevf_free_vector(hdev, vector_id);
 892
 893         return 0;
 894 }
 895
 896 static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
 897                                         bool en_uc_pmc, bool en_mc_pmc)
 898 {
 899         struct hclge_mbx_vf_to_pf_cmd *req;
 900         struct hclgevf_desc desc;
 901         int status;
 902
 903         req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data;
 904
 905         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false);
 906         req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE;
 907         req->msg[1] = en_uc_pmc ? 1 : 0;
 908         req->msg[2] = en_mc_pmc ? 1 : 0;
 909
 910         status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 911         if (status)
 912                 dev_err(&hdev->pdev->dev,
 913                         "Set promisc mode fail, status is %d.\n", status);
 914
 915         return status;
 916 }
 917
 918 static int hclgevf_set_promisc_mode(struct hnae3_handle *handle,
 919                                     bool en_uc_pmc, bool en_mc_pmc)
 920 {
 921         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 922
 923         return hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc);
 924 }
 925
 926 static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id,
 927                               int stream_id, bool enable)
 928 {
 929         struct hclgevf_cfg_com_tqp_queue_cmd *req;
 930         struct hclgevf_desc desc;
 931         int status;
 932
 933         req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;
 934
 935         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE,
 936                                      false);
 937         req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK);
 938         req->stream_id = cpu_to_le16(stream_id);
 939         req->enable |= enable << HCLGEVF_TQP_ENABLE_B;
 940
 941         status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
 942         if (status)
 943                 dev_err(&hdev->pdev->dev,
 944                         "TQP enable fail, status =%d.\n", status);
 945
 946         return status;
 947 }
 948
 949 static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle)
 950 {
 951         struct hnae3_knic_private_info *kinfo = &handle->kinfo;
 952         struct hclgevf_tqp *tqp;
 953         int i;
 954
 955         for (i = 0; i < kinfo->num_tqps; i++) {
 956                 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
 957                 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
 958         }
 959 }
 960
 961 static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p)
 962 {
 963         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 964
 965         ether_addr_copy(p, hdev->hw.mac.mac_addr);
 966 }
 967
 968 static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p,
 969                                 bool is_first)
 970 {
 971         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 972         u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr;
 973         u8 *new_mac_addr = (u8 *)p;
 974         u8 msg_data[ETH_ALEN * 2];
 975         u16 subcode;
 976         int status;
 977
 978         ether_addr_copy(msg_data, new_mac_addr);
 979         ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr);
 980
 981         subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD :
 982                         HCLGE_MBX_MAC_VLAN_UC_MODIFY;
 983
 984         status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
 985                                       subcode, msg_data, ETH_ALEN * 2,
 986                                       true, NULL, 0);
 987         if (!status)
 988                 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr);
 989
 990         return status;
 991 }
 992
 993 static int hclgevf_add_uc_addr(struct hnae3_handle *handle,
 994                                const unsigned char *addr)
 995 {
 996         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
 997
 998         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
 999                                     HCLGE_MBX_MAC_VLAN_UC_ADD,
1000                                     addr, ETH_ALEN, false, NULL, 0);
1001 }
1002
1003 static int hclgevf_rm_uc_addr(struct hnae3_handle *handle,
1004                               const unsigned char *addr)
1005 {
1006         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1007
1008         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
1009                                     HCLGE_MBX_MAC_VLAN_UC_REMOVE,
1010                                     addr, ETH_ALEN, false, NULL, 0);
1011 }
1012
1013 static int hclgevf_add_mc_addr(struct hnae3_handle *handle,
1014                                const unsigned char *addr)
1015 {
1016         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1017
1018         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
1019                                     HCLGE_MBX_MAC_VLAN_MC_ADD,
1020                                     addr, ETH_ALEN, false, NULL, 0);
1021 }
1022
1023 static int hclgevf_rm_mc_addr(struct hnae3_handle *handle,
1024                               const unsigned char *addr)
1025 {
1026         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1027
1028         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
1029                                     HCLGE_MBX_MAC_VLAN_MC_REMOVE,
1030                                     addr, ETH_ALEN, false, NULL, 0);
1031 }
1032
1033 static int hclgevf_set_vlan_filter(struct hnae3_handle *handle,
1034                                    __be16 proto, u16 vlan_id,
1035                                    bool is_kill)
1036 {
1037 #define HCLGEVF_VLAN_MBX_MSG_LEN 5
1038         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1039         u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN];
1040
1041         if (vlan_id > 4095)
1042                 return -EINVAL;
1043
1044         if (proto != htons(ETH_P_8021Q))
1045                 return -EPROTONOSUPPORT;
1046
1047         msg_data[0] = is_kill;
1048         memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
1049         memcpy(&msg_data[3], &proto, sizeof(proto));
1050         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN,
1051                                     HCLGE_MBX_VLAN_FILTER, msg_data,
1052                                     HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0);
1053 }
1054
1055 static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
1056 {
1057         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1058         u8 msg_data;
1059
1060         msg_data = enable ? 1 : 0;
1061         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN,
1062                                     HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data,
1063                                     1, false, NULL, 0);
1064 }
1065
1066 static int hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
1067 {
1068         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1069         u8 msg_data[2];
1070         int ret;
1071
1072         memcpy(&msg_data[0], &queue_id, sizeof(queue_id));
1073
1074         /* disable vf queue before send queue reset msg to PF */
1075         ret = hclgevf_tqp_enable(hdev, queue_id, 0, false);
1076         if (ret)
1077                 return ret;
1078
1079         return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data,
1080                                     2, true, NULL, 0);
1081 }
1082
1083 static int hclgevf_notify_client(struct hclgevf_dev *hdev,
1084                                  enum hnae3_reset_notify_type type)
1085 {
1086         struct hnae3_client *client = hdev->nic_client;
1087         struct hnae3_handle *handle = &hdev->nic;
1088
1089         if (!client->ops->reset_notify)
1090                 return -EOPNOTSUPP;
1091
1092         return client->ops->reset_notify(handle, type);
1093 }
1094
1095 static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
1096 {
1097 #define HCLGEVF_RESET_WAIT_MS   500
1098 #define HCLGEVF_RESET_WAIT_CNT  20
1099         u32 val, cnt = 0;
1100
1101         /* wait to check the hardware reset completion status */
1102         val = hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING);
1103         while (hnae3_get_bit(val, HCLGEVF_FUN_RST_ING_B) &&
1104                (cnt < HCLGEVF_RESET_WAIT_CNT)) {
1105                 msleep(HCLGEVF_RESET_WAIT_MS);
1106                 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING);
1107                 cnt++;
1108         }
1109
1110         /* hardware completion status should be available by this time */
1111         if (cnt >= HCLGEVF_RESET_WAIT_CNT) {
1112                 dev_warn(&hdev->pdev->dev,
1113                          "could'nt get reset done status from h/w, timeout!\n");
1114                 return -EBUSY;
1115         }
1116
1117         /* we will wait a bit more to let reset of the stack to complete. This
1118          * might happen in case reset assertion was made by PF. Yes, this also
1119          * means we might end up waiting bit more even for VF reset.
1120          */
1121         msleep(5000);
1122
1123         return 0;
1124 }
1125
1126 static int hclgevf_reset_stack(struct hclgevf_dev *hdev)
1127 {
1128         int ret;
1129
1130         /* uninitialize the nic client */
1131         hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1132
1133         /* re-initialize the hclge device */
1134         ret = hclgevf_reset_hdev(hdev);
1135         if (ret) {
1136                 dev_err(&hdev->pdev->dev,
1137                         "hclge device re-init failed, VF is disabled!\n");
1138                 return ret;
1139         }
1140
1141         /* bring up the nic client again */
1142         hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT);
1143
1144         return 0;
1145 }
1146
1147 static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)
1148 {
1149         int ret = 0;
1150
1151         switch (hdev->reset_type) {
1152         case HNAE3_VF_FUNC_RESET:
1153                 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL,
1154                                            0, true, NULL, sizeof(u8));
1155                 break;
1156         default:
1157                 break;
1158         }
1159
1160         dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n",
1161                  hdev->reset_type, ret);
1162
1163         return ret;
1164 }
1165
1166 static int hclgevf_reset(struct hclgevf_dev *hdev)
1167 {
1168         struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
1169         int ret;
1170
1171         /* Initialize ae_dev reset status as well, in case enet layer wants to
1172          * know if device is undergoing reset
1173          */
1174         ae_dev->reset_type = hdev->reset_type;
1175         hdev->reset_count++;
1176         rtnl_lock();
1177
1178         /* bring down the nic to stop any ongoing TX/RX */
1179         hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
1180
1181         rtnl_unlock();
1182
1183         hclgevf_reset_prepare_wait(hdev);
1184
1185         /* check if VF could successfully fetch the hardware reset completion
1186          * status from the hardware
1187          */
1188         ret = hclgevf_reset_wait(hdev);
1189         if (ret) {
1190                 /* can't do much in this situation, will disable VF */
1191                 dev_err(&hdev->pdev->dev,
1192                         "VF failed(=%d) to fetch H/W reset completion status\n",
1193                         ret);
1194
1195                 dev_warn(&hdev->pdev->dev, "VF reset failed, disabling VF!\n");
1196                 rtnl_lock();
1197                 hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1198
1199                 rtnl_unlock();
1200                 return ret;
1201         }
1202
1203         rtnl_lock();
1204
1205         /* now, re-initialize the nic client and ae device*/
1206         ret = hclgevf_reset_stack(hdev);
1207         if (ret)
1208                 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");
1209
1210         /* bring up the nic to enable TX/RX again */
1211         hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
1212
1213         rtnl_unlock();
1214
1215         return ret;
1216 }
1217
1218 static enum hnae3_reset_type hclgevf_get_reset_level(struct hclgevf_dev *hdev,
1219                                                      unsigned long *addr)
1220 {
1221         enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
1222
1223         /* return the highest priority reset level amongst all */
1224         if (test_bit(HNAE3_VF_FULL_RESET, addr)) {
1225                 rst_level = HNAE3_VF_FULL_RESET;
1226                 clear_bit(HNAE3_VF_FULL_RESET, addr);
1227                 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1228         } else if (test_bit(HNAE3_VF_FUNC_RESET, addr)) {
1229                 rst_level = HNAE3_VF_FUNC_RESET;
1230                 clear_bit(HNAE3_VF_FUNC_RESET, addr);
1231         }
1232
1233         return rst_level;
1234 }
1235
1236 static void hclgevf_reset_event(struct pci_dev *pdev,
1237                                 struct hnae3_handle *handle)
1238 {
1239         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1240
1241         dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
1242
1243         if (!hdev->default_reset_request)
1244                 hdev->reset_level =
1245                         hclgevf_get_reset_level(hdev,
1246                                                 &hdev->default_reset_request);
1247         else
1248                 hdev->reset_level = HNAE3_VF_FUNC_RESET;
1249
1250         /* reset of this VF requested */
1251         set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
1252         hclgevf_reset_task_schedule(hdev);
1253
1254         hdev->last_reset_time = jiffies;
1255 }
1256
1257 static void hclgevf_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
1258                                           enum hnae3_reset_type rst_type)
1259 {
1260         struct hclgevf_dev *hdev = ae_dev->priv;
1261
1262         set_bit(rst_type, &hdev->default_reset_request);
1263 }
1264
1265 static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)
1266 {
1267         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1268
1269         return hdev->fw_version;
1270 }
1271
1272 static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)
1273 {
1274         struct hclgevf_misc_vector *vector = &hdev->misc_vector;
1275
1276         vector->vector_irq = pci_irq_vector(hdev->pdev,
1277                                             HCLGEVF_MISC_VECTOR_NUM);
1278         vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
1279         /* vector status always valid for Vector 0 */
1280         hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;
1281         hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;
1282
1283         hdev->num_msi_left -= 1;
1284         hdev->num_msi_used += 1;
1285 }
1286
1287 void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev)
1288 {
1289         if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) &&
1290             !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) {
1291                 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state);
1292                 schedule_work(&hdev->rst_service_task);
1293         }
1294 }
1295
1296 void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev)
1297 {
1298         if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) &&
1299             !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) {
1300                 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1301                 schedule_work(&hdev->mbx_service_task);
1302         }
1303 }
1304
1305 static void hclgevf_task_schedule(struct hclgevf_dev *hdev)
1306 {
1307         if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state)  &&
1308             !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state))
1309                 schedule_work(&hdev->service_task);
1310 }
1311
1312 static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev)
1313 {
1314         /* if we have any pending mailbox event then schedule the mbx task */
1315         if (hdev->mbx_event_pending)
1316                 hclgevf_mbx_task_schedule(hdev);
1317
1318         if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state))
1319                 hclgevf_reset_task_schedule(hdev);
1320 }
1321
1322 static void hclgevf_service_timer(struct timer_list *t)
1323 {
1324         struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer);
1325
1326         mod_timer(&hdev->service_timer, jiffies + 5 * HZ);
1327
1328         hclgevf_task_schedule(hdev);
1329 }
1330
1331 static void hclgevf_reset_service_task(struct work_struct *work)
1332 {
1333         struct hclgevf_dev *hdev =
1334                 container_of(work, struct hclgevf_dev, rst_service_task);
1335         int ret;
1336
1337         if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
1338                 return;
1339
1340         clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state);
1341
1342         if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
1343                                &hdev->reset_state)) {
1344                 /* PF has initmated that it is about to reset the hardware.
1345                  * We now have to poll & check if harware has actually completed
1346                  * the reset sequence. On hardware reset completion, VF needs to
1347                  * reset the client and ae device.
1348                  */
1349                 hdev->reset_attempts = 0;
1350
1351                 hdev->last_reset_time = jiffies;
1352                 while ((hdev->reset_type =
1353                         hclgevf_get_reset_level(hdev, &hdev->reset_pending))
1354                        != HNAE3_NONE_RESET) {
1355                         ret = hclgevf_reset(hdev);
1356                         if (ret)
1357                                 dev_err(&hdev->pdev->dev,
1358                                         "VF stack reset failed %d.\n", ret);
1359                 }
1360         } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,
1361                                       &hdev->reset_state)) {
1362                 /* we could be here when either of below happens:
1363                  * 1. reset was initiated due to watchdog timeout due to
1364                  *    a. IMP was earlier reset and our TX got choked down and
1365                  *       which resulted in watchdog reacting and inducing VF
1366                  *       reset. This also means our cmdq would be unreliable.
1367                  *    b. problem in TX due to other lower layer(example link
1368                  *       layer not functioning properly etc.)
1369                  * 2. VF reset might have been initiated due to some config
1370                  *    change.
1371                  *
1372                  * NOTE: Theres no clear way to detect above cases than to react
1373                  * to the response of PF for this reset request. PF will ack the
1374                  * 1b and 2. cases but we will not get any intimation about 1a
1375                  * from PF as cmdq would be in unreliable state i.e. mailbox
1376                  * communication between PF and VF would be broken.
1377                  */
1378
1379                 /* if we are never geting into pending state it means either:
1380                  * 1. PF is not receiving our request which could be due to IMP
1381                  *    reset
1382                  * 2. PF is screwed
1383                  * We cannot do much for 2. but to check first we can try reset
1384                  * our PCIe + stack and see if it alleviates the problem.
1385                  */
1386                 if (hdev->reset_attempts > 3) {
1387                         /* prepare for full reset of stack + pcie interface */
1388                         set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending);
1389
1390                         /* "defer" schedule the reset task again */
1391                         set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1392                 } else {
1393                         hdev->reset_attempts++;
1394
1395                         set_bit(hdev->reset_level, &hdev->reset_pending);
1396                         set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1397                 }
1398                 hclgevf_reset_task_schedule(hdev);
1399         }
1400
1401         clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
1402 }
1403
1404 static void hclgevf_mailbox_service_task(struct work_struct *work)
1405 {
1406         struct hclgevf_dev *hdev;
1407
1408         hdev = container_of(work, struct hclgevf_dev, mbx_service_task);
1409
1410         if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state))
1411                 return;
1412
1413         clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1414
1415         hclgevf_mbx_async_handler(hdev);
1416
1417         clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
1418 }
1419
1420 static void hclgevf_service_task(struct work_struct *work)
1421 {
1422         struct hclgevf_dev *hdev;
1423
1424         hdev = container_of(work, struct hclgevf_dev, service_task);
1425
1426         /* request the link status from the PF. PF would be able to tell VF
1427          * about such updates in future so we might remove this later
1428          */
1429         hclgevf_request_link_info(hdev);
1430
1431         hclgevf_deferred_task_schedule(hdev);
1432
1433         clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
1434 }
1435
1436 static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)
1437 {
1438         hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr);
1439 }
1440
1441 static bool hclgevf_check_event_cause(struct hclgevf_dev *hdev, u32 *clearval)
1442 {
1443         u32 cmdq_src_reg;
1444
1445         /* fetch the events from their corresponding regs */
1446         cmdq_src_reg = hclgevf_read_dev(&hdev->hw,
1447                                         HCLGEVF_VECTOR0_CMDQ_SRC_REG);
1448
1449         /* check for vector0 mailbox(=CMDQ RX) event source */
1450         if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
1451                 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
1452                 *clearval = cmdq_src_reg;
1453                 return true;
1454         }
1455
1456         dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n");
1457
1458         return false;
1459 }
1460
1461 static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
1462 {
1463         writel(en ? 1 : 0, vector->addr);
1464 }
1465
1466 static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
1467 {
1468         struct hclgevf_dev *hdev = data;
1469         u32 clearval;
1470
1471         hclgevf_enable_vector(&hdev->misc_vector, false);
1472         if (!hclgevf_check_event_cause(hdev, &clearval))
1473                 goto skip_sched;
1474
1475         hclgevf_mbx_handler(hdev);
1476
1477         hclgevf_clear_event_cause(hdev, clearval);
1478
1479 skip_sched:
1480         hclgevf_enable_vector(&hdev->misc_vector, true);
1481
1482         return IRQ_HANDLED;
1483 }
1484
1485 static int hclgevf_configure(struct hclgevf_dev *hdev)
1486 {
1487         int ret;
1488
1489         hdev->hw.mac.media_type = HNAE3_MEDIA_TYPE_NONE;
1490
1491         /* get queue configuration from PF */
1492         ret = hclgevf_get_queue_info(hdev);
1493         if (ret)
1494                 return ret;
1495         /* get tc configuration from PF */
1496         return hclgevf_get_tc_info(hdev);
1497 }
1498
1499 static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev)
1500 {
1501         struct pci_dev *pdev = ae_dev->pdev;
1502         struct hclgevf_dev *hdev = ae_dev->priv;
1503
1504         hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
1505         if (!hdev)
1506                 return -ENOMEM;
1507
1508         hdev->pdev = pdev;
1509         hdev->ae_dev = ae_dev;
1510         ae_dev->priv = hdev;
1511
1512         return 0;
1513 }
1514
1515 static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
1516 {
1517         struct hnae3_handle *roce = &hdev->roce;
1518         struct hnae3_handle *nic = &hdev->nic;
1519
1520         roce->rinfo.num_vectors = hdev->num_roce_msix;
1521
1522         if (hdev->num_msi_left < roce->rinfo.num_vectors ||
1523             hdev->num_msi_left == 0)
1524                 return -EINVAL;
1525
1526         roce->rinfo.base_vector = hdev->roce_base_vector;
1527
1528         roce->rinfo.netdev = nic->kinfo.netdev;
1529         roce->rinfo.roce_io_base = hdev->hw.io_base;
1530
1531         roce->pdev = nic->pdev;
1532         roce->ae_algo = nic->ae_algo;
1533         roce->numa_node_mask = nic->numa_node_mask;
1534
1535         return 0;
1536 }
1537
1538 static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
1539 {
1540         struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
1541         int i, ret;
1542
1543         rss_cfg->rss_size = hdev->rss_size_max;
1544
1545         if (hdev->pdev->revision >= 0x21) {
1546                 rss_cfg->hash_algo = HCLGEVF_RSS_HASH_ALGO_TOEPLITZ;
1547                 netdev_rss_key_fill(rss_cfg->rss_hash_key,
1548                                     HCLGEVF_RSS_KEY_SIZE);
1549
1550                 ret = hclgevf_set_rss_algo_key(hdev, rss_cfg->hash_algo,
1551                                                rss_cfg->rss_hash_key);
1552                 if (ret)
1553                         return ret;
1554
1555                 rss_cfg->rss_tuple_sets.ipv4_tcp_en =
1556                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1557                 rss_cfg->rss_tuple_sets.ipv4_udp_en =
1558                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1559                 rss_cfg->rss_tuple_sets.ipv4_sctp_en =
1560                                         HCLGEVF_RSS_INPUT_TUPLE_SCTP;
1561                 rss_cfg->rss_tuple_sets.ipv4_fragment_en =
1562                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1563                 rss_cfg->rss_tuple_sets.ipv6_tcp_en =
1564                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1565                 rss_cfg->rss_tuple_sets.ipv6_udp_en =
1566                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1567                 rss_cfg->rss_tuple_sets.ipv6_sctp_en =
1568                                         HCLGEVF_RSS_INPUT_TUPLE_SCTP;
1569                 rss_cfg->rss_tuple_sets.ipv6_fragment_en =
1570                                         HCLGEVF_RSS_INPUT_TUPLE_OTHER;
1571
1572                 ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg);
1573                 if (ret)
1574                         return ret;
1575
1576         }
1577
1578         /* Initialize RSS indirect table for each vport */
1579         for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
1580                 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max;
1581
1582         ret = hclgevf_set_rss_indir_table(hdev);
1583         if (ret)
1584                 return ret;
1585
1586         return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max);
1587 }
1588
1589 static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)
1590 {
1591         /* other vlan config(like, VLAN TX/RX offload) would also be added
1592          * here later
1593          */
1594         return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
1595                                        false);
1596 }
1597
1598 static int hclgevf_ae_start(struct hnae3_handle *handle)
1599 {
1600         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1601
1602         /* reset tqp stats */
1603         hclgevf_reset_tqp_stats(handle);
1604
1605         hclgevf_request_link_info(hdev);
1606
1607         clear_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1608         mod_timer(&hdev->service_timer, jiffies + HZ);
1609
1610         return 0;
1611 }
1612
1613 static void hclgevf_ae_stop(struct hnae3_handle *handle)
1614 {
1615         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1616
1617         set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1618
1619         /* reset tqp stats */
1620         hclgevf_reset_tqp_stats(handle);
1621         del_timer_sync(&hdev->service_timer);
1622         cancel_work_sync(&hdev->service_task);
1623         clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
1624         hclgevf_update_link_status(hdev, 0);
1625 }
1626
1627 static void hclgevf_state_init(struct hclgevf_dev *hdev)
1628 {
1629         /* setup tasks for the MBX */
1630         INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task);
1631         clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1632         clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
1633
1634         /* setup tasks for service timer */
1635         timer_setup(&hdev->service_timer, hclgevf_service_timer, 0);
1636
1637         INIT_WORK(&hdev->service_task, hclgevf_service_task);
1638         clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
1639
1640         INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task);
1641
1642         mutex_init(&hdev->mbx_resp.mbx_mutex);
1643
1644         /* bring the device down */
1645         set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1646 }
1647
1648 static void hclgevf_state_uninit(struct hclgevf_dev *hdev)
1649 {
1650         set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1651
1652         if (hdev->service_timer.function)
1653                 del_timer_sync(&hdev->service_timer);
1654         if (hdev->service_task.func)
1655                 cancel_work_sync(&hdev->service_task);
1656         if (hdev->mbx_service_task.func)
1657                 cancel_work_sync(&hdev->mbx_service_task);
1658         if (hdev->rst_service_task.func)
1659                 cancel_work_sync(&hdev->rst_service_task);
1660
1661         mutex_destroy(&hdev->mbx_resp.mbx_mutex);
1662 }
1663
1664 static int hclgevf_init_msi(struct hclgevf_dev *hdev)
1665 {
1666         struct pci_dev *pdev = hdev->pdev;
1667         int vectors;
1668         int i;
1669
1670         if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B))
1671                 vectors = pci_alloc_irq_vectors(pdev,
1672                                                 hdev->roce_base_msix_offset + 1,
1673                                                 hdev->num_msi,
1674                                                 PCI_IRQ_MSIX);
1675         else
1676                 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1677                                                 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1678
1679         if (vectors < 0) {
1680                 dev_err(&pdev->dev,
1681                         "failed(%d) to allocate MSI/MSI-X vectors\n",
1682                         vectors);
1683                 return vectors;
1684         }
1685         if (vectors < hdev->num_msi)
1686                 dev_warn(&hdev->pdev->dev,
1687                          "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1688                          hdev->num_msi, vectors);
1689
1690         hdev->num_msi = vectors;
1691         hdev->num_msi_left = vectors;
1692         hdev->base_msi_vector = pdev->irq;
1693         hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset;
1694
1695         hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1696                                            sizeof(u16), GFP_KERNEL);
1697         if (!hdev->vector_status) {
1698                 pci_free_irq_vectors(pdev);
1699                 return -ENOMEM;
1700         }
1701
1702         for (i = 0; i < hdev->num_msi; i++)
1703                 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT;
1704
1705         hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1706                                         sizeof(int), GFP_KERNEL);
1707         if (!hdev->vector_irq) {
1708                 pci_free_irq_vectors(pdev);
1709                 return -ENOMEM;
1710         }
1711
1712         return 0;
1713 }
1714
1715 static void hclgevf_uninit_msi(struct hclgevf_dev *hdev)
1716 {
1717         struct pci_dev *pdev = hdev->pdev;
1718
1719         pci_free_irq_vectors(pdev);
1720 }
1721
1722 static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev)
1723 {
1724         int ret = 0;
1725
1726         hclgevf_get_misc_vector(hdev);
1727
1728         ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle,
1729                           0, "hclgevf_cmd", hdev);
1730         if (ret) {
1731                 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n",
1732                         hdev->misc_vector.vector_irq);
1733                 return ret;
1734         }
1735
1736         hclgevf_clear_event_cause(hdev, 0);
1737
1738         /* enable misc. vector(vector 0) */
1739         hclgevf_enable_vector(&hdev->misc_vector, true);
1740
1741         return ret;
1742 }
1743
1744 static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev)
1745 {
1746         /* disable misc vector(vector 0) */
1747         hclgevf_enable_vector(&hdev->misc_vector, false);
1748         synchronize_irq(hdev->misc_vector.vector_irq);
1749         free_irq(hdev->misc_vector.vector_irq, hdev);
1750         hclgevf_free_vector(hdev, 0);
1751 }
1752
1753 static int hclgevf_init_client_instance(struct hnae3_client *client,
1754                                         struct hnae3_ae_dev *ae_dev)
1755 {
1756         struct hclgevf_dev *hdev = ae_dev->priv;
1757         int ret;
1758
1759         switch (client->type) {
1760         case HNAE3_CLIENT_KNIC:
1761                 hdev->nic_client = client;
1762                 hdev->nic.client = client;
1763
1764                 ret = client->ops->init_instance(&hdev->nic);
1765                 if (ret)
1766                         goto clear_nic;
1767
1768                 hnae3_set_client_init_flag(client, ae_dev, 1);
1769
1770                 if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) {
1771                         struct hnae3_client *rc = hdev->roce_client;
1772
1773                         ret = hclgevf_init_roce_base_info(hdev);
1774                         if (ret)
1775                                 goto clear_roce;
1776                         ret = rc->ops->init_instance(&hdev->roce);
1777                         if (ret)
1778                                 goto clear_roce;
1779
1780                         hnae3_set_client_init_flag(hdev->roce_client, ae_dev,
1781                                                    1);
1782                 }
1783                 break;
1784         case HNAE3_CLIENT_UNIC:
1785                 hdev->nic_client = client;
1786                 hdev->nic.client = client;
1787
1788                 ret = client->ops->init_instance(&hdev->nic);
1789                 if (ret)
1790                         goto clear_nic;
1791
1792                 hnae3_set_client_init_flag(client, ae_dev, 1);
1793                 break;
1794         case HNAE3_CLIENT_ROCE:
1795                 if (hnae3_dev_roce_supported(hdev)) {
1796                         hdev->roce_client = client;
1797                         hdev->roce.client = client;
1798                 }
1799
1800                 if (hdev->roce_client && hdev->nic_client) {
1801                         ret = hclgevf_init_roce_base_info(hdev);
1802                         if (ret)
1803                                 goto clear_roce;
1804
1805                         ret = client->ops->init_instance(&hdev->roce);
1806                         if (ret)
1807                                 goto clear_roce;
1808                 }
1809
1810                 hnae3_set_client_init_flag(client, ae_dev, 1);
1811                 break;
1812         default:
1813                 return -EINVAL;
1814         }
1815
1816         return 0;
1817
1818 clear_nic:
1819         hdev->nic_client = NULL;
1820         hdev->nic.client = NULL;
1821         return ret;
1822 clear_roce:
1823         hdev->roce_client = NULL;
1824         hdev->roce.client = NULL;
1825         return ret;
1826 }
1827
1828 static void hclgevf_uninit_client_instance(struct hnae3_client *client,
1829                                            struct hnae3_ae_dev *ae_dev)
1830 {
1831         struct hclgevf_dev *hdev = ae_dev->priv;
1832
1833         /* un-init roce, if it exists */
1834         if (hdev->roce_client) {
1835                 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);
1836                 hdev->roce_client = NULL;
1837                 hdev->roce.client = NULL;
1838         }
1839
1840         /* un-init nic/unic, if this was not called by roce client */
1841         if (client->ops->uninit_instance && hdev->nic_client &&
1842             client->type != HNAE3_CLIENT_ROCE) {
1843                 client->ops->uninit_instance(&hdev->nic, 0);
1844                 hdev->nic_client = NULL;
1845                 hdev->nic.client = NULL;
1846         }
1847 }
1848
1849 static int hclgevf_pci_init(struct hclgevf_dev *hdev)
1850 {
1851         struct pci_dev *pdev = hdev->pdev;
1852         struct hclgevf_hw *hw;
1853         int ret;
1854
1855         ret = pci_enable_device(pdev);
1856         if (ret) {
1857                 dev_err(&pdev->dev, "failed to enable PCI device\n");
1858                 return ret;
1859         }
1860
1861         ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1862         if (ret) {
1863                 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");
1864                 goto err_disable_device;
1865         }
1866
1867         ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME);
1868         if (ret) {
1869                 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
1870                 goto err_disable_device;
1871         }
1872
1873         pci_set_master(pdev);
1874         hw = &hdev->hw;
1875         hw->hdev = hdev;
1876         hw->io_base = pci_iomap(pdev, 2, 0);
1877         if (!hw->io_base) {
1878                 dev_err(&pdev->dev, "can't map configuration register space\n");
1879                 ret = -ENOMEM;
1880                 goto err_clr_master;
1881         }
1882
1883         return 0;
1884
1885 err_clr_master:
1886         pci_clear_master(pdev);
1887         pci_release_regions(pdev);
1888 err_disable_device:
1889         pci_disable_device(pdev);
1890
1891         return ret;
1892 }
1893
1894 static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
1895 {
1896         struct pci_dev *pdev = hdev->pdev;
1897
1898         pci_iounmap(pdev, hdev->hw.io_base);
1899         pci_clear_master(pdev);
1900         pci_release_regions(pdev);
1901         pci_disable_device(pdev);
1902 }
1903
1904 static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)
1905 {
1906         struct hclgevf_query_res_cmd *req;
1907         struct hclgevf_desc desc;
1908         int ret;
1909
1910         hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true);
1911         ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
1912         if (ret) {
1913                 dev_err(&hdev->pdev->dev,
1914                         "query vf resource failed, ret = %d.\n", ret);
1915                 return ret;
1916         }
1917
1918         req = (struct hclgevf_query_res_cmd *)desc.data;
1919
1920         if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) {
1921                 hdev->roce_base_msix_offset =
1922                 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
1923                                 HCLGEVF_MSIX_OFT_ROCEE_M,
1924                                 HCLGEVF_MSIX_OFT_ROCEE_S);
1925                 hdev->num_roce_msix =
1926                 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),
1927                                 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
1928
1929                 /* VF should have NIC vectors and Roce vectors, NIC vectors
1930                  * are queued before Roce vectors. The offset is fixed to 64.
1931                  */
1932                 hdev->num_msi = hdev->num_roce_msix +
1933                                 hdev->roce_base_msix_offset;
1934         } else {
1935                 hdev->num_msi =
1936                 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),
1937                                 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
1938         }
1939
1940         return 0;
1941 }
1942
1943 static int hclgevf_reset_hdev(struct hclgevf_dev *hdev)
1944 {
1945         struct pci_dev *pdev = hdev->pdev;
1946         int ret;
1947
1948         ret = hclgevf_cmd_init(hdev);
1949         if (ret) {
1950                 dev_err(&pdev->dev, "cmd failed %d\n", ret);
1951                 return ret;
1952         }
1953
1954         ret = hclgevf_rss_init_hw(hdev);
1955         if (ret) {
1956                 dev_err(&hdev->pdev->dev,
1957                         "failed(%d) to initialize RSS\n", ret);
1958                 return ret;
1959         }
1960
1961         ret = hclgevf_init_vlan_config(hdev);
1962         if (ret) {
1963                 dev_err(&hdev->pdev->dev,
1964                         "failed(%d) to initialize VLAN config\n", ret);
1965                 return ret;
1966         }
1967
1968         dev_info(&hdev->pdev->dev, "Reset done\n");
1969
1970         return 0;
1971 }
1972
1973 static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
1974 {
1975         struct pci_dev *pdev = hdev->pdev;
1976         int ret;
1977
1978         ret = hclgevf_pci_init(hdev);
1979         if (ret) {
1980                 dev_err(&pdev->dev, "PCI initialization failed\n");
1981                 return ret;
1982         }
1983
1984         ret = hclgevf_cmd_queue_init(hdev);
1985         if (ret) {
1986                 dev_err(&pdev->dev, "Cmd queue init failed: %d\n", ret);
1987                 goto err_cmd_queue_init;
1988         }
1989
1990         ret = hclgevf_cmd_init(hdev);
1991         if (ret)
1992                 goto err_cmd_init;
1993
1994         /* Get vf resource */
1995         ret = hclgevf_query_vf_resource(hdev);
1996         if (ret) {
1997                 dev_err(&hdev->pdev->dev,
1998                         "Query vf status error, ret = %d.\n", ret);
1999                 goto err_cmd_init;
2000         }
2001
2002         ret = hclgevf_init_msi(hdev);
2003         if (ret) {
2004                 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
2005                 goto err_cmd_init;
2006         }
2007
2008         hclgevf_state_init(hdev);
2009         hdev->reset_level = HNAE3_VF_FUNC_RESET;
2010
2011         ret = hclgevf_misc_irq_init(hdev);
2012         if (ret) {
2013                 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
2014                         ret);
2015                 goto err_misc_irq_init;
2016         }
2017
2018         ret = hclgevf_configure(hdev);
2019         if (ret) {
2020                 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret);
2021                 goto err_config;
2022         }
2023
2024         ret = hclgevf_alloc_tqps(hdev);
2025         if (ret) {
2026                 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);
2027                 goto err_config;
2028         }
2029
2030         ret = hclgevf_set_handle_info(hdev);
2031         if (ret) {
2032                 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret);
2033                 goto err_config;
2034         }
2035
2036         /* Initialize RSS for this VF */
2037         ret = hclgevf_rss_init_hw(hdev);
2038         if (ret) {
2039                 dev_err(&hdev->pdev->dev,
2040                         "failed(%d) to initialize RSS\n", ret);
2041                 goto err_config;
2042         }
2043
2044         ret = hclgevf_init_vlan_config(hdev);
2045         if (ret) {
2046                 dev_err(&hdev->pdev->dev,
2047                         "failed(%d) to initialize VLAN config\n", ret);
2048                 goto err_config;
2049         }
2050
2051         hdev->last_reset_time = jiffies;
2052         pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME);
2053
2054         return 0;
2055
2056 err_config:
2057         hclgevf_misc_irq_uninit(hdev);
2058 err_misc_irq_init:
2059         hclgevf_state_uninit(hdev);
2060         hclgevf_uninit_msi(hdev);
2061 err_cmd_init:
2062         hclgevf_cmd_uninit(hdev);
2063 err_cmd_queue_init:
2064         hclgevf_pci_uninit(hdev);
2065         return ret;
2066 }
2067
2068 static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
2069 {
2070         hclgevf_state_uninit(hdev);
2071         hclgevf_misc_irq_uninit(hdev);
2072         hclgevf_cmd_uninit(hdev);
2073         hclgevf_uninit_msi(hdev);
2074         hclgevf_pci_uninit(hdev);
2075 }
2076
2077 static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev)
2078 {
2079         struct pci_dev *pdev = ae_dev->pdev;
2080         int ret;
2081
2082         ret = hclgevf_alloc_hdev(ae_dev);
2083         if (ret) {
2084                 dev_err(&pdev->dev, "hclge device allocation failed\n");
2085                 return ret;
2086         }
2087
2088         ret = hclgevf_init_hdev(ae_dev->priv);
2089         if (ret)
2090                 dev_err(&pdev->dev, "hclge device initialization failed\n");
2091
2092         return ret;
2093 }
2094
2095 static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
2096 {
2097         struct hclgevf_dev *hdev = ae_dev->priv;
2098
2099         hclgevf_uninit_hdev(hdev);
2100         ae_dev->priv = NULL;
2101 }
2102
2103 static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)
2104 {
2105         struct hnae3_handle *nic = &hdev->nic;
2106         struct hnae3_knic_private_info *kinfo = &nic->kinfo;
2107
2108         return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
2109 }
2110
2111 /**
2112  * hclgevf_get_channels - Get the current channels enabled and max supported.
2113  * @handle: hardware information for network interface
2114  * @ch: ethtool channels structure
2115  *
2116  * We don't support separate tx and rx queues as channels. The other count
2117  * represents how many queues are being used for control. max_combined counts
2118  * how many queue pairs we can support. They may not be mapped 1 to 1 with
2119  * q_vectors since we support a lot more queue pairs than q_vectors.
2120  **/
2121 static void hclgevf_get_channels(struct hnae3_handle *handle,
2122                                  struct ethtool_channels *ch)
2123 {
2124         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2125
2126         ch->max_combined = hclgevf_get_max_channels(hdev);
2127         ch->other_count = 0;
2128         ch->max_other = 0;
2129         ch->combined_count = hdev->num_tqps;
2130 }
2131
2132 static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,
2133                                           u16 *alloc_tqps, u16 *max_rss_size)
2134 {
2135         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2136
2137         *alloc_tqps = hdev->num_tqps;
2138         *max_rss_size = hdev->rss_size_max;
2139 }
2140
2141 static int hclgevf_get_status(struct hnae3_handle *handle)
2142 {
2143         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2144
2145         return hdev->hw.mac.link;
2146 }
2147
2148 static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
2149                                             u8 *auto_neg, u32 *speed,
2150                                             u8 *duplex)
2151 {
2152         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2153
2154         if (speed)
2155                 *speed = hdev->hw.mac.speed;
2156         if (duplex)
2157                 *duplex = hdev->hw.mac.duplex;
2158         if (auto_neg)
2159                 *auto_neg = AUTONEG_DISABLE;
2160 }
2161
2162 void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
2163                                  u8 duplex)
2164 {
2165         hdev->hw.mac.speed = speed;
2166         hdev->hw.mac.duplex = duplex;
2167 }
2168
2169 static void hclgevf_get_media_type(struct hnae3_handle *handle,
2170                                   u8 *media_type)
2171 {
2172         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2173         if (media_type)
2174                 *media_type = hdev->hw.mac.media_type;
2175 }
2176
2177 static bool hclgevf_get_hw_reset_stat(struct hnae3_handle *handle)
2178 {
2179         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2180
2181         return !!hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING);
2182 }
2183
2184 static bool hclgevf_ae_dev_resetting(struct hnae3_handle *handle)
2185 {
2186         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2187
2188         return test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
2189 }
2190
2191 static unsigned long hclgevf_ae_dev_reset_cnt(struct hnae3_handle *handle)
2192 {
2193         struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2194
2195         return hdev->reset_count;
2196 }
2197
2198 static const struct hnae3_ae_ops hclgevf_ops = {
2199         .init_ae_dev = hclgevf_init_ae_dev,
2200         .uninit_ae_dev = hclgevf_uninit_ae_dev,
2201         .init_client_instance = hclgevf_init_client_instance,
2202         .uninit_client_instance = hclgevf_uninit_client_instance,
2203         .start = hclgevf_ae_start,
2204         .stop = hclgevf_ae_stop,
2205         .map_ring_to_vector = hclgevf_map_ring_to_vector,
2206         .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector,
2207         .get_vector = hclgevf_get_vector,
2208         .put_vector = hclgevf_put_vector,
2209         .reset_queue = hclgevf_reset_tqp,
2210         .set_promisc_mode = hclgevf_set_promisc_mode,
2211         .get_mac_addr = hclgevf_get_mac_addr,
2212         .set_mac_addr = hclgevf_set_mac_addr,
2213         .add_uc_addr = hclgevf_add_uc_addr,
2214         .rm_uc_addr = hclgevf_rm_uc_addr,
2215         .add_mc_addr = hclgevf_add_mc_addr,
2216         .rm_mc_addr = hclgevf_rm_mc_addr,
2217         .get_stats = hclgevf_get_stats,
2218         .update_stats = hclgevf_update_stats,
2219         .get_strings = hclgevf_get_strings,
2220         .get_sset_count = hclgevf_get_sset_count,
2221         .get_rss_key_size = hclgevf_get_rss_key_size,
2222         .get_rss_indir_size = hclgevf_get_rss_indir_size,
2223         .get_rss = hclgevf_get_rss,
2224         .set_rss = hclgevf_set_rss,
2225         .get_rss_tuple = hclgevf_get_rss_tuple,
2226         .set_rss_tuple = hclgevf_set_rss_tuple,
2227         .get_tc_size = hclgevf_get_tc_size,
2228         .get_fw_version = hclgevf_get_fw_version,
2229         .set_vlan_filter = hclgevf_set_vlan_filter,
2230         .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag,
2231         .reset_event = hclgevf_reset_event,
2232         .set_default_reset_request = hclgevf_set_def_reset_request,
2233         .get_channels = hclgevf_get_channels,
2234         .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
2235         .get_status = hclgevf_get_status,
2236         .get_ksettings_an_result = hclgevf_get_ksettings_an_result,
2237         .get_media_type = hclgevf_get_media_type,
2238         .get_hw_reset_stat = hclgevf_get_hw_reset_stat,
2239         .ae_dev_resetting = hclgevf_ae_dev_resetting,
2240         .ae_dev_reset_cnt = hclgevf_ae_dev_reset_cnt,
2241 };
2242
2243 static struct hnae3_ae_algo ae_algovf = {
2244         .ops = &hclgevf_ops,
2245         .pdev_id_table = ae_algovf_pci_tbl,
2246 };
2247
2248 static int hclgevf_init(void)
2249 {
2250         pr_info("%s is initializing\n", HCLGEVF_NAME);
2251
2252         hnae3_register_ae_algo(&ae_algovf);
2253
2254         return 0;
2255 }
2256
2257 static void hclgevf_exit(void)
2258 {
2259         hnae3_unregister_ae_algo(&ae_algovf);
2260 }
2261 module_init(hclgevf_init);
2262 module_exit(hclgevf_exit);
2263
2264 MODULE_LICENSE("GPL");
2265 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
2266 MODULE_DESCRIPTION("HCLGEVF Driver");
2267 MODULE_VERSION(HCLGEVF_MOD_VERSION);