1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*******************************************************************************
4 * Intel Ethernet Controller XL710 Family Linux Driver
5 * Copyright(c) 2013 - 2014 Intel Corporation.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along
17 * with this program. If not, see <http://www.gnu.org/licenses/>.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 ******************************************************************************/
31 #include "i40e_type.h"
33 #define I40E_DCBX_STATUS_NOT_STARTED 0
34 #define I40E_DCBX_STATUS_IN_PROGRESS 1
35 #define I40E_DCBX_STATUS_DONE 2
36 #define I40E_DCBX_STATUS_MULTIPLE_PEERS 3
37 #define I40E_DCBX_STATUS_DISABLED 7
39 #define I40E_TLV_TYPE_END 0
40 #define I40E_TLV_TYPE_ORG 127
42 #define I40E_IEEE_8021QAZ_OUI 0x0080C2
43 #define I40E_IEEE_SUBTYPE_ETS_CFG 9
44 #define I40E_IEEE_SUBTYPE_ETS_REC 10
45 #define I40E_IEEE_SUBTYPE_PFC_CFG 11
46 #define I40E_IEEE_SUBTYPE_APP_PRI 12
48 #define I40E_CEE_DCBX_OUI 0x001b21
49 #define I40E_CEE_DCBX_TYPE 2
51 #define I40E_CEE_SUBTYPE_CTRL 1
52 #define I40E_CEE_SUBTYPE_PG_CFG 2
53 #define I40E_CEE_SUBTYPE_PFC_CFG 3
54 #define I40E_CEE_SUBTYPE_APP_PRI 4
56 #define I40E_CEE_MAX_FEAT_TYPE 3
57 /* Defines for LLDP TLV header */
58 #define I40E_LLDP_TLV_LEN_SHIFT 0
59 #define I40E_LLDP_TLV_LEN_MASK (0x01FF << I40E_LLDP_TLV_LEN_SHIFT)
60 #define I40E_LLDP_TLV_TYPE_SHIFT 9
61 #define I40E_LLDP_TLV_TYPE_MASK (0x7F << I40E_LLDP_TLV_TYPE_SHIFT)
62 #define I40E_LLDP_TLV_SUBTYPE_SHIFT 0
63 #define I40E_LLDP_TLV_SUBTYPE_MASK (0xFF << I40E_LLDP_TLV_SUBTYPE_SHIFT)
64 #define I40E_LLDP_TLV_OUI_SHIFT 8
65 #define I40E_LLDP_TLV_OUI_MASK (0xFFFFFF << I40E_LLDP_TLV_OUI_SHIFT)
67 /* Defines for IEEE ETS TLV */
68 #define I40E_IEEE_ETS_MAXTC_SHIFT 0
69 #define I40E_IEEE_ETS_MAXTC_MASK (0x7 << I40E_IEEE_ETS_MAXTC_SHIFT)
70 #define I40E_IEEE_ETS_CBS_SHIFT 6
71 #define I40E_IEEE_ETS_CBS_MASK BIT(I40E_IEEE_ETS_CBS_SHIFT)
72 #define I40E_IEEE_ETS_WILLING_SHIFT 7
73 #define I40E_IEEE_ETS_WILLING_MASK BIT(I40E_IEEE_ETS_WILLING_SHIFT)
74 #define I40E_IEEE_ETS_PRIO_0_SHIFT 0
75 #define I40E_IEEE_ETS_PRIO_0_MASK (0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT)
76 #define I40E_IEEE_ETS_PRIO_1_SHIFT 4
77 #define I40E_IEEE_ETS_PRIO_1_MASK (0x7 << I40E_IEEE_ETS_PRIO_1_SHIFT)
78 #define I40E_CEE_PGID_PRIO_0_SHIFT 0
79 #define I40E_CEE_PGID_PRIO_0_MASK (0xF << I40E_CEE_PGID_PRIO_0_SHIFT)
80 #define I40E_CEE_PGID_PRIO_1_SHIFT 4
81 #define I40E_CEE_PGID_PRIO_1_MASK (0xF << I40E_CEE_PGID_PRIO_1_SHIFT)
82 #define I40E_CEE_PGID_STRICT 15
84 /* Defines for IEEE TSA types */
85 #define I40E_IEEE_TSA_STRICT 0
86 #define I40E_IEEE_TSA_ETS 2
88 /* Defines for IEEE PFC TLV */
89 #define I40E_IEEE_PFC_CAP_SHIFT 0
90 #define I40E_IEEE_PFC_CAP_MASK (0xF << I40E_IEEE_PFC_CAP_SHIFT)
91 #define I40E_IEEE_PFC_MBC_SHIFT 6
92 #define I40E_IEEE_PFC_MBC_MASK BIT(I40E_IEEE_PFC_MBC_SHIFT)
93 #define I40E_IEEE_PFC_WILLING_SHIFT 7
94 #define I40E_IEEE_PFC_WILLING_MASK BIT(I40E_IEEE_PFC_WILLING_SHIFT)
96 /* Defines for IEEE APP TLV */
97 #define I40E_IEEE_APP_SEL_SHIFT 0
98 #define I40E_IEEE_APP_SEL_MASK (0x7 << I40E_IEEE_APP_SEL_SHIFT)
99 #define I40E_IEEE_APP_PRIO_SHIFT 5
100 #define I40E_IEEE_APP_PRIO_MASK (0x7 << I40E_IEEE_APP_PRIO_SHIFT)
105 /* IEEE 802.1AB LLDP Organization specific TLV */
106 struct i40e_lldp_org_tlv {
112 struct i40e_cee_tlv_hdr {
118 struct i40e_cee_ctrl_tlv {
119 struct i40e_cee_tlv_hdr hdr;
124 struct i40e_cee_feat_tlv {
125 struct i40e_cee_tlv_hdr hdr;
126 u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */
127 #define I40E_CEE_FEAT_TLV_ENABLE_MASK 0x80
128 #define I40E_CEE_FEAT_TLV_WILLING_MASK 0x40
129 #define I40E_CEE_FEAT_TLV_ERR_MASK 0x20
134 struct i40e_cee_app_prio {
136 u8 upper_oui_sel; /* Bits: |Upper OUI(6)|Selector(2)| */
137 #define I40E_CEE_APP_SELECTOR_MASK 0x03
143 i40e_status i40e_get_dcbx_status(struct i40e_hw *hw,
145 i40e_status i40e_lldp_to_dcb_config(u8 *lldpmib,
146 struct i40e_dcbx_config *dcbcfg);
147 i40e_status i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,
149 struct i40e_dcbx_config *dcbcfg);
150 i40e_status i40e_get_dcb_config(struct i40e_hw *hw);
151 i40e_status i40e_init_dcb(struct i40e_hw *hw);
152 #endif /* _I40E_DCB_H_ */