1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
4 #ifndef _ICE_ADMINQ_CMD_H_
5 #define _ICE_ADMINQ_CMD_H_
7 /* This header file defines the Admin Queue commands, error codes and
8 * descriptor format. It is shared between Firmware and Software.
11 #define ICE_MAX_VSI 768
12 #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
13 #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
15 struct ice_aqc_generic {
22 /* Get version (direct 0x0001) */
23 struct ice_aqc_get_ver {
36 /* Send driver version (indirect 0x0002) */
37 struct ice_aqc_driver_ver {
47 /* Queue Shutdown (direct 0x0003) */
48 struct ice_aqc_q_shutdown {
50 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
54 /* Request resource ownership (direct 0x0008)
55 * Release resource ownership (direct 0x0009)
57 struct ice_aqc_req_res {
59 #define ICE_AQC_RES_ID_NVM 1
60 #define ICE_AQC_RES_ID_SDP 2
61 #define ICE_AQC_RES_ID_CHNG_LOCK 3
62 #define ICE_AQC_RES_ID_GLBL_LOCK 4
64 #define ICE_AQC_RES_ACCESS_READ 1
65 #define ICE_AQC_RES_ACCESS_WRITE 2
67 /* Upon successful completion, FW writes this value and driver is
68 * expected to release resource before timeout. This value is provided
72 #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
73 #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
74 #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
75 #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
76 /* For SDP: pin ID of the SDP */
78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
80 #define ICE_AQ_RES_GLBL_SUCCESS 0
81 #define ICE_AQ_RES_GLBL_IN_PROG 1
82 #define ICE_AQ_RES_GLBL_DONE 2
86 /* Get function capabilities (indirect 0x000A)
87 * Get device capabilities (indirect 0x000B)
89 struct ice_aqc_list_caps {
98 /* Device/Function buffer entry, repeated per reported capability */
99 struct ice_aqc_list_caps_elem {
101 #define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
102 #define ICE_AQC_CAPS_SRIOV 0x0012
103 #define ICE_AQC_CAPS_VF 0x0013
104 #define ICE_AQC_CAPS_VSI 0x0017
105 #define ICE_AQC_CAPS_DCB 0x0018
106 #define ICE_AQC_CAPS_RSS 0x0040
107 #define ICE_AQC_CAPS_RXQS 0x0041
108 #define ICE_AQC_CAPS_TXQS 0x0042
109 #define ICE_AQC_CAPS_MSIX 0x0043
110 #define ICE_AQC_CAPS_MAX_MTU 0x0047
114 /* Number of resources described by this capability */
116 /* Only meaningful for some types of resources */
118 /* Only meaningful for some types of resources */
124 /* Manage MAC address, read command - indirect (0x0107)
125 * This struct is also used for the response
127 struct ice_aqc_manage_mac_read {
128 __le16 flags; /* Zeroed by device driver */
129 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
130 #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
131 #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
132 #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
133 #define ICE_AQC_MAN_MAC_READ_S 4
134 #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
136 u8 num_addr; /* Used in response */
142 /* Response buffer format for manage MAC read command */
143 struct ice_aqc_manage_mac_read_resp {
146 #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
147 #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
148 u8 mac_addr[ETH_ALEN];
151 /* Manage MAC address, write command - direct (0x0108) */
152 struct ice_aqc_manage_mac_write {
155 #define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
156 #define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
157 #define ICE_AQC_MAN_MAC_WR_S 6
158 #define ICE_AQC_MAN_MAC_WR_M (3 << ICE_AQC_MAN_MAC_WR_S)
159 #define ICE_AQC_MAN_MAC_UPDATE_LAA 0
160 #define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL (BIT(0) << ICE_AQC_MAN_MAC_WR_S)
161 /* High 16 bits of MAC address in big endian order */
163 /* Low 32 bits of MAC address in big endian order */
169 /* Clear PXE Command and response (direct 0x0110) */
170 struct ice_aqc_clear_pxe {
172 #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
176 /* Get switch configuration (0x0200) */
177 struct ice_aqc_get_sw_cfg {
178 /* Reserved for command and copy of request flags for response */
180 /* First desc in case of command and next_elem in case of response
181 * In case of response, if it is not zero, means all the configuration
182 * was not returned and new command shall be sent with this value in
183 * the 'first desc' field
186 /* Reserved for command, only used for response */
193 /* Each entry in the response buffer is of the following type: */
194 struct ice_aqc_get_sw_cfg_resp_elem {
195 /* VSI/Port Number */
197 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
198 #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
199 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
200 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
201 #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
202 #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
203 #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
204 #define ICE_AQC_GET_SW_CONF_RESP_VSI 2
206 /* SWID VSI/Port belongs to */
209 /* Bit 14..0 : PF/VF number VSI belongs to
210 * Bit 15 : VF indication bit
213 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
214 #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
215 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
216 #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
219 /* The response buffer is as follows. Note that the length of the
220 * elements array varies with the length of the command response.
222 struct ice_aqc_get_sw_cfg_resp {
223 struct ice_aqc_get_sw_cfg_resp_elem elements[1];
226 /* These resource type defines are used for all switch resource
227 * commands where a resource type is required, such as:
228 * Get Resource Allocation command (indirect 0x0204)
229 * Allocate Resources command (indirect 0x0208)
230 * Free Resources command (indirect 0x0209)
231 * Get Allocated Resource Descriptors Command (indirect 0x020A)
233 #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
234 #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
235 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
236 #define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
238 #define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
239 #define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
241 #define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
243 /* Allocate Resources command (indirect 0x0208)
244 * Free Resources command (indirect 0x0209)
246 struct ice_aqc_alloc_free_res_cmd {
247 __le16 num_entries; /* Number of Resource entries */
253 /* Resource descriptor */
254 struct ice_aqc_res_elem {
261 /* Buffer for Allocate/Free Resources commands */
262 struct ice_aqc_alloc_free_res_elem {
263 __le16 res_type; /* Types defined above cmd 0x0204 */
264 #define ICE_AQC_RES_TYPE_SHARED_S 7
265 #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S)
266 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
267 #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
268 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
270 struct ice_aqc_res_elem elem[1];
273 /* Add VSI (indirect 0x0210)
274 * Update VSI (indirect 0x0211)
275 * Get VSI (indirect 0x0212)
276 * Free VSI (indirect 0x0213)
278 struct ice_aqc_add_get_update_free_vsi {
280 #define ICE_AQ_VSI_NUM_S 0
281 #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
282 #define ICE_AQ_VSI_IS_VALID BIT(15)
284 #define ICE_AQ_VSI_KEEP_ALLOC 0x1
288 #define ICE_AQ_VSI_TYPE_S 0
289 #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
290 #define ICE_AQ_VSI_TYPE_VF 0x0
291 #define ICE_AQ_VSI_TYPE_VMDQ2 0x1
292 #define ICE_AQ_VSI_TYPE_PF 0x2
293 #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
298 /* Response descriptor for:
299 * Add VSI (indirect 0x0210)
300 * Update VSI (indirect 0x0211)
301 * Free VSI (indirect 0x0213)
303 struct ice_aqc_add_update_free_vsi_resp {
312 struct ice_aqc_vsi_props {
313 __le16 valid_sections;
314 #define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
315 #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
316 #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
317 #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
318 #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
319 #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
320 #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
321 #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
322 #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
323 #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
324 #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
328 #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
329 #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
330 #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
332 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
333 #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
334 (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
335 #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
336 #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
338 #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
339 #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
340 #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
341 /* security section */
343 #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
344 #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
345 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
346 #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
347 #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
350 __le16 pvid; /* VLANS include priority bits */
351 u8 pvlan_reserved[2];
353 #define ICE_AQ_VSI_VLAN_MODE_S 0
354 #define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
355 #define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
356 #define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
357 #define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
358 #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
359 #define ICE_AQ_VSI_VLAN_EMOD_S 3
360 #define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
361 #define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
362 #define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
363 #define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
364 #define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
365 u8 pvlan_reserved2[3];
366 /* ingress egress up sections */
367 __le32 ingress_table; /* bitmap, 3 bits per up */
368 #define ICE_AQ_VSI_UP_TABLE_UP0_S 0
369 #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
370 #define ICE_AQ_VSI_UP_TABLE_UP1_S 3
371 #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
372 #define ICE_AQ_VSI_UP_TABLE_UP2_S 6
373 #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
374 #define ICE_AQ_VSI_UP_TABLE_UP3_S 9
375 #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
376 #define ICE_AQ_VSI_UP_TABLE_UP4_S 12
377 #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
378 #define ICE_AQ_VSI_UP_TABLE_UP5_S 15
379 #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
380 #define ICE_AQ_VSI_UP_TABLE_UP6_S 18
381 #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
382 #define ICE_AQ_VSI_UP_TABLE_UP7_S 21
383 #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
384 __le32 egress_table; /* same defines as for ingress table */
385 /* outer tags section */
388 #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
389 #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
390 #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
391 #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
392 #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
393 #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
394 #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
395 #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
396 #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
397 #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
398 #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
399 #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
400 #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
401 u8 outer_tag_reserved;
402 /* queue mapping section */
403 __le16 mapping_flags;
404 #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
405 #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
406 __le16 q_mapping[16];
407 #define ICE_AQ_VSI_Q_S 0
408 #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
409 __le16 tc_mapping[8];
410 #define ICE_AQ_VSI_TC_Q_OFFSET_S 0
411 #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
412 #define ICE_AQ_VSI_TC_Q_NUM_S 11
413 #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
414 /* queueing option section */
416 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
417 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
418 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
419 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
420 #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
421 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
422 #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
423 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
424 #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
425 #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
426 #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
427 #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
428 #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
430 #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
431 #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
432 #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
434 #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
435 u8 q_opt_reserved[3];
436 /* outer up section */
437 __le32 outer_up_table; /* same structure and defines as ingress tbl */
439 __le16 sect_10_reserved;
440 /* flow director section */
442 #define ICE_AQ_VSI_FD_ENABLE BIT(0)
443 #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
444 #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
445 __le16 max_fd_fltr_dedicated;
446 __le16 max_fd_fltr_shared;
448 #define ICE_AQ_VSI_FD_DEF_Q_S 0
449 #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
450 #define ICE_AQ_VSI_FD_DEF_GRP_S 12
451 #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
452 __le16 fd_report_opt;
453 #define ICE_AQ_VSI_FD_REPORT_Q_S 0
454 #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
455 #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
456 #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
457 #define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
460 #define ICE_AQ_VSI_PASID_ID_S 0
461 #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
462 #define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
466 #define ICE_MAX_NUM_RECIPES 64
468 /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
470 struct ice_aqc_sw_rules {
471 /* ops: add switch rules, referring the number of rules.
472 * ops: update switch rules, referring the number of filters
473 * ops: remove switch rules, referring the entry index.
474 * ops: get switch rules, referring to the number of filters.
476 __le16 num_rules_fltr_entry_index;
482 /* Add/Update/Get/Remove lookup Rx/Tx command/response entry
483 * This structures describes the lookup rules and associated actions. "index"
484 * is returned as part of a response to a successful Add command, and can be
485 * used to identify the rule for Update/Get/Remove commands.
487 struct ice_sw_rule_lkup_rx_tx {
489 #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
490 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
494 /* Bit 0:1 - Action type */
495 #define ICE_SINGLE_ACT_TYPE_S 0x00
496 #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
498 /* Bit 2 - Loop back enable
501 #define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
502 #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
504 /* Action type = 0 - Forward to VSI or VSI list */
505 #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
507 #define ICE_SINGLE_ACT_VSI_ID_S 4
508 #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
509 #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
510 #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
511 /* This bit needs to be set if action is forward to VSI list */
512 #define ICE_SINGLE_ACT_VSI_LIST BIT(14)
513 #define ICE_SINGLE_ACT_VALID_BIT BIT(17)
514 #define ICE_SINGLE_ACT_DROP BIT(18)
516 /* Action type = 1 - Forward to Queue of Queue group */
517 #define ICE_SINGLE_ACT_TO_Q 0x1
518 #define ICE_SINGLE_ACT_Q_INDEX_S 4
519 #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
520 #define ICE_SINGLE_ACT_Q_REGION_S 15
521 #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
522 #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
524 /* Action type = 2 - Prune */
525 #define ICE_SINGLE_ACT_PRUNE 0x2
526 #define ICE_SINGLE_ACT_EGRESS BIT(15)
527 #define ICE_SINGLE_ACT_INGRESS BIT(16)
528 #define ICE_SINGLE_ACT_PRUNET BIT(17)
529 /* Bit 18 should be set to 0 for this action */
531 /* Action type = 2 - Pointer */
532 #define ICE_SINGLE_ACT_PTR 0x2
533 #define ICE_SINGLE_ACT_PTR_VAL_S 4
534 #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
535 /* Bit 18 should be set to 1 */
536 #define ICE_SINGLE_ACT_PTR_BIT BIT(18)
538 /* Action type = 3 - Other actions. Last two bits
539 * are other action identifier
541 #define ICE_SINGLE_ACT_OTHER_ACTS 0x3
542 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
543 #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
544 (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
546 /* Bit 17:18 - Defines other actions */
547 /* Other action = 0 - Mirror VSI */
548 #define ICE_SINGLE_OTHER_ACT_MIRROR 0
549 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
550 #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
551 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
553 /* Other action = 3 - Set Stat count */
554 #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
555 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
556 #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
557 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
559 __le16 index; /* The index of the rule in the lookup table */
560 /* Length and values of the header to be matched per recipe or
567 /* Add/Update/Remove large action command/response entry
568 * "index" is returned as part of a response to a successful Add command, and
569 * can be used to identify the action for Update/Get/Remove commands.
571 struct ice_sw_rule_lg_act {
572 __le16 index; /* Index in large action table */
574 __le32 act[1]; /* array of size for actions */
575 /* Max number of large actions */
576 #define ICE_MAX_LG_ACT 4
577 /* Bit 0:1 - Action type */
578 #define ICE_LG_ACT_TYPE_S 0
579 #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
581 /* Action type = 0 - Forward to VSI or VSI list */
582 #define ICE_LG_ACT_VSI_FORWARDING 0
583 #define ICE_LG_ACT_VSI_ID_S 3
584 #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
585 #define ICE_LG_ACT_VSI_LIST_ID_S 3
586 #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
587 /* This bit needs to be set if action is forward to VSI list */
588 #define ICE_LG_ACT_VSI_LIST BIT(13)
590 #define ICE_LG_ACT_VALID_BIT BIT(16)
592 /* Action type = 1 - Forward to Queue of Queue group */
593 #define ICE_LG_ACT_TO_Q 0x1
594 #define ICE_LG_ACT_Q_INDEX_S 3
595 #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
596 #define ICE_LG_ACT_Q_REGION_S 14
597 #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
598 #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
600 /* Action type = 2 - Prune */
601 #define ICE_LG_ACT_PRUNE 0x2
602 #define ICE_LG_ACT_EGRESS BIT(14)
603 #define ICE_LG_ACT_INGRESS BIT(15)
604 #define ICE_LG_ACT_PRUNET BIT(16)
606 /* Action type = 3 - Mirror VSI */
607 #define ICE_LG_OTHER_ACT_MIRROR 0x3
608 #define ICE_LG_ACT_MIRROR_VSI_ID_S 3
609 #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
611 /* Action type = 5 - Generic Value */
612 #define ICE_LG_ACT_GENERIC 0x5
613 #define ICE_LG_ACT_GENERIC_VALUE_S 3
614 #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
615 #define ICE_LG_ACT_GENERIC_OFFSET_S 19
616 #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
617 #define ICE_LG_ACT_GENERIC_PRIORITY_S 22
618 #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
619 #define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
621 /* Action = 7 - Set Stat count */
622 #define ICE_LG_ACT_STAT_COUNT 0x7
623 #define ICE_LG_ACT_STAT_COUNT_S 3
624 #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
627 /* Add/Update/Remove VSI list command/response entry
628 * "index" is returned as part of a response to a successful Add command, and
629 * can be used to identify the VSI list for Update/Get/Remove commands.
631 struct ice_sw_rule_vsi_list {
632 __le16 index; /* Index of VSI/Prune list */
634 __le16 vsi[1]; /* Array of number_vsi VSI numbers */
637 /* Query VSI list command/response entry */
638 struct ice_sw_rule_vsi_list_query {
640 DECLARE_BITMAP(vsi_list, ICE_MAX_VSI);
643 /* Add switch rule response:
644 * Content of return buffer is same as the input buffer. The status field and
645 * LUT index are updated as part of the response
647 struct ice_aqc_sw_rules_elem {
648 __le16 type; /* Switch rule type, one of T_... */
649 #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
650 #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
651 #define ICE_AQC_SW_RULES_T_LG_ACT 0x2
652 #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
653 #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
654 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
655 #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
658 struct ice_sw_rule_lkup_rx_tx lkup_tx_rx;
659 struct ice_sw_rule_lg_act lg_act;
660 struct ice_sw_rule_vsi_list vsi_list;
661 struct ice_sw_rule_vsi_list_query vsi_list_query;
665 /* Get Default Topology (indirect 0x0400) */
666 struct ice_aqc_get_topo {
675 /* Update TSE (indirect 0x0403)
676 * Get TSE (indirect 0x0404)
677 * Add TSE (indirect 0x0401)
678 * Delete TSE (indirect 0x040F)
679 * Move TSE (indirect 0x0408)
680 * Suspend Nodes (indirect 0x0409)
681 * Resume Nodes (indirect 0x040A)
683 struct ice_aqc_sched_elem_cmd {
684 __le16 num_elem_req; /* Used by commands */
685 __le16 num_elem_resp; /* Used by responses */
691 /* This is the buffer for:
692 * Suspend Nodes (indirect 0x0409)
693 * Resume Nodes (indirect 0x040A)
695 struct ice_aqc_suspend_resume_elem {
699 struct ice_aqc_elem_info_bw {
700 __le16 bw_profile_idx;
704 struct ice_aqc_txsched_elem {
705 u8 elem_type; /* Special field, reserved for some aq calls */
706 #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
707 #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
708 #define ICE_AQC_ELEM_TYPE_TC 0x2
709 #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
710 #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
711 #define ICE_AQC_ELEM_TYPE_LEAF 0x5
712 #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
714 #define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
715 #define ICE_AQC_ELEM_VALID_CIR BIT(1)
716 #define ICE_AQC_ELEM_VALID_EIR BIT(2)
717 #define ICE_AQC_ELEM_VALID_SHARED BIT(3)
719 #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
720 #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
721 #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S)
722 #define ICE_AQC_ELEM_GENERIC_SP_S 0x4
723 #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S)
724 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
725 #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
726 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
727 u8 flags; /* Special field, reserved for some aq calls */
728 #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
729 struct ice_aqc_elem_info_bw cir_bw;
730 struct ice_aqc_elem_info_bw eir_bw;
735 struct ice_aqc_txsched_elem_data {
738 struct ice_aqc_txsched_elem data;
741 struct ice_aqc_txsched_topo_grp_info_hdr {
747 struct ice_aqc_add_elem {
748 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
749 struct ice_aqc_txsched_elem_data generic[1];
752 struct ice_aqc_conf_elem {
753 struct ice_aqc_txsched_elem_data generic[1];
756 struct ice_aqc_get_elem {
757 struct ice_aqc_txsched_elem_data generic[1];
760 struct ice_aqc_get_topo_elem {
761 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
762 struct ice_aqc_txsched_elem_data
763 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
766 struct ice_aqc_delete_elem {
767 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
771 /* Query Port ETS (indirect 0x040E)
773 * This indirect command is used to query port TC node configuration.
775 struct ice_aqc_query_port_ets {
782 struct ice_aqc_port_ets_elem {
785 /* 3 bits for UP per TC 0-7, 4th byte reserved */
788 __le32 port_eir_prof_id;
789 __le32 port_cir_prof_id;
790 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
792 #define ICE_TC_NODE_PRIO_S 0x4
794 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
797 /* Rate limiting profile for
798 * Add RL profile (indirect 0x0410)
799 * Query RL profile (indirect 0x0411)
800 * Remove RL profile (indirect 0x0415)
801 * These indirect commands acts on single or multiple
802 * RL profiles with specified data.
804 struct ice_aqc_rl_profile {
806 __le16 num_processed; /* Only for response. Reserved in Command. */
812 struct ice_aqc_rl_profile_elem {
815 #define ICE_AQC_RL_PROFILE_TYPE_S 0x0
816 #define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
817 #define ICE_AQC_RL_PROFILE_TYPE_CIR 0
818 #define ICE_AQC_RL_PROFILE_TYPE_EIR 1
819 #define ICE_AQC_RL_PROFILE_TYPE_SRL 2
820 /* The following flag is used for Query RL Profile Data */
821 #define ICE_AQC_RL_PROFILE_INVAL_S 0x7
822 #define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
825 __le16 max_burst_size;
831 struct ice_aqc_rl_profile_generic_elem {
832 struct ice_aqc_rl_profile_elem generic[1];
835 /* Query Scheduler Resource Allocation (indirect 0x0412)
836 * This indirect command retrieves the scheduler resources allocated by
837 * EMP Firmware to the given PF.
839 struct ice_aqc_query_txsched_res {
845 struct ice_aqc_generic_sched_props {
847 __le16 logical_levels;
848 u8 flattening_bitmap;
856 struct ice_aqc_layer_props {
859 __le16 max_device_nodes;
862 __le16 max_sibl_grp_sz;
863 __le16 max_cir_rl_profiles;
864 __le16 max_eir_rl_profiles;
865 __le16 max_srl_profiles;
869 struct ice_aqc_query_txsched_res_resp {
870 struct ice_aqc_generic_sched_props sched_props;
871 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
874 /* Get PHY capabilities (indirect 0x0600) */
875 struct ice_aqc_get_phy_caps {
879 /* 18.0 - Report qualified modules */
880 #define ICE_AQC_GET_PHY_RQM BIT(0)
881 /* 18.1 - 18.2 : Report mode
882 * 00b - Report NVM capabilities
883 * 01b - Report topology capabilities
884 * 10b - Report SW configured
886 #define ICE_AQC_REPORT_MODE_S 1
887 #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S)
888 #define ICE_AQC_REPORT_NVM_CAP 0
889 #define ICE_AQC_REPORT_TOPO_CAP BIT(1)
890 #define ICE_AQC_REPORT_SW_CFG BIT(2)
896 /* This is #define of PHY type (Extended):
897 * The first set of defines is for phy_type_low.
899 #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
900 #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
901 #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
902 #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
903 #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
904 #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
905 #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
906 #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
907 #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
908 #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
909 #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
910 #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
911 #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
912 #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
913 #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
914 #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
915 #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
916 #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
917 #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
918 #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
919 #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
920 #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
921 #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
922 #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
923 #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
924 #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
925 #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
926 #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
927 #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
928 #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
929 #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
930 #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
931 #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
932 #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
933 #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
934 #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
935 #define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
936 #define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
937 #define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
938 #define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
939 #define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
940 #define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
941 #define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
942 #define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
943 #define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
944 #define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
945 #define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
946 #define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
947 #define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
948 #define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
949 #define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
950 #define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
951 #define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
952 #define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
953 #define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
954 #define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
955 #define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
956 #define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
957 #define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
958 #define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
959 #define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
960 #define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
961 #define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
962 #define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
963 #define ICE_PHY_TYPE_LOW_MAX_INDEX 63
964 /* The second set of defines is for phy_type_high. */
965 #define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
966 #define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
967 #define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
968 #define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
969 #define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
970 #define ICE_PHY_TYPE_HIGH_MAX_INDEX 19
972 struct ice_aqc_get_phy_caps_data {
973 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
974 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
976 #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
977 #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
978 #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
979 #define ICE_AQC_PHY_EN_LINK BIT(3)
980 #define ICE_AQC_PHY_AN_MODE BIT(4)
981 #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5)
982 #define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
983 #define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0)
985 #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
987 #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
988 #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
989 #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
990 #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
991 #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
992 #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
993 #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
995 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
998 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
999 #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1000 #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1001 #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1002 #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1003 #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1004 #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1005 #define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0)
1006 u8 rsvd1; /* Byte 35 reserved */
1007 u8 extended_compliance_code;
1008 #define ICE_MODULE_TYPE_TOTAL_BYTE 3
1009 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1010 #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1011 #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1012 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1013 #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1014 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1015 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1016 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1017 #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1018 #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1019 #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1020 u8 qualified_module_count;
1021 u8 rsvd2[7]; /* Bytes 47:41 reserved */
1022 #define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1029 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1032 /* Set PHY capabilities (direct 0x0601)
1033 * NOTE: This command must be followed by setup link and restart auto-neg
1035 struct ice_aqc_set_phy_cfg {
1042 /* Set PHY config command data structure */
1043 struct ice_aqc_set_phy_cfg_data {
1044 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1045 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1047 #define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0)
1048 #define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1049 #define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1050 #define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1051 #define ICE_AQ_PHY_ENA_LINK BIT(3)
1052 #define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1053 #define ICE_AQ_PHY_ENA_LESM BIT(6)
1054 #define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1056 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1058 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1062 /* Restart AN command data structure (direct 0x0605)
1063 * Also used for response, with only the lport_num field present.
1065 struct ice_aqc_restart_an {
1069 #define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1070 #define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1074 /* Get link status (indirect 0x0607), also used for Link Status Event */
1075 struct ice_aqc_get_link_status {
1079 #define ICE_AQ_LSE_M 0x3
1080 #define ICE_AQ_LSE_NOP 0x0
1081 #define ICE_AQ_LSE_DIS 0x2
1082 #define ICE_AQ_LSE_ENA 0x3
1083 /* only response uses this flag */
1084 #define ICE_AQ_LSE_IS_ENABLED 0x1
1090 /* Get link status response data structure, also used for Link Status Event */
1091 struct ice_aqc_get_link_status_data {
1092 u8 topo_media_conflict;
1093 #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1094 #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1095 #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1096 #define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1097 #define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1098 #define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1099 #define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1102 #define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1103 #define ICE_AQ_LINK_FAULT BIT(1)
1104 #define ICE_AQ_LINK_FAULT_TX BIT(2)
1105 #define ICE_AQ_LINK_FAULT_RX BIT(3)
1106 #define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1107 #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1108 #define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1109 #define ICE_AQ_SIGNAL_DETECT BIT(7)
1111 #define ICE_AQ_AN_COMPLETED BIT(0)
1112 #define ICE_AQ_LP_AN_ABILITY BIT(1)
1113 #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1114 #define ICE_AQ_FEC_EN BIT(3)
1115 #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1116 #define ICE_AQ_LINK_PAUSE_TX BIT(5)
1117 #define ICE_AQ_LINK_PAUSE_RX BIT(6)
1118 #define ICE_AQ_QUALIFIED_MODULE BIT(7)
1120 #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1121 #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1122 /* Port Tx Suspended */
1123 #define ICE_AQ_LINK_TX_S 2
1124 #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1125 #define ICE_AQ_LINK_TX_ACTIVE 0
1126 #define ICE_AQ_LINK_TX_DRAINED 1
1127 #define ICE_AQ_LINK_TX_FLUSHED 3
1129 __le16 max_frame_size;
1131 #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1132 #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1133 #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1134 #define ICE_AQ_FEC_MASK ICE_M(0x7, 0)
1136 #define ICE_AQ_CFG_PACING_S 3
1137 #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1138 #define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1139 #define ICE_AQ_CFG_PACING_TYPE_AVG 0
1140 #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1141 /* External Device Power Ability */
1143 #define ICE_AQ_PWR_CLASS_M 0x3
1144 #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1145 #define ICE_AQ_LINK_PWR_BASET_HIGH 1
1146 #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1147 #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1148 #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1149 #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1151 #define ICE_AQ_LINK_SPEED_10MB BIT(0)
1152 #define ICE_AQ_LINK_SPEED_100MB BIT(1)
1153 #define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1154 #define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1155 #define ICE_AQ_LINK_SPEED_5GB BIT(4)
1156 #define ICE_AQ_LINK_SPEED_10GB BIT(5)
1157 #define ICE_AQ_LINK_SPEED_20GB BIT(6)
1158 #define ICE_AQ_LINK_SPEED_25GB BIT(7)
1159 #define ICE_AQ_LINK_SPEED_40GB BIT(8)
1160 #define ICE_AQ_LINK_SPEED_50GB BIT(9)
1161 #define ICE_AQ_LINK_SPEED_100GB BIT(10)
1162 #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1163 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1164 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1165 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1168 /* Set event mask command (direct 0x0613) */
1169 struct ice_aqc_set_event_mask {
1173 #define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1174 #define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1175 #define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1176 #define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1177 #define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1178 #define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1179 #define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1180 #define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1181 #define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1185 /* Set MAC Loopback command (direct 0x0620) */
1186 struct ice_aqc_set_mac_lb {
1188 #define ICE_AQ_MAC_LB_EN BIT(0)
1189 #define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1193 /* Set Port Identification LED (direct, 0x06E9) */
1194 struct ice_aqc_set_port_id_led {
1198 #define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1199 #define ICE_AQC_PORT_IDENT_LED_ORIG 0
1203 /* Read/Write SFF EEPROM command (indirect 0x06EE) */
1204 struct ice_aqc_sff_eeprom {
1207 #define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
1208 __le16 i2c_bus_addr;
1209 #define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
1210 #define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
1211 #define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
1212 #define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
1213 #define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
1214 #define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
1215 #define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1216 #define ICE_AQC_SFF_NO_PAGE_CHANGE 0
1217 #define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
1218 #define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
1219 #define ICE_AQC_SFF_IS_WRITE BIT(15)
1220 __le16 i2c_mem_addr;
1222 #define ICE_AQC_SFF_EEPROM_BANK_S 0
1223 #define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1224 #define ICE_AQC_SFF_EEPROM_PAGE_S 8
1225 #define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1230 /* NVM Read command (indirect 0x0701)
1231 * NVM Erase commands (direct 0x0702)
1232 * NVM Update commands (indirect 0x0703)
1234 struct ice_aqc_nvm {
1238 #define ICE_AQC_NVM_LAST_CMD BIT(0)
1239 #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
1240 #define ICE_AQC_NVM_PRESERVATION_S 1
1241 #define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1242 #define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1243 #define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1244 #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1245 #define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1246 __le16 module_typeid;
1248 #define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1253 /* NVM Checksum Command (direct, 0x0706) */
1254 struct ice_aqc_nvm_checksum {
1256 #define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1257 #define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1259 __le16 checksum; /* Used only by response */
1260 #define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1265 * Send to PF command (indirect 0x0801) ID is only used by PF
1267 * Send to VF command (indirect 0x0802) ID is only used by PF
1270 struct ice_aqc_pf_vf_msg {
1277 /* Get LLDP MIB (indirect 0x0A00)
1278 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1279 * as the format is the same.
1281 struct ice_aqc_lldp_get_mib {
1283 #define ICE_AQ_LLDP_MIB_TYPE_S 0
1284 #define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1285 #define ICE_AQ_LLDP_MIB_LOCAL 0
1286 #define ICE_AQ_LLDP_MIB_REMOTE 1
1287 #define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1288 #define ICE_AQ_LLDP_BRID_TYPE_S 2
1289 #define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1290 #define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1291 #define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1292 /* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1293 #define ICE_AQ_LLDP_TX_S 0x4
1294 #define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1295 #define ICE_AQ_LLDP_TX_ACTIVE 0
1296 #define ICE_AQ_LLDP_TX_SUSPENDED 1
1297 #define ICE_AQ_LLDP_TX_FLUSHED 3
1298 /* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1299 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1300 * Get LLDP MIB (0x0A00) response only.
1310 /* Configure LLDP MIB Change Event (direct 0x0A01) */
1311 /* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1312 struct ice_aqc_lldp_set_mib_change {
1314 #define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1315 #define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1319 /* Stop LLDP (direct 0x0A05) */
1320 struct ice_aqc_lldp_stop {
1322 #define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1323 #define ICE_AQ_LLDP_AGENT_STOP 0x0
1324 #define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1325 #define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1329 /* Start LLDP (direct 0x0A06) */
1330 struct ice_aqc_lldp_start {
1332 #define ICE_AQ_LLDP_AGENT_START BIT(0)
1333 #define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1337 /* Get CEE DCBX Oper Config (0x0A07)
1338 * The command uses the generic descriptor struct and
1339 * returns the struct below as an indirect response.
1341 struct ice_aqc_get_cee_dcb_cfg_resp {
1346 __le16 oper_app_prio;
1347 #define ICE_AQC_CEE_APP_FCOE_S 0
1348 #define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1349 #define ICE_AQC_CEE_APP_ISCSI_S 3
1350 #define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1351 #define ICE_AQC_CEE_APP_FIP_S 8
1352 #define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1354 #define ICE_AQC_CEE_PG_STATUS_S 0
1355 #define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1356 #define ICE_AQC_CEE_PFC_STATUS_S 3
1357 #define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1358 #define ICE_AQC_CEE_FCOE_STATUS_S 8
1359 #define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1360 #define ICE_AQC_CEE_ISCSI_STATUS_S 11
1361 #define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1362 #define ICE_AQC_CEE_FIP_STATUS_S 16
1363 #define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1367 /* Set Local LLDP MIB (indirect 0x0A08)
1368 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1370 struct ice_aqc_lldp_set_local_mib {
1372 #define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1373 #define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1374 #define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1375 #define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1376 #define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
1384 /* Stop/Start LLDP Agent (direct 0x0A09)
1385 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
1386 * The same structure is used for the response, with the command field
1387 * being used as the status field.
1389 struct ice_aqc_lldp_stop_start_specific_agent {
1391 #define ICE_AQC_START_STOP_AGENT_M BIT(0)
1392 #define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
1393 #define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
1397 /* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1398 struct ice_aqc_get_set_rss_key {
1399 #define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1400 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1401 #define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1408 #define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1409 #define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1410 #define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1411 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1412 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1414 struct ice_aqc_get_set_rss_keys {
1415 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1416 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1419 /* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1420 struct ice_aqc_get_set_rss_lut {
1421 #define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1422 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1423 #define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x1FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1425 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1426 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1427 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1429 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1430 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1431 #define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1433 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1434 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1435 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1437 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1438 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1439 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1440 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1441 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1442 #define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1444 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1445 #define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1446 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1454 /* Add Tx LAN Queues (indirect 0x0C30) */
1455 struct ice_aqc_add_txqs {
1463 /* This is the descriptor of each queue entry for the Add Tx LAN Queues
1464 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1466 struct ice_aqc_add_txqs_perq {
1472 struct ice_aqc_txsched_elem info;
1475 /* The format of the command buffer for Add Tx LAN Queues (0x0C30)
1476 * is an array of the following structs. Please note that the length of
1477 * each struct ice_aqc_add_tx_qgrp is variable due
1478 * to the variable number of queues in each group!
1480 struct ice_aqc_add_tx_qgrp {
1484 struct ice_aqc_add_txqs_perq txqs[1];
1487 /* Disable Tx LAN Queues (indirect 0x0C31) */
1488 struct ice_aqc_dis_txqs {
1490 #define ICE_AQC_Q_DIS_CMD_S 0
1491 #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
1492 #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
1493 #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
1494 #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
1495 #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
1496 #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
1497 #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
1499 __le16 vmvf_and_timeout;
1500 #define ICE_AQC_Q_DIS_VMVF_NUM_S 0
1501 #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1502 #define ICE_AQC_Q_DIS_TIMEOUT_S 10
1503 #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1504 __le32 blocked_cgds;
1509 /* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
1510 * contains the following structures, arrayed one after the
1512 * Note: Since the q_id is 16 bits wide, if the
1513 * number of queues is even, then 2 bytes of alignment MUST be
1514 * added before the start of the next group, to allow correct
1515 * alignment of the parent_teid field.
1517 struct ice_aqc_dis_txq_item {
1521 /* The length of the q_id array varies according to num_qs */
1523 /* This only applies from F8 onward */
1524 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
1525 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
1526 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1527 #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
1528 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1531 struct ice_aqc_dis_txq {
1532 struct ice_aqc_dis_txq_item qgrps[1];
1535 /* Configure Firmware Logging Command (indirect 0xFF09)
1536 * Logging Information Read Response (indirect 0xFF10)
1537 * Note: The 0xFF10 command has no input parameters.
1539 struct ice_aqc_fw_logging {
1541 #define ICE_AQC_FW_LOG_AQ_EN BIT(0)
1542 #define ICE_AQC_FW_LOG_UART_EN BIT(1)
1544 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
1545 #define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
1546 #define ICE_AQC_FW_LOG_UART_VALID BIT(1)
1552 enum ice_aqc_fw_logging_mod {
1553 ICE_AQC_FW_LOG_ID_GENERAL = 0,
1554 ICE_AQC_FW_LOG_ID_CTRL,
1555 ICE_AQC_FW_LOG_ID_LINK,
1556 ICE_AQC_FW_LOG_ID_LINK_TOPO,
1557 ICE_AQC_FW_LOG_ID_DNL,
1558 ICE_AQC_FW_LOG_ID_I2C,
1559 ICE_AQC_FW_LOG_ID_SDP,
1560 ICE_AQC_FW_LOG_ID_MDIO,
1561 ICE_AQC_FW_LOG_ID_ADMINQ,
1562 ICE_AQC_FW_LOG_ID_HDMA,
1563 ICE_AQC_FW_LOG_ID_LLDP,
1564 ICE_AQC_FW_LOG_ID_DCBX,
1565 ICE_AQC_FW_LOG_ID_DCB,
1566 ICE_AQC_FW_LOG_ID_NETPROXY,
1567 ICE_AQC_FW_LOG_ID_NVM,
1568 ICE_AQC_FW_LOG_ID_AUTH,
1569 ICE_AQC_FW_LOG_ID_VPD,
1570 ICE_AQC_FW_LOG_ID_IOSF,
1571 ICE_AQC_FW_LOG_ID_PARSER,
1572 ICE_AQC_FW_LOG_ID_SW,
1573 ICE_AQC_FW_LOG_ID_SCHEDULER,
1574 ICE_AQC_FW_LOG_ID_TXQ,
1575 ICE_AQC_FW_LOG_ID_RSVD,
1576 ICE_AQC_FW_LOG_ID_POST,
1577 ICE_AQC_FW_LOG_ID_WATCHDOG,
1578 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
1579 ICE_AQC_FW_LOG_ID_MNG,
1580 ICE_AQC_FW_LOG_ID_MAX,
1583 /* This is the buffer for both of the logging commands.
1584 * The entry array size depends on the datalen parameter in the descriptor.
1585 * There will be a total of datalen / 2 entries.
1587 struct ice_aqc_fw_logging_data {
1589 #define ICE_AQC_FW_LOG_ID_S 0
1590 #define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
1592 #define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */
1593 #define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */
1595 #define ICE_AQC_FW_LOG_EN_S 12
1596 #define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
1597 #define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
1598 #define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
1599 #define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
1600 #define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */
1603 /* Get/Clear FW Log (indirect 0xFF11) */
1604 struct ice_aqc_get_clear_fw_log {
1606 #define ICE_AQC_FW_LOG_CLEAR BIT(0)
1607 #define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
1613 /* Download Package (indirect 0x0C40) */
1614 /* Also used for Update Package (indirect 0x0C42) */
1615 struct ice_aqc_download_pkg {
1617 #define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
1624 struct ice_aqc_download_pkg_resp {
1625 __le32 error_offset;
1631 /* Get Package Info List (indirect 0x0C43) */
1632 struct ice_aqc_get_pkg_info_list {
1639 /* Version format for packages */
1640 struct ice_pkg_ver {
1647 #define ICE_PKG_NAME_SIZE 32
1649 struct ice_aqc_get_pkg_info {
1650 struct ice_pkg_ver ver;
1651 char name[ICE_PKG_NAME_SIZE];
1654 u8 is_active_at_boot;
1658 /* Get Package Info List response buffer format (0x0C43) */
1659 struct ice_aqc_get_pkg_info_resp {
1661 struct ice_aqc_get_pkg_info pkg_info[1];
1665 * struct ice_aq_desc - Admin Queue (AQ) descriptor
1666 * @flags: ICE_AQ_FLAG_* flags
1667 * @opcode: AQ command opcode
1668 * @datalen: length in bytes of indirect/external data buffer
1669 * @retval: return value from firmware
1670 * @cookie_h: opaque data high-half
1671 * @cookie_l: opaque data low-half
1672 * @params: command-specific parameters
1674 * Descriptor format for commands the driver posts on the Admin Transmit Queue
1675 * (ATQ). The firmware writes back onto the command descriptor and returns
1676 * the result of the command. Asynchronous events that are not an immediate
1677 * result of the command are written to the Admin Receive Queue (ARQ) using
1678 * the same descriptor format. Descriptors are in little-endian notation with
1681 struct ice_aq_desc {
1690 struct ice_aqc_generic generic;
1691 struct ice_aqc_get_ver get_ver;
1692 struct ice_aqc_driver_ver driver_ver;
1693 struct ice_aqc_q_shutdown q_shutdown;
1694 struct ice_aqc_req_res res_owner;
1695 struct ice_aqc_manage_mac_read mac_read;
1696 struct ice_aqc_manage_mac_write mac_write;
1697 struct ice_aqc_clear_pxe clear_pxe;
1698 struct ice_aqc_list_caps get_cap;
1699 struct ice_aqc_get_phy_caps get_phy;
1700 struct ice_aqc_set_phy_cfg set_phy;
1701 struct ice_aqc_restart_an restart_an;
1702 struct ice_aqc_sff_eeprom read_write_sff_param;
1703 struct ice_aqc_set_port_id_led set_port_id_led;
1704 struct ice_aqc_get_sw_cfg get_sw_conf;
1705 struct ice_aqc_sw_rules sw_rules;
1706 struct ice_aqc_get_topo get_topo;
1707 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
1708 struct ice_aqc_query_txsched_res query_sched_res;
1709 struct ice_aqc_query_port_ets port_ets;
1710 struct ice_aqc_rl_profile rl_profile;
1711 struct ice_aqc_nvm nvm;
1712 struct ice_aqc_nvm_checksum nvm_checksum;
1713 struct ice_aqc_pf_vf_msg virt;
1714 struct ice_aqc_lldp_get_mib lldp_get_mib;
1715 struct ice_aqc_lldp_set_mib_change lldp_set_event;
1716 struct ice_aqc_lldp_stop lldp_stop;
1717 struct ice_aqc_lldp_start lldp_start;
1718 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
1719 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
1720 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
1721 struct ice_aqc_get_set_rss_key get_set_rss_key;
1722 struct ice_aqc_add_txqs add_txqs;
1723 struct ice_aqc_dis_txqs dis_txqs;
1724 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
1725 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
1726 struct ice_aqc_fw_logging fw_logging;
1727 struct ice_aqc_get_clear_fw_log get_clear_fw_log;
1728 struct ice_aqc_download_pkg download_pkg;
1729 struct ice_aqc_set_mac_lb set_mac_lb;
1730 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
1731 struct ice_aqc_set_event_mask set_event_mask;
1732 struct ice_aqc_get_link_status get_link_status;
1736 /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
1737 #define ICE_AQ_LG_BUF 512
1739 #define ICE_AQ_FLAG_ERR_S 2
1740 #define ICE_AQ_FLAG_LB_S 9
1741 #define ICE_AQ_FLAG_RD_S 10
1742 #define ICE_AQ_FLAG_BUF_S 12
1743 #define ICE_AQ_FLAG_SI_S 13
1745 #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
1746 #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
1747 #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
1748 #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
1749 #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
1753 ICE_AQ_RC_OK = 0, /* Success */
1754 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
1755 ICE_AQ_RC_ENOENT = 2, /* No such element */
1756 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
1757 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
1758 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
1759 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
1760 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
1761 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
1762 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
1763 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
1764 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
1765 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
1768 /* Admin Queue command opcodes */
1769 enum ice_adminq_opc {
1771 ice_aqc_opc_get_ver = 0x0001,
1772 ice_aqc_opc_driver_ver = 0x0002,
1773 ice_aqc_opc_q_shutdown = 0x0003,
1775 /* resource ownership */
1776 ice_aqc_opc_req_res = 0x0008,
1777 ice_aqc_opc_release_res = 0x0009,
1779 /* device/function capabilities */
1780 ice_aqc_opc_list_func_caps = 0x000A,
1781 ice_aqc_opc_list_dev_caps = 0x000B,
1783 /* manage MAC address */
1784 ice_aqc_opc_manage_mac_read = 0x0107,
1785 ice_aqc_opc_manage_mac_write = 0x0108,
1788 ice_aqc_opc_clear_pxe_mode = 0x0110,
1790 /* internal switch commands */
1791 ice_aqc_opc_get_sw_cfg = 0x0200,
1793 /* Alloc/Free/Get Resources */
1794 ice_aqc_opc_alloc_res = 0x0208,
1795 ice_aqc_opc_free_res = 0x0209,
1798 ice_aqc_opc_add_vsi = 0x0210,
1799 ice_aqc_opc_update_vsi = 0x0211,
1800 ice_aqc_opc_free_vsi = 0x0213,
1802 /* switch rules population commands */
1803 ice_aqc_opc_add_sw_rules = 0x02A0,
1804 ice_aqc_opc_update_sw_rules = 0x02A1,
1805 ice_aqc_opc_remove_sw_rules = 0x02A2,
1807 ice_aqc_opc_clear_pf_cfg = 0x02A4,
1809 /* transmit scheduler commands */
1810 ice_aqc_opc_get_dflt_topo = 0x0400,
1811 ice_aqc_opc_add_sched_elems = 0x0401,
1812 ice_aqc_opc_cfg_sched_elems = 0x0403,
1813 ice_aqc_opc_get_sched_elems = 0x0404,
1814 ice_aqc_opc_suspend_sched_elems = 0x0409,
1815 ice_aqc_opc_resume_sched_elems = 0x040A,
1816 ice_aqc_opc_query_port_ets = 0x040E,
1817 ice_aqc_opc_delete_sched_elems = 0x040F,
1818 ice_aqc_opc_add_rl_profiles = 0x0410,
1819 ice_aqc_opc_query_sched_res = 0x0412,
1820 ice_aqc_opc_remove_rl_profiles = 0x0415,
1823 ice_aqc_opc_get_phy_caps = 0x0600,
1824 ice_aqc_opc_set_phy_cfg = 0x0601,
1825 ice_aqc_opc_restart_an = 0x0605,
1826 ice_aqc_opc_get_link_status = 0x0607,
1827 ice_aqc_opc_set_event_mask = 0x0613,
1828 ice_aqc_opc_set_mac_lb = 0x0620,
1829 ice_aqc_opc_set_port_id_led = 0x06E9,
1830 ice_aqc_opc_sff_eeprom = 0x06EE,
1833 ice_aqc_opc_nvm_read = 0x0701,
1834 ice_aqc_opc_nvm_checksum = 0x0706,
1836 /* PF/VF mailbox commands */
1837 ice_mbx_opc_send_msg_to_pf = 0x0801,
1838 ice_mbx_opc_send_msg_to_vf = 0x0802,
1840 ice_aqc_opc_lldp_get_mib = 0x0A00,
1841 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
1842 ice_aqc_opc_lldp_stop = 0x0A05,
1843 ice_aqc_opc_lldp_start = 0x0A06,
1844 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
1845 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
1846 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
1849 ice_aqc_opc_set_rss_key = 0x0B02,
1850 ice_aqc_opc_set_rss_lut = 0x0B03,
1851 ice_aqc_opc_get_rss_key = 0x0B04,
1852 ice_aqc_opc_get_rss_lut = 0x0B05,
1854 /* Tx queue handling commands/events */
1855 ice_aqc_opc_add_txqs = 0x0C30,
1856 ice_aqc_opc_dis_txqs = 0x0C31,
1858 /* package commands */
1859 ice_aqc_opc_download_pkg = 0x0C40,
1860 ice_aqc_opc_update_pkg = 0x0C42,
1861 ice_aqc_opc_get_pkg_info_list = 0x0C43,
1863 /* debug commands */
1864 ice_aqc_opc_fw_logging = 0xFF09,
1865 ice_aqc_opc_fw_logging_info = 0xFF10,
1868 #endif /* _ICE_ADMINQ_CMD_H_ */