1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019, Intel Corporation. */
5 #include "ice_dcb_lib.h"
8 * __ice_vsi_get_qs_contig - Assign a contiguous chunk of queues to VSI
9 * @qs_cfg: gathered variables needed for PF->VSI queues assignment
11 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap
13 static int __ice_vsi_get_qs_contig(struct ice_qs_cfg *qs_cfg)
17 mutex_lock(qs_cfg->qs_mutex);
18 offset = bitmap_find_next_zero_area(qs_cfg->pf_map, qs_cfg->pf_map_size,
19 0, qs_cfg->q_count, 0);
20 if (offset >= qs_cfg->pf_map_size) {
21 mutex_unlock(qs_cfg->qs_mutex);
25 bitmap_set(qs_cfg->pf_map, offset, qs_cfg->q_count);
26 for (i = 0; i < qs_cfg->q_count; i++)
27 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = i + offset;
28 mutex_unlock(qs_cfg->qs_mutex);
34 * __ice_vsi_get_qs_sc - Assign a scattered queues from PF to VSI
35 * @qs_cfg: gathered variables needed for pf->vsi queues assignment
37 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap
39 static int __ice_vsi_get_qs_sc(struct ice_qs_cfg *qs_cfg)
43 mutex_lock(qs_cfg->qs_mutex);
44 for (i = 0; i < qs_cfg->q_count; i++) {
45 index = find_next_zero_bit(qs_cfg->pf_map,
46 qs_cfg->pf_map_size, index);
47 if (index >= qs_cfg->pf_map_size)
49 set_bit(index, qs_cfg->pf_map);
50 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = index;
52 mutex_unlock(qs_cfg->qs_mutex);
56 for (index = 0; index < i; index++) {
57 clear_bit(qs_cfg->vsi_map[index], qs_cfg->pf_map);
58 qs_cfg->vsi_map[index + qs_cfg->vsi_map_offset] = 0;
60 mutex_unlock(qs_cfg->qs_mutex);
66 * ice_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
67 * @pf: the PF being configured
69 * @ena: enable or disable state of the queue
71 * This routine will wait for the given Rx queue of the PF to reach the
72 * enabled or disabled state.
73 * Returns -ETIMEDOUT in case of failing to reach the requested state after
74 * multiple retries; else will return 0 in case of success.
76 static int ice_pf_rxq_wait(struct ice_pf *pf, int pf_q, bool ena)
80 for (i = 0; i < ICE_Q_WAIT_MAX_RETRY; i++) {
81 if (ena == !!(rd32(&pf->hw, QRX_CTRL(pf_q)) &
82 QRX_CTRL_QENA_STAT_M))
92 * ice_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
93 * @vsi: the VSI being configured
94 * @v_idx: index of the vector in the VSI struct
96 * We allocate one q_vector and set default value for ITR setting associated
97 * with this q_vector. If allocation fails we return -ENOMEM.
99 static int ice_vsi_alloc_q_vector(struct ice_vsi *vsi, int v_idx)
101 struct ice_pf *pf = vsi->back;
102 struct ice_q_vector *q_vector;
104 /* allocate q_vector */
105 q_vector = devm_kzalloc(ice_pf_to_dev(pf), sizeof(*q_vector),
111 q_vector->v_idx = v_idx;
112 q_vector->tx.itr_setting = ICE_DFLT_TX_ITR;
113 q_vector->rx.itr_setting = ICE_DFLT_RX_ITR;
114 if (vsi->type == ICE_VSI_VF)
116 /* only set affinity_mask if the CPU is online */
117 if (cpu_online(v_idx))
118 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
120 /* This will not be called in the driver load path because the netdev
121 * will not be created yet. All other cases with register the NAPI
122 * handler here (i.e. resume, reset/rebuild, etc.)
125 netif_napi_add(vsi->netdev, &q_vector->napi, ice_napi_poll,
129 /* tie q_vector and VSI together */
130 vsi->q_vectors[v_idx] = q_vector;
136 * ice_free_q_vector - Free memory allocated for a specific interrupt vector
137 * @vsi: VSI having the memory freed
138 * @v_idx: index of the vector to be freed
140 static void ice_free_q_vector(struct ice_vsi *vsi, int v_idx)
142 struct ice_q_vector *q_vector;
143 struct ice_pf *pf = vsi->back;
144 struct ice_ring *ring;
147 dev = ice_pf_to_dev(pf);
148 if (!vsi->q_vectors[v_idx]) {
149 dev_dbg(dev, "Queue vector at index %d not found\n", v_idx);
152 q_vector = vsi->q_vectors[v_idx];
154 ice_for_each_ring(ring, q_vector->tx)
155 ring->q_vector = NULL;
156 ice_for_each_ring(ring, q_vector->rx)
157 ring->q_vector = NULL;
159 /* only VSI with an associated netdev is set up with NAPI */
161 netif_napi_del(&q_vector->napi);
163 devm_kfree(dev, q_vector);
164 vsi->q_vectors[v_idx] = NULL;
168 * ice_cfg_itr_gran - set the ITR granularity to 2 usecs if not already set
169 * @hw: board specific structure
171 static void ice_cfg_itr_gran(struct ice_hw *hw)
173 u32 regval = rd32(hw, GLINT_CTL);
175 /* no need to update global register if ITR gran is already set */
176 if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) &&
177 (((regval & GLINT_CTL_ITR_GRAN_200_M) >>
178 GLINT_CTL_ITR_GRAN_200_S) == ICE_ITR_GRAN_US) &&
179 (((regval & GLINT_CTL_ITR_GRAN_100_M) >>
180 GLINT_CTL_ITR_GRAN_100_S) == ICE_ITR_GRAN_US) &&
181 (((regval & GLINT_CTL_ITR_GRAN_50_M) >>
182 GLINT_CTL_ITR_GRAN_50_S) == ICE_ITR_GRAN_US) &&
183 (((regval & GLINT_CTL_ITR_GRAN_25_M) >>
184 GLINT_CTL_ITR_GRAN_25_S) == ICE_ITR_GRAN_US))
187 regval = ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_200_S) &
188 GLINT_CTL_ITR_GRAN_200_M) |
189 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_100_S) &
190 GLINT_CTL_ITR_GRAN_100_M) |
191 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_50_S) &
192 GLINT_CTL_ITR_GRAN_50_M) |
193 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_25_S) &
194 GLINT_CTL_ITR_GRAN_25_M);
195 wr32(hw, GLINT_CTL, regval);
199 * ice_calc_q_handle - calculate the queue handle
200 * @vsi: VSI that ring belongs to
201 * @ring: ring to get the absolute queue index
202 * @tc: traffic class number
204 static u16 ice_calc_q_handle(struct ice_vsi *vsi, struct ice_ring *ring, u8 tc)
206 WARN_ONCE(ice_ring_is_xdp(ring) && tc,
207 "XDP ring can't belong to TC other than 0");
209 /* Idea here for calculation is that we subtract the number of queue
210 * count from TC that ring belongs to from it's absolute queue index
211 * and as a result we get the queue's index within TC.
213 return ring->q_index - vsi->tc_cfg.tc_info[tc].qoffset;
217 * ice_setup_tx_ctx - setup a struct ice_tlan_ctx instance
218 * @ring: The Tx ring to configure
219 * @tlan_ctx: Pointer to the Tx LAN queue context structure to be initialized
220 * @pf_q: queue index in the PF space
222 * Configure the Tx descriptor ring in TLAN context.
225 ice_setup_tx_ctx(struct ice_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf_q)
227 struct ice_vsi *vsi = ring->vsi;
228 struct ice_hw *hw = &vsi->back->hw;
230 tlan_ctx->base = ring->dma >> ICE_TLAN_CTX_BASE_S;
232 tlan_ctx->port_num = vsi->port_info->lport;
234 /* Transmit Queue Length */
235 tlan_ctx->qlen = ring->count;
237 ice_set_cgd_num(tlan_ctx, ring);
240 tlan_ctx->pf_num = hw->pf_id;
242 /* queue belongs to a specific VSI type
243 * VF / VM index should be programmed per vmvf_type setting:
244 * for vmvf_type = VF, it is VF number between 0-256
245 * for vmvf_type = VM, it is VM number between 0-767
246 * for PF or EMP this field should be set to zero
252 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
255 /* Firmware expects vmvf_num to be absolute VF ID */
256 tlan_ctx->vmvf_num = hw->func_caps.vf_base_id + vsi->vf_id;
257 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VF;
263 /* make sure the context is associated with the right VSI */
264 tlan_ctx->src_vsi = ice_get_hw_vsi_num(hw, vsi->idx);
266 tlan_ctx->tso_ena = ICE_TX_LEGACY;
267 tlan_ctx->tso_qnum = pf_q;
269 /* Legacy or Advanced Host Interface:
270 * 0: Advanced Host Interface
271 * 1: Legacy Host Interface
273 tlan_ctx->legacy_int = ICE_TX_LEGACY;
277 * ice_setup_rx_ctx - Configure a receive ring context
278 * @ring: The Rx ring to configure
280 * Configure the Rx descriptor ring in RLAN context.
282 int ice_setup_rx_ctx(struct ice_ring *ring)
284 int chain_len = ICE_MAX_CHAINED_RX_BUFS;
285 struct ice_vsi *vsi = ring->vsi;
286 u32 rxdid = ICE_RXDID_FLEX_NIC;
287 struct ice_rlan_ctx rlan_ctx;
295 /* what is Rx queue number in global space of 2K Rx queues */
296 pf_q = vsi->rxq_map[ring->q_index];
298 /* clear the context structure first */
299 memset(&rlan_ctx, 0, sizeof(rlan_ctx));
301 ring->rx_buf_len = vsi->rx_buf_len;
303 if (ring->vsi->type == ICE_VSI_PF) {
304 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq))
305 xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev,
308 ring->xsk_umem = ice_xsk_umem(ring);
309 if (ring->xsk_umem) {
310 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
312 ring->rx_buf_len = ring->xsk_umem->chunk_size_nohr -
314 /* For AF_XDP ZC, we disallow packets to span on
315 * multiple buffers, thus letting us skip that
316 * handling in the fast-path.
319 ring->zca.free = ice_zca_free;
320 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
326 dev_info(&vsi->back->pdev->dev, "Registered XDP mem model MEM_TYPE_ZERO_COPY on Rx ring %d\n",
329 ring->zca.free = NULL;
330 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq))
331 xdp_rxq_info_reg(&ring->xdp_rxq,
335 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
336 MEM_TYPE_PAGE_SHARED,
342 /* Receive Queue Base Address.
343 * Indicates the starting address of the descriptor queue defined in
346 rlan_ctx.base = ring->dma >> 7;
348 rlan_ctx.qlen = ring->count;
350 /* Receive Packet Data Buffer Size.
351 * The Packet Data Buffer Size is defined in 128 byte units.
353 rlan_ctx.dbuf = ring->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
355 /* use 32 byte descriptors */
358 /* Strip the Ethernet CRC bytes before the packet is posted to host
361 rlan_ctx.crcstrip = 1;
363 /* L2TSEL flag defines the reported L2 Tags in the receive descriptor */
366 rlan_ctx.dtype = ICE_RX_DTYPE_NO_SPLIT;
367 rlan_ctx.hsplit_0 = ICE_RLAN_RX_HSPLIT_0_NO_SPLIT;
368 rlan_ctx.hsplit_1 = ICE_RLAN_RX_HSPLIT_1_NO_SPLIT;
370 /* This controls whether VLAN is stripped from inner headers
371 * The VLAN in the inner L2 header is stripped to the receive
372 * descriptor if enabled by this flag.
376 /* Max packet size for this queue - must not be set to a larger value
379 rlan_ctx.rxmax = min_t(u16, vsi->max_frame,
380 chain_len * ring->rx_buf_len);
382 /* Rx queue threshold in units of 64 */
383 rlan_ctx.lrxqthresh = 1;
385 /* Enable Flexible Descriptors in the queue context which
386 * allows this driver to select a specific receive descriptor format
388 if (vsi->type != ICE_VSI_VF) {
389 regval = rd32(hw, QRXFLXP_CNTXT(pf_q));
390 regval |= (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
391 QRXFLXP_CNTXT_RXDID_IDX_M;
393 /* increasing context priority to pick up profile ID;
394 * default is 0x01; setting to 0x03 to ensure profile
395 * is programming if prev context is of same priority
397 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
398 QRXFLXP_CNTXT_RXDID_PRIO_M;
400 wr32(hw, QRXFLXP_CNTXT(pf_q), regval);
403 /* Absolute queue number out of 2K needs to be passed */
404 err = ice_write_rxq_ctx(hw, &rlan_ctx, pf_q);
406 dev_err(&vsi->back->pdev->dev,
407 "Failed to set LAN Rx queue context for absolute Rx queue %d error: %d\n",
412 if (vsi->type == ICE_VSI_VF)
415 /* configure Rx buffer alignment */
416 if (!vsi->netdev || test_bit(ICE_FLAG_LEGACY_RX, vsi->back->flags))
417 ice_clear_ring_build_skb_ena(ring);
419 ice_set_ring_build_skb_ena(ring);
421 /* init queue specific tail register */
422 ring->tail = hw->hw_addr + QRX_TAIL(pf_q);
423 writel(0, ring->tail);
425 err = ring->xsk_umem ?
426 ice_alloc_rx_bufs_slow_zc(ring, ICE_DESC_UNUSED(ring)) :
427 ice_alloc_rx_bufs(ring, ICE_DESC_UNUSED(ring));
429 dev_info(&vsi->back->pdev->dev,
430 "Failed allocate some buffers on %sRx ring %d (pf_q %d)\n",
431 ring->xsk_umem ? "UMEM enabled " : "",
432 ring->q_index, pf_q);
438 * __ice_vsi_get_qs - helper function for assigning queues from PF to VSI
439 * @qs_cfg: gathered variables needed for pf->vsi queues assignment
441 * This function first tries to find contiguous space. If it is not successful,
442 * it tries with the scatter approach.
444 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap
446 int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg)
450 ret = __ice_vsi_get_qs_contig(qs_cfg);
452 /* contig failed, so try with scatter approach */
453 qs_cfg->mapping_mode = ICE_VSI_MAP_SCATTER;
454 qs_cfg->q_count = min_t(u16, qs_cfg->q_count,
455 qs_cfg->scatter_count);
456 ret = __ice_vsi_get_qs_sc(qs_cfg);
462 * ice_vsi_ctrl_rx_ring - Start or stop a VSI's Rx ring
463 * @vsi: the VSI being configured
464 * @ena: start or stop the Rx rings
465 * @rxq_idx: Rx queue index
467 int ice_vsi_ctrl_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx)
469 int pf_q = vsi->rxq_map[rxq_idx];
470 struct ice_pf *pf = vsi->back;
471 struct ice_hw *hw = &pf->hw;
475 rx_reg = rd32(hw, QRX_CTRL(pf_q));
477 /* Skip if the queue is already in the requested state */
478 if (ena == !!(rx_reg & QRX_CTRL_QENA_STAT_M))
481 /* turn on/off the queue */
483 rx_reg |= QRX_CTRL_QENA_REQ_M;
485 rx_reg &= ~QRX_CTRL_QENA_REQ_M;
486 wr32(hw, QRX_CTRL(pf_q), rx_reg);
488 /* wait for the change to finish */
489 ret = ice_pf_rxq_wait(pf, pf_q, ena);
491 dev_err(ice_pf_to_dev(pf),
492 "VSI idx %d Rx ring %d %sable timeout\n",
493 vsi->idx, pf_q, (ena ? "en" : "dis"));
499 * ice_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
500 * @vsi: the VSI being configured
502 * We allocate one q_vector per queue interrupt. If allocation fails we
505 int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi)
507 struct ice_pf *pf = vsi->back;
508 int v_idx = 0, num_q_vectors;
512 dev = ice_pf_to_dev(pf);
513 if (vsi->q_vectors[0]) {
514 dev_dbg(dev, "VSI %d has existing q_vectors\n", vsi->vsi_num);
518 num_q_vectors = vsi->num_q_vectors;
520 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
521 err = ice_vsi_alloc_q_vector(vsi, v_idx);
530 ice_free_q_vector(vsi, v_idx);
532 dev_err(dev, "Failed to allocate %d q_vector for VSI %d, ret=%d\n",
533 vsi->num_q_vectors, vsi->vsi_num, err);
534 vsi->num_q_vectors = 0;
539 * ice_vsi_map_rings_to_vectors - Map VSI rings to interrupt vectors
540 * @vsi: the VSI being configured
542 * This function maps descriptor rings to the queue-specific vectors allotted
543 * through the MSI-X enabling code. On a constrained vector budget, we map Tx
544 * and Rx rings to the vector as "efficiently" as possible.
546 void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi)
548 int q_vectors = vsi->num_q_vectors;
549 int tx_rings_rem, rx_rings_rem;
552 /* initially assigning remaining rings count to VSIs num queue value */
553 tx_rings_rem = vsi->num_txq;
554 rx_rings_rem = vsi->num_rxq;
556 for (v_id = 0; v_id < q_vectors; v_id++) {
557 struct ice_q_vector *q_vector = vsi->q_vectors[v_id];
558 int tx_rings_per_v, rx_rings_per_v, q_id, q_base;
560 /* Tx rings mapping to vector */
561 tx_rings_per_v = DIV_ROUND_UP(tx_rings_rem, q_vectors - v_id);
562 q_vector->num_ring_tx = tx_rings_per_v;
563 q_vector->tx.ring = NULL;
564 q_vector->tx.itr_idx = ICE_TX_ITR;
565 q_base = vsi->num_txq - tx_rings_rem;
567 for (q_id = q_base; q_id < (q_base + tx_rings_per_v); q_id++) {
568 struct ice_ring *tx_ring = vsi->tx_rings[q_id];
570 tx_ring->q_vector = q_vector;
571 tx_ring->next = q_vector->tx.ring;
572 q_vector->tx.ring = tx_ring;
574 tx_rings_rem -= tx_rings_per_v;
576 /* Rx rings mapping to vector */
577 rx_rings_per_v = DIV_ROUND_UP(rx_rings_rem, q_vectors - v_id);
578 q_vector->num_ring_rx = rx_rings_per_v;
579 q_vector->rx.ring = NULL;
580 q_vector->rx.itr_idx = ICE_RX_ITR;
581 q_base = vsi->num_rxq - rx_rings_rem;
583 for (q_id = q_base; q_id < (q_base + rx_rings_per_v); q_id++) {
584 struct ice_ring *rx_ring = vsi->rx_rings[q_id];
586 rx_ring->q_vector = q_vector;
587 rx_ring->next = q_vector->rx.ring;
588 q_vector->rx.ring = rx_ring;
590 rx_rings_rem -= rx_rings_per_v;
595 * ice_vsi_free_q_vectors - Free memory allocated for interrupt vectors
596 * @vsi: the VSI having memory freed
598 void ice_vsi_free_q_vectors(struct ice_vsi *vsi)
602 ice_for_each_q_vector(vsi, v_idx)
603 ice_free_q_vector(vsi, v_idx);
607 * ice_vsi_cfg_txq - Configure single Tx queue
608 * @vsi: the VSI that queue belongs to
609 * @ring: Tx ring to be configured
610 * @qg_buf: queue group buffer
613 ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_ring *ring,
614 struct ice_aqc_add_tx_qgrp *qg_buf)
616 struct ice_tlan_ctx tlan_ctx = { 0 };
617 struct ice_aqc_add_txqs_perq *txq;
618 struct ice_pf *pf = vsi->back;
619 u8 buf_len = sizeof(*qg_buf);
620 enum ice_status status;
624 pf_q = ring->reg_idx;
625 ice_setup_tx_ctx(ring, &tlan_ctx, pf_q);
626 /* copy context contents into the qg_buf */
627 qg_buf->txqs[0].txq_id = cpu_to_le16(pf_q);
628 ice_set_ctx((u8 *)&tlan_ctx, qg_buf->txqs[0].txq_ctx,
631 /* init queue specific tail reg. It is referred as
632 * transmit comm scheduler queue doorbell.
634 ring->tail = pf->hw.hw_addr + QTX_COMM_DBELL(pf_q);
636 if (IS_ENABLED(CONFIG_DCB))
641 /* Add unique software queue handle of the Tx queue per
642 * TC into the VSI Tx ring
644 ring->q_handle = ice_calc_q_handle(vsi, ring, tc);
646 status = ice_ena_vsi_txq(vsi->port_info, vsi->idx, tc, ring->q_handle,
647 1, qg_buf, buf_len, NULL);
649 dev_err(ice_pf_to_dev(pf),
650 "Failed to set LAN Tx queue context, error: %d\n",
655 /* Add Tx Queue TEID into the VSI Tx ring from the
656 * response. This will complete configuring and
657 * enabling the queue.
659 txq = &qg_buf->txqs[0];
660 if (pf_q == le16_to_cpu(txq->txq_id))
661 ring->txq_teid = le32_to_cpu(txq->q_teid);
667 * ice_cfg_itr - configure the initial interrupt throttle values
668 * @hw: pointer to the HW structure
669 * @q_vector: interrupt vector that's being configured
671 * Configure interrupt throttling values for the ring containers that are
672 * associated with the interrupt vector passed in.
674 void ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector)
676 ice_cfg_itr_gran(hw);
678 if (q_vector->num_ring_rx) {
679 struct ice_ring_container *rc = &q_vector->rx;
681 rc->target_itr = ITR_TO_REG(rc->itr_setting);
682 rc->next_update = jiffies + 1;
683 rc->current_itr = rc->target_itr;
684 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx),
685 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S);
688 if (q_vector->num_ring_tx) {
689 struct ice_ring_container *rc = &q_vector->tx;
691 rc->target_itr = ITR_TO_REG(rc->itr_setting);
692 rc->next_update = jiffies + 1;
693 rc->current_itr = rc->target_itr;
694 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx),
695 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S);
700 * ice_cfg_txq_interrupt - configure interrupt on Tx queue
701 * @vsi: the VSI being configured
702 * @txq: Tx queue being mapped to MSI-X vector
703 * @msix_idx: MSI-X vector index within the function
704 * @itr_idx: ITR index of the interrupt cause
706 * Configure interrupt on Tx queue by associating Tx queue to MSI-X vector
707 * within the function space.
710 ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx)
712 struct ice_pf *pf = vsi->back;
713 struct ice_hw *hw = &pf->hw;
716 itr_idx = (itr_idx << QINT_TQCTL_ITR_INDX_S) & QINT_TQCTL_ITR_INDX_M;
718 val = QINT_TQCTL_CAUSE_ENA_M | itr_idx |
719 ((msix_idx << QINT_TQCTL_MSIX_INDX_S) & QINT_TQCTL_MSIX_INDX_M);
721 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val);
722 if (ice_is_xdp_ena_vsi(vsi)) {
723 u32 xdp_txq = txq + vsi->num_xdp_txq;
725 wr32(hw, QINT_TQCTL(vsi->txq_map[xdp_txq]),
732 * ice_cfg_rxq_interrupt - configure interrupt on Rx queue
733 * @vsi: the VSI being configured
734 * @rxq: Rx queue being mapped to MSI-X vector
735 * @msix_idx: MSI-X vector index within the function
736 * @itr_idx: ITR index of the interrupt cause
738 * Configure interrupt on Rx queue by associating Rx queue to MSI-X vector
739 * within the function space.
742 ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx)
744 struct ice_pf *pf = vsi->back;
745 struct ice_hw *hw = &pf->hw;
748 itr_idx = (itr_idx << QINT_RQCTL_ITR_INDX_S) & QINT_RQCTL_ITR_INDX_M;
750 val = QINT_RQCTL_CAUSE_ENA_M | itr_idx |
751 ((msix_idx << QINT_RQCTL_MSIX_INDX_S) & QINT_RQCTL_MSIX_INDX_M);
753 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val);
759 * ice_trigger_sw_intr - trigger a software interrupt
760 * @hw: pointer to the HW structure
761 * @q_vector: interrupt vector to trigger the software interrupt for
763 void ice_trigger_sw_intr(struct ice_hw *hw, struct ice_q_vector *q_vector)
765 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx),
766 (ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S) |
767 GLINT_DYN_CTL_SWINT_TRIG_M |
768 GLINT_DYN_CTL_INTENA_M);
772 * ice_vsi_stop_tx_ring - Disable single Tx ring
773 * @vsi: the VSI being configured
774 * @rst_src: reset source
775 * @rel_vmvf_num: Relative ID of VF/VM
776 * @ring: Tx ring to be stopped
777 * @txq_meta: Meta data of Tx ring to be stopped
780 ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,
781 u16 rel_vmvf_num, struct ice_ring *ring,
782 struct ice_txq_meta *txq_meta)
784 struct ice_pf *pf = vsi->back;
785 struct ice_q_vector *q_vector;
786 struct ice_hw *hw = &pf->hw;
787 enum ice_status status;
790 /* clear cause_ena bit for disabled queues */
791 val = rd32(hw, QINT_TQCTL(ring->reg_idx));
792 val &= ~QINT_TQCTL_CAUSE_ENA_M;
793 wr32(hw, QINT_TQCTL(ring->reg_idx), val);
795 /* software is expected to wait for 100 ns */
798 /* trigger a software interrupt for the vector
799 * associated to the queue to schedule NAPI handler
801 q_vector = ring->q_vector;
803 ice_trigger_sw_intr(hw, q_vector);
805 status = ice_dis_vsi_txq(vsi->port_info, txq_meta->vsi_idx,
806 txq_meta->tc, 1, &txq_meta->q_handle,
807 &txq_meta->q_id, &txq_meta->q_teid, rst_src,
810 /* if the disable queue command was exercised during an
811 * active reset flow, ICE_ERR_RESET_ONGOING is returned.
812 * This is not an error as the reset operation disables
813 * queues at the hardware level anyway.
815 if (status == ICE_ERR_RESET_ONGOING) {
816 dev_dbg(&vsi->back->pdev->dev,
817 "Reset in progress. LAN Tx queues already disabled\n");
818 } else if (status == ICE_ERR_DOES_NOT_EXIST) {
819 dev_dbg(&vsi->back->pdev->dev,
820 "LAN Tx queues do not exist, nothing to disable\n");
822 dev_err(&vsi->back->pdev->dev,
823 "Failed to disable LAN Tx queues, error: %d\n", status);
831 * ice_fill_txq_meta - Prepare the Tx queue's meta data
832 * @vsi: VSI that ring belongs to
833 * @ring: ring that txq_meta will be based on
834 * @txq_meta: a helper struct that wraps Tx queue's information
836 * Set up a helper struct that will contain all the necessary fields that
837 * are needed for stopping Tx queue
840 ice_fill_txq_meta(struct ice_vsi *vsi, struct ice_ring *ring,
841 struct ice_txq_meta *txq_meta)
845 if (IS_ENABLED(CONFIG_DCB))
850 txq_meta->q_id = ring->reg_idx;
851 txq_meta->q_teid = ring->txq_teid;
852 txq_meta->q_handle = ring->q_handle;
853 txq_meta->vsi_idx = vsi->idx;