1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019, Intel Corporation. */
5 #include "ice_dcb_lib.h"
8 * __ice_vsi_get_qs_contig - Assign a contiguous chunk of queues to VSI
9 * @qs_cfg: gathered variables needed for PF->VSI queues assignment
11 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap
13 static int __ice_vsi_get_qs_contig(struct ice_qs_cfg *qs_cfg)
17 mutex_lock(qs_cfg->qs_mutex);
18 offset = bitmap_find_next_zero_area(qs_cfg->pf_map, qs_cfg->pf_map_size,
19 0, qs_cfg->q_count, 0);
20 if (offset >= qs_cfg->pf_map_size) {
21 mutex_unlock(qs_cfg->qs_mutex);
25 bitmap_set(qs_cfg->pf_map, offset, qs_cfg->q_count);
26 for (i = 0; i < qs_cfg->q_count; i++)
27 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = i + offset;
28 mutex_unlock(qs_cfg->qs_mutex);
34 * __ice_vsi_get_qs_sc - Assign a scattered queues from PF to VSI
35 * @qs_cfg: gathered variables needed for pf->vsi queues assignment
37 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap
39 static int __ice_vsi_get_qs_sc(struct ice_qs_cfg *qs_cfg)
43 mutex_lock(qs_cfg->qs_mutex);
44 for (i = 0; i < qs_cfg->q_count; i++) {
45 index = find_next_zero_bit(qs_cfg->pf_map,
46 qs_cfg->pf_map_size, index);
47 if (index >= qs_cfg->pf_map_size)
49 set_bit(index, qs_cfg->pf_map);
50 qs_cfg->vsi_map[i + qs_cfg->vsi_map_offset] = index;
52 mutex_unlock(qs_cfg->qs_mutex);
56 for (index = 0; index < i; index++) {
57 clear_bit(qs_cfg->vsi_map[index], qs_cfg->pf_map);
58 qs_cfg->vsi_map[index + qs_cfg->vsi_map_offset] = 0;
60 mutex_unlock(qs_cfg->qs_mutex);
66 * ice_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
67 * @pf: the PF being configured
69 * @ena: enable or disable state of the queue
71 * This routine will wait for the given Rx queue of the PF to reach the
72 * enabled or disabled state.
73 * Returns -ETIMEDOUT in case of failing to reach the requested state after
74 * multiple retries; else will return 0 in case of success.
76 static int ice_pf_rxq_wait(struct ice_pf *pf, int pf_q, bool ena)
80 for (i = 0; i < ICE_Q_WAIT_MAX_RETRY; i++) {
81 if (ena == !!(rd32(&pf->hw, QRX_CTRL(pf_q)) &
82 QRX_CTRL_QENA_STAT_M))
92 * ice_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
93 * @vsi: the VSI being configured
94 * @v_idx: index of the vector in the VSI struct
96 * We allocate one q_vector. If allocation fails we return -ENOMEM.
98 static int ice_vsi_alloc_q_vector(struct ice_vsi *vsi, int v_idx)
100 struct ice_pf *pf = vsi->back;
101 struct ice_q_vector *q_vector;
103 /* allocate q_vector */
104 q_vector = devm_kzalloc(ice_pf_to_dev(pf), sizeof(*q_vector),
110 q_vector->v_idx = v_idx;
111 if (vsi->type == ICE_VSI_VF)
113 /* only set affinity_mask if the CPU is online */
114 if (cpu_online(v_idx))
115 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
117 /* This will not be called in the driver load path because the netdev
118 * will not be created yet. All other cases with register the NAPI
119 * handler here (i.e. resume, reset/rebuild, etc.)
122 netif_napi_add(vsi->netdev, &q_vector->napi, ice_napi_poll,
126 /* tie q_vector and VSI together */
127 vsi->q_vectors[v_idx] = q_vector;
133 * ice_free_q_vector - Free memory allocated for a specific interrupt vector
134 * @vsi: VSI having the memory freed
135 * @v_idx: index of the vector to be freed
137 static void ice_free_q_vector(struct ice_vsi *vsi, int v_idx)
139 struct ice_q_vector *q_vector;
140 struct ice_pf *pf = vsi->back;
141 struct ice_ring *ring;
144 dev = ice_pf_to_dev(pf);
145 if (!vsi->q_vectors[v_idx]) {
146 dev_dbg(dev, "Queue vector at index %d not found\n", v_idx);
149 q_vector = vsi->q_vectors[v_idx];
151 ice_for_each_ring(ring, q_vector->tx)
152 ring->q_vector = NULL;
153 ice_for_each_ring(ring, q_vector->rx)
154 ring->q_vector = NULL;
156 /* only VSI with an associated netdev is set up with NAPI */
158 netif_napi_del(&q_vector->napi);
160 devm_kfree(dev, q_vector);
161 vsi->q_vectors[v_idx] = NULL;
165 * ice_cfg_itr_gran - set the ITR granularity to 2 usecs if not already set
166 * @hw: board specific structure
168 static void ice_cfg_itr_gran(struct ice_hw *hw)
170 u32 regval = rd32(hw, GLINT_CTL);
172 /* no need to update global register if ITR gran is already set */
173 if (!(regval & GLINT_CTL_DIS_AUTOMASK_M) &&
174 (((regval & GLINT_CTL_ITR_GRAN_200_M) >>
175 GLINT_CTL_ITR_GRAN_200_S) == ICE_ITR_GRAN_US) &&
176 (((regval & GLINT_CTL_ITR_GRAN_100_M) >>
177 GLINT_CTL_ITR_GRAN_100_S) == ICE_ITR_GRAN_US) &&
178 (((regval & GLINT_CTL_ITR_GRAN_50_M) >>
179 GLINT_CTL_ITR_GRAN_50_S) == ICE_ITR_GRAN_US) &&
180 (((regval & GLINT_CTL_ITR_GRAN_25_M) >>
181 GLINT_CTL_ITR_GRAN_25_S) == ICE_ITR_GRAN_US))
184 regval = ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_200_S) &
185 GLINT_CTL_ITR_GRAN_200_M) |
186 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_100_S) &
187 GLINT_CTL_ITR_GRAN_100_M) |
188 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_50_S) &
189 GLINT_CTL_ITR_GRAN_50_M) |
190 ((ICE_ITR_GRAN_US << GLINT_CTL_ITR_GRAN_25_S) &
191 GLINT_CTL_ITR_GRAN_25_M);
192 wr32(hw, GLINT_CTL, regval);
196 * ice_calc_q_handle - calculate the queue handle
197 * @vsi: VSI that ring belongs to
198 * @ring: ring to get the absolute queue index
199 * @tc: traffic class number
201 static u16 ice_calc_q_handle(struct ice_vsi *vsi, struct ice_ring *ring, u8 tc)
203 WARN_ONCE(ice_ring_is_xdp(ring) && tc,
204 "XDP ring can't belong to TC other than 0");
206 /* Idea here for calculation is that we subtract the number of queue
207 * count from TC that ring belongs to from it's absolute queue index
208 * and as a result we get the queue's index within TC.
210 return ring->q_index - vsi->tc_cfg.tc_info[tc].qoffset;
214 * ice_setup_tx_ctx - setup a struct ice_tlan_ctx instance
215 * @ring: The Tx ring to configure
216 * @tlan_ctx: Pointer to the Tx LAN queue context structure to be initialized
217 * @pf_q: queue index in the PF space
219 * Configure the Tx descriptor ring in TLAN context.
222 ice_setup_tx_ctx(struct ice_ring *ring, struct ice_tlan_ctx *tlan_ctx, u16 pf_q)
224 struct ice_vsi *vsi = ring->vsi;
225 struct ice_hw *hw = &vsi->back->hw;
227 tlan_ctx->base = ring->dma >> ICE_TLAN_CTX_BASE_S;
229 tlan_ctx->port_num = vsi->port_info->lport;
231 /* Transmit Queue Length */
232 tlan_ctx->qlen = ring->count;
234 ice_set_cgd_num(tlan_ctx, ring);
237 tlan_ctx->pf_num = hw->pf_id;
239 /* queue belongs to a specific VSI type
240 * VF / VM index should be programmed per vmvf_type setting:
241 * for vmvf_type = VF, it is VF number between 0-256
242 * for vmvf_type = VM, it is VM number between 0-767
243 * for PF or EMP this field should be set to zero
249 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
252 /* Firmware expects vmvf_num to be absolute VF ID */
253 tlan_ctx->vmvf_num = hw->func_caps.vf_base_id + vsi->vf_id;
254 tlan_ctx->vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_VF;
260 /* make sure the context is associated with the right VSI */
261 tlan_ctx->src_vsi = ice_get_hw_vsi_num(hw, vsi->idx);
263 tlan_ctx->tso_ena = ICE_TX_LEGACY;
264 tlan_ctx->tso_qnum = pf_q;
266 /* Legacy or Advanced Host Interface:
267 * 0: Advanced Host Interface
268 * 1: Legacy Host Interface
270 tlan_ctx->legacy_int = ICE_TX_LEGACY;
274 * ice_setup_rx_ctx - Configure a receive ring context
275 * @ring: The Rx ring to configure
277 * Configure the Rx descriptor ring in RLAN context.
279 int ice_setup_rx_ctx(struct ice_ring *ring)
281 int chain_len = ICE_MAX_CHAINED_RX_BUFS;
282 struct ice_vsi *vsi = ring->vsi;
283 u32 rxdid = ICE_RXDID_FLEX_NIC;
284 struct ice_rlan_ctx rlan_ctx;
292 /* what is Rx queue number in global space of 2K Rx queues */
293 pf_q = vsi->rxq_map[ring->q_index];
295 /* clear the context structure first */
296 memset(&rlan_ctx, 0, sizeof(rlan_ctx));
298 ring->rx_buf_len = vsi->rx_buf_len;
300 if (ring->vsi->type == ICE_VSI_PF) {
301 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq))
302 xdp_rxq_info_reg(&ring->xdp_rxq, ring->netdev,
305 ring->xsk_umem = ice_xsk_umem(ring);
306 if (ring->xsk_umem) {
307 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
309 ring->rx_buf_len = ring->xsk_umem->chunk_size_nohr -
311 /* For AF_XDP ZC, we disallow packets to span on
312 * multiple buffers, thus letting us skip that
313 * handling in the fast-path.
316 ring->zca.free = ice_zca_free;
317 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
323 dev_info(&vsi->back->pdev->dev, "Registered XDP mem model MEM_TYPE_ZERO_COPY on Rx ring %d\n",
326 if (!xdp_rxq_info_is_reg(&ring->xdp_rxq))
327 xdp_rxq_info_reg(&ring->xdp_rxq,
331 err = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
332 MEM_TYPE_PAGE_SHARED,
338 /* Receive Queue Base Address.
339 * Indicates the starting address of the descriptor queue defined in
342 rlan_ctx.base = ring->dma >> 7;
344 rlan_ctx.qlen = ring->count;
346 /* Receive Packet Data Buffer Size.
347 * The Packet Data Buffer Size is defined in 128 byte units.
349 rlan_ctx.dbuf = ring->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
351 /* use 32 byte descriptors */
354 /* Strip the Ethernet CRC bytes before the packet is posted to host
357 rlan_ctx.crcstrip = 1;
359 /* L2TSEL flag defines the reported L2 Tags in the receive descriptor */
362 rlan_ctx.dtype = ICE_RX_DTYPE_NO_SPLIT;
363 rlan_ctx.hsplit_0 = ICE_RLAN_RX_HSPLIT_0_NO_SPLIT;
364 rlan_ctx.hsplit_1 = ICE_RLAN_RX_HSPLIT_1_NO_SPLIT;
366 /* This controls whether VLAN is stripped from inner headers
367 * The VLAN in the inner L2 header is stripped to the receive
368 * descriptor if enabled by this flag.
372 /* Max packet size for this queue - must not be set to a larger value
375 rlan_ctx.rxmax = min_t(u16, vsi->max_frame,
376 chain_len * ring->rx_buf_len);
378 /* Rx queue threshold in units of 64 */
379 rlan_ctx.lrxqthresh = 1;
381 /* Enable Flexible Descriptors in the queue context which
382 * allows this driver to select a specific receive descriptor format
384 if (vsi->type != ICE_VSI_VF) {
385 regval = rd32(hw, QRXFLXP_CNTXT(pf_q));
386 regval |= (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
387 QRXFLXP_CNTXT_RXDID_IDX_M;
389 /* increasing context priority to pick up profile ID;
390 * default is 0x01; setting to 0x03 to ensure profile
391 * is programming if prev context is of same priority
393 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
394 QRXFLXP_CNTXT_RXDID_PRIO_M;
396 wr32(hw, QRXFLXP_CNTXT(pf_q), regval);
399 /* Absolute queue number out of 2K needs to be passed */
400 err = ice_write_rxq_ctx(hw, &rlan_ctx, pf_q);
402 dev_err(&vsi->back->pdev->dev,
403 "Failed to set LAN Rx queue context for absolute Rx queue %d error: %d\n",
408 if (vsi->type == ICE_VSI_VF)
411 /* configure Rx buffer alignment */
412 if (!vsi->netdev || test_bit(ICE_FLAG_LEGACY_RX, vsi->back->flags))
413 ice_clear_ring_build_skb_ena(ring);
415 ice_set_ring_build_skb_ena(ring);
417 /* init queue specific tail register */
418 ring->tail = hw->hw_addr + QRX_TAIL(pf_q);
419 writel(0, ring->tail);
421 err = ring->xsk_umem ?
422 ice_alloc_rx_bufs_slow_zc(ring, ICE_DESC_UNUSED(ring)) :
423 ice_alloc_rx_bufs(ring, ICE_DESC_UNUSED(ring));
425 dev_info(&vsi->back->pdev->dev,
426 "Failed allocate some buffers on %sRx ring %d (pf_q %d)\n",
427 ring->xsk_umem ? "UMEM enabled " : "",
428 ring->q_index, pf_q);
434 * __ice_vsi_get_qs - helper function for assigning queues from PF to VSI
435 * @qs_cfg: gathered variables needed for pf->vsi queues assignment
437 * This function first tries to find contiguous space. If it is not successful,
438 * it tries with the scatter approach.
440 * Return 0 on success and -ENOMEM in case of no left space in PF queue bitmap
442 int __ice_vsi_get_qs(struct ice_qs_cfg *qs_cfg)
446 ret = __ice_vsi_get_qs_contig(qs_cfg);
448 /* contig failed, so try with scatter approach */
449 qs_cfg->mapping_mode = ICE_VSI_MAP_SCATTER;
450 qs_cfg->q_count = min_t(u16, qs_cfg->q_count,
451 qs_cfg->scatter_count);
452 ret = __ice_vsi_get_qs_sc(qs_cfg);
458 * ice_vsi_ctrl_rx_ring - Start or stop a VSI's Rx ring
459 * @vsi: the VSI being configured
460 * @ena: start or stop the Rx rings
461 * @rxq_idx: Rx queue index
463 int ice_vsi_ctrl_rx_ring(struct ice_vsi *vsi, bool ena, u16 rxq_idx)
465 int pf_q = vsi->rxq_map[rxq_idx];
466 struct ice_pf *pf = vsi->back;
467 struct ice_hw *hw = &pf->hw;
471 rx_reg = rd32(hw, QRX_CTRL(pf_q));
473 /* Skip if the queue is already in the requested state */
474 if (ena == !!(rx_reg & QRX_CTRL_QENA_STAT_M))
477 /* turn on/off the queue */
479 rx_reg |= QRX_CTRL_QENA_REQ_M;
481 rx_reg &= ~QRX_CTRL_QENA_REQ_M;
482 wr32(hw, QRX_CTRL(pf_q), rx_reg);
484 /* wait for the change to finish */
485 ret = ice_pf_rxq_wait(pf, pf_q, ena);
487 dev_err(ice_pf_to_dev(pf),
488 "VSI idx %d Rx ring %d %sable timeout\n",
489 vsi->idx, pf_q, (ena ? "en" : "dis"));
495 * ice_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
496 * @vsi: the VSI being configured
498 * We allocate one q_vector per queue interrupt. If allocation fails we
501 int ice_vsi_alloc_q_vectors(struct ice_vsi *vsi)
503 struct ice_pf *pf = vsi->back;
504 int v_idx = 0, num_q_vectors;
508 dev = ice_pf_to_dev(pf);
509 if (vsi->q_vectors[0]) {
510 dev_dbg(dev, "VSI %d has existing q_vectors\n", vsi->vsi_num);
514 num_q_vectors = vsi->num_q_vectors;
516 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
517 err = ice_vsi_alloc_q_vector(vsi, v_idx);
526 ice_free_q_vector(vsi, v_idx);
528 dev_err(dev, "Failed to allocate %d q_vector for VSI %d, ret=%d\n",
529 vsi->num_q_vectors, vsi->vsi_num, err);
530 vsi->num_q_vectors = 0;
535 * ice_vsi_map_rings_to_vectors - Map VSI rings to interrupt vectors
536 * @vsi: the VSI being configured
538 * This function maps descriptor rings to the queue-specific vectors allotted
539 * through the MSI-X enabling code. On a constrained vector budget, we map Tx
540 * and Rx rings to the vector as "efficiently" as possible.
542 void ice_vsi_map_rings_to_vectors(struct ice_vsi *vsi)
544 int q_vectors = vsi->num_q_vectors;
545 int tx_rings_rem, rx_rings_rem;
548 /* initially assigning remaining rings count to VSIs num queue value */
549 tx_rings_rem = vsi->num_txq;
550 rx_rings_rem = vsi->num_rxq;
552 for (v_id = 0; v_id < q_vectors; v_id++) {
553 struct ice_q_vector *q_vector = vsi->q_vectors[v_id];
554 int tx_rings_per_v, rx_rings_per_v, q_id, q_base;
556 /* Tx rings mapping to vector */
557 tx_rings_per_v = DIV_ROUND_UP(tx_rings_rem, q_vectors - v_id);
558 q_vector->num_ring_tx = tx_rings_per_v;
559 q_vector->tx.ring = NULL;
560 q_vector->tx.itr_idx = ICE_TX_ITR;
561 q_base = vsi->num_txq - tx_rings_rem;
563 for (q_id = q_base; q_id < (q_base + tx_rings_per_v); q_id++) {
564 struct ice_ring *tx_ring = vsi->tx_rings[q_id];
566 tx_ring->q_vector = q_vector;
567 tx_ring->next = q_vector->tx.ring;
568 q_vector->tx.ring = tx_ring;
570 tx_rings_rem -= tx_rings_per_v;
572 /* Rx rings mapping to vector */
573 rx_rings_per_v = DIV_ROUND_UP(rx_rings_rem, q_vectors - v_id);
574 q_vector->num_ring_rx = rx_rings_per_v;
575 q_vector->rx.ring = NULL;
576 q_vector->rx.itr_idx = ICE_RX_ITR;
577 q_base = vsi->num_rxq - rx_rings_rem;
579 for (q_id = q_base; q_id < (q_base + rx_rings_per_v); q_id++) {
580 struct ice_ring *rx_ring = vsi->rx_rings[q_id];
582 rx_ring->q_vector = q_vector;
583 rx_ring->next = q_vector->rx.ring;
584 q_vector->rx.ring = rx_ring;
586 rx_rings_rem -= rx_rings_per_v;
591 * ice_vsi_free_q_vectors - Free memory allocated for interrupt vectors
592 * @vsi: the VSI having memory freed
594 void ice_vsi_free_q_vectors(struct ice_vsi *vsi)
598 ice_for_each_q_vector(vsi, v_idx)
599 ice_free_q_vector(vsi, v_idx);
603 * ice_vsi_cfg_txq - Configure single Tx queue
604 * @vsi: the VSI that queue belongs to
605 * @ring: Tx ring to be configured
606 * @qg_buf: queue group buffer
609 ice_vsi_cfg_txq(struct ice_vsi *vsi, struct ice_ring *ring,
610 struct ice_aqc_add_tx_qgrp *qg_buf)
612 struct ice_tlan_ctx tlan_ctx = { 0 };
613 struct ice_aqc_add_txqs_perq *txq;
614 struct ice_pf *pf = vsi->back;
615 u8 buf_len = sizeof(*qg_buf);
616 enum ice_status status;
620 pf_q = ring->reg_idx;
621 ice_setup_tx_ctx(ring, &tlan_ctx, pf_q);
622 /* copy context contents into the qg_buf */
623 qg_buf->txqs[0].txq_id = cpu_to_le16(pf_q);
624 ice_set_ctx((u8 *)&tlan_ctx, qg_buf->txqs[0].txq_ctx,
627 /* init queue specific tail reg. It is referred as
628 * transmit comm scheduler queue doorbell.
630 ring->tail = pf->hw.hw_addr + QTX_COMM_DBELL(pf_q);
632 if (IS_ENABLED(CONFIG_DCB))
637 /* Add unique software queue handle of the Tx queue per
638 * TC into the VSI Tx ring
640 ring->q_handle = ice_calc_q_handle(vsi, ring, tc);
642 status = ice_ena_vsi_txq(vsi->port_info, vsi->idx, tc, ring->q_handle,
643 1, qg_buf, buf_len, NULL);
645 dev_err(ice_pf_to_dev(pf),
646 "Failed to set LAN Tx queue context, error: %d\n",
651 /* Add Tx Queue TEID into the VSI Tx ring from the
652 * response. This will complete configuring and
653 * enabling the queue.
655 txq = &qg_buf->txqs[0];
656 if (pf_q == le16_to_cpu(txq->txq_id))
657 ring->txq_teid = le32_to_cpu(txq->q_teid);
663 * ice_cfg_itr - configure the initial interrupt throttle values
664 * @hw: pointer to the HW structure
665 * @q_vector: interrupt vector that's being configured
667 * Configure interrupt throttling values for the ring containers that are
668 * associated with the interrupt vector passed in.
670 void ice_cfg_itr(struct ice_hw *hw, struct ice_q_vector *q_vector)
672 ice_cfg_itr_gran(hw);
674 if (q_vector->num_ring_rx) {
675 struct ice_ring_container *rc = &q_vector->rx;
677 /* if this value is set then don't overwrite with default */
678 if (!rc->itr_setting)
679 rc->itr_setting = ICE_DFLT_RX_ITR;
681 rc->target_itr = ITR_TO_REG(rc->itr_setting);
682 rc->next_update = jiffies + 1;
683 rc->current_itr = rc->target_itr;
684 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx),
685 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S);
688 if (q_vector->num_ring_tx) {
689 struct ice_ring_container *rc = &q_vector->tx;
691 /* if this value is set then don't overwrite with default */
692 if (!rc->itr_setting)
693 rc->itr_setting = ICE_DFLT_TX_ITR;
695 rc->target_itr = ITR_TO_REG(rc->itr_setting);
696 rc->next_update = jiffies + 1;
697 rc->current_itr = rc->target_itr;
698 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx),
699 ITR_REG_ALIGN(rc->current_itr) >> ICE_ITR_GRAN_S);
704 * ice_cfg_txq_interrupt - configure interrupt on Tx queue
705 * @vsi: the VSI being configured
706 * @txq: Tx queue being mapped to MSI-X vector
707 * @msix_idx: MSI-X vector index within the function
708 * @itr_idx: ITR index of the interrupt cause
710 * Configure interrupt on Tx queue by associating Tx queue to MSI-X vector
711 * within the function space.
714 ice_cfg_txq_interrupt(struct ice_vsi *vsi, u16 txq, u16 msix_idx, u16 itr_idx)
716 struct ice_pf *pf = vsi->back;
717 struct ice_hw *hw = &pf->hw;
720 itr_idx = (itr_idx << QINT_TQCTL_ITR_INDX_S) & QINT_TQCTL_ITR_INDX_M;
722 val = QINT_TQCTL_CAUSE_ENA_M | itr_idx |
723 ((msix_idx << QINT_TQCTL_MSIX_INDX_S) & QINT_TQCTL_MSIX_INDX_M);
725 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), val);
726 if (ice_is_xdp_ena_vsi(vsi)) {
727 u32 xdp_txq = txq + vsi->num_xdp_txq;
729 wr32(hw, QINT_TQCTL(vsi->txq_map[xdp_txq]),
736 * ice_cfg_rxq_interrupt - configure interrupt on Rx queue
737 * @vsi: the VSI being configured
738 * @rxq: Rx queue being mapped to MSI-X vector
739 * @msix_idx: MSI-X vector index within the function
740 * @itr_idx: ITR index of the interrupt cause
742 * Configure interrupt on Rx queue by associating Rx queue to MSI-X vector
743 * within the function space.
746 ice_cfg_rxq_interrupt(struct ice_vsi *vsi, u16 rxq, u16 msix_idx, u16 itr_idx)
748 struct ice_pf *pf = vsi->back;
749 struct ice_hw *hw = &pf->hw;
752 itr_idx = (itr_idx << QINT_RQCTL_ITR_INDX_S) & QINT_RQCTL_ITR_INDX_M;
754 val = QINT_RQCTL_CAUSE_ENA_M | itr_idx |
755 ((msix_idx << QINT_RQCTL_MSIX_INDX_S) & QINT_RQCTL_MSIX_INDX_M);
757 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), val);
763 * ice_trigger_sw_intr - trigger a software interrupt
764 * @hw: pointer to the HW structure
765 * @q_vector: interrupt vector to trigger the software interrupt for
767 void ice_trigger_sw_intr(struct ice_hw *hw, struct ice_q_vector *q_vector)
769 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx),
770 (ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S) |
771 GLINT_DYN_CTL_SWINT_TRIG_M |
772 GLINT_DYN_CTL_INTENA_M);
776 * ice_vsi_stop_tx_ring - Disable single Tx ring
777 * @vsi: the VSI being configured
778 * @rst_src: reset source
779 * @rel_vmvf_num: Relative ID of VF/VM
780 * @ring: Tx ring to be stopped
781 * @txq_meta: Meta data of Tx ring to be stopped
784 ice_vsi_stop_tx_ring(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,
785 u16 rel_vmvf_num, struct ice_ring *ring,
786 struct ice_txq_meta *txq_meta)
788 struct ice_pf *pf = vsi->back;
789 struct ice_q_vector *q_vector;
790 struct ice_hw *hw = &pf->hw;
791 enum ice_status status;
794 /* clear cause_ena bit for disabled queues */
795 val = rd32(hw, QINT_TQCTL(ring->reg_idx));
796 val &= ~QINT_TQCTL_CAUSE_ENA_M;
797 wr32(hw, QINT_TQCTL(ring->reg_idx), val);
799 /* software is expected to wait for 100 ns */
802 /* trigger a software interrupt for the vector
803 * associated to the queue to schedule NAPI handler
805 q_vector = ring->q_vector;
807 ice_trigger_sw_intr(hw, q_vector);
809 status = ice_dis_vsi_txq(vsi->port_info, txq_meta->vsi_idx,
810 txq_meta->tc, 1, &txq_meta->q_handle,
811 &txq_meta->q_id, &txq_meta->q_teid, rst_src,
814 /* if the disable queue command was exercised during an
815 * active reset flow, ICE_ERR_RESET_ONGOING is returned.
816 * This is not an error as the reset operation disables
817 * queues at the hardware level anyway.
819 if (status == ICE_ERR_RESET_ONGOING) {
820 dev_dbg(&vsi->back->pdev->dev,
821 "Reset in progress. LAN Tx queues already disabled\n");
822 } else if (status == ICE_ERR_DOES_NOT_EXIST) {
823 dev_dbg(&vsi->back->pdev->dev,
824 "LAN Tx queues do not exist, nothing to disable\n");
826 dev_err(&vsi->back->pdev->dev,
827 "Failed to disable LAN Tx queues, error: %d\n", status);
835 * ice_fill_txq_meta - Prepare the Tx queue's meta data
836 * @vsi: VSI that ring belongs to
837 * @ring: ring that txq_meta will be based on
838 * @txq_meta: a helper struct that wraps Tx queue's information
840 * Set up a helper struct that will contain all the necessary fields that
841 * are needed for stopping Tx queue
844 ice_fill_txq_meta(struct ice_vsi *vsi, struct ice_ring *ring,
845 struct ice_txq_meta *txq_meta)
849 if (IS_ENABLED(CONFIG_DCB))
854 txq_meta->q_id = ring->reg_idx;
855 txq_meta->q_teid = ring->txq_teid;
856 txq_meta->q_handle = ring->q_handle;
857 txq_meta->vsi_idx = vsi->idx;