1 // SPDX-License-Identifier: GPL-2.0
2 /* Intel(R) Gigabit Ethernet Linux driver
3 * Copyright(c) 2007-2014 Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 #include <linux/if_ether.h>
25 #include <linux/delay.h>
27 #include "e1000_mac.h"
28 #include "e1000_nvm.h"
31 * igb_raise_eec_clk - Raise EEPROM clock
32 * @hw: pointer to the HW structure
33 * @eecd: pointer to the EEPROM
35 * Enable/Raise the EEPROM clock bit.
37 static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
39 *eecd = *eecd | E1000_EECD_SK;
40 wr32(E1000_EECD, *eecd);
42 udelay(hw->nvm.delay_usec);
46 * igb_lower_eec_clk - Lower EEPROM clock
47 * @hw: pointer to the HW structure
48 * @eecd: pointer to the EEPROM
50 * Clear/Lower the EEPROM clock bit.
52 static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
54 *eecd = *eecd & ~E1000_EECD_SK;
55 wr32(E1000_EECD, *eecd);
57 udelay(hw->nvm.delay_usec);
61 * igb_shift_out_eec_bits - Shift data bits our to the EEPROM
62 * @hw: pointer to the HW structure
63 * @data: data to send to the EEPROM
64 * @count: number of bits to shift out
66 * We need to shift 'count' bits out to the EEPROM. So, the value in the
67 * "data" parameter will be shifted out to the EEPROM one bit at a time.
68 * In order to do this, "data" must be broken down into bits.
70 static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
72 struct e1000_nvm_info *nvm = &hw->nvm;
73 u32 eecd = rd32(E1000_EECD);
76 mask = 1u << (count - 1);
77 if (nvm->type == e1000_nvm_eeprom_spi)
78 eecd |= E1000_EECD_DO;
81 eecd &= ~E1000_EECD_DI;
84 eecd |= E1000_EECD_DI;
86 wr32(E1000_EECD, eecd);
89 udelay(nvm->delay_usec);
91 igb_raise_eec_clk(hw, &eecd);
92 igb_lower_eec_clk(hw, &eecd);
97 eecd &= ~E1000_EECD_DI;
98 wr32(E1000_EECD, eecd);
102 * igb_shift_in_eec_bits - Shift data bits in from the EEPROM
103 * @hw: pointer to the HW structure
104 * @count: number of bits to shift in
106 * In order to read a register from the EEPROM, we need to shift 'count' bits
107 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
108 * the EEPROM (setting the SK bit), and then reading the value of the data out
109 * "DO" bit. During this "shifting in" process the data in "DI" bit should
112 static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
118 eecd = rd32(E1000_EECD);
120 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
123 for (i = 0; i < count; i++) {
125 igb_raise_eec_clk(hw, &eecd);
127 eecd = rd32(E1000_EECD);
129 eecd &= ~E1000_EECD_DI;
130 if (eecd & E1000_EECD_DO)
133 igb_lower_eec_clk(hw, &eecd);
140 * igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion
141 * @hw: pointer to the HW structure
142 * @ee_reg: EEPROM flag for polling
144 * Polls the EEPROM status bit for either read or write completion based
145 * upon the value of 'ee_reg'.
147 static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
149 u32 attempts = 100000;
151 s32 ret_val = -E1000_ERR_NVM;
153 for (i = 0; i < attempts; i++) {
154 if (ee_reg == E1000_NVM_POLL_READ)
155 reg = rd32(E1000_EERD);
157 reg = rd32(E1000_EEWR);
159 if (reg & E1000_NVM_RW_REG_DONE) {
171 * igb_acquire_nvm - Generic request for access to EEPROM
172 * @hw: pointer to the HW structure
174 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
175 * Return successful if access grant bit set, else clear the request for
176 * EEPROM access and return -E1000_ERR_NVM (-1).
178 s32 igb_acquire_nvm(struct e1000_hw *hw)
180 u32 eecd = rd32(E1000_EECD);
181 s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
185 wr32(E1000_EECD, eecd | E1000_EECD_REQ);
186 eecd = rd32(E1000_EECD);
189 if (eecd & E1000_EECD_GNT)
192 eecd = rd32(E1000_EECD);
197 eecd &= ~E1000_EECD_REQ;
198 wr32(E1000_EECD, eecd);
199 hw_dbg("Could not acquire NVM grant\n");
200 ret_val = -E1000_ERR_NVM;
207 * igb_standby_nvm - Return EEPROM to standby state
208 * @hw: pointer to the HW structure
210 * Return the EEPROM to a standby state.
212 static void igb_standby_nvm(struct e1000_hw *hw)
214 struct e1000_nvm_info *nvm = &hw->nvm;
215 u32 eecd = rd32(E1000_EECD);
217 if (nvm->type == e1000_nvm_eeprom_spi) {
218 /* Toggle CS to flush commands */
219 eecd |= E1000_EECD_CS;
220 wr32(E1000_EECD, eecd);
222 udelay(nvm->delay_usec);
223 eecd &= ~E1000_EECD_CS;
224 wr32(E1000_EECD, eecd);
226 udelay(nvm->delay_usec);
231 * e1000_stop_nvm - Terminate EEPROM command
232 * @hw: pointer to the HW structure
234 * Terminates the current command by inverting the EEPROM's chip select pin.
236 static void e1000_stop_nvm(struct e1000_hw *hw)
240 eecd = rd32(E1000_EECD);
241 if (hw->nvm.type == e1000_nvm_eeprom_spi) {
243 eecd |= E1000_EECD_CS;
244 igb_lower_eec_clk(hw, &eecd);
249 * igb_release_nvm - Release exclusive access to EEPROM
250 * @hw: pointer to the HW structure
252 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
254 void igb_release_nvm(struct e1000_hw *hw)
260 eecd = rd32(E1000_EECD);
261 eecd &= ~E1000_EECD_REQ;
262 wr32(E1000_EECD, eecd);
266 * igb_ready_nvm_eeprom - Prepares EEPROM for read/write
267 * @hw: pointer to the HW structure
269 * Setups the EEPROM for reading and writing.
271 static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
273 struct e1000_nvm_info *nvm = &hw->nvm;
274 u32 eecd = rd32(E1000_EECD);
280 if (nvm->type == e1000_nvm_eeprom_spi) {
281 /* Clear SK and CS */
282 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
283 wr32(E1000_EECD, eecd);
286 timeout = NVM_MAX_RETRY_SPI;
288 /* Read "Status Register" repeatedly until the LSB is cleared.
289 * The EEPROM will signal that the command has been completed
290 * by clearing bit 0 of the internal status register. If it's
291 * not cleared within 'timeout', then error out.
294 igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
295 hw->nvm.opcode_bits);
296 spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8);
297 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
306 hw_dbg("SPI NVM Status error\n");
307 ret_val = -E1000_ERR_NVM;
317 * igb_read_nvm_spi - Read EEPROM's using SPI
318 * @hw: pointer to the HW structure
319 * @offset: offset of word in the EEPROM to read
320 * @words: number of words to read
321 * @data: word read from the EEPROM
323 * Reads a 16 bit word from the EEPROM.
325 s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
327 struct e1000_nvm_info *nvm = &hw->nvm;
331 u8 read_opcode = NVM_READ_OPCODE_SPI;
333 /* A check for invalid values: offset too large, too many words,
334 * and not enough words.
336 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
338 hw_dbg("nvm parameter(s) out of bounds\n");
339 ret_val = -E1000_ERR_NVM;
343 ret_val = nvm->ops.acquire(hw);
347 ret_val = igb_ready_nvm_eeprom(hw);
353 if ((nvm->address_bits == 8) && (offset >= 128))
354 read_opcode |= NVM_A8_OPCODE_SPI;
356 /* Send the READ command (opcode + addr) */
357 igb_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
358 igb_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
360 /* Read the data. SPI NVMs increment the address with each byte
361 * read and will roll over if reading beyond the end. This allows
362 * us to read the whole NVM from any offset
364 for (i = 0; i < words; i++) {
365 word_in = igb_shift_in_eec_bits(hw, 16);
366 data[i] = (word_in >> 8) | (word_in << 8);
370 nvm->ops.release(hw);
377 * igb_read_nvm_eerd - Reads EEPROM using EERD register
378 * @hw: pointer to the HW structure
379 * @offset: offset of word in the EEPROM to read
380 * @words: number of words to read
381 * @data: word read from the EEPROM
383 * Reads a 16 bit word from the EEPROM using the EERD register.
385 s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
387 struct e1000_nvm_info *nvm = &hw->nvm;
391 /* A check for invalid values: offset too large, too many words,
392 * and not enough words.
394 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
396 hw_dbg("nvm parameter(s) out of bounds\n");
397 ret_val = -E1000_ERR_NVM;
401 for (i = 0; i < words; i++) {
402 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
403 E1000_NVM_RW_REG_START;
405 wr32(E1000_EERD, eerd);
406 ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
410 data[i] = (rd32(E1000_EERD) >>
411 E1000_NVM_RW_REG_DATA);
419 * igb_write_nvm_spi - Write to EEPROM using SPI
420 * @hw: pointer to the HW structure
421 * @offset: offset within the EEPROM to be written to
422 * @words: number of words to write
423 * @data: 16 bit word(s) to be written to the EEPROM
425 * Writes data to EEPROM at offset using SPI interface.
427 * If e1000_update_nvm_checksum is not called after this function , the
428 * EEPROM will most likley contain an invalid checksum.
430 s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
432 struct e1000_nvm_info *nvm = &hw->nvm;
433 s32 ret_val = -E1000_ERR_NVM;
436 /* A check for invalid values: offset too large, too many words,
437 * and not enough words.
439 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
441 hw_dbg("nvm parameter(s) out of bounds\n");
445 while (widx < words) {
446 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
448 ret_val = nvm->ops.acquire(hw);
452 ret_val = igb_ready_nvm_eeprom(hw);
454 nvm->ops.release(hw);
460 /* Send the WRITE ENABLE command (8 bit opcode) */
461 igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
466 /* Some SPI eeproms use the 8th address bit embedded in the
469 if ((nvm->address_bits == 8) && (offset >= 128))
470 write_opcode |= NVM_A8_OPCODE_SPI;
472 /* Send the Write command (8-bit opcode + addr) */
473 igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
474 igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
477 /* Loop to allow for up to whole page write of eeprom */
478 while (widx < words) {
479 u16 word_out = data[widx];
481 word_out = (word_out >> 8) | (word_out << 8);
482 igb_shift_out_eec_bits(hw, word_out, 16);
485 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
490 usleep_range(1000, 2000);
491 nvm->ops.release(hw);
498 * igb_read_part_string - Read device part number
499 * @hw: pointer to the HW structure
500 * @part_num: pointer to device part number
501 * @part_num_size: size of part number buffer
503 * Reads the product board assembly (PBA) number from the EEPROM and stores
504 * the value in part_num.
506 s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num, u32 part_num_size)
514 if (part_num == NULL) {
515 hw_dbg("PBA string buffer was null\n");
516 ret_val = E1000_ERR_INVALID_ARGUMENT;
520 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
522 hw_dbg("NVM Read Error\n");
526 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pointer);
528 hw_dbg("NVM Read Error\n");
532 /* if nvm_data is not ptr guard the PBA must be in legacy format which
533 * means pointer is actually our second data word for the PBA number
534 * and we can decode it into an ascii string
536 if (nvm_data != NVM_PBA_PTR_GUARD) {
537 hw_dbg("NVM PBA number is not stored as string\n");
539 /* we will need 11 characters to store the PBA */
540 if (part_num_size < 11) {
541 hw_dbg("PBA string buffer too small\n");
542 return E1000_ERR_NO_SPACE;
545 /* extract hex string from data and pointer */
546 part_num[0] = (nvm_data >> 12) & 0xF;
547 part_num[1] = (nvm_data >> 8) & 0xF;
548 part_num[2] = (nvm_data >> 4) & 0xF;
549 part_num[3] = nvm_data & 0xF;
550 part_num[4] = (pointer >> 12) & 0xF;
551 part_num[5] = (pointer >> 8) & 0xF;
554 part_num[8] = (pointer >> 4) & 0xF;
555 part_num[9] = pointer & 0xF;
557 /* put a null character on the end of our string */
560 /* switch all the data but the '-' to hex char */
561 for (offset = 0; offset < 10; offset++) {
562 if (part_num[offset] < 0xA)
563 part_num[offset] += '0';
564 else if (part_num[offset] < 0x10)
565 part_num[offset] += 'A' - 0xA;
571 ret_val = hw->nvm.ops.read(hw, pointer, 1, &length);
573 hw_dbg("NVM Read Error\n");
577 if (length == 0xFFFF || length == 0) {
578 hw_dbg("NVM PBA number section invalid length\n");
579 ret_val = E1000_ERR_NVM_PBA_SECTION;
582 /* check if part_num buffer is big enough */
583 if (part_num_size < (((u32)length * 2) - 1)) {
584 hw_dbg("PBA string buffer too small\n");
585 ret_val = E1000_ERR_NO_SPACE;
589 /* trim pba length from start of string */
593 for (offset = 0; offset < length; offset++) {
594 ret_val = hw->nvm.ops.read(hw, pointer + offset, 1, &nvm_data);
596 hw_dbg("NVM Read Error\n");
599 part_num[offset * 2] = (u8)(nvm_data >> 8);
600 part_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
602 part_num[offset * 2] = '\0';
609 * igb_read_mac_addr - Read device MAC address
610 * @hw: pointer to the HW structure
612 * Reads the device MAC address from the EEPROM and stores the value.
613 * Since devices with two ports use the same EEPROM, we increment the
614 * last bit in the MAC address for the second port.
616 s32 igb_read_mac_addr(struct e1000_hw *hw)
622 rar_high = rd32(E1000_RAH(0));
623 rar_low = rd32(E1000_RAL(0));
625 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
626 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
628 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
629 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
631 for (i = 0; i < ETH_ALEN; i++)
632 hw->mac.addr[i] = hw->mac.perm_addr[i];
638 * igb_validate_nvm_checksum - Validate EEPROM checksum
639 * @hw: pointer to the HW structure
641 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
642 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
644 s32 igb_validate_nvm_checksum(struct e1000_hw *hw)
650 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
651 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
653 hw_dbg("NVM Read Error\n");
656 checksum += nvm_data;
659 if (checksum != (u16) NVM_SUM) {
660 hw_dbg("NVM Checksum Invalid\n");
661 ret_val = -E1000_ERR_NVM;
670 * igb_update_nvm_checksum - Update EEPROM checksum
671 * @hw: pointer to the HW structure
673 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
674 * up to the checksum. Then calculates the EEPROM checksum and writes the
675 * value to the EEPROM.
677 s32 igb_update_nvm_checksum(struct e1000_hw *hw)
683 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
684 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
686 hw_dbg("NVM Read Error while updating checksum.\n");
689 checksum += nvm_data;
691 checksum = (u16) NVM_SUM - checksum;
692 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
694 hw_dbg("NVM Write Error while updating checksum.\n");
701 * igb_get_fw_version - Get firmware version information
702 * @hw: pointer to the HW structure
703 * @fw_vers: pointer to output structure
705 * unsupported MAC types will return all 0 version structure
707 void igb_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
709 u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
710 u8 q, hval, rem, result;
711 u16 comb_verh, comb_verl, comb_offset;
713 memset(fw_vers, 0, sizeof(struct e1000_fw_version));
715 /* basic eeprom version numbers and bits used vary by part and by tool
716 * used to create the nvm images. Check which data format we have.
718 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
719 switch (hw->mac.type) {
721 igb_read_invm_version(hw, fw_vers);
726 /* Use this format, unless EETRACK ID exists,
727 * then use alternate format
729 if ((etrack_test & NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {
730 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
731 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
733 fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)
735 fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);
740 if (!(igb_get_flash_presence_i210(hw))) {
741 igb_read_invm_version(hw, fw_vers);
746 /* find combo image version */
747 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
748 if ((comb_offset != 0x0) &&
749 (comb_offset != NVM_VER_INVALID)) {
751 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
752 + 1), 1, &comb_verh);
753 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
756 /* get Option Rom version if it exists and is valid */
757 if ((comb_verh && comb_verl) &&
758 ((comb_verh != NVM_VER_INVALID) &&
759 (comb_verl != NVM_VER_INVALID))) {
761 fw_vers->or_valid = true;
763 comb_verl >> NVM_COMB_VER_SHFT;
765 (comb_verl << NVM_COMB_VER_SHFT)
766 | (comb_verh >> NVM_COMB_VER_SHFT);
768 comb_verh & NVM_COMB_VER_MASK;
775 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
776 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
779 /* check for old style version format in newer images*/
780 if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
781 eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
783 eeprom_verl = (fw_version & NVM_MINOR_MASK)
786 /* Convert minor value to hex before assigning to output struct
787 * Val to be converted will not be higher than 99, per tool output
789 q = eeprom_verl / NVM_HEX_CONV;
790 hval = q * NVM_HEX_TENS;
791 rem = eeprom_verl % NVM_HEX_CONV;
793 fw_vers->eep_minor = result;
796 if ((etrack_test & NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
797 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
798 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
799 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)