drivers/net/ethernet/intel/igb/igb_main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
   3
   4 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   5
   6 #include <linux/module.h>
   7 #include <linux/types.h>
   8 #include <linux/init.h>
   9 #include <linux/bitops.h>
  10 #include <linux/vmalloc.h>
  11 #include <linux/pagemap.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/ipv6.h>
  14 #include <linux/slab.h>
  15 #include <net/checksum.h>
  16 #include <net/ip6_checksum.h>
  17 #include <net/pkt_sched.h>
  18 #include <net/pkt_cls.h>
  19 #include <linux/net_tstamp.h>
  20 #include <linux/mii.h>
  21 #include <linux/ethtool.h>
  22 #include <linux/if.h>
  23 #include <linux/if_vlan.h>
  24 #include <linux/pci.h>
  25 #include <linux/delay.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/ip.h>
  28 #include <linux/tcp.h>
  29 #include <linux/sctp.h>
  30 #include <linux/if_ether.h>
  31 #include <linux/aer.h>
  32 #include <linux/prefetch.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/etherdevice.h>
  35 #ifdef CONFIG_IGB_DCA
  36 #include <linux/dca.h>
  37 #endif
  38 #include <linux/i2c.h>
  39 #include "igb.h"
  40
  41 #define MAJ 5
  42 #define MIN 6
  43 #define BUILD 0
  44 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  45 __stringify(BUILD) "-k"
  46
  47 enum queue_mode {
  48         QUEUE_MODE_STRICT_PRIORITY,
  49         QUEUE_MODE_STREAM_RESERVATION,
  50 };
  51
  52 enum tx_queue_prio {
  53         TX_QUEUE_PRIO_HIGH,
  54         TX_QUEUE_PRIO_LOW,
  55 };
  56
  57 char igb_driver_name[] = "igb";
  58 char igb_driver_version[] = DRV_VERSION;
  59 static const char igb_driver_string[] =
  60                                 "Intel(R) Gigabit Ethernet Network Driver";
  61 static const char igb_copyright[] =
  62                                 "Copyright (c) 2007-2014 Intel Corporation.";
  63
  64 static const struct e1000_info *igb_info_tbl[] = {
  65         [board_82575] = &e1000_82575_info,
  66 };
  67
  68 static const struct pci_device_id igb_pci_tbl[] = {
  69         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) },
  70         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) },
  71         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) },
  72         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
  73         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
  74         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
  75         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
  76         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
  77         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 },
  78         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 },
  79         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
  80         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
  81         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
  82         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
  83         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
  84         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
  85         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
  86         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
  87         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
  88         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
  89         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
  90         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
  91         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
  92         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
  93         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
  94         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
  95         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
  96         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
  97         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
  98         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
  99         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
 100         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
 101         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
 102         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
 103         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
 104         /* required last entry */
 105         {0, }
 106 };
 107
 108 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
 109
 110 static int igb_setup_all_tx_resources(struct igb_adapter *);
 111 static int igb_setup_all_rx_resources(struct igb_adapter *);
 112 static void igb_free_all_tx_resources(struct igb_adapter *);
 113 static void igb_free_all_rx_resources(struct igb_adapter *);
 114 static void igb_setup_mrqc(struct igb_adapter *);
 115 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
 116 static void igb_remove(struct pci_dev *pdev);
 117 static int igb_sw_init(struct igb_adapter *);
 118 int igb_open(struct net_device *);
 119 int igb_close(struct net_device *);
 120 static void igb_configure(struct igb_adapter *);
 121 static void igb_configure_tx(struct igb_adapter *);
 122 static void igb_configure_rx(struct igb_adapter *);
 123 static void igb_clean_all_tx_rings(struct igb_adapter *);
 124 static void igb_clean_all_rx_rings(struct igb_adapter *);
 125 static void igb_clean_tx_ring(struct igb_ring *);
 126 static void igb_clean_rx_ring(struct igb_ring *);
 127 static void igb_set_rx_mode(struct net_device *);
 128 static void igb_update_phy_info(struct timer_list *);
 129 static void igb_watchdog(struct timer_list *);
 130 static void igb_watchdog_task(struct work_struct *);
 131 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
 132 static void igb_get_stats64(struct net_device *dev,
 133                             struct rtnl_link_stats64 *stats);
 134 static int igb_change_mtu(struct net_device *, int);
 135 static int igb_set_mac(struct net_device *, void *);
 136 static void igb_set_uta(struct igb_adapter *adapter, bool set);
 137 static irqreturn_t igb_intr(int irq, void *);
 138 static irqreturn_t igb_intr_msi(int irq, void *);
 139 static irqreturn_t igb_msix_other(int irq, void *);
 140 static irqreturn_t igb_msix_ring(int irq, void *);
 141 #ifdef CONFIG_IGB_DCA
 142 static void igb_update_dca(struct igb_q_vector *);
 143 static void igb_setup_dca(struct igb_adapter *);
 144 #endif /* CONFIG_IGB_DCA */
 145 static int igb_poll(struct napi_struct *, int);
 146 static bool igb_clean_tx_irq(struct igb_q_vector *, int);
 147 static int igb_clean_rx_irq(struct igb_q_vector *, int);
 148 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 149 static void igb_tx_timeout(struct net_device *);
 150 static void igb_reset_task(struct work_struct *);
 151 static void igb_vlan_mode(struct net_device *netdev,
 152                           netdev_features_t features);
 153 static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16);
 154 static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16);
 155 static void igb_restore_vlan(struct igb_adapter *);
 156 static void igb_rar_set_index(struct igb_adapter *, u32);
 157 static void igb_ping_all_vfs(struct igb_adapter *);
 158 static void igb_msg_task(struct igb_adapter *);
 159 static void igb_vmm_control(struct igb_adapter *);
 160 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
 161 static void igb_flush_mac_table(struct igb_adapter *);
 162 static int igb_available_rars(struct igb_adapter *, u8);
 163 static void igb_set_default_mac_filter(struct igb_adapter *);
 164 static int igb_uc_sync(struct net_device *, const unsigned char *);
 165 static int igb_uc_unsync(struct net_device *, const unsigned char *);
 166 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 167 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
 168 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
 169                                int vf, u16 vlan, u8 qos, __be16 vlan_proto);
 170 static int igb_ndo_set_vf_bw(struct net_device *, int, int, int);
 171 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
 172                                    bool setting);
 173 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf,
 174                                 bool setting);
 175 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
 176                                  struct ifla_vf_info *ivi);
 177 static void igb_check_vf_rate_limit(struct igb_adapter *);
 178 static void igb_nfc_filter_exit(struct igb_adapter *adapter);
 179 static void igb_nfc_filter_restore(struct igb_adapter *adapter);
 180
 181 #ifdef CONFIG_PCI_IOV
 182 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
 183 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs);
 184 static int igb_disable_sriov(struct pci_dev *dev);
 185 static int igb_pci_disable_sriov(struct pci_dev *dev);
 186 #endif
 187
 188 static int igb_suspend(struct device *);
 189 static int igb_resume(struct device *);
 190 static int igb_runtime_suspend(struct device *dev);
 191 static int igb_runtime_resume(struct device *dev);
 192 static int igb_runtime_idle(struct device *dev);
 193 static const struct dev_pm_ops igb_pm_ops = {
 194         SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
 195         SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
 196                         igb_runtime_idle)
 197 };
 198 static void igb_shutdown(struct pci_dev *);
 199 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
 200 #ifdef CONFIG_IGB_DCA
 201 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 202 static struct notifier_block dca_notifier = {
 203         .notifier_call  = igb_notify_dca,
 204         .next           = NULL,
 205         .priority       = 0
 206 };
 207 #endif
 208 #ifdef CONFIG_PCI_IOV
 209 static unsigned int max_vfs;
 210 module_param(max_vfs, uint, 0);
 211 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
 212 #endif /* CONFIG_PCI_IOV */
 213
 214 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 215                      pci_channel_state_t);
 216 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 217 static void igb_io_resume(struct pci_dev *);
 218
 219 static const struct pci_error_handlers igb_err_handler = {
 220         .error_detected = igb_io_error_detected,
 221         .slot_reset = igb_io_slot_reset,
 222         .resume = igb_io_resume,
 223 };
 224
 225 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
 226
 227 static struct pci_driver igb_driver = {
 228         .name     = igb_driver_name,
 229         .id_table = igb_pci_tbl,
 230         .probe    = igb_probe,
 231         .remove   = igb_remove,
 232 #ifdef CONFIG_PM
 233         .driver.pm = &igb_pm_ops,
 234 #endif
 235         .shutdown = igb_shutdown,
 236         .sriov_configure = igb_pci_sriov_configure,
 237         .err_handler = &igb_err_handler
 238 };
 239
 240 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 241 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 242 MODULE_LICENSE("GPL v2");
 243 MODULE_VERSION(DRV_VERSION);
 244
 245 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
 246 static int debug = -1;
 247 module_param(debug, int, 0);
 248 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
 249
 250 struct igb_reg_info {
 251         u32 ofs;
 252         char *name;
 253 };
 254
 255 static const struct igb_reg_info igb_reg_info_tbl[] = {
 256
 257         /* General Registers */
 258         {E1000_CTRL, "CTRL"},
 259         {E1000_STATUS, "STATUS"},
 260         {E1000_CTRL_EXT, "CTRL_EXT"},
 261
 262         /* Interrupt Registers */
 263         {E1000_ICR, "ICR"},
 264
 265         /* RX Registers */
 266         {E1000_RCTL, "RCTL"},
 267         {E1000_RDLEN(0), "RDLEN"},
 268         {E1000_RDH(0), "RDH"},
 269         {E1000_RDT(0), "RDT"},
 270         {E1000_RXDCTL(0), "RXDCTL"},
 271         {E1000_RDBAL(0), "RDBAL"},
 272         {E1000_RDBAH(0), "RDBAH"},
 273
 274         /* TX Registers */
 275         {E1000_TCTL, "TCTL"},
 276         {E1000_TDBAL(0), "TDBAL"},
 277         {E1000_TDBAH(0), "TDBAH"},
 278         {E1000_TDLEN(0), "TDLEN"},
 279         {E1000_TDH(0), "TDH"},
 280         {E1000_TDT(0), "TDT"},
 281         {E1000_TXDCTL(0), "TXDCTL"},
 282         {E1000_TDFH, "TDFH"},
 283         {E1000_TDFT, "TDFT"},
 284         {E1000_TDFHS, "TDFHS"},
 285         {E1000_TDFPC, "TDFPC"},
 286
 287         /* List Terminator */
 288         {}
 289 };
 290
 291 /* igb_regdump - register printout routine */
 292 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
 293 {
 294         int n = 0;
 295         char rname[16];
 296         u32 regs[8];
 297
 298         switch (reginfo->ofs) {
 299         case E1000_RDLEN(0):
 300                 for (n = 0; n < 4; n++)
 301                         regs[n] = rd32(E1000_RDLEN(n));
 302                 break;
 303         case E1000_RDH(0):
 304                 for (n = 0; n < 4; n++)
 305                         regs[n] = rd32(E1000_RDH(n));
 306                 break;
 307         case E1000_RDT(0):
 308                 for (n = 0; n < 4; n++)
 309                         regs[n] = rd32(E1000_RDT(n));
 310                 break;
 311         case E1000_RXDCTL(0):
 312                 for (n = 0; n < 4; n++)
 313                         regs[n] = rd32(E1000_RXDCTL(n));
 314                 break;
 315         case E1000_RDBAL(0):
 316                 for (n = 0; n < 4; n++)
 317                         regs[n] = rd32(E1000_RDBAL(n));
 318                 break;
 319         case E1000_RDBAH(0):
 320                 for (n = 0; n < 4; n++)
 321                         regs[n] = rd32(E1000_RDBAH(n));
 322                 break;
 323         case E1000_TDBAL(0):
 324                 for (n = 0; n < 4; n++)
 325                         regs[n] = rd32(E1000_RDBAL(n));
 326                 break;
 327         case E1000_TDBAH(0):
 328                 for (n = 0; n < 4; n++)
 329                         regs[n] = rd32(E1000_TDBAH(n));
 330                 break;
 331         case E1000_TDLEN(0):
 332                 for (n = 0; n < 4; n++)
 333                         regs[n] = rd32(E1000_TDLEN(n));
 334                 break;
 335         case E1000_TDH(0):
 336                 for (n = 0; n < 4; n++)
 337                         regs[n] = rd32(E1000_TDH(n));
 338                 break;
 339         case E1000_TDT(0):
 340                 for (n = 0; n < 4; n++)
 341                         regs[n] = rd32(E1000_TDT(n));
 342                 break;
 343         case E1000_TXDCTL(0):
 344                 for (n = 0; n < 4; n++)
 345                         regs[n] = rd32(E1000_TXDCTL(n));
 346                 break;
 347         default:
 348                 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
 349                 return;
 350         }
 351
 352         snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
 353         pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
 354                 regs[2], regs[3]);
 355 }
 356
 357 /* igb_dump - Print registers, Tx-rings and Rx-rings */
 358 static void igb_dump(struct igb_adapter *adapter)
 359 {
 360         struct net_device *netdev = adapter->netdev;
 361         struct e1000_hw *hw = &adapter->hw;
 362         struct igb_reg_info *reginfo;
 363         struct igb_ring *tx_ring;
 364         union e1000_adv_tx_desc *tx_desc;
 365         struct my_u0 { u64 a; u64 b; } *u0;
 366         struct igb_ring *rx_ring;
 367         union e1000_adv_rx_desc *rx_desc;
 368         u32 staterr;
 369         u16 i, n;
 370
 371         if (!netif_msg_hw(adapter))
 372                 return;
 373
 374         /* Print netdevice Info */
 375         if (netdev) {
 376                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 377                 pr_info("Device Name     state            trans_start\n");
 378                 pr_info("%-15s %016lX %016lX\n", netdev->name,
 379                         netdev->state, dev_trans_start(netdev));
 380         }
 381
 382         /* Print Registers */
 383         dev_info(&adapter->pdev->dev, "Register Dump\n");
 384         pr_info(" Register Name   Value\n");
 385         for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
 386              reginfo->name; reginfo++) {
 387                 igb_regdump(hw, reginfo);
 388         }
 389
 390         /* Print TX Ring Summary */
 391         if (!netdev || !netif_running(netdev))
 392                 goto exit;
 393
 394         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 395         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 396         for (n = 0; n < adapter->num_tx_queues; n++) {
 397                 struct igb_tx_buffer *buffer_info;
 398                 tx_ring = adapter->tx_ring[n];
 399                 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 400                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 401                         n, tx_ring->next_to_use, tx_ring->next_to_clean,
 402                         (u64)dma_unmap_addr(buffer_info, dma),
 403                         dma_unmap_len(buffer_info, len),
 404                         buffer_info->next_to_watch,
 405                         (u64)buffer_info->time_stamp);
 406         }
 407
 408         /* Print TX Rings */
 409         if (!netif_msg_tx_done(adapter))
 410                 goto rx_ring_summary;
 411
 412         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 413
 414         /* Transmit Descriptor Formats
 415          *
 416          * Advanced Transmit Descriptor
 417          *   +--------------------------------------------------------------+
 418          * 0 |         Buffer Address [63:0]                                |
 419          *   +--------------------------------------------------------------+
 420          * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
 421          *   +--------------------------------------------------------------+
 422          *   63      46 45    40 39 38 36 35 32 31   24             15       0
 423          */
 424
 425         for (n = 0; n < adapter->num_tx_queues; n++) {
 426                 tx_ring = adapter->tx_ring[n];
 427                 pr_info("------------------------------------\n");
 428                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 429                 pr_info("------------------------------------\n");
 430                 pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] [bi->dma       ] leng  ntw timestamp        bi->skb\n");
 431
 432                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 433                         const char *next_desc;
 434                         struct igb_tx_buffer *buffer_info;
 435                         tx_desc = IGB_TX_DESC(tx_ring, i);
 436                         buffer_info = &tx_ring->tx_buffer_info[i];
 437                         u0 = (struct my_u0 *)tx_desc;
 438                         if (i == tx_ring->next_to_use &&
 439                             i == tx_ring->next_to_clean)
 440                                 next_desc = " NTC/U";
 441                         else if (i == tx_ring->next_to_use)
 442                                 next_desc = " NTU";
 443                         else if (i == tx_ring->next_to_clean)
 444                                 next_desc = " NTC";
 445                         else
 446                                 next_desc = "";
 447
 448                         pr_info("T [0x%03X]    %016llX %016llX %016llX %04X  %p %016llX %p%s\n",
 449                                 i, le64_to_cpu(u0->a),
 450                                 le64_to_cpu(u0->b),
 451                                 (u64)dma_unmap_addr(buffer_info, dma),
 452                                 dma_unmap_len(buffer_info, len),
 453                                 buffer_info->next_to_watch,
 454                                 (u64)buffer_info->time_stamp,
 455                                 buffer_info->skb, next_desc);
 456
 457                         if (netif_msg_pktdata(adapter) && buffer_info->skb)
 458                                 print_hex_dump(KERN_INFO, "",
 459                                         DUMP_PREFIX_ADDRESS,
 460                                         16, 1, buffer_info->skb->data,
 461                                         dma_unmap_len(buffer_info, len),
 462                                         true);
 463                 }
 464         }
 465
 466         /* Print RX Rings Summary */
 467 rx_ring_summary:
 468         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 469         pr_info("Queue [NTU] [NTC]\n");
 470         for (n = 0; n < adapter->num_rx_queues; n++) {
 471                 rx_ring = adapter->rx_ring[n];
 472                 pr_info(" %5d %5X %5X\n",
 473                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 474         }
 475
 476         /* Print RX Rings */
 477         if (!netif_msg_rx_status(adapter))
 478                 goto exit;
 479
 480         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 481
 482         /* Advanced Receive Descriptor (Read) Format
 483          *    63                                           1        0
 484          *    +-----------------------------------------------------+
 485          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 486          *    +----------------------------------------------+------+
 487          *  8 |       Header Buffer Address [63:1]           |  DD  |
 488          *    +-----------------------------------------------------+
 489          *
 490          *
 491          * Advanced Receive Descriptor (Write-Back) Format
 492          *
 493          *   63       48 47    32 31  30      21 20 17 16   4 3     0
 494          *   +------------------------------------------------------+
 495          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 496          *   | Checksum   Ident  |   |           |    | Type | Type |
 497          *   +------------------------------------------------------+
 498          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 499          *   +------------------------------------------------------+
 500          *   63       48 47    32 31            20 19               0
 501          */
 502
 503         for (n = 0; n < adapter->num_rx_queues; n++) {
 504                 rx_ring = adapter->rx_ring[n];
 505                 pr_info("------------------------------------\n");
 506                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 507                 pr_info("------------------------------------\n");
 508                 pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] [bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
 509                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
 510
 511                 for (i = 0; i < rx_ring->count; i++) {
 512                         const char *next_desc;
 513                         struct igb_rx_buffer *buffer_info;
 514                         buffer_info = &rx_ring->rx_buffer_info[i];
 515                         rx_desc = IGB_RX_DESC(rx_ring, i);
 516                         u0 = (struct my_u0 *)rx_desc;
 517                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 518
 519                         if (i == rx_ring->next_to_use)
 520                                 next_desc = " NTU";
 521                         else if (i == rx_ring->next_to_clean)
 522                                 next_desc = " NTC";
 523                         else
 524                                 next_desc = "";
 525
 526                         if (staterr & E1000_RXD_STAT_DD) {
 527                                 /* Descriptor Done */
 528                                 pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
 529                                         "RWB", i,
 530                                         le64_to_cpu(u0->a),
 531                                         le64_to_cpu(u0->b),
 532                                         next_desc);
 533                         } else {
 534                                 pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
 535                                         "R  ", i,
 536                                         le64_to_cpu(u0->a),
 537                                         le64_to_cpu(u0->b),
 538                                         (u64)buffer_info->dma,
 539                                         next_desc);
 540
 541                                 if (netif_msg_pktdata(adapter) &&
 542                                     buffer_info->dma && buffer_info->page) {
 543                                         print_hex_dump(KERN_INFO, "",
 544                                           DUMP_PREFIX_ADDRESS,
 545                                           16, 1,
 546                                           page_address(buffer_info->page) +
 547                                                       buffer_info->page_offset,
 548                                           igb_rx_bufsz(rx_ring), true);
 549                                 }
 550                         }
 551                 }
 552         }
 553
 554 exit:
 555         return;
 556 }
 557
 558 /**
 559  *  igb_get_i2c_data - Reads the I2C SDA data bit
 560  *  @hw: pointer to hardware structure
 561  *  @i2cctl: Current value of I2CCTL register
 562  *
 563  *  Returns the I2C data bit value
 564  **/
 565 static int igb_get_i2c_data(void *data)
 566 {
 567         struct igb_adapter *adapter = (struct igb_adapter *)data;
 568         struct e1000_hw *hw = &adapter->hw;
 569         s32 i2cctl = rd32(E1000_I2CPARAMS);
 570
 571         return !!(i2cctl & E1000_I2C_DATA_IN);
 572 }
 573
 574 /**
 575  *  igb_set_i2c_data - Sets the I2C data bit
 576  *  @data: pointer to hardware structure
 577  *  @state: I2C data value (0 or 1) to set
 578  *
 579  *  Sets the I2C data bit
 580  **/
 581 static void igb_set_i2c_data(void *data, int state)
 582 {
 583         struct igb_adapter *adapter = (struct igb_adapter *)data;
 584         struct e1000_hw *hw = &adapter->hw;
 585         s32 i2cctl = rd32(E1000_I2CPARAMS);
 586
 587         if (state)
 588                 i2cctl |= E1000_I2C_DATA_OUT;
 589         else
 590                 i2cctl &= ~E1000_I2C_DATA_OUT;
 591
 592         i2cctl &= ~E1000_I2C_DATA_OE_N;
 593         i2cctl |= E1000_I2C_CLK_OE_N;
 594         wr32(E1000_I2CPARAMS, i2cctl);
 595         wrfl();
 596
 597 }
 598
 599 /**
 600  *  igb_set_i2c_clk - Sets the I2C SCL clock
 601  *  @data: pointer to hardware structure
 602  *  @state: state to set clock
 603  *
 604  *  Sets the I2C clock line to state
 605  **/
 606 static void igb_set_i2c_clk(void *data, int state)
 607 {
 608         struct igb_adapter *adapter = (struct igb_adapter *)data;
 609         struct e1000_hw *hw = &adapter->hw;
 610         s32 i2cctl = rd32(E1000_I2CPARAMS);
 611
 612         if (state) {
 613                 i2cctl |= E1000_I2C_CLK_OUT;
 614                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 615         } else {
 616                 i2cctl &= ~E1000_I2C_CLK_OUT;
 617                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 618         }
 619         wr32(E1000_I2CPARAMS, i2cctl);
 620         wrfl();
 621 }
 622
 623 /**
 624  *  igb_get_i2c_clk - Gets the I2C SCL clock state
 625  *  @data: pointer to hardware structure
 626  *
 627  *  Gets the I2C clock state
 628  **/
 629 static int igb_get_i2c_clk(void *data)
 630 {
 631         struct igb_adapter *adapter = (struct igb_adapter *)data;
 632         struct e1000_hw *hw = &adapter->hw;
 633         s32 i2cctl = rd32(E1000_I2CPARAMS);
 634
 635         return !!(i2cctl & E1000_I2C_CLK_IN);
 636 }
 637
 638 static const struct i2c_algo_bit_data igb_i2c_algo = {
 639         .setsda         = igb_set_i2c_data,
 640         .setscl         = igb_set_i2c_clk,
 641         .getsda         = igb_get_i2c_data,
 642         .getscl         = igb_get_i2c_clk,
 643         .udelay         = 5,
 644         .timeout        = 20,
 645 };
 646
 647 /**
 648  *  igb_get_hw_dev - return device
 649  *  @hw: pointer to hardware structure
 650  *
 651  *  used by hardware layer to print debugging information
 652  **/
 653 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
 654 {
 655         struct igb_adapter *adapter = hw->back;
 656         return adapter->netdev;
 657 }
 658
 659 /**
 660  *  igb_init_module - Driver Registration Routine
 661  *
 662  *  igb_init_module is the first routine called when the driver is
 663  *  loaded. All it does is register with the PCI subsystem.
 664  **/
 665 static int __init igb_init_module(void)
 666 {
 667         int ret;
 668
 669         pr_info("%s - version %s\n",
 670                igb_driver_string, igb_driver_version);
 671         pr_info("%s\n", igb_copyright);
 672
 673 #ifdef CONFIG_IGB_DCA
 674         dca_register_notify(&dca_notifier);
 675 #endif
 676         ret = pci_register_driver(&igb_driver);
 677         return ret;
 678 }
 679
 680 module_init(igb_init_module);
 681
 682 /**
 683  *  igb_exit_module - Driver Exit Cleanup Routine
 684  *
 685  *  igb_exit_module is called just before the driver is removed
 686  *  from memory.
 687  **/
 688 static void __exit igb_exit_module(void)
 689 {
 690 #ifdef CONFIG_IGB_DCA
 691         dca_unregister_notify(&dca_notifier);
 692 #endif
 693         pci_unregister_driver(&igb_driver);
 694 }
 695
 696 module_exit(igb_exit_module);
 697
 698 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 699 /**
 700  *  igb_cache_ring_register - Descriptor ring to register mapping
 701  *  @adapter: board private structure to initialize
 702  *
 703  *  Once we know the feature-set enabled for the device, we'll cache
 704  *  the register offset the descriptor ring is assigned to.
 705  **/
 706 static void igb_cache_ring_register(struct igb_adapter *adapter)
 707 {
 708         int i = 0, j = 0;
 709         u32 rbase_offset = adapter->vfs_allocated_count;
 710
 711         switch (adapter->hw.mac.type) {
 712         case e1000_82576:
 713                 /* The queues are allocated for virtualization such that VF 0
 714                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 715                  * In order to avoid collision we start at the first free queue
 716                  * and continue consuming queues in the same sequence
 717                  */
 718                 if (adapter->vfs_allocated_count) {
 719                         for (; i < adapter->rss_queues; i++)
 720                                 adapter->rx_ring[i]->reg_idx = rbase_offset +
 721                                                                Q_IDX_82576(i);
 722                 }
 723                 /* Fall through */
 724         case e1000_82575:
 725         case e1000_82580:
 726         case e1000_i350:
 727         case e1000_i354:
 728         case e1000_i210:
 729         case e1000_i211:
 730                 /* Fall through */
 731         default:
 732                 for (; i < adapter->num_rx_queues; i++)
 733                         adapter->rx_ring[i]->reg_idx = rbase_offset + i;
 734                 for (; j < adapter->num_tx_queues; j++)
 735                         adapter->tx_ring[j]->reg_idx = rbase_offset + j;
 736                 break;
 737         }
 738 }
 739
 740 u32 igb_rd32(struct e1000_hw *hw, u32 reg)
 741 {
 742         struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw);
 743         u8 __iomem *hw_addr = READ_ONCE(hw->hw_addr);
 744         u32 value = 0;
 745
 746         if (E1000_REMOVED(hw_addr))
 747                 return ~value;
 748
 749         value = readl(&hw_addr[reg]);
 750
 751         /* reads should not return all F's */
 752         if (!(~value) && (!reg || !(~readl(hw_addr)))) {
 753                 struct net_device *netdev = igb->netdev;
 754                 hw->hw_addr = NULL;
 755                 netdev_err(netdev, "PCIe link lost\n");
 756         }
 757
 758         return value;
 759 }
 760
 761 /**
 762  *  igb_write_ivar - configure ivar for given MSI-X vector
 763  *  @hw: pointer to the HW structure
 764  *  @msix_vector: vector number we are allocating to a given ring
 765  *  @index: row index of IVAR register to write within IVAR table
 766  *  @offset: column offset of in IVAR, should be multiple of 8
 767  *
 768  *  This function is intended to handle the writing of the IVAR register
 769  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
 770  *  each containing an cause allocation for an Rx and Tx ring, and a
 771  *  variable number of rows depending on the number of queues supported.
 772  **/
 773 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
 774                            int index, int offset)
 775 {
 776         u32 ivar = array_rd32(E1000_IVAR0, index);
 777
 778         /* clear any bits that are currently set */
 779         ivar &= ~((u32)0xFF << offset);
 780
 781         /* write vector and valid bit */
 782         ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
 783
 784         array_wr32(E1000_IVAR0, index, ivar);
 785 }
 786
 787 #define IGB_N0_QUEUE -1
 788 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
 789 {
 790         struct igb_adapter *adapter = q_vector->adapter;
 791         struct e1000_hw *hw = &adapter->hw;
 792         int rx_queue = IGB_N0_QUEUE;
 793         int tx_queue = IGB_N0_QUEUE;
 794         u32 msixbm = 0;
 795
 796         if (q_vector->rx.ring)
 797                 rx_queue = q_vector->rx.ring->reg_idx;
 798         if (q_vector->tx.ring)
 799                 tx_queue = q_vector->tx.ring->reg_idx;
 800
 801         switch (hw->mac.type) {
 802         case e1000_82575:
 803                 /* The 82575 assigns vectors using a bitmask, which matches the
 804                  * bitmask for the EICR/EIMS/EIMC registers.  To assign one
 805                  * or more queues to a vector, we write the appropriate bits
 806                  * into the MSIXBM register for that vector.
 807                  */
 808                 if (rx_queue > IGB_N0_QUEUE)
 809                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 810                 if (tx_queue > IGB_N0_QUEUE)
 811                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 812                 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0)
 813                         msixbm |= E1000_EIMS_OTHER;
 814                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 815                 q_vector->eims_value = msixbm;
 816                 break;
 817         case e1000_82576:
 818                 /* 82576 uses a table that essentially consists of 2 columns
 819                  * with 8 rows.  The ordering is column-major so we use the
 820                  * lower 3 bits as the row index, and the 4th bit as the
 821                  * column offset.
 822                  */
 823                 if (rx_queue > IGB_N0_QUEUE)
 824                         igb_write_ivar(hw, msix_vector,
 825                                        rx_queue & 0x7,
 826                                        (rx_queue & 0x8) << 1);
 827                 if (tx_queue > IGB_N0_QUEUE)
 828                         igb_write_ivar(hw, msix_vector,
 829                                        tx_queue & 0x7,
 830                                        ((tx_queue & 0x8) << 1) + 8);
 831                 q_vector->eims_value = BIT(msix_vector);
 832                 break;
 833         case e1000_82580:
 834         case e1000_i350:
 835         case e1000_i354:
 836         case e1000_i210:
 837         case e1000_i211:
 838                 /* On 82580 and newer adapters the scheme is similar to 82576
 839                  * however instead of ordering column-major we have things
 840                  * ordered row-major.  So we traverse the table by using
 841                  * bit 0 as the column offset, and the remaining bits as the
 842                  * row index.
 843                  */
 844                 if (rx_queue > IGB_N0_QUEUE)
 845                         igb_write_ivar(hw, msix_vector,
 846                                        rx_queue >> 1,
 847                                        (rx_queue & 0x1) << 4);
 848                 if (tx_queue > IGB_N0_QUEUE)
 849                         igb_write_ivar(hw, msix_vector,
 850                                        tx_queue >> 1,
 851                                        ((tx_queue & 0x1) << 4) + 8);
 852                 q_vector->eims_value = BIT(msix_vector);
 853                 break;
 854         default:
 855                 BUG();
 856                 break;
 857         }
 858
 859         /* add q_vector eims value to global eims_enable_mask */
 860         adapter->eims_enable_mask |= q_vector->eims_value;
 861
 862         /* configure q_vector to set itr on first interrupt */
 863         q_vector->set_itr = 1;
 864 }
 865
 866 /**
 867  *  igb_configure_msix - Configure MSI-X hardware
 868  *  @adapter: board private structure to initialize
 869  *
 870  *  igb_configure_msix sets up the hardware to properly
 871  *  generate MSI-X interrupts.
 872  **/
 873 static void igb_configure_msix(struct igb_adapter *adapter)
 874 {
 875         u32 tmp;
 876         int i, vector = 0;
 877         struct e1000_hw *hw = &adapter->hw;
 878
 879         adapter->eims_enable_mask = 0;
 880
 881         /* set vector for other causes, i.e. link changes */
 882         switch (hw->mac.type) {
 883         case e1000_82575:
 884                 tmp = rd32(E1000_CTRL_EXT);
 885                 /* enable MSI-X PBA support*/
 886                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 887
 888                 /* Auto-Mask interrupts upon ICR read. */
 889                 tmp |= E1000_CTRL_EXT_EIAME;
 890                 tmp |= E1000_CTRL_EXT_IRCA;
 891
 892                 wr32(E1000_CTRL_EXT, tmp);
 893
 894                 /* enable msix_other interrupt */
 895                 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER);
 896                 adapter->eims_other = E1000_EIMS_OTHER;
 897
 898                 break;
 899
 900         case e1000_82576:
 901         case e1000_82580:
 902         case e1000_i350:
 903         case e1000_i354:
 904         case e1000_i210:
 905         case e1000_i211:
 906                 /* Turn on MSI-X capability first, or our settings
 907                  * won't stick.  And it will take days to debug.
 908                  */
 909                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 910                      E1000_GPIE_PBA | E1000_GPIE_EIAME |
 911                      E1000_GPIE_NSICR);
 912
 913                 /* enable msix_other interrupt */
 914                 adapter->eims_other = BIT(vector);
 915                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 916
 917                 wr32(E1000_IVAR_MISC, tmp);
 918                 break;
 919         default:
 920                 /* do nothing, since nothing else supports MSI-X */
 921                 break;
 922         } /* switch (hw->mac.type) */
 923
 924         adapter->eims_enable_mask |= adapter->eims_other;
 925
 926         for (i = 0; i < adapter->num_q_vectors; i++)
 927                 igb_assign_vector(adapter->q_vector[i], vector++);
 928
 929         wrfl();
 930 }
 931
 932 /**
 933  *  igb_request_msix - Initialize MSI-X interrupts
 934  *  @adapter: board private structure to initialize
 935  *
 936  *  igb_request_msix allocates MSI-X vectors and requests interrupts from the
 937  *  kernel.
 938  **/
 939 static int igb_request_msix(struct igb_adapter *adapter)
 940 {
 941         struct net_device *netdev = adapter->netdev;
 942         int i, err = 0, vector = 0, free_vector = 0;
 943
 944         err = request_irq(adapter->msix_entries[vector].vector,
 945                           igb_msix_other, 0, netdev->name, adapter);
 946         if (err)
 947                 goto err_out;
 948
 949         for (i = 0; i < adapter->num_q_vectors; i++) {
 950                 struct igb_q_vector *q_vector = adapter->q_vector[i];
 951
 952                 vector++;
 953
 954                 q_vector->itr_register = adapter->io_addr + E1000_EITR(vector);
 955
 956                 if (q_vector->rx.ring && q_vector->tx.ring)
 957                         sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
 958                                 q_vector->rx.ring->queue_index);
 959                 else if (q_vector->tx.ring)
 960                         sprintf(q_vector->name, "%s-tx-%u", netdev->name,
 961                                 q_vector->tx.ring->queue_index);
 962                 else if (q_vector->rx.ring)
 963                         sprintf(q_vector->name, "%s-rx-%u", netdev->name,
 964                                 q_vector->rx.ring->queue_index);
 965                 else
 966                         sprintf(q_vector->name, "%s-unused", netdev->name);
 967
 968                 err = request_irq(adapter->msix_entries[vector].vector,
 969                                   igb_msix_ring, 0, q_vector->name,
 970                                   q_vector);
 971                 if (err)
 972                         goto err_free;
 973         }
 974
 975         igb_configure_msix(adapter);
 976         return 0;
 977
 978 err_free:
 979         /* free already assigned IRQs */
 980         free_irq(adapter->msix_entries[free_vector++].vector, adapter);
 981
 982         vector--;
 983         for (i = 0; i < vector; i++) {
 984                 free_irq(adapter->msix_entries[free_vector++].vector,
 985                          adapter->q_vector[i]);
 986         }
 987 err_out:
 988         return err;
 989 }
 990
 991 /**
 992  *  igb_free_q_vector - Free memory allocated for specific interrupt vector
 993  *  @adapter: board private structure to initialize
 994  *  @v_idx: Index of vector to be freed
 995  *
 996  *  This function frees the memory allocated to the q_vector.
 997  **/
 998 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
 999 {
1000         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1001
1002         adapter->q_vector[v_idx] = NULL;
1003
1004         /* igb_get_stats64() might access the rings on this vector,
1005          * we must wait a grace period before freeing it.
1006          */
1007         if (q_vector)
1008                 kfree_rcu(q_vector, rcu);
1009 }
1010
1011 /**
1012  *  igb_reset_q_vector - Reset config for interrupt vector
1013  *  @adapter: board private structure to initialize
1014  *  @v_idx: Index of vector to be reset
1015  *
1016  *  If NAPI is enabled it will delete any references to the
1017  *  NAPI struct. This is preparation for igb_free_q_vector.
1018  **/
1019 static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx)
1020 {
1021         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1022
1023         /* Coming from igb_set_interrupt_capability, the vectors are not yet
1024          * allocated. So, q_vector is NULL so we should stop here.
1025          */
1026         if (!q_vector)
1027                 return;
1028
1029         if (q_vector->tx.ring)
1030                 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
1031
1032         if (q_vector->rx.ring)
1033                 adapter->rx_ring[q_vector->rx.ring->queue_index] = NULL;
1034
1035         netif_napi_del(&q_vector->napi);
1036
1037 }
1038
1039 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
1040 {
1041         int v_idx = adapter->num_q_vectors;
1042
1043         if (adapter->flags & IGB_FLAG_HAS_MSIX)
1044                 pci_disable_msix(adapter->pdev);
1045         else if (adapter->flags & IGB_FLAG_HAS_MSI)
1046                 pci_disable_msi(adapter->pdev);
1047
1048         while (v_idx--)
1049                 igb_reset_q_vector(adapter, v_idx);
1050 }
1051
1052 /**
1053  *  igb_free_q_vectors - Free memory allocated for interrupt vectors
1054  *  @adapter: board private structure to initialize
1055  *
1056  *  This function frees the memory allocated to the q_vectors.  In addition if
1057  *  NAPI is enabled it will delete any references to the NAPI struct prior
1058  *  to freeing the q_vector.
1059  **/
1060 static void igb_free_q_vectors(struct igb_adapter *adapter)
1061 {
1062         int v_idx = adapter->num_q_vectors;
1063
1064         adapter->num_tx_queues = 0;
1065         adapter->num_rx_queues = 0;
1066         adapter->num_q_vectors = 0;
1067
1068         while (v_idx--) {
1069                 igb_reset_q_vector(adapter, v_idx);
1070                 igb_free_q_vector(adapter, v_idx);
1071         }
1072 }
1073
1074 /**
1075  *  igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1076  *  @adapter: board private structure to initialize
1077  *
1078  *  This function resets the device so that it has 0 Rx queues, Tx queues, and
1079  *  MSI-X interrupts allocated.
1080  */
1081 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1082 {
1083         igb_free_q_vectors(adapter);
1084         igb_reset_interrupt_capability(adapter);
1085 }
1086
1087 /**
1088  *  igb_set_interrupt_capability - set MSI or MSI-X if supported
1089  *  @adapter: board private structure to initialize
1090  *  @msix: boolean value of MSIX capability
1091  *
1092  *  Attempt to configure interrupts using the best available
1093  *  capabilities of the hardware and kernel.
1094  **/
1095 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1096 {
1097         int err;
1098         int numvecs, i;
1099
1100         if (!msix)
1101                 goto msi_only;
1102         adapter->flags |= IGB_FLAG_HAS_MSIX;
1103
1104         /* Number of supported queues. */
1105         adapter->num_rx_queues = adapter->rss_queues;
1106         if (adapter->vfs_allocated_count)
1107                 adapter->num_tx_queues = 1;
1108         else
1109                 adapter->num_tx_queues = adapter->rss_queues;
1110
1111         /* start with one vector for every Rx queue */
1112         numvecs = adapter->num_rx_queues;
1113
1114         /* if Tx handler is separate add 1 for every Tx queue */
1115         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1116                 numvecs += adapter->num_tx_queues;
1117
1118         /* store the number of vectors reserved for queues */
1119         adapter->num_q_vectors = numvecs;
1120
1121         /* add 1 vector for link status interrupts */
1122         numvecs++;
1123         for (i = 0; i < numvecs; i++)
1124                 adapter->msix_entries[i].entry = i;
1125
1126         err = pci_enable_msix_range(adapter->pdev,
1127                                     adapter->msix_entries,
1128                                     numvecs,
1129                                     numvecs);
1130         if (err > 0)
1131                 return;
1132
1133         igb_reset_interrupt_capability(adapter);
1134
1135         /* If we can't do MSI-X, try MSI */
1136 msi_only:
1137         adapter->flags &= ~IGB_FLAG_HAS_MSIX;
1138 #ifdef CONFIG_PCI_IOV
1139         /* disable SR-IOV for non MSI-X configurations */
1140         if (adapter->vf_data) {
1141                 struct e1000_hw *hw = &adapter->hw;
1142                 /* disable iov and allow time for transactions to clear */
1143                 pci_disable_sriov(adapter->pdev);
1144                 msleep(500);
1145
1146                 kfree(adapter->vf_mac_list);
1147                 adapter->vf_mac_list = NULL;
1148                 kfree(adapter->vf_data);
1149                 adapter->vf_data = NULL;
1150                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1151                 wrfl();
1152                 msleep(100);
1153                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1154         }
1155 #endif
1156         adapter->vfs_allocated_count = 0;
1157         adapter->rss_queues = 1;
1158         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1159         adapter->num_rx_queues = 1;
1160         adapter->num_tx_queues = 1;
1161         adapter->num_q_vectors = 1;
1162         if (!pci_enable_msi(adapter->pdev))
1163                 adapter->flags |= IGB_FLAG_HAS_MSI;
1164 }
1165
1166 static void igb_add_ring(struct igb_ring *ring,
1167                          struct igb_ring_container *head)
1168 {
1169         head->ring = ring;
1170         head->count++;
1171 }
1172
1173 /**
1174  *  igb_alloc_q_vector - Allocate memory for a single interrupt vector
1175  *  @adapter: board private structure to initialize
1176  *  @v_count: q_vectors allocated on adapter, used for ring interleaving
1177  *  @v_idx: index of vector in adapter struct
1178  *  @txr_count: total number of Tx rings to allocate
1179  *  @txr_idx: index of first Tx ring to allocate
1180  *  @rxr_count: total number of Rx rings to allocate
1181  *  @rxr_idx: index of first Rx ring to allocate
1182  *
1183  *  We allocate one q_vector.  If allocation fails we return -ENOMEM.
1184  **/
1185 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1186                               int v_count, int v_idx,
1187                               int txr_count, int txr_idx,
1188                               int rxr_count, int rxr_idx)
1189 {
1190         struct igb_q_vector *q_vector;
1191         struct igb_ring *ring;
1192         int ring_count;
1193         size_t size;
1194
1195         /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1196         if (txr_count > 1 || rxr_count > 1)
1197                 return -ENOMEM;
1198
1199         ring_count = txr_count + rxr_count;
1200         size = struct_size(q_vector, ring, ring_count);
1201
1202         /* allocate q_vector and rings */
1203         q_vector = adapter->q_vector[v_idx];
1204         if (!q_vector) {
1205                 q_vector = kzalloc(size, GFP_KERNEL);
1206         } else if (size > ksize(q_vector)) {
1207                 kfree_rcu(q_vector, rcu);
1208                 q_vector = kzalloc(size, GFP_KERNEL);
1209         } else {
1210                 memset(q_vector, 0, size);
1211         }
1212         if (!q_vector)
1213                 return -ENOMEM;
1214
1215         /* initialize NAPI */
1216         netif_napi_add(adapter->netdev, &q_vector->napi,
1217                        igb_poll, 64);
1218
1219         /* tie q_vector and adapter together */
1220         adapter->q_vector[v_idx] = q_vector;
1221         q_vector->adapter = adapter;
1222
1223         /* initialize work limits */
1224         q_vector->tx.work_limit = adapter->tx_work_limit;
1225
1226         /* initialize ITR configuration */
1227         q_vector->itr_register = adapter->io_addr + E1000_EITR(0);
1228         q_vector->itr_val = IGB_START_ITR;
1229
1230         /* initialize pointer to rings */
1231         ring = q_vector->ring;
1232
1233         /* intialize ITR */
1234         if (rxr_count) {
1235                 /* rx or rx/tx vector */
1236                 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3)
1237                         q_vector->itr_val = adapter->rx_itr_setting;
1238         } else {
1239                 /* tx only vector */
1240                 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3)
1241                         q_vector->itr_val = adapter->tx_itr_setting;
1242         }
1243
1244         if (txr_count) {
1245                 /* assign generic ring traits */
1246                 ring->dev = &adapter->pdev->dev;
1247                 ring->netdev = adapter->netdev;
1248
1249                 /* configure backlink on ring */
1250                 ring->q_vector = q_vector;
1251
1252                 /* update q_vector Tx values */
1253                 igb_add_ring(ring, &q_vector->tx);
1254
1255                 /* For 82575, context index must be unique per ring. */
1256                 if (adapter->hw.mac.type == e1000_82575)
1257                         set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1258
1259                 /* apply Tx specific ring traits */
1260                 ring->count = adapter->tx_ring_count;
1261                 ring->queue_index = txr_idx;
1262
1263                 ring->cbs_enable = false;
1264                 ring->idleslope = 0;
1265                 ring->sendslope = 0;
1266                 ring->hicredit = 0;
1267                 ring->locredit = 0;
1268
1269                 u64_stats_init(&ring->tx_syncp);
1270                 u64_stats_init(&ring->tx_syncp2);
1271
1272                 /* assign ring to adapter */
1273                 adapter->tx_ring[txr_idx] = ring;
1274
1275                 /* push pointer to next ring */
1276                 ring++;
1277         }
1278
1279         if (rxr_count) {
1280                 /* assign generic ring traits */
1281                 ring->dev = &adapter->pdev->dev;
1282                 ring->netdev = adapter->netdev;
1283
1284                 /* configure backlink on ring */
1285                 ring->q_vector = q_vector;
1286
1287                 /* update q_vector Rx values */
1288                 igb_add_ring(ring, &q_vector->rx);
1289
1290                 /* set flag indicating ring supports SCTP checksum offload */
1291                 if (adapter->hw.mac.type >= e1000_82576)
1292                         set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1293
1294                 /* On i350, i354, i210, and i211, loopback VLAN packets
1295                  * have the tag byte-swapped.
1296                  */
1297                 if (adapter->hw.mac.type >= e1000_i350)
1298                         set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1299
1300                 /* apply Rx specific ring traits */
1301                 ring->count = adapter->rx_ring_count;
1302                 ring->queue_index = rxr_idx;
1303
1304                 u64_stats_init(&ring->rx_syncp);
1305
1306                 /* assign ring to adapter */
1307                 adapter->rx_ring[rxr_idx] = ring;
1308         }
1309
1310         return 0;
1311 }
1312
1313
1314 /**
1315  *  igb_alloc_q_vectors - Allocate memory for interrupt vectors
1316  *  @adapter: board private structure to initialize
1317  *
1318  *  We allocate one q_vector per queue interrupt.  If allocation fails we
1319  *  return -ENOMEM.
1320  **/
1321 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1322 {
1323         int q_vectors = adapter->num_q_vectors;
1324         int rxr_remaining = adapter->num_rx_queues;
1325         int txr_remaining = adapter->num_tx_queues;
1326         int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1327         int err;
1328
1329         if (q_vectors >= (rxr_remaining + txr_remaining)) {
1330                 for (; rxr_remaining; v_idx++) {
1331                         err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1332                                                  0, 0, 1, rxr_idx);
1333
1334                         if (err)
1335                                 goto err_out;
1336
1337                         /* update counts and index */
1338                         rxr_remaining--;
1339                         rxr_idx++;
1340                 }
1341         }
1342
1343         for (; v_idx < q_vectors; v_idx++) {
1344                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1345                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1346
1347                 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1348                                          tqpv, txr_idx, rqpv, rxr_idx);
1349
1350                 if (err)
1351                         goto err_out;
1352
1353                 /* update counts and index */
1354                 rxr_remaining -= rqpv;
1355                 txr_remaining -= tqpv;
1356                 rxr_idx++;
1357                 txr_idx++;
1358         }
1359
1360         return 0;
1361
1362 err_out:
1363         adapter->num_tx_queues = 0;
1364         adapter->num_rx_queues = 0;
1365         adapter->num_q_vectors = 0;
1366
1367         while (v_idx--)
1368                 igb_free_q_vector(adapter, v_idx);
1369
1370         return -ENOMEM;
1371 }
1372
1373 /**
1374  *  igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1375  *  @adapter: board private structure to initialize
1376  *  @msix: boolean value of MSIX capability
1377  *
1378  *  This function initializes the interrupts and allocates all of the queues.
1379  **/
1380 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1381 {
1382         struct pci_dev *pdev = adapter->pdev;
1383         int err;
1384
1385         igb_set_interrupt_capability(adapter, msix);
1386
1387         err = igb_alloc_q_vectors(adapter);
1388         if (err) {
1389                 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1390                 goto err_alloc_q_vectors;
1391         }
1392
1393         igb_cache_ring_register(adapter);
1394
1395         return 0;
1396
1397 err_alloc_q_vectors:
1398         igb_reset_interrupt_capability(adapter);
1399         return err;
1400 }
1401
1402 /**
1403  *  igb_request_irq - initialize interrupts
1404  *  @adapter: board private structure to initialize
1405  *
1406  *  Attempts to configure interrupts using the best available
1407  *  capabilities of the hardware and kernel.
1408  **/
1409 static int igb_request_irq(struct igb_adapter *adapter)
1410 {
1411         struct net_device *netdev = adapter->netdev;
1412         struct pci_dev *pdev = adapter->pdev;
1413         int err = 0;
1414
1415         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1416                 err = igb_request_msix(adapter);
1417                 if (!err)
1418                         goto request_done;
1419                 /* fall back to MSI */
1420                 igb_free_all_tx_resources(adapter);
1421                 igb_free_all_rx_resources(adapter);
1422
1423                 igb_clear_interrupt_scheme(adapter);
1424                 err = igb_init_interrupt_scheme(adapter, false);
1425                 if (err)
1426                         goto request_done;
1427
1428                 igb_setup_all_tx_resources(adapter);
1429                 igb_setup_all_rx_resources(adapter);
1430                 igb_configure(adapter);
1431         }
1432
1433         igb_assign_vector(adapter->q_vector[0], 0);
1434
1435         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1436                 err = request_irq(pdev->irq, igb_intr_msi, 0,
1437                                   netdev->name, adapter);
1438                 if (!err)
1439                         goto request_done;
1440
1441                 /* fall back to legacy interrupts */
1442                 igb_reset_interrupt_capability(adapter);
1443                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1444         }
1445
1446         err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1447                           netdev->name, adapter);
1448
1449         if (err)
1450                 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1451                         err);
1452
1453 request_done:
1454         return err;
1455 }
1456
1457 static void igb_free_irq(struct igb_adapter *adapter)
1458 {
1459         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1460                 int vector = 0, i;
1461
1462                 free_irq(adapter->msix_entries[vector++].vector, adapter);
1463
1464                 for (i = 0; i < adapter->num_q_vectors; i++)
1465                         free_irq(adapter->msix_entries[vector++].vector,
1466                                  adapter->q_vector[i]);
1467         } else {
1468                 free_irq(adapter->pdev->irq, adapter);
1469         }
1470 }
1471
1472 /**
1473  *  igb_irq_disable - Mask off interrupt generation on the NIC
1474  *  @adapter: board private structure
1475  **/
1476 static void igb_irq_disable(struct igb_adapter *adapter)
1477 {
1478         struct e1000_hw *hw = &adapter->hw;
1479
1480         /* we need to be careful when disabling interrupts.  The VFs are also
1481          * mapped into these registers and so clearing the bits can cause
1482          * issues on the VF drivers so we only need to clear what we set
1483          */
1484         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1485                 u32 regval = rd32(E1000_EIAM);
1486
1487                 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1488                 wr32(E1000_EIMC, adapter->eims_enable_mask);
1489                 regval = rd32(E1000_EIAC);
1490                 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1491         }
1492
1493         wr32(E1000_IAM, 0);
1494         wr32(E1000_IMC, ~0);
1495         wrfl();
1496         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1497                 int i;
1498
1499                 for (i = 0; i < adapter->num_q_vectors; i++)
1500                         synchronize_irq(adapter->msix_entries[i].vector);
1501         } else {
1502                 synchronize_irq(adapter->pdev->irq);
1503         }
1504 }
1505
1506 /**
1507  *  igb_irq_enable - Enable default interrupt generation settings
1508  *  @adapter: board private structure
1509  **/
1510 static void igb_irq_enable(struct igb_adapter *adapter)
1511 {
1512         struct e1000_hw *hw = &adapter->hw;
1513
1514         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
1515                 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1516                 u32 regval = rd32(E1000_EIAC);
1517
1518                 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1519                 regval = rd32(E1000_EIAM);
1520                 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1521                 wr32(E1000_EIMS, adapter->eims_enable_mask);
1522                 if (adapter->vfs_allocated_count) {
1523                         wr32(E1000_MBVFIMR, 0xFF);
1524                         ims |= E1000_IMS_VMMB;
1525                 }
1526                 wr32(E1000_IMS, ims);
1527         } else {
1528                 wr32(E1000_IMS, IMS_ENABLE_MASK |
1529                                 E1000_IMS_DRSTA);
1530                 wr32(E1000_IAM, IMS_ENABLE_MASK |
1531                                 E1000_IMS_DRSTA);
1532         }
1533 }
1534
1535 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1536 {
1537         struct e1000_hw *hw = &adapter->hw;
1538         u16 pf_id = adapter->vfs_allocated_count;
1539         u16 vid = adapter->hw.mng_cookie.vlan_id;
1540         u16 old_vid = adapter->mng_vlan_id;
1541
1542         if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1543                 /* add VID to filter table */
1544                 igb_vfta_set(hw, vid, pf_id, true, true);
1545                 adapter->mng_vlan_id = vid;
1546         } else {
1547                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1548         }
1549
1550         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1551             (vid != old_vid) &&
1552             !test_bit(old_vid, adapter->active_vlans)) {
1553                 /* remove VID from filter table */
1554                 igb_vfta_set(hw, vid, pf_id, false, true);
1555         }
1556 }
1557
1558 /**
1559  *  igb_release_hw_control - release control of the h/w to f/w
1560  *  @adapter: address of board private structure
1561  *
1562  *  igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1563  *  For ASF and Pass Through versions of f/w this means that the
1564  *  driver is no longer loaded.
1565  **/
1566 static void igb_release_hw_control(struct igb_adapter *adapter)
1567 {
1568         struct e1000_hw *hw = &adapter->hw;
1569         u32 ctrl_ext;
1570
1571         /* Let firmware take over control of h/w */
1572         ctrl_ext = rd32(E1000_CTRL_EXT);
1573         wr32(E1000_CTRL_EXT,
1574                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1575 }
1576
1577 /**
1578  *  igb_get_hw_control - get control of the h/w from f/w
1579  *  @adapter: address of board private structure
1580  *
1581  *  igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1582  *  For ASF and Pass Through versions of f/w this means that
1583  *  the driver is loaded.
1584  **/
1585 static void igb_get_hw_control(struct igb_adapter *adapter)
1586 {
1587         struct e1000_hw *hw = &adapter->hw;
1588         u32 ctrl_ext;
1589
1590         /* Let firmware know the driver has taken over */
1591         ctrl_ext = rd32(E1000_CTRL_EXT);
1592         wr32(E1000_CTRL_EXT,
1593                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1594 }
1595
1596 static void enable_fqtss(struct igb_adapter *adapter, bool enable)
1597 {
1598         struct net_device *netdev = adapter->netdev;
1599         struct e1000_hw *hw = &adapter->hw;
1600
1601         WARN_ON(hw->mac.type != e1000_i210);
1602
1603         if (enable)
1604                 adapter->flags |= IGB_FLAG_FQTSS;
1605         else
1606                 adapter->flags &= ~IGB_FLAG_FQTSS;
1607
1608         if (netif_running(netdev))
1609                 schedule_work(&adapter->reset_task);
1610 }
1611
1612 static bool is_fqtss_enabled(struct igb_adapter *adapter)
1613 {
1614         return (adapter->flags & IGB_FLAG_FQTSS) ? true : false;
1615 }
1616
1617 static void set_tx_desc_fetch_prio(struct e1000_hw *hw, int queue,
1618                                    enum tx_queue_prio prio)
1619 {
1620         u32 val;
1621
1622         WARN_ON(hw->mac.type != e1000_i210);
1623         WARN_ON(queue < 0 || queue > 4);
1624
1625         val = rd32(E1000_I210_TXDCTL(queue));
1626
1627         if (prio == TX_QUEUE_PRIO_HIGH)
1628                 val |= E1000_TXDCTL_PRIORITY;
1629         else
1630                 val &= ~E1000_TXDCTL_PRIORITY;
1631
1632         wr32(E1000_I210_TXDCTL(queue), val);
1633 }
1634
1635 static void set_queue_mode(struct e1000_hw *hw, int queue, enum queue_mode mode)
1636 {
1637         u32 val;
1638
1639         WARN_ON(hw->mac.type != e1000_i210);
1640         WARN_ON(queue < 0 || queue > 1);
1641
1642         val = rd32(E1000_I210_TQAVCC(queue));
1643
1644         if (mode == QUEUE_MODE_STREAM_RESERVATION)
1645                 val |= E1000_TQAVCC_QUEUEMODE;
1646         else
1647                 val &= ~E1000_TQAVCC_QUEUEMODE;
1648
1649         wr32(E1000_I210_TQAVCC(queue), val);
1650 }
1651
1652 static bool is_any_cbs_enabled(struct igb_adapter *adapter)
1653 {
1654         int i;
1655
1656         for (i = 0; i < adapter->num_tx_queues; i++) {
1657                 if (adapter->tx_ring[i]->cbs_enable)
1658                         return true;
1659         }
1660
1661         return false;
1662 }
1663
1664 static bool is_any_txtime_enabled(struct igb_adapter *adapter)
1665 {
1666         int i;
1667
1668         for (i = 0; i < adapter->num_tx_queues; i++) {
1669                 if (adapter->tx_ring[i]->launchtime_enable)
1670                         return true;
1671         }
1672
1673         return false;
1674 }
1675
1676 /**
1677  *  igb_config_tx_modes - Configure "Qav Tx mode" features on igb
1678  *  @adapter: pointer to adapter struct
1679  *  @queue: queue number
1680  *
1681  *  Configure CBS and Launchtime for a given hardware queue.
1682  *  Parameters are retrieved from the correct Tx ring, so
1683  *  igb_save_cbs_params() and igb_save_txtime_params() should be used
1684  *  for setting those correctly prior to this function being called.
1685  **/
1686 static void igb_config_tx_modes(struct igb_adapter *adapter, int queue)
1687 {
1688         struct igb_ring *ring = adapter->tx_ring[queue];
1689         struct net_device *netdev = adapter->netdev;
1690         struct e1000_hw *hw = &adapter->hw;
1691         u32 tqavcc, tqavctrl;
1692         u16 value;
1693
1694         WARN_ON(hw->mac.type != e1000_i210);
1695         WARN_ON(queue < 0 || queue > 1);
1696
1697         /* If any of the Qav features is enabled, configure queues as SR and
1698          * with HIGH PRIO. If none is, then configure them with LOW PRIO and
1699          * as SP.
1700          */
1701         if (ring->cbs_enable || ring->launchtime_enable) {
1702                 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_HIGH);
1703                 set_queue_mode(hw, queue, QUEUE_MODE_STREAM_RESERVATION);
1704         } else {
1705                 set_tx_desc_fetch_prio(hw, queue, TX_QUEUE_PRIO_LOW);
1706                 set_queue_mode(hw, queue, QUEUE_MODE_STRICT_PRIORITY);
1707         }
1708
1709         /* If CBS is enabled, set DataTranARB and config its parameters. */
1710         if (ring->cbs_enable || queue == 0) {
1711                 /* i210 does not allow the queue 0 to be in the Strict
1712                  * Priority mode while the Qav mode is enabled, so,
1713                  * instead of disabling strict priority mode, we give
1714                  * queue 0 the maximum of credits possible.
1715                  *
1716                  * See section 8.12.19 of the i210 datasheet, "Note:
1717                  * Queue0 QueueMode must be set to 1b when
1718                  * TransmitMode is set to Qav."
1719                  */
1720                 if (queue == 0 && !ring->cbs_enable) {
1721                         /* max "linkspeed" idleslope in kbps */
1722                         ring->idleslope = 1000000;
1723                         ring->hicredit = ETH_FRAME_LEN;
1724                 }
1725
1726                 /* Always set data transfer arbitration to credit-based
1727                  * shaper algorithm on TQAVCTRL if CBS is enabled for any of
1728                  * the queues.
1729                  */
1730                 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1731                 tqavctrl |= E1000_TQAVCTRL_DATATRANARB;
1732                 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1733
1734                 /* According to i210 datasheet section 7.2.7.7, we should set
1735                  * the 'idleSlope' field from TQAVCC register following the
1736                  * equation:
1737                  *
1738                  * For 100 Mbps link speed:
1739                  *
1740                  *     value = BW * 0x7735 * 0.2                          (E1)
1741                  *
1742                  * For 1000Mbps link speed:
1743                  *
1744                  *     value = BW * 0x7735 * 2                            (E2)
1745                  *
1746                  * E1 and E2 can be merged into one equation as shown below.
1747                  * Note that 'link-speed' is in Mbps.
1748                  *
1749                  *     value = BW * 0x7735 * 2 * link-speed
1750                  *                           --------------               (E3)
1751                  *                                1000
1752                  *
1753                  * 'BW' is the percentage bandwidth out of full link speed
1754                  * which can be found with the following equation. Note that
1755                  * idleSlope here is the parameter from this function which
1756                  * is in kbps.
1757                  *
1758                  *     BW =     idleSlope
1759                  *          -----------------                             (E4)
1760                  *          link-speed * 1000
1761                  *
1762                  * That said, we can come up with a generic equation to
1763                  * calculate the value we should set it TQAVCC register by
1764                  * replacing 'BW' in E3 by E4. The resulting equation is:
1765                  *
1766                  * value =     idleSlope     * 0x7735 * 2 * link-speed
1767                  *         -----------------            --------------    (E5)
1768                  *         link-speed * 1000                 1000
1769                  *
1770                  * 'link-speed' is present in both sides of the fraction so
1771                  * it is canceled out. The final equation is the following:
1772                  *
1773                  *     value = idleSlope * 61034
1774                  *             -----------------                          (E6)
1775                  *                  1000000
1776                  *
1777                  * NOTE: For i210, given the above, we can see that idleslope
1778                  *       is represented in 16.38431 kbps units by the value at
1779                  *       the TQAVCC register (1Gbps / 61034), which reduces
1780                  *       the granularity for idleslope increments.
1781                  *       For instance, if you want to configure a 2576kbps
1782                  *       idleslope, the value to be written on the register
1783                  *       would have to be 157.23. If rounded down, you end
1784                  *       up with less bandwidth available than originally
1785                  *       required (~2572 kbps). If rounded up, you end up
1786                  *       with a higher bandwidth (~2589 kbps). Below the
1787                  *       approach we take is to always round up the
1788                  *       calculated value, so the resulting bandwidth might
1789                  *       be slightly higher for some configurations.
1790                  */
1791                 value = DIV_ROUND_UP_ULL(ring->idleslope * 61034ULL, 1000000);
1792
1793                 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1794                 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1795                 tqavcc |= value;
1796                 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1797
1798                 wr32(E1000_I210_TQAVHC(queue),
1799                      0x80000000 + ring->hicredit * 0x7735);
1800         } else {
1801
1802                 /* Set idleSlope to zero. */
1803                 tqavcc = rd32(E1000_I210_TQAVCC(queue));
1804                 tqavcc &= ~E1000_TQAVCC_IDLESLOPE_MASK;
1805                 wr32(E1000_I210_TQAVCC(queue), tqavcc);
1806
1807                 /* Set hiCredit to zero. */
1808                 wr32(E1000_I210_TQAVHC(queue), 0);
1809
1810                 /* If CBS is not enabled for any queues anymore, then return to
1811                  * the default state of Data Transmission Arbitration on
1812                  * TQAVCTRL.
1813                  */
1814                 if (!is_any_cbs_enabled(adapter)) {
1815                         tqavctrl = rd32(E1000_I210_TQAVCTRL);
1816                         tqavctrl &= ~E1000_TQAVCTRL_DATATRANARB;
1817                         wr32(E1000_I210_TQAVCTRL, tqavctrl);
1818                 }
1819         }
1820
1821         /* If LaunchTime is enabled, set DataTranTIM. */
1822         if (ring->launchtime_enable) {
1823                 /* Always set DataTranTIM on TQAVCTRL if LaunchTime is enabled
1824                  * for any of the SR queues, and configure fetchtime delta.
1825                  * XXX NOTE:
1826                  *     - LaunchTime will be enabled for all SR queues.
1827                  *     - A fixed offset can be added relative to the launch
1828                  *       time of all packets if configured at reg LAUNCH_OS0.
1829                  *       We are keeping it as 0 for now (default value).
1830                  */
1831                 tqavctrl = rd32(E1000_I210_TQAVCTRL);
1832                 tqavctrl |= E1000_TQAVCTRL_DATATRANTIM |
1833                        E1000_TQAVCTRL_FETCHTIME_DELTA;
1834                 wr32(E1000_I210_TQAVCTRL, tqavctrl);
1835         } else {
1836                 /* If Launchtime is not enabled for any SR queues anymore,
1837                  * then clear DataTranTIM on TQAVCTRL and clear fetchtime delta,
1838                  * effectively disabling Launchtime.
1839                  */
1840                 if (!is_any_txtime_enabled(adapter)) {
1841                         tqavctrl = rd32(E1000_I210_TQAVCTRL);
1842                         tqavctrl &= ~E1000_TQAVCTRL_DATATRANTIM;
1843                         tqavctrl &= ~E1000_TQAVCTRL_FETCHTIME_DELTA;
1844                         wr32(E1000_I210_TQAVCTRL, tqavctrl);
1845                 }
1846         }
1847
1848         /* XXX: In i210 controller the sendSlope and loCredit parameters from
1849          * CBS are not configurable by software so we don't do any 'controller
1850          * configuration' in respect to these parameters.
1851          */
1852
1853         netdev_dbg(netdev, "Qav Tx mode: cbs %s, launchtime %s, queue %d idleslope %d sendslope %d hiCredit %d locredit %d\n",
1854                    ring->cbs_enable ? "enabled" : "disabled",
1855                    ring->launchtime_enable ? "enabled" : "disabled",
1856                    queue,
1857                    ring->idleslope, ring->sendslope,
1858                    ring->hicredit, ring->locredit);
1859 }
1860
1861 static int igb_save_txtime_params(struct igb_adapter *adapter, int queue,
1862                                   bool enable)
1863 {
1864         struct igb_ring *ring;
1865
1866         if (queue < 0 || queue > adapter->num_tx_queues)
1867                 return -EINVAL;
1868
1869         ring = adapter->tx_ring[queue];
1870         ring->launchtime_enable = enable;
1871
1872         return 0;
1873 }
1874
1875 static int igb_save_cbs_params(struct igb_adapter *adapter, int queue,
1876                                bool enable, int idleslope, int sendslope,
1877                                int hicredit, int locredit)
1878 {
1879         struct igb_ring *ring;
1880
1881         if (queue < 0 || queue > adapter->num_tx_queues)
1882                 return -EINVAL;
1883
1884         ring = adapter->tx_ring[queue];
1885
1886         ring->cbs_enable = enable;
1887         ring->idleslope = idleslope;
1888         ring->sendslope = sendslope;
1889         ring->hicredit = hicredit;
1890         ring->locredit = locredit;
1891
1892         return 0;
1893 }
1894
1895 /**
1896  *  igb_setup_tx_mode - Switch to/from Qav Tx mode when applicable
1897  *  @adapter: pointer to adapter struct
1898  *
1899  *  Configure TQAVCTRL register switching the controller's Tx mode
1900  *  if FQTSS mode is enabled or disabled. Additionally, will issue
1901  *  a call to igb_config_tx_modes() per queue so any previously saved
1902  *  Tx parameters are applied.
1903  **/
1904 static void igb_setup_tx_mode(struct igb_adapter *adapter)
1905 {
1906         struct net_device *netdev = adapter->netdev;
1907         struct e1000_hw *hw = &adapter->hw;
1908         u32 val;
1909
1910         /* Only i210 controller supports changing the transmission mode. */
1911         if (hw->mac.type != e1000_i210)
1912                 return;
1913
1914         if (is_fqtss_enabled(adapter)) {
1915                 int i, max_queue;
1916
1917                 /* Configure TQAVCTRL register: set transmit mode to 'Qav',
1918                  * set data fetch arbitration to 'round robin', set SP_WAIT_SR
1919                  * so SP queues wait for SR ones.
1920                  */
1921                 val = rd32(E1000_I210_TQAVCTRL);
1922                 val |= E1000_TQAVCTRL_XMIT_MODE | E1000_TQAVCTRL_SP_WAIT_SR;
1923                 val &= ~E1000_TQAVCTRL_DATAFETCHARB;
1924                 wr32(E1000_I210_TQAVCTRL, val);
1925
1926                 /* Configure Tx and Rx packet buffers sizes as described in
1927                  * i210 datasheet section 7.2.7.7.
1928                  */
1929                 val = rd32(E1000_TXPBS);
1930                 val &= ~I210_TXPBSIZE_MASK;
1931                 val |= I210_TXPBSIZE_PB0_8KB | I210_TXPBSIZE_PB1_8KB |
1932                         I210_TXPBSIZE_PB2_4KB | I210_TXPBSIZE_PB3_4KB;
1933                 wr32(E1000_TXPBS, val);
1934
1935                 val = rd32(E1000_RXPBS);
1936                 val &= ~I210_RXPBSIZE_MASK;
1937                 val |= I210_RXPBSIZE_PB_30KB;
1938                 wr32(E1000_RXPBS, val);
1939
1940                 /* Section 8.12.9 states that MAX_TPKT_SIZE from DTXMXPKTSZ
1941                  * register should not exceed the buffer size programmed in
1942                  * TXPBS. The smallest buffer size programmed in TXPBS is 4kB
1943                  * so according to the datasheet we should set MAX_TPKT_SIZE to
1944                  * 4kB / 64.
1945                  *
1946                  * However, when we do so, no frame from queue 2 and 3 are
1947                  * transmitted.  It seems the MAX_TPKT_SIZE should not be great
1948                  * or _equal_ to the buffer size programmed in TXPBS. For this
1949                  * reason, we set set MAX_ TPKT_SIZE to (4kB - 1) / 64.
1950                  */
1951                 val = (4096 - 1) / 64;
1952                 wr32(E1000_I210_DTXMXPKTSZ, val);
1953
1954                 /* Since FQTSS mode is enabled, apply any CBS configuration
1955                  * previously set. If no previous CBS configuration has been
1956                  * done, then the initial configuration is applied, which means
1957                  * CBS is disabled.
1958                  */
1959                 max_queue = (adapter->num_tx_queues < I210_SR_QUEUES_NUM) ?
1960                             adapter->num_tx_queues : I210_SR_QUEUES_NUM;
1961
1962                 for (i = 0; i < max_queue; i++) {
1963                         igb_config_tx_modes(adapter, i);
1964                 }
1965         } else {
1966                 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
1967                 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
1968                 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT);
1969
1970                 val = rd32(E1000_I210_TQAVCTRL);
1971                 /* According to Section 8.12.21, the other flags we've set when
1972                  * enabling FQTSS are not relevant when disabling FQTSS so we
1973                  * don't set they here.
1974                  */
1975                 val &= ~E1000_TQAVCTRL_XMIT_MODE;
1976                 wr32(E1000_I210_TQAVCTRL, val);
1977         }
1978
1979         netdev_dbg(netdev, "FQTSS %s\n", (is_fqtss_enabled(adapter)) ?
1980                    "enabled" : "disabled");
1981 }
1982
1983 /**
1984  *  igb_configure - configure the hardware for RX and TX
1985  *  @adapter: private board structure
1986  **/
1987 static void igb_configure(struct igb_adapter *adapter)
1988 {
1989         struct net_device *netdev = adapter->netdev;
1990         int i;
1991
1992         igb_get_hw_control(adapter);
1993         igb_set_rx_mode(netdev);
1994         igb_setup_tx_mode(adapter);
1995
1996         igb_restore_vlan(adapter);
1997
1998         igb_setup_tctl(adapter);
1999         igb_setup_mrqc(adapter);
2000         igb_setup_rctl(adapter);
2001
2002         igb_nfc_filter_restore(adapter);
2003         igb_configure_tx(adapter);
2004         igb_configure_rx(adapter);
2005
2006         igb_rx_fifo_flush_82575(&adapter->hw);
2007
2008         /* call igb_desc_unused which always leaves
2009          * at least 1 descriptor unused to make sure
2010          * next_to_use != next_to_clean
2011          */
2012         for (i = 0; i < adapter->num_rx_queues; i++) {
2013                 struct igb_ring *ring = adapter->rx_ring[i];
2014                 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
2015         }
2016 }
2017
2018 /**
2019  *  igb_power_up_link - Power up the phy/serdes link
2020  *  @adapter: address of board private structure
2021  **/
2022 void igb_power_up_link(struct igb_adapter *adapter)
2023 {
2024         igb_reset_phy(&adapter->hw);
2025
2026         if (adapter->hw.phy.media_type == e1000_media_type_copper)
2027                 igb_power_up_phy_copper(&adapter->hw);
2028         else
2029                 igb_power_up_serdes_link_82575(&adapter->hw);
2030
2031         igb_setup_link(&adapter->hw);
2032 }
2033
2034 /**
2035  *  igb_power_down_link - Power down the phy/serdes link
2036  *  @adapter: address of board private structure
2037  */
2038 static void igb_power_down_link(struct igb_adapter *adapter)
2039 {
2040         if (adapter->hw.phy.media_type == e1000_media_type_copper)
2041                 igb_power_down_phy_copper_82575(&adapter->hw);
2042         else
2043                 igb_shutdown_serdes_link_82575(&adapter->hw);
2044 }
2045
2046 /**
2047  * Detect and switch function for Media Auto Sense
2048  * @adapter: address of the board private structure
2049  **/
2050 static void igb_check_swap_media(struct igb_adapter *adapter)
2051 {
2052         struct e1000_hw *hw = &adapter->hw;
2053         u32 ctrl_ext, connsw;
2054         bool swap_now = false;
2055
2056         ctrl_ext = rd32(E1000_CTRL_EXT);
2057         connsw = rd32(E1000_CONNSW);
2058
2059         /* need to live swap if current media is copper and we have fiber/serdes
2060          * to go to.
2061          */
2062
2063         if ((hw->phy.media_type == e1000_media_type_copper) &&
2064             (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) {
2065                 swap_now = true;
2066         } else if (!(connsw & E1000_CONNSW_SERDESD)) {
2067                 /* copper signal takes time to appear */
2068                 if (adapter->copper_tries < 4) {
2069                         adapter->copper_tries++;
2070                         connsw |= E1000_CONNSW_AUTOSENSE_CONF;
2071                         wr32(E1000_CONNSW, connsw);
2072                         return;
2073                 } else {
2074                         adapter->copper_tries = 0;
2075                         if ((connsw & E1000_CONNSW_PHYSD) &&
2076                             (!(connsw & E1000_CONNSW_PHY_PDN))) {
2077                                 swap_now = true;
2078                                 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF;
2079                                 wr32(E1000_CONNSW, connsw);
2080                         }
2081                 }
2082         }
2083
2084         if (!swap_now)
2085                 return;
2086
2087         switch (hw->phy.media_type) {
2088         case e1000_media_type_copper:
2089                 netdev_info(adapter->netdev,
2090                         "MAS: changing media to fiber/serdes\n");
2091                 ctrl_ext |=
2092                         E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2093                 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2094                 adapter->copper_tries = 0;
2095                 break;
2096         case e1000_media_type_internal_serdes:
2097         case e1000_media_type_fiber:
2098                 netdev_info(adapter->netdev,
2099                         "MAS: changing media to copper\n");
2100                 ctrl_ext &=
2101                         ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
2102                 adapter->flags |= IGB_FLAG_MEDIA_RESET;
2103                 break;
2104         default:
2105                 /* shouldn't get here during regular operation */
2106                 netdev_err(adapter->netdev,
2107                         "AMS: Invalid media type found, returning\n");
2108                 break;
2109         }
2110         wr32(E1000_CTRL_EXT, ctrl_ext);
2111 }
2112
2113 /**
2114  *  igb_up - Open the interface and prepare it to handle traffic
2115  *  @adapter: board private structure
2116  **/
2117 int igb_up(struct igb_adapter *adapter)
2118 {
2119         struct e1000_hw *hw = &adapter->hw;
2120         int i;
2121
2122         /* hardware has been reset, we need to reload some things */
2123         igb_configure(adapter);
2124
2125         clear_bit(__IGB_DOWN, &adapter->state);
2126
2127         for (i = 0; i < adapter->num_q_vectors; i++)
2128                 napi_enable(&(adapter->q_vector[i]->napi));
2129
2130         if (adapter->flags & IGB_FLAG_HAS_MSIX)
2131                 igb_configure_msix(adapter);
2132         else
2133                 igb_assign_vector(adapter->q_vector[0], 0);
2134
2135         /* Clear any pending interrupts. */
2136         rd32(E1000_TSICR);
2137         rd32(E1000_ICR);
2138         igb_irq_enable(adapter);
2139
2140         /* notify VFs that reset has been completed */
2141         if (adapter->vfs_allocated_count) {
2142                 u32 reg_data = rd32(E1000_CTRL_EXT);
2143
2144                 reg_data |= E1000_CTRL_EXT_PFRSTD;
2145                 wr32(E1000_CTRL_EXT, reg_data);
2146         }
2147
2148         netif_tx_start_all_queues(adapter->netdev);
2149
2150         /* start the watchdog. */
2151         hw->mac.get_link_status = 1;
2152         schedule_work(&adapter->watchdog_task);
2153
2154         if ((adapter->flags & IGB_FLAG_EEE) &&
2155             (!hw->dev_spec._82575.eee_disable))
2156                 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
2157
2158         return 0;
2159 }
2160
2161 void igb_down(struct igb_adapter *adapter)
2162 {
2163         struct net_device *netdev = adapter->netdev;
2164         struct e1000_hw *hw = &adapter->hw;
2165         u32 tctl, rctl;
2166         int i;
2167
2168         /* signal that we're down so the interrupt handler does not
2169          * reschedule our watchdog timer
2170          */
2171         set_bit(__IGB_DOWN, &adapter->state);
2172
2173         /* disable receives in the hardware */
2174         rctl = rd32(E1000_RCTL);
2175         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
2176         /* flush and sleep below */
2177
2178         igb_nfc_filter_exit(adapter);
2179
2180         netif_carrier_off(netdev);
2181         netif_tx_stop_all_queues(netdev);
2182
2183         /* disable transmits in the hardware */
2184         tctl = rd32(E1000_TCTL);
2185         tctl &= ~E1000_TCTL_EN;
2186         wr32(E1000_TCTL, tctl);
2187         /* flush both disables and wait for them to finish */
2188         wrfl();
2189         usleep_range(10000, 11000);
2190
2191         igb_irq_disable(adapter);
2192
2193         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
2194
2195         for (i = 0; i < adapter->num_q_vectors; i++) {
2196                 if (adapter->q_vector[i]) {
2197                         napi_synchronize(&adapter->q_vector[i]->napi);
2198                         napi_disable(&adapter->q_vector[i]->napi);
2199                 }
2200         }
2201
2202         del_timer_sync(&adapter->watchdog_timer);
2203         del_timer_sync(&adapter->phy_info_timer);
2204
2205         /* record the stats before reset*/
2206         spin_lock(&adapter->stats64_lock);
2207         igb_update_stats(adapter);
2208         spin_unlock(&adapter->stats64_lock);
2209
2210         adapter->link_speed = 0;
2211         adapter->link_duplex = 0;
2212
2213         if (!pci_channel_offline(adapter->pdev))
2214                 igb_reset(adapter);
2215
2216         /* clear VLAN promisc flag so VFTA will be updated if necessary */
2217         adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
2218
2219         igb_clean_all_tx_rings(adapter);
2220         igb_clean_all_rx_rings(adapter);
2221 #ifdef CONFIG_IGB_DCA
2222
2223         /* since we reset the hardware DCA settings were cleared */
2224         igb_setup_dca(adapter);
2225 #endif
2226 }
2227
2228 void igb_reinit_locked(struct igb_adapter *adapter)
2229 {
2230         WARN_ON(in_interrupt());
2231         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2232                 usleep_range(1000, 2000);
2233         igb_down(adapter);
2234         igb_up(adapter);
2235         clear_bit(__IGB_RESETTING, &adapter->state);
2236 }
2237
2238 /** igb_enable_mas - Media Autosense re-enable after swap
2239  *
2240  * @adapter: adapter struct
2241  **/
2242 static void igb_enable_mas(struct igb_adapter *adapter)
2243 {
2244         struct e1000_hw *hw = &adapter->hw;
2245         u32 connsw = rd32(E1000_CONNSW);
2246
2247         /* configure for SerDes media detect */
2248         if ((hw->phy.media_type == e1000_media_type_copper) &&
2249             (!(connsw & E1000_CONNSW_SERDESD))) {
2250                 connsw |= E1000_CONNSW_ENRGSRC;
2251                 connsw |= E1000_CONNSW_AUTOSENSE_EN;
2252                 wr32(E1000_CONNSW, connsw);
2253                 wrfl();
2254         }
2255 }
2256
2257 void igb_reset(struct igb_adapter *adapter)
2258 {
2259         struct pci_dev *pdev = adapter->pdev;
2260         struct e1000_hw *hw = &adapter->hw;
2261         struct e1000_mac_info *mac = &hw->mac;
2262         struct e1000_fc_info *fc = &hw->fc;
2263         u32 pba, hwm;
2264
2265         /* Repartition Pba for greater than 9k mtu
2266          * To take effect CTRL.RST is required.
2267          */
2268         switch (mac->type) {
2269         case e1000_i350:
2270         case e1000_i354:
2271         case e1000_82580:
2272                 pba = rd32(E1000_RXPBS);
2273                 pba = igb_rxpbs_adjust_82580(pba);
2274                 break;
2275         case e1000_82576:
2276                 pba = rd32(E1000_RXPBS);
2277                 pba &= E1000_RXPBS_SIZE_MASK_82576;
2278                 break;
2279         case e1000_82575:
2280         case e1000_i210:
2281         case e1000_i211:
2282         default:
2283                 pba = E1000_PBA_34K;
2284                 break;
2285         }
2286
2287         if (mac->type == e1000_82575) {
2288                 u32 min_rx_space, min_tx_space, needed_tx_space;
2289
2290                 /* write Rx PBA so that hardware can report correct Tx PBA */
2291                 wr32(E1000_PBA, pba);
2292
2293                 /* To maintain wire speed transmits, the Tx FIFO should be
2294                  * large enough to accommodate two full transmit packets,
2295                  * rounded up to the next 1KB and expressed in KB.  Likewise,
2296                  * the Rx FIFO should be large enough to accommodate at least
2297                  * one full receive packet and is similarly rounded up and
2298                  * expressed in KB.
2299                  */
2300                 min_rx_space = DIV_ROUND_UP(MAX_JUMBO_FRAME_SIZE, 1024);
2301
2302                 /* The Tx FIFO also stores 16 bytes of information about the Tx
2303                  * but don't include Ethernet FCS because hardware appends it.
2304                  * We only need to round down to the nearest 512 byte block
2305                  * count since the value we care about is 2 frames, not 1.
2306                  */
2307                 min_tx_space = adapter->max_frame_size;
2308                 min_tx_space += sizeof(union e1000_adv_tx_desc) - ETH_FCS_LEN;
2309                 min_tx_space = DIV_ROUND_UP(min_tx_space, 512);
2310
2311                 /* upper 16 bits has Tx packet buffer allocation size in KB */
2312                 needed_tx_space = min_tx_space - (rd32(E1000_PBA) >> 16);
2313
2314                 /* If current Tx allocation is less than the min Tx FIFO size,
2315                  * and the min Tx FIFO size is less than the current Rx FIFO
2316                  * allocation, take space away from current Rx allocation.
2317                  */
2318                 if (needed_tx_space < pba) {
2319                         pba -= needed_tx_space;
2320
2321                         /* if short on Rx space, Rx wins and must trump Tx
2322                          * adjustment
2323                          */
2324                         if (pba < min_rx_space)
2325                                 pba = min_rx_space;
2326                 }
2327
2328                 /* adjust PBA for jumbo frames */
2329                 wr32(E1000_PBA, pba);
2330         }
2331
2332         /* flow control settings
2333          * The high water mark must be low enough to fit one full frame
2334          * after transmitting the pause frame.  As such we must have enough
2335          * space to allow for us to complete our current transmit and then
2336          * receive the frame that is in progress from the link partner.
2337          * Set it to:
2338          * - the full Rx FIFO size minus one full Tx plus one full Rx frame
2339          */
2340         hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);
2341
2342         fc->high_water = hwm & 0xFFFFFFF0;      /* 16-byte granularity */
2343         fc->low_water = fc->high_water - 16;
2344         fc->pause_time = 0xFFFF;
2345         fc->send_xon = 1;
2346         fc->current_mode = fc->requested_mode;
2347
2348         /* disable receive for all VFs and wait one second */
2349         if (adapter->vfs_allocated_count) {
2350                 int i;
2351
2352                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
2353                         adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
2354
2355                 /* ping all the active vfs to let them know we are going down */
2356                 igb_ping_all_vfs(adapter);
2357
2358                 /* disable transmits and receives */
2359                 wr32(E1000_VFRE, 0);
2360                 wr32(E1000_VFTE, 0);
2361         }
2362
2363         /* Allow time for pending master requests to run */
2364         hw->mac.ops.reset_hw(hw);
2365         wr32(E1000_WUC, 0);
2366
2367         if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
2368                 /* need to resetup here after media swap */
2369                 adapter->ei.get_invariants(hw);
2370                 adapter->flags &= ~IGB_FLAG_MEDIA_RESET;
2371         }
2372         if ((mac->type == e1000_82575) &&
2373             (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
2374                 igb_enable_mas(adapter);
2375         }
2376         if (hw->mac.ops.init_hw(hw))
2377                 dev_err(&pdev->dev, "Hardware Error\n");
2378
2379         /* RAR registers were cleared during init_hw, clear mac table */
2380         igb_flush_mac_table(adapter);
2381         __dev_uc_unsync(adapter->netdev, NULL);
2382
2383         /* Recover default RAR entry */
2384         igb_set_default_mac_filter(adapter);
2385
2386         /* Flow control settings reset on hardware reset, so guarantee flow
2387          * control is off when forcing speed.
2388          */
2389         if (!hw->mac.autoneg)
2390                 igb_force_mac_fc(hw);
2391
2392         igb_init_dmac(adapter, pba);
2393 #ifdef CONFIG_IGB_HWMON
2394         /* Re-initialize the thermal sensor on i350 devices. */
2395         if (!test_bit(__IGB_DOWN, &adapter->state)) {
2396                 if (mac->type == e1000_i350 && hw->bus.func == 0) {
2397                         /* If present, re-initialize the external thermal sensor
2398                          * interface.
2399                          */
2400                         if (adapter->ets)
2401                                 mac->ops.init_thermal_sensor_thresh(hw);
2402                 }
2403         }
2404 #endif
2405         /* Re-establish EEE setting */
2406         if (hw->phy.media_type == e1000_media_type_copper) {
2407                 switch (mac->type) {
2408                 case e1000_i350:
2409                 case e1000_i210:
2410                 case e1000_i211:
2411                         igb_set_eee_i350(hw, true, true);
2412                         break;
2413                 case e1000_i354:
2414                         igb_set_eee_i354(hw, true, true);
2415                         break;
2416                 default:
2417                         break;
2418                 }
2419         }
2420         if (!netif_running(adapter->netdev))
2421                 igb_power_down_link(adapter);
2422
2423         igb_update_mng_vlan(adapter);
2424
2425         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2426         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
2427
2428         /* Re-enable PTP, where applicable. */
2429         if (adapter->ptp_flags & IGB_PTP_ENABLED)
2430                 igb_ptp_reset(adapter);
2431
2432         igb_get_phy_info(hw);
2433 }
2434
2435 static netdev_features_t igb_fix_features(struct net_device *netdev,
2436         netdev_features_t features)
2437 {
2438         /* Since there is no support for separate Rx/Tx vlan accel
2439          * enable/disable make sure Tx flag is always in same state as Rx.
2440          */
2441         if (features & NETIF_F_HW_VLAN_CTAG_RX)
2442                 features |= NETIF_F_HW_VLAN_CTAG_TX;
2443         else
2444                 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
2445
2446         return features;
2447 }
2448
2449 static int igb_set_features(struct net_device *netdev,
2450         netdev_features_t features)
2451 {
2452         netdev_features_t changed = netdev->features ^ features;
2453         struct igb_adapter *adapter = netdev_priv(netdev);
2454
2455         if (changed & NETIF_F_HW_VLAN_CTAG_RX)
2456                 igb_vlan_mode(netdev, features);
2457
2458         if (!(changed & (NETIF_F_RXALL | NETIF_F_NTUPLE)))
2459                 return 0;
2460
2461         if (!(features & NETIF_F_NTUPLE)) {
2462                 struct hlist_node *node2;
2463                 struct igb_nfc_filter *rule;
2464
2465                 spin_lock(&adapter->nfc_lock);
2466                 hlist_for_each_entry_safe(rule, node2,
2467                                           &adapter->nfc_filter_list, nfc_node) {
2468                         igb_erase_filter(adapter, rule);
2469                         hlist_del(&rule->nfc_node);
2470                         kfree(rule);
2471                 }
2472                 spin_unlock(&adapter->nfc_lock);
2473                 adapter->nfc_filter_count = 0;
2474         }
2475
2476         netdev->features = features;
2477
2478         if (netif_running(netdev))
2479                 igb_reinit_locked(adapter);
2480         else
2481                 igb_reset(adapter);
2482
2483         return 1;
2484 }
2485
2486 static int igb_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
2487                            struct net_device *dev,
2488                            const unsigned char *addr, u16 vid,
2489                            u16 flags,
2490                            struct netlink_ext_ack *extack)
2491 {
2492         /* guarantee we can provide a unique filter for the unicast address */
2493         if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2494                 struct igb_adapter *adapter = netdev_priv(dev);
2495                 int vfn = adapter->vfs_allocated_count;
2496
2497                 if (netdev_uc_count(dev) >= igb_available_rars(adapter, vfn))
2498                         return -ENOMEM;
2499         }
2500
2501         return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
2502 }
2503
2504 #define IGB_MAX_MAC_HDR_LEN     127
2505 #define IGB_MAX_NETWORK_HDR_LEN 511
2506
2507 static netdev_features_t
2508 igb_features_check(struct sk_buff *skb, struct net_device *dev,
2509                    netdev_features_t features)
2510 {
2511         unsigned int network_hdr_len, mac_hdr_len;
2512
2513         /* Make certain the headers can be described by a context descriptor */
2514         mac_hdr_len = skb_network_header(skb) - skb->data;
2515         if (unlikely(mac_hdr_len > IGB_MAX_MAC_HDR_LEN))
2516                 return features & ~(NETIF_F_HW_CSUM |
2517                                     NETIF_F_SCTP_CRC |
2518                                     NETIF_F_HW_VLAN_CTAG_TX |
2519                                     NETIF_F_TSO |
2520                                     NETIF_F_TSO6);
2521
2522         network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
2523         if (unlikely(network_hdr_len >  IGB_MAX_NETWORK_HDR_LEN))
2524                 return features & ~(NETIF_F_HW_CSUM |
2525                                     NETIF_F_SCTP_CRC |
2526                                     NETIF_F_TSO |
2527                                     NETIF_F_TSO6);
2528
2529         /* We can only support IPV4 TSO in tunnels if we can mangle the
2530          * inner IP ID field, so strip TSO if MANGLEID is not supported.
2531          */
2532         if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID))
2533                 features &= ~NETIF_F_TSO;
2534
2535         return features;
2536 }
2537
2538 static void igb_offload_apply(struct igb_adapter *adapter, s32 queue)
2539 {
2540         if (!is_fqtss_enabled(adapter)) {
2541                 enable_fqtss(adapter, true);
2542                 return;
2543         }
2544
2545         igb_config_tx_modes(adapter, queue);
2546
2547         if (!is_any_cbs_enabled(adapter) && !is_any_txtime_enabled(adapter))
2548                 enable_fqtss(adapter, false);
2549 }
2550
2551 static int igb_offload_cbs(struct igb_adapter *adapter,
2552                            struct tc_cbs_qopt_offload *qopt)
2553 {
2554         struct e1000_hw *hw = &adapter->hw;
2555         int err;
2556
2557         /* CBS offloading is only supported by i210 controller. */
2558         if (hw->mac.type != e1000_i210)
2559                 return -EOPNOTSUPP;
2560
2561         /* CBS offloading is only supported by queue 0 and queue 1. */
2562         if (qopt->queue < 0 || qopt->queue > 1)
2563                 return -EINVAL;
2564
2565         err = igb_save_cbs_params(adapter, qopt->queue, qopt->enable,
2566                                   qopt->idleslope, qopt->sendslope,
2567                                   qopt->hicredit, qopt->locredit);
2568         if (err)
2569                 return err;
2570
2571         igb_offload_apply(adapter, qopt->queue);
2572
2573         return 0;
2574 }
2575
2576 #define ETHER_TYPE_FULL_MASK ((__force __be16)~0)
2577 #define VLAN_PRIO_FULL_MASK (0x07)
2578
2579 static int igb_parse_cls_flower(struct igb_adapter *adapter,
2580                                 struct tc_cls_flower_offload *f,
2581                                 int traffic_class,
2582                                 struct igb_nfc_filter *input)
2583 {
2584         struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f);
2585         struct flow_dissector *dissector = rule->match.dissector;
2586         struct netlink_ext_ack *extack = f->common.extack;
2587
2588         if (dissector->used_keys &
2589             ~(BIT(FLOW_DISSECTOR_KEY_BASIC) |
2590               BIT(FLOW_DISSECTOR_KEY_CONTROL) |
2591               BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2592               BIT(FLOW_DISSECTOR_KEY_VLAN))) {
2593                 NL_SET_ERR_MSG_MOD(extack,
2594                                    "Unsupported key used, only BASIC, CONTROL, ETH_ADDRS and VLAN are supported");
2595                 return -EOPNOTSUPP;
2596         }
2597
2598         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2599                 struct flow_match_eth_addrs match;
2600
2601                 flow_rule_match_eth_addrs(rule, &match);
2602                 if (!is_zero_ether_addr(match.mask->dst)) {
2603                         if (!is_broadcast_ether_addr(match.mask->dst)) {
2604                                 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for destination MAC address");
2605                                 return -EINVAL;
2606                         }
2607
2608                         input->filter.match_flags |=
2609                                 IGB_FILTER_FLAG_DST_MAC_ADDR;
2610                         ether_addr_copy(input->filter.dst_addr, match.key->dst);
2611                 }
2612
2613                 if (!is_zero_ether_addr(match.mask->src)) {
2614                         if (!is_broadcast_ether_addr(match.mask->src)) {
2615                                 NL_SET_ERR_MSG_MOD(extack, "Only full masks are supported for source MAC address");
2616                                 return -EINVAL;
2617                         }
2618
2619                         input->filter.match_flags |=
2620                                 IGB_FILTER_FLAG_SRC_MAC_ADDR;
2621                         ether_addr_copy(input->filter.src_addr, match.key->src);
2622                 }
2623         }
2624
2625         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2626                 struct flow_match_basic match;
2627
2628                 flow_rule_match_basic(rule, &match);
2629                 if (match.mask->n_proto) {
2630                         if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) {
2631                                 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for EtherType filter");
2632                                 return -EINVAL;
2633                         }
2634
2635                         input->filter.match_flags |= IGB_FILTER_FLAG_ETHER_TYPE;
2636                         input->filter.etype = match.key->n_proto;
2637                 }
2638         }
2639
2640         if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) {
2641                 struct flow_match_vlan match;
2642
2643                 flow_rule_match_vlan(rule, &match);
2644                 if (match.mask->vlan_priority) {
2645                         if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) {
2646                                 NL_SET_ERR_MSG_MOD(extack, "Only full mask is supported for VLAN priority");
2647                                 return -EINVAL;
2648                         }
2649
2650                         input->filter.match_flags |= IGB_FILTER_FLAG_VLAN_TCI;
2651                         input->filter.vlan_tci = match.key->vlan_priority;
2652                 }
2653         }
2654
2655         input->action = traffic_class;
2656         input->cookie = f->cookie;
2657
2658         return 0;
2659 }
2660
2661 static int igb_configure_clsflower(struct igb_adapter *adapter,
2662                                    struct tc_cls_flower_offload *cls_flower)
2663 {
2664         struct netlink_ext_ack *extack = cls_flower->common.extack;
2665         struct igb_nfc_filter *filter, *f;
2666         int err, tc;
2667
2668         tc = tc_classid_to_hwtc(adapter->netdev, cls_flower->classid);
2669         if (tc < 0) {
2670                 NL_SET_ERR_MSG_MOD(extack, "Invalid traffic class");
2671                 return -EINVAL;
2672         }
2673
2674         filter = kzalloc(sizeof(*filter), GFP_KERNEL);
2675         if (!filter)
2676                 return -ENOMEM;
2677
2678         err = igb_parse_cls_flower(adapter, cls_flower, tc, filter);
2679         if (err < 0)
2680                 goto err_parse;
2681
2682         spin_lock(&adapter->nfc_lock);
2683
2684         hlist_for_each_entry(f, &adapter->nfc_filter_list, nfc_node) {
2685                 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2686                         err = -EEXIST;
2687                         NL_SET_ERR_MSG_MOD(extack,
2688                                            "This filter is already set in ethtool");
2689                         goto err_locked;
2690                 }
2691         }
2692
2693         hlist_for_each_entry(f, &adapter->cls_flower_list, nfc_node) {
2694                 if (!memcmp(&f->filter, &filter->filter, sizeof(f->filter))) {
2695                         err = -EEXIST;
2696                         NL_SET_ERR_MSG_MOD(extack,
2697                                            "This filter is already set in cls_flower");
2698                         goto err_locked;
2699                 }
2700         }
2701
2702         err = igb_add_filter(adapter, filter);
2703         if (err < 0) {
2704                 NL_SET_ERR_MSG_MOD(extack, "Could not add filter to the adapter");
2705                 goto err_locked;
2706         }
2707
2708         hlist_add_head(&filter->nfc_node, &adapter->cls_flower_list);
2709
2710         spin_unlock(&adapter->nfc_lock);
2711
2712         return 0;
2713
2714 err_locked:
2715         spin_unlock(&adapter->nfc_lock);
2716
2717 err_parse:
2718         kfree(filter);
2719
2720         return err;
2721 }
2722
2723 static int igb_delete_clsflower(struct igb_adapter *adapter,
2724                                 struct tc_cls_flower_offload *cls_flower)
2725 {
2726         struct igb_nfc_filter *filter;
2727         int err;
2728
2729         spin_lock(&adapter->nfc_lock);
2730
2731         hlist_for_each_entry(filter, &adapter->cls_flower_list, nfc_node)
2732                 if (filter->cookie == cls_flower->cookie)
2733                         break;
2734
2735         if (!filter) {
2736                 err = -ENOENT;
2737                 goto out;
2738         }
2739
2740         err = igb_erase_filter(adapter, filter);
2741         if (err < 0)
2742                 goto out;
2743
2744         hlist_del(&filter->nfc_node);
2745         kfree(filter);
2746
2747 out:
2748         spin_unlock(&adapter->nfc_lock);
2749
2750         return err;
2751 }
2752
2753 static int igb_setup_tc_cls_flower(struct igb_adapter *adapter,
2754                                    struct tc_cls_flower_offload *cls_flower)
2755 {
2756         switch (cls_flower->command) {
2757         case TC_CLSFLOWER_REPLACE:
2758                 return igb_configure_clsflower(adapter, cls_flower);
2759         case TC_CLSFLOWER_DESTROY:
2760                 return igb_delete_clsflower(adapter, cls_flower);
2761         case TC_CLSFLOWER_STATS:
2762                 return -EOPNOTSUPP;
2763         default:
2764                 return -EOPNOTSUPP;
2765         }
2766 }
2767
2768 static int igb_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
2769                                  void *cb_priv)
2770 {
2771         struct igb_adapter *adapter = cb_priv;
2772
2773         if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
2774                 return -EOPNOTSUPP;
2775
2776         switch (type) {
2777         case TC_SETUP_CLSFLOWER:
2778                 return igb_setup_tc_cls_flower(adapter, type_data);
2779
2780         default:
2781                 return -EOPNOTSUPP;
2782         }
2783 }
2784
2785 static int igb_setup_tc_block(struct igb_adapter *adapter,
2786                               struct tc_block_offload *f)
2787 {
2788         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
2789                 return -EOPNOTSUPP;
2790
2791         switch (f->command) {
2792         case TC_BLOCK_BIND:
2793                 return tcf_block_cb_register(f->block, igb_setup_tc_block_cb,
2794                                              adapter, adapter, f->extack);
2795         case TC_BLOCK_UNBIND:
2796                 tcf_block_cb_unregister(f->block, igb_setup_tc_block_cb,
2797                                         adapter);
2798                 return 0;
2799         default:
2800                 return -EOPNOTSUPP;
2801         }
2802 }
2803
2804 static int igb_offload_txtime(struct igb_adapter *adapter,
2805                               struct tc_etf_qopt_offload *qopt)
2806 {
2807         struct e1000_hw *hw = &adapter->hw;
2808         int err;
2809
2810         /* Launchtime offloading is only supported by i210 controller. */
2811         if (hw->mac.type != e1000_i210)
2812                 return -EOPNOTSUPP;
2813
2814         /* Launchtime offloading is only supported by queues 0 and 1. */
2815         if (qopt->queue < 0 || qopt->queue > 1)
2816                 return -EINVAL;
2817
2818         err = igb_save_txtime_params(adapter, qopt->queue, qopt->enable);
2819         if (err)
2820                 return err;
2821
2822         igb_offload_apply(adapter, qopt->queue);
2823
2824         return 0;
2825 }
2826
2827 static int igb_setup_tc(struct net_device *dev, enum tc_setup_type type,
2828                         void *type_data)
2829 {
2830         struct igb_adapter *adapter = netdev_priv(dev);
2831
2832         switch (type) {
2833         case TC_SETUP_QDISC_CBS:
2834                 return igb_offload_cbs(adapter, type_data);
2835         case TC_SETUP_BLOCK:
2836                 return igb_setup_tc_block(adapter, type_data);
2837         case TC_SETUP_QDISC_ETF:
2838                 return igb_offload_txtime(adapter, type_data);
2839
2840         default:
2841                 return -EOPNOTSUPP;
2842         }
2843 }
2844
2845 static const struct net_device_ops igb_netdev_ops = {
2846         .ndo_open               = igb_open,
2847         .ndo_stop               = igb_close,
2848         .ndo_start_xmit         = igb_xmit_frame,
2849         .ndo_get_stats64        = igb_get_stats64,
2850         .ndo_set_rx_mode        = igb_set_rx_mode,
2851         .ndo_set_mac_address    = igb_set_mac,
2852         .ndo_change_mtu         = igb_change_mtu,
2853         .ndo_do_ioctl           = igb_ioctl,
2854         .ndo_tx_timeout         = igb_tx_timeout,
2855         .ndo_validate_addr      = eth_validate_addr,
2856         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
2857         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
2858         .ndo_set_vf_mac         = igb_ndo_set_vf_mac,
2859         .ndo_set_vf_vlan        = igb_ndo_set_vf_vlan,
2860         .ndo_set_vf_rate        = igb_ndo_set_vf_bw,
2861         .ndo_set_vf_spoofchk    = igb_ndo_set_vf_spoofchk,
2862         .ndo_set_vf_trust       = igb_ndo_set_vf_trust,
2863         .ndo_get_vf_config      = igb_ndo_get_vf_config,
2864         .ndo_fix_features       = igb_fix_features,
2865         .ndo_set_features       = igb_set_features,
2866         .ndo_fdb_add            = igb_ndo_fdb_add,
2867         .ndo_features_check     = igb_features_check,
2868         .ndo_setup_tc           = igb_setup_tc,
2869 };
2870
2871 /**
2872  * igb_set_fw_version - Configure version string for ethtool
2873  * @adapter: adapter struct
2874  **/
2875 void igb_set_fw_version(struct igb_adapter *adapter)
2876 {
2877         struct e1000_hw *hw = &adapter->hw;
2878         struct e1000_fw_version fw;
2879
2880         igb_get_fw_version(hw, &fw);
2881
2882         switch (hw->mac.type) {
2883         case e1000_i210:
2884         case e1000_i211:
2885                 if (!(igb_get_flash_presence_i210(hw))) {
2886                         snprintf(adapter->fw_version,
2887                                  sizeof(adapter->fw_version),
2888                                  "%2d.%2d-%d",
2889                                  fw.invm_major, fw.invm_minor,
2890                                  fw.invm_img_type);
2891                         break;
2892                 }
2893                 /* fall through */
2894         default:
2895                 /* if option is rom valid, display its version too */
2896                 if (fw.or_valid) {
2897                         snprintf(adapter->fw_version,
2898                                  sizeof(adapter->fw_version),
2899                                  "%d.%d, 0x%08x, %d.%d.%d",
2900                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
2901                                  fw.or_major, fw.or_build, fw.or_patch);
2902                 /* no option rom */
2903                 } else if (fw.etrack_id != 0X0000) {
2904                         snprintf(adapter->fw_version,
2905                             sizeof(adapter->fw_version),
2906                             "%d.%d, 0x%08x",
2907                             fw.eep_major, fw.eep_minor, fw.etrack_id);
2908                 } else {
2909                 snprintf(adapter->fw_version,
2910                     sizeof(adapter->fw_version),
2911                     "%d.%d.%d",
2912                     fw.eep_major, fw.eep_minor, fw.eep_build);
2913                 }
2914                 break;
2915         }
2916 }
2917
2918 /**
2919  * igb_init_mas - init Media Autosense feature if enabled in the NVM
2920  *
2921  * @adapter: adapter struct
2922  **/
2923 static void igb_init_mas(struct igb_adapter *adapter)
2924 {
2925         struct e1000_hw *hw = &adapter->hw;
2926         u16 eeprom_data;
2927
2928         hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data);
2929         switch (hw->bus.func) {
2930         case E1000_FUNC_0:
2931                 if (eeprom_data & IGB_MAS_ENABLE_0) {
2932                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
2933                         netdev_info(adapter->netdev,
2934                                 "MAS: Enabling Media Autosense for port %d\n",
2935                                 hw->bus.func);
2936                 }
2937                 break;
2938         case E1000_FUNC_1:
2939                 if (eeprom_data & IGB_MAS_ENABLE_1) {
2940                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
2941                         netdev_info(adapter->netdev,
2942                                 "MAS: Enabling Media Autosense for port %d\n",
2943                                 hw->bus.func);
2944                 }
2945                 break;
2946         case E1000_FUNC_2:
2947                 if (eeprom_data & IGB_MAS_ENABLE_2) {
2948                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
2949                         netdev_info(adapter->netdev,
2950                                 "MAS: Enabling Media Autosense for port %d\n",
2951                                 hw->bus.func);
2952                 }
2953                 break;
2954         case E1000_FUNC_3:
2955                 if (eeprom_data & IGB_MAS_ENABLE_3) {
2956                         adapter->flags |= IGB_FLAG_MAS_ENABLE;
2957                         netdev_info(adapter->netdev,
2958                                 "MAS: Enabling Media Autosense for port %d\n",
2959                                 hw->bus.func);
2960                 }
2961                 break;
2962         default:
2963                 /* Shouldn't get here */
2964                 netdev_err(adapter->netdev,
2965                         "MAS: Invalid port configuration, returning\n");
2966                 break;
2967         }
2968 }
2969
2970 /**
2971  *  igb_init_i2c - Init I2C interface
2972  *  @adapter: pointer to adapter structure
2973  **/
2974 static s32 igb_init_i2c(struct igb_adapter *adapter)
2975 {
2976         s32 status = 0;
2977
2978         /* I2C interface supported on i350 devices */
2979         if (adapter->hw.mac.type != e1000_i350)
2980                 return 0;
2981
2982         /* Initialize the i2c bus which is controlled by the registers.
2983          * This bus will use the i2c_algo_bit structue that implements
2984          * the protocol through toggling of the 4 bits in the register.
2985          */
2986         adapter->i2c_adap.owner = THIS_MODULE;
2987         adapter->i2c_algo = igb_i2c_algo;
2988         adapter->i2c_algo.data = adapter;
2989         adapter->i2c_adap.algo_data = &adapter->i2c_algo;
2990         adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
2991         strlcpy(adapter->i2c_adap.name, "igb BB",
2992                 sizeof(adapter->i2c_adap.name));
2993         status = i2c_bit_add_bus(&adapter->i2c_adap);
2994         return status;
2995 }
2996
2997 /**
2998  *  igb_probe - Device Initialization Routine
2999  *  @pdev: PCI device information struct
3000  *  @ent: entry in igb_pci_tbl
3001  *
3002  *  Returns 0 on success, negative on failure
3003  *
3004  *  igb_probe initializes an adapter identified by a pci_dev structure.
3005  *  The OS initialization, configuring of the adapter private structure,
3006  *  and a hardware reset occur.
3007  **/
3008 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3009 {
3010         struct net_device *netdev;
3011         struct igb_adapter *adapter;
3012         struct e1000_hw *hw;
3013         u16 eeprom_data = 0;
3014         s32 ret_val;
3015         static int global_quad_port_a; /* global quad port a indication */
3016         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
3017         int err, pci_using_dac;
3018         u8 part_str[E1000_PBANUM_LENGTH];
3019
3020         /* Catch broken hardware that put the wrong VF device ID in
3021          * the PCIe SR-IOV capability.
3022          */
3023         if (pdev->is_virtfn) {
3024                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
3025                         pci_name(pdev), pdev->vendor, pdev->device);
3026                 return -EINVAL;
3027         }
3028
3029         err = pci_enable_device_mem(pdev);
3030         if (err)
3031                 return err;
3032
3033         pci_using_dac = 0;
3034         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3035         if (!err) {
3036                 pci_using_dac = 1;
3037         } else {
3038                 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
3039                 if (err) {
3040                         dev_err(&pdev->dev,
3041                                 "No usable DMA configuration, aborting\n");
3042                         goto err_dma;
3043                 }
3044         }
3045
3046         err = pci_request_mem_regions(pdev, igb_driver_name);
3047         if (err)
3048                 goto err_pci_reg;
3049
3050         pci_enable_pcie_error_reporting(pdev);
3051
3052         pci_set_master(pdev);
3053         pci_save_state(pdev);
3054
3055         err = -ENOMEM;
3056         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
3057                                    IGB_MAX_TX_QUEUES);
3058         if (!netdev)
3059                 goto err_alloc_etherdev;
3060
3061         SET_NETDEV_DEV(netdev, &pdev->dev);
3062
3063         pci_set_drvdata(pdev, netdev);
3064         adapter = netdev_priv(netdev);
3065         adapter->netdev = netdev;
3066         adapter->pdev = pdev;
3067         hw = &adapter->hw;
3068         hw->back = adapter;
3069         adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3070
3071         err = -EIO;
3072         adapter->io_addr = pci_iomap(pdev, 0, 0);
3073         if (!adapter->io_addr)
3074                 goto err_ioremap;
3075         /* hw->hw_addr can be altered, we'll use adapter->io_addr for unmap */
3076         hw->hw_addr = adapter->io_addr;
3077
3078         netdev->netdev_ops = &igb_netdev_ops;
3079         igb_set_ethtool_ops(netdev);
3080         netdev->watchdog_timeo = 5 * HZ;
3081
3082         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
3083
3084         netdev->mem_start = pci_resource_start(pdev, 0);
3085         netdev->mem_end = pci_resource_end(pdev, 0);
3086
3087         /* PCI config space info */
3088         hw->vendor_id = pdev->vendor;
3089         hw->device_id = pdev->device;
3090         hw->revision_id = pdev->revision;
3091         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3092         hw->subsystem_device_id = pdev->subsystem_device;
3093
3094         /* Copy the default MAC, PHY and NVM function pointers */
3095         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
3096         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
3097         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
3098         /* Initialize skew-specific constants */
3099         err = ei->get_invariants(hw);
3100         if (err)
3101                 goto err_sw_init;
3102
3103         /* setup the private structure */
3104         err = igb_sw_init(adapter);
3105         if (err)
3106                 goto err_sw_init;
3107
3108         igb_get_bus_info_pcie(hw);
3109
3110         hw->phy.autoneg_wait_to_complete = false;
3111
3112         /* Copper options */
3113         if (hw->phy.media_type == e1000_media_type_copper) {
3114                 hw->phy.mdix = AUTO_ALL_MODES;
3115                 hw->phy.disable_polarity_correction = false;
3116                 hw->phy.ms_type = e1000_ms_hw_default;
3117         }
3118
3119         if (igb_check_reset_block(hw))
3120                 dev_info(&pdev->dev,
3121                         "PHY reset is blocked due to SOL/IDER session.\n");
3122
3123         /* features is initialized to 0 in allocation, it might have bits
3124          * set by igb_sw_init so we should use an or instead of an
3125          * assignment.
3126          */
3127         netdev->features |= NETIF_F_SG |
3128                             NETIF_F_TSO |
3129                             NETIF_F_TSO6 |
3130                             NETIF_F_RXHASH |
3131                             NETIF_F_RXCSUM |
3132                             NETIF_F_HW_CSUM;
3133
3134         if (hw->mac.type >= e1000_82576)
3135                 netdev->features |= NETIF_F_SCTP_CRC;
3136
3137         if (hw->mac.type >= e1000_i350)
3138                 netdev->features |= NETIF_F_HW_TC;
3139
3140 #define IGB_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
3141                                   NETIF_F_GSO_GRE_CSUM | \
3142                                   NETIF_F_GSO_IPXIP4 | \
3143                                   NETIF_F_GSO_IPXIP6 | \
3144                                   NETIF_F_GSO_UDP_TUNNEL | \
3145                                   NETIF_F_GSO_UDP_TUNNEL_CSUM)
3146
3147         netdev->gso_partial_features = IGB_GSO_PARTIAL_FEATURES;
3148         netdev->features |= NETIF_F_GSO_PARTIAL | IGB_GSO_PARTIAL_FEATURES;
3149
3150         /* copy netdev features into list of user selectable features */
3151         netdev->hw_features |= netdev->features |
3152                                NETIF_F_HW_VLAN_CTAG_RX |
3153                                NETIF_F_HW_VLAN_CTAG_TX |
3154                                NETIF_F_RXALL;
3155
3156         if (hw->mac.type >= e1000_i350)
3157                 netdev->hw_features |= NETIF_F_NTUPLE;
3158
3159         if (pci_using_dac)
3160                 netdev->features |= NETIF_F_HIGHDMA;
3161
3162         netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
3163         netdev->mpls_features |= NETIF_F_HW_CSUM;
3164         netdev->hw_enc_features |= netdev->vlan_features;
3165
3166         /* set this bit last since it cannot be part of vlan_features */
3167         netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
3168                             NETIF_F_HW_VLAN_CTAG_RX |
3169                             NETIF_F_HW_VLAN_CTAG_TX;
3170
3171         netdev->priv_flags |= IFF_SUPP_NOFCS;
3172
3173         netdev->priv_flags |= IFF_UNICAST_FLT;
3174
3175         /* MTU range: 68 - 9216 */
3176         netdev->min_mtu = ETH_MIN_MTU;
3177         netdev->max_mtu = MAX_STD_JUMBO_FRAME_SIZE;
3178
3179         adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
3180
3181         /* before reading the NVM, reset the controller to put the device in a
3182          * known good starting state
3183          */
3184         hw->mac.ops.reset_hw(hw);
3185
3186         /* make sure the NVM is good , i211/i210 parts can have special NVM
3187          * that doesn't contain a checksum
3188          */
3189         switch (hw->mac.type) {
3190         case e1000_i210:
3191         case e1000_i211:
3192                 if (igb_get_flash_presence_i210(hw)) {
3193                         if (hw->nvm.ops.validate(hw) < 0) {
3194                                 dev_err(&pdev->dev,
3195                                         "The NVM Checksum Is Not Valid\n");
3196                                 err = -EIO;
3197                                 goto err_eeprom;
3198                         }
3199                 }
3200                 break;
3201         default:
3202                 if (hw->nvm.ops.validate(hw) < 0) {
3203                         dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
3204                         err = -EIO;
3205                         goto err_eeprom;
3206                 }
3207                 break;
3208         }
3209
3210         if (eth_platform_get_mac_address(&pdev->dev, hw->mac.addr)) {
3211                 /* copy the MAC address out of the NVM */
3212                 if (hw->mac.ops.read_mac_addr(hw))
3213                         dev_err(&pdev->dev, "NVM Read Error\n");
3214         }
3215
3216         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
3217
3218         if (!is_valid_ether_addr(netdev->dev_addr)) {
3219                 dev_err(&pdev->dev, "Invalid MAC Address\n");
3220                 err = -EIO;
3221                 goto err_eeprom;
3222         }
3223
3224         igb_set_default_mac_filter(adapter);
3225
3226         /* get firmware version for ethtool -i */
3227         igb_set_fw_version(adapter);
3228
3229         /* configure RXPBSIZE and TXPBSIZE */
3230         if (hw->mac.type == e1000_i210) {
3231                 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT);
3232                 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT);
3233         }
3234
3235         timer_setup(&adapter->watchdog_timer, igb_watchdog, 0);
3236         timer_setup(&adapter->phy_info_timer, igb_update_phy_info, 0);
3237
3238         INIT_WORK(&adapter->reset_task, igb_reset_task);
3239         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
3240
3241         /* Initialize link properties that are user-changeable */
3242         adapter->fc_autoneg = true;
3243         hw->mac.autoneg = true;
3244         hw->phy.autoneg_advertised = 0x2f;
3245
3246         hw->fc.requested_mode = e1000_fc_default;
3247         hw->fc.current_mode = e1000_fc_default;
3248
3249         igb_validate_mdi_setting(hw);
3250
3251         /* By default, support wake on port A */
3252         if (hw->bus.func == 0)
3253                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3254
3255         /* Check the NVM for wake support on non-port A ports */
3256         if (hw->mac.type >= e1000_82580)
3257                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
3258                                  NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
3259                                  &eeprom_data);
3260         else if (hw->bus.func == 1)
3261                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
3262
3263         if (eeprom_data & IGB_EEPROM_APME)
3264                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3265
3266         /* now that we have the eeprom settings, apply the special cases where
3267          * the eeprom may be wrong or the board simply won't support wake on
3268          * lan on a particular port
3269          */
3270         switch (pdev->device) {
3271         case E1000_DEV_ID_82575GB_QUAD_COPPER:
3272                 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3273                 break;
3274         case E1000_DEV_ID_82575EB_FIBER_SERDES:
3275         case E1000_DEV_ID_82576_FIBER:
3276         case E1000_DEV_ID_82576_SERDES:
3277                 /* Wake events only supported on port A for dual fiber
3278                  * regardless of eeprom setting
3279                  */
3280                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
3281                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3282                 break;
3283         case E1000_DEV_ID_82576_QUAD_COPPER:
3284         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
3285                 /* if quad port adapter, disable WoL on all but port A */
3286                 if (global_quad_port_a != 0)
3287                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3288                 else
3289                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
3290                 /* Reset for multiple quad port adapters */
3291                 if (++global_quad_port_a == 4)
3292                         global_quad_port_a = 0;
3293                 break;
3294         default:
3295                 /* If the device can't wake, don't set software support */
3296                 if (!device_can_wakeup(&adapter->pdev->dev))
3297                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
3298         }
3299
3300         /* initialize the wol settings based on the eeprom settings */
3301         if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
3302                 adapter->wol |= E1000_WUFC_MAG;
3303
3304         /* Some vendors want WoL disabled by default, but still supported */
3305         if ((hw->mac.type == e1000_i350) &&
3306             (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
3307                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3308                 adapter->wol = 0;
3309         }
3310
3311         /* Some vendors want the ability to Use the EEPROM setting as
3312          * enable/disable only, and not for capability
3313          */
3314         if (((hw->mac.type == e1000_i350) ||
3315              (hw->mac.type == e1000_i354)) &&
3316             (pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)) {
3317                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3318                 adapter->wol = 0;
3319         }
3320         if (hw->mac.type == e1000_i350) {
3321                 if (((pdev->subsystem_device == 0x5001) ||
3322                      (pdev->subsystem_device == 0x5002)) &&
3323                                 (hw->bus.func == 0)) {
3324                         adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3325                         adapter->wol = 0;
3326                 }
3327                 if (pdev->subsystem_device == 0x1F52)
3328                         adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
3329         }
3330
3331         device_set_wakeup_enable(&adapter->pdev->dev,
3332                                  adapter->flags & IGB_FLAG_WOL_SUPPORTED);
3333
3334         /* reset the hardware with the new settings */
3335         igb_reset(adapter);
3336
3337         /* Init the I2C interface */
3338         err = igb_init_i2c(adapter);
3339         if (err) {
3340                 dev_err(&pdev->dev, "failed to init i2c interface\n");
3341                 goto err_eeprom;
3342         }
3343
3344         /* let the f/w know that the h/w is now under the control of the
3345          * driver.
3346          */
3347         igb_get_hw_control(adapter);
3348
3349         strcpy(netdev->name, "eth%d");
3350         err = register_netdev(netdev);
3351         if (err)
3352                 goto err_register;
3353
3354         /* carrier off reporting is important to ethtool even BEFORE open */
3355         netif_carrier_off(netdev);
3356
3357 #ifdef CONFIG_IGB_DCA
3358         if (dca_add_requester(&pdev->dev) == 0) {
3359                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
3360                 dev_info(&pdev->dev, "DCA enabled\n");
3361                 igb_setup_dca(adapter);
3362         }
3363
3364 #endif
3365 #ifdef CONFIG_IGB_HWMON
3366         /* Initialize the thermal sensor on i350 devices. */
3367         if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
3368                 u16 ets_word;
3369
3370                 /* Read the NVM to determine if this i350 device supports an
3371                  * external thermal sensor.
3372                  */
3373                 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
3374                 if (ets_word != 0x0000 && ets_word != 0xFFFF)
3375                         adapter->ets = true;
3376                 else
3377                         adapter->ets = false;
3378                 if (igb_sysfs_init(adapter))
3379                         dev_err(&pdev->dev,
3380                                 "failed to allocate sysfs resources\n");
3381         } else {
3382                 adapter->ets = false;
3383         }
3384 #endif
3385         /* Check if Media Autosense is enabled */
3386         adapter->ei = *ei;
3387         if (hw->dev_spec._82575.mas_capable)
3388                 igb_init_mas(adapter);
3389
3390         /* do hw tstamp init after resetting */
3391         igb_ptp_init(adapter);
3392
3393         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
3394         /* print bus type/speed/width info, not applicable to i354 */
3395         if (hw->mac.type != e1000_i354) {
3396                 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
3397                          netdev->name,
3398                          ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
3399                           (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
3400                            "unknown"),
3401                          ((hw->bus.width == e1000_bus_width_pcie_x4) ?
3402                           "Width x4" :
3403                           (hw->bus.width == e1000_bus_width_pcie_x2) ?
3404                           "Width x2" :
3405                           (hw->bus.width == e1000_bus_width_pcie_x1) ?
3406                           "Width x1" : "unknown"), netdev->dev_addr);
3407         }
3408
3409         if ((hw->mac.type >= e1000_i210 ||
3410              igb_get_flash_presence_i210(hw))) {
3411                 ret_val = igb_read_part_string(hw, part_str,
3412                                                E1000_PBANUM_LENGTH);
3413         } else {
3414                 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND;
3415         }
3416
3417         if (ret_val)
3418                 strcpy(part_str, "Unknown");
3419         dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
3420         dev_info(&pdev->dev,
3421                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
3422                 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" :
3423                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
3424                 adapter->num_rx_queues, adapter->num_tx_queues);
3425         if (hw->phy.media_type == e1000_media_type_copper) {
3426                 switch (hw->mac.type) {
3427                 case e1000_i350:
3428                 case e1000_i210:
3429                 case e1000_i211:
3430                         /* Enable EEE for internal copper PHY devices */
3431                         err = igb_set_eee_i350(hw, true, true);
3432                         if ((!err) &&
3433                             (!hw->dev_spec._82575.eee_disable)) {
3434                                 adapter->eee_advert =
3435                                         MDIO_EEE_100TX | MDIO_EEE_1000T;
3436                                 adapter->flags |= IGB_FLAG_EEE;
3437                         }
3438                         break;
3439                 case e1000_i354:
3440                         if ((rd32(E1000_CTRL_EXT) &
3441                             E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3442                                 err = igb_set_eee_i354(hw, true, true);
3443                                 if ((!err) &&
3444                                         (!hw->dev_spec._82575.eee_disable)) {
3445                                         adapter->eee_advert =
3446                                            MDIO_EEE_100TX | MDIO_EEE_1000T;
3447                                         adapter->flags |= IGB_FLAG_EEE;
3448                                 }
3449                         }
3450                         break;
3451                 default:
3452                         break;
3453                 }
3454         }
3455
3456         dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_NEVER_SKIP);
3457
3458         pm_runtime_put_noidle(&pdev->dev);
3459         return 0;
3460
3461 err_register:
3462         igb_release_hw_control(adapter);
3463         memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
3464 err_eeprom:
3465         if (!igb_check_reset_block(hw))
3466                 igb_reset_phy(hw);
3467
3468         if (hw->flash_address)
3469                 iounmap(hw->flash_address);
3470 err_sw_init:
3471         kfree(adapter->mac_table);
3472         kfree(adapter->shadow_vfta);
3473         igb_clear_interrupt_scheme(adapter);
3474 #ifdef CONFIG_PCI_IOV
3475         igb_disable_sriov(pdev);
3476 #endif
3477         pci_iounmap(pdev, adapter->io_addr);
3478 err_ioremap:
3479         free_netdev(netdev);
3480 err_alloc_etherdev:
3481         pci_release_mem_regions(pdev);
3482 err_pci_reg:
3483 err_dma:
3484         pci_disable_device(pdev);
3485         return err;
3486 }
3487
3488 #ifdef CONFIG_PCI_IOV
3489 static int igb_disable_sriov(struct pci_dev *pdev)
3490 {
3491         struct net_device *netdev = pci_get_drvdata(pdev);
3492         struct igb_adapter *adapter = netdev_priv(netdev);
3493         struct e1000_hw *hw = &adapter->hw;
3494
3495         /* reclaim resources allocated to VFs */
3496         if (adapter->vf_data) {
3497                 /* disable iov and allow time for transactions to clear */
3498                 if (pci_vfs_assigned(pdev)) {
3499                         dev_warn(&pdev->dev,
3500                                  "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
3501                         return -EPERM;
3502                 } else {
3503                         pci_disable_sriov(pdev);
3504                         msleep(500);
3505                 }
3506
3507                 kfree(adapter->vf_mac_list);
3508                 adapter->vf_mac_list = NULL;
3509                 kfree(adapter->vf_data);
3510                 adapter->vf_data = NULL;
3511                 adapter->vfs_allocated_count = 0;
3512                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
3513                 wrfl();
3514                 msleep(100);
3515                 dev_info(&pdev->dev, "IOV Disabled\n");
3516
3517                 /* Re-enable DMA Coalescing flag since IOV is turned off */
3518                 adapter->flags |= IGB_FLAG_DMAC;
3519         }
3520
3521         return 0;
3522 }
3523
3524 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
3525 {
3526         struct net_device *netdev = pci_get_drvdata(pdev);
3527         struct igb_adapter *adapter = netdev_priv(netdev);
3528         int old_vfs = pci_num_vf(pdev);
3529         struct vf_mac_filter *mac_list;
3530         int err = 0;
3531         int num_vf_mac_filters, i;
3532
3533         if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) {
3534                 err = -EPERM;
3535                 goto out;
3536         }
3537         if (!num_vfs)
3538                 goto out;
3539
3540         if (old_vfs) {
3541                 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n",
3542                          old_vfs, max_vfs);
3543                 adapter->vfs_allocated_count = old_vfs;
3544         } else
3545                 adapter->vfs_allocated_count = num_vfs;
3546
3547         adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
3548                                 sizeof(struct vf_data_storage), GFP_KERNEL);
3549
3550         /* if allocation failed then we do not support SR-IOV */
3551         if (!adapter->vf_data) {
3552                 adapter->vfs_allocated_count = 0;
3553                 err = -ENOMEM;
3554                 goto out;
3555         }
3556
3557         /* Due to the limited number of RAR entries calculate potential
3558          * number of MAC filters available for the VFs. Reserve entries
3559          * for PF default MAC, PF MAC filters and at least one RAR entry
3560          * for each VF for VF MAC.
3561          */
3562         num_vf_mac_filters = adapter->hw.mac.rar_entry_count -
3563                              (1 + IGB_PF_MAC_FILTERS_RESERVED +
3564                               adapter->vfs_allocated_count);
3565
3566         adapter->vf_mac_list = kcalloc(num_vf_mac_filters,
3567                                        sizeof(struct vf_mac_filter),
3568                                        GFP_KERNEL);
3569
3570         mac_list = adapter->vf_mac_list;
3571         INIT_LIST_HEAD(&adapter->vf_macs.l);
3572
3573         if (adapter->vf_mac_list) {
3574                 /* Initialize list of VF MAC filters */
3575                 for (i = 0; i < num_vf_mac_filters; i++) {
3576                         mac_list->vf = -1;
3577                         mac_list->free = true;
3578                         list_add(&mac_list->l, &adapter->vf_macs.l);
3579                         mac_list++;
3580                 }
3581         } else {
3582                 /* If we could not allocate memory for the VF MAC filters
3583                  * we can continue without this feature but warn user.
3584                  */
3585                 dev_err(&pdev->dev,
3586                         "Unable to allocate memory for VF MAC filter list\n");
3587         }
3588
3589         /* only call pci_enable_sriov() if no VFs are allocated already */
3590         if (!old_vfs) {
3591                 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
3592                 if (err)
3593                         goto err_out;
3594         }
3595         dev_info(&pdev->dev, "%d VFs allocated\n",
3596                  adapter->vfs_allocated_count);
3597         for (i = 0; i < adapter->vfs_allocated_count; i++)
3598                 igb_vf_configure(adapter, i);
3599
3600         /* DMA Coalescing is not supported in IOV mode. */
3601         adapter->flags &= ~IGB_FLAG_DMAC;
3602         goto out;
3603
3604 err_out:
3605         kfree(adapter->vf_mac_list);
3606         adapter->vf_mac_list = NULL;
3607         kfree(adapter->vf_data);
3608         adapter->vf_data = NULL;
3609         adapter->vfs_allocated_count = 0;
3610 out:
3611         return err;
3612 }
3613
3614 #endif
3615 /**
3616  *  igb_remove_i2c - Cleanup  I2C interface
3617  *  @adapter: pointer to adapter structure
3618  **/
3619 static void igb_remove_i2c(struct igb_adapter *adapter)
3620 {
3621         /* free the adapter bus structure */
3622         i2c_del_adapter(&adapter->i2c_adap);
3623 }
3624
3625 /**
3626  *  igb_remove - Device Removal Routine
3627  *  @pdev: PCI device information struct
3628  *
3629  *  igb_remove is called by the PCI subsystem to alert the driver
3630  *  that it should release a PCI device.  The could be caused by a
3631  *  Hot-Plug event, or because the driver is going to be removed from
3632  *  memory.
3633  **/
3634 static void igb_remove(struct pci_dev *pdev)
3635 {
3636         struct net_device *netdev = pci_get_drvdata(pdev);
3637         struct igb_adapter *adapter = netdev_priv(netdev);
3638         struct e1000_hw *hw = &adapter->hw;
3639
3640         pm_runtime_get_noresume(&pdev->dev);
3641 #ifdef CONFIG_IGB_HWMON
3642         igb_sysfs_exit(adapter);
3643 #endif
3644         igb_remove_i2c(adapter);
3645         igb_ptp_stop(adapter);
3646         /* The watchdog timer may be rescheduled, so explicitly
3647          * disable watchdog from being rescheduled.
3648          */
3649         set_bit(__IGB_DOWN, &adapter->state);
3650         del_timer_sync(&adapter->watchdog_timer);
3651         del_timer_sync(&adapter->phy_info_timer);
3652
3653         cancel_work_sync(&adapter->reset_task);
3654         cancel_work_sync(&adapter->watchdog_task);
3655
3656 #ifdef CONFIG_IGB_DCA
3657         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
3658                 dev_info(&pdev->dev, "DCA disabled\n");
3659                 dca_remove_requester(&pdev->dev);
3660                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
3661                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
3662         }
3663 #endif
3664
3665         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
3666          * would have already happened in close and is redundant.
3667          */
3668         igb_release_hw_control(adapter);
3669
3670 #ifdef CONFIG_PCI_IOV
3671         igb_disable_sriov(pdev);
3672 #endif
3673
3674         unregister_netdev(netdev);
3675
3676         igb_clear_interrupt_scheme(adapter);
3677
3678         pci_iounmap(pdev, adapter->io_addr);
3679         if (hw->flash_address)
3680                 iounmap(hw->flash_address);
3681         pci_release_mem_regions(pdev);
3682
3683         kfree(adapter->mac_table);
3684         kfree(adapter->shadow_vfta);
3685         free_netdev(netdev);
3686
3687         pci_disable_pcie_error_reporting(pdev);
3688
3689         pci_disable_device(pdev);
3690 }
3691
3692 /**
3693  *  igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
3694  *  @adapter: board private structure to initialize
3695  *
3696  *  This function initializes the vf specific data storage and then attempts to
3697  *  allocate the VFs.  The reason for ordering it this way is because it is much
3698  *  mor expensive time wise to disable SR-IOV than it is to allocate and free
3699  *  the memory for the VFs.
3700  **/
3701 static void igb_probe_vfs(struct igb_adapter *adapter)
3702 {
3703 #ifdef CONFIG_PCI_IOV
3704         struct pci_dev *pdev = adapter->pdev;
3705         struct e1000_hw *hw = &adapter->hw;
3706
3707         /* Virtualization features not supported on i210 family. */
3708         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
3709                 return;
3710
3711         /* Of the below we really only want the effect of getting
3712          * IGB_FLAG_HAS_MSIX set (if available), without which
3713          * igb_enable_sriov() has no effect.
3714          */
3715         igb_set_interrupt_capability(adapter, true);
3716         igb_reset_interrupt_capability(adapter);
3717
3718         pci_sriov_set_totalvfs(pdev, 7);
3719         igb_enable_sriov(pdev, max_vfs);
3720
3721 #endif /* CONFIG_PCI_IOV */
3722 }
3723
3724 unsigned int igb_get_max_rss_queues(struct igb_adapter *adapter)
3725 {
3726         struct e1000_hw *hw = &adapter->hw;
3727         unsigned int max_rss_queues;
3728
3729         /* Determine the maximum number of RSS queues supported. */
3730         switch (hw->mac.type) {
3731         case e1000_i211:
3732                 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
3733                 break;
3734         case e1000_82575:
3735         case e1000_i210:
3736                 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
3737                 break;
3738         case e1000_i350:
3739                 /* I350 cannot do RSS and SR-IOV at the same time */
3740                 if (!!adapter->vfs_allocated_count) {
3741                         max_rss_queues = 1;
3742                         break;
3743                 }
3744                 /* fall through */
3745         case e1000_82576:
3746                 if (!!adapter->vfs_allocated_count) {
3747                         max_rss_queues = 2;
3748                         break;
3749                 }
3750                 /* fall through */
3751         case e1000_82580:
3752         case e1000_i354:
3753         default:
3754                 max_rss_queues = IGB_MAX_RX_QUEUES;
3755                 break;
3756         }
3757
3758         return max_rss_queues;
3759 }
3760
3761 static void igb_init_queue_configuration(struct igb_adapter *adapter)
3762 {
3763         u32 max_rss_queues;
3764
3765         max_rss_queues = igb_get_max_rss_queues(adapter);
3766         adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
3767
3768         igb_set_flag_queue_pairs(adapter, max_rss_queues);
3769 }
3770
3771 void igb_set_flag_queue_pairs(struct igb_adapter *adapter,
3772                               const u32 max_rss_queues)
3773 {
3774         struct e1000_hw *hw = &adapter->hw;
3775
3776         /* Determine if we need to pair queues. */
3777         switch (hw->mac.type) {
3778         case e1000_82575:
3779         case e1000_i211:
3780                 /* Device supports enough interrupts without queue pairing. */
3781                 break;
3782         case e1000_82576:
3783         case e1000_82580:
3784         case e1000_i350:
3785         case e1000_i354:
3786         case e1000_i210:
3787         default:
3788                 /* If rss_queues > half of max_rss_queues, pair the queues in
3789                  * order to conserve interrupts due to limited supply.
3790                  */
3791                 if (adapter->rss_queues > (max_rss_queues / 2))
3792                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
3793                 else
3794                         adapter->flags &= ~IGB_FLAG_QUEUE_PAIRS;
3795                 break;
3796         }
3797 }
3798
3799 /**
3800  *  igb_sw_init - Initialize general software structures (struct igb_adapter)
3801  *  @adapter: board private structure to initialize
3802  *
3803  *  igb_sw_init initializes the Adapter private data structure.
3804  *  Fields are initialized based on PCI device information and
3805  *  OS network device settings (MTU size).
3806  **/
3807 static int igb_sw_init(struct igb_adapter *adapter)
3808 {
3809         struct e1000_hw *hw = &adapter->hw;
3810         struct net_device *netdev = adapter->netdev;
3811         struct pci_dev *pdev = adapter->pdev;
3812
3813         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
3814
3815         /* set default ring sizes */
3816         adapter->tx_ring_count = IGB_DEFAULT_TXD;
3817         adapter->rx_ring_count = IGB_DEFAULT_RXD;
3818
3819         /* set default ITR values */
3820         adapter->rx_itr_setting = IGB_DEFAULT_ITR;
3821         adapter->tx_itr_setting = IGB_DEFAULT_ITR;
3822
3823         /* set default work limits */
3824         adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
3825
3826         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
3827                                   VLAN_HLEN;
3828         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
3829
3830         spin_lock_init(&adapter->nfc_lock);
3831         spin_lock_init(&adapter->stats64_lock);
3832 #ifdef CONFIG_PCI_IOV
3833         switch (hw->mac.type) {
3834         case e1000_82576:
3835         case e1000_i350:
3836                 if (max_vfs > 7) {
3837                         dev_warn(&pdev->dev,
3838                                  "Maximum of 7 VFs per PF, using max\n");
3839                         max_vfs = adapter->vfs_allocated_count = 7;
3840                 } else
3841                         adapter->vfs_allocated_count = max_vfs;
3842                 if (adapter->vfs_allocated_count)
3843                         dev_warn(&pdev->dev,
3844                                  "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
3845                 break;
3846         default:
3847                 break;
3848         }
3849 #endif /* CONFIG_PCI_IOV */
3850
3851         /* Assume MSI-X interrupts, will be checked during IRQ allocation */
3852         adapter->flags |= IGB_FLAG_HAS_MSIX;
3853
3854         adapter->mac_table = kcalloc(hw->mac.rar_entry_count,
3855                                      sizeof(struct igb_mac_addr),
3856                                      GFP_KERNEL);
3857         if (!adapter->mac_table)
3858                 return -ENOMEM;
3859
3860         igb_probe_vfs(adapter);
3861
3862         igb_init_queue_configuration(adapter);
3863
3864         /* Setup and initialize a copy of the hw vlan table array */
3865         adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
3866                                        GFP_KERNEL);
3867         if (!adapter->shadow_vfta)
3868                 return -ENOMEM;
3869
3870         /* This call may decrease the number of queues */
3871         if (igb_init_interrupt_scheme(adapter, true)) {
3872                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
3873                 return -ENOMEM;
3874         }
3875
3876         /* Explicitly disable IRQ since the NIC can be in any state. */
3877         igb_irq_disable(adapter);
3878
3879         if (hw->mac.type >= e1000_i350)
3880                 adapter->flags &= ~IGB_FLAG_DMAC;
3881
3882         set_bit(__IGB_DOWN, &adapter->state);
3883         return 0;
3884 }
3885
3886 /**
3887  *  igb_open - Called when a network interface is made active
3888  *  @netdev: network interface device structure
3889  *
3890  *  Returns 0 on success, negative value on failure
3891  *
3892  *  The open entry point is called when a network interface is made
3893  *  active by the system (IFF_UP).  At this point all resources needed
3894  *  for transmit and receive operations are allocated, the interrupt
3895  *  handler is registered with the OS, the watchdog timer is started,
3896  *  and the stack is notified that the interface is ready.
3897  **/
3898 static int __igb_open(struct net_device *netdev, bool resuming)
3899 {
3900         struct igb_adapter *adapter = netdev_priv(netdev);
3901         struct e1000_hw *hw = &adapter->hw;
3902         struct pci_dev *pdev = adapter->pdev;
3903         int err;
3904         int i;
3905
3906         /* disallow open during test */
3907         if (test_bit(__IGB_TESTING, &adapter->state)) {
3908                 WARN_ON(resuming);
3909                 return -EBUSY;
3910         }
3911
3912         if (!resuming)
3913                 pm_runtime_get_sync(&pdev->dev);
3914
3915         netif_carrier_off(netdev);
3916
3917         /* allocate transmit descriptors */
3918         err = igb_setup_all_tx_resources(adapter);
3919         if (err)
3920                 goto err_setup_tx;
3921
3922         /* allocate receive descriptors */
3923         err = igb_setup_all_rx_resources(adapter);
3924         if (err)
3925                 goto err_setup_rx;
3926
3927         igb_power_up_link(adapter);
3928
3929         /* before we allocate an interrupt, we must be ready to handle it.
3930          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3931          * as soon as we call pci_request_irq, so we have to setup our
3932          * clean_rx handler before we do so.
3933          */
3934         igb_configure(adapter);
3935
3936         err = igb_request_irq(adapter);
3937         if (err)
3938                 goto err_req_irq;
3939
3940         /* Notify the stack of the actual queue counts. */
3941         err = netif_set_real_num_tx_queues(adapter->netdev,
3942                                            adapter->num_tx_queues);
3943         if (err)
3944                 goto err_set_queues;
3945
3946         err = netif_set_real_num_rx_queues(adapter->netdev,
3947                                            adapter->num_rx_queues);
3948         if (err)
3949                 goto err_set_queues;
3950
3951         /* From here on the code is the same as igb_up() */
3952         clear_bit(__IGB_DOWN, &adapter->state);
3953
3954         for (i = 0; i < adapter->num_q_vectors; i++)
3955                 napi_enable(&(adapter->q_vector[i]->napi));
3956
3957         /* Clear any pending interrupts. */
3958         rd32(E1000_TSICR);
3959         rd32(E1000_ICR);
3960
3961         igb_irq_enable(adapter);
3962
3963         /* notify VFs that reset has been completed */
3964         if (adapter->vfs_allocated_count) {
3965                 u32 reg_data = rd32(E1000_CTRL_EXT);
3966
3967                 reg_data |= E1000_CTRL_EXT_PFRSTD;
3968                 wr32(E1000_CTRL_EXT, reg_data);
3969         }
3970
3971         netif_tx_start_all_queues(netdev);
3972
3973         if (!resuming)
3974                 pm_runtime_put(&pdev->dev);
3975
3976         /* start the watchdog. */
3977         hw->mac.get_link_status = 1;
3978         schedule_work(&adapter->watchdog_task);
3979
3980         return 0;
3981
3982 err_set_queues:
3983         igb_free_irq(adapter);
3984 err_req_irq:
3985         igb_release_hw_control(adapter);
3986         igb_power_down_link(adapter);
3987         igb_free_all_rx_resources(adapter);
3988 err_setup_rx:
3989         igb_free_all_tx_resources(adapter);
3990 err_setup_tx:
3991         igb_reset(adapter);
3992         if (!resuming)
3993                 pm_runtime_put(&pdev->dev);
3994
3995         return err;
3996 }
3997
3998 int igb_open(struct net_device *netdev)
3999 {
4000         return __igb_open(netdev, false);
4001 }
4002
4003 /**
4004  *  igb_close - Disables a network interface
4005  *  @netdev: network interface device structure
4006  *
4007  *  Returns 0, this is not allowed to fail
4008  *
4009  *  The close entry point is called when an interface is de-activated
4010  *  by the OS.  The hardware is still under the driver's control, but
4011  *  needs to be disabled.  A global MAC reset is issued to stop the
4012  *  hardware, and all transmit and receive resources are freed.
4013  **/
4014 static int __igb_close(struct net_device *netdev, bool suspending)
4015 {
4016         struct igb_adapter *adapter = netdev_priv(netdev);
4017         struct pci_dev *pdev = adapter->pdev;
4018
4019         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
4020
4021         if (!suspending)
4022                 pm_runtime_get_sync(&pdev->dev);
4023
4024         igb_down(adapter);
4025         igb_free_irq(adapter);
4026
4027         igb_free_all_tx_resources(adapter);
4028         igb_free_all_rx_resources(adapter);
4029
4030         if (!suspending)
4031                 pm_runtime_put_sync(&pdev->dev);
4032         return 0;
4033 }
4034
4035 int igb_close(struct net_device *netdev)
4036 {
4037         if (netif_device_present(netdev) || netdev->dismantle)
4038                 return __igb_close(netdev, false);
4039         return 0;
4040 }
4041
4042 /**
4043  *  igb_setup_tx_resources - allocate Tx resources (Descriptors)
4044  *  @tx_ring: tx descriptor ring (for a specific queue) to setup
4045  *
4046  *  Return 0 on success, negative on failure
4047  **/
4048 int igb_setup_tx_resources(struct igb_ring *tx_ring)
4049 {
4050         struct device *dev = tx_ring->dev;
4051         int size;
4052
4053         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
4054
4055         tx_ring->tx_buffer_info = vmalloc(size);
4056         if (!tx_ring->tx_buffer_info)
4057                 goto err;
4058
4059         /* round up to nearest 4K */
4060         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
4061         tx_ring->size = ALIGN(tx_ring->size, 4096);
4062
4063         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4064                                            &tx_ring->dma, GFP_KERNEL);
4065         if (!tx_ring->desc)
4066                 goto err;
4067
4068         tx_ring->next_to_use = 0;
4069         tx_ring->next_to_clean = 0;
4070
4071         return 0;
4072
4073 err:
4074         vfree(tx_ring->tx_buffer_info);
4075         tx_ring->tx_buffer_info = NULL;
4076         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4077         return -ENOMEM;
4078 }
4079
4080 /**
4081  *  igb_setup_all_tx_resources - wrapper to allocate Tx resources
4082  *                               (Descriptors) for all queues
4083  *  @adapter: board private structure
4084  *
4085  *  Return 0 on success, negative on failure
4086  **/
4087 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
4088 {
4089         struct pci_dev *pdev = adapter->pdev;
4090         int i, err = 0;
4091
4092         for (i = 0; i < adapter->num_tx_queues; i++) {
4093                 err = igb_setup_tx_resources(adapter->tx_ring[i]);
4094                 if (err) {
4095                         dev_err(&pdev->dev,
4096                                 "Allocation for Tx Queue %u failed\n", i);
4097                         for (i--; i >= 0; i--)
4098                                 igb_free_tx_resources(adapter->tx_ring[i]);
4099                         break;
4100                 }
4101         }
4102
4103         return err;
4104 }
4105
4106 /**
4107  *  igb_setup_tctl - configure the transmit control registers
4108  *  @adapter: Board private structure
4109  **/
4110 void igb_setup_tctl(struct igb_adapter *adapter)
4111 {
4112         struct e1000_hw *hw = &adapter->hw;
4113         u32 tctl;
4114
4115         /* disable queue 0 which is enabled by default on 82575 and 82576 */
4116         wr32(E1000_TXDCTL(0), 0);
4117
4118         /* Program the Transmit Control Register */
4119         tctl = rd32(E1000_TCTL);
4120         tctl &= ~E1000_TCTL_CT;
4121         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
4122                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
4123
4124         igb_config_collision_dist(hw);
4125
4126         /* Enable transmits */
4127         tctl |= E1000_TCTL_EN;
4128
4129         wr32(E1000_TCTL, tctl);
4130 }
4131
4132 /**
4133  *  igb_configure_tx_ring - Configure transmit ring after Reset
4134  *  @adapter: board private structure
4135  *  @ring: tx ring to configure
4136  *
4137  *  Configure a transmit ring after a reset.
4138  **/
4139 void igb_configure_tx_ring(struct igb_adapter *adapter,
4140                            struct igb_ring *ring)
4141 {
4142         struct e1000_hw *hw = &adapter->hw;
4143         u32 txdctl = 0;
4144         u64 tdba = ring->dma;
4145         int reg_idx = ring->reg_idx;
4146
4147         wr32(E1000_TDLEN(reg_idx),
4148              ring->count * sizeof(union e1000_adv_tx_desc));
4149         wr32(E1000_TDBAL(reg_idx),
4150              tdba & 0x00000000ffffffffULL);
4151         wr32(E1000_TDBAH(reg_idx), tdba >> 32);
4152
4153         ring->tail = adapter->io_addr + E1000_TDT(reg_idx);
4154         wr32(E1000_TDH(reg_idx), 0);
4155         writel(0, ring->tail);
4156
4157         txdctl |= IGB_TX_PTHRESH;
4158         txdctl |= IGB_TX_HTHRESH << 8;
4159         txdctl |= IGB_TX_WTHRESH << 16;
4160
4161         /* reinitialize tx_buffer_info */
4162         memset(ring->tx_buffer_info, 0,
4163                sizeof(struct igb_tx_buffer) * ring->count);
4164
4165         txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
4166         wr32(E1000_TXDCTL(reg_idx), txdctl);
4167 }
4168
4169 /**
4170  *  igb_configure_tx - Configure transmit Unit after Reset
4171  *  @adapter: board private structure
4172  *
4173  *  Configure the Tx unit of the MAC after a reset.
4174  **/
4175 static void igb_configure_tx(struct igb_adapter *adapter)
4176 {
4177         struct e1000_hw *hw = &adapter->hw;
4178         int i;
4179
4180         /* disable the queues */
4181         for (i = 0; i < adapter->num_tx_queues; i++)
4182                 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0);
4183
4184         wrfl();
4185         usleep_range(10000, 20000);
4186
4187         for (i = 0; i < adapter->num_tx_queues; i++)
4188                 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
4189 }
4190
4191 /**
4192  *  igb_setup_rx_resources - allocate Rx resources (Descriptors)
4193  *  @rx_ring: Rx descriptor ring (for a specific queue) to setup
4194  *
4195  *  Returns 0 on success, negative on failure
4196  **/
4197 int igb_setup_rx_resources(struct igb_ring *rx_ring)
4198 {
4199         struct device *dev = rx_ring->dev;
4200         int size;
4201
4202         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
4203
4204         rx_ring->rx_buffer_info = vmalloc(size);
4205         if (!rx_ring->rx_buffer_info)
4206                 goto err;
4207
4208         /* Round up to nearest 4K */
4209         rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
4210         rx_ring->size = ALIGN(rx_ring->size, 4096);
4211
4212         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4213                                            &rx_ring->dma, GFP_KERNEL);
4214         if (!rx_ring->desc)
4215                 goto err;
4216
4217         rx_ring->next_to_alloc = 0;
4218         rx_ring->next_to_clean = 0;
4219         rx_ring->next_to_use = 0;
4220
4221         return 0;
4222
4223 err:
4224         vfree(rx_ring->rx_buffer_info);
4225         rx_ring->rx_buffer_info = NULL;
4226         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
4227         return -ENOMEM;
4228 }
4229
4230 /**
4231  *  igb_setup_all_rx_resources - wrapper to allocate Rx resources
4232  *                               (Descriptors) for all queues
4233  *  @adapter: board private structure
4234  *
4235  *  Return 0 on success, negative on failure
4236  **/
4237 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
4238 {
4239         struct pci_dev *pdev = adapter->pdev;
4240         int i, err = 0;
4241
4242         for (i = 0; i < adapter->num_rx_queues; i++) {
4243                 err = igb_setup_rx_resources(adapter->rx_ring[i]);
4244                 if (err) {
4245                         dev_err(&pdev->dev,
4246                                 "Allocation for Rx Queue %u failed\n", i);
4247                         for (i--; i >= 0; i--)
4248                                 igb_free_rx_resources(adapter->rx_ring[i]);
4249                         break;
4250                 }
4251         }
4252
4253         return err;
4254 }
4255
4256 /**
4257  *  igb_setup_mrqc - configure the multiple receive queue control registers
4258  *  @adapter: Board private structure
4259  **/
4260 static void igb_setup_mrqc(struct igb_adapter *adapter)
4261 {
4262         struct e1000_hw *hw = &adapter->hw;
4263         u32 mrqc, rxcsum;
4264         u32 j, num_rx_queues;
4265         u32 rss_key[10];
4266
4267         netdev_rss_key_fill(rss_key, sizeof(rss_key));
4268         for (j = 0; j < 10; j++)
4269                 wr32(E1000_RSSRK(j), rss_key[j]);
4270
4271         num_rx_queues = adapter->rss_queues;
4272
4273         switch (hw->mac.type) {
4274         case e1000_82576:
4275                 /* 82576 supports 2 RSS queues for SR-IOV */
4276                 if (adapter->vfs_allocated_count)
4277                         num_rx_queues = 2;
4278                 break;
4279         default:
4280                 break;
4281         }
4282
4283         if (adapter->rss_indir_tbl_init != num_rx_queues) {
4284                 for (j = 0; j < IGB_RETA_SIZE; j++)
4285                         adapter->rss_indir_tbl[j] =
4286                         (j * num_rx_queues) / IGB_RETA_SIZE;
4287                 adapter->rss_indir_tbl_init = num_rx_queues;
4288         }
4289         igb_write_rss_indir_tbl(adapter);
4290
4291         /* Disable raw packet checksumming so that RSS hash is placed in
4292          * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
4293          * offloads as they are enabled by default
4294          */
4295         rxcsum = rd32(E1000_RXCSUM);
4296         rxcsum |= E1000_RXCSUM_PCSD;
4297
4298         if (adapter->hw.mac.type >= e1000_82576)
4299                 /* Enable Receive Checksum Offload for SCTP */
4300                 rxcsum |= E1000_RXCSUM_CRCOFL;
4301
4302         /* Don't need to set TUOFL or IPOFL, they default to 1 */
4303         wr32(E1000_RXCSUM, rxcsum);
4304
4305         /* Generate RSS hash based on packet types, TCP/UDP
4306          * port numbers and/or IPv4/v6 src and dst addresses
4307          */
4308         mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
4309                E1000_MRQC_RSS_FIELD_IPV4_TCP |
4310                E1000_MRQC_RSS_FIELD_IPV6 |
4311                E1000_MRQC_RSS_FIELD_IPV6_TCP |
4312                E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
4313
4314         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
4315                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
4316         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
4317                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
4318
4319         /* If VMDq is enabled then we set the appropriate mode for that, else
4320          * we default to RSS so that an RSS hash is calculated per packet even
4321          * if we are only using one queue
4322          */
4323         if (adapter->vfs_allocated_count) {
4324                 if (hw->mac.type > e1000_82575) {
4325                         /* Set the default pool for the PF's first queue */
4326                         u32 vtctl = rd32(E1000_VT_CTL);
4327
4328                         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
4329                                    E1000_VT_CTL_DISABLE_DEF_POOL);
4330                         vtctl |= adapter->vfs_allocated_count <<
4331                                 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
4332                         wr32(E1000_VT_CTL, vtctl);
4333                 }
4334                 if (adapter->rss_queues > 1)
4335                         mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_MQ;
4336                 else
4337                         mrqc |= E1000_MRQC_ENABLE_VMDQ;
4338         } else {
4339                 if (hw->mac.type != e1000_i211)
4340                         mrqc |= E1000_MRQC_ENABLE_RSS_MQ;
4341         }
4342         igb_vmm_control(adapter);
4343
4344         wr32(E1000_MRQC, mrqc);
4345 }
4346
4347 /**
4348  *  igb_setup_rctl - configure the receive control registers
4349  *  @adapter: Board private structure
4350  **/
4351 void igb_setup_rctl(struct igb_adapter *adapter)
4352 {
4353         struct e1000_hw *hw = &adapter->hw;
4354         u32 rctl;
4355
4356         rctl = rd32(E1000_RCTL);
4357
4358         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4359         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
4360
4361         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
4362                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
4363
4364         /* enable stripping of CRC. It's unlikely this will break BMC
4365          * redirection as it did with e1000. Newer features require
4366          * that the HW strips the CRC.
4367          */
4368         rctl |= E1000_RCTL_SECRC;
4369
4370         /* disable store bad packets and clear size bits. */
4371         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
4372
4373         /* enable LPE to allow for reception of jumbo frames */
4374         rctl |= E1000_RCTL_LPE;
4375
4376         /* disable queue 0 to prevent tail write w/o re-config */
4377         wr32(E1000_RXDCTL(0), 0);
4378
4379         /* Attention!!!  For SR-IOV PF driver operations you must enable
4380          * queue drop for all VF and PF queues to prevent head of line blocking
4381          * if an un-trusted VF does not provide descriptors to hardware.
4382          */
4383         if (adapter->vfs_allocated_count) {
4384                 /* set all queue drop enable bits */
4385                 wr32(E1000_QDE, ALL_QUEUES);
4386         }
4387
4388         /* This is useful for sniffing bad packets. */
4389         if (adapter->netdev->features & NETIF_F_RXALL) {
4390                 /* UPE and MPE will be handled by normal PROMISC logic
4391                  * in e1000e_set_rx_mode
4392                  */
4393                 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
4394                          E1000_RCTL_BAM | /* RX All Bcast Pkts */
4395                          E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
4396
4397                 rctl &= ~(E1000_RCTL_DPF | /* Allow filtered pause */
4398                           E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
4399                 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
4400                  * and that breaks VLANs.
4401                  */
4402         }
4403
4404         wr32(E1000_RCTL, rctl);
4405 }
4406
4407 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
4408                                    int vfn)
4409 {
4410         struct e1000_hw *hw = &adapter->hw;
4411         u32 vmolr;
4412
4413         if (size > MAX_JUMBO_FRAME_SIZE)
4414                 size = MAX_JUMBO_FRAME_SIZE;
4415
4416         vmolr = rd32(E1000_VMOLR(vfn));
4417         vmolr &= ~E1000_VMOLR_RLPML_MASK;
4418         vmolr |= size | E1000_VMOLR_LPE;
4419         wr32(E1000_VMOLR(vfn), vmolr);
4420
4421         return 0;
4422 }
4423
4424 static inline void igb_set_vf_vlan_strip(struct igb_adapter *adapter,
4425                                          int vfn, bool enable)
4426 {
4427         struct e1000_hw *hw = &adapter->hw;
4428         u32 val, reg;
4429
4430         if (hw->mac.type < e1000_82576)
4431                 return;
4432
4433         if (hw->mac.type == e1000_i350)
4434                 reg = E1000_DVMOLR(vfn);
4435         else
4436                 reg = E1000_VMOLR(vfn);
4437
4438         val = rd32(reg);
4439         if (enable)
4440                 val |= E1000_VMOLR_STRVLAN;
4441         else
4442                 val &= ~(E1000_VMOLR_STRVLAN);
4443         wr32(reg, val);
4444 }
4445
4446 static inline void igb_set_vmolr(struct igb_adapter *adapter,
4447                                  int vfn, bool aupe)
4448 {
4449         struct e1000_hw *hw = &adapter->hw;
4450         u32 vmolr;
4451
4452         /* This register exists only on 82576 and newer so if we are older then
4453          * we should exit and do nothing
4454          */
4455         if (hw->mac.type < e1000_82576)
4456                 return;
4457
4458         vmolr = rd32(E1000_VMOLR(vfn));
4459         if (aupe)
4460                 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */
4461         else
4462                 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
4463
4464         /* clear all bits that might not be set */
4465         vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
4466
4467         if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
4468                 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
4469         /* for VMDq only allow the VFs and pool 0 to accept broadcast and
4470          * multicast packets
4471          */
4472         if (vfn <= adapter->vfs_allocated_count)
4473                 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */
4474
4475         wr32(E1000_VMOLR(vfn), vmolr);
4476 }
4477
4478 /**
4479  *  igb_configure_rx_ring - Configure a receive ring after Reset
4480  *  @adapter: board private structure
4481  *  @ring: receive ring to be configured
4482  *
4483  *  Configure the Rx unit of the MAC after a reset.
4484  **/
4485 void igb_configure_rx_ring(struct igb_adapter *adapter,
4486                            struct igb_ring *ring)
4487 {
4488         struct e1000_hw *hw = &adapter->hw;
4489         union e1000_adv_rx_desc *rx_desc;
4490         u64 rdba = ring->dma;
4491         int reg_idx = ring->reg_idx;
4492         u32 srrctl = 0, rxdctl = 0;
4493
4494         /* disable the queue */
4495         wr32(E1000_RXDCTL(reg_idx), 0);
4496
4497         /* Set DMA base address registers */
4498         wr32(E1000_RDBAL(reg_idx),
4499              rdba & 0x00000000ffffffffULL);
4500         wr32(E1000_RDBAH(reg_idx), rdba >> 32);
4501         wr32(E1000_RDLEN(reg_idx),
4502              ring->count * sizeof(union e1000_adv_rx_desc));
4503
4504         /* initialize head and tail */
4505         ring->tail = adapter->io_addr + E1000_RDT(reg_idx);
4506         wr32(E1000_RDH(reg_idx), 0);
4507         writel(0, ring->tail);
4508
4509         /* set descriptor configuration */
4510         srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
4511         if (ring_uses_large_buffer(ring))
4512                 srrctl |= IGB_RXBUFFER_3072 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4513         else
4514                 srrctl |= IGB_RXBUFFER_2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
4515         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
4516         if (hw->mac.type >= e1000_82580)
4517                 srrctl |= E1000_SRRCTL_TIMESTAMP;
4518         /* Only set Drop Enable if we are supporting multiple queues */
4519         if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
4520                 srrctl |= E1000_SRRCTL_DROP_EN;
4521
4522         wr32(E1000_SRRCTL(reg_idx), srrctl);
4523
4524         /* set filtering for VMDQ pools */
4525         igb_set_vmolr(adapter, reg_idx & 0x7, true);
4526
4527         rxdctl |= IGB_RX_PTHRESH;
4528         rxdctl |= IGB_RX_HTHRESH << 8;
4529         rxdctl |= IGB_RX_WTHRESH << 16;
4530
4531         /* initialize rx_buffer_info */
4532         memset(ring->rx_buffer_info, 0,
4533                sizeof(struct igb_rx_buffer) * ring->count);
4534
4535         /* initialize Rx descriptor 0 */
4536         rx_desc = IGB_RX_DESC(ring, 0);
4537         rx_desc->wb.upper.length = 0;
4538
4539         /* enable receive descriptor fetching */
4540         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
4541         wr32(E1000_RXDCTL(reg_idx), rxdctl);
4542 }
4543
4544 static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
4545                                   struct igb_ring *rx_ring)
4546 {
4547         /* set build_skb and buffer size flags */
4548         clear_ring_build_skb_enabled(rx_ring);
4549         clear_ring_uses_large_buffer(rx_ring);
4550
4551         if (adapter->flags & IGB_FLAG_RX_LEGACY)
4552                 return;
4553
4554         set_ring_build_skb_enabled(rx_ring);
4555
4556 #if (PAGE_SIZE < 8192)
4557         if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
4558                 return;
4559
4560         set_ring_uses_large_buffer(rx_ring);
4561 #endif
4562 }
4563
4564 /**
4565  *  igb_configure_rx - Configure receive Unit after Reset
4566  *  @adapter: board private structure
4567  *
4568  *  Configure the Rx unit of the MAC after a reset.
4569  **/
4570 static void igb_configure_rx(struct igb_adapter *adapter)
4571 {
4572         int i;
4573
4574         /* set the correct pool for the PF default MAC address in entry 0 */
4575         igb_set_default_mac_filter(adapter);
4576
4577         /* Setup the HW Rx Head and Tail Descriptor Pointers and
4578          * the Base and Length of the Rx Descriptor Ring
4579          */
4580         for (i = 0; i < adapter->num_rx_queues; i++) {
4581                 struct igb_ring *rx_ring = adapter->rx_ring[i];
4582
4583                 igb_set_rx_buffer_len(adapter, rx_ring);
4584                 igb_configure_rx_ring(adapter, rx_ring);
4585         }
4586 }
4587
4588 /**
4589  *  igb_free_tx_resources - Free Tx Resources per Queue
4590  *  @tx_ring: Tx descriptor ring for a specific queue
4591  *
4592  *  Free all transmit software resources
4593  **/
4594 void igb_free_tx_resources(struct igb_ring *tx_ring)
4595 {
4596         igb_clean_tx_ring(tx_ring);
4597
4598         vfree(tx_ring->tx_buffer_info);
4599         tx_ring->tx_buffer_info = NULL;
4600
4601         /* if not set, then don't free */
4602         if (!tx_ring->desc)
4603                 return;
4604
4605         dma_free_coherent(tx_ring->dev, tx_ring->size,
4606                           tx_ring->desc, tx_ring->dma);
4607
4608         tx_ring->desc = NULL;
4609 }
4610
4611 /**
4612  *  igb_free_all_tx_resources - Free Tx Resources for All Queues
4613  *  @adapter: board private structure
4614  *
4615  *  Free all transmit software resources
4616  **/
4617 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
4618 {
4619         int i;
4620
4621         for (i = 0; i < adapter->num_tx_queues; i++)
4622                 if (adapter->tx_ring[i])
4623                         igb_free_tx_resources(adapter->tx_ring[i]);
4624 }
4625
4626 /**
4627  *  igb_clean_tx_ring - Free Tx Buffers
4628  *  @tx_ring: ring to be cleaned
4629  **/
4630 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
4631 {
4632         u16 i = tx_ring->next_to_clean;
4633         struct igb_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
4634
4635         while (i != tx_ring->next_to_use) {
4636                 union e1000_adv_tx_desc *eop_desc, *tx_desc;
4637
4638                 /* Free all the Tx ring sk_buffs */
4639                 dev_kfree_skb_any(tx_buffer->skb);
4640
4641                 /* unmap skb header data */
4642                 dma_unmap_single(tx_ring->dev,
4643                                  dma_unmap_addr(tx_buffer, dma),
4644                                  dma_unmap_len(tx_buffer, len),
4645                                  DMA_TO_DEVICE);
4646
4647                 /* check for eop_desc to determine the end of the packet */
4648                 eop_desc = tx_buffer->next_to_watch;
4649                 tx_desc = IGB_TX_DESC(tx_ring, i);
4650
4651                 /* unmap remaining buffers */
4652                 while (tx_desc != eop_desc) {
4653                         tx_buffer++;
4654                         tx_desc++;
4655                         i++;
4656                         if (unlikely(i == tx_ring->count)) {
4657                                 i = 0;
4658                                 tx_buffer = tx_ring->tx_buffer_info;
4659                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
4660                         }
4661
4662                         /* unmap any remaining paged data */
4663                         if (dma_unmap_len(tx_buffer, len))
4664                                 dma_unmap_page(tx_ring->dev,
4665                                                dma_unmap_addr(tx_buffer, dma),
4666                                                dma_unmap_len(tx_buffer, len),
4667                                                DMA_TO_DEVICE);
4668                 }
4669
4670                 /* move us one more past the eop_desc for start of next pkt */
4671                 tx_buffer++;
4672                 i++;
4673                 if (unlikely(i == tx_ring->count)) {
4674                         i = 0;
4675                         tx_buffer = tx_ring->tx_buffer_info;
4676                 }
4677         }
4678
4679         /* reset BQL for queue */
4680         netdev_tx_reset_queue(txring_txq(tx_ring));
4681
4682         /* reset next_to_use and next_to_clean */
4683         tx_ring->next_to_use = 0;
4684         tx_ring->next_to_clean = 0;
4685 }
4686
4687 /**
4688  *  igb_clean_all_tx_rings - Free Tx Buffers for all queues
4689  *  @adapter: board private structure
4690  **/
4691 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
4692 {
4693         int i;
4694
4695         for (i = 0; i < adapter->num_tx_queues; i++)
4696                 if (adapter->tx_ring[i])
4697                         igb_clean_tx_ring(adapter->tx_ring[i]);
4698 }
4699
4700 /**
4701  *  igb_free_rx_resources - Free Rx Resources
4702  *  @rx_ring: ring to clean the resources from
4703  *
4704  *  Free all receive software resources
4705  **/
4706 void igb_free_rx_resources(struct igb_ring *rx_ring)
4707 {
4708         igb_clean_rx_ring(rx_ring);
4709
4710         vfree(rx_ring->rx_buffer_info);
4711         rx_ring->rx_buffer_info = NULL;
4712
4713         /* if not set, then don't free */
4714         if (!rx_ring->desc)
4715                 return;
4716
4717         dma_free_coherent(rx_ring->dev, rx_ring->size,
4718                           rx_ring->desc, rx_ring->dma);
4719
4720         rx_ring->desc = NULL;
4721 }
4722
4723 /**
4724  *  igb_free_all_rx_resources - Free Rx Resources for All Queues
4725  *  @adapter: board private structure
4726  *
4727  *  Free all receive software resources
4728  **/
4729 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
4730 {
4731         int i;
4732
4733         for (i = 0; i < adapter->num_rx_queues; i++)
4734                 if (adapter->rx_ring[i])
4735                         igb_free_rx_resources(adapter->rx_ring[i]);
4736 }
4737
4738 /**
4739  *  igb_clean_rx_ring - Free Rx Buffers per Queue
4740  *  @rx_ring: ring to free buffers from
4741  **/
4742 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
4743 {
4744         u16 i = rx_ring->next_to_clean;
4745
4746         if (rx_ring->skb)
4747                 dev_kfree_skb(rx_ring->skb);
4748         rx_ring->skb = NULL;
4749
4750         /* Free all the Rx ring sk_buffs */
4751         while (i != rx_ring->next_to_alloc) {
4752                 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
4753
4754                 /* Invalidate cache lines that may have been written to by
4755                  * device so that we avoid corrupting memory.
4756                  */
4757                 dma_sync_single_range_for_cpu(rx_ring->dev,
4758                                               buffer_info->dma,
4759                                               buffer_info->page_offset,
4760                                               igb_rx_bufsz(rx_ring),
4761                                               DMA_FROM_DEVICE);
4762
4763                 /* free resources associated with mapping */
4764                 dma_unmap_page_attrs(rx_ring->dev,
4765                                      buffer_info->dma,
4766                                      igb_rx_pg_size(rx_ring),
4767                                      DMA_FROM_DEVICE,
4768                                      IGB_RX_DMA_ATTR);
4769                 __page_frag_cache_drain(buffer_info->page,
4770                                         buffer_info->pagecnt_bias);
4771
4772                 i++;
4773                 if (i == rx_ring->count)
4774                         i = 0;
4775         }
4776
4777         rx_ring->next_to_alloc = 0;
4778         rx_ring->next_to_clean = 0;
4779         rx_ring->next_to_use = 0;
4780 }
4781
4782 /**
4783  *  igb_clean_all_rx_rings - Free Rx Buffers for all queues
4784  *  @adapter: board private structure
4785  **/
4786 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
4787 {
4788         int i;
4789
4790         for (i = 0; i < adapter->num_rx_queues; i++)
4791                 if (adapter->rx_ring[i])
4792                         igb_clean_rx_ring(adapter->rx_ring[i]);
4793 }
4794
4795 /**
4796  *  igb_set_mac - Change the Ethernet Address of the NIC
4797  *  @netdev: network interface device structure
4798  *  @p: pointer to an address structure
4799  *
4800  *  Returns 0 on success, negative on failure
4801  **/
4802 static int igb_set_mac(struct net_device *netdev, void *p)
4803 {
4804         struct igb_adapter *adapter = netdev_priv(netdev);
4805         struct e1000_hw *hw = &adapter->hw;
4806         struct sockaddr *addr = p;
4807
4808         if (!is_valid_ether_addr(addr->sa_data))
4809                 return -EADDRNOTAVAIL;
4810
4811         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4812         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
4813
4814         /* set the correct pool for the new PF MAC address in entry 0 */
4815         igb_set_default_mac_filter(adapter);
4816
4817         return 0;
4818 }
4819
4820 /**
4821  *  igb_write_mc_addr_list - write multicast addresses to MTA
4822  *  @netdev: network interface device structure
4823  *
4824  *  Writes multicast address list to the MTA hash table.
4825  *  Returns: -ENOMEM on failure
4826  *           0 on no addresses written
4827  *           X on writing X addresses to MTA
4828  **/
4829 static int igb_write_mc_addr_list(struct net_device *netdev)
4830 {
4831         struct igb_adapter *adapter = netdev_priv(netdev);
4832         struct e1000_hw *hw = &adapter->hw;
4833         struct netdev_hw_addr *ha;
4834         u8  *mta_list;
4835         int i;
4836
4837         if (netdev_mc_empty(netdev)) {
4838                 /* nothing to program, so clear mc list */
4839                 igb_update_mc_addr_list(hw, NULL, 0);
4840                 igb_restore_vf_multicasts(adapter);
4841                 return 0;
4842         }
4843
4844         mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);
4845         if (!mta_list)
4846                 return -ENOMEM;
4847
4848         /* The shared function expects a packed array of only addresses. */
4849         i = 0;
4850         netdev_for_each_mc_addr(ha, netdev)
4851                 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
4852
4853         igb_update_mc_addr_list(hw, mta_list, i);
4854         kfree(mta_list);
4855
4856         return netdev_mc_count(netdev);
4857 }
4858
4859 static int igb_vlan_promisc_enable(struct igb_adapter *adapter)
4860 {
4861         struct e1000_hw *hw = &adapter->hw;
4862         u32 i, pf_id;
4863
4864         switch (hw->mac.type) {
4865         case e1000_i210:
4866         case e1000_i211:
4867         case e1000_i350:
4868                 /* VLAN filtering needed for VLAN prio filter */
4869                 if (adapter->netdev->features & NETIF_F_NTUPLE)
4870                         break;
4871                 /* fall through */
4872         case e1000_82576:
4873         case e1000_82580:
4874         case e1000_i354:
4875                 /* VLAN filtering needed for pool filtering */
4876                 if (adapter->vfs_allocated_count)
4877                         break;
4878                 /* fall through */
4879         default:
4880                 return 1;
4881         }
4882
4883         /* We are already in VLAN promisc, nothing to do */
4884         if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
4885                 return 0;
4886
4887         if (!adapter->vfs_allocated_count)
4888                 goto set_vfta;
4889
4890         /* Add PF to all active pools */
4891         pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4892
4893         for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4894                 u32 vlvf = rd32(E1000_VLVF(i));
4895
4896                 vlvf |= BIT(pf_id);
4897                 wr32(E1000_VLVF(i), vlvf);
4898         }
4899
4900 set_vfta:
4901         /* Set all bits in the VLAN filter table array */
4902         for (i = E1000_VLAN_FILTER_TBL_SIZE; i--;)
4903                 hw->mac.ops.write_vfta(hw, i, ~0U);
4904
4905         /* Set flag so we don't redo unnecessary work */
4906         adapter->flags |= IGB_FLAG_VLAN_PROMISC;
4907
4908         return 0;
4909 }
4910
4911 #define VFTA_BLOCK_SIZE 8
4912 static void igb_scrub_vfta(struct igb_adapter *adapter, u32 vfta_offset)
4913 {
4914         struct e1000_hw *hw = &adapter->hw;
4915         u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4916         u32 vid_start = vfta_offset * 32;
4917         u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4918         u32 i, vid, word, bits, pf_id;
4919
4920         /* guarantee that we don't scrub out management VLAN */
4921         vid = adapter->mng_vlan_id;
4922         if (vid >= vid_start && vid < vid_end)
4923                 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4924
4925         if (!adapter->vfs_allocated_count)
4926                 goto set_vfta;
4927
4928         pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
4929
4930         for (i = E1000_VLVF_ARRAY_SIZE; --i;) {
4931                 u32 vlvf = rd32(E1000_VLVF(i));
4932
4933                 /* pull VLAN ID from VLVF */
4934                 vid = vlvf & VLAN_VID_MASK;
4935
4936                 /* only concern ourselves with a certain range */
4937                 if (vid < vid_start || vid >= vid_end)
4938                         continue;
4939
4940                 if (vlvf & E1000_VLVF_VLANID_ENABLE) {
4941                         /* record VLAN ID in VFTA */
4942                         vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4943
4944                         /* if PF is part of this then continue */
4945                         if (test_bit(vid, adapter->active_vlans))
4946                                 continue;
4947                 }
4948
4949                 /* remove PF from the pool */
4950                 bits = ~BIT(pf_id);
4951                 bits &= rd32(E1000_VLVF(i));
4952                 wr32(E1000_VLVF(i), bits);
4953         }
4954
4955 set_vfta:
4956         /* extract values from active_vlans and write back to VFTA */
4957         for (i = VFTA_BLOCK_SIZE; i--;) {
4958                 vid = (vfta_offset + i) * 32;
4959                 word = vid / BITS_PER_LONG;
4960                 bits = vid % BITS_PER_LONG;
4961
4962                 vfta[i] |= adapter->active_vlans[word] >> bits;
4963
4964                 hw->mac.ops.write_vfta(hw, vfta_offset + i, vfta[i]);
4965         }
4966 }
4967
4968 static void igb_vlan_promisc_disable(struct igb_adapter *adapter)
4969 {
4970         u32 i;
4971
4972         /* We are not in VLAN promisc, nothing to do */
4973         if (!(adapter->flags & IGB_FLAG_VLAN_PROMISC))
4974                 return;
4975
4976         /* Set flag so we don't redo unnecessary work */
4977         adapter->flags &= ~IGB_FLAG_VLAN_PROMISC;
4978
4979         for (i = 0; i < E1000_VLAN_FILTER_TBL_SIZE; i += VFTA_BLOCK_SIZE)
4980                 igb_scrub_vfta(adapter, i);
4981 }
4982
4983 /**
4984  *  igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
4985  *  @netdev: network interface device structure
4986  *
4987  *  The set_rx_mode entry point is called whenever the unicast or multicast
4988  *  address lists or the network interface flags are updated.  This routine is
4989  *  responsible for configuring the hardware for proper unicast, multicast,
4990  *  promiscuous mode, and all-multi behavior.
4991  **/
4992 static void igb_set_rx_mode(struct net_device *netdev)
4993 {
4994         struct igb_adapter *adapter = netdev_priv(netdev);
4995         struct e1000_hw *hw = &adapter->hw;
4996         unsigned int vfn = adapter->vfs_allocated_count;
4997         u32 rctl = 0, vmolr = 0, rlpml = MAX_JUMBO_FRAME_SIZE;
4998         int count;
4999
5000         /* Check for Promiscuous and All Multicast modes */
5001         if (netdev->flags & IFF_PROMISC) {
5002                 rctl |= E1000_RCTL_UPE | E1000_RCTL_MPE;
5003                 vmolr |= E1000_VMOLR_MPME;
5004
5005                 /* enable use of UTA filter to force packets to default pool */
5006                 if (hw->mac.type == e1000_82576)
5007                         vmolr |= E1000_VMOLR_ROPE;
5008         } else {
5009                 if (netdev->flags & IFF_ALLMULTI) {
5010                         rctl |= E1000_RCTL_MPE;
5011                         vmolr |= E1000_VMOLR_MPME;
5012                 } else {
5013                         /* Write addresses to the MTA, if the attempt fails
5014                          * then we should just turn on promiscuous mode so
5015                          * that we can at least receive multicast traffic
5016                          */
5017                         count = igb_write_mc_addr_list(netdev);
5018                         if (count < 0) {
5019                                 rctl |= E1000_RCTL_MPE;
5020                                 vmolr |= E1000_VMOLR_MPME;
5021                         } else if (count) {
5022                                 vmolr |= E1000_VMOLR_ROMPE;
5023                         }
5024                 }
5025         }
5026
5027         /* Write addresses to available RAR registers, if there is not
5028          * sufficient space to store all the addresses then enable
5029          * unicast promiscuous mode
5030          */
5031         if (__dev_uc_sync(netdev, igb_uc_sync, igb_uc_unsync)) {
5032                 rctl |= E1000_RCTL_UPE;
5033                 vmolr |= E1000_VMOLR_ROPE;
5034         }
5035
5036         /* enable VLAN filtering by default */
5037         rctl |= E1000_RCTL_VFE;
5038
5039         /* disable VLAN filtering for modes that require it */
5040         if ((netdev->flags & IFF_PROMISC) ||
5041             (netdev->features & NETIF_F_RXALL)) {
5042                 /* if we fail to set all rules then just clear VFE */
5043                 if (igb_vlan_promisc_enable(adapter))
5044                         rctl &= ~E1000_RCTL_VFE;
5045         } else {
5046                 igb_vlan_promisc_disable(adapter);
5047         }
5048
5049         /* update state of unicast, multicast, and VLAN filtering modes */
5050         rctl |= rd32(E1000_RCTL) & ~(E1000_RCTL_UPE | E1000_RCTL_MPE |
5051                                      E1000_RCTL_VFE);
5052         wr32(E1000_RCTL, rctl);
5053
5054 #if (PAGE_SIZE < 8192)
5055         if (!adapter->vfs_allocated_count) {
5056                 if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5057                         rlpml = IGB_MAX_FRAME_BUILD_SKB;
5058         }
5059 #endif
5060         wr32(E1000_RLPML, rlpml);
5061
5062         /* In order to support SR-IOV and eventually VMDq it is necessary to set
5063          * the VMOLR to enable the appropriate modes.  Without this workaround
5064          * we will have issues with VLAN tag stripping not being done for frames
5065          * that are only arriving because we are the default pool
5066          */
5067         if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
5068                 return;
5069
5070         /* set UTA to appropriate mode */
5071         igb_set_uta(adapter, !!(vmolr & E1000_VMOLR_ROPE));
5072
5073         vmolr |= rd32(E1000_VMOLR(vfn)) &
5074                  ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
5075
5076         /* enable Rx jumbo frames, restrict as needed to support build_skb */
5077         vmolr &= ~E1000_VMOLR_RLPML_MASK;
5078 #if (PAGE_SIZE < 8192)
5079         if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB)
5080                 vmolr |= IGB_MAX_FRAME_BUILD_SKB;
5081         else
5082 #endif
5083                 vmolr |= MAX_JUMBO_FRAME_SIZE;
5084         vmolr |= E1000_VMOLR_LPE;
5085
5086         wr32(E1000_VMOLR(vfn), vmolr);
5087
5088         igb_restore_vf_multicasts(adapter);
5089 }
5090
5091 static void igb_check_wvbr(struct igb_adapter *adapter)
5092 {
5093         struct e1000_hw *hw = &adapter->hw;
5094         u32 wvbr = 0;
5095
5096         switch (hw->mac.type) {
5097         case e1000_82576:
5098         case e1000_i350:
5099                 wvbr = rd32(E1000_WVBR);
5100                 if (!wvbr)
5101                         return;
5102                 break;
5103         default:
5104                 break;
5105         }
5106
5107         adapter->wvbr |= wvbr;
5108 }
5109
5110 #define IGB_STAGGERED_QUEUE_OFFSET 8
5111
5112 static void igb_spoof_check(struct igb_adapter *adapter)
5113 {
5114         int j;
5115
5116         if (!adapter->wvbr)
5117                 return;
5118
5119         for (j = 0; j < adapter->vfs_allocated_count; j++) {
5120                 if (adapter->wvbr & BIT(j) ||
5121                     adapter->wvbr & BIT(j + IGB_STAGGERED_QUEUE_OFFSET)) {
5122                         dev_warn(&adapter->pdev->dev,
5123                                 "Spoof event(s) detected on VF %d\n", j);
5124                         adapter->wvbr &=
5125                                 ~(BIT(j) |
5126                                   BIT(j + IGB_STAGGERED_QUEUE_OFFSET));
5127                 }
5128         }
5129 }
5130
5131 /* Need to wait a few seconds after link up to get diagnostic information from
5132  * the phy
5133  */
5134 static void igb_update_phy_info(struct timer_list *t)
5135 {
5136         struct igb_adapter *adapter = from_timer(adapter, t, phy_info_timer);
5137         igb_get_phy_info(&adapter->hw);
5138 }
5139
5140 /**
5141  *  igb_has_link - check shared code for link and determine up/down
5142  *  @adapter: pointer to driver private info
5143  **/
5144 bool igb_has_link(struct igb_adapter *adapter)
5145 {
5146         struct e1000_hw *hw = &adapter->hw;
5147         bool link_active = false;
5148
5149         /* get_link_status is set on LSC (link status) interrupt or
5150          * rx sequence error interrupt.  get_link_status will stay
5151          * false until the e1000_check_for_link establishes link
5152          * for copper adapters ONLY
5153          */
5154         switch (hw->phy.media_type) {
5155         case e1000_media_type_copper:
5156                 if (!hw->mac.get_link_status)
5157                         return true;
5158                 /* fall through */
5159         case e1000_media_type_internal_serdes:
5160                 hw->mac.ops.check_for_link(hw);
5161                 link_active = !hw->mac.get_link_status;
5162                 break;
5163         default:
5164         case e1000_media_type_unknown:
5165                 break;
5166         }
5167
5168         if (((hw->mac.type == e1000_i210) ||
5169              (hw->mac.type == e1000_i211)) &&
5170              (hw->phy.id == I210_I_PHY_ID)) {
5171                 if (!netif_carrier_ok(adapter->netdev)) {
5172                         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5173                 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) {
5174                         adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE;
5175                         adapter->link_check_timeout = jiffies;
5176                 }
5177         }
5178
5179         return link_active;
5180 }
5181
5182 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
5183 {
5184         bool ret = false;
5185         u32 ctrl_ext, thstat;
5186
5187         /* check for thermal sensor event on i350 copper only */
5188         if (hw->mac.type == e1000_i350) {
5189                 thstat = rd32(E1000_THSTAT);
5190                 ctrl_ext = rd32(E1000_CTRL_EXT);
5191
5192                 if ((hw->phy.media_type == e1000_media_type_copper) &&
5193                     !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII))
5194                         ret = !!(thstat & event);
5195         }
5196
5197         return ret;
5198 }
5199
5200 /**
5201  *  igb_check_lvmmc - check for malformed packets received
5202  *  and indicated in LVMMC register
5203  *  @adapter: pointer to adapter
5204  **/
5205 static void igb_check_lvmmc(struct igb_adapter *adapter)
5206 {
5207         struct e1000_hw *hw = &adapter->hw;
5208         u32 lvmmc;
5209
5210         lvmmc = rd32(E1000_LVMMC);
5211         if (lvmmc) {
5212                 if (unlikely(net_ratelimit())) {
5213                         netdev_warn(adapter->netdev,
5214                                     "malformed Tx packet detected and dropped, LVMMC:0x%08x\n",
5215                                     lvmmc);
5216                 }
5217         }
5218 }
5219
5220 /**
5221  *  igb_watchdog - Timer Call-back
5222  *  @data: pointer to adapter cast into an unsigned long
5223  **/
5224 static void igb_watchdog(struct timer_list *t)
5225 {
5226         struct igb_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5227         /* Do the rest outside of interrupt context */
5228         schedule_work(&adapter->watchdog_task);
5229 }
5230
5231 static void igb_watchdog_task(struct work_struct *work)
5232 {
5233         struct igb_adapter *adapter = container_of(work,
5234                                                    struct igb_adapter,
5235                                                    watchdog_task);
5236         struct e1000_hw *hw = &adapter->hw;
5237         struct e1000_phy_info *phy = &hw->phy;
5238         struct net_device *netdev = adapter->netdev;
5239         u32 link;
5240         int i;
5241         u32 connsw;
5242         u16 phy_data, retry_count = 20;
5243
5244         link = igb_has_link(adapter);
5245
5246         if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) {
5247                 if (time_after(jiffies, (adapter->link_check_timeout + HZ)))
5248                         adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE;
5249                 else
5250                         link = false;
5251         }
5252
5253         /* Force link down if we have fiber to swap to */
5254         if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5255                 if (hw->phy.media_type == e1000_media_type_copper) {
5256                         connsw = rd32(E1000_CONNSW);
5257                         if (!(connsw & E1000_CONNSW_AUTOSENSE_EN))
5258                                 link = 0;
5259                 }
5260         }
5261         if (link) {
5262                 /* Perform a reset if the media type changed. */
5263                 if (hw->dev_spec._82575.media_changed) {
5264                         hw->dev_spec._82575.media_changed = false;
5265                         adapter->flags |= IGB_FLAG_MEDIA_RESET;
5266                         igb_reset(adapter);
5267                 }
5268                 /* Cancel scheduled suspend requests. */
5269                 pm_runtime_resume(netdev->dev.parent);
5270
5271                 if (!netif_carrier_ok(netdev)) {
5272                         u32 ctrl;
5273
5274                         hw->mac.ops.get_speed_and_duplex(hw,
5275                                                          &adapter->link_speed,
5276                                                          &adapter->link_duplex);
5277
5278                         ctrl = rd32(E1000_CTRL);
5279                         /* Links status message must follow this format */
5280                         netdev_info(netdev,
5281                                "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5282                                netdev->name,
5283                                adapter->link_speed,
5284                                adapter->link_duplex == FULL_DUPLEX ?
5285                                "Full" : "Half",
5286                                (ctrl & E1000_CTRL_TFCE) &&
5287                                (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
5288                                (ctrl & E1000_CTRL_RFCE) ?  "RX" :
5289                                (ctrl & E1000_CTRL_TFCE) ?  "TX" : "None");
5290
5291                         /* disable EEE if enabled */
5292                         if ((adapter->flags & IGB_FLAG_EEE) &&
5293                                 (adapter->link_duplex == HALF_DUPLEX)) {
5294                                 dev_info(&adapter->pdev->dev,
5295                                 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n");
5296                                 adapter->hw.dev_spec._82575.eee_disable = true;
5297                                 adapter->flags &= ~IGB_FLAG_EEE;
5298                         }
5299
5300                         /* check if SmartSpeed worked */
5301                         igb_check_downshift(hw);
5302                         if (phy->speed_downgraded)
5303                                 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n");
5304
5305                         /* check for thermal sensor event */
5306                         if (igb_thermal_sensor_event(hw,
5307                             E1000_THSTAT_LINK_THROTTLE))
5308                                 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n");
5309
5310                         /* adjust timeout factor according to speed/duplex */
5311                         adapter->tx_timeout_factor = 1;
5312                         switch (adapter->link_speed) {
5313                         case SPEED_10:
5314                                 adapter->tx_timeout_factor = 14;
5315                                 break;
5316                         case SPEED_100:
5317                                 /* maybe add some timeout factor ? */
5318                                 break;
5319                         }
5320
5321                         if (adapter->link_speed != SPEED_1000)
5322                                 goto no_wait;
5323
5324                         /* wait for Remote receiver status OK */
5325 retry_read_status:
5326                         if (!igb_read_phy_reg(hw, PHY_1000T_STATUS,
5327                                               &phy_data)) {
5328                                 if (!(phy_data & SR_1000T_REMOTE_RX_STATUS) &&
5329                                     retry_count) {
5330                                         msleep(100);
5331                                         retry_count--;
5332                                         goto retry_read_status;
5333                                 } else if (!retry_count) {
5334                                         dev_err(&adapter->pdev->dev, "exceed max 2 second\n");
5335                                 }
5336                         } else {
5337                                 dev_err(&adapter->pdev->dev, "read 1000Base-T Status Reg\n");
5338                         }
5339 no_wait:
5340                         netif_carrier_on(netdev);
5341
5342                         igb_ping_all_vfs(adapter);
5343                         igb_check_vf_rate_limit(adapter);
5344
5345                         /* link state has changed, schedule phy info update */
5346                         if (!test_bit(__IGB_DOWN, &adapter->state))
5347                                 mod_timer(&adapter->phy_info_timer,
5348                                           round_jiffies(jiffies + 2 * HZ));
5349                 }
5350         } else {
5351                 if (netif_carrier_ok(netdev)) {
5352                         adapter->link_speed = 0;
5353                         adapter->link_duplex = 0;
5354
5355                         /* check for thermal sensor event */
5356                         if (igb_thermal_sensor_event(hw,
5357                             E1000_THSTAT_PWR_DOWN)) {
5358                                 netdev_err(netdev, "The network adapter was stopped because it overheated\n");
5359                         }
5360
5361                         /* Links status message must follow this format */
5362                         netdev_info(netdev, "igb: %s NIC Link is Down\n",
5363                                netdev->name);
5364                         netif_carrier_off(netdev);
5365
5366                         igb_ping_all_vfs(adapter);
5367
5368                         /* link state has changed, schedule phy info update */
5369                         if (!test_bit(__IGB_DOWN, &adapter->state))
5370                                 mod_timer(&adapter->phy_info_timer,
5371                                           round_jiffies(jiffies + 2 * HZ));
5372
5373                         /* link is down, time to check for alternate media */
5374                         if (adapter->flags & IGB_FLAG_MAS_ENABLE) {
5375                                 igb_check_swap_media(adapter);
5376                                 if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5377                                         schedule_work(&adapter->reset_task);
5378                                         /* return immediately */
5379                                         return;
5380                                 }
5381                         }
5382                         pm_schedule_suspend(netdev->dev.parent,
5383                                             MSEC_PER_SEC * 5);
5384
5385                 /* also check for alternate media here */
5386                 } else if (!netif_carrier_ok(netdev) &&
5387                            (adapter->flags & IGB_FLAG_MAS_ENABLE)) {
5388                         igb_check_swap_media(adapter);
5389                         if (adapter->flags & IGB_FLAG_MEDIA_RESET) {
5390                                 schedule_work(&adapter->reset_task);
5391                                 /* return immediately */
5392                                 return;
5393                         }
5394                 }
5395         }
5396
5397         spin_lock(&adapter->stats64_lock);
5398         igb_update_stats(adapter);
5399         spin_unlock(&adapter->stats64_lock);
5400
5401         for (i = 0; i < adapter->num_tx_queues; i++) {
5402                 struct igb_ring *tx_ring = adapter->tx_ring[i];
5403                 if (!netif_carrier_ok(netdev)) {
5404                         /* We've lost link, so the controller stops DMA,
5405                          * but we've got queued Tx work that's never going
5406                          * to get done, so reset controller to flush Tx.
5407                          * (Do the reset outside of interrupt context).
5408                          */
5409                         if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
5410                                 adapter->tx_timeout_count++;
5411                                 schedule_work(&adapter->reset_task);
5412                                 /* return immediately since reset is imminent */
5413                                 return;
5414                         }
5415                 }
5416
5417                 /* Force detection of hung controller every watchdog period */
5418                 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5419         }
5420
5421         /* Cause software interrupt to ensure Rx ring is cleaned */
5422         if (adapter->flags & IGB_FLAG_HAS_MSIX) {
5423                 u32 eics = 0;
5424
5425                 for (i = 0; i < adapter->num_q_vectors; i++)
5426                         eics |= adapter->q_vector[i]->eims_value;
5427                 wr32(E1000_EICS, eics);
5428         } else {
5429                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
5430         }
5431
5432         igb_spoof_check(adapter);
5433         igb_ptp_rx_hang(adapter);
5434         igb_ptp_tx_hang(adapter);
5435
5436         /* Check LVMMC register on i350/i354 only */
5437         if ((adapter->hw.mac.type == e1000_i350) ||
5438             (adapter->hw.mac.type == e1000_i354))
5439                 igb_check_lvmmc(adapter);
5440
5441         /* Reset the timer */
5442         if (!test_bit(__IGB_DOWN, &adapter->state)) {
5443                 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)
5444                         mod_timer(&adapter->watchdog_timer,
5445                                   round_jiffies(jiffies +  HZ));
5446                 else
5447                         mod_timer(&adapter->watchdog_timer,
5448                                   round_jiffies(jiffies + 2 * HZ));
5449         }
5450 }
5451
5452 enum latency_range {
5453         lowest_latency = 0,
5454         low_latency = 1,
5455         bulk_latency = 2,
5456         latency_invalid = 255
5457 };
5458
5459 /**
5460  *  igb_update_ring_itr - update the dynamic ITR value based on packet size
5461  *  @q_vector: pointer to q_vector
5462  *
5463  *  Stores a new ITR value based on strictly on packet size.  This
5464  *  algorithm is less sophisticated than that used in igb_update_itr,
5465  *  due to the difficulty of synchronizing statistics across multiple
5466  *  receive rings.  The divisors and thresholds used by this function
5467  *  were determined based on theoretical maximum wire speed and testing
5468  *  data, in order to minimize response time while increasing bulk
5469  *  throughput.
5470  *  This functionality is controlled by ethtool's coalescing settings.
5471  *  NOTE:  This function is called only when operating in a multiqueue
5472  *         receive environment.
5473  **/
5474 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
5475 {
5476         int new_val = q_vector->itr_val;
5477         int avg_wire_size = 0;
5478         struct igb_adapter *adapter = q_vector->adapter;
5479         unsigned int packets;
5480
5481         /* For non-gigabit speeds, just fix the interrupt rate at 4000
5482          * ints/sec - ITR timer value of 120 ticks.
5483          */
5484         if (adapter->link_speed != SPEED_1000) {
5485                 new_val = IGB_4K_ITR;
5486                 goto set_itr_val;
5487         }
5488
5489         packets = q_vector->rx.total_packets;
5490         if (packets)
5491                 avg_wire_size = q_vector->rx.total_bytes / packets;
5492
5493         packets = q_vector->tx.total_packets;
5494         if (packets)
5495                 avg_wire_size = max_t(u32, avg_wire_size,
5496                                       q_vector->tx.total_bytes / packets);
5497
5498         /* if avg_wire_size isn't set no work was done */
5499         if (!avg_wire_size)
5500                 goto clear_counts;
5501
5502         /* Add 24 bytes to size to account for CRC, preamble, and gap */
5503         avg_wire_size += 24;
5504
5505         /* Don't starve jumbo frames */
5506         avg_wire_size = min(avg_wire_size, 3000);
5507
5508         /* Give a little boost to mid-size frames */
5509         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
5510                 new_val = avg_wire_size / 3;
5511         else
5512                 new_val = avg_wire_size / 2;
5513
5514         /* conservative mode (itr 3) eliminates the lowest_latency setting */
5515         if (new_val < IGB_20K_ITR &&
5516             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5517              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5518                 new_val = IGB_20K_ITR;
5519
5520 set_itr_val:
5521         if (new_val != q_vector->itr_val) {
5522                 q_vector->itr_val = new_val;
5523                 q_vector->set_itr = 1;
5524         }
5525 clear_counts:
5526         q_vector->rx.total_bytes = 0;
5527         q_vector->rx.total_packets = 0;
5528         q_vector->tx.total_bytes = 0;
5529         q_vector->tx.total_packets = 0;
5530 }
5531
5532 /**
5533  *  igb_update_itr - update the dynamic ITR value based on statistics
5534  *  @q_vector: pointer to q_vector
5535  *  @ring_container: ring info to update the itr for
5536  *
5537  *  Stores a new ITR value based on packets and byte
5538  *  counts during the last interrupt.  The advantage of per interrupt
5539  *  computation is faster updates and more accurate ITR for the current
5540  *  traffic pattern.  Constants in this function were computed
5541  *  based on theoretical maximum wire speed and thresholds were set based
5542  *  on testing data as well as attempting to minimize response time
5543  *  while increasing bulk throughput.
5544  *  This functionality is controlled by ethtool's coalescing settings.
5545  *  NOTE:  These calculations are only valid when operating in a single-
5546  *         queue environment.
5547  **/
5548 static void igb_update_itr(struct igb_q_vector *q_vector,
5549                            struct igb_ring_container *ring_container)
5550 {
5551         unsigned int packets = ring_container->total_packets;
5552         unsigned int bytes = ring_container->total_bytes;
5553         u8 itrval = ring_container->itr;
5554
5555         /* no packets, exit with status unchanged */
5556         if (packets == 0)
5557                 return;
5558
5559         switch (itrval) {
5560         case lowest_latency:
5561                 /* handle TSO and jumbo frames */
5562                 if (bytes/packets > 8000)
5563                         itrval = bulk_latency;
5564                 else if ((packets < 5) && (bytes > 512))
5565                         itrval = low_latency;
5566                 break;
5567         case low_latency:  /* 50 usec aka 20000 ints/s */
5568                 if (bytes > 10000) {
5569                         /* this if handles the TSO accounting */
5570                         if (bytes/packets > 8000)
5571                                 itrval = bulk_latency;
5572                         else if ((packets < 10) || ((bytes/packets) > 1200))
5573                                 itrval = bulk_latency;
5574                         else if ((packets > 35))
5575                                 itrval = lowest_latency;
5576                 } else if (bytes/packets > 2000) {
5577                         itrval = bulk_latency;
5578                 } else if (packets <= 2 && bytes < 512) {
5579                         itrval = lowest_latency;
5580                 }
5581                 break;
5582         case bulk_latency: /* 250 usec aka 4000 ints/s */
5583                 if (bytes > 25000) {
5584                         if (packets > 35)
5585                                 itrval = low_latency;
5586                 } else if (bytes < 1500) {
5587                         itrval = low_latency;
5588                 }
5589                 break;
5590         }
5591
5592         /* clear work counters since we have the values we need */
5593         ring_container->total_bytes = 0;
5594         ring_container->total_packets = 0;
5595
5596         /* write updated itr to ring container */
5597         ring_container->itr = itrval;
5598 }
5599
5600 static void igb_set_itr(struct igb_q_vector *q_vector)
5601 {
5602         struct igb_adapter *adapter = q_vector->adapter;
5603         u32 new_itr = q_vector->itr_val;
5604         u8 current_itr = 0;
5605
5606         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
5607         if (adapter->link_speed != SPEED_1000) {
5608                 current_itr = 0;
5609                 new_itr = IGB_4K_ITR;
5610                 goto set_itr_now;
5611         }
5612
5613         igb_update_itr(q_vector, &q_vector->tx);
5614         igb_update_itr(q_vector, &q_vector->rx);
5615
5616         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
5617
5618         /* conservative mode (itr 3) eliminates the lowest_latency setting */
5619         if (current_itr == lowest_latency &&
5620             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
5621              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
5622                 current_itr = low_latency;
5623
5624         switch (current_itr) {
5625         /* counts and packets in update_itr are dependent on these numbers */
5626         case lowest_latency:
5627                 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
5628                 break;
5629         case low_latency:
5630                 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
5631                 break;
5632         case bulk_latency:
5633                 new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
5634                 break;
5635         default:
5636                 break;
5637         }
5638
5639 set_itr_now:
5640         if (new_itr != q_vector->itr_val) {
5641                 /* this attempts to bias the interrupt rate towards Bulk
5642                  * by adding intermediate steps when interrupt rate is
5643                  * increasing
5644                  */
5645                 new_itr = new_itr > q_vector->itr_val ?
5646                           max((new_itr * q_vector->itr_val) /
5647                           (new_itr + (q_vector->itr_val >> 2)),
5648                           new_itr) : new_itr;
5649                 /* Don't write the value here; it resets the adapter's
5650                  * internal timer, and causes us to delay far longer than
5651                  * we should between interrupts.  Instead, we write the ITR
5652                  * value at the beginning of the next interrupt so the timing
5653                  * ends up being correct.
5654                  */
5655                 q_vector->itr_val = new_itr;
5656                 q_vector->set_itr = 1;
5657         }
5658 }
5659
5660 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring,
5661                             struct igb_tx_buffer *first,
5662                             u32 vlan_macip_lens, u32 type_tucmd,
5663                             u32 mss_l4len_idx)
5664 {
5665         struct e1000_adv_tx_context_desc *context_desc;
5666         u16 i = tx_ring->next_to_use;
5667         struct timespec64 ts;
5668
5669         context_desc = IGB_TX_CTXTDESC(tx_ring, i);
5670
5671         i++;
5672         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
5673
5674         /* set bits to identify this as an advanced context descriptor */
5675         type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
5676
5677         /* For 82575, context index must be unique per ring. */
5678         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
5679                 mss_l4len_idx |= tx_ring->reg_idx << 4;
5680
5681         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
5682         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
5683         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
5684
5685         /* We assume there is always a valid tx time available. Invalid times
5686          * should have been handled by the upper layers.
5687          */
5688         if (tx_ring->launchtime_enable) {
5689                 ts = ns_to_timespec64(first->skb->tstamp);
5690                 context_desc->seqnum_seed = cpu_to_le32(ts.tv_nsec / 32);
5691         } else {
5692                 context_desc->seqnum_seed = 0;
5693         }
5694 }
5695
5696 static int igb_tso(struct igb_ring *tx_ring,
5697                    struct igb_tx_buffer *first,
5698                    u8 *hdr_len)
5699 {
5700         u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
5701         struct sk_buff *skb = first->skb;
5702         union {
5703                 struct iphdr *v4;
5704                 struct ipv6hdr *v6;
5705                 unsigned char *hdr;
5706         } ip;
5707         union {
5708                 struct tcphdr *tcp;
5709                 unsigned char *hdr;
5710         } l4;
5711         u32 paylen, l4_offset;
5712         int err;
5713
5714         if (skb->ip_summed != CHECKSUM_PARTIAL)
5715                 return 0;
5716
5717         if (!skb_is_gso(skb))
5718                 return 0;
5719
5720         err = skb_cow_head(skb, 0);
5721         if (err < 0)
5722                 return err;
5723
5724         ip.hdr = skb_network_header(skb);
5725         l4.hdr = skb_checksum_start(skb);
5726
5727         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5728         type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
5729
5730         /* initialize outer IP header fields */
5731         if (ip.v4->version == 4) {
5732                 unsigned char *csum_start = skb_checksum_start(skb);
5733                 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
5734
5735                 /* IP header will have to cancel out any data that
5736                  * is not a part of the outer IP header
5737                  */
5738                 ip.v4->check = csum_fold(csum_partial(trans_start,
5739                                                       csum_start - trans_start,
5740                                                       0));
5741                 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
5742
5743                 ip.v4->tot_len = 0;
5744                 first->tx_flags |= IGB_TX_FLAGS_TSO |
5745                                    IGB_TX_FLAGS_CSUM |
5746                                    IGB_TX_FLAGS_IPV4;
5747         } else {
5748                 ip.v6->payload_len = 0;
5749                 first->tx_flags |= IGB_TX_FLAGS_TSO |
5750                                    IGB_TX_FLAGS_CSUM;
5751         }
5752
5753         /* determine offset of inner transport header */
5754         l4_offset = l4.hdr - skb->data;
5755
5756         /* compute length of segmentation header */
5757         *hdr_len = (l4.tcp->doff * 4) + l4_offset;
5758
5759         /* remove payload length from inner checksum */
5760         paylen = skb->len - l4_offset;
5761         csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
5762
5763         /* update gso size and bytecount with header size */
5764         first->gso_segs = skb_shinfo(skb)->gso_segs;
5765         first->bytecount += (first->gso_segs - 1) * *hdr_len;
5766
5767         /* MSS L4LEN IDX */
5768         mss_l4len_idx = (*hdr_len - l4_offset) << E1000_ADVTXD_L4LEN_SHIFT;
5769         mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
5770
5771         /* VLAN MACLEN IPLEN */
5772         vlan_macip_lens = l4.hdr - ip.hdr;
5773         vlan_macip_lens |= (ip.hdr - skb->data) << E1000_ADVTXD_MACLEN_SHIFT;
5774         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
5775
5776         igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens,
5777                         type_tucmd, mss_l4len_idx);
5778
5779         return 1;
5780 }
5781
5782 static inline bool igb_ipv6_csum_is_sctp(struct sk_buff *skb)
5783 {
5784         unsigned int offset = 0;
5785
5786         ipv6_find_hdr(skb, &offset, IPPROTO_SCTP, NULL, NULL);
5787
5788         return offset == skb_checksum_start_offset(skb);
5789 }
5790
5791 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
5792 {
5793         struct sk_buff *skb = first->skb;
5794         u32 vlan_macip_lens = 0;
5795         u32 type_tucmd = 0;
5796
5797         if (skb->ip_summed != CHECKSUM_PARTIAL) {
5798 csum_failed:
5799                 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN) &&
5800                     !tx_ring->launchtime_enable)
5801                         return;
5802                 goto no_csum;
5803         }
5804
5805         switch (skb->csum_offset) {
5806         case offsetof(struct tcphdr, check):
5807                 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
5808                 /* fall through */
5809         case offsetof(struct udphdr, check):
5810                 break;
5811         case offsetof(struct sctphdr, checksum):
5812                 /* validate that this is actually an SCTP request */
5813                 if (((first->protocol == htons(ETH_P_IP)) &&
5814                      (ip_hdr(skb)->protocol == IPPROTO_SCTP)) ||
5815                     ((first->protocol == htons(ETH_P_IPV6)) &&
5816                      igb_ipv6_csum_is_sctp(skb))) {
5817                         type_tucmd = E1000_ADVTXD_TUCMD_L4T_SCTP;
5818                         break;
5819                 }
5820                 /* fall through */
5821         default:
5822                 skb_checksum_help(skb);
5823                 goto csum_failed;
5824         }
5825
5826         /* update TX checksum flag */
5827         first->tx_flags |= IGB_TX_FLAGS_CSUM;
5828         vlan_macip_lens = skb_checksum_start_offset(skb) -
5829                           skb_network_offset(skb);
5830 no_csum:
5831         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
5832         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
5833
5834         igb_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0);
5835 }
5836
5837 #define IGB_SET_FLAG(_input, _flag, _result) \
5838         ((_flag <= _result) ? \
5839          ((u32)(_input & _flag) * (_result / _flag)) : \
5840          ((u32)(_input & _flag) / (_flag / _result)))
5841
5842 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
5843 {
5844         /* set type for advanced descriptor with frame checksum insertion */
5845         u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
5846                        E1000_ADVTXD_DCMD_DEXT |
5847                        E1000_ADVTXD_DCMD_IFCS;
5848
5849         /* set HW vlan bit if vlan is present */
5850         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
5851                                  (E1000_ADVTXD_DCMD_VLE));
5852
5853         /* set segmentation bits for TSO */
5854         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
5855                                  (E1000_ADVTXD_DCMD_TSE));
5856
5857         /* set timestamp bit if present */
5858         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
5859                                  (E1000_ADVTXD_MAC_TSTAMP));
5860
5861         /* insert frame checksum */
5862         cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
5863
5864         return cmd_type;
5865 }
5866
5867 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
5868                                  union e1000_adv_tx_desc *tx_desc,
5869                                  u32 tx_flags, unsigned int paylen)
5870 {
5871         u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
5872
5873         /* 82575 requires a unique index per ring */
5874         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
5875                 olinfo_status |= tx_ring->reg_idx << 4;
5876
5877         /* insert L4 checksum */
5878         olinfo_status |= IGB_SET_FLAG(tx_flags,
5879                                       IGB_TX_FLAGS_CSUM,
5880                                       (E1000_TXD_POPTS_TXSM << 8));
5881
5882         /* insert IPv4 checksum */
5883         olinfo_status |= IGB_SET_FLAG(tx_flags,
5884                                       IGB_TX_FLAGS_IPV4,
5885                                       (E1000_TXD_POPTS_IXSM << 8));
5886
5887         tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5888 }
5889
5890 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5891 {
5892         struct net_device *netdev = tx_ring->netdev;
5893
5894         netif_stop_subqueue(netdev, tx_ring->queue_index);
5895
5896         /* Herbert's original patch had:
5897          *  smp_mb__after_netif_stop_queue();
5898          * but since that doesn't exist yet, just open code it.
5899          */
5900         smp_mb();
5901
5902         /* We need to check again in a case another CPU has just
5903          * made room available.
5904          */
5905         if (igb_desc_unused(tx_ring) < size)
5906                 return -EBUSY;
5907
5908         /* A reprieve! */
5909         netif_wake_subqueue(netdev, tx_ring->queue_index);
5910
5911         u64_stats_update_begin(&tx_ring->tx_syncp2);
5912         tx_ring->tx_stats.restart_queue2++;
5913         u64_stats_update_end(&tx_ring->tx_syncp2);
5914
5915         return 0;
5916 }
5917
5918 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
5919 {
5920         if (igb_desc_unused(tx_ring) >= size)
5921                 return 0;
5922         return __igb_maybe_stop_tx(tx_ring, size);
5923 }
5924
5925 static int igb_tx_map(struct igb_ring *tx_ring,
5926                       struct igb_tx_buffer *first,
5927                       const u8 hdr_len)
5928 {
5929         struct sk_buff *skb = first->skb;
5930         struct igb_tx_buffer *tx_buffer;
5931         union e1000_adv_tx_desc *tx_desc;
5932         struct skb_frag_struct *frag;
5933         dma_addr_t dma;
5934         unsigned int data_len, size;
5935         u32 tx_flags = first->tx_flags;
5936         u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
5937         u16 i = tx_ring->next_to_use;
5938
5939         tx_desc = IGB_TX_DESC(tx_ring, i);
5940
5941         igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
5942
5943         size = skb_headlen(skb);
5944         data_len = skb->data_len;
5945
5946         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
5947
5948         tx_buffer = first;
5949
5950         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
5951                 if (dma_mapping_error(tx_ring->dev, dma))
5952                         goto dma_error;
5953
5954                 /* record length, and DMA address */
5955                 dma_unmap_len_set(tx_buffer, len, size);
5956                 dma_unmap_addr_set(tx_buffer, dma, dma);
5957
5958                 tx_desc->read.buffer_addr = cpu_to_le64(dma);
5959
5960                 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
5961                         tx_desc->read.cmd_type_len =
5962                                 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
5963
5964                         i++;
5965                         tx_desc++;
5966                         if (i == tx_ring->count) {
5967                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
5968                                 i = 0;
5969                         }
5970                         tx_desc->read.olinfo_status = 0;
5971
5972                         dma += IGB_MAX_DATA_PER_TXD;
5973                         size -= IGB_MAX_DATA_PER_TXD;
5974
5975                         tx_desc->read.buffer_addr = cpu_to_le64(dma);
5976                 }
5977
5978                 if (likely(!data_len))
5979                         break;
5980
5981                 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
5982
5983                 i++;
5984                 tx_desc++;
5985                 if (i == tx_ring->count) {
5986                         tx_desc = IGB_TX_DESC(tx_ring, 0);
5987                         i = 0;
5988                 }
5989                 tx_desc->read.olinfo_status = 0;
5990
5991                 size = skb_frag_size(frag);
5992                 data_len -= size;
5993
5994                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
5995                                        size, DMA_TO_DEVICE);
5996
5997                 tx_buffer = &tx_ring->tx_buffer_info[i];
5998         }
5999
6000         /* write last descriptor with RS and EOP bits */
6001         cmd_type |= size | IGB_TXD_DCMD;
6002         tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
6003
6004         netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
6005
6006         /* set the timestamp */
6007         first->time_stamp = jiffies;
6008
6009         skb_tx_timestamp(skb);
6010
6011         /* Force memory writes to complete before letting h/w know there
6012          * are new descriptors to fetch.  (Only applicable for weak-ordered
6013          * memory model archs, such as IA-64).
6014          *
6015          * We also need this memory barrier to make certain all of the
6016          * status bits have been updated before next_to_watch is written.
6017          */
6018         dma_wmb();
6019
6020         /* set next_to_watch value indicating a packet is present */
6021         first->next_to_watch = tx_desc;
6022
6023         i++;
6024         if (i == tx_ring->count)
6025                 i = 0;
6026
6027         tx_ring->next_to_use = i;
6028
6029         /* Make sure there is space in the ring for the next send. */
6030         igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
6031
6032         if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
6033                 writel(i, tx_ring->tail);
6034
6035                 /* we need this if more than one processor can write to our tail
6036                  * at a time, it synchronizes IO on IA64/Altix systems
6037                  */
6038                 mmiowb();
6039         }
6040         return 0;
6041
6042 dma_error:
6043         dev_err(tx_ring->dev, "TX DMA map failed\n");
6044         tx_buffer = &tx_ring->tx_buffer_info[i];
6045
6046         /* clear dma mappings for failed tx_buffer_info map */
6047         while (tx_buffer != first) {
6048                 if (dma_unmap_len(tx_buffer, len))
6049                         dma_unmap_page(tx_ring->dev,
6050                                        dma_unmap_addr(tx_buffer, dma),
6051                                        dma_unmap_len(tx_buffer, len),
6052                                        DMA_TO_DEVICE);
6053                 dma_unmap_len_set(tx_buffer, len, 0);
6054
6055                 if (i-- == 0)
6056                         i += tx_ring->count;
6057                 tx_buffer = &tx_ring->tx_buffer_info[i];
6058         }
6059
6060         if (dma_unmap_len(tx_buffer, len))
6061                 dma_unmap_single(tx_ring->dev,
6062                                  dma_unmap_addr(tx_buffer, dma),
6063                                  dma_unmap_len(tx_buffer, len),
6064                                  DMA_TO_DEVICE);
6065         dma_unmap_len_set(tx_buffer, len, 0);
6066
6067         dev_kfree_skb_any(tx_buffer->skb);
6068         tx_buffer->skb = NULL;
6069
6070         tx_ring->next_to_use = i;
6071
6072         return -1;
6073 }
6074
6075 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
6076                                 struct igb_ring *tx_ring)
6077 {
6078         struct igb_tx_buffer *first;
6079         int tso;
6080         u32 tx_flags = 0;
6081         unsigned short f;
6082         u16 count = TXD_USE_COUNT(skb_headlen(skb));
6083         __be16 protocol = vlan_get_protocol(skb);
6084         u8 hdr_len = 0;
6085
6086         /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
6087          *       + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
6088          *       + 2 desc gap to keep tail from touching head,
6089          *       + 1 desc for context descriptor,
6090          * otherwise try next time
6091          */
6092         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6093                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6094
6095         if (igb_maybe_stop_tx(tx_ring, count + 3)) {
6096                 /* this is a hard error */
6097                 return NETDEV_TX_BUSY;
6098         }
6099
6100         /* record the location of the first descriptor for this packet */
6101         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6102         first->skb = skb;
6103         first->bytecount = skb->len;
6104         first->gso_segs = 1;
6105
6106         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6107                 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6108
6109                 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
6110                     !test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS,
6111                                            &adapter->state)) {
6112                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6113                         tx_flags |= IGB_TX_FLAGS_TSTAMP;
6114
6115                         adapter->ptp_tx_skb = skb_get(skb);
6116                         adapter->ptp_tx_start = jiffies;
6117                         if (adapter->hw.mac.type == e1000_82576)
6118                                 schedule_work(&adapter->ptp_tx_work);
6119                 } else {
6120                         adapter->tx_hwtstamp_skipped++;
6121                 }
6122         }
6123
6124         if (skb_vlan_tag_present(skb)) {
6125                 tx_flags |= IGB_TX_FLAGS_VLAN;
6126                 tx_flags |= (skb_vlan_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
6127         }
6128
6129         /* record initial flags and protocol */
6130         first->tx_flags = tx_flags;
6131         first->protocol = protocol;
6132
6133         tso = igb_tso(tx_ring, first, &hdr_len);
6134         if (tso < 0)
6135                 goto out_drop;
6136         else if (!tso)
6137                 igb_tx_csum(tx_ring, first);
6138
6139         if (igb_tx_map(tx_ring, first, hdr_len))
6140                 goto cleanup_tx_tstamp;
6141
6142         return NETDEV_TX_OK;
6143
6144 out_drop:
6145         dev_kfree_skb_any(first->skb);
6146         first->skb = NULL;
6147 cleanup_tx_tstamp:
6148         if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) {
6149                 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
6150
6151                 dev_kfree_skb_any(adapter->ptp_tx_skb);
6152                 adapter->ptp_tx_skb = NULL;
6153                 if (adapter->hw.mac.type == e1000_82576)
6154                         cancel_work_sync(&adapter->ptp_tx_work);
6155                 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
6156         }
6157
6158         return NETDEV_TX_OK;
6159 }
6160
6161 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
6162                                                     struct sk_buff *skb)
6163 {
6164         unsigned int r_idx = skb->queue_mapping;
6165
6166         if (r_idx >= adapter->num_tx_queues)
6167                 r_idx = r_idx % adapter->num_tx_queues;
6168
6169         return adapter->tx_ring[r_idx];
6170 }
6171
6172 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
6173                                   struct net_device *netdev)
6174 {
6175         struct igb_adapter *adapter = netdev_priv(netdev);
6176
6177         /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
6178          * in order to meet this minimum size requirement.
6179          */
6180         if (skb_put_padto(skb, 17))
6181                 return NETDEV_TX_OK;
6182
6183         return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
6184 }
6185
6186 /**
6187  *  igb_tx_timeout - Respond to a Tx Hang
6188  *  @netdev: network interface device structure
6189  **/
6190 static void igb_tx_timeout(struct net_device *netdev)
6191 {
6192         struct igb_adapter *adapter = netdev_priv(netdev);
6193         struct e1000_hw *hw = &adapter->hw;
6194
6195         /* Do the reset outside of interrupt context */
6196         adapter->tx_timeout_count++;
6197
6198         if (hw->mac.type >= e1000_82580)
6199                 hw->dev_spec._82575.global_device_reset = true;
6200
6201         schedule_work(&adapter->reset_task);
6202         wr32(E1000_EICS,
6203              (adapter->eims_enable_mask & ~adapter->eims_other));
6204 }
6205
6206 static void igb_reset_task(struct work_struct *work)
6207 {
6208         struct igb_adapter *adapter;
6209         adapter = container_of(work, struct igb_adapter, reset_task);
6210
6211         igb_dump(adapter);
6212         netdev_err(adapter->netdev, "Reset adapter\n");
6213         igb_reinit_locked(adapter);
6214 }
6215
6216 /**
6217  *  igb_get_stats64 - Get System Network Statistics
6218  *  @netdev: network interface device structure
6219  *  @stats: rtnl_link_stats64 pointer
6220  **/
6221 static void igb_get_stats64(struct net_device *netdev,
6222                             struct rtnl_link_stats64 *stats)
6223 {
6224         struct igb_adapter *adapter = netdev_priv(netdev);
6225
6226         spin_lock(&adapter->stats64_lock);
6227         igb_update_stats(adapter);
6228         memcpy(stats, &adapter->stats64, sizeof(*stats));
6229         spin_unlock(&adapter->stats64_lock);
6230 }
6231
6232 /**
6233  *  igb_change_mtu - Change the Maximum Transfer Unit
6234  *  @netdev: network interface device structure
6235  *  @new_mtu: new value for maximum frame size
6236  *
6237  *  Returns 0 on success, negative on failure
6238  **/
6239 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
6240 {
6241         struct igb_adapter *adapter = netdev_priv(netdev);
6242         struct pci_dev *pdev = adapter->pdev;
6243         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
6244
6245         /* adjust max frame to be at least the size of a standard frame */
6246         if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
6247                 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN;
6248
6249         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
6250                 usleep_range(1000, 2000);
6251
6252         /* igb_down has a dependency on max_frame_size */
6253         adapter->max_frame_size = max_frame;
6254
6255         if (netif_running(netdev))
6256                 igb_down(adapter);
6257
6258         dev_info(&pdev->dev, "changing MTU from %d to %d\n",
6259                  netdev->mtu, new_mtu);
6260         netdev->mtu = new_mtu;
6261
6262         if (netif_running(netdev))
6263                 igb_up(adapter);
6264         else
6265                 igb_reset(adapter);
6266
6267         clear_bit(__IGB_RESETTING, &adapter->state);
6268
6269         return 0;
6270 }
6271
6272 /**
6273  *  igb_update_stats - Update the board statistics counters
6274  *  @adapter: board private structure
6275  **/
6276 void igb_update_stats(struct igb_adapter *adapter)
6277 {
6278         struct rtnl_link_stats64 *net_stats = &adapter->stats64;
6279         struct e1000_hw *hw = &adapter->hw;
6280         struct pci_dev *pdev = adapter->pdev;
6281         u32 reg, mpc;
6282         int i;
6283         u64 bytes, packets;
6284         unsigned int start;
6285         u64 _bytes, _packets;
6286
6287         /* Prevent stats update while adapter is being reset, or if the pci
6288          * connection is down.
6289          */
6290         if (adapter->link_speed == 0)
6291                 return;
6292         if (pci_channel_offline(pdev))
6293                 return;
6294
6295         bytes = 0;
6296         packets = 0;
6297
6298         rcu_read_lock();
6299         for (i = 0; i < adapter->num_rx_queues; i++) {
6300                 struct igb_ring *ring = adapter->rx_ring[i];
6301                 u32 rqdpc = rd32(E1000_RQDPC(i));
6302                 if (hw->mac.type >= e1000_i210)
6303                         wr32(E1000_RQDPC(i), 0);
6304
6305                 if (rqdpc) {
6306                         ring->rx_stats.drops += rqdpc;
6307                         net_stats->rx_fifo_errors += rqdpc;
6308                 }
6309
6310                 do {
6311                         start = u64_stats_fetch_begin_irq(&ring->rx_syncp);
6312                         _bytes = ring->rx_stats.bytes;
6313                         _packets = ring->rx_stats.packets;
6314                 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start));
6315                 bytes += _bytes;
6316                 packets += _packets;
6317         }
6318
6319         net_stats->rx_bytes = bytes;
6320         net_stats->rx_packets = packets;
6321
6322         bytes = 0;
6323         packets = 0;
6324         for (i = 0; i < adapter->num_tx_queues; i++) {
6325                 struct igb_ring *ring = adapter->tx_ring[i];
6326                 do {
6327                         start = u64_stats_fetch_begin_irq(&ring->tx_syncp);
6328                         _bytes = ring->tx_stats.bytes;
6329                         _packets = ring->tx_stats.packets;
6330                 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start));
6331                 bytes += _bytes;
6332                 packets += _packets;
6333         }
6334         net_stats->tx_bytes = bytes;
6335         net_stats->tx_packets = packets;
6336         rcu_read_unlock();
6337
6338         /* read stats registers */
6339         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
6340         adapter->stats.gprc += rd32(E1000_GPRC);
6341         adapter->stats.gorc += rd32(E1000_GORCL);
6342         rd32(E1000_GORCH); /* clear GORCL */
6343         adapter->stats.bprc += rd32(E1000_BPRC);
6344         adapter->stats.mprc += rd32(E1000_MPRC);
6345         adapter->stats.roc += rd32(E1000_ROC);
6346
6347         adapter->stats.prc64 += rd32(E1000_PRC64);
6348         adapter->stats.prc127 += rd32(E1000_PRC127);
6349         adapter->stats.prc255 += rd32(E1000_PRC255);
6350         adapter->stats.prc511 += rd32(E1000_PRC511);
6351         adapter->stats.prc1023 += rd32(E1000_PRC1023);
6352         adapter->stats.prc1522 += rd32(E1000_PRC1522);
6353         adapter->stats.symerrs += rd32(E1000_SYMERRS);
6354         adapter->stats.sec += rd32(E1000_SEC);
6355
6356         mpc = rd32(E1000_MPC);
6357         adapter->stats.mpc += mpc;
6358         net_stats->rx_fifo_errors += mpc;
6359         adapter->stats.scc += rd32(E1000_SCC);
6360         adapter->stats.ecol += rd32(E1000_ECOL);
6361         adapter->stats.mcc += rd32(E1000_MCC);
6362         adapter->stats.latecol += rd32(E1000_LATECOL);
6363         adapter->stats.dc += rd32(E1000_DC);
6364         adapter->stats.rlec += rd32(E1000_RLEC);
6365         adapter->stats.xonrxc += rd32(E1000_XONRXC);
6366         adapter->stats.xontxc += rd32(E1000_XONTXC);
6367         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
6368         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
6369         adapter->stats.fcruc += rd32(E1000_FCRUC);
6370         adapter->stats.gptc += rd32(E1000_GPTC);
6371         adapter->stats.gotc += rd32(E1000_GOTCL);
6372         rd32(E1000_GOTCH); /* clear GOTCL */
6373         adapter->stats.rnbc += rd32(E1000_RNBC);
6374         adapter->stats.ruc += rd32(E1000_RUC);
6375         adapter->stats.rfc += rd32(E1000_RFC);
6376         adapter->stats.rjc += rd32(E1000_RJC);
6377         adapter->stats.tor += rd32(E1000_TORH);
6378         adapter->stats.tot += rd32(E1000_TOTH);
6379         adapter->stats.tpr += rd32(E1000_TPR);
6380
6381         adapter->stats.ptc64 += rd32(E1000_PTC64);
6382         adapter->stats.ptc127 += rd32(E1000_PTC127);
6383         adapter->stats.ptc255 += rd32(E1000_PTC255);
6384         adapter->stats.ptc511 += rd32(E1000_PTC511);
6385         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
6386         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
6387
6388         adapter->stats.mptc += rd32(E1000_MPTC);
6389         adapter->stats.bptc += rd32(E1000_BPTC);
6390
6391         adapter->stats.tpt += rd32(E1000_TPT);
6392         adapter->stats.colc += rd32(E1000_COLC);
6393
6394         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
6395         /* read internal phy specific stats */
6396         reg = rd32(E1000_CTRL_EXT);
6397         if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
6398                 adapter->stats.rxerrc += rd32(E1000_RXERRC);
6399
6400                 /* this stat has invalid values on i210/i211 */
6401                 if ((hw->mac.type != e1000_i210) &&
6402                     (hw->mac.type != e1000_i211))
6403                         adapter->stats.tncrs += rd32(E1000_TNCRS);
6404         }
6405
6406         adapter->stats.tsctc += rd32(E1000_TSCTC);
6407         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
6408
6409         adapter->stats.iac += rd32(E1000_IAC);
6410         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
6411         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
6412         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
6413         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
6414         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
6415         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
6416         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
6417         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
6418
6419         /* Fill out the OS statistics structure */
6420         net_stats->multicast = adapter->stats.mprc;
6421         net_stats->collisions = adapter->stats.colc;
6422
6423         /* Rx Errors */
6424
6425         /* RLEC on some newer hardware can be incorrect so build
6426          * our own version based on RUC and ROC
6427          */
6428         net_stats->rx_errors = adapter->stats.rxerrc +
6429                 adapter->stats.crcerrs + adapter->stats.algnerrc +
6430                 adapter->stats.ruc + adapter->stats.roc +
6431                 adapter->stats.cexterr;
6432         net_stats->rx_length_errors = adapter->stats.ruc +
6433                                       adapter->stats.roc;
6434         net_stats->rx_crc_errors = adapter->stats.crcerrs;
6435         net_stats->rx_frame_errors = adapter->stats.algnerrc;
6436         net_stats->rx_missed_errors = adapter->stats.mpc;
6437
6438         /* Tx Errors */
6439         net_stats->tx_errors = adapter->stats.ecol +
6440                                adapter->stats.latecol;
6441         net_stats->tx_aborted_errors = adapter->stats.ecol;
6442         net_stats->tx_window_errors = adapter->stats.latecol;
6443         net_stats->tx_carrier_errors = adapter->stats.tncrs;
6444
6445         /* Tx Dropped needs to be maintained elsewhere */
6446
6447         /* Management Stats */
6448         adapter->stats.mgptc += rd32(E1000_MGTPTC);
6449         adapter->stats.mgprc += rd32(E1000_MGTPRC);
6450         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
6451
6452         /* OS2BMC Stats */
6453         reg = rd32(E1000_MANC);
6454         if (reg & E1000_MANC_EN_BMC2OS) {
6455                 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
6456                 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
6457                 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
6458                 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
6459         }
6460 }
6461
6462 static void igb_tsync_interrupt(struct igb_adapter *adapter)
6463 {
6464         struct e1000_hw *hw = &adapter->hw;
6465         struct ptp_clock_event event;
6466         struct timespec64 ts;
6467         u32 ack = 0, tsauxc, sec, nsec, tsicr = rd32(E1000_TSICR);
6468
6469         if (tsicr & TSINTR_SYS_WRAP) {
6470                 event.type = PTP_CLOCK_PPS;
6471                 if (adapter->ptp_caps.pps)
6472                         ptp_clock_event(adapter->ptp_clock, &event);
6473                 ack |= TSINTR_SYS_WRAP;
6474         }
6475
6476         if (tsicr & E1000_TSICR_TXTS) {
6477                 /* retrieve hardware timestamp */
6478                 schedule_work(&adapter->ptp_tx_work);
6479                 ack |= E1000_TSICR_TXTS;
6480         }
6481
6482         if (tsicr & TSINTR_TT0) {
6483                 spin_lock(&adapter->tmreg_lock);
6484                 ts = timespec64_add(adapter->perout[0].start,
6485                                     adapter->perout[0].period);
6486                 /* u32 conversion of tv_sec is safe until y2106 */
6487                 wr32(E1000_TRGTTIML0, ts.tv_nsec);
6488                 wr32(E1000_TRGTTIMH0, (u32)ts.tv_sec);
6489                 tsauxc = rd32(E1000_TSAUXC);
6490                 tsauxc |= TSAUXC_EN_TT0;
6491                 wr32(E1000_TSAUXC, tsauxc);
6492                 adapter->perout[0].start = ts;
6493                 spin_unlock(&adapter->tmreg_lock);
6494                 ack |= TSINTR_TT0;
6495         }
6496
6497         if (tsicr & TSINTR_TT1) {
6498                 spin_lock(&adapter->tmreg_lock);
6499                 ts = timespec64_add(adapter->perout[1].start,
6500                                     adapter->perout[1].period);
6501                 wr32(E1000_TRGTTIML1, ts.tv_nsec);
6502                 wr32(E1000_TRGTTIMH1, (u32)ts.tv_sec);
6503                 tsauxc = rd32(E1000_TSAUXC);
6504                 tsauxc |= TSAUXC_EN_TT1;
6505                 wr32(E1000_TSAUXC, tsauxc);
6506                 adapter->perout[1].start = ts;
6507                 spin_unlock(&adapter->tmreg_lock);
6508                 ack |= TSINTR_TT1;
6509         }
6510
6511         if (tsicr & TSINTR_AUTT0) {
6512                 nsec = rd32(E1000_AUXSTMPL0);
6513                 sec  = rd32(E1000_AUXSTMPH0);
6514                 event.type = PTP_CLOCK_EXTTS;
6515                 event.index = 0;
6516                 event.timestamp = sec * 1000000000ULL + nsec;
6517                 ptp_clock_event(adapter->ptp_clock, &event);
6518                 ack |= TSINTR_AUTT0;
6519         }
6520
6521         if (tsicr & TSINTR_AUTT1) {
6522                 nsec = rd32(E1000_AUXSTMPL1);
6523                 sec  = rd32(E1000_AUXSTMPH1);
6524                 event.type = PTP_CLOCK_EXTTS;
6525                 event.index = 1;
6526                 event.timestamp = sec * 1000000000ULL + nsec;
6527                 ptp_clock_event(adapter->ptp_clock, &event);
6528                 ack |= TSINTR_AUTT1;
6529         }
6530
6531         /* acknowledge the interrupts */
6532         wr32(E1000_TSICR, ack);
6533 }
6534
6535 static irqreturn_t igb_msix_other(int irq, void *data)
6536 {
6537         struct igb_adapter *adapter = data;
6538         struct e1000_hw *hw = &adapter->hw;
6539         u32 icr = rd32(E1000_ICR);
6540         /* reading ICR causes bit 31 of EICR to be cleared */
6541
6542         if (icr & E1000_ICR_DRSTA)
6543                 schedule_work(&adapter->reset_task);
6544
6545         if (icr & E1000_ICR_DOUTSYNC) {
6546                 /* HW is reporting DMA is out of sync */
6547                 adapter->stats.doosync++;
6548                 /* The DMA Out of Sync is also indication of a spoof event
6549                  * in IOV mode. Check the Wrong VM Behavior register to
6550                  * see if it is really a spoof event.
6551                  */
6552                 igb_check_wvbr(adapter);
6553         }
6554
6555         /* Check for a mailbox event */
6556         if (icr & E1000_ICR_VMMB)
6557                 igb_msg_task(adapter);
6558
6559         if (icr & E1000_ICR_LSC) {
6560                 hw->mac.get_link_status = 1;
6561                 /* guard against interrupt when we're going down */
6562                 if (!test_bit(__IGB_DOWN, &adapter->state))
6563                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
6564         }
6565
6566         if (icr & E1000_ICR_TS)
6567                 igb_tsync_interrupt(adapter);
6568
6569         wr32(E1000_EIMS, adapter->eims_other);
6570
6571         return IRQ_HANDLED;
6572 }
6573
6574 static void igb_write_itr(struct igb_q_vector *q_vector)
6575 {
6576         struct igb_adapter *adapter = q_vector->adapter;
6577         u32 itr_val = q_vector->itr_val & 0x7FFC;
6578
6579         if (!q_vector->set_itr)
6580                 return;
6581
6582         if (!itr_val)
6583                 itr_val = 0x4;
6584
6585         if (adapter->hw.mac.type == e1000_82575)
6586                 itr_val |= itr_val << 16;
6587         else
6588                 itr_val |= E1000_EITR_CNT_IGNR;
6589
6590         writel(itr_val, q_vector->itr_register);
6591         q_vector->set_itr = 0;
6592 }
6593
6594 static irqreturn_t igb_msix_ring(int irq, void *data)
6595 {
6596         struct igb_q_vector *q_vector = data;
6597
6598         /* Write the ITR value calculated from the previous interrupt. */
6599         igb_write_itr(q_vector);
6600
6601         napi_schedule(&q_vector->napi);
6602
6603         return IRQ_HANDLED;
6604 }
6605
6606 #ifdef CONFIG_IGB_DCA
6607 static void igb_update_tx_dca(struct igb_adapter *adapter,
6608                               struct igb_ring *tx_ring,
6609                               int cpu)
6610 {
6611         struct e1000_hw *hw = &adapter->hw;
6612         u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
6613
6614         if (hw->mac.type != e1000_82575)
6615                 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
6616
6617         /* We can enable relaxed ordering for reads, but not writes when
6618          * DCA is enabled.  This is due to a known issue in some chipsets
6619          * which will cause the DCA tag to be cleared.
6620          */
6621         txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
6622                   E1000_DCA_TXCTRL_DATA_RRO_EN |
6623                   E1000_DCA_TXCTRL_DESC_DCA_EN;
6624
6625         wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
6626 }
6627
6628 static void igb_update_rx_dca(struct igb_adapter *adapter,
6629                               struct igb_ring *rx_ring,
6630                               int cpu)
6631 {
6632         struct e1000_hw *hw = &adapter->hw;
6633         u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
6634
6635         if (hw->mac.type != e1000_82575)
6636                 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
6637
6638         /* We can enable relaxed ordering for reads, but not writes when
6639          * DCA is enabled.  This is due to a known issue in some chipsets
6640          * which will cause the DCA tag to be cleared.
6641          */
6642         rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
6643                   E1000_DCA_RXCTRL_DESC_DCA_EN;
6644
6645         wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
6646 }
6647
6648 static void igb_update_dca(struct igb_q_vector *q_vector)
6649 {
6650         struct igb_adapter *adapter = q_vector->adapter;
6651         int cpu = get_cpu();
6652
6653         if (q_vector->cpu == cpu)
6654                 goto out_no_update;
6655
6656         if (q_vector->tx.ring)
6657                 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
6658
6659         if (q_vector->rx.ring)
6660                 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
6661
6662         q_vector->cpu = cpu;
6663 out_no_update:
6664         put_cpu();
6665 }
6666
6667 static void igb_setup_dca(struct igb_adapter *adapter)
6668 {
6669         struct e1000_hw *hw = &adapter->hw;
6670         int i;
6671
6672         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
6673                 return;
6674
6675         /* Always use CB2 mode, difference is masked in the CB driver. */
6676         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
6677
6678         for (i = 0; i < adapter->num_q_vectors; i++) {
6679                 adapter->q_vector[i]->cpu = -1;
6680                 igb_update_dca(adapter->q_vector[i]);
6681         }
6682 }
6683
6684 static int __igb_notify_dca(struct device *dev, void *data)
6685 {
6686         struct net_device *netdev = dev_get_drvdata(dev);
6687         struct igb_adapter *adapter = netdev_priv(netdev);
6688         struct pci_dev *pdev = adapter->pdev;
6689         struct e1000_hw *hw = &adapter->hw;
6690         unsigned long event = *(unsigned long *)data;
6691
6692         switch (event) {
6693         case DCA_PROVIDER_ADD:
6694                 /* if already enabled, don't do it again */
6695                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
6696                         break;
6697                 if (dca_add_requester(dev) == 0) {
6698                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
6699                         dev_info(&pdev->dev, "DCA enabled\n");
6700                         igb_setup_dca(adapter);
6701                         break;
6702                 }
6703                 /* Fall Through since DCA is disabled. */
6704         case DCA_PROVIDER_REMOVE:
6705                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
6706                         /* without this a class_device is left
6707                          * hanging around in the sysfs model
6708                          */
6709                         dca_remove_requester(dev);
6710                         dev_info(&pdev->dev, "DCA disabled\n");
6711                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
6712                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
6713                 }
6714                 break;
6715         }
6716
6717         return 0;
6718 }
6719
6720 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
6721                           void *p)
6722 {
6723         int ret_val;
6724
6725         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
6726                                          __igb_notify_dca);
6727
6728         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6729 }
6730 #endif /* CONFIG_IGB_DCA */
6731
6732 #ifdef CONFIG_PCI_IOV
6733 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
6734 {
6735         unsigned char mac_addr[ETH_ALEN];
6736
6737         eth_zero_addr(mac_addr);
6738         igb_set_vf_mac(adapter, vf, mac_addr);
6739
6740         /* By default spoof check is enabled for all VFs */
6741         adapter->vf_data[vf].spoofchk_enabled = true;
6742
6743         /* By default VFs are not trusted */
6744         adapter->vf_data[vf].trusted = false;
6745
6746         return 0;
6747 }
6748
6749 #endif
6750 static void igb_ping_all_vfs(struct igb_adapter *adapter)
6751 {
6752         struct e1000_hw *hw = &adapter->hw;
6753         u32 ping;
6754         int i;
6755
6756         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
6757                 ping = E1000_PF_CONTROL_MSG;
6758                 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
6759                         ping |= E1000_VT_MSGTYPE_CTS;
6760                 igb_write_mbx(hw, &ping, 1, i);
6761         }
6762 }
6763
6764 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
6765 {
6766         struct e1000_hw *hw = &adapter->hw;
6767         u32 vmolr = rd32(E1000_VMOLR(vf));
6768         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6769
6770         vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
6771                             IGB_VF_FLAG_MULTI_PROMISC);
6772         vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
6773
6774         if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
6775                 vmolr |= E1000_VMOLR_MPME;
6776                 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
6777                 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
6778         } else {
6779                 /* if we have hashes and we are clearing a multicast promisc
6780                  * flag we need to write the hashes to the MTA as this step
6781                  * was previously skipped
6782                  */
6783                 if (vf_data->num_vf_mc_hashes > 30) {
6784                         vmolr |= E1000_VMOLR_MPME;
6785                 } else if (vf_data->num_vf_mc_hashes) {
6786                         int j;
6787
6788                         vmolr |= E1000_VMOLR_ROMPE;
6789                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
6790                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
6791                 }
6792         }
6793
6794         wr32(E1000_VMOLR(vf), vmolr);
6795
6796         /* there are flags left unprocessed, likely not supported */
6797         if (*msgbuf & E1000_VT_MSGINFO_MASK)
6798                 return -EINVAL;
6799
6800         return 0;
6801 }
6802
6803 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
6804                                   u32 *msgbuf, u32 vf)
6805 {
6806         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
6807         u16 *hash_list = (u16 *)&msgbuf[1];
6808         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
6809         int i;
6810
6811         /* salt away the number of multicast addresses assigned
6812          * to this VF for later use to restore when the PF multi cast
6813          * list changes
6814          */
6815         vf_data->num_vf_mc_hashes = n;
6816
6817         /* only up to 30 hash values supported */
6818         if (n > 30)
6819                 n = 30;
6820
6821         /* store the hashes for later use */
6822         for (i = 0; i < n; i++)
6823                 vf_data->vf_mc_hashes[i] = hash_list[i];
6824
6825         /* Flush and reset the mta with the new values */
6826         igb_set_rx_mode(adapter->netdev);
6827
6828         return 0;
6829 }
6830
6831 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
6832 {
6833         struct e1000_hw *hw = &adapter->hw;
6834         struct vf_data_storage *vf_data;
6835         int i, j;
6836
6837         for (i = 0; i < adapter->vfs_allocated_count; i++) {
6838                 u32 vmolr = rd32(E1000_VMOLR(i));
6839
6840                 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
6841
6842                 vf_data = &adapter->vf_data[i];
6843
6844                 if ((vf_data->num_vf_mc_hashes > 30) ||
6845                     (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
6846                         vmolr |= E1000_VMOLR_MPME;
6847                 } else if (vf_data->num_vf_mc_hashes) {
6848                         vmolr |= E1000_VMOLR_ROMPE;
6849                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
6850                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
6851                 }
6852                 wr32(E1000_VMOLR(i), vmolr);
6853         }
6854 }
6855
6856 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
6857 {
6858         struct e1000_hw *hw = &adapter->hw;
6859         u32 pool_mask, vlvf_mask, i;
6860
6861         /* create mask for VF and other pools */
6862         pool_mask = E1000_VLVF_POOLSEL_MASK;
6863         vlvf_mask = BIT(E1000_VLVF_POOLSEL_SHIFT + vf);
6864
6865         /* drop PF from pool bits */
6866         pool_mask &= ~BIT(E1000_VLVF_POOLSEL_SHIFT +
6867                              adapter->vfs_allocated_count);
6868
6869         /* Find the vlan filter for this id */
6870         for (i = E1000_VLVF_ARRAY_SIZE; i--;) {
6871                 u32 vlvf = rd32(E1000_VLVF(i));
6872                 u32 vfta_mask, vid, vfta;
6873
6874                 /* remove the vf from the pool */
6875                 if (!(vlvf & vlvf_mask))
6876                         continue;
6877
6878                 /* clear out bit from VLVF */
6879                 vlvf ^= vlvf_mask;
6880
6881                 /* if other pools are present, just remove ourselves */
6882                 if (vlvf & pool_mask)
6883                         goto update_vlvfb;
6884
6885                 /* if PF is present, leave VFTA */
6886                 if (vlvf & E1000_VLVF_POOLSEL_MASK)
6887                         goto update_vlvf;
6888
6889                 vid = vlvf & E1000_VLVF_VLANID_MASK;
6890                 vfta_mask = BIT(vid % 32);
6891
6892                 /* clear bit from VFTA */
6893                 vfta = adapter->shadow_vfta[vid / 32];
6894                 if (vfta & vfta_mask)
6895                         hw->mac.ops.write_vfta(hw, vid / 32, vfta ^ vfta_mask);
6896 update_vlvf:
6897                 /* clear pool selection enable */
6898                 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
6899                         vlvf &= E1000_VLVF_POOLSEL_MASK;
6900                 else
6901                         vlvf = 0;
6902 update_vlvfb:
6903                 /* clear pool bits */
6904                 wr32(E1000_VLVF(i), vlvf);
6905         }
6906 }
6907
6908 static int igb_find_vlvf_entry(struct e1000_hw *hw, u32 vlan)
6909 {
6910         u32 vlvf;
6911         int idx;
6912
6913         /* short cut the special case */
6914         if (vlan == 0)
6915                 return 0;
6916
6917         /* Search for the VLAN id in the VLVF entries */
6918         for (idx = E1000_VLVF_ARRAY_SIZE; --idx;) {
6919                 vlvf = rd32(E1000_VLVF(idx));
6920                 if ((vlvf & VLAN_VID_MASK) == vlan)
6921                         break;
6922         }
6923
6924         return idx;
6925 }
6926
6927 static void igb_update_pf_vlvf(struct igb_adapter *adapter, u32 vid)
6928 {
6929         struct e1000_hw *hw = &adapter->hw;
6930         u32 bits, pf_id;
6931         int idx;
6932
6933         idx = igb_find_vlvf_entry(hw, vid);
6934         if (!idx)
6935                 return;
6936
6937         /* See if any other pools are set for this VLAN filter
6938          * entry other than the PF.
6939          */
6940         pf_id = adapter->vfs_allocated_count + E1000_VLVF_POOLSEL_SHIFT;
6941         bits = ~BIT(pf_id) & E1000_VLVF_POOLSEL_MASK;
6942         bits &= rd32(E1000_VLVF(idx));
6943
6944         /* Disable the filter so this falls into the default pool. */
6945         if (!bits) {
6946                 if (adapter->flags & IGB_FLAG_VLAN_PROMISC)
6947                         wr32(E1000_VLVF(idx), BIT(pf_id));
6948                 else
6949                         wr32(E1000_VLVF(idx), 0);
6950         }
6951 }
6952
6953 static s32 igb_set_vf_vlan(struct igb_adapter *adapter, u32 vid,
6954                            bool add, u32 vf)
6955 {
6956         int pf_id = adapter->vfs_allocated_count;
6957         struct e1000_hw *hw = &adapter->hw;
6958         int err;
6959
6960         /* If VLAN overlaps with one the PF is currently monitoring make
6961          * sure that we are able to allocate a VLVF entry.  This may be
6962          * redundant but it guarantees PF will maintain visibility to
6963          * the VLAN.
6964          */
6965         if (add && test_bit(vid, adapter->active_vlans)) {
6966                 err = igb_vfta_set(hw, vid, pf_id, true, false);
6967                 if (err)
6968                         return err;
6969         }
6970
6971         err = igb_vfta_set(hw, vid, vf, add, false);
6972
6973         if (add && !err)
6974                 return err;
6975
6976         /* If we failed to add the VF VLAN or we are removing the VF VLAN
6977          * we may need to drop the PF pool bit in order to allow us to free
6978          * up the VLVF resources.
6979          */
6980         if (test_bit(vid, adapter->active_vlans) ||
6981             (adapter->flags & IGB_FLAG_VLAN_PROMISC))
6982                 igb_update_pf_vlvf(adapter, vid);
6983
6984         return err;
6985 }
6986
6987 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
6988 {
6989         struct e1000_hw *hw = &adapter->hw;
6990
6991         if (vid)
6992                 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
6993         else
6994                 wr32(E1000_VMVIR(vf), 0);
6995 }
6996
6997 static int igb_enable_port_vlan(struct igb_adapter *adapter, int vf,
6998                                 u16 vlan, u8 qos)
6999 {
7000         int err;
7001
7002         err = igb_set_vf_vlan(adapter, vlan, true, vf);
7003         if (err)
7004                 return err;
7005
7006         igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
7007         igb_set_vmolr(adapter, vf, !vlan);
7008
7009         /* revoke access to previous VLAN */
7010         if (vlan != adapter->vf_data[vf].pf_vlan)
7011                 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7012                                 false, vf);
7013
7014         adapter->vf_data[vf].pf_vlan = vlan;
7015         adapter->vf_data[vf].pf_qos = qos;
7016         igb_set_vf_vlan_strip(adapter, vf, true);
7017         dev_info(&adapter->pdev->dev,
7018                  "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
7019         if (test_bit(__IGB_DOWN, &adapter->state)) {
7020                 dev_warn(&adapter->pdev->dev,
7021                          "The VF VLAN has been set, but the PF device is not up.\n");
7022                 dev_warn(&adapter->pdev->dev,
7023                          "Bring the PF device up before attempting to use the VF device.\n");
7024         }
7025
7026         return err;
7027 }
7028
7029 static int igb_disable_port_vlan(struct igb_adapter *adapter, int vf)
7030 {
7031         /* Restore tagless access via VLAN 0 */
7032         igb_set_vf_vlan(adapter, 0, true, vf);
7033
7034         igb_set_vmvir(adapter, 0, vf);
7035         igb_set_vmolr(adapter, vf, true);
7036
7037         /* Remove any PF assigned VLAN */
7038         if (adapter->vf_data[vf].pf_vlan)
7039                 igb_set_vf_vlan(adapter, adapter->vf_data[vf].pf_vlan,
7040                                 false, vf);
7041
7042         adapter->vf_data[vf].pf_vlan = 0;
7043         adapter->vf_data[vf].pf_qos = 0;
7044         igb_set_vf_vlan_strip(adapter, vf, false);
7045
7046         return 0;
7047 }
7048
7049 static int igb_ndo_set_vf_vlan(struct net_device *netdev, int vf,
7050                                u16 vlan, u8 qos, __be16 vlan_proto)
7051 {
7052         struct igb_adapter *adapter = netdev_priv(netdev);
7053
7054         if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
7055                 return -EINVAL;
7056
7057         if (vlan_proto != htons(ETH_P_8021Q))
7058                 return -EPROTONOSUPPORT;
7059
7060         return (vlan || qos) ? igb_enable_port_vlan(adapter, vf, vlan, qos) :
7061                                igb_disable_port_vlan(adapter, vf);
7062 }
7063
7064 static int igb_set_vf_vlan_msg(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
7065 {
7066         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
7067         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
7068         int ret;
7069
7070         if (adapter->vf_data[vf].pf_vlan)
7071                 return -1;
7072
7073         /* VLAN 0 is a special case, don't allow it to be removed */
7074         if (!vid && !add)
7075                 return 0;
7076
7077         ret = igb_set_vf_vlan(adapter, vid, !!add, vf);
7078         if (!ret)
7079                 igb_set_vf_vlan_strip(adapter, vf, !!vid);
7080         return ret;
7081 }
7082
7083 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
7084 {
7085         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7086
7087         /* clear flags - except flag that indicates PF has set the MAC */
7088         vf_data->flags &= IGB_VF_FLAG_PF_SET_MAC;
7089         vf_data->last_nack = jiffies;
7090
7091         /* reset vlans for device */
7092         igb_clear_vf_vfta(adapter, vf);
7093         igb_set_vf_vlan(adapter, vf_data->pf_vlan, true, vf);
7094         igb_set_vmvir(adapter, vf_data->pf_vlan |
7095                                (vf_data->pf_qos << VLAN_PRIO_SHIFT), vf);
7096         igb_set_vmolr(adapter, vf, !vf_data->pf_vlan);
7097         igb_set_vf_vlan_strip(adapter, vf, !!(vf_data->pf_vlan));
7098
7099         /* reset multicast table array for vf */
7100         adapter->vf_data[vf].num_vf_mc_hashes = 0;
7101
7102         /* Flush and reset the mta with the new values */
7103         igb_set_rx_mode(adapter->netdev);
7104 }
7105
7106 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
7107 {
7108         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7109
7110         /* clear mac address as we were hotplug removed/added */
7111         if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
7112                 eth_zero_addr(vf_mac);
7113
7114         /* process remaining reset events */
7115         igb_vf_reset(adapter, vf);
7116 }
7117
7118 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
7119 {
7120         struct e1000_hw *hw = &adapter->hw;
7121         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
7122         u32 reg, msgbuf[3];
7123         u8 *addr = (u8 *)(&msgbuf[1]);
7124
7125         /* process all the same items cleared in a function level reset */
7126         igb_vf_reset(adapter, vf);
7127
7128         /* set vf mac address */
7129         igb_set_vf_mac(adapter, vf, vf_mac);
7130
7131         /* enable transmit and receive for vf */
7132         reg = rd32(E1000_VFTE);
7133         wr32(E1000_VFTE, reg | BIT(vf));
7134         reg = rd32(E1000_VFRE);
7135         wr32(E1000_VFRE, reg | BIT(vf));
7136
7137         adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
7138
7139         /* reply to reset with ack and vf mac address */
7140         if (!is_zero_ether_addr(vf_mac)) {
7141                 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
7142                 memcpy(addr, vf_mac, ETH_ALEN);
7143         } else {
7144                 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_NACK;
7145         }
7146         igb_write_mbx(hw, msgbuf, 3, vf);
7147 }
7148
7149 static void igb_flush_mac_table(struct igb_adapter *adapter)
7150 {
7151         struct e1000_hw *hw = &adapter->hw;
7152         int i;
7153
7154         for (i = 0; i < hw->mac.rar_entry_count; i++) {
7155                 adapter->mac_table[i].state &= ~IGB_MAC_STATE_IN_USE;
7156                 memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
7157                 adapter->mac_table[i].queue = 0;
7158                 igb_rar_set_index(adapter, i);
7159         }
7160 }
7161
7162 static int igb_available_rars(struct igb_adapter *adapter, u8 queue)
7163 {
7164         struct e1000_hw *hw = &adapter->hw;
7165         /* do not count rar entries reserved for VFs MAC addresses */
7166         int rar_entries = hw->mac.rar_entry_count -
7167                           adapter->vfs_allocated_count;
7168         int i, count = 0;
7169
7170         for (i = 0; i < rar_entries; i++) {
7171                 /* do not count default entries */
7172                 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT)
7173                         continue;
7174
7175                 /* do not count "in use" entries for different queues */
7176                 if ((adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE) &&
7177                     (adapter->mac_table[i].queue != queue))
7178                         continue;
7179
7180                 count++;
7181         }
7182
7183         return count;
7184 }
7185
7186 /* Set default MAC address for the PF in the first RAR entry */
7187 static void igb_set_default_mac_filter(struct igb_adapter *adapter)
7188 {
7189         struct igb_mac_addr *mac_table = &adapter->mac_table[0];
7190
7191         ether_addr_copy(mac_table->addr, adapter->hw.mac.addr);
7192         mac_table->queue = adapter->vfs_allocated_count;
7193         mac_table->state = IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7194
7195         igb_rar_set_index(adapter, 0);
7196 }
7197
7198 /* If the filter to be added and an already existing filter express
7199  * the same address and address type, it should be possible to only
7200  * override the other configurations, for example the queue to steer
7201  * traffic.
7202  */
7203 static bool igb_mac_entry_can_be_used(const struct igb_mac_addr *entry,
7204                                       const u8 *addr, const u8 flags)
7205 {
7206         if (!(entry->state & IGB_MAC_STATE_IN_USE))
7207                 return true;
7208
7209         if ((entry->state & IGB_MAC_STATE_SRC_ADDR) !=
7210             (flags & IGB_MAC_STATE_SRC_ADDR))
7211                 return false;
7212
7213         if (!ether_addr_equal(addr, entry->addr))
7214                 return false;
7215
7216         return true;
7217 }
7218
7219 /* Add a MAC filter for 'addr' directing matching traffic to 'queue',
7220  * 'flags' is used to indicate what kind of match is made, match is by
7221  * default for the destination address, if matching by source address
7222  * is desired the flag IGB_MAC_STATE_SRC_ADDR can be used.
7223  */
7224 static int igb_add_mac_filter_flags(struct igb_adapter *adapter,
7225                                     const u8 *addr, const u8 queue,
7226                                     const u8 flags)
7227 {
7228         struct e1000_hw *hw = &adapter->hw;
7229         int rar_entries = hw->mac.rar_entry_count -
7230                           adapter->vfs_allocated_count;
7231         int i;
7232
7233         if (is_zero_ether_addr(addr))
7234                 return -EINVAL;
7235
7236         /* Search for the first empty entry in the MAC table.
7237          * Do not touch entries at the end of the table reserved for the VF MAC
7238          * addresses.
7239          */
7240         for (i = 0; i < rar_entries; i++) {
7241                 if (!igb_mac_entry_can_be_used(&adapter->mac_table[i],
7242                                                addr, flags))
7243                         continue;
7244
7245                 ether_addr_copy(adapter->mac_table[i].addr, addr);
7246                 adapter->mac_table[i].queue = queue;
7247                 adapter->mac_table[i].state |= IGB_MAC_STATE_IN_USE | flags;
7248
7249                 igb_rar_set_index(adapter, i);
7250                 return i;
7251         }
7252
7253         return -ENOSPC;
7254 }
7255
7256 static int igb_add_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7257                               const u8 queue)
7258 {
7259         return igb_add_mac_filter_flags(adapter, addr, queue, 0);
7260 }
7261
7262 /* Remove a MAC filter for 'addr' directing matching traffic to
7263  * 'queue', 'flags' is used to indicate what kind of match need to be
7264  * removed, match is by default for the destination address, if
7265  * matching by source address is to be removed the flag
7266  * IGB_MAC_STATE_SRC_ADDR can be used.
7267  */
7268 static int igb_del_mac_filter_flags(struct igb_adapter *adapter,
7269                                     const u8 *addr, const u8 queue,
7270                                     const u8 flags)
7271 {
7272         struct e1000_hw *hw = &adapter->hw;
7273         int rar_entries = hw->mac.rar_entry_count -
7274                           adapter->vfs_allocated_count;
7275         int i;
7276
7277         if (is_zero_ether_addr(addr))
7278                 return -EINVAL;
7279
7280         /* Search for matching entry in the MAC table based on given address
7281          * and queue. Do not touch entries at the end of the table reserved
7282          * for the VF MAC addresses.
7283          */
7284         for (i = 0; i < rar_entries; i++) {
7285                 if (!(adapter->mac_table[i].state & IGB_MAC_STATE_IN_USE))
7286                         continue;
7287                 if ((adapter->mac_table[i].state & flags) != flags)
7288                         continue;
7289                 if (adapter->mac_table[i].queue != queue)
7290                         continue;
7291                 if (!ether_addr_equal(adapter->mac_table[i].addr, addr))
7292                         continue;
7293
7294                 /* When a filter for the default address is "deleted",
7295                  * we return it to its initial configuration
7296                  */
7297                 if (adapter->mac_table[i].state & IGB_MAC_STATE_DEFAULT) {
7298                         adapter->mac_table[i].state =
7299                                 IGB_MAC_STATE_DEFAULT | IGB_MAC_STATE_IN_USE;
7300                         adapter->mac_table[i].queue =
7301                                 adapter->vfs_allocated_count;
7302                 } else {
7303                         adapter->mac_table[i].state = 0;
7304                         adapter->mac_table[i].queue = 0;
7305                         memset(adapter->mac_table[i].addr, 0, ETH_ALEN);
7306                 }
7307
7308                 igb_rar_set_index(adapter, i);
7309                 return 0;
7310         }
7311
7312         return -ENOENT;
7313 }
7314
7315 static int igb_del_mac_filter(struct igb_adapter *adapter, const u8 *addr,
7316                               const u8 queue)
7317 {
7318         return igb_del_mac_filter_flags(adapter, addr, queue, 0);
7319 }
7320
7321 int igb_add_mac_steering_filter(struct igb_adapter *adapter,
7322                                 const u8 *addr, u8 queue, u8 flags)
7323 {
7324         struct e1000_hw *hw = &adapter->hw;
7325
7326         /* In theory, this should be supported on 82575 as well, but
7327          * that part wasn't easily accessible during development.
7328          */
7329         if (hw->mac.type != e1000_i210)
7330                 return -EOPNOTSUPP;
7331
7332         return igb_add_mac_filter_flags(adapter, addr, queue,
7333                                         IGB_MAC_STATE_QUEUE_STEERING | flags);
7334 }
7335
7336 int igb_del_mac_steering_filter(struct igb_adapter *adapter,
7337                                 const u8 *addr, u8 queue, u8 flags)
7338 {
7339         return igb_del_mac_filter_flags(adapter, addr, queue,
7340                                         IGB_MAC_STATE_QUEUE_STEERING | flags);
7341 }
7342
7343 static int igb_uc_sync(struct net_device *netdev, const unsigned char *addr)
7344 {
7345         struct igb_adapter *adapter = netdev_priv(netdev);
7346         int ret;
7347
7348         ret = igb_add_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7349
7350         return min_t(int, ret, 0);
7351 }
7352
7353 static int igb_uc_unsync(struct net_device *netdev, const unsigned char *addr)
7354 {
7355         struct igb_adapter *adapter = netdev_priv(netdev);
7356
7357         igb_del_mac_filter(adapter, addr, adapter->vfs_allocated_count);
7358
7359         return 0;
7360 }
7361
7362 static int igb_set_vf_mac_filter(struct igb_adapter *adapter, const int vf,
7363                                  const u32 info, const u8 *addr)
7364 {
7365         struct pci_dev *pdev = adapter->pdev;
7366         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7367         struct list_head *pos;
7368         struct vf_mac_filter *entry = NULL;
7369         int ret = 0;
7370
7371         switch (info) {
7372         case E1000_VF_MAC_FILTER_CLR:
7373                 /* remove all unicast MAC filters related to the current VF */
7374                 list_for_each(pos, &adapter->vf_macs.l) {
7375                         entry = list_entry(pos, struct vf_mac_filter, l);
7376                         if (entry->vf == vf) {
7377                                 entry->vf = -1;
7378                                 entry->free = true;
7379                                 igb_del_mac_filter(adapter, entry->vf_mac, vf);
7380                         }
7381                 }
7382                 break;
7383         case E1000_VF_MAC_FILTER_ADD:
7384                 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7385                     !vf_data->trusted) {
7386                         dev_warn(&pdev->dev,
7387                                  "VF %d requested MAC filter but is administratively denied\n",
7388                                  vf);
7389                         return -EINVAL;
7390                 }
7391                 if (!is_valid_ether_addr(addr)) {
7392                         dev_warn(&pdev->dev,
7393                                  "VF %d attempted to set invalid MAC filter\n",
7394                                  vf);
7395                         return -EINVAL;
7396                 }
7397
7398                 /* try to find empty slot in the list */
7399                 list_for_each(pos, &adapter->vf_macs.l) {
7400                         entry = list_entry(pos, struct vf_mac_filter, l);
7401                         if (entry->free)
7402                                 break;
7403                 }
7404
7405                 if (entry && entry->free) {
7406                         entry->free = false;
7407                         entry->vf = vf;
7408                         ether_addr_copy(entry->vf_mac, addr);
7409
7410                         ret = igb_add_mac_filter(adapter, addr, vf);
7411                         ret = min_t(int, ret, 0);
7412                 } else {
7413                         ret = -ENOSPC;
7414                 }
7415
7416                 if (ret == -ENOSPC)
7417                         dev_warn(&pdev->dev,
7418                                  "VF %d has requested MAC filter but there is no space for it\n",
7419                                  vf);
7420                 break;
7421         default:
7422                 ret = -EINVAL;
7423                 break;
7424         }
7425
7426         return ret;
7427 }
7428
7429 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
7430 {
7431         struct pci_dev *pdev = adapter->pdev;
7432         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7433         u32 info = msg[0] & E1000_VT_MSGINFO_MASK;
7434
7435         /* The VF MAC Address is stored in a packed array of bytes
7436          * starting at the second 32 bit word of the msg array
7437          */
7438         unsigned char *addr = (unsigned char *)&msg[1];
7439         int ret = 0;
7440
7441         if (!info) {
7442                 if ((vf_data->flags & IGB_VF_FLAG_PF_SET_MAC) &&
7443                     !vf_data->trusted) {
7444                         dev_warn(&pdev->dev,
7445                                  "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
7446                                  vf);
7447                         return -EINVAL;
7448                 }
7449
7450                 if (!is_valid_ether_addr(addr)) {
7451                         dev_warn(&pdev->dev,
7452                                  "VF %d attempted to set invalid MAC\n",
7453                                  vf);
7454                         return -EINVAL;
7455                 }
7456
7457                 ret = igb_set_vf_mac(adapter, vf, addr);
7458         } else {
7459                 ret = igb_set_vf_mac_filter(adapter, vf, info, addr);
7460         }
7461
7462         return ret;
7463 }
7464
7465 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
7466 {
7467         struct e1000_hw *hw = &adapter->hw;
7468         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7469         u32 msg = E1000_VT_MSGTYPE_NACK;
7470
7471         /* if device isn't clear to send it shouldn't be reading either */
7472         if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
7473             time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
7474                 igb_write_mbx(hw, &msg, 1, vf);
7475                 vf_data->last_nack = jiffies;
7476         }
7477 }
7478
7479 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
7480 {
7481         struct pci_dev *pdev = adapter->pdev;
7482         u32 msgbuf[E1000_VFMAILBOX_SIZE];
7483         struct e1000_hw *hw = &adapter->hw;
7484         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
7485         s32 retval;
7486
7487         retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf, false);
7488
7489         if (retval) {
7490                 /* if receive failed revoke VF CTS stats and restart init */
7491                 dev_err(&pdev->dev, "Error receiving message from VF\n");
7492                 vf_data->flags &= ~IGB_VF_FLAG_CTS;
7493                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7494                         goto unlock;
7495                 goto out;
7496         }
7497
7498         /* this is a message we already processed, do nothing */
7499         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
7500                 goto unlock;
7501
7502         /* until the vf completes a reset it should not be
7503          * allowed to start any configuration.
7504          */
7505         if (msgbuf[0] == E1000_VF_RESET) {
7506                 /* unlocks mailbox */
7507                 igb_vf_reset_msg(adapter, vf);
7508                 return;
7509         }
7510
7511         if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
7512                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
7513                         goto unlock;
7514                 retval = -1;
7515                 goto out;
7516         }
7517
7518         switch ((msgbuf[0] & 0xFFFF)) {
7519         case E1000_VF_SET_MAC_ADDR:
7520                 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
7521                 break;
7522         case E1000_VF_SET_PROMISC:
7523                 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
7524                 break;
7525         case E1000_VF_SET_MULTICAST:
7526                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
7527                 break;
7528         case E1000_VF_SET_LPE:
7529                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
7530                 break;
7531         case E1000_VF_SET_VLAN:
7532                 retval = -1;
7533                 if (vf_data->pf_vlan)
7534                         dev_warn(&pdev->dev,
7535                                  "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
7536                                  vf);
7537                 else
7538                         retval = igb_set_vf_vlan_msg(adapter, msgbuf, vf);
7539                 break;
7540         default:
7541                 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
7542                 retval = -1;
7543                 break;
7544         }
7545
7546         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
7547 out:
7548         /* notify the VF of the results of what it sent us */
7549         if (retval)
7550                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
7551         else
7552                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
7553
7554         /* unlocks mailbox */
7555         igb_write_mbx(hw, msgbuf, 1, vf);
7556         return;
7557
7558 unlock:
7559         igb_unlock_mbx(hw, vf);
7560 }
7561
7562 static void igb_msg_task(struct igb_adapter *adapter)
7563 {
7564         struct e1000_hw *hw = &adapter->hw;
7565         u32 vf;
7566
7567         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
7568                 /* process any reset requests */
7569                 if (!igb_check_for_rst(hw, vf))
7570                         igb_vf_reset_event(adapter, vf);
7571
7572                 /* process any messages pending */
7573                 if (!igb_check_for_msg(hw, vf))
7574                         igb_rcv_msg_from_vf(adapter, vf);
7575
7576                 /* process any acks */
7577                 if (!igb_check_for_ack(hw, vf))
7578                         igb_rcv_ack_from_vf(adapter, vf);
7579         }
7580 }
7581
7582 /**
7583  *  igb_set_uta - Set unicast filter table address
7584  *  @adapter: board private structure
7585  *  @set: boolean indicating if we are setting or clearing bits
7586  *
7587  *  The unicast table address is a register array of 32-bit registers.
7588  *  The table is meant to be used in a way similar to how the MTA is used
7589  *  however due to certain limitations in the hardware it is necessary to
7590  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
7591  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
7592  **/
7593 static void igb_set_uta(struct igb_adapter *adapter, bool set)
7594 {
7595         struct e1000_hw *hw = &adapter->hw;
7596         u32 uta = set ? ~0 : 0;
7597         int i;
7598
7599         /* we only need to do this if VMDq is enabled */
7600         if (!adapter->vfs_allocated_count)
7601                 return;
7602
7603         for (i = hw->mac.uta_reg_count; i--;)
7604                 array_wr32(E1000_UTA, i, uta);
7605 }
7606
7607 /**
7608  *  igb_intr_msi - Interrupt Handler
7609  *  @irq: interrupt number
7610  *  @data: pointer to a network interface device structure
7611  **/
7612 static irqreturn_t igb_intr_msi(int irq, void *data)
7613 {
7614         struct igb_adapter *adapter = data;
7615         struct igb_q_vector *q_vector = adapter->q_vector[0];
7616         struct e1000_hw *hw = &adapter->hw;
7617         /* read ICR disables interrupts using IAM */
7618         u32 icr = rd32(E1000_ICR);
7619
7620         igb_write_itr(q_vector);
7621
7622         if (icr & E1000_ICR_DRSTA)
7623                 schedule_work(&adapter->reset_task);
7624
7625         if (icr & E1000_ICR_DOUTSYNC) {
7626                 /* HW is reporting DMA is out of sync */
7627                 adapter->stats.doosync++;
7628         }
7629
7630         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
7631                 hw->mac.get_link_status = 1;
7632                 if (!test_bit(__IGB_DOWN, &adapter->state))
7633                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
7634         }
7635
7636         if (icr & E1000_ICR_TS)
7637                 igb_tsync_interrupt(adapter);
7638
7639         napi_schedule(&q_vector->napi);
7640
7641         return IRQ_HANDLED;
7642 }
7643
7644 /**
7645  *  igb_intr - Legacy Interrupt Handler
7646  *  @irq: interrupt number
7647  *  @data: pointer to a network interface device structure
7648  **/
7649 static irqreturn_t igb_intr(int irq, void *data)
7650 {
7651         struct igb_adapter *adapter = data;
7652         struct igb_q_vector *q_vector = adapter->q_vector[0];
7653         struct e1000_hw *hw = &adapter->hw;
7654         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
7655          * need for the IMC write
7656          */
7657         u32 icr = rd32(E1000_ICR);
7658
7659         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
7660          * not set, then the adapter didn't send an interrupt
7661          */
7662         if (!(icr & E1000_ICR_INT_ASSERTED))
7663                 return IRQ_NONE;
7664
7665         igb_write_itr(q_vector);
7666
7667         if (icr & E1000_ICR_DRSTA)
7668                 schedule_work(&adapter->reset_task);
7669
7670         if (icr & E1000_ICR_DOUTSYNC) {
7671                 /* HW is reporting DMA is out of sync */
7672                 adapter->stats.doosync++;
7673         }
7674
7675         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
7676                 hw->mac.get_link_status = 1;
7677                 /* guard against interrupt when we're going down */
7678                 if (!test_bit(__IGB_DOWN, &adapter->state))
7679                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
7680         }
7681
7682         if (icr & E1000_ICR_TS)
7683                 igb_tsync_interrupt(adapter);
7684
7685         napi_schedule(&q_vector->napi);
7686
7687         return IRQ_HANDLED;
7688 }
7689
7690 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
7691 {
7692         struct igb_adapter *adapter = q_vector->adapter;
7693         struct e1000_hw *hw = &adapter->hw;
7694
7695         if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
7696             (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
7697                 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
7698                         igb_set_itr(q_vector);
7699                 else
7700                         igb_update_ring_itr(q_vector);
7701         }
7702
7703         if (!test_bit(__IGB_DOWN, &adapter->state)) {
7704                 if (adapter->flags & IGB_FLAG_HAS_MSIX)
7705                         wr32(E1000_EIMS, q_vector->eims_value);
7706                 else
7707                         igb_irq_enable(adapter);
7708         }
7709 }
7710
7711 /**
7712  *  igb_poll - NAPI Rx polling callback
7713  *  @napi: napi polling structure
7714  *  @budget: count of how many packets we should handle
7715  **/
7716 static int igb_poll(struct napi_struct *napi, int budget)
7717 {
7718         struct igb_q_vector *q_vector = container_of(napi,
7719                                                      struct igb_q_vector,
7720                                                      napi);
7721         bool clean_complete = true;
7722         int work_done = 0;
7723
7724 #ifdef CONFIG_IGB_DCA
7725         if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
7726                 igb_update_dca(q_vector);
7727 #endif
7728         if (q_vector->tx.ring)
7729                 clean_complete = igb_clean_tx_irq(q_vector, budget);
7730
7731         if (q_vector->rx.ring) {
7732                 int cleaned = igb_clean_rx_irq(q_vector, budget);
7733
7734                 work_done += cleaned;
7735                 if (cleaned >= budget)
7736                         clean_complete = false;
7737         }
7738
7739         /* If all work not completed, return budget and keep polling */
7740         if (!clean_complete)
7741                 return budget;
7742
7743         /* Exit the polling mode, but don't re-enable interrupts if stack might
7744          * poll us due to busy-polling
7745          */
7746         if (likely(napi_complete_done(napi, work_done)))
7747                 igb_ring_irq_enable(q_vector);
7748
7749         return min(work_done, budget - 1);
7750 }
7751
7752 /**
7753  *  igb_clean_tx_irq - Reclaim resources after transmit completes
7754  *  @q_vector: pointer to q_vector containing needed info
7755  *  @napi_budget: Used to determine if we are in netpoll
7756  *
7757  *  returns true if ring is completely cleaned
7758  **/
7759 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector, int napi_budget)
7760 {
7761         struct igb_adapter *adapter = q_vector->adapter;
7762         struct igb_ring *tx_ring = q_vector->tx.ring;
7763         struct igb_tx_buffer *tx_buffer;
7764         union e1000_adv_tx_desc *tx_desc;
7765         unsigned int total_bytes = 0, total_packets = 0;
7766         unsigned int budget = q_vector->tx.work_limit;
7767         unsigned int i = tx_ring->next_to_clean;
7768
7769         if (test_bit(__IGB_DOWN, &adapter->state))
7770                 return true;
7771
7772         tx_buffer = &tx_ring->tx_buffer_info[i];
7773         tx_desc = IGB_TX_DESC(tx_ring, i);
7774         i -= tx_ring->count;
7775
7776         do {
7777                 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
7778
7779                 /* if next_to_watch is not set then there is no work pending */
7780                 if (!eop_desc)
7781                         break;
7782
7783                 /* prevent any other reads prior to eop_desc */
7784                 smp_rmb();
7785
7786                 /* if DD is not set pending work has not been completed */
7787                 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
7788                         break;
7789
7790                 /* clear next_to_watch to prevent false hangs */
7791                 tx_buffer->next_to_watch = NULL;
7792
7793                 /* update the statistics for this packet */
7794                 total_bytes += tx_buffer->bytecount;
7795                 total_packets += tx_buffer->gso_segs;
7796
7797                 /* free the skb */
7798                 napi_consume_skb(tx_buffer->skb, napi_budget);
7799
7800                 /* unmap skb header data */
7801                 dma_unmap_single(tx_ring->dev,
7802                                  dma_unmap_addr(tx_buffer, dma),
7803                                  dma_unmap_len(tx_buffer, len),
7804                                  DMA_TO_DEVICE);
7805
7806                 /* clear tx_buffer data */
7807                 dma_unmap_len_set(tx_buffer, len, 0);
7808
7809                 /* clear last DMA location and unmap remaining buffers */
7810                 while (tx_desc != eop_desc) {
7811                         tx_buffer++;
7812                         tx_desc++;
7813                         i++;
7814                         if (unlikely(!i)) {
7815                                 i -= tx_ring->count;
7816                                 tx_buffer = tx_ring->tx_buffer_info;
7817                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
7818                         }
7819
7820                         /* unmap any remaining paged data */
7821                         if (dma_unmap_len(tx_buffer, len)) {
7822                                 dma_unmap_page(tx_ring->dev,
7823                                                dma_unmap_addr(tx_buffer, dma),
7824                                                dma_unmap_len(tx_buffer, len),
7825                                                DMA_TO_DEVICE);
7826                                 dma_unmap_len_set(tx_buffer, len, 0);
7827                         }
7828                 }
7829
7830                 /* move us one more past the eop_desc for start of next pkt */
7831                 tx_buffer++;
7832                 tx_desc++;
7833                 i++;
7834                 if (unlikely(!i)) {
7835                         i -= tx_ring->count;
7836                         tx_buffer = tx_ring->tx_buffer_info;
7837                         tx_desc = IGB_TX_DESC(tx_ring, 0);
7838                 }
7839
7840                 /* issue prefetch for next Tx descriptor */
7841                 prefetch(tx_desc);
7842
7843                 /* update budget accounting */
7844                 budget--;
7845         } while (likely(budget));
7846
7847         netdev_tx_completed_queue(txring_txq(tx_ring),
7848                                   total_packets, total_bytes);
7849         i += tx_ring->count;
7850         tx_ring->next_to_clean = i;
7851         u64_stats_update_begin(&tx_ring->tx_syncp);
7852         tx_ring->tx_stats.bytes += total_bytes;
7853         tx_ring->tx_stats.packets += total_packets;
7854         u64_stats_update_end(&tx_ring->tx_syncp);
7855         q_vector->tx.total_bytes += total_bytes;
7856         q_vector->tx.total_packets += total_packets;
7857
7858         if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
7859                 struct e1000_hw *hw = &adapter->hw;
7860
7861                 /* Detect a transmit hang in hardware, this serializes the
7862                  * check with the clearing of time_stamp and movement of i
7863                  */
7864                 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
7865                 if (tx_buffer->next_to_watch &&
7866                     time_after(jiffies, tx_buffer->time_stamp +
7867                                (adapter->tx_timeout_factor * HZ)) &&
7868                     !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
7869
7870                         /* detected Tx unit hang */
7871                         dev_err(tx_ring->dev,
7872                                 "Detected Tx Unit Hang\n"
7873                                 "  Tx Queue             <%d>\n"
7874                                 "  TDH                  <%x>\n"
7875                                 "  TDT                  <%x>\n"
7876                                 "  next_to_use          <%x>\n"
7877                                 "  next_to_clean        <%x>\n"
7878                                 "buffer_info[next_to_clean]\n"
7879                                 "  time_stamp           <%lx>\n"
7880                                 "  next_to_watch        <%p>\n"
7881                                 "  jiffies              <%lx>\n"
7882                                 "  desc.status          <%x>\n",
7883                                 tx_ring->queue_index,
7884                                 rd32(E1000_TDH(tx_ring->reg_idx)),
7885                                 readl(tx_ring->tail),
7886                                 tx_ring->next_to_use,
7887                                 tx_ring->next_to_clean,
7888                                 tx_buffer->time_stamp,
7889                                 tx_buffer->next_to_watch,
7890                                 jiffies,
7891                                 tx_buffer->next_to_watch->wb.status);
7892                         netif_stop_subqueue(tx_ring->netdev,
7893                                             tx_ring->queue_index);
7894
7895                         /* we are about to reset, no point in enabling stuff */
7896                         return true;
7897                 }
7898         }
7899
7900 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
7901         if (unlikely(total_packets &&
7902             netif_carrier_ok(tx_ring->netdev) &&
7903             igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
7904                 /* Make sure that anybody stopping the queue after this
7905                  * sees the new next_to_clean.
7906                  */
7907                 smp_mb();
7908                 if (__netif_subqueue_stopped(tx_ring->netdev,
7909                                              tx_ring->queue_index) &&
7910                     !(test_bit(__IGB_DOWN, &adapter->state))) {
7911                         netif_wake_subqueue(tx_ring->netdev,
7912                                             tx_ring->queue_index);
7913
7914                         u64_stats_update_begin(&tx_ring->tx_syncp);
7915                         tx_ring->tx_stats.restart_queue++;
7916                         u64_stats_update_end(&tx_ring->tx_syncp);
7917                 }
7918         }
7919
7920         return !!budget;
7921 }
7922
7923 /**
7924  *  igb_reuse_rx_page - page flip buffer and store it back on the ring
7925  *  @rx_ring: rx descriptor ring to store buffers on
7926  *  @old_buff: donor buffer to have page reused
7927  *
7928  *  Synchronizes page for reuse by the adapter
7929  **/
7930 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
7931                               struct igb_rx_buffer *old_buff)
7932 {
7933         struct igb_rx_buffer *new_buff;
7934         u16 nta = rx_ring->next_to_alloc;
7935
7936         new_buff = &rx_ring->rx_buffer_info[nta];
7937
7938         /* update, and store next to alloc */
7939         nta++;
7940         rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
7941
7942         /* Transfer page from old buffer to new buffer.
7943          * Move each member individually to avoid possible store
7944          * forwarding stalls.
7945          */
7946         new_buff->dma           = old_buff->dma;
7947         new_buff->page          = old_buff->page;
7948         new_buff->page_offset   = old_buff->page_offset;
7949         new_buff->pagecnt_bias  = old_buff->pagecnt_bias;
7950 }
7951
7952 static inline bool igb_page_is_reserved(struct page *page)
7953 {
7954         return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
7955 }
7956
7957 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer)
7958 {
7959         unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
7960         struct page *page = rx_buffer->page;
7961
7962         /* avoid re-using remote pages */
7963         if (unlikely(igb_page_is_reserved(page)))
7964                 return false;
7965
7966 #if (PAGE_SIZE < 8192)
7967         /* if we are only owner of page we can reuse it */
7968         if (unlikely((page_ref_count(page) - pagecnt_bias) > 1))
7969                 return false;
7970 #else
7971 #define IGB_LAST_OFFSET \
7972         (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGB_RXBUFFER_2048)
7973
7974         if (rx_buffer->page_offset > IGB_LAST_OFFSET)
7975                 return false;
7976 #endif
7977
7978         /* If we have drained the page fragment pool we need to update
7979          * the pagecnt_bias and page count so that we fully restock the
7980          * number of references the driver holds.
7981          */
7982         if (unlikely(!pagecnt_bias)) {
7983                 page_ref_add(page, USHRT_MAX);
7984                 rx_buffer->pagecnt_bias = USHRT_MAX;
7985         }
7986
7987         return true;
7988 }
7989
7990 /**
7991  *  igb_add_rx_frag - Add contents of Rx buffer to sk_buff
7992  *  @rx_ring: rx descriptor ring to transact packets on
7993  *  @rx_buffer: buffer containing page to add
7994  *  @skb: sk_buff to place the data into
7995  *  @size: size of buffer to be added
7996  *
7997  *  This function will add the data contained in rx_buffer->page to the skb.
7998  **/
7999 static void igb_add_rx_frag(struct igb_ring *rx_ring,
8000                             struct igb_rx_buffer *rx_buffer,
8001                             struct sk_buff *skb,
8002                             unsigned int size)
8003 {
8004 #if (PAGE_SIZE < 8192)
8005         unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8006 #else
8007         unsigned int truesize = ring_uses_build_skb(rx_ring) ?
8008                                 SKB_DATA_ALIGN(IGB_SKB_PAD + size) :
8009                                 SKB_DATA_ALIGN(size);
8010 #endif
8011         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
8012                         rx_buffer->page_offset, size, truesize);
8013 #if (PAGE_SIZE < 8192)
8014         rx_buffer->page_offset ^= truesize;
8015 #else
8016         rx_buffer->page_offset += truesize;
8017 #endif
8018 }
8019
8020 static struct sk_buff *igb_construct_skb(struct igb_ring *rx_ring,
8021                                          struct igb_rx_buffer *rx_buffer,
8022                                          union e1000_adv_rx_desc *rx_desc,
8023                                          unsigned int size)
8024 {
8025         void *va = page_address(rx_buffer->page) + rx_buffer->page_offset;
8026 #if (PAGE_SIZE < 8192)
8027         unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8028 #else
8029         unsigned int truesize = SKB_DATA_ALIGN(size);
8030 #endif
8031         unsigned int headlen;
8032         struct sk_buff *skb;
8033
8034         /* prefetch first cache line of first page */
8035         prefetch(va);
8036 #if L1_CACHE_BYTES < 128
8037         prefetch(va + L1_CACHE_BYTES);
8038 #endif
8039
8040         /* allocate a skb to store the frags */
8041         skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGB_RX_HDR_LEN);
8042         if (unlikely(!skb))
8043                 return NULL;
8044
8045         if (unlikely(igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))) {
8046                 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
8047                 va += IGB_TS_HDR_LEN;
8048                 size -= IGB_TS_HDR_LEN;
8049         }
8050
8051         /* Determine available headroom for copy */
8052         headlen = size;
8053         if (headlen > IGB_RX_HDR_LEN)
8054                 headlen = eth_get_headlen(va, IGB_RX_HDR_LEN);
8055
8056         /* align pull length to size of long to optimize memcpy performance */
8057         memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long)));
8058
8059         /* update all of the pointers */
8060         size -= headlen;
8061         if (size) {
8062                 skb_add_rx_frag(skb, 0, rx_buffer->page,
8063                                 (va + headlen) - page_address(rx_buffer->page),
8064                                 size, truesize);
8065 #if (PAGE_SIZE < 8192)
8066                 rx_buffer->page_offset ^= truesize;
8067 #else
8068                 rx_buffer->page_offset += truesize;
8069 #endif
8070         } else {
8071                 rx_buffer->pagecnt_bias++;
8072         }
8073
8074         return skb;
8075 }
8076
8077 static struct sk_buff *igb_build_skb(struct igb_ring *rx_ring,
8078                                      struct igb_rx_buffer *rx_buffer,
8079                                      union e1000_adv_rx_desc *rx_desc,
8080                                      unsigned int size)
8081 {
8082         void *va = page_address(rx_buffer->page) + rx_buffer->page_offset;
8083 #if (PAGE_SIZE < 8192)
8084         unsigned int truesize = igb_rx_pg_size(rx_ring) / 2;
8085 #else
8086         unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
8087                                 SKB_DATA_ALIGN(IGB_SKB_PAD + size);
8088 #endif
8089         struct sk_buff *skb;
8090
8091         /* prefetch first cache line of first page */
8092         prefetch(va);
8093 #if L1_CACHE_BYTES < 128
8094         prefetch(va + L1_CACHE_BYTES);
8095 #endif
8096
8097         /* build an skb around the page buffer */
8098         skb = build_skb(va - IGB_SKB_PAD, truesize);
8099         if (unlikely(!skb))
8100                 return NULL;
8101
8102         /* update pointers within the skb to store the data */
8103         skb_reserve(skb, IGB_SKB_PAD);
8104         __skb_put(skb, size);
8105
8106         /* pull timestamp out of packet data */
8107         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
8108                 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb);
8109                 __skb_pull(skb, IGB_TS_HDR_LEN);
8110         }
8111
8112         /* update buffer offset */
8113 #if (PAGE_SIZE < 8192)
8114         rx_buffer->page_offset ^= truesize;
8115 #else
8116         rx_buffer->page_offset += truesize;
8117 #endif
8118
8119         return skb;
8120 }
8121
8122 static inline void igb_rx_checksum(struct igb_ring *ring,
8123                                    union e1000_adv_rx_desc *rx_desc,
8124                                    struct sk_buff *skb)
8125 {
8126         skb_checksum_none_assert(skb);
8127
8128         /* Ignore Checksum bit is set */
8129         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
8130                 return;
8131
8132         /* Rx checksum disabled via ethtool */
8133         if (!(ring->netdev->features & NETIF_F_RXCSUM))
8134                 return;
8135
8136         /* TCP/UDP checksum error bit is set */
8137         if (igb_test_staterr(rx_desc,
8138                              E1000_RXDEXT_STATERR_TCPE |
8139                              E1000_RXDEXT_STATERR_IPE)) {
8140                 /* work around errata with sctp packets where the TCPE aka
8141                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
8142                  * packets, (aka let the stack check the crc32c)
8143                  */
8144                 if (!((skb->len == 60) &&
8145                       test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
8146                         u64_stats_update_begin(&ring->rx_syncp);
8147                         ring->rx_stats.csum_err++;
8148                         u64_stats_update_end(&ring->rx_syncp);
8149                 }
8150                 /* let the stack verify checksum errors */
8151                 return;
8152         }
8153         /* It must be a TCP or UDP packet with a valid checksum */
8154         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
8155                                       E1000_RXD_STAT_UDPCS))
8156                 skb->ip_summed = CHECKSUM_UNNECESSARY;
8157
8158         dev_dbg(ring->dev, "cksum success: bits %08X\n",
8159                 le32_to_cpu(rx_desc->wb.upper.status_error));
8160 }
8161
8162 static inline void igb_rx_hash(struct igb_ring *ring,
8163                                union e1000_adv_rx_desc *rx_desc,
8164                                struct sk_buff *skb)
8165 {
8166         if (ring->netdev->features & NETIF_F_RXHASH)
8167                 skb_set_hash(skb,
8168                              le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
8169                              PKT_HASH_TYPE_L3);
8170 }
8171
8172 /**
8173  *  igb_is_non_eop - process handling of non-EOP buffers
8174  *  @rx_ring: Rx ring being processed
8175  *  @rx_desc: Rx descriptor for current buffer
8176  *  @skb: current socket buffer containing buffer in progress
8177  *
8178  *  This function updates next to clean.  If the buffer is an EOP buffer
8179  *  this function exits returning false, otherwise it will place the
8180  *  sk_buff in the next buffer to be chained and return true indicating
8181  *  that this is in fact a non-EOP buffer.
8182  **/
8183 static bool igb_is_non_eop(struct igb_ring *rx_ring,
8184                            union e1000_adv_rx_desc *rx_desc)
8185 {
8186         u32 ntc = rx_ring->next_to_clean + 1;
8187
8188         /* fetch, update, and store next to clean */
8189         ntc = (ntc < rx_ring->count) ? ntc : 0;
8190         rx_ring->next_to_clean = ntc;
8191
8192         prefetch(IGB_RX_DESC(rx_ring, ntc));
8193
8194         if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
8195                 return false;
8196
8197         return true;
8198 }
8199
8200 /**
8201  *  igb_cleanup_headers - Correct corrupted or empty headers
8202  *  @rx_ring: rx descriptor ring packet is being transacted on
8203  *  @rx_desc: pointer to the EOP Rx descriptor
8204  *  @skb: pointer to current skb being fixed
8205  *
8206  *  Address the case where we are pulling data in on pages only
8207  *  and as such no data is present in the skb header.
8208  *
8209  *  In addition if skb is not at least 60 bytes we need to pad it so that
8210  *  it is large enough to qualify as a valid Ethernet frame.
8211  *
8212  *  Returns true if an error was encountered and skb was freed.
8213  **/
8214 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
8215                                 union e1000_adv_rx_desc *rx_desc,
8216                                 struct sk_buff *skb)
8217 {
8218         if (unlikely((igb_test_staterr(rx_desc,
8219                                        E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
8220                 struct net_device *netdev = rx_ring->netdev;
8221                 if (!(netdev->features & NETIF_F_RXALL)) {
8222                         dev_kfree_skb_any(skb);
8223                         return true;
8224                 }
8225         }
8226
8227         /* if eth_skb_pad returns an error the skb was freed */
8228         if (eth_skb_pad(skb))
8229                 return true;
8230
8231         return false;
8232 }
8233
8234 /**
8235  *  igb_process_skb_fields - Populate skb header fields from Rx descriptor
8236  *  @rx_ring: rx descriptor ring packet is being transacted on
8237  *  @rx_desc: pointer to the EOP Rx descriptor
8238  *  @skb: pointer to current skb being populated
8239  *
8240  *  This function checks the ring, descriptor, and packet information in
8241  *  order to populate the hash, checksum, VLAN, timestamp, protocol, and
8242  *  other fields within the skb.
8243  **/
8244 static void igb_process_skb_fields(struct igb_ring *rx_ring,
8245                                    union e1000_adv_rx_desc *rx_desc,
8246                                    struct sk_buff *skb)
8247 {
8248         struct net_device *dev = rx_ring->netdev;
8249
8250         igb_rx_hash(rx_ring, rx_desc, skb);
8251
8252         igb_rx_checksum(rx_ring, rx_desc, skb);
8253
8254         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) &&
8255             !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP))
8256                 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb);
8257
8258         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
8259             igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
8260                 u16 vid;
8261
8262                 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
8263                     test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
8264                         vid = be16_to_cpu(rx_desc->wb.upper.vlan);
8265                 else
8266                         vid = le16_to_cpu(rx_desc->wb.upper.vlan);
8267
8268                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
8269         }
8270
8271         skb_record_rx_queue(skb, rx_ring->queue_index);
8272
8273         skb->protocol = eth_type_trans(skb, rx_ring->netdev);
8274 }
8275
8276 static struct igb_rx_buffer *igb_get_rx_buffer(struct igb_ring *rx_ring,
8277                                                const unsigned int size)
8278 {
8279         struct igb_rx_buffer *rx_buffer;
8280
8281         rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
8282         prefetchw(rx_buffer->page);
8283
8284         /* we are reusing so sync this buffer for CPU use */
8285         dma_sync_single_range_for_cpu(rx_ring->dev,
8286                                       rx_buffer->dma,
8287                                       rx_buffer->page_offset,
8288                                       size,
8289                                       DMA_FROM_DEVICE);
8290
8291         rx_buffer->pagecnt_bias--;
8292
8293         return rx_buffer;
8294 }
8295
8296 static void igb_put_rx_buffer(struct igb_ring *rx_ring,
8297                               struct igb_rx_buffer *rx_buffer)
8298 {
8299         if (igb_can_reuse_rx_page(rx_buffer)) {
8300                 /* hand second half of page back to the ring */
8301                 igb_reuse_rx_page(rx_ring, rx_buffer);
8302         } else {
8303                 /* We are not reusing the buffer so unmap it and free
8304                  * any references we are holding to it
8305                  */
8306                 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
8307                                      igb_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
8308                                      IGB_RX_DMA_ATTR);
8309                 __page_frag_cache_drain(rx_buffer->page,
8310                                         rx_buffer->pagecnt_bias);
8311         }
8312
8313         /* clear contents of rx_buffer */
8314         rx_buffer->page = NULL;
8315 }
8316
8317 static int igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
8318 {
8319         struct igb_ring *rx_ring = q_vector->rx.ring;
8320         struct sk_buff *skb = rx_ring->skb;
8321         unsigned int total_bytes = 0, total_packets = 0;
8322         u16 cleaned_count = igb_desc_unused(rx_ring);
8323
8324         while (likely(total_packets < budget)) {
8325                 union e1000_adv_rx_desc *rx_desc;
8326                 struct igb_rx_buffer *rx_buffer;
8327                 unsigned int size;
8328
8329                 /* return some buffers to hardware, one at a time is too slow */
8330                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
8331                         igb_alloc_rx_buffers(rx_ring, cleaned_count);
8332                         cleaned_count = 0;
8333                 }
8334
8335                 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
8336                 size = le16_to_cpu(rx_desc->wb.upper.length);
8337                 if (!size)
8338                         break;
8339
8340                 /* This memory barrier is needed to keep us from reading
8341                  * any other fields out of the rx_desc until we know the
8342                  * descriptor has been written back
8343                  */
8344                 dma_rmb();
8345
8346                 rx_buffer = igb_get_rx_buffer(rx_ring, size);
8347
8348                 /* retrieve a buffer from the ring */
8349                 if (skb)
8350                         igb_add_rx_frag(rx_ring, rx_buffer, skb, size);
8351                 else if (ring_uses_build_skb(rx_ring))
8352                         skb = igb_build_skb(rx_ring, rx_buffer, rx_desc, size);
8353                 else
8354                         skb = igb_construct_skb(rx_ring, rx_buffer,
8355                                                 rx_desc, size);
8356
8357                 /* exit if we failed to retrieve a buffer */
8358                 if (!skb) {
8359                         rx_ring->rx_stats.alloc_failed++;
8360                         rx_buffer->pagecnt_bias++;
8361                         break;
8362                 }
8363
8364                 igb_put_rx_buffer(rx_ring, rx_buffer);
8365                 cleaned_count++;
8366
8367                 /* fetch next buffer in frame if non-eop */
8368                 if (igb_is_non_eop(rx_ring, rx_desc))
8369                         continue;
8370
8371                 /* verify the packet layout is correct */
8372                 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
8373                         skb = NULL;
8374                         continue;
8375                 }
8376
8377                 /* probably a little skewed due to removing CRC */
8378                 total_bytes += skb->len;
8379
8380                 /* populate checksum, timestamp, VLAN, and protocol */
8381                 igb_process_skb_fields(rx_ring, rx_desc, skb);
8382
8383                 napi_gro_receive(&q_vector->napi, skb);
8384
8385                 /* reset skb pointer */
8386                 skb = NULL;
8387
8388                 /* update budget accounting */
8389                 total_packets++;
8390         }
8391
8392         /* place incomplete frames back on ring for completion */
8393         rx_ring->skb = skb;
8394
8395         u64_stats_update_begin(&rx_ring->rx_syncp);
8396         rx_ring->rx_stats.packets += total_packets;
8397         rx_ring->rx_stats.bytes += total_bytes;
8398         u64_stats_update_end(&rx_ring->rx_syncp);
8399         q_vector->rx.total_packets += total_packets;
8400         q_vector->rx.total_bytes += total_bytes;
8401
8402         if (cleaned_count)
8403                 igb_alloc_rx_buffers(rx_ring, cleaned_count);
8404
8405         return total_packets;
8406 }
8407
8408 static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring)
8409 {
8410         return ring_uses_build_skb(rx_ring) ? IGB_SKB_PAD : 0;
8411 }
8412
8413 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
8414                                   struct igb_rx_buffer *bi)
8415 {
8416         struct page *page = bi->page;
8417         dma_addr_t dma;
8418
8419         /* since we are recycling buffers we should seldom need to alloc */
8420         if (likely(page))
8421                 return true;
8422
8423         /* alloc new page for storage */
8424         page = dev_alloc_pages(igb_rx_pg_order(rx_ring));
8425         if (unlikely(!page)) {
8426                 rx_ring->rx_stats.alloc_failed++;
8427                 return false;
8428         }
8429
8430         /* map page for use */
8431         dma = dma_map_page_attrs(rx_ring->dev, page, 0,
8432                                  igb_rx_pg_size(rx_ring),
8433                                  DMA_FROM_DEVICE,
8434                                  IGB_RX_DMA_ATTR);
8435
8436         /* if mapping failed free memory back to system since
8437          * there isn't much point in holding memory we can't use
8438          */
8439         if (dma_mapping_error(rx_ring->dev, dma)) {
8440                 __free_pages(page, igb_rx_pg_order(rx_ring));
8441
8442                 rx_ring->rx_stats.alloc_failed++;
8443                 return false;
8444         }
8445
8446         bi->dma = dma;
8447         bi->page = page;
8448         bi->page_offset = igb_rx_offset(rx_ring);
8449         bi->pagecnt_bias = 1;
8450
8451         return true;
8452 }
8453
8454 /**
8455  *  igb_alloc_rx_buffers - Replace used receive buffers; packet split
8456  *  @adapter: address of board private structure
8457  **/
8458 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
8459 {
8460         union e1000_adv_rx_desc *rx_desc;
8461         struct igb_rx_buffer *bi;
8462         u16 i = rx_ring->next_to_use;
8463         u16 bufsz;
8464
8465         /* nothing to do */
8466         if (!cleaned_count)
8467                 return;
8468
8469         rx_desc = IGB_RX_DESC(rx_ring, i);
8470         bi = &rx_ring->rx_buffer_info[i];
8471         i -= rx_ring->count;
8472
8473         bufsz = igb_rx_bufsz(rx_ring);
8474
8475         do {
8476                 if (!igb_alloc_mapped_page(rx_ring, bi))
8477                         break;
8478
8479                 /* sync the buffer for use by the device */
8480                 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
8481                                                  bi->page_offset, bufsz,
8482                                                  DMA_FROM_DEVICE);
8483
8484                 /* Refresh the desc even if buffer_addrs didn't change
8485                  * because each write-back erases this info.
8486                  */
8487                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
8488
8489                 rx_desc++;
8490                 bi++;
8491                 i++;
8492                 if (unlikely(!i)) {
8493                         rx_desc = IGB_RX_DESC(rx_ring, 0);
8494                         bi = rx_ring->rx_buffer_info;
8495                         i -= rx_ring->count;
8496                 }
8497
8498                 /* clear the length for the next_to_use descriptor */
8499                 rx_desc->wb.upper.length = 0;
8500
8501                 cleaned_count--;
8502         } while (cleaned_count);
8503
8504         i += rx_ring->count;
8505
8506         if (rx_ring->next_to_use != i) {
8507                 /* record the next descriptor to use */
8508                 rx_ring->next_to_use = i;
8509
8510                 /* update next to alloc since we have filled the ring */
8511                 rx_ring->next_to_alloc = i;
8512
8513                 /* Force memory writes to complete before letting h/w
8514                  * know there are new descriptors to fetch.  (Only
8515                  * applicable for weak-ordered memory model archs,
8516                  * such as IA-64).
8517                  */
8518                 dma_wmb();
8519                 writel(i, rx_ring->tail);
8520         }
8521 }
8522
8523 /**
8524  * igb_mii_ioctl -
8525  * @netdev:
8526  * @ifreq:
8527  * @cmd:
8528  **/
8529 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
8530 {
8531         struct igb_adapter *adapter = netdev_priv(netdev);
8532         struct mii_ioctl_data *data = if_mii(ifr);
8533
8534         if (adapter->hw.phy.media_type != e1000_media_type_copper)
8535                 return -EOPNOTSUPP;
8536
8537         switch (cmd) {
8538         case SIOCGMIIPHY:
8539                 data->phy_id = adapter->hw.phy.addr;
8540                 break;
8541         case SIOCGMIIREG:
8542                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
8543                                      &data->val_out))
8544                         return -EIO;
8545                 break;
8546         case SIOCSMIIREG:
8547         default:
8548                 return -EOPNOTSUPP;
8549         }
8550         return 0;
8551 }
8552
8553 /**
8554  * igb_ioctl -
8555  * @netdev:
8556  * @ifreq:
8557  * @cmd:
8558  **/
8559 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
8560 {
8561         switch (cmd) {
8562         case SIOCGMIIPHY:
8563         case SIOCGMIIREG:
8564         case SIOCSMIIREG:
8565                 return igb_mii_ioctl(netdev, ifr, cmd);
8566         case SIOCGHWTSTAMP:
8567                 return igb_ptp_get_ts_config(netdev, ifr);
8568         case SIOCSHWTSTAMP:
8569                 return igb_ptp_set_ts_config(netdev, ifr);
8570         default:
8571                 return -EOPNOTSUPP;
8572         }
8573 }
8574
8575 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
8576 {
8577         struct igb_adapter *adapter = hw->back;
8578
8579         pci_read_config_word(adapter->pdev, reg, value);
8580 }
8581
8582 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value)
8583 {
8584         struct igb_adapter *adapter = hw->back;
8585
8586         pci_write_config_word(adapter->pdev, reg, *value);
8587 }
8588
8589 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
8590 {
8591         struct igb_adapter *adapter = hw->back;
8592
8593         if (pcie_capability_read_word(adapter->pdev, reg, value))
8594                 return -E1000_ERR_CONFIG;
8595
8596         return 0;
8597 }
8598
8599 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
8600 {
8601         struct igb_adapter *adapter = hw->back;
8602
8603         if (pcie_capability_write_word(adapter->pdev, reg, *value))
8604                 return -E1000_ERR_CONFIG;
8605
8606         return 0;
8607 }
8608
8609 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
8610 {
8611         struct igb_adapter *adapter = netdev_priv(netdev);
8612         struct e1000_hw *hw = &adapter->hw;
8613         u32 ctrl, rctl;
8614         bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
8615
8616         if (enable) {
8617                 /* enable VLAN tag insert/strip */
8618                 ctrl = rd32(E1000_CTRL);
8619                 ctrl |= E1000_CTRL_VME;
8620                 wr32(E1000_CTRL, ctrl);
8621
8622                 /* Disable CFI check */
8623                 rctl = rd32(E1000_RCTL);
8624                 rctl &= ~E1000_RCTL_CFIEN;
8625                 wr32(E1000_RCTL, rctl);
8626         } else {
8627                 /* disable VLAN tag insert/strip */
8628                 ctrl = rd32(E1000_CTRL);
8629                 ctrl &= ~E1000_CTRL_VME;
8630                 wr32(E1000_CTRL, ctrl);
8631         }
8632
8633         igb_set_vf_vlan_strip(adapter, adapter->vfs_allocated_count, enable);
8634 }
8635
8636 static int igb_vlan_rx_add_vid(struct net_device *netdev,
8637                                __be16 proto, u16 vid)
8638 {
8639         struct igb_adapter *adapter = netdev_priv(netdev);
8640         struct e1000_hw *hw = &adapter->hw;
8641         int pf_id = adapter->vfs_allocated_count;
8642
8643         /* add the filter since PF can receive vlans w/o entry in vlvf */
8644         if (!vid || !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
8645                 igb_vfta_set(hw, vid, pf_id, true, !!vid);
8646
8647         set_bit(vid, adapter->active_vlans);
8648
8649         return 0;
8650 }
8651
8652 static int igb_vlan_rx_kill_vid(struct net_device *netdev,
8653                                 __be16 proto, u16 vid)
8654 {
8655         struct igb_adapter *adapter = netdev_priv(netdev);
8656         int pf_id = adapter->vfs_allocated_count;
8657         struct e1000_hw *hw = &adapter->hw;
8658
8659         /* remove VID from filter table */
8660         if (vid && !(adapter->flags & IGB_FLAG_VLAN_PROMISC))
8661                 igb_vfta_set(hw, vid, pf_id, false, true);
8662
8663         clear_bit(vid, adapter->active_vlans);
8664
8665         return 0;
8666 }
8667
8668 static void igb_restore_vlan(struct igb_adapter *adapter)
8669 {
8670         u16 vid = 1;
8671
8672         igb_vlan_mode(adapter->netdev, adapter->netdev->features);
8673         igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
8674
8675         for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
8676                 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
8677 }
8678
8679 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
8680 {
8681         struct pci_dev *pdev = adapter->pdev;
8682         struct e1000_mac_info *mac = &adapter->hw.mac;
8683
8684         mac->autoneg = 0;
8685
8686         /* Make sure dplx is at most 1 bit and lsb of speed is not set
8687          * for the switch() below to work
8688          */
8689         if ((spd & 1) || (dplx & ~1))
8690                 goto err_inval;
8691
8692         /* Fiber NIC's only allow 1000 gbps Full duplex
8693          * and 100Mbps Full duplex for 100baseFx sfp
8694          */
8695         if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) {
8696                 switch (spd + dplx) {
8697                 case SPEED_10 + DUPLEX_HALF:
8698                 case SPEED_10 + DUPLEX_FULL:
8699                 case SPEED_100 + DUPLEX_HALF:
8700                         goto err_inval;
8701                 default:
8702                         break;
8703                 }
8704         }
8705
8706         switch (spd + dplx) {
8707         case SPEED_10 + DUPLEX_HALF:
8708                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
8709                 break;
8710         case SPEED_10 + DUPLEX_FULL:
8711                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
8712                 break;
8713         case SPEED_100 + DUPLEX_HALF:
8714                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
8715                 break;
8716         case SPEED_100 + DUPLEX_FULL:
8717                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
8718                 break;
8719         case SPEED_1000 + DUPLEX_FULL:
8720                 mac->autoneg = 1;
8721                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
8722                 break;
8723         case SPEED_1000 + DUPLEX_HALF: /* not supported */
8724         default:
8725                 goto err_inval;
8726         }
8727
8728         /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
8729         adapter->hw.phy.mdix = AUTO_ALL_MODES;
8730
8731         return 0;
8732
8733 err_inval:
8734         dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
8735         return -EINVAL;
8736 }
8737
8738 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
8739                           bool runtime)
8740 {
8741         struct net_device *netdev = pci_get_drvdata(pdev);
8742         struct igb_adapter *adapter = netdev_priv(netdev);
8743         struct e1000_hw *hw = &adapter->hw;
8744         u32 ctrl, rctl, status;
8745         u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
8746 #ifdef CONFIG_PM
8747         int retval = 0;
8748 #endif
8749
8750         rtnl_lock();
8751         netif_device_detach(netdev);
8752
8753         if (netif_running(netdev))
8754                 __igb_close(netdev, true);
8755
8756         igb_ptp_suspend(adapter);
8757
8758         igb_clear_interrupt_scheme(adapter);
8759         rtnl_unlock();
8760
8761 #ifdef CONFIG_PM
8762         if (!runtime) {
8763                 retval = pci_save_state(pdev);
8764                 if (retval)
8765                         return retval;
8766         }
8767 #endif
8768
8769         status = rd32(E1000_STATUS);
8770         if (status & E1000_STATUS_LU)
8771                 wufc &= ~E1000_WUFC_LNKC;
8772
8773         if (wufc) {
8774                 igb_setup_rctl(adapter);
8775                 igb_set_rx_mode(netdev);
8776
8777                 /* turn on all-multi mode if wake on multicast is enabled */
8778                 if (wufc & E1000_WUFC_MC) {
8779                         rctl = rd32(E1000_RCTL);
8780                         rctl |= E1000_RCTL_MPE;
8781                         wr32(E1000_RCTL, rctl);
8782                 }
8783
8784                 ctrl = rd32(E1000_CTRL);
8785                 /* advertise wake from D3Cold */
8786                 #define E1000_CTRL_ADVD3WUC 0x00100000
8787                 /* phy power management enable */
8788                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
8789                 ctrl |= E1000_CTRL_ADVD3WUC;
8790                 wr32(E1000_CTRL, ctrl);
8791
8792                 /* Allow time for pending master requests to run */
8793                 igb_disable_pcie_master(hw);
8794
8795                 wr32(E1000_WUC, E1000_WUC_PME_EN);
8796                 wr32(E1000_WUFC, wufc);
8797         } else {
8798                 wr32(E1000_WUC, 0);
8799                 wr32(E1000_WUFC, 0);
8800         }
8801
8802         *enable_wake = wufc || adapter->en_mng_pt;
8803         if (!*enable_wake)
8804                 igb_power_down_link(adapter);
8805         else
8806                 igb_power_up_link(adapter);
8807
8808         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
8809          * would have already happened in close and is redundant.
8810          */
8811         igb_release_hw_control(adapter);
8812
8813         pci_disable_device(pdev);
8814
8815         return 0;
8816 }
8817
8818 static void igb_deliver_wake_packet(struct net_device *netdev)
8819 {
8820         struct igb_adapter *adapter = netdev_priv(netdev);
8821         struct e1000_hw *hw = &adapter->hw;
8822         struct sk_buff *skb;
8823         u32 wupl;
8824
8825         wupl = rd32(E1000_WUPL) & E1000_WUPL_MASK;
8826
8827         /* WUPM stores only the first 128 bytes of the wake packet.
8828          * Read the packet only if we have the whole thing.
8829          */
8830         if ((wupl == 0) || (wupl > E1000_WUPM_BYTES))
8831                 return;
8832
8833         skb = netdev_alloc_skb_ip_align(netdev, E1000_WUPM_BYTES);
8834         if (!skb)
8835                 return;
8836
8837         skb_put(skb, wupl);
8838
8839         /* Ensure reads are 32-bit aligned */
8840         wupl = roundup(wupl, 4);
8841
8842         memcpy_fromio(skb->data, hw->hw_addr + E1000_WUPM_REG(0), wupl);
8843
8844         skb->protocol = eth_type_trans(skb, netdev);
8845         netif_rx(skb);
8846 }
8847
8848 static int __maybe_unused igb_suspend(struct device *dev)
8849 {
8850         int retval;
8851         bool wake;
8852         struct pci_dev *pdev = to_pci_dev(dev);
8853
8854         retval = __igb_shutdown(pdev, &wake, 0);
8855         if (retval)
8856                 return retval;
8857
8858         if (wake) {
8859                 pci_prepare_to_sleep(pdev);
8860         } else {
8861                 pci_wake_from_d3(pdev, false);
8862                 pci_set_power_state(pdev, PCI_D3hot);
8863         }
8864
8865         return 0;
8866 }
8867
8868 static int __maybe_unused igb_resume(struct device *dev)
8869 {
8870         struct pci_dev *pdev = to_pci_dev(dev);
8871         struct net_device *netdev = pci_get_drvdata(pdev);
8872         struct igb_adapter *adapter = netdev_priv(netdev);
8873         struct e1000_hw *hw = &adapter->hw;
8874         u32 err, val;
8875
8876         pci_set_power_state(pdev, PCI_D0);
8877         pci_restore_state(pdev);
8878         pci_save_state(pdev);
8879
8880         if (!pci_device_is_present(pdev))
8881                 return -ENODEV;
8882         err = pci_enable_device_mem(pdev);
8883         if (err) {
8884                 dev_err(&pdev->dev,
8885                         "igb: Cannot enable PCI device from suspend\n");
8886                 return err;
8887         }
8888         pci_set_master(pdev);
8889
8890         pci_enable_wake(pdev, PCI_D3hot, 0);
8891         pci_enable_wake(pdev, PCI_D3cold, 0);
8892
8893         if (igb_init_interrupt_scheme(adapter, true)) {
8894                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8895                 return -ENOMEM;
8896         }
8897
8898         igb_reset(adapter);
8899
8900         /* let the f/w know that the h/w is now under the control of the
8901          * driver.
8902          */
8903         igb_get_hw_control(adapter);
8904
8905         val = rd32(E1000_WUS);
8906         if (val & WAKE_PKT_WUS)
8907                 igb_deliver_wake_packet(netdev);
8908
8909         wr32(E1000_WUS, ~0);
8910
8911         rtnl_lock();
8912         if (!err && netif_running(netdev))
8913                 err = __igb_open(netdev, true);
8914
8915         if (!err)
8916                 netif_device_attach(netdev);
8917         rtnl_unlock();
8918
8919         return err;
8920 }
8921
8922 static int __maybe_unused igb_runtime_idle(struct device *dev)
8923 {
8924         struct pci_dev *pdev = to_pci_dev(dev);
8925         struct net_device *netdev = pci_get_drvdata(pdev);
8926         struct igb_adapter *adapter = netdev_priv(netdev);
8927
8928         if (!igb_has_link(adapter))
8929                 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
8930
8931         return -EBUSY;
8932 }
8933
8934 static int __maybe_unused igb_runtime_suspend(struct device *dev)
8935 {
8936         struct pci_dev *pdev = to_pci_dev(dev);
8937         int retval;
8938         bool wake;
8939
8940         retval = __igb_shutdown(pdev, &wake, 1);
8941         if (retval)
8942                 return retval;
8943
8944         if (wake) {
8945                 pci_prepare_to_sleep(pdev);
8946         } else {
8947                 pci_wake_from_d3(pdev, false);
8948                 pci_set_power_state(pdev, PCI_D3hot);
8949         }
8950
8951         return 0;
8952 }
8953
8954 static int __maybe_unused igb_runtime_resume(struct device *dev)
8955 {
8956         return igb_resume(dev);
8957 }
8958
8959 static void igb_shutdown(struct pci_dev *pdev)
8960 {
8961         bool wake;
8962
8963         __igb_shutdown(pdev, &wake, 0);
8964
8965         if (system_state == SYSTEM_POWER_OFF) {
8966                 pci_wake_from_d3(pdev, wake);
8967                 pci_set_power_state(pdev, PCI_D3hot);
8968         }
8969 }
8970
8971 #ifdef CONFIG_PCI_IOV
8972 static int igb_sriov_reinit(struct pci_dev *dev)
8973 {
8974         struct net_device *netdev = pci_get_drvdata(dev);
8975         struct igb_adapter *adapter = netdev_priv(netdev);
8976         struct pci_dev *pdev = adapter->pdev;
8977
8978         rtnl_lock();
8979
8980         if (netif_running(netdev))
8981                 igb_close(netdev);
8982         else
8983                 igb_reset(adapter);
8984
8985         igb_clear_interrupt_scheme(adapter);
8986
8987         igb_init_queue_configuration(adapter);
8988
8989         if (igb_init_interrupt_scheme(adapter, true)) {
8990                 rtnl_unlock();
8991                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
8992                 return -ENOMEM;
8993         }
8994
8995         if (netif_running(netdev))
8996                 igb_open(netdev);
8997
8998         rtnl_unlock();
8999
9000         return 0;
9001 }
9002
9003 static int igb_pci_disable_sriov(struct pci_dev *dev)
9004 {
9005         int err = igb_disable_sriov(dev);
9006
9007         if (!err)
9008                 err = igb_sriov_reinit(dev);
9009
9010         return err;
9011 }
9012
9013 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
9014 {
9015         int err = igb_enable_sriov(dev, num_vfs);
9016
9017         if (err)
9018                 goto out;
9019
9020         err = igb_sriov_reinit(dev);
9021         if (!err)
9022                 return num_vfs;
9023
9024 out:
9025         return err;
9026 }
9027
9028 #endif
9029 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
9030 {
9031 #ifdef CONFIG_PCI_IOV
9032         if (num_vfs == 0)
9033                 return igb_pci_disable_sriov(dev);
9034         else
9035                 return igb_pci_enable_sriov(dev, num_vfs);
9036 #endif
9037         return 0;
9038 }
9039
9040 /**
9041  *  igb_io_error_detected - called when PCI error is detected
9042  *  @pdev: Pointer to PCI device
9043  *  @state: The current pci connection state
9044  *
9045  *  This function is called after a PCI bus error affecting
9046  *  this device has been detected.
9047  **/
9048 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
9049                                               pci_channel_state_t state)
9050 {
9051         struct net_device *netdev = pci_get_drvdata(pdev);
9052         struct igb_adapter *adapter = netdev_priv(netdev);
9053
9054         netif_device_detach(netdev);
9055
9056         if (state == pci_channel_io_perm_failure)
9057                 return PCI_ERS_RESULT_DISCONNECT;
9058
9059         if (netif_running(netdev))
9060                 igb_down(adapter);
9061         pci_disable_device(pdev);
9062
9063         /* Request a slot slot reset. */
9064         return PCI_ERS_RESULT_NEED_RESET;
9065 }
9066
9067 /**
9068  *  igb_io_slot_reset - called after the pci bus has been reset.
9069  *  @pdev: Pointer to PCI device
9070  *
9071  *  Restart the card from scratch, as if from a cold-boot. Implementation
9072  *  resembles the first-half of the igb_resume routine.
9073  **/
9074 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
9075 {
9076         struct net_device *netdev = pci_get_drvdata(pdev);
9077         struct igb_adapter *adapter = netdev_priv(netdev);
9078         struct e1000_hw *hw = &adapter->hw;
9079         pci_ers_result_t result;
9080
9081         if (pci_enable_device_mem(pdev)) {
9082                 dev_err(&pdev->dev,
9083                         "Cannot re-enable PCI device after reset.\n");
9084                 result = PCI_ERS_RESULT_DISCONNECT;
9085         } else {
9086                 pci_set_master(pdev);
9087                 pci_restore_state(pdev);
9088                 pci_save_state(pdev);
9089
9090                 pci_enable_wake(pdev, PCI_D3hot, 0);
9091                 pci_enable_wake(pdev, PCI_D3cold, 0);
9092
9093                 /* In case of PCI error, adapter lose its HW address
9094                  * so we should re-assign it here.
9095                  */
9096                 hw->hw_addr = adapter->io_addr;
9097
9098                 igb_reset(adapter);
9099                 wr32(E1000_WUS, ~0);
9100                 result = PCI_ERS_RESULT_RECOVERED;
9101         }
9102
9103         return result;
9104 }
9105
9106 /**
9107  *  igb_io_resume - called when traffic can start flowing again.
9108  *  @pdev: Pointer to PCI device
9109  *
9110  *  This callback is called when the error recovery driver tells us that
9111  *  its OK to resume normal operation. Implementation resembles the
9112  *  second-half of the igb_resume routine.
9113  */
9114 static void igb_io_resume(struct pci_dev *pdev)
9115 {
9116         struct net_device *netdev = pci_get_drvdata(pdev);
9117         struct igb_adapter *adapter = netdev_priv(netdev);
9118
9119         if (netif_running(netdev)) {
9120                 if (igb_up(adapter)) {
9121                         dev_err(&pdev->dev, "igb_up failed after reset\n");
9122                         return;
9123                 }
9124         }
9125
9126         netif_device_attach(netdev);
9127
9128         /* let the f/w know that the h/w is now under the control of the
9129          * driver.
9130          */
9131         igb_get_hw_control(adapter);
9132 }
9133
9134 /**
9135  *  igb_rar_set_index - Sync RAL[index] and RAH[index] registers with MAC table
9136  *  @adapter: Pointer to adapter structure
9137  *  @index: Index of the RAR entry which need to be synced with MAC table
9138  **/
9139 static void igb_rar_set_index(struct igb_adapter *adapter, u32 index)
9140 {
9141         struct e1000_hw *hw = &adapter->hw;
9142         u32 rar_low, rar_high;
9143         u8 *addr = adapter->mac_table[index].addr;
9144
9145         /* HW expects these to be in network order when they are plugged
9146          * into the registers which are little endian.  In order to guarantee
9147          * that ordering we need to do an leXX_to_cpup here in order to be
9148          * ready for the byteswap that occurs with writel
9149          */
9150         rar_low = le32_to_cpup((__le32 *)(addr));
9151         rar_high = le16_to_cpup((__le16 *)(addr + 4));
9152
9153         /* Indicate to hardware the Address is Valid. */
9154         if (adapter->mac_table[index].state & IGB_MAC_STATE_IN_USE) {
9155                 if (is_valid_ether_addr(addr))
9156                         rar_high |= E1000_RAH_AV;
9157
9158                 if (adapter->mac_table[index].state & IGB_MAC_STATE_SRC_ADDR)
9159                         rar_high |= E1000_RAH_ASEL_SRC_ADDR;
9160
9161                 switch (hw->mac.type) {
9162                 case e1000_82575:
9163                 case e1000_i210:
9164                         if (adapter->mac_table[index].state &
9165                             IGB_MAC_STATE_QUEUE_STEERING)
9166                                 rar_high |= E1000_RAH_QSEL_ENABLE;
9167
9168                         rar_high |= E1000_RAH_POOL_1 *
9169                                     adapter->mac_table[index].queue;
9170                         break;
9171                 default:
9172                         rar_high |= E1000_RAH_POOL_1 <<
9173                                     adapter->mac_table[index].queue;
9174                         break;
9175                 }
9176         }
9177
9178         wr32(E1000_RAL(index), rar_low);
9179         wrfl();
9180         wr32(E1000_RAH(index), rar_high);
9181         wrfl();
9182 }
9183
9184 static int igb_set_vf_mac(struct igb_adapter *adapter,
9185                           int vf, unsigned char *mac_addr)
9186 {
9187         struct e1000_hw *hw = &adapter->hw;
9188         /* VF MAC addresses start at end of receive addresses and moves
9189          * towards the first, as a result a collision should not be possible
9190          */
9191         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
9192         unsigned char *vf_mac_addr = adapter->vf_data[vf].vf_mac_addresses;
9193
9194         ether_addr_copy(vf_mac_addr, mac_addr);
9195         ether_addr_copy(adapter->mac_table[rar_entry].addr, mac_addr);
9196         adapter->mac_table[rar_entry].queue = vf;
9197         adapter->mac_table[rar_entry].state |= IGB_MAC_STATE_IN_USE;
9198         igb_rar_set_index(adapter, rar_entry);
9199
9200         return 0;
9201 }
9202
9203 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
9204 {
9205         struct igb_adapter *adapter = netdev_priv(netdev);
9206
9207         if (vf >= adapter->vfs_allocated_count)
9208                 return -EINVAL;
9209
9210         /* Setting the VF MAC to 0 reverts the IGB_VF_FLAG_PF_SET_MAC
9211          * flag and allows to overwrite the MAC via VF netdev.  This
9212          * is necessary to allow libvirt a way to restore the original
9213          * MAC after unbinding vfio-pci and reloading igbvf after shutting
9214          * down a VM.
9215          */
9216         if (is_zero_ether_addr(mac)) {
9217                 adapter->vf_data[vf].flags &= ~IGB_VF_FLAG_PF_SET_MAC;
9218                 dev_info(&adapter->pdev->dev,
9219                          "remove administratively set MAC on VF %d\n",
9220                          vf);
9221         } else if (is_valid_ether_addr(mac)) {
9222                 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
9223                 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n",
9224                          mac, vf);
9225                 dev_info(&adapter->pdev->dev,
9226                          "Reload the VF driver to make this change effective.");
9227                 /* Generate additional warning if PF is down */
9228                 if (test_bit(__IGB_DOWN, &adapter->state)) {
9229                         dev_warn(&adapter->pdev->dev,
9230                                  "The VF MAC address has been set, but the PF device is not up.\n");
9231                         dev_warn(&adapter->pdev->dev,
9232                                  "Bring the PF device up before attempting to use the VF device.\n");
9233                 }
9234         } else {
9235                 return -EINVAL;
9236         }
9237         return igb_set_vf_mac(adapter, vf, mac);
9238 }
9239
9240 static int igb_link_mbps(int internal_link_speed)
9241 {
9242         switch (internal_link_speed) {
9243         case SPEED_100:
9244                 return 100;
9245         case SPEED_1000:
9246                 return 1000;
9247         default:
9248                 return 0;
9249         }
9250 }
9251
9252 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
9253                                   int link_speed)
9254 {
9255         int rf_dec, rf_int;
9256         u32 bcnrc_val;
9257
9258         if (tx_rate != 0) {
9259                 /* Calculate the rate factor values to set */
9260                 rf_int = link_speed / tx_rate;
9261                 rf_dec = (link_speed - (rf_int * tx_rate));
9262                 rf_dec = (rf_dec * BIT(E1000_RTTBCNRC_RF_INT_SHIFT)) /
9263                          tx_rate;
9264
9265                 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
9266                 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) &
9267                               E1000_RTTBCNRC_RF_INT_MASK);
9268                 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
9269         } else {
9270                 bcnrc_val = 0;
9271         }
9272
9273         wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
9274         /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
9275          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
9276          */
9277         wr32(E1000_RTTBCNRM, 0x14);
9278         wr32(E1000_RTTBCNRC, bcnrc_val);
9279 }
9280
9281 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
9282 {
9283         int actual_link_speed, i;
9284         bool reset_rate = false;
9285
9286         /* VF TX rate limit was not set or not supported */
9287         if ((adapter->vf_rate_link_speed == 0) ||
9288             (adapter->hw.mac.type != e1000_82576))
9289                 return;
9290
9291         actual_link_speed = igb_link_mbps(adapter->link_speed);
9292         if (actual_link_speed != adapter->vf_rate_link_speed) {
9293                 reset_rate = true;
9294                 adapter->vf_rate_link_speed = 0;
9295                 dev_info(&adapter->pdev->dev,
9296                          "Link speed has been changed. VF Transmit rate is disabled\n");
9297         }
9298
9299         for (i = 0; i < adapter->vfs_allocated_count; i++) {
9300                 if (reset_rate)
9301                         adapter->vf_data[i].tx_rate = 0;
9302
9303                 igb_set_vf_rate_limit(&adapter->hw, i,
9304                                       adapter->vf_data[i].tx_rate,
9305                                       actual_link_speed);
9306         }
9307 }
9308
9309 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf,
9310                              int min_tx_rate, int max_tx_rate)
9311 {
9312         struct igb_adapter *adapter = netdev_priv(netdev);
9313         struct e1000_hw *hw = &adapter->hw;
9314         int actual_link_speed;
9315
9316         if (hw->mac.type != e1000_82576)
9317                 return -EOPNOTSUPP;
9318
9319         if (min_tx_rate)
9320                 return -EINVAL;
9321
9322         actual_link_speed = igb_link_mbps(adapter->link_speed);
9323         if ((vf >= adapter->vfs_allocated_count) ||
9324             (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
9325             (max_tx_rate < 0) ||
9326             (max_tx_rate > actual_link_speed))
9327                 return -EINVAL;
9328
9329         adapter->vf_rate_link_speed = actual_link_speed;
9330         adapter->vf_data[vf].tx_rate = (u16)max_tx_rate;
9331         igb_set_vf_rate_limit(hw, vf, max_tx_rate, actual_link_speed);
9332
9333         return 0;
9334 }
9335
9336 static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf,
9337                                    bool setting)
9338 {
9339         struct igb_adapter *adapter = netdev_priv(netdev);
9340         struct e1000_hw *hw = &adapter->hw;
9341         u32 reg_val, reg_offset;
9342
9343         if (!adapter->vfs_allocated_count)
9344                 return -EOPNOTSUPP;
9345
9346         if (vf >= adapter->vfs_allocated_count)
9347                 return -EINVAL;
9348
9349         reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC;
9350         reg_val = rd32(reg_offset);
9351         if (setting)
9352                 reg_val |= (BIT(vf) |
9353                             BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9354         else
9355                 reg_val &= ~(BIT(vf) |
9356                              BIT(vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT));
9357         wr32(reg_offset, reg_val);
9358
9359         adapter->vf_data[vf].spoofchk_enabled = setting;
9360         return 0;
9361 }
9362
9363 static int igb_ndo_set_vf_trust(struct net_device *netdev, int vf, bool setting)
9364 {
9365         struct igb_adapter *adapter = netdev_priv(netdev);
9366
9367         if (vf >= adapter->vfs_allocated_count)
9368                 return -EINVAL;
9369         if (adapter->vf_data[vf].trusted == setting)
9370                 return 0;
9371
9372         adapter->vf_data[vf].trusted = setting;
9373
9374         dev_info(&adapter->pdev->dev, "VF %u is %strusted\n",
9375                  vf, setting ? "" : "not ");
9376         return 0;
9377 }
9378
9379 static int igb_ndo_get_vf_config(struct net_device *netdev,
9380                                  int vf, struct ifla_vf_info *ivi)
9381 {
9382         struct igb_adapter *adapter = netdev_priv(netdev);
9383         if (vf >= adapter->vfs_allocated_count)
9384                 return -EINVAL;
9385         ivi->vf = vf;
9386         memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
9387         ivi->max_tx_rate = adapter->vf_data[vf].tx_rate;
9388         ivi->min_tx_rate = 0;
9389         ivi->vlan = adapter->vf_data[vf].pf_vlan;
9390         ivi->qos = adapter->vf_data[vf].pf_qos;
9391         ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled;
9392         ivi->trusted = adapter->vf_data[vf].trusted;
9393         return 0;
9394 }
9395
9396 static void igb_vmm_control(struct igb_adapter *adapter)
9397 {
9398         struct e1000_hw *hw = &adapter->hw;
9399         u32 reg;
9400
9401         switch (hw->mac.type) {
9402         case e1000_82575:
9403         case e1000_i210:
9404         case e1000_i211:
9405         case e1000_i354:
9406         default:
9407                 /* replication is not supported for 82575 */
9408                 return;
9409         case e1000_82576:
9410                 /* notify HW that the MAC is adding vlan tags */
9411                 reg = rd32(E1000_DTXCTL);
9412                 reg |= E1000_DTXCTL_VLAN_ADDED;
9413                 wr32(E1000_DTXCTL, reg);
9414                 /* Fall through */
9415         case e1000_82580:
9416                 /* enable replication vlan tag stripping */
9417                 reg = rd32(E1000_RPLOLR);
9418                 reg |= E1000_RPLOLR_STRVLAN;
9419                 wr32(E1000_RPLOLR, reg);
9420                 /* Fall through */
9421         case e1000_i350:
9422                 /* none of the above registers are supported by i350 */
9423                 break;
9424         }
9425
9426         if (adapter->vfs_allocated_count) {
9427                 igb_vmdq_set_loopback_pf(hw, true);
9428                 igb_vmdq_set_replication_pf(hw, true);
9429                 igb_vmdq_set_anti_spoofing_pf(hw, true,
9430                                               adapter->vfs_allocated_count);
9431         } else {
9432                 igb_vmdq_set_loopback_pf(hw, false);
9433                 igb_vmdq_set_replication_pf(hw, false);
9434         }
9435 }
9436
9437 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
9438 {
9439         struct e1000_hw *hw = &adapter->hw;
9440         u32 dmac_thr;
9441         u16 hwm;
9442
9443         if (hw->mac.type > e1000_82580) {
9444                 if (adapter->flags & IGB_FLAG_DMAC) {
9445                         u32 reg;
9446
9447                         /* force threshold to 0. */
9448                         wr32(E1000_DMCTXTH, 0);
9449
9450                         /* DMA Coalescing high water mark needs to be greater
9451                          * than the Rx threshold. Set hwm to PBA - max frame
9452                          * size in 16B units, capping it at PBA - 6KB.
9453                          */
9454                         hwm = 64 * (pba - 6);
9455                         reg = rd32(E1000_FCRTC);
9456                         reg &= ~E1000_FCRTC_RTH_COAL_MASK;
9457                         reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
9458                                 & E1000_FCRTC_RTH_COAL_MASK);
9459                         wr32(E1000_FCRTC, reg);
9460
9461                         /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
9462                          * frame size, capping it at PBA - 10KB.
9463                          */
9464                         dmac_thr = pba - 10;
9465                         reg = rd32(E1000_DMACR);
9466                         reg &= ~E1000_DMACR_DMACTHR_MASK;
9467                         reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
9468                                 & E1000_DMACR_DMACTHR_MASK);
9469
9470                         /* transition to L0x or L1 if available..*/
9471                         reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
9472
9473                         /* watchdog timer= +-1000 usec in 32usec intervals */
9474                         reg |= (1000 >> 5);
9475
9476                         /* Disable BMC-to-OS Watchdog Enable */
9477                         if (hw->mac.type != e1000_i354)
9478                                 reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
9479
9480                         wr32(E1000_DMACR, reg);
9481
9482                         /* no lower threshold to disable
9483                          * coalescing(smart fifb)-UTRESH=0
9484                          */
9485                         wr32(E1000_DMCRTRH, 0);
9486
9487                         reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
9488
9489                         wr32(E1000_DMCTLX, reg);
9490
9491                         /* free space in tx packet buffer to wake from
9492                          * DMA coal
9493                          */
9494                         wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
9495                              (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
9496
9497                         /* make low power state decision controlled
9498                          * by DMA coal
9499                          */
9500                         reg = rd32(E1000_PCIEMISC);
9501                         reg &= ~E1000_PCIEMISC_LX_DECISION;
9502                         wr32(E1000_PCIEMISC, reg);
9503                 } /* endif adapter->dmac is not disabled */
9504         } else if (hw->mac.type == e1000_82580) {
9505                 u32 reg = rd32(E1000_PCIEMISC);
9506
9507                 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
9508                 wr32(E1000_DMACR, 0);
9509         }
9510 }
9511
9512 /**
9513  *  igb_read_i2c_byte - Reads 8 bit word over I2C
9514  *  @hw: pointer to hardware structure
9515  *  @byte_offset: byte offset to read
9516  *  @dev_addr: device address
9517  *  @data: value read
9518  *
9519  *  Performs byte read operation over I2C interface at
9520  *  a specified device address.
9521  **/
9522 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
9523                       u8 dev_addr, u8 *data)
9524 {
9525         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
9526         struct i2c_client *this_client = adapter->i2c_client;
9527         s32 status;
9528         u16 swfw_mask = 0;
9529
9530         if (!this_client)
9531                 return E1000_ERR_I2C;
9532
9533         swfw_mask = E1000_SWFW_PHY0_SM;
9534
9535         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
9536                 return E1000_ERR_SWFW_SYNC;
9537
9538         status = i2c_smbus_read_byte_data(this_client, byte_offset);
9539         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
9540
9541         if (status < 0)
9542                 return E1000_ERR_I2C;
9543         else {
9544                 *data = status;
9545                 return 0;
9546         }
9547 }
9548
9549 /**
9550  *  igb_write_i2c_byte - Writes 8 bit word over I2C
9551  *  @hw: pointer to hardware structure
9552  *  @byte_offset: byte offset to write
9553  *  @dev_addr: device address
9554  *  @data: value to write
9555  *
9556  *  Performs byte write operation over I2C interface at
9557  *  a specified device address.
9558  **/
9559 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
9560                        u8 dev_addr, u8 data)
9561 {
9562         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
9563         struct i2c_client *this_client = adapter->i2c_client;
9564         s32 status;
9565         u16 swfw_mask = E1000_SWFW_PHY0_SM;
9566
9567         if (!this_client)
9568                 return E1000_ERR_I2C;
9569
9570         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
9571                 return E1000_ERR_SWFW_SYNC;
9572         status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
9573         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
9574
9575         if (status)
9576                 return E1000_ERR_I2C;
9577         else
9578                 return 0;
9579
9580 }
9581
9582 int igb_reinit_queues(struct igb_adapter *adapter)
9583 {
9584         struct net_device *netdev = adapter->netdev;
9585         struct pci_dev *pdev = adapter->pdev;
9586         int err = 0;
9587
9588         if (netif_running(netdev))
9589                 igb_close(netdev);
9590
9591         igb_reset_interrupt_capability(adapter);
9592
9593         if (igb_init_interrupt_scheme(adapter, true)) {
9594                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
9595                 return -ENOMEM;
9596         }
9597
9598         if (netif_running(netdev))
9599                 err = igb_open(netdev);
9600
9601         return err;
9602 }
9603
9604 static void igb_nfc_filter_exit(struct igb_adapter *adapter)
9605 {
9606         struct igb_nfc_filter *rule;
9607
9608         spin_lock(&adapter->nfc_lock);
9609
9610         hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
9611                 igb_erase_filter(adapter, rule);
9612
9613         hlist_for_each_entry(rule, &adapter->cls_flower_list, nfc_node)
9614                 igb_erase_filter(adapter, rule);
9615
9616         spin_unlock(&adapter->nfc_lock);
9617 }
9618
9619 static void igb_nfc_filter_restore(struct igb_adapter *adapter)
9620 {
9621         struct igb_nfc_filter *rule;
9622
9623         spin_lock(&adapter->nfc_lock);
9624
9625         hlist_for_each_entry(rule, &adapter->nfc_filter_list, nfc_node)
9626                 igb_add_filter(adapter, rule);
9627
9628         spin_unlock(&adapter->nfc_lock);
9629 }
9630 /* igb_main.c */