1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018 Intel Corporation */
4 #ifndef _IGC_DEFINES_H_
5 #define _IGC_DEFINES_H_
7 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
8 #define REQ_TX_DESCRIPTOR_MULTIPLE 8
9 #define REQ_RX_DESCRIPTOR_MULTIPLE 8
11 #define IGC_CTRL_EXT_DRV_LOAD 0x10000000 /* Drv loaded bit for FW */
14 #define PCIE_DEVICE_CONTROL2 0x28
15 #define PCIE_DEVICE_CONTROL2_16ms 0x0005
17 /* Physical Func Reset Done Indication */
18 #define IGC_CTRL_EXT_LINK_MODE_MASK 0x00C00000
20 /* Loop limit on how long we wait for auto-negotiation to complete */
21 #define COPPER_LINK_UP_LIMIT 10
22 #define PHY_AUTO_NEG_LIMIT 45
23 #define PHY_FORCE_LIMIT 20
25 /* Number of 100 microseconds we wait for PCI Express master disable */
26 #define MASTER_DISABLE_TIMEOUT 800
27 /*Blocks new Master requests */
28 #define IGC_CTRL_GIO_MASTER_DISABLE 0x00000004
29 /* Status of Master requests. */
30 #define IGC_STATUS_GIO_MASTER_ENABLE 0x00080000
33 * Number of high/low register pairs in the RAR. The RAR (Receive Address
34 * Registers) holds the directed and multicast addresses that we monitor.
35 * Technically, we have 16 spots. However, we reserve one of these spots
36 * (RAR[15]) for our directed address used by controllers with
37 * manageability enabled, allowing us room for 15 multicast addresses.
39 #define IGC_RAH_AV 0x80000000 /* Receive descriptor valid */
40 #define IGC_RAH_POOL_1 0x00040000
41 #define IGC_RAL_MAC_ADDR_LEN 4
42 #define IGC_RAH_MAC_ADDR_LEN 2
48 #define IGC_ERR_CONFIG 3
49 #define IGC_ERR_PARAM 4
50 #define IGC_ERR_MAC_INIT 5
51 #define IGC_ERR_RESET 9
52 #define IGC_ERR_MASTER_REQUESTS_PENDING 10
53 #define IGC_ERR_BLK_PHY_RESET 12
54 #define IGC_ERR_SWFW_SYNC 13
57 #define IGC_CTRL_RST 0x04000000 /* Global reset */
59 #define IGC_CTRL_PHY_RST 0x80000000 /* PHY Reset */
60 #define IGC_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
61 #define IGC_CTRL_FRCSPD 0x00000800 /* Force Speed */
62 #define IGC_CTRL_FRCDPX 0x00001000 /* Force Duplex */
64 #define IGC_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
65 #define IGC_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
67 #define IGC_CONNSW_AUTOSENSE_EN 0x1
69 /* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */
70 #define MAX_JUMBO_FRAME_SIZE 0x2600
73 #define IGC_PBA_34K 0x0022
75 /* SW Semaphore Register */
76 #define IGC_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
77 #define IGC_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
79 /* SWFW_SYNC Definitions */
80 #define IGC_SWFW_EEP_SM 0x1
81 #define IGC_SWFW_PHY0_SM 0x2
83 /* Autoneg Advertisement Register */
84 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
85 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
86 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
87 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
88 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
89 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
91 /* Link Partner Ability Register (Base Page) */
92 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
93 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
95 /* 1000BASE-T Control Register */
96 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
97 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
98 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
100 /* 1000BASE-T Status Register */
101 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
102 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
104 /* PHY GPY 211 registers */
105 #define STANDARD_AN_REG_MASK 0x0007 /* MMD */
106 #define ANEG_MULTIGBT_AN_CTRL 0x0020 /* MULTI GBT AN Control Register */
107 #define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */
108 #define CR_2500T_FD_CAPS 0x0080 /* Advertise 2500T FD capability */
111 /* Number of milliseconds for NVM auto read done after MAC reset. */
112 #define AUTO_READ_DONE_TIMEOUT 10
113 #define IGC_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
114 #define IGC_EECD_REQ 0x00000040 /* NVM Access Request */
115 #define IGC_EECD_GNT 0x00000080 /* NVM Access Grant */
116 /* NVM Addressing bits based on type 0=small, 1=large */
117 #define IGC_EECD_ADDR_BITS 0x00000400
118 #define IGC_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
119 #define IGC_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
120 #define IGC_EECD_SIZE_EX_SHIFT 11
121 #define IGC_EECD_FLUPD_I225 0x00800000 /* Update FLASH */
122 #define IGC_EECD_FLUDONE_I225 0x04000000 /* Update FLASH done*/
123 #define IGC_EECD_FLASH_DETECTED_I225 0x00080000 /* FLASH detected */
124 #define IGC_FLUDONE_ATTEMPTS 20000
125 #define IGC_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */
127 /* Offset to data in NVM read/write registers */
128 #define IGC_NVM_RW_REG_DATA 16
129 #define IGC_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
130 #define IGC_NVM_RW_REG_START 1 /* Start operation */
131 #define IGC_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
132 #define IGC_NVM_POLL_READ 0 /* Flag for polling for read complete */
134 /* NVM Word Offsets */
135 #define NVM_CHECKSUM_REG 0x003F
137 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
138 #define NVM_SUM 0xBABA
140 #define NVM_PBA_OFFSET_0 8
141 #define NVM_PBA_OFFSET_1 9
142 #define NVM_RESERVED_WORD 0xFFFF
143 #define NVM_PBA_PTR_GUARD 0xFAFA
144 #define NVM_WORD_SIZE_BASE_SHIFT 6
146 /* Collision related configuration parameters */
147 #define IGC_COLLISION_THRESHOLD 15
148 #define IGC_CT_SHIFT 4
149 #define IGC_COLLISION_DISTANCE 63
150 #define IGC_COLD_SHIFT 12
153 #define IGC_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
154 #define IGC_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
155 #define IGC_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
156 #define IGC_STATUS_FUNC_SHIFT 2
157 #define IGC_STATUS_FUNC_1 0x00000004 /* Function 1 */
158 #define IGC_STATUS_TXOFF 0x00000010 /* transmission paused */
159 #define IGC_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
160 #define IGC_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
161 #define IGC_STATUS_SPEED_2500 0x00400000 /* Speed 2.5Gb/s */
164 #define SPEED_100 100
165 #define SPEED_1000 1000
166 #define SPEED_2500 2500
167 #define HALF_DUPLEX 1
168 #define FULL_DUPLEX 2
170 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
171 #define ADVERTISE_10_HALF 0x0001
172 #define ADVERTISE_10_FULL 0x0002
173 #define ADVERTISE_100_HALF 0x0004
174 #define ADVERTISE_100_FULL 0x0008
175 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */
176 #define ADVERTISE_1000_FULL 0x0020
177 #define ADVERTISE_2500_HALF 0x0040 /* Not used, just FYI */
178 #define ADVERTISE_2500_FULL 0x0080
180 #define IGC_ALL_SPEED_DUPLEX_2500 ( \
181 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
182 ADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL)
184 #define AUTONEG_ADVERTISE_SPEED_DEFAULT_2500 IGC_ALL_SPEED_DUPLEX_2500
186 /* Interrupt Cause Read */
187 #define IGC_ICR_TXDW BIT(0) /* Transmit desc written back */
188 #define IGC_ICR_TXQE BIT(1) /* Transmit Queue empty */
189 #define IGC_ICR_LSC BIT(2) /* Link Status Change */
190 #define IGC_ICR_RXSEQ BIT(3) /* Rx sequence error */
191 #define IGC_ICR_RXDMT0 BIT(4) /* Rx desc min. threshold (0) */
192 #define IGC_ICR_RXO BIT(6) /* Rx overrun */
193 #define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */
194 #define IGC_ICR_DRSTA BIT(30) /* Device Reset Asserted */
196 /* If this bit asserted, the driver should claim the interrupt */
197 #define IGC_ICR_INT_ASSERTED BIT(31)
199 #define IGC_ICS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
201 #define IMS_ENABLE_MASK ( \
208 /* Interrupt Mask Set */
209 #define IGC_IMS_TXDW IGC_ICR_TXDW /* Tx desc written back */
210 #define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */
211 #define IGC_IMS_LSC IGC_ICR_LSC /* Link Status Change */
212 #define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */
213 #define IGC_IMS_DRSTA IGC_ICR_DRSTA /* Device Reset Asserted */
214 #define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
215 #define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */
217 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
218 #define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */
220 /* Interrupt Cause Set */
221 #define IGC_ICS_LSC IGC_ICR_LSC /* Link Status Change */
222 #define IGC_ICS_RXDMT0 IGC_ICR_RXDMT0 /* rx desc min. threshold */
223 #define IGC_ICS_DRSTA IGC_ICR_DRSTA /* Device Reset Aserted */
225 #define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
226 #define IGC_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
227 #define IGC_IVAR_VALID 0x80
228 #define IGC_GPIE_NSICR 0x00000001
229 #define IGC_GPIE_MSIX_MODE 0x00000010
230 #define IGC_GPIE_EIAME 0x40000000
231 #define IGC_GPIE_PBA 0x80000000
233 /* Transmit Descriptor bit definitions */
234 #define IGC_TXD_DTYP_D 0x00100000 /* Data Descriptor */
235 #define IGC_TXD_DTYP_C 0x00000000 /* Context Descriptor */
236 #define IGC_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
237 #define IGC_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
238 #define IGC_TXD_CMD_EOP 0x01000000 /* End of Packet */
239 #define IGC_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
240 #define IGC_TXD_CMD_IC 0x04000000 /* Insert Checksum */
241 #define IGC_TXD_CMD_RS 0x08000000 /* Report Status */
242 #define IGC_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
243 #define IGC_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
244 #define IGC_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
245 #define IGC_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
246 #define IGC_TXD_STAT_DD 0x00000001 /* Descriptor Done */
247 #define IGC_TXD_STAT_EC 0x00000002 /* Excess Collisions */
248 #define IGC_TXD_STAT_LC 0x00000004 /* Late Collisions */
249 #define IGC_TXD_STAT_TU 0x00000008 /* Transmit underrun */
250 #define IGC_TXD_CMD_TCP 0x01000000 /* TCP packet */
251 #define IGC_TXD_CMD_IP 0x02000000 /* IP packet */
252 #define IGC_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
253 #define IGC_TXD_STAT_TC 0x00000004 /* Tx Underrun */
254 #define IGC_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */
256 /* Transmit Control */
257 #define IGC_TCTL_EN 0x00000002 /* enable Tx */
258 #define IGC_TCTL_PSP 0x00000008 /* pad short packets */
259 #define IGC_TCTL_CT 0x00000ff0 /* collision threshold */
260 #define IGC_TCTL_COLD 0x003ff000 /* collision distance */
261 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
262 #define IGC_TCTL_MULR 0x10000000 /* Multiple request support */
264 /* Flow Control Constants */
265 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
266 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
267 #define FLOW_CONTROL_TYPE 0x8808
268 /* Enable XON frame transmission */
269 #define IGC_FCRTL_XONE 0x80000000
271 /* Management Control */
272 #define IGC_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
273 #define IGC_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
275 /* Receive Control */
276 #define IGC_RCTL_RST 0x00000001 /* Software reset */
277 #define IGC_RCTL_EN 0x00000002 /* enable */
278 #define IGC_RCTL_SBP 0x00000004 /* store bad packet */
279 #define IGC_RCTL_UPE 0x00000008 /* unicast promisc enable */
280 #define IGC_RCTL_MPE 0x00000010 /* multicast promisc enable */
281 #define IGC_RCTL_LPE 0x00000020 /* long packet enable */
282 #define IGC_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
283 #define IGC_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
285 #define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
286 #define IGC_RCTL_BAM 0x00008000 /* broadcast enable */
288 /* Receive Descriptor bit definitions */
289 #define IGC_RXD_STAT_EOP 0x02 /* End of Packet */
291 #define IGC_RXDEXT_STATERR_CE 0x01000000
292 #define IGC_RXDEXT_STATERR_SE 0x02000000
293 #define IGC_RXDEXT_STATERR_SEQ 0x04000000
294 #define IGC_RXDEXT_STATERR_CXE 0x10000000
295 #define IGC_RXDEXT_STATERR_TCPE 0x20000000
296 #define IGC_RXDEXT_STATERR_IPE 0x40000000
297 #define IGC_RXDEXT_STATERR_RXE 0x80000000
299 /* Same mask, but for extended and packet split descriptors */
300 #define IGC_RXDEXT_ERR_FRAME_ERR_MASK ( \
301 IGC_RXDEXT_STATERR_CE | \
302 IGC_RXDEXT_STATERR_SE | \
303 IGC_RXDEXT_STATERR_SEQ | \
304 IGC_RXDEXT_STATERR_CXE | \
305 IGC_RXDEXT_STATERR_RXE)
307 #define IGC_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
308 #define IGC_MRQC_RSS_FIELD_IPV4 0x00020000
309 #define IGC_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000
310 #define IGC_MRQC_RSS_FIELD_IPV6 0x00100000
311 #define IGC_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
313 /* Header split receive */
314 #define IGC_RFCTL_IPV6_EX_DIS 0x00010000
315 #define IGC_RFCTL_LEF 0x00040000
317 #define IGC_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
319 #define IGC_RCTL_MO_SHIFT 12 /* multicast offset shift */
320 #define IGC_RCTL_CFIEN 0x00080000 /* canonical form enable */
321 #define IGC_RCTL_DPF 0x00400000 /* discard pause frames */
322 #define IGC_RCTL_PMCF 0x00800000 /* pass MAC control frames */
323 #define IGC_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
325 #define I225_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */
326 #define I225_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
328 /* Receive Checksum Control */
329 #define IGC_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */
330 #define IGC_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
332 /* GPY211 - I225 defines */
333 #define GPY_MMD_MASK 0xFFFF0000
334 #define GPY_MMD_SHIFT 16
335 #define GPY_REG_MASK 0x0000FFFF
337 #define IGC_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */
339 /* MAC definitions */
340 #define IGC_FACTPS_MNGCG 0x20000000
341 #define IGC_FWSM_MODE_MASK 0xE
342 #define IGC_FWSM_MODE_SHIFT 1
344 /* Management Control */
345 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
346 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
349 #define PHY_REVISION_MASK 0xFFFFFFF0
350 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
351 #define IGC_GEN_POLL_TIMEOUT 1920
353 /* PHY Control Register */
354 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
355 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
356 #define MII_CR_POWER_DOWN 0x0800 /* Power down */
357 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
358 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
359 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
360 #define MII_CR_SPEED_1000 0x0040
361 #define MII_CR_SPEED_100 0x2000
362 #define MII_CR_SPEED_10 0x0000
364 /* PHY Status Register */
365 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
366 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
368 /* PHY 1000 MII Register/Bit Definitions */
369 /* PHY Registers defined by IEEE */
370 #define PHY_CONTROL 0x00 /* Control Register */
371 #define PHY_STATUS 0x01 /* Status Register */
372 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
373 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
374 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
375 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
376 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
377 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
379 /* Bit definitions for valid PHY IDs. I = Integrated E = External */
380 #define I225_I_PHY_ID 0x67C9DC00
383 #define IGC_MDIC_DATA_MASK 0x0000FFFF
384 #define IGC_MDIC_REG_MASK 0x001F0000
385 #define IGC_MDIC_REG_SHIFT 16
386 #define IGC_MDIC_PHY_MASK 0x03E00000
387 #define IGC_MDIC_PHY_SHIFT 21
388 #define IGC_MDIC_OP_WRITE 0x04000000
389 #define IGC_MDIC_OP_READ 0x08000000
390 #define IGC_MDIC_READY 0x10000000
391 #define IGC_MDIC_INT_EN 0x20000000
392 #define IGC_MDIC_ERROR 0x40000000
393 #define IGC_MDIC_DEST 0x80000000
395 #define IGC_N0_QUEUE -1
397 #define IGC_MAX_MAC_HDR_LEN 127
398 #define IGC_MAX_NETWORK_HDR_LEN 511
400 #define IGC_VLAPQF_QUEUE_SEL(_n, q_idx) ((q_idx) << ((_n) * 4))
401 #define IGC_VLAPQF_P_VALID(_n) (0x1 << (3 + (_n) * 4))
402 #define IGC_VLAPQF_QUEUE_MASK 0x03
404 #endif /* _IGC_DEFINES_H_ */
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