1 /*******************************************************************************
3 * Intel 10 Gigabit PCI Express Linux driver
4 * Copyright(c) 2017 Oracle and/or its affiliates. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * Linux NICS <linux.nics@intel.com>
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 ******************************************************************************/
30 #include <crypto/aead.h>
33 * ixgbe_ipsec_set_tx_sa - set the Tx SA registers
34 * @hw: hw specific details
35 * @idx: register index to write
36 * @key: key byte array
39 static void ixgbe_ipsec_set_tx_sa(struct ixgbe_hw *hw, u16 idx,
45 for (i = 0; i < 4; i++)
46 IXGBE_WRITE_REG(hw, IXGBE_IPSTXKEY(i), cpu_to_be32(key[3 - i]));
47 IXGBE_WRITE_REG(hw, IXGBE_IPSTXSALT, cpu_to_be32(salt));
48 IXGBE_WRITE_FLUSH(hw);
50 reg = IXGBE_READ_REG(hw, IXGBE_IPSTXIDX);
51 reg &= IXGBE_RXTXIDX_IPS_EN;
52 reg |= idx << IXGBE_RXTXIDX_IDX_SHIFT | IXGBE_RXTXIDX_WRITE;
53 IXGBE_WRITE_REG(hw, IXGBE_IPSTXIDX, reg);
54 IXGBE_WRITE_FLUSH(hw);
58 * ixgbe_ipsec_set_rx_item - set an Rx table item
59 * @hw: hw specific details
60 * @idx: register index to write
61 * @tbl: table selector
63 * Trigger the device to store into a particular Rx table the
64 * data that has already been loaded into the input register
66 static void ixgbe_ipsec_set_rx_item(struct ixgbe_hw *hw, u16 idx,
67 enum ixgbe_ipsec_tbl_sel tbl)
71 reg = IXGBE_READ_REG(hw, IXGBE_IPSRXIDX);
72 reg &= IXGBE_RXTXIDX_IPS_EN;
73 reg |= tbl << IXGBE_RXIDX_TBL_SHIFT |
74 idx << IXGBE_RXTXIDX_IDX_SHIFT |
76 IXGBE_WRITE_REG(hw, IXGBE_IPSRXIDX, reg);
77 IXGBE_WRITE_FLUSH(hw);
81 * ixgbe_ipsec_set_rx_sa - set up the register bits to save SA info
82 * @hw: hw specific details
83 * @idx: register index to write
84 * @spi: security parameter index
85 * @key: key byte array
87 * @mode: rx decrypt control bits
88 * @ip_idx: index into IP table for related IP address
90 static void ixgbe_ipsec_set_rx_sa(struct ixgbe_hw *hw, u16 idx, __be32 spi,
91 u32 key[], u32 salt, u32 mode, u32 ip_idx)
95 /* store the SPI (in bigendian) and IPidx */
96 IXGBE_WRITE_REG(hw, IXGBE_IPSRXSPI, cpu_to_le32(spi));
97 IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPIDX, ip_idx);
98 IXGBE_WRITE_FLUSH(hw);
100 ixgbe_ipsec_set_rx_item(hw, idx, ips_rx_spi_tbl);
102 /* store the key, salt, and mode */
103 for (i = 0; i < 4; i++)
104 IXGBE_WRITE_REG(hw, IXGBE_IPSRXKEY(i), cpu_to_be32(key[3 - i]));
105 IXGBE_WRITE_REG(hw, IXGBE_IPSRXSALT, cpu_to_be32(salt));
106 IXGBE_WRITE_REG(hw, IXGBE_IPSRXMOD, mode);
107 IXGBE_WRITE_FLUSH(hw);
109 ixgbe_ipsec_set_rx_item(hw, idx, ips_rx_key_tbl);
113 * ixgbe_ipsec_set_rx_ip - set up the register bits to save SA IP addr info
114 * @hw: hw specific details
115 * @idx: register index to write
116 * @addr: IP address byte array
118 static void ixgbe_ipsec_set_rx_ip(struct ixgbe_hw *hw, u16 idx, __be32 addr[])
122 /* store the ip address */
123 for (i = 0; i < 4; i++)
124 IXGBE_WRITE_REG(hw, IXGBE_IPSRXIPADDR(i), cpu_to_le32(addr[i]));
125 IXGBE_WRITE_FLUSH(hw);
127 ixgbe_ipsec_set_rx_item(hw, idx, ips_rx_ip_tbl);
131 * ixgbe_ipsec_clear_hw_tables - because some tables don't get cleared on reset
132 * @adapter: board private structure
134 static void ixgbe_ipsec_clear_hw_tables(struct ixgbe_adapter *adapter)
136 struct ixgbe_ipsec *ipsec = adapter->ipsec;
137 struct ixgbe_hw *hw = &adapter->hw;
138 u32 buf[4] = {0, 0, 0, 0};
141 /* disable Rx and Tx SA lookup */
142 IXGBE_WRITE_REG(hw, IXGBE_IPSRXIDX, 0);
143 IXGBE_WRITE_REG(hw, IXGBE_IPSTXIDX, 0);
145 /* scrub the tables - split the loops for the max of the IP table */
146 for (idx = 0; idx < IXGBE_IPSEC_MAX_RX_IP_COUNT; idx++) {
147 ixgbe_ipsec_set_tx_sa(hw, idx, buf, 0);
148 ixgbe_ipsec_set_rx_sa(hw, idx, 0, buf, 0, 0, 0);
149 ixgbe_ipsec_set_rx_ip(hw, idx, (__be32 *)buf);
151 for (; idx < IXGBE_IPSEC_MAX_SA_COUNT; idx++) {
152 ixgbe_ipsec_set_tx_sa(hw, idx, buf, 0);
153 ixgbe_ipsec_set_rx_sa(hw, idx, 0, buf, 0, 0, 0);
156 ipsec->num_rx_sa = 0;
157 ipsec->num_tx_sa = 0;
161 * ixgbe_ipsec_stop_data
162 * @adapter: board private structure
164 static void ixgbe_ipsec_stop_data(struct ixgbe_adapter *adapter)
166 struct ixgbe_hw *hw = &adapter->hw;
167 bool link = adapter->link_up;
172 /* halt data paths */
173 reg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
174 reg |= IXGBE_SECTXCTRL_TX_DIS;
175 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, reg);
177 reg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
178 reg |= IXGBE_SECRXCTRL_RX_DIS;
179 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, reg);
181 IXGBE_WRITE_FLUSH(hw);
183 /* If the tx fifo doesn't have link, but still has data,
184 * we can't clear the tx sec block. Set the MAC loopback
188 reg = IXGBE_READ_REG(hw, IXGBE_MACC);
189 reg |= IXGBE_MACC_FLU;
190 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg);
192 reg = IXGBE_READ_REG(hw, IXGBE_HLREG0);
193 reg |= IXGBE_HLREG0_LPBK;
194 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg);
196 IXGBE_WRITE_FLUSH(hw);
200 /* wait for the paths to empty */
204 t_rdy = IXGBE_READ_REG(hw, IXGBE_SECTXSTAT) &
205 IXGBE_SECTXSTAT_SECTX_RDY;
206 r_rdy = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT) &
207 IXGBE_SECRXSTAT_SECRX_RDY;
208 } while (!t_rdy && !r_rdy && limit--);
210 /* undo loopback if we played with it earlier */
212 reg = IXGBE_READ_REG(hw, IXGBE_MACC);
213 reg &= ~IXGBE_MACC_FLU;
214 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg);
216 reg = IXGBE_READ_REG(hw, IXGBE_HLREG0);
217 reg &= ~IXGBE_HLREG0_LPBK;
218 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg);
220 IXGBE_WRITE_FLUSH(hw);
225 * ixgbe_ipsec_stop_engine
226 * @adapter: board private structure
228 static void ixgbe_ipsec_stop_engine(struct ixgbe_adapter *adapter)
230 struct ixgbe_hw *hw = &adapter->hw;
233 ixgbe_ipsec_stop_data(adapter);
235 /* disable Rx and Tx SA lookup */
236 IXGBE_WRITE_REG(hw, IXGBE_IPSTXIDX, 0);
237 IXGBE_WRITE_REG(hw, IXGBE_IPSRXIDX, 0);
239 /* disable the Rx and Tx engines and full packet store-n-forward */
240 reg = IXGBE_READ_REG(hw, IXGBE_SECTXCTRL);
241 reg |= IXGBE_SECTXCTRL_SECTX_DIS;
242 reg &= ~IXGBE_SECTXCTRL_STORE_FORWARD;
243 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, reg);
245 reg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
246 reg |= IXGBE_SECRXCTRL_SECRX_DIS;
247 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, reg);
249 /* restore the "tx security buffer almost full threshold" to 0x250 */
250 IXGBE_WRITE_REG(hw, IXGBE_SECTXBUFFAF, 0x250);
252 /* Set minimum IFG between packets back to the default 0x1 */
253 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
254 reg = (reg & 0xfffffff0) | 0x1;
255 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
257 /* final set for normal (no ipsec offload) processing */
258 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, IXGBE_SECTXCTRL_SECTX_DIS);
259 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, IXGBE_SECRXCTRL_SECRX_DIS);
261 IXGBE_WRITE_FLUSH(hw);
265 * ixgbe_ipsec_start_engine
266 * @adapter: board private structure
268 * NOTE: this increases power consumption whether being used or not
270 static void ixgbe_ipsec_start_engine(struct ixgbe_adapter *adapter)
272 struct ixgbe_hw *hw = &adapter->hw;
275 ixgbe_ipsec_stop_data(adapter);
277 /* Set minimum IFG between packets to 3 */
278 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
279 reg = (reg & 0xfffffff0) | 0x3;
280 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
282 /* Set "tx security buffer almost full threshold" to 0x15 so that the
283 * almost full indication is generated only after buffer contains at
284 * least an entire jumbo packet.
286 reg = IXGBE_READ_REG(hw, IXGBE_SECTXBUFFAF);
287 reg = (reg & 0xfffffc00) | 0x15;
288 IXGBE_WRITE_REG(hw, IXGBE_SECTXBUFFAF, reg);
290 /* restart the data paths by clearing the DISABLE bits */
291 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, 0);
292 IXGBE_WRITE_REG(hw, IXGBE_SECTXCTRL, IXGBE_SECTXCTRL_STORE_FORWARD);
294 /* enable Rx and Tx SA lookup */
295 IXGBE_WRITE_REG(hw, IXGBE_IPSTXIDX, IXGBE_RXTXIDX_IPS_EN);
296 IXGBE_WRITE_REG(hw, IXGBE_IPSRXIDX, IXGBE_RXTXIDX_IPS_EN);
298 IXGBE_WRITE_FLUSH(hw);
302 * ixgbe_ipsec_find_empty_idx - find the first unused security parameter index
303 * @ipsec: pointer to ipsec struct
304 * @rxtable: true if we need to look in the Rx table
306 * Returns the first unused index in either the Rx or Tx SA table
308 static int ixgbe_ipsec_find_empty_idx(struct ixgbe_ipsec *ipsec, bool rxtable)
313 if (ipsec->num_rx_sa == IXGBE_IPSEC_MAX_SA_COUNT)
316 /* search rx sa table */
317 for (i = 0; i < IXGBE_IPSEC_MAX_SA_COUNT; i++) {
318 if (!ipsec->rx_tbl[i].used)
322 if (ipsec->num_tx_sa == IXGBE_IPSEC_MAX_SA_COUNT)
325 /* search tx sa table */
326 for (i = 0; i < IXGBE_IPSEC_MAX_SA_COUNT; i++) {
327 if (!ipsec->tx_tbl[i].used)
336 * ixgbe_ipsec_parse_proto_keys - find the key and salt based on the protocol
337 * @xs: pointer to xfrm_state struct
338 * @mykey: pointer to key array to populate
339 * @mysalt: pointer to salt value to populate
341 * This copies the protocol keys and salt to our own data tables. The
342 * 82599 family only supports the one algorithm.
344 static int ixgbe_ipsec_parse_proto_keys(struct xfrm_state *xs,
345 u32 *mykey, u32 *mysalt)
347 struct net_device *dev = xs->xso.dev;
348 unsigned char *key_data;
349 char *alg_name = NULL;
350 const char aes_gcm_name[] = "rfc4106(gcm(aes))";
354 key_data = &xs->aead->alg_key[0];
355 key_len = xs->aead->alg_key_len;
356 alg_name = xs->aead->alg_name;
358 netdev_err(dev, "Unsupported IPsec algorithm\n");
362 if (strcmp(alg_name, aes_gcm_name)) {
363 netdev_err(dev, "Unsupported IPsec algorithm - please use %s\n",
368 /* The key bytes come down in a bigendian array of bytes, so
369 * we don't need to do any byteswapping.
370 * 160 accounts for 16 byte key and 4 byte salt
372 if (key_len == 160) {
373 *mysalt = ((u32 *)key_data)[4];
374 } else if (key_len != 128) {
375 netdev_err(dev, "IPsec hw offload only supports keys up to 128 bits with a 32 bit salt\n");
378 netdev_info(dev, "IPsec hw offload parameters missing 32 bit salt value\n");
381 memcpy(mykey, key_data, 16);
387 * ixgbe_ipsec_add_sa - program device with a security association
388 * @xs: pointer to transformer state struct
390 static int ixgbe_ipsec_add_sa(struct xfrm_state *xs)
392 struct net_device *dev = xs->xso.dev;
393 struct ixgbe_adapter *adapter = netdev_priv(dev);
394 struct ixgbe_ipsec *ipsec = adapter->ipsec;
395 struct ixgbe_hw *hw = &adapter->hw;
396 int checked, match, first;
401 if (xs->id.proto != IPPROTO_ESP && xs->id.proto != IPPROTO_AH) {
402 netdev_err(dev, "Unsupported protocol 0x%04x for ipsec offload\n",
407 if (xs->xso.flags & XFRM_OFFLOAD_INBOUND) {
411 netdev_err(dev, "Compression offload not supported\n");
415 /* find the first unused index */
416 ret = ixgbe_ipsec_find_empty_idx(ipsec, true);
418 netdev_err(dev, "No space for SA in Rx table!\n");
423 memset(&rsa, 0, sizeof(rsa));
427 if (rsa.xs->id.proto & IPPROTO_ESP)
428 rsa.decrypt = xs->ealg || xs->aead;
430 /* get the key and salt */
431 ret = ixgbe_ipsec_parse_proto_keys(xs, rsa.key, &rsa.salt);
433 netdev_err(dev, "Failed to get key data for Rx SA table\n");
437 /* get ip for rx sa table */
438 if (xs->xso.flags & XFRM_OFFLOAD_IPV6)
439 memcpy(rsa.ipaddr, &xs->id.daddr.a6, 16);
441 memcpy(&rsa.ipaddr[3], &xs->id.daddr.a4, 4);
443 /* The HW does not have a 1:1 mapping from keys to IP addrs, so
444 * check for a matching IP addr entry in the table. If the addr
445 * already exists, use it; else find an unused slot and add the
446 * addr. If one does not exist and there are no unused table
447 * entries, fail the request.
450 /* Find an existing match or first not used, and stop looking
451 * after we've checked all we know we have.
457 i < IXGBE_IPSEC_MAX_RX_IP_COUNT &&
458 (checked < ipsec->num_rx_sa || first < 0);
460 if (ipsec->ip_tbl[i].used) {
461 if (!memcmp(ipsec->ip_tbl[i].ipaddr,
462 rsa.ipaddr, sizeof(rsa.ipaddr))) {
467 } else if (first < 0) {
468 first = i; /* track the first empty seen */
472 if (ipsec->num_rx_sa == 0)
476 /* addrs are the same, we should use this one */
477 rsa.iptbl_ind = match;
478 ipsec->ip_tbl[match].ref_cnt++;
480 } else if (first >= 0) {
481 /* no matches, but here's an empty slot */
482 rsa.iptbl_ind = first;
484 memcpy(ipsec->ip_tbl[first].ipaddr,
485 rsa.ipaddr, sizeof(rsa.ipaddr));
486 ipsec->ip_tbl[first].ref_cnt = 1;
487 ipsec->ip_tbl[first].used = true;
489 ixgbe_ipsec_set_rx_ip(hw, rsa.iptbl_ind, rsa.ipaddr);
492 /* no match and no empty slot */
493 netdev_err(dev, "No space for SA in Rx IP SA table\n");
494 memset(&rsa, 0, sizeof(rsa));
498 rsa.mode = IXGBE_RXMOD_VALID;
499 if (rsa.xs->id.proto & IPPROTO_ESP)
500 rsa.mode |= IXGBE_RXMOD_PROTO_ESP;
502 rsa.mode |= IXGBE_RXMOD_DECRYPT;
503 if (rsa.xs->xso.flags & XFRM_OFFLOAD_IPV6)
504 rsa.mode |= IXGBE_RXMOD_IPV6;
506 /* the preparations worked, so save the info */
507 memcpy(&ipsec->rx_tbl[sa_idx], &rsa, sizeof(rsa));
509 ixgbe_ipsec_set_rx_sa(hw, sa_idx, rsa.xs->id.spi, rsa.key,
510 rsa.salt, rsa.mode, rsa.iptbl_ind);
511 xs->xso.offload_handle = sa_idx + IXGBE_IPSEC_BASE_RX_INDEX;
515 /* hash the new entry for faster search in Rx path */
516 hash_add_rcu(ipsec->rx_sa_list, &ipsec->rx_tbl[sa_idx].hlist,
521 /* find the first unused index */
522 ret = ixgbe_ipsec_find_empty_idx(ipsec, false);
524 netdev_err(dev, "No space for SA in Tx table\n");
529 memset(&tsa, 0, sizeof(tsa));
533 if (xs->id.proto & IPPROTO_ESP)
534 tsa.encrypt = xs->ealg || xs->aead;
536 ret = ixgbe_ipsec_parse_proto_keys(xs, tsa.key, &tsa.salt);
538 netdev_err(dev, "Failed to get key data for Tx SA table\n");
539 memset(&tsa, 0, sizeof(tsa));
543 /* the preparations worked, so save the info */
544 memcpy(&ipsec->tx_tbl[sa_idx], &tsa, sizeof(tsa));
546 ixgbe_ipsec_set_tx_sa(hw, sa_idx, tsa.key, tsa.salt);
548 xs->xso.offload_handle = sa_idx + IXGBE_IPSEC_BASE_TX_INDEX;
553 /* enable the engine if not already warmed up */
554 if (!(adapter->flags2 & IXGBE_FLAG2_IPSEC_ENABLED)) {
555 ixgbe_ipsec_start_engine(adapter);
556 adapter->flags2 |= IXGBE_FLAG2_IPSEC_ENABLED;
563 * ixgbe_ipsec_del_sa - clear out this specific SA
564 * @xs: pointer to transformer state struct
566 static void ixgbe_ipsec_del_sa(struct xfrm_state *xs)
568 struct net_device *dev = xs->xso.dev;
569 struct ixgbe_adapter *adapter = netdev_priv(dev);
570 struct ixgbe_ipsec *ipsec = adapter->ipsec;
571 struct ixgbe_hw *hw = &adapter->hw;
572 u32 zerobuf[4] = {0, 0, 0, 0};
575 if (xs->xso.flags & XFRM_OFFLOAD_INBOUND) {
579 sa_idx = xs->xso.offload_handle - IXGBE_IPSEC_BASE_RX_INDEX;
580 rsa = &ipsec->rx_tbl[sa_idx];
583 netdev_err(dev, "Invalid Rx SA selected sa_idx=%d offload_handle=%lu\n",
584 sa_idx, xs->xso.offload_handle);
588 ixgbe_ipsec_set_rx_sa(hw, sa_idx, 0, zerobuf, 0, 0, 0);
589 hash_del_rcu(&rsa->hlist);
591 /* if the IP table entry is referenced by only this SA,
592 * i.e. ref_cnt is only 1, clear the IP table entry as well
594 ipi = rsa->iptbl_ind;
595 if (ipsec->ip_tbl[ipi].ref_cnt > 0) {
596 ipsec->ip_tbl[ipi].ref_cnt--;
598 if (!ipsec->ip_tbl[ipi].ref_cnt) {
599 memset(&ipsec->ip_tbl[ipi], 0,
600 sizeof(struct rx_ip_sa));
601 ixgbe_ipsec_set_rx_ip(hw, ipi, zerobuf);
605 memset(rsa, 0, sizeof(struct rx_sa));
608 sa_idx = xs->xso.offload_handle - IXGBE_IPSEC_BASE_TX_INDEX;
610 if (!ipsec->tx_tbl[sa_idx].used) {
611 netdev_err(dev, "Invalid Tx SA selected sa_idx=%d offload_handle=%lu\n",
612 sa_idx, xs->xso.offload_handle);
616 ixgbe_ipsec_set_tx_sa(hw, sa_idx, zerobuf, 0);
617 memset(&ipsec->tx_tbl[sa_idx], 0, sizeof(struct tx_sa));
621 /* if there are no SAs left, stop the engine to save energy */
622 if (ipsec->num_rx_sa == 0 && ipsec->num_tx_sa == 0) {
623 adapter->flags2 &= ~IXGBE_FLAG2_IPSEC_ENABLED;
624 ixgbe_ipsec_stop_engine(adapter);
628 static const struct xfrmdev_ops ixgbe_xfrmdev_ops = {
629 .xdo_dev_state_add = ixgbe_ipsec_add_sa,
630 .xdo_dev_state_delete = ixgbe_ipsec_del_sa,
634 * ixgbe_init_ipsec_offload - initialize security registers for IPSec operation
635 * @adapter: board private structure
637 void ixgbe_init_ipsec_offload(struct ixgbe_adapter *adapter)
639 struct ixgbe_ipsec *ipsec;
642 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
645 ipsec = kzalloc(sizeof(*ipsec), GFP_KERNEL);
648 hash_init(ipsec->rx_sa_list);
650 size = sizeof(struct rx_sa) * IXGBE_IPSEC_MAX_SA_COUNT;
651 ipsec->rx_tbl = kzalloc(size, GFP_KERNEL);
655 size = sizeof(struct tx_sa) * IXGBE_IPSEC_MAX_SA_COUNT;
656 ipsec->tx_tbl = kzalloc(size, GFP_KERNEL);
660 size = sizeof(struct rx_ip_sa) * IXGBE_IPSEC_MAX_RX_IP_COUNT;
661 ipsec->ip_tbl = kzalloc(size, GFP_KERNEL);
665 ipsec->num_rx_sa = 0;
666 ipsec->num_tx_sa = 0;
668 adapter->ipsec = ipsec;
669 ixgbe_ipsec_stop_engine(adapter);
670 ixgbe_ipsec_clear_hw_tables(adapter);
675 kfree(ipsec->ip_tbl);
676 kfree(ipsec->rx_tbl);
677 kfree(ipsec->tx_tbl);
679 kfree(adapter->ipsec);
680 netdev_err(adapter->netdev, "Unable to allocate memory for SA tables");
684 * ixgbe_stop_ipsec_offload - tear down the ipsec offload
685 * @adapter: board private structure
687 void ixgbe_stop_ipsec_offload(struct ixgbe_adapter *adapter)
689 struct ixgbe_ipsec *ipsec = adapter->ipsec;
691 adapter->ipsec = NULL;
693 kfree(ipsec->ip_tbl);
694 kfree(ipsec->rx_tbl);
695 kfree(ipsec->tx_tbl);