2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * Copyright (C) 2013 Michael Stapelberg <michael@stapelberg.de>
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License
27 * as published by the Free Software Foundation; either version 2
28 * of the License, or (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, see <http://www.gnu.org/licenses/>.
39 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41 #include <linux/init.h>
42 #include <linux/dma-mapping.h>
46 #include <linux/tcp.h>
47 #include <linux/udp.h>
48 #include <linux/etherdevice.h>
49 #include <linux/delay.h>
50 #include <linux/ethtool.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/kernel.h>
54 #include <linux/spinlock.h>
55 #include <linux/workqueue.h>
56 #include <linux/phy.h>
57 #include <linux/mv643xx_eth.h>
59 #include <linux/interrupt.h>
60 #include <linux/types.h>
61 #include <linux/slab.h>
62 #include <linux/clk.h>
64 #include <linux/of_irq.h>
65 #include <linux/of_net.h>
66 #include <linux/of_mdio.h>
68 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
69 static char mv643xx_eth_driver_version[] = "1.4";
73 * Registers shared between all ports.
75 #define PHY_ADDR 0x0000
76 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
77 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
78 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
79 #define WINDOW_BAR_ENABLE 0x0290
80 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
83 * Main per-port registers. These live at offset 0x0400 for
84 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
86 #define PORT_CONFIG 0x0000
87 #define UNICAST_PROMISCUOUS_MODE 0x00000001
88 #define PORT_CONFIG_EXT 0x0004
89 #define MAC_ADDR_LOW 0x0014
90 #define MAC_ADDR_HIGH 0x0018
91 #define SDMA_CONFIG 0x001c
92 #define TX_BURST_SIZE_16_64BIT 0x01000000
93 #define TX_BURST_SIZE_4_64BIT 0x00800000
94 #define BLM_TX_NO_SWAP 0x00000020
95 #define BLM_RX_NO_SWAP 0x00000010
96 #define RX_BURST_SIZE_16_64BIT 0x00000008
97 #define RX_BURST_SIZE_4_64BIT 0x00000004
98 #define PORT_SERIAL_CONTROL 0x003c
99 #define SET_MII_SPEED_TO_100 0x01000000
100 #define SET_GMII_SPEED_TO_1000 0x00800000
101 #define SET_FULL_DUPLEX_MODE 0x00200000
102 #define MAX_RX_PACKET_9700BYTE 0x000a0000
103 #define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
104 #define DO_NOT_FORCE_LINK_FAIL 0x00000400
105 #define SERIAL_PORT_CONTROL_RESERVED 0x00000200
106 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
107 #define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
108 #define FORCE_LINK_PASS 0x00000002
109 #define SERIAL_PORT_ENABLE 0x00000001
110 #define PORT_STATUS 0x0044
111 #define TX_FIFO_EMPTY 0x00000400
112 #define TX_IN_PROGRESS 0x00000080
113 #define PORT_SPEED_MASK 0x00000030
114 #define PORT_SPEED_1000 0x00000010
115 #define PORT_SPEED_100 0x00000020
116 #define PORT_SPEED_10 0x00000000
117 #define FLOW_CONTROL_ENABLED 0x00000008
118 #define FULL_DUPLEX 0x00000004
119 #define LINK_UP 0x00000002
120 #define TXQ_COMMAND 0x0048
121 #define TXQ_FIX_PRIO_CONF 0x004c
122 #define PORT_SERIAL_CONTROL1 0x004c
123 #define CLK125_BYPASS_EN 0x00000010
124 #define TX_BW_RATE 0x0050
125 #define TX_BW_MTU 0x0058
126 #define TX_BW_BURST 0x005c
127 #define INT_CAUSE 0x0060
128 #define INT_TX_END 0x07f80000
129 #define INT_TX_END_0 0x00080000
130 #define INT_RX 0x000003fc
131 #define INT_RX_0 0x00000004
132 #define INT_EXT 0x00000002
133 #define INT_CAUSE_EXT 0x0064
134 #define INT_EXT_LINK_PHY 0x00110000
135 #define INT_EXT_TX 0x000000ff
136 #define INT_MASK 0x0068
137 #define INT_MASK_EXT 0x006c
138 #define TX_FIFO_URGENT_THRESHOLD 0x0074
139 #define RX_DISCARD_FRAME_CNT 0x0084
140 #define RX_OVERRUN_FRAME_CNT 0x0088
141 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
142 #define TX_BW_RATE_MOVED 0x00e0
143 #define TX_BW_MTU_MOVED 0x00e8
144 #define TX_BW_BURST_MOVED 0x00ec
145 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
146 #define RXQ_COMMAND 0x0280
147 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
148 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
149 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
150 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
153 * Misc per-port registers.
155 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
156 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
157 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
158 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
162 * SDMA configuration register default value.
164 #if defined(__BIG_ENDIAN)
165 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
166 (RX_BURST_SIZE_4_64BIT | \
167 TX_BURST_SIZE_4_64BIT)
168 #elif defined(__LITTLE_ENDIAN)
169 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
170 (RX_BURST_SIZE_4_64BIT | \
173 TX_BURST_SIZE_4_64BIT)
175 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
182 #define DEFAULT_RX_QUEUE_SIZE 128
183 #define DEFAULT_TX_QUEUE_SIZE 512
184 #define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
186 #define TSO_HEADER_SIZE 128
188 /* Max number of allowed TCP segments for software TSO */
189 #define MV643XX_MAX_TSO_SEGS 100
190 #define MV643XX_MAX_SKB_DESCS (MV643XX_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
192 #define IS_TSO_HEADER(txq, addr) \
193 ((addr >= txq->tso_hdrs_dma) && \
194 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
196 #define DESC_DMA_MAP_SINGLE 0
197 #define DESC_DMA_MAP_PAGE 1
202 #if defined(__BIG_ENDIAN)
204 u16 byte_cnt; /* Descriptor buffer byte count */
205 u16 buf_size; /* Buffer size */
206 u32 cmd_sts; /* Descriptor command status */
207 u32 next_desc_ptr; /* Next descriptor pointer */
208 u32 buf_ptr; /* Descriptor buffer pointer */
212 u16 byte_cnt; /* buffer byte count */
213 u16 l4i_chk; /* CPU provided TCP checksum */
214 u32 cmd_sts; /* Command/status field */
215 u32 next_desc_ptr; /* Pointer to next descriptor */
216 u32 buf_ptr; /* pointer to buffer for this descriptor*/
218 #elif defined(__LITTLE_ENDIAN)
220 u32 cmd_sts; /* Descriptor command status */
221 u16 buf_size; /* Buffer size */
222 u16 byte_cnt; /* Descriptor buffer byte count */
223 u32 buf_ptr; /* Descriptor buffer pointer */
224 u32 next_desc_ptr; /* Next descriptor pointer */
228 u32 cmd_sts; /* Command/status field */
229 u16 l4i_chk; /* CPU provided TCP checksum */
230 u16 byte_cnt; /* buffer byte count */
231 u32 buf_ptr; /* pointer to buffer for this descriptor*/
232 u32 next_desc_ptr; /* Pointer to next descriptor */
235 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
238 /* RX & TX descriptor command */
239 #define BUFFER_OWNED_BY_DMA 0x80000000
241 /* RX & TX descriptor status */
242 #define ERROR_SUMMARY 0x00000001
244 /* RX descriptor status */
245 #define LAYER_4_CHECKSUM_OK 0x40000000
246 #define RX_ENABLE_INTERRUPT 0x20000000
247 #define RX_FIRST_DESC 0x08000000
248 #define RX_LAST_DESC 0x04000000
249 #define RX_IP_HDR_OK 0x02000000
250 #define RX_PKT_IS_IPV4 0x01000000
251 #define RX_PKT_IS_ETHERNETV2 0x00800000
252 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
253 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
254 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
256 /* TX descriptor command */
257 #define TX_ENABLE_INTERRUPT 0x00800000
258 #define GEN_CRC 0x00400000
259 #define TX_FIRST_DESC 0x00200000
260 #define TX_LAST_DESC 0x00100000
261 #define ZERO_PADDING 0x00080000
262 #define GEN_IP_V4_CHECKSUM 0x00040000
263 #define GEN_TCP_UDP_CHECKSUM 0x00020000
264 #define UDP_FRAME 0x00010000
265 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
266 #define GEN_TCP_UDP_CHK_FULL 0x00000400
267 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
269 #define TX_IHL_SHIFT 11
272 /* global *******************************************************************/
273 struct mv643xx_eth_shared_private {
275 * Ethernet controller base address.
280 * Per-port MBUS window access register value.
285 * Hardware-specific parameters.
287 int extended_rx_coal_limit;
293 #define TX_BW_CONTROL_ABSENT 0
294 #define TX_BW_CONTROL_OLD_LAYOUT 1
295 #define TX_BW_CONTROL_NEW_LAYOUT 2
297 static int mv643xx_eth_open(struct net_device *dev);
298 static int mv643xx_eth_stop(struct net_device *dev);
301 /* per-port *****************************************************************/
302 struct mib_counters {
303 u64 good_octets_received;
304 u32 bad_octets_received;
305 u32 internal_mac_transmit_err;
306 u32 good_frames_received;
307 u32 bad_frames_received;
308 u32 broadcast_frames_received;
309 u32 multicast_frames_received;
310 u32 frames_64_octets;
311 u32 frames_65_to_127_octets;
312 u32 frames_128_to_255_octets;
313 u32 frames_256_to_511_octets;
314 u32 frames_512_to_1023_octets;
315 u32 frames_1024_to_max_octets;
316 u64 good_octets_sent;
317 u32 good_frames_sent;
318 u32 excessive_collision;
319 u32 multicast_frames_sent;
320 u32 broadcast_frames_sent;
321 u32 unrec_mac_control_received;
323 u32 good_fc_received;
325 u32 undersize_received;
326 u32 fragments_received;
327 u32 oversize_received;
329 u32 mac_receive_error;
333 /* Non MIB hardware counters */
347 struct rx_desc *rx_desc_area;
348 dma_addr_t rx_desc_dma;
349 int rx_desc_area_size;
350 struct sk_buff **rx_skb;
362 int tx_stop_threshold;
363 int tx_wake_threshold;
366 dma_addr_t tso_hdrs_dma;
368 struct tx_desc *tx_desc_area;
369 char *tx_desc_mapping; /* array to track the type of the dma mapping */
370 dma_addr_t tx_desc_dma;
371 int tx_desc_area_size;
373 struct sk_buff_head tx_skb;
375 unsigned long tx_packets;
376 unsigned long tx_bytes;
377 unsigned long tx_dropped;
380 struct mv643xx_eth_private {
381 struct mv643xx_eth_shared_private *shared;
385 struct net_device *dev;
387 struct timer_list mib_counters_timer;
388 spinlock_t mib_counters_lock;
389 struct mib_counters mib_counters;
391 struct work_struct tx_timeout_task;
393 struct napi_struct napi;
408 unsigned long rx_desc_sram_addr;
409 int rx_desc_sram_size;
411 struct timer_list rx_oom;
412 struct rx_queue rxq[8];
418 unsigned long tx_desc_sram_addr;
419 int tx_desc_sram_size;
421 struct tx_queue txq[8];
424 * Hardware-specific parameters.
431 /* port register accessors **************************************************/
432 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
434 return readl(mp->shared->base + offset);
437 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
439 return readl(mp->base + offset);
442 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
444 writel(data, mp->shared->base + offset);
447 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
449 writel(data, mp->base + offset);
453 /* rxq/txq helper functions *************************************************/
454 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
456 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
459 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
461 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
464 static void rxq_enable(struct rx_queue *rxq)
466 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
467 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
470 static void rxq_disable(struct rx_queue *rxq)
472 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
473 u8 mask = 1 << rxq->index;
475 wrlp(mp, RXQ_COMMAND, mask << 8);
476 while (rdlp(mp, RXQ_COMMAND) & mask)
480 static void txq_reset_hw_ptr(struct tx_queue *txq)
482 struct mv643xx_eth_private *mp = txq_to_mp(txq);
485 addr = (u32)txq->tx_desc_dma;
486 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
487 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
490 static void txq_enable(struct tx_queue *txq)
492 struct mv643xx_eth_private *mp = txq_to_mp(txq);
493 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
496 static void txq_disable(struct tx_queue *txq)
498 struct mv643xx_eth_private *mp = txq_to_mp(txq);
499 u8 mask = 1 << txq->index;
501 wrlp(mp, TXQ_COMMAND, mask << 8);
502 while (rdlp(mp, TXQ_COMMAND) & mask)
506 static void txq_maybe_wake(struct tx_queue *txq)
508 struct mv643xx_eth_private *mp = txq_to_mp(txq);
509 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
511 if (netif_tx_queue_stopped(nq)) {
512 __netif_tx_lock(nq, smp_processor_id());
513 if (txq->tx_desc_count <= txq->tx_wake_threshold)
514 netif_tx_wake_queue(nq);
515 __netif_tx_unlock(nq);
519 static int rxq_process(struct rx_queue *rxq, int budget)
521 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
522 struct net_device_stats *stats = &mp->dev->stats;
526 while (rx < budget && rxq->rx_desc_count) {
527 struct rx_desc *rx_desc;
528 unsigned int cmd_sts;
532 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
534 cmd_sts = rx_desc->cmd_sts;
535 if (cmd_sts & BUFFER_OWNED_BY_DMA)
539 skb = rxq->rx_skb[rxq->rx_curr_desc];
540 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
543 if (rxq->rx_curr_desc == rxq->rx_ring_size)
544 rxq->rx_curr_desc = 0;
546 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
547 rx_desc->buf_size, DMA_FROM_DEVICE);
548 rxq->rx_desc_count--;
551 mp->work_rx_refill |= 1 << rxq->index;
553 byte_cnt = rx_desc->byte_cnt;
558 * Note that the descriptor byte count includes 2 dummy
559 * bytes automatically inserted by the hardware at the
560 * start of the packet (which we don't count), and a 4
561 * byte CRC at the end of the packet (which we do count).
564 stats->rx_bytes += byte_cnt - 2;
567 * In case we received a packet without first / last bits
568 * on, or the error summary bit is set, the packet needs
571 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
572 != (RX_FIRST_DESC | RX_LAST_DESC))
576 * The -4 is for the CRC in the trailer of the
579 skb_put(skb, byte_cnt - 2 - 4);
581 if (cmd_sts & LAYER_4_CHECKSUM_OK)
582 skb->ip_summed = CHECKSUM_UNNECESSARY;
583 skb->protocol = eth_type_trans(skb, mp->dev);
585 napi_gro_receive(&mp->napi, skb);
592 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
593 (RX_FIRST_DESC | RX_LAST_DESC)) {
596 "received packet spanning multiple descriptors\n");
599 if (cmd_sts & ERROR_SUMMARY)
606 mp->work_rx &= ~(1 << rxq->index);
611 static int rxq_refill(struct rx_queue *rxq, int budget)
613 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
617 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
620 struct rx_desc *rx_desc;
623 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
631 skb_reserve(skb, SKB_DMA_REALIGN);
634 rxq->rx_desc_count++;
636 rx = rxq->rx_used_desc++;
637 if (rxq->rx_used_desc == rxq->rx_ring_size)
638 rxq->rx_used_desc = 0;
640 rx_desc = rxq->rx_desc_area + rx;
642 size = skb_end_pointer(skb) - skb->data;
643 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
646 rx_desc->buf_size = size;
647 rxq->rx_skb[rx] = skb;
649 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
653 * The hardware automatically prepends 2 bytes of
654 * dummy data to each received packet, so that the
655 * IP header ends up 16-byte aligned.
660 if (refilled < budget)
661 mp->work_rx_refill &= ~(1 << rxq->index);
668 /* tx ***********************************************************************/
669 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
673 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
674 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
676 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
683 static inline __be16 sum16_as_be(__sum16 sum)
685 return (__force __be16)sum;
688 static int skb_tx_csum(struct mv643xx_eth_private *mp, struct sk_buff *skb,
689 u16 *l4i_chk, u32 *command, int length)
694 if (skb->ip_summed == CHECKSUM_PARTIAL) {
698 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
699 skb->protocol != htons(ETH_P_8021Q));
701 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
702 tag_bytes = hdr_len - ETH_HLEN;
704 if (length - hdr_len > mp->shared->tx_csum_limit ||
705 unlikely(tag_bytes & ~12)) {
706 ret = skb_checksum_help(skb);
713 cmd |= MAC_HDR_EXTRA_4_BYTES;
715 cmd |= MAC_HDR_EXTRA_8_BYTES;
717 cmd |= GEN_TCP_UDP_CHECKSUM | GEN_TCP_UDP_CHK_FULL |
719 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
721 /* TODO: Revisit this. With the usage of GEN_TCP_UDP_CHK_FULL
722 * it seems we don't need to pass the initial checksum. */
723 switch (ip_hdr(skb)->protocol) {
732 WARN(1, "protocol not supported");
736 /* Errata BTS #50, IHL must be 5 if no HW checksum */
737 cmd |= 5 << TX_IHL_SHIFT;
744 txq_put_data_tso(struct net_device *dev, struct tx_queue *txq,
745 struct sk_buff *skb, char *data, int length,
746 bool last_tcp, bool is_last)
750 struct tx_desc *desc;
752 tx_index = txq->tx_curr_desc++;
753 if (txq->tx_curr_desc == txq->tx_ring_size)
754 txq->tx_curr_desc = 0;
755 desc = &txq->tx_desc_area[tx_index];
756 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
759 desc->byte_cnt = length;
761 if (length <= 8 && (uintptr_t)data & 0x7) {
762 /* Copy unaligned small data fragment to TSO header data area */
763 memcpy(txq->tso_hdrs + tx_index * TSO_HEADER_SIZE,
765 desc->buf_ptr = txq->tso_hdrs_dma
766 + tx_index * TSO_HEADER_SIZE;
768 /* Alignment is okay, map buffer and hand off to hardware */
769 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
770 desc->buf_ptr = dma_map_single(dev->dev.parent, data,
771 length, DMA_TO_DEVICE);
772 if (unlikely(dma_mapping_error(dev->dev.parent,
774 WARN(1, "dma_map_single failed!\n");
779 cmd_sts = BUFFER_OWNED_BY_DMA;
781 /* last descriptor in the TCP packet */
782 cmd_sts |= ZERO_PADDING | TX_LAST_DESC;
783 /* last descriptor in SKB */
785 cmd_sts |= TX_ENABLE_INTERRUPT;
787 desc->cmd_sts = cmd_sts;
792 txq_put_hdr_tso(struct sk_buff *skb, struct tx_queue *txq, int length,
793 u32 *first_cmd_sts, bool first_desc)
795 struct mv643xx_eth_private *mp = txq_to_mp(txq);
796 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
798 struct tx_desc *desc;
804 tx_index = txq->tx_curr_desc;
805 desc = &txq->tx_desc_area[tx_index];
807 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_csum, length);
809 WARN(1, "failed to prepare checksum!");
811 /* Should we set this? Can't use the value from skb_tx_csum()
812 * as it's not the correct initial L4 checksum to use. */
815 desc->byte_cnt = hdr_len;
816 desc->buf_ptr = txq->tso_hdrs_dma +
817 txq->tx_curr_desc * TSO_HEADER_SIZE;
818 cmd_sts = cmd_csum | BUFFER_OWNED_BY_DMA | TX_FIRST_DESC |
821 /* Defer updating the first command descriptor until all
822 * following descriptors have been written.
825 *first_cmd_sts = cmd_sts;
827 desc->cmd_sts = cmd_sts;
830 if (txq->tx_curr_desc == txq->tx_ring_size)
831 txq->tx_curr_desc = 0;
834 static int txq_submit_tso(struct tx_queue *txq, struct sk_buff *skb,
835 struct net_device *dev)
837 struct mv643xx_eth_private *mp = txq_to_mp(txq);
838 int total_len, data_left, ret;
841 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
842 struct tx_desc *first_tx_desc;
843 u32 first_cmd_sts = 0;
845 /* Count needed descriptors */
846 if ((txq->tx_desc_count + tso_count_descs(skb)) >= txq->tx_ring_size) {
847 netdev_dbg(dev, "not enough descriptors for TSO!\n");
851 first_tx_desc = &txq->tx_desc_area[txq->tx_curr_desc];
853 /* Initialize the TSO handler, and prepare the first payload */
854 tso_start(skb, &tso);
856 total_len = skb->len - hdr_len;
857 while (total_len > 0) {
858 bool first_desc = (desc_count == 0);
861 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
862 total_len -= data_left;
865 /* prepare packet headers: MAC + IP + TCP */
866 hdr = txq->tso_hdrs + txq->tx_curr_desc * TSO_HEADER_SIZE;
867 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
868 txq_put_hdr_tso(skb, txq, data_left, &first_cmd_sts,
871 while (data_left > 0) {
875 size = min_t(int, tso.size, data_left);
876 ret = txq_put_data_tso(dev, txq, skb, tso.data, size,
882 tso_build_data(skb, &tso, size);
886 __skb_queue_tail(&txq->tx_skb, skb);
887 skb_tx_timestamp(skb);
889 /* ensure all other descriptors are written before first cmd_sts */
891 first_tx_desc->cmd_sts = first_cmd_sts;
893 /* clear TX_END status */
894 mp->work_tx_end &= ~(1 << txq->index);
896 /* ensure all descriptors are written before poking hardware */
899 txq->tx_desc_count += desc_count;
902 /* TODO: Release all used data descriptors; header descriptors must not
908 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
910 struct mv643xx_eth_private *mp = txq_to_mp(txq);
911 int nr_frags = skb_shinfo(skb)->nr_frags;
914 for (frag = 0; frag < nr_frags; frag++) {
915 skb_frag_t *this_frag;
917 struct tx_desc *desc;
919 this_frag = &skb_shinfo(skb)->frags[frag];
920 tx_index = txq->tx_curr_desc++;
921 if (txq->tx_curr_desc == txq->tx_ring_size)
922 txq->tx_curr_desc = 0;
923 desc = &txq->tx_desc_area[tx_index];
924 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_PAGE;
927 * The last fragment will generate an interrupt
928 * which will free the skb on TX completion.
930 if (frag == nr_frags - 1) {
931 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
932 ZERO_PADDING | TX_LAST_DESC |
935 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
939 desc->byte_cnt = skb_frag_size(this_frag);
940 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
941 this_frag, 0, desc->byte_cnt,
946 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb,
947 struct net_device *dev)
949 struct mv643xx_eth_private *mp = txq_to_mp(txq);
950 int nr_frags = skb_shinfo(skb)->nr_frags;
952 struct tx_desc *desc;
960 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
962 netdev_err(dev, "tx queue full?!\n");
966 ret = skb_tx_csum(mp, skb, &l4i_chk, &cmd_sts, skb->len);
969 cmd_sts |= TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
971 tx_index = txq->tx_curr_desc++;
972 if (txq->tx_curr_desc == txq->tx_ring_size)
973 txq->tx_curr_desc = 0;
974 desc = &txq->tx_desc_area[tx_index];
975 txq->tx_desc_mapping[tx_index] = DESC_DMA_MAP_SINGLE;
978 txq_submit_frag_skb(txq, skb);
979 length = skb_headlen(skb);
981 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
985 desc->l4i_chk = l4i_chk;
986 desc->byte_cnt = length;
987 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
988 length, DMA_TO_DEVICE);
990 __skb_queue_tail(&txq->tx_skb, skb);
992 skb_tx_timestamp(skb);
994 /* ensure all other descriptors are written before first cmd_sts */
996 desc->cmd_sts = cmd_sts;
998 /* clear TX_END status */
999 mp->work_tx_end &= ~(1 << txq->index);
1001 /* ensure all descriptors are written before poking hardware */
1005 txq->tx_desc_count += nr_frags + 1;
1010 static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1012 struct mv643xx_eth_private *mp = netdev_priv(dev);
1013 int length, queue, ret;
1014 struct tx_queue *txq;
1015 struct netdev_queue *nq;
1017 queue = skb_get_queue_mapping(skb);
1018 txq = mp->txq + queue;
1019 nq = netdev_get_tx_queue(dev, queue);
1021 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
1022 netdev_printk(KERN_DEBUG, dev,
1023 "failed to linearize skb with tiny unaligned fragment\n");
1024 return NETDEV_TX_BUSY;
1029 if (skb_is_gso(skb))
1030 ret = txq_submit_tso(txq, skb, dev);
1032 ret = txq_submit_skb(txq, skb, dev);
1034 txq->tx_bytes += length;
1037 if (txq->tx_desc_count >= txq->tx_stop_threshold)
1038 netif_tx_stop_queue(nq);
1041 dev_kfree_skb_any(skb);
1044 return NETDEV_TX_OK;
1048 /* tx napi ******************************************************************/
1049 static void txq_kick(struct tx_queue *txq)
1051 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1052 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1056 __netif_tx_lock(nq, smp_processor_id());
1058 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1061 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1062 expected_ptr = (u32)txq->tx_desc_dma +
1063 txq->tx_curr_desc * sizeof(struct tx_desc);
1065 if (hw_desc_ptr != expected_ptr)
1069 __netif_tx_unlock(nq);
1071 mp->work_tx_end &= ~(1 << txq->index);
1074 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
1076 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1077 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1080 __netif_tx_lock_bh(nq);
1083 while (reclaimed < budget && txq->tx_desc_count > 0) {
1085 struct tx_desc *desc;
1089 tx_index = txq->tx_used_desc;
1090 desc = &txq->tx_desc_area[tx_index];
1091 desc_dma_map = txq->tx_desc_mapping[tx_index];
1093 cmd_sts = desc->cmd_sts;
1095 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1098 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1101 txq->tx_used_desc = tx_index + 1;
1102 if (txq->tx_used_desc == txq->tx_ring_size)
1103 txq->tx_used_desc = 0;
1106 txq->tx_desc_count--;
1108 if (!IS_TSO_HEADER(txq, desc->buf_ptr)) {
1110 if (desc_dma_map == DESC_DMA_MAP_PAGE)
1111 dma_unmap_page(mp->dev->dev.parent,
1116 dma_unmap_single(mp->dev->dev.parent,
1122 if (cmd_sts & TX_ENABLE_INTERRUPT) {
1123 struct sk_buff *skb = __skb_dequeue(&txq->tx_skb);
1129 if (cmd_sts & ERROR_SUMMARY) {
1130 netdev_info(mp->dev, "tx error\n");
1131 mp->dev->stats.tx_errors++;
1136 __netif_tx_unlock_bh(nq);
1138 if (reclaimed < budget)
1139 mp->work_tx &= ~(1 << txq->index);
1145 /* tx rate control **********************************************************/
1147 * Set total maximum TX rate (shared by all TX queues for this port)
1148 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1150 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1156 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1157 if (token_rate > 1023)
1160 mtu = (mp->dev->mtu + 255) >> 8;
1164 bucket_size = (burst + 255) >> 8;
1165 if (bucket_size > 65535)
1166 bucket_size = 65535;
1168 switch (mp->shared->tx_bw_control) {
1169 case TX_BW_CONTROL_OLD_LAYOUT:
1170 wrlp(mp, TX_BW_RATE, token_rate);
1171 wrlp(mp, TX_BW_MTU, mtu);
1172 wrlp(mp, TX_BW_BURST, bucket_size);
1174 case TX_BW_CONTROL_NEW_LAYOUT:
1175 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1176 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1177 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1182 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1184 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1188 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
1189 if (token_rate > 1023)
1192 bucket_size = (burst + 255) >> 8;
1193 if (bucket_size > 65535)
1194 bucket_size = 65535;
1196 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1197 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1200 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1202 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1207 * Turn on fixed priority mode.
1210 switch (mp->shared->tx_bw_control) {
1211 case TX_BW_CONTROL_OLD_LAYOUT:
1212 off = TXQ_FIX_PRIO_CONF;
1214 case TX_BW_CONTROL_NEW_LAYOUT:
1215 off = TXQ_FIX_PRIO_CONF_MOVED;
1220 val = rdlp(mp, off);
1221 val |= 1 << txq->index;
1227 /* mii management interface *************************************************/
1228 static void mv643xx_eth_adjust_link(struct net_device *dev)
1230 struct mv643xx_eth_private *mp = netdev_priv(dev);
1231 u32 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
1232 u32 autoneg_disable = FORCE_LINK_PASS |
1233 DISABLE_AUTO_NEG_SPEED_GMII |
1234 DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1235 DISABLE_AUTO_NEG_FOR_DUPLEX;
1237 if (dev->phydev->autoneg == AUTONEG_ENABLE) {
1238 /* enable auto negotiation */
1239 pscr &= ~autoneg_disable;
1243 pscr |= autoneg_disable;
1245 if (dev->phydev->speed == SPEED_1000) {
1246 /* force gigabit, half duplex not supported */
1247 pscr |= SET_GMII_SPEED_TO_1000;
1248 pscr |= SET_FULL_DUPLEX_MODE;
1252 pscr &= ~SET_GMII_SPEED_TO_1000;
1254 if (dev->phydev->speed == SPEED_100)
1255 pscr |= SET_MII_SPEED_TO_100;
1257 pscr &= ~SET_MII_SPEED_TO_100;
1259 if (dev->phydev->duplex == DUPLEX_FULL)
1260 pscr |= SET_FULL_DUPLEX_MODE;
1262 pscr &= ~SET_FULL_DUPLEX_MODE;
1265 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
1268 /* statistics ***************************************************************/
1269 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1271 struct mv643xx_eth_private *mp = netdev_priv(dev);
1272 struct net_device_stats *stats = &dev->stats;
1273 unsigned long tx_packets = 0;
1274 unsigned long tx_bytes = 0;
1275 unsigned long tx_dropped = 0;
1278 for (i = 0; i < mp->txq_count; i++) {
1279 struct tx_queue *txq = mp->txq + i;
1281 tx_packets += txq->tx_packets;
1282 tx_bytes += txq->tx_bytes;
1283 tx_dropped += txq->tx_dropped;
1286 stats->tx_packets = tx_packets;
1287 stats->tx_bytes = tx_bytes;
1288 stats->tx_dropped = tx_dropped;
1293 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1295 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1298 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1302 for (i = 0; i < 0x80; i += 4)
1305 /* Clear non MIB hw counters also */
1306 rdlp(mp, RX_DISCARD_FRAME_CNT);
1307 rdlp(mp, RX_OVERRUN_FRAME_CNT);
1310 static void mib_counters_update(struct mv643xx_eth_private *mp)
1312 struct mib_counters *p = &mp->mib_counters;
1314 spin_lock_bh(&mp->mib_counters_lock);
1315 p->good_octets_received += mib_read(mp, 0x00);
1316 p->bad_octets_received += mib_read(mp, 0x08);
1317 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1318 p->good_frames_received += mib_read(mp, 0x10);
1319 p->bad_frames_received += mib_read(mp, 0x14);
1320 p->broadcast_frames_received += mib_read(mp, 0x18);
1321 p->multicast_frames_received += mib_read(mp, 0x1c);
1322 p->frames_64_octets += mib_read(mp, 0x20);
1323 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1324 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1325 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1326 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1327 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1328 p->good_octets_sent += mib_read(mp, 0x38);
1329 p->good_frames_sent += mib_read(mp, 0x40);
1330 p->excessive_collision += mib_read(mp, 0x44);
1331 p->multicast_frames_sent += mib_read(mp, 0x48);
1332 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1333 p->unrec_mac_control_received += mib_read(mp, 0x50);
1334 p->fc_sent += mib_read(mp, 0x54);
1335 p->good_fc_received += mib_read(mp, 0x58);
1336 p->bad_fc_received += mib_read(mp, 0x5c);
1337 p->undersize_received += mib_read(mp, 0x60);
1338 p->fragments_received += mib_read(mp, 0x64);
1339 p->oversize_received += mib_read(mp, 0x68);
1340 p->jabber_received += mib_read(mp, 0x6c);
1341 p->mac_receive_error += mib_read(mp, 0x70);
1342 p->bad_crc_event += mib_read(mp, 0x74);
1343 p->collision += mib_read(mp, 0x78);
1344 p->late_collision += mib_read(mp, 0x7c);
1345 /* Non MIB hardware counters */
1346 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1347 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
1348 spin_unlock_bh(&mp->mib_counters_lock);
1351 static void mib_counters_timer_wrapper(unsigned long _mp)
1353 struct mv643xx_eth_private *mp = (void *)_mp;
1354 mib_counters_update(mp);
1355 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1359 /* interrupt coalescing *****************************************************/
1361 * Hardware coalescing parameters are set in units of 64 t_clk
1364 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1366 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1368 * In the ->set*() methods, we round the computed register value
1369 * to the nearest integer.
1371 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1373 u32 val = rdlp(mp, SDMA_CONFIG);
1376 if (mp->shared->extended_rx_coal_limit)
1377 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1379 temp = (val & 0x003fff00) >> 8;
1382 do_div(temp, mp->t_clk);
1384 return (unsigned int)temp;
1387 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1392 temp = (u64)usec * mp->t_clk;
1394 do_div(temp, 64000000);
1396 val = rdlp(mp, SDMA_CONFIG);
1397 if (mp->shared->extended_rx_coal_limit) {
1401 val |= (temp & 0x8000) << 10;
1402 val |= (temp & 0x7fff) << 7;
1407 val |= (temp & 0x3fff) << 8;
1409 wrlp(mp, SDMA_CONFIG, val);
1412 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1416 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1418 do_div(temp, mp->t_clk);
1420 return (unsigned int)temp;
1423 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1427 temp = (u64)usec * mp->t_clk;
1429 do_div(temp, 64000000);
1434 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1438 /* ethtool ******************************************************************/
1439 struct mv643xx_eth_stats {
1440 char stat_string[ETH_GSTRING_LEN];
1447 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1448 offsetof(struct net_device, stats.m), -1 }
1450 #define MIBSTAT(m) \
1451 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1452 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1454 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1463 MIBSTAT(good_octets_received),
1464 MIBSTAT(bad_octets_received),
1465 MIBSTAT(internal_mac_transmit_err),
1466 MIBSTAT(good_frames_received),
1467 MIBSTAT(bad_frames_received),
1468 MIBSTAT(broadcast_frames_received),
1469 MIBSTAT(multicast_frames_received),
1470 MIBSTAT(frames_64_octets),
1471 MIBSTAT(frames_65_to_127_octets),
1472 MIBSTAT(frames_128_to_255_octets),
1473 MIBSTAT(frames_256_to_511_octets),
1474 MIBSTAT(frames_512_to_1023_octets),
1475 MIBSTAT(frames_1024_to_max_octets),
1476 MIBSTAT(good_octets_sent),
1477 MIBSTAT(good_frames_sent),
1478 MIBSTAT(excessive_collision),
1479 MIBSTAT(multicast_frames_sent),
1480 MIBSTAT(broadcast_frames_sent),
1481 MIBSTAT(unrec_mac_control_received),
1483 MIBSTAT(good_fc_received),
1484 MIBSTAT(bad_fc_received),
1485 MIBSTAT(undersize_received),
1486 MIBSTAT(fragments_received),
1487 MIBSTAT(oversize_received),
1488 MIBSTAT(jabber_received),
1489 MIBSTAT(mac_receive_error),
1490 MIBSTAT(bad_crc_event),
1492 MIBSTAT(late_collision),
1493 MIBSTAT(rx_discard),
1494 MIBSTAT(rx_overrun),
1498 mv643xx_eth_get_link_ksettings_phy(struct mv643xx_eth_private *mp,
1499 struct ethtool_link_ksettings *cmd)
1501 struct net_device *dev = mp->dev;
1503 u32 supported, advertising;
1505 err = phy_read_status(dev->phydev);
1507 err = phy_ethtool_ksettings_get(dev->phydev, cmd);
1510 * The MAC does not support 1000baseT_Half.
1512 ethtool_convert_link_mode_to_legacy_u32(&supported,
1513 cmd->link_modes.supported);
1514 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1515 cmd->link_modes.advertising);
1516 supported &= ~SUPPORTED_1000baseT_Half;
1517 advertising &= ~ADVERTISED_1000baseT_Half;
1518 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1520 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1527 mv643xx_eth_get_link_ksettings_phyless(struct mv643xx_eth_private *mp,
1528 struct ethtool_link_ksettings *cmd)
1531 u32 supported, advertising;
1533 port_status = rdlp(mp, PORT_STATUS);
1535 supported = SUPPORTED_MII;
1536 advertising = ADVERTISED_MII;
1537 switch (port_status & PORT_SPEED_MASK) {
1539 cmd->base.speed = SPEED_10;
1541 case PORT_SPEED_100:
1542 cmd->base.speed = SPEED_100;
1544 case PORT_SPEED_1000:
1545 cmd->base.speed = SPEED_1000;
1548 cmd->base.speed = -1;
1551 cmd->base.duplex = (port_status & FULL_DUPLEX) ?
1552 DUPLEX_FULL : DUPLEX_HALF;
1553 cmd->base.port = PORT_MII;
1554 cmd->base.phy_address = 0;
1555 cmd->base.autoneg = AUTONEG_DISABLE;
1557 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1559 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1566 mv643xx_eth_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1571 phy_ethtool_get_wol(dev->phydev, wol);
1575 mv643xx_eth_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1582 err = phy_ethtool_set_wol(dev->phydev, wol);
1583 /* Given that mv643xx_eth works without the marvell-specific PHY driver,
1584 * this debugging hint is useful to have.
1586 if (err == -EOPNOTSUPP)
1587 netdev_info(dev, "The PHY does not support set_wol, was CONFIG_MARVELL_PHY enabled?\n");
1592 mv643xx_eth_get_link_ksettings(struct net_device *dev,
1593 struct ethtool_link_ksettings *cmd)
1595 struct mv643xx_eth_private *mp = netdev_priv(dev);
1598 return mv643xx_eth_get_link_ksettings_phy(mp, cmd);
1600 return mv643xx_eth_get_link_ksettings_phyless(mp, cmd);
1604 mv643xx_eth_set_link_ksettings(struct net_device *dev,
1605 const struct ethtool_link_ksettings *cmd)
1607 struct ethtool_link_ksettings c = *cmd;
1615 * The MAC does not support 1000baseT_Half.
1617 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1618 c.link_modes.advertising);
1619 advertising &= ~ADVERTISED_1000baseT_Half;
1620 ethtool_convert_legacy_u32_to_link_mode(c.link_modes.advertising,
1623 ret = phy_ethtool_ksettings_set(dev->phydev, &c);
1625 mv643xx_eth_adjust_link(dev);
1629 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1630 struct ethtool_drvinfo *drvinfo)
1632 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1633 sizeof(drvinfo->driver));
1634 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
1635 sizeof(drvinfo->version));
1636 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1637 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
1640 static int mv643xx_eth_nway_reset(struct net_device *dev)
1645 return genphy_restart_aneg(dev->phydev);
1649 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1651 struct mv643xx_eth_private *mp = netdev_priv(dev);
1653 ec->rx_coalesce_usecs = get_rx_coal(mp);
1654 ec->tx_coalesce_usecs = get_tx_coal(mp);
1660 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1662 struct mv643xx_eth_private *mp = netdev_priv(dev);
1664 set_rx_coal(mp, ec->rx_coalesce_usecs);
1665 set_tx_coal(mp, ec->tx_coalesce_usecs);
1671 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1673 struct mv643xx_eth_private *mp = netdev_priv(dev);
1675 er->rx_max_pending = 4096;
1676 er->tx_max_pending = 4096;
1678 er->rx_pending = mp->rx_ring_size;
1679 er->tx_pending = mp->tx_ring_size;
1683 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1685 struct mv643xx_eth_private *mp = netdev_priv(dev);
1687 if (er->rx_mini_pending || er->rx_jumbo_pending)
1690 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1691 mp->tx_ring_size = clamp_t(unsigned int, er->tx_pending,
1692 MV643XX_MAX_SKB_DESCS * 2, 4096);
1693 if (mp->tx_ring_size != er->tx_pending)
1694 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
1695 mp->tx_ring_size, er->tx_pending);
1697 if (netif_running(dev)) {
1698 mv643xx_eth_stop(dev);
1699 if (mv643xx_eth_open(dev)) {
1701 "fatal error on re-opening device after ring param change\n");
1711 mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
1713 struct mv643xx_eth_private *mp = netdev_priv(dev);
1714 bool rx_csum = features & NETIF_F_RXCSUM;
1716 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1721 static void mv643xx_eth_get_strings(struct net_device *dev,
1722 uint32_t stringset, uint8_t *data)
1726 if (stringset == ETH_SS_STATS) {
1727 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1728 memcpy(data + i * ETH_GSTRING_LEN,
1729 mv643xx_eth_stats[i].stat_string,
1735 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1736 struct ethtool_stats *stats,
1739 struct mv643xx_eth_private *mp = netdev_priv(dev);
1742 mv643xx_eth_get_stats(dev);
1743 mib_counters_update(mp);
1745 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1746 const struct mv643xx_eth_stats *stat;
1749 stat = mv643xx_eth_stats + i;
1751 if (stat->netdev_off >= 0)
1752 p = ((void *)mp->dev) + stat->netdev_off;
1754 p = ((void *)mp) + stat->mp_off;
1756 data[i] = (stat->sizeof_stat == 8) ?
1757 *(uint64_t *)p : *(uint32_t *)p;
1761 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1763 if (sset == ETH_SS_STATS)
1764 return ARRAY_SIZE(mv643xx_eth_stats);
1769 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1770 .get_drvinfo = mv643xx_eth_get_drvinfo,
1771 .nway_reset = mv643xx_eth_nway_reset,
1772 .get_link = ethtool_op_get_link,
1773 .get_coalesce = mv643xx_eth_get_coalesce,
1774 .set_coalesce = mv643xx_eth_set_coalesce,
1775 .get_ringparam = mv643xx_eth_get_ringparam,
1776 .set_ringparam = mv643xx_eth_set_ringparam,
1777 .get_strings = mv643xx_eth_get_strings,
1778 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1779 .get_sset_count = mv643xx_eth_get_sset_count,
1780 .get_ts_info = ethtool_op_get_ts_info,
1781 .get_wol = mv643xx_eth_get_wol,
1782 .set_wol = mv643xx_eth_set_wol,
1783 .get_link_ksettings = mv643xx_eth_get_link_ksettings,
1784 .set_link_ksettings = mv643xx_eth_set_link_ksettings,
1788 /* address handling *********************************************************/
1789 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1791 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1792 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1794 addr[0] = (mac_h >> 24) & 0xff;
1795 addr[1] = (mac_h >> 16) & 0xff;
1796 addr[2] = (mac_h >> 8) & 0xff;
1797 addr[3] = mac_h & 0xff;
1798 addr[4] = (mac_l >> 8) & 0xff;
1799 addr[5] = mac_l & 0xff;
1802 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1804 wrlp(mp, MAC_ADDR_HIGH,
1805 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1806 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1809 static u32 uc_addr_filter_mask(struct net_device *dev)
1811 struct netdev_hw_addr *ha;
1814 if (dev->flags & IFF_PROMISC)
1817 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1818 netdev_for_each_uc_addr(ha, dev) {
1819 if (memcmp(dev->dev_addr, ha->addr, 5))
1821 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
1824 nibbles |= 1 << (ha->addr[5] & 0x0f);
1830 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1832 struct mv643xx_eth_private *mp = netdev_priv(dev);
1837 uc_addr_set(mp, dev->dev_addr);
1839 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1841 nibbles = uc_addr_filter_mask(dev);
1843 port_config |= UNICAST_PROMISCUOUS_MODE;
1847 for (i = 0; i < 16; i += 4) {
1848 int off = UNICAST_TABLE(mp->port_num) + i;
1865 wrlp(mp, PORT_CONFIG, port_config);
1868 static int addr_crc(unsigned char *addr)
1873 for (i = 0; i < 6; i++) {
1876 crc = (crc ^ addr[i]) << 8;
1877 for (j = 7; j >= 0; j--) {
1878 if (crc & (0x100 << j))
1886 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1888 struct mv643xx_eth_private *mp = netdev_priv(dev);
1891 struct netdev_hw_addr *ha;
1894 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI))
1897 /* Allocate both mc_spec and mc_other tables */
1898 mc_spec = kcalloc(128, sizeof(u32), GFP_ATOMIC);
1901 mc_other = &mc_spec[64];
1903 netdev_for_each_mc_addr(ha, dev) {
1908 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1913 entry = addr_crc(a);
1916 table[entry >> 2] |= 1 << (8 * (entry & 3));
1919 for (i = 0; i < 64; i++) {
1920 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1922 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1930 for (i = 0; i < 64; i++) {
1931 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1933 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i * sizeof(u32),
1938 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1940 mv643xx_eth_program_unicast_filter(dev);
1941 mv643xx_eth_program_multicast_filter(dev);
1944 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1946 struct sockaddr *sa = addr;
1948 if (!is_valid_ether_addr(sa->sa_data))
1949 return -EADDRNOTAVAIL;
1951 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1953 netif_addr_lock_bh(dev);
1954 mv643xx_eth_program_unicast_filter(dev);
1955 netif_addr_unlock_bh(dev);
1961 /* rx/tx queue initialisation ***********************************************/
1962 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1964 struct rx_queue *rxq = mp->rxq + index;
1965 struct rx_desc *rx_desc;
1971 rxq->rx_ring_size = mp->rx_ring_size;
1973 rxq->rx_desc_count = 0;
1974 rxq->rx_curr_desc = 0;
1975 rxq->rx_used_desc = 0;
1977 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1979 if (index == 0 && size <= mp->rx_desc_sram_size) {
1980 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1981 mp->rx_desc_sram_size);
1982 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1984 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1985 size, &rxq->rx_desc_dma,
1989 if (rxq->rx_desc_area == NULL) {
1991 "can't allocate rx ring (%d bytes)\n", size);
1994 memset(rxq->rx_desc_area, 0, size);
1996 rxq->rx_desc_area_size = size;
1997 rxq->rx_skb = kcalloc(rxq->rx_ring_size, sizeof(*rxq->rx_skb),
1999 if (rxq->rx_skb == NULL)
2002 rx_desc = rxq->rx_desc_area;
2003 for (i = 0; i < rxq->rx_ring_size; i++) {
2007 if (nexti == rxq->rx_ring_size)
2010 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
2011 nexti * sizeof(struct rx_desc);
2018 if (index == 0 && size <= mp->rx_desc_sram_size)
2019 iounmap(rxq->rx_desc_area);
2021 dma_free_coherent(mp->dev->dev.parent, size,
2029 static void rxq_deinit(struct rx_queue *rxq)
2031 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
2036 for (i = 0; i < rxq->rx_ring_size; i++) {
2037 if (rxq->rx_skb[i]) {
2038 dev_kfree_skb(rxq->rx_skb[i]);
2039 rxq->rx_desc_count--;
2043 if (rxq->rx_desc_count) {
2044 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
2045 rxq->rx_desc_count);
2048 if (rxq->index == 0 &&
2049 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
2050 iounmap(rxq->rx_desc_area);
2052 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
2053 rxq->rx_desc_area, rxq->rx_desc_dma);
2058 static int txq_init(struct mv643xx_eth_private *mp, int index)
2060 struct tx_queue *txq = mp->txq + index;
2061 struct tx_desc *tx_desc;
2068 txq->tx_ring_size = mp->tx_ring_size;
2070 /* A queue must always have room for at least one skb.
2071 * Therefore, stop the queue when the free entries reaches
2072 * the maximum number of descriptors per skb.
2074 txq->tx_stop_threshold = txq->tx_ring_size - MV643XX_MAX_SKB_DESCS;
2075 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2077 txq->tx_desc_count = 0;
2078 txq->tx_curr_desc = 0;
2079 txq->tx_used_desc = 0;
2081 size = txq->tx_ring_size * sizeof(struct tx_desc);
2083 if (index == 0 && size <= mp->tx_desc_sram_size) {
2084 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2085 mp->tx_desc_sram_size);
2086 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2088 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
2089 size, &txq->tx_desc_dma,
2093 if (txq->tx_desc_area == NULL) {
2095 "can't allocate tx ring (%d bytes)\n", size);
2098 memset(txq->tx_desc_area, 0, size);
2100 txq->tx_desc_area_size = size;
2102 tx_desc = txq->tx_desc_area;
2103 for (i = 0; i < txq->tx_ring_size; i++) {
2104 struct tx_desc *txd = tx_desc + i;
2108 if (nexti == txq->tx_ring_size)
2112 txd->next_desc_ptr = txq->tx_desc_dma +
2113 nexti * sizeof(struct tx_desc);
2116 txq->tx_desc_mapping = kcalloc(txq->tx_ring_size, sizeof(char),
2118 if (!txq->tx_desc_mapping) {
2120 goto err_free_desc_area;
2123 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2124 txq->tso_hdrs = dma_alloc_coherent(mp->dev->dev.parent,
2125 txq->tx_ring_size * TSO_HEADER_SIZE,
2126 &txq->tso_hdrs_dma, GFP_KERNEL);
2127 if (txq->tso_hdrs == NULL) {
2129 goto err_free_desc_mapping;
2131 skb_queue_head_init(&txq->tx_skb);
2135 err_free_desc_mapping:
2136 kfree(txq->tx_desc_mapping);
2138 if (index == 0 && size <= mp->tx_desc_sram_size)
2139 iounmap(txq->tx_desc_area);
2141 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2142 txq->tx_desc_area, txq->tx_desc_dma);
2146 static void txq_deinit(struct tx_queue *txq)
2148 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2151 txq_reclaim(txq, txq->tx_ring_size, 1);
2153 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2155 if (txq->index == 0 &&
2156 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2157 iounmap(txq->tx_desc_area);
2159 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
2160 txq->tx_desc_area, txq->tx_desc_dma);
2161 kfree(txq->tx_desc_mapping);
2164 dma_free_coherent(mp->dev->dev.parent,
2165 txq->tx_ring_size * TSO_HEADER_SIZE,
2166 txq->tso_hdrs, txq->tso_hdrs_dma);
2170 /* netdev ops and related ***************************************************/
2171 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2176 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
2181 if (int_cause & INT_EXT) {
2182 int_cause &= ~INT_EXT;
2183 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2187 wrlp(mp, INT_CAUSE, ~int_cause);
2188 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2189 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2190 mp->work_rx |= (int_cause & INT_RX) >> 2;
2193 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2194 if (int_cause_ext) {
2195 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2196 if (int_cause_ext & INT_EXT_LINK_PHY)
2198 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2204 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2206 struct net_device *dev = (struct net_device *)dev_id;
2207 struct mv643xx_eth_private *mp = netdev_priv(dev);
2209 if (unlikely(!mv643xx_eth_collect_events(mp)))
2212 wrlp(mp, INT_MASK, 0);
2213 napi_schedule(&mp->napi);
2218 static void handle_link_event(struct mv643xx_eth_private *mp)
2220 struct net_device *dev = mp->dev;
2226 port_status = rdlp(mp, PORT_STATUS);
2227 if (!(port_status & LINK_UP)) {
2228 if (netif_carrier_ok(dev)) {
2231 netdev_info(dev, "link down\n");
2233 netif_carrier_off(dev);
2235 for (i = 0; i < mp->txq_count; i++) {
2236 struct tx_queue *txq = mp->txq + i;
2238 txq_reclaim(txq, txq->tx_ring_size, 1);
2239 txq_reset_hw_ptr(txq);
2245 switch (port_status & PORT_SPEED_MASK) {
2249 case PORT_SPEED_100:
2252 case PORT_SPEED_1000:
2259 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2260 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2262 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2263 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2265 if (!netif_carrier_ok(dev))
2266 netif_carrier_on(dev);
2269 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2271 struct mv643xx_eth_private *mp;
2274 mp = container_of(napi, struct mv643xx_eth_private, napi);
2276 if (unlikely(mp->oom)) {
2278 del_timer(&mp->rx_oom);
2282 while (work_done < budget) {
2287 if (mp->work_link) {
2289 handle_link_event(mp);
2294 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2295 if (likely(!mp->oom))
2296 queue_mask |= mp->work_rx_refill;
2299 if (mv643xx_eth_collect_events(mp))
2304 queue = fls(queue_mask) - 1;
2305 queue_mask = 1 << queue;
2307 work_tbd = budget - work_done;
2311 if (mp->work_tx_end & queue_mask) {
2312 txq_kick(mp->txq + queue);
2313 } else if (mp->work_tx & queue_mask) {
2314 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2315 txq_maybe_wake(mp->txq + queue);
2316 } else if (mp->work_rx & queue_mask) {
2317 work_done += rxq_process(mp->rxq + queue, work_tbd);
2318 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
2319 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2325 if (work_done < budget) {
2327 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2328 napi_complete(napi);
2329 wrlp(mp, INT_MASK, mp->int_mask);
2335 static inline void oom_timer_wrapper(unsigned long data)
2337 struct mv643xx_eth_private *mp = (void *)data;
2339 napi_schedule(&mp->napi);
2342 static void port_start(struct mv643xx_eth_private *mp)
2344 struct net_device *dev = mp->dev;
2349 * Perform PHY reset, if there is a PHY.
2352 struct ethtool_link_ksettings cmd;
2354 mv643xx_eth_get_link_ksettings(dev, &cmd);
2355 phy_init_hw(dev->phydev);
2356 mv643xx_eth_set_link_ksettings(
2357 dev, (const struct ethtool_link_ksettings *)&cmd);
2358 phy_start(dev->phydev);
2362 * Configure basic link parameters.
2364 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2366 pscr |= SERIAL_PORT_ENABLE;
2367 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2369 pscr |= DO_NOT_FORCE_LINK_FAIL;
2371 pscr |= FORCE_LINK_PASS;
2372 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2375 * Configure TX path and queues.
2377 tx_set_rate(mp, 1000000000, 16777216);
2378 for (i = 0; i < mp->txq_count; i++) {
2379 struct tx_queue *txq = mp->txq + i;
2381 txq_reset_hw_ptr(txq);
2382 txq_set_rate(txq, 1000000000, 16777216);
2383 txq_set_fixed_prio_mode(txq);
2387 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2388 * frames to RX queue #0, and include the pseudo-header when
2389 * calculating receive checksums.
2391 mv643xx_eth_set_features(mp->dev, mp->dev->features);
2394 * Treat BPDUs as normal multicasts, and disable partition mode.
2396 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2399 * Add configured unicast addresses to address filter table.
2401 mv643xx_eth_program_unicast_filter(mp->dev);
2404 * Enable the receive queues.
2406 for (i = 0; i < mp->rxq_count; i++) {
2407 struct rx_queue *rxq = mp->rxq + i;
2410 addr = (u32)rxq->rx_desc_dma;
2411 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2412 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2418 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2423 * Reserve 2+14 bytes for an ethernet header (the hardware
2424 * automatically prepends 2 bytes of dummy data to each
2425 * received packet), 16 bytes for up to four VLAN tags, and
2426 * 4 bytes for the trailing FCS -- 36 bytes total.
2428 skb_size = mp->dev->mtu + 36;
2431 * Make sure that the skb size is a multiple of 8 bytes, as
2432 * the lower three bits of the receive descriptor's buffer
2433 * size field are ignored by the hardware.
2435 mp->skb_size = (skb_size + 7) & ~7;
2438 * If NET_SKB_PAD is smaller than a cache line,
2439 * netdev_alloc_skb() will cause skb->data to be misaligned
2440 * to a cache line boundary. If this is the case, include
2441 * some extra space to allow re-aligning the data area.
2443 mp->skb_size += SKB_DMA_REALIGN;
2446 static int mv643xx_eth_open(struct net_device *dev)
2448 struct mv643xx_eth_private *mp = netdev_priv(dev);
2452 wrlp(mp, INT_CAUSE, 0);
2453 wrlp(mp, INT_CAUSE_EXT, 0);
2454 rdlp(mp, INT_CAUSE_EXT);
2456 err = request_irq(dev->irq, mv643xx_eth_irq,
2457 IRQF_SHARED, dev->name, dev);
2459 netdev_err(dev, "can't assign irq\n");
2463 mv643xx_eth_recalc_skb_size(mp);
2465 napi_enable(&mp->napi);
2467 mp->int_mask = INT_EXT;
2469 for (i = 0; i < mp->rxq_count; i++) {
2470 err = rxq_init(mp, i);
2473 rxq_deinit(mp->rxq + i);
2477 rxq_refill(mp->rxq + i, INT_MAX);
2478 mp->int_mask |= INT_RX_0 << i;
2482 mp->rx_oom.expires = jiffies + (HZ / 10);
2483 add_timer(&mp->rx_oom);
2486 for (i = 0; i < mp->txq_count; i++) {
2487 err = txq_init(mp, i);
2490 txq_deinit(mp->txq + i);
2493 mp->int_mask |= INT_TX_END_0 << i;
2496 add_timer(&mp->mib_counters_timer);
2499 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2500 wrlp(mp, INT_MASK, mp->int_mask);
2506 for (i = 0; i < mp->rxq_count; i++)
2507 rxq_deinit(mp->rxq + i);
2509 free_irq(dev->irq, dev);
2514 static void port_reset(struct mv643xx_eth_private *mp)
2519 for (i = 0; i < mp->rxq_count; i++)
2520 rxq_disable(mp->rxq + i);
2521 for (i = 0; i < mp->txq_count; i++)
2522 txq_disable(mp->txq + i);
2525 u32 ps = rdlp(mp, PORT_STATUS);
2527 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2532 /* Reset the Enable bit in the Configuration Register */
2533 data = rdlp(mp, PORT_SERIAL_CONTROL);
2534 data &= ~(SERIAL_PORT_ENABLE |
2535 DO_NOT_FORCE_LINK_FAIL |
2537 wrlp(mp, PORT_SERIAL_CONTROL, data);
2540 static int mv643xx_eth_stop(struct net_device *dev)
2542 struct mv643xx_eth_private *mp = netdev_priv(dev);
2545 wrlp(mp, INT_MASK_EXT, 0x00000000);
2546 wrlp(mp, INT_MASK, 0x00000000);
2549 napi_disable(&mp->napi);
2551 del_timer_sync(&mp->rx_oom);
2553 netif_carrier_off(dev);
2555 phy_stop(dev->phydev);
2556 free_irq(dev->irq, dev);
2559 mv643xx_eth_get_stats(dev);
2560 mib_counters_update(mp);
2561 del_timer_sync(&mp->mib_counters_timer);
2563 for (i = 0; i < mp->rxq_count; i++)
2564 rxq_deinit(mp->rxq + i);
2565 for (i = 0; i < mp->txq_count; i++)
2566 txq_deinit(mp->txq + i);
2571 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2578 ret = phy_mii_ioctl(dev->phydev, ifr, cmd);
2580 mv643xx_eth_adjust_link(dev);
2584 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2586 struct mv643xx_eth_private *mp = netdev_priv(dev);
2589 mv643xx_eth_recalc_skb_size(mp);
2590 tx_set_rate(mp, 1000000000, 16777216);
2592 if (!netif_running(dev))
2596 * Stop and then re-open the interface. This will allocate RX
2597 * skbs of the new MTU.
2598 * There is a possible danger that the open will not succeed,
2599 * due to memory being full.
2601 mv643xx_eth_stop(dev);
2602 if (mv643xx_eth_open(dev)) {
2604 "fatal error on re-opening device after MTU change\n");
2610 static void tx_timeout_task(struct work_struct *ugly)
2612 struct mv643xx_eth_private *mp;
2614 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2615 if (netif_running(mp->dev)) {
2616 netif_tx_stop_all_queues(mp->dev);
2619 netif_tx_wake_all_queues(mp->dev);
2623 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2625 struct mv643xx_eth_private *mp = netdev_priv(dev);
2627 netdev_info(dev, "tx timeout\n");
2629 schedule_work(&mp->tx_timeout_task);
2632 #ifdef CONFIG_NET_POLL_CONTROLLER
2633 static void mv643xx_eth_netpoll(struct net_device *dev)
2635 struct mv643xx_eth_private *mp = netdev_priv(dev);
2637 wrlp(mp, INT_MASK, 0x00000000);
2640 mv643xx_eth_irq(dev->irq, dev);
2642 wrlp(mp, INT_MASK, mp->int_mask);
2647 /* platform glue ************************************************************/
2649 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2650 const struct mbus_dram_target_info *dram)
2652 void __iomem *base = msp->base;
2657 for (i = 0; i < 6; i++) {
2658 writel(0, base + WINDOW_BASE(i));
2659 writel(0, base + WINDOW_SIZE(i));
2661 writel(0, base + WINDOW_REMAP_HIGH(i));
2667 for (i = 0; i < dram->num_cs; i++) {
2668 const struct mbus_dram_window *cs = dram->cs + i;
2670 writel((cs->base & 0xffff0000) |
2671 (cs->mbus_attr << 8) |
2672 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2673 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2675 win_enable &= ~(1 << i);
2676 win_protect |= 3 << (2 * i);
2679 writel(win_enable, base + WINDOW_BAR_ENABLE);
2680 msp->win_protect = win_protect;
2683 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2686 * Check whether we have a 14-bit coal limit field in bits
2687 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2688 * SDMA config register.
2690 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2691 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2692 msp->extended_rx_coal_limit = 1;
2694 msp->extended_rx_coal_limit = 0;
2697 * Check whether the MAC supports TX rate control, and if
2698 * yes, whether its associated registers are in the old or
2701 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2702 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2703 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2705 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2706 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2707 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2709 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2713 #if defined(CONFIG_OF)
2714 static const struct of_device_id mv643xx_eth_shared_ids[] = {
2715 { .compatible = "marvell,orion-eth", },
2716 { .compatible = "marvell,kirkwood-eth", },
2719 MODULE_DEVICE_TABLE(of, mv643xx_eth_shared_ids);
2722 #if defined(CONFIG_OF) && !defined(CONFIG_MV64X60)
2723 #define mv643xx_eth_property(_np, _name, _v) \
2726 if (!of_property_read_u32(_np, "marvell," _name, &tmp)) \
2730 static struct platform_device *port_platdev[3];
2732 static int mv643xx_eth_shared_of_add_port(struct platform_device *pdev,
2733 struct device_node *pnp)
2735 struct platform_device *ppdev;
2736 struct mv643xx_eth_platform_data ppd;
2737 struct resource res;
2738 const char *mac_addr;
2742 memset(&ppd, 0, sizeof(ppd));
2745 memset(&res, 0, sizeof(res));
2746 if (!of_irq_to_resource(pnp, 0, &res)) {
2747 dev_err(&pdev->dev, "missing interrupt on %s\n", pnp->name);
2751 if (of_property_read_u32(pnp, "reg", &ppd.port_number)) {
2752 dev_err(&pdev->dev, "missing reg property on %s\n", pnp->name);
2756 if (ppd.port_number >= 3) {
2757 dev_err(&pdev->dev, "invalid reg property on %s\n", pnp->name);
2761 while (dev_num < 3 && port_platdev[dev_num])
2765 dev_err(&pdev->dev, "too many ports registered\n");
2769 mac_addr = of_get_mac_address(pnp);
2771 memcpy(ppd.mac_addr, mac_addr, ETH_ALEN);
2773 mv643xx_eth_property(pnp, "tx-queue-size", ppd.tx_queue_size);
2774 mv643xx_eth_property(pnp, "tx-sram-addr", ppd.tx_sram_addr);
2775 mv643xx_eth_property(pnp, "tx-sram-size", ppd.tx_sram_size);
2776 mv643xx_eth_property(pnp, "rx-queue-size", ppd.rx_queue_size);
2777 mv643xx_eth_property(pnp, "rx-sram-addr", ppd.rx_sram_addr);
2778 mv643xx_eth_property(pnp, "rx-sram-size", ppd.rx_sram_size);
2780 ppd.phy_node = of_parse_phandle(pnp, "phy-handle", 0);
2781 if (!ppd.phy_node) {
2782 ppd.phy_addr = MV643XX_ETH_PHY_NONE;
2783 of_property_read_u32(pnp, "speed", &ppd.speed);
2784 of_property_read_u32(pnp, "duplex", &ppd.duplex);
2787 ppdev = platform_device_alloc(MV643XX_ETH_NAME, dev_num);
2790 ppdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
2791 ppdev->dev.of_node = pnp;
2793 ret = platform_device_add_resources(ppdev, &res, 1);
2797 ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
2801 ret = platform_device_add(ppdev);
2805 port_platdev[dev_num] = ppdev;
2810 platform_device_put(ppdev);
2814 static int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2816 struct mv643xx_eth_shared_platform_data *pd;
2817 struct device_node *pnp, *np = pdev->dev.of_node;
2820 /* bail out if not registered from DT */
2824 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
2827 pdev->dev.platform_data = pd;
2829 mv643xx_eth_property(np, "tx-checksum-limit", pd->tx_csum_limit);
2831 for_each_available_child_of_node(np, pnp) {
2832 ret = mv643xx_eth_shared_of_add_port(pdev, pnp);
2841 static void mv643xx_eth_shared_of_remove(void)
2845 for (n = 0; n < 3; n++) {
2846 platform_device_del(port_platdev[n]);
2847 port_platdev[n] = NULL;
2851 static inline int mv643xx_eth_shared_of_probe(struct platform_device *pdev)
2856 static inline void mv643xx_eth_shared_of_remove(void)
2861 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2863 static int mv643xx_eth_version_printed;
2864 struct mv643xx_eth_shared_platform_data *pd;
2865 struct mv643xx_eth_shared_private *msp;
2866 const struct mbus_dram_target_info *dram;
2867 struct resource *res;
2870 if (!mv643xx_eth_version_printed++)
2871 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2872 mv643xx_eth_driver_version);
2874 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2878 msp = devm_kzalloc(&pdev->dev, sizeof(*msp), GFP_KERNEL);
2881 platform_set_drvdata(pdev, msp);
2883 msp->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
2884 if (msp->base == NULL)
2887 msp->clk = devm_clk_get(&pdev->dev, NULL);
2888 if (!IS_ERR(msp->clk))
2889 clk_prepare_enable(msp->clk);
2892 * (Re-)program MBUS remapping windows if we are asked to.
2894 dram = mv_mbus_dram_info();
2896 mv643xx_eth_conf_mbus_windows(msp, dram);
2898 ret = mv643xx_eth_shared_of_probe(pdev);
2901 pd = dev_get_platdata(&pdev->dev);
2903 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2904 pd->tx_csum_limit : 9 * 1024;
2905 infer_hw_params(msp);
2910 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2912 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2914 mv643xx_eth_shared_of_remove();
2915 if (!IS_ERR(msp->clk))
2916 clk_disable_unprepare(msp->clk);
2920 static struct platform_driver mv643xx_eth_shared_driver = {
2921 .probe = mv643xx_eth_shared_probe,
2922 .remove = mv643xx_eth_shared_remove,
2924 .name = MV643XX_ETH_SHARED_NAME,
2925 .of_match_table = of_match_ptr(mv643xx_eth_shared_ids),
2929 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2931 int addr_shift = 5 * mp->port_num;
2934 data = rdl(mp, PHY_ADDR);
2935 data &= ~(0x1f << addr_shift);
2936 data |= (phy_addr & 0x1f) << addr_shift;
2937 wrl(mp, PHY_ADDR, data);
2940 static int phy_addr_get(struct mv643xx_eth_private *mp)
2944 data = rdl(mp, PHY_ADDR);
2946 return (data >> (5 * mp->port_num)) & 0x1f;
2949 static void set_params(struct mv643xx_eth_private *mp,
2950 struct mv643xx_eth_platform_data *pd)
2952 struct net_device *dev = mp->dev;
2953 unsigned int tx_ring_size;
2955 if (is_valid_ether_addr(pd->mac_addr))
2956 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2958 uc_addr_get(mp, dev->dev_addr);
2960 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2961 if (pd->rx_queue_size)
2962 mp->rx_ring_size = pd->rx_queue_size;
2963 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2964 mp->rx_desc_sram_size = pd->rx_sram_size;
2966 mp->rxq_count = pd->rx_queue_count ? : 1;
2968 tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2969 if (pd->tx_queue_size)
2970 tx_ring_size = pd->tx_queue_size;
2972 mp->tx_ring_size = clamp_t(unsigned int, tx_ring_size,
2973 MV643XX_MAX_SKB_DESCS * 2, 4096);
2974 if (mp->tx_ring_size != tx_ring_size)
2975 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
2976 mp->tx_ring_size, tx_ring_size);
2978 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2979 mp->tx_desc_sram_size = pd->tx_sram_size;
2981 mp->txq_count = pd->tx_queue_count ? : 1;
2984 static int get_phy_mode(struct mv643xx_eth_private *mp)
2986 struct device *dev = mp->dev->dev.parent;
2990 iface = of_get_phy_mode(dev->of_node);
2992 /* Historical default if unspecified. We could also read/write
2993 * the interface state in the PSC1
2996 iface = PHY_INTERFACE_MODE_GMII;
3000 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
3003 struct phy_device *phydev;
3007 char phy_id[MII_BUS_ID_SIZE + 3];
3009 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
3010 start = phy_addr_get(mp) & 0x1f;
3013 start = phy_addr & 0x1f;
3017 /* Attempt to connect to the PHY using orion-mdio */
3018 phydev = ERR_PTR(-ENODEV);
3019 for (i = 0; i < num; i++) {
3020 int addr = (start + i) & 0x1f;
3022 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
3023 "orion-mdio-mii", addr);
3025 phydev = phy_connect(mp->dev, phy_id, mv643xx_eth_adjust_link,
3027 if (!IS_ERR(phydev)) {
3028 phy_addr_set(mp, addr);
3036 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
3038 struct net_device *dev = mp->dev;
3039 struct phy_device *phy = dev->phydev;
3042 phy->autoneg = AUTONEG_ENABLE;
3045 phy->advertising = phy->supported | ADVERTISED_Autoneg;
3047 phy->autoneg = AUTONEG_DISABLE;
3048 phy->advertising = 0;
3050 phy->duplex = duplex;
3052 phy_start_aneg(phy);
3055 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
3057 struct net_device *dev = mp->dev;
3060 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
3061 if (pscr & SERIAL_PORT_ENABLE) {
3062 pscr &= ~SERIAL_PORT_ENABLE;
3063 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3066 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
3068 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
3069 if (speed == SPEED_1000)
3070 pscr |= SET_GMII_SPEED_TO_1000;
3071 else if (speed == SPEED_100)
3072 pscr |= SET_MII_SPEED_TO_100;
3074 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
3076 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
3077 if (duplex == DUPLEX_FULL)
3078 pscr |= SET_FULL_DUPLEX_MODE;
3081 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
3084 static const struct net_device_ops mv643xx_eth_netdev_ops = {
3085 .ndo_open = mv643xx_eth_open,
3086 .ndo_stop = mv643xx_eth_stop,
3087 .ndo_start_xmit = mv643xx_eth_xmit,
3088 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
3089 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
3090 .ndo_validate_addr = eth_validate_addr,
3091 .ndo_do_ioctl = mv643xx_eth_ioctl,
3092 .ndo_change_mtu = mv643xx_eth_change_mtu,
3093 .ndo_set_features = mv643xx_eth_set_features,
3094 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
3095 .ndo_get_stats = mv643xx_eth_get_stats,
3096 #ifdef CONFIG_NET_POLL_CONTROLLER
3097 .ndo_poll_controller = mv643xx_eth_netpoll,
3101 static int mv643xx_eth_probe(struct platform_device *pdev)
3103 struct mv643xx_eth_platform_data *pd;
3104 struct mv643xx_eth_private *mp;
3105 struct net_device *dev;
3106 struct phy_device *phydev = NULL;
3107 struct resource *res;
3110 pd = dev_get_platdata(&pdev->dev);
3112 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
3116 if (pd->shared == NULL) {
3117 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
3121 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
3125 SET_NETDEV_DEV(dev, &pdev->dev);
3126 mp = netdev_priv(dev);
3127 platform_set_drvdata(pdev, mp);
3129 mp->shared = platform_get_drvdata(pd->shared);
3130 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
3131 mp->port_num = pd->port_number;
3135 /* Kirkwood resets some registers on gated clocks. Especially
3136 * CLK125_BYPASS_EN must be cleared but is not available on
3137 * all other SoCs/System Controllers using this driver.
3139 if (of_device_is_compatible(pdev->dev.of_node,
3140 "marvell,kirkwood-eth-port"))
3141 wrlp(mp, PORT_SERIAL_CONTROL1,
3142 rdlp(mp, PORT_SERIAL_CONTROL1) & ~CLK125_BYPASS_EN);
3145 * Start with a default rate, and if there is a clock, allow
3146 * it to override the default.
3148 mp->t_clk = 133000000;
3149 mp->clk = devm_clk_get(&pdev->dev, NULL);
3150 if (!IS_ERR(mp->clk)) {
3151 clk_prepare_enable(mp->clk);
3152 mp->t_clk = clk_get_rate(mp->clk);
3153 } else if (!IS_ERR(mp->shared->clk)) {
3154 mp->t_clk = clk_get_rate(mp->shared->clk);
3158 netif_set_real_num_tx_queues(dev, mp->txq_count);
3159 netif_set_real_num_rx_queues(dev, mp->rxq_count);
3163 phydev = of_phy_connect(mp->dev, pd->phy_node,
3164 mv643xx_eth_adjust_link, 0,
3169 phy_addr_set(mp, phydev->mdio.addr);
3170 } else if (pd->phy_addr != MV643XX_ETH_PHY_NONE) {
3171 phydev = phy_scan(mp, pd->phy_addr);
3174 err = PTR_ERR(phydev);
3176 phy_init(mp, pd->speed, pd->duplex);
3178 if (err == -ENODEV) {
3179 err = -EPROBE_DEFER;
3185 dev->ethtool_ops = &mv643xx_eth_ethtool_ops;
3187 init_pscr(mp, pd->speed, pd->duplex);
3190 mib_counters_clear(mp);
3192 setup_timer(&mp->mib_counters_timer, mib_counters_timer_wrapper,
3194 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
3196 spin_lock_init(&mp->mib_counters_lock);
3198 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
3200 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, NAPI_POLL_WEIGHT);
3202 setup_timer(&mp->rx_oom, oom_timer_wrapper, (unsigned long)mp);
3205 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
3207 dev->irq = res->start;
3209 dev->netdev_ops = &mv643xx_eth_netdev_ops;
3211 dev->watchdog_timeo = 2 * HZ;
3214 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3215 dev->vlan_features = dev->features;
3217 dev->features |= NETIF_F_RXCSUM;
3218 dev->hw_features = dev->features;
3220 dev->priv_flags |= IFF_UNICAST_FLT;
3221 dev->gso_max_segs = MV643XX_MAX_TSO_SEGS;
3224 /* MTU range: 64 - 9500 */
3226 dev->max_mtu = 9500;
3228 SET_NETDEV_DEV(dev, &pdev->dev);
3231 >>>>>>> 2a26d99b251b8625d27aed14e97fc10707a3a81f
3232 if (mp->shared->win_protect)
3233 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
3235 netif_carrier_off(dev);
3237 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
3239 set_rx_coal(mp, 250);
3242 err = register_netdev(dev);
3246 netdev_notice(dev, "port %d with MAC address %pM\n",
3247 mp->port_num, dev->dev_addr);
3249 if (mp->tx_desc_sram_size > 0)
3250 netdev_notice(dev, "configured with sram\n");
3255 if (!IS_ERR(mp->clk))
3256 clk_disable_unprepare(mp->clk);
3262 static int mv643xx_eth_remove(struct platform_device *pdev)
3264 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3265 struct net_device *dev = mp->dev;
3267 unregister_netdev(mp->dev);
3269 phy_disconnect(dev->phydev);
3270 cancel_work_sync(&mp->tx_timeout_task);
3272 if (!IS_ERR(mp->clk))
3273 clk_disable_unprepare(mp->clk);
3275 free_netdev(mp->dev);
3280 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3282 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3284 /* Mask all interrupts on ethernet port */
3285 wrlp(mp, INT_MASK, 0);
3288 if (netif_running(mp->dev))
3292 static struct platform_driver mv643xx_eth_driver = {
3293 .probe = mv643xx_eth_probe,
3294 .remove = mv643xx_eth_remove,
3295 .shutdown = mv643xx_eth_shutdown,
3297 .name = MV643XX_ETH_NAME,
3301 static struct platform_driver * const drivers[] = {
3302 &mv643xx_eth_shared_driver,
3303 &mv643xx_eth_driver,
3306 static int __init mv643xx_eth_init_module(void)
3308 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
3310 module_init(mv643xx_eth_init_module);
3312 static void __exit mv643xx_eth_cleanup_module(void)
3314 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
3316 module_exit(mv643xx_eth_cleanup_module);
3318 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3319 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3320 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3321 MODULE_LICENSE("GPL");
3322 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3323 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);