1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Marvell PPv2 network controller for Armada 375 SoC.
5 * Copyright (C) 2014 Marvell
7 * Marcin Wojtas <mw@semihalf.com>
10 #include <linux/acpi.h>
11 #include <linux/kernel.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/platform_device.h>
15 #include <linux/skbuff.h>
16 #include <linux/inetdevice.h>
17 #include <linux/mbus.h>
18 #include <linux/module.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/interrupt.h>
21 #include <linux/cpumask.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_mdio.h>
25 #include <linux/of_net.h>
26 #include <linux/of_address.h>
27 #include <linux/of_device.h>
28 #include <linux/phy.h>
29 #include <linux/phylink.h>
30 #include <linux/phy/phy.h>
31 #include <linux/clk.h>
32 #include <linux/hrtimer.h>
33 #include <linux/ktime.h>
34 #include <linux/regmap.h>
35 #include <uapi/linux/ppp_defs.h>
41 #include "mvpp2_prs.h"
42 #include "mvpp2_cls.h"
44 enum mvpp2_bm_pool_log_num {
54 } mvpp2_pools[MVPP2_BM_POOLS_NUM];
56 /* The prototype is added here to be used in start_dev when using ACPI. This
57 * will be removed once phylink is used for all modes (dt+ACPI).
59 static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
60 const struct phylink_link_state *state);
61 static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode,
62 phy_interface_t interface, struct phy_device *phy);
65 #define MVPP2_QDIST_SINGLE_MODE 0
66 #define MVPP2_QDIST_MULTI_MODE 1
68 static int queue_mode = MVPP2_QDIST_MULTI_MODE;
70 module_param(queue_mode, int, 0444);
71 MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
73 /* Utility/helper methods */
75 void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
77 writel(data, priv->swth_base[0] + offset);
80 u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
82 return readl(priv->swth_base[0] + offset);
85 static u32 mvpp2_read_relaxed(struct mvpp2 *priv, u32 offset)
87 return readl_relaxed(priv->swth_base[0] + offset);
90 static inline u32 mvpp2_cpu_to_thread(struct mvpp2 *priv, int cpu)
92 return cpu % priv->nthreads;
95 /* These accessors should be used to access:
97 * - per-thread registers, where each thread has its own copy of the
100 * MVPP2_BM_VIRT_ALLOC_REG
101 * MVPP2_BM_ADDR_HIGH_ALLOC
102 * MVPP22_BM_ADDR_HIGH_RLS_REG
103 * MVPP2_BM_VIRT_RLS_REG
104 * MVPP2_ISR_RX_TX_CAUSE_REG
105 * MVPP2_ISR_RX_TX_MASK_REG
107 * MVPP2_AGGR_TXQ_UPDATE_REG
108 * MVPP2_TXQ_RSVD_REQ_REG
109 * MVPP2_TXQ_RSVD_RSLT_REG
113 * - global registers that must be accessed through a specific thread
114 * window, because they are related to an access to a per-thread
117 * MVPP2_BM_PHY_ALLOC_REG (related to MVPP2_BM_VIRT_ALLOC_REG)
118 * MVPP2_BM_PHY_RLS_REG (related to MVPP2_BM_VIRT_RLS_REG)
119 * MVPP2_RXQ_THRESH_REG (related to MVPP2_RXQ_NUM_REG)
120 * MVPP2_RXQ_DESC_ADDR_REG (related to MVPP2_RXQ_NUM_REG)
121 * MVPP2_RXQ_DESC_SIZE_REG (related to MVPP2_RXQ_NUM_REG)
122 * MVPP2_RXQ_INDEX_REG (related to MVPP2_RXQ_NUM_REG)
123 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
124 * MVPP2_TXQ_DESC_ADDR_REG (related to MVPP2_TXQ_NUM_REG)
125 * MVPP2_TXQ_DESC_SIZE_REG (related to MVPP2_TXQ_NUM_REG)
126 * MVPP2_TXQ_INDEX_REG (related to MVPP2_TXQ_NUM_REG)
127 * MVPP2_TXQ_PENDING_REG (related to MVPP2_TXQ_NUM_REG)
128 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
129 * MVPP2_TXQ_PREF_BUF_REG (related to MVPP2_TXQ_NUM_REG)
131 static void mvpp2_thread_write(struct mvpp2 *priv, unsigned int thread,
132 u32 offset, u32 data)
134 writel(data, priv->swth_base[thread] + offset);
137 static u32 mvpp2_thread_read(struct mvpp2 *priv, unsigned int thread,
140 return readl(priv->swth_base[thread] + offset);
143 static void mvpp2_thread_write_relaxed(struct mvpp2 *priv, unsigned int thread,
144 u32 offset, u32 data)
146 writel_relaxed(data, priv->swth_base[thread] + offset);
149 static u32 mvpp2_thread_read_relaxed(struct mvpp2 *priv, unsigned int thread,
152 return readl_relaxed(priv->swth_base[thread] + offset);
155 static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
156 struct mvpp2_tx_desc *tx_desc)
158 if (port->priv->hw_version == MVPP21)
159 return le32_to_cpu(tx_desc->pp21.buf_dma_addr);
161 return le64_to_cpu(tx_desc->pp22.buf_dma_addr_ptp) &
165 static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
166 struct mvpp2_tx_desc *tx_desc,
169 dma_addr_t addr, offset;
171 addr = dma_addr & ~MVPP2_TX_DESC_ALIGN;
172 offset = dma_addr & MVPP2_TX_DESC_ALIGN;
174 if (port->priv->hw_version == MVPP21) {
175 tx_desc->pp21.buf_dma_addr = cpu_to_le32(addr);
176 tx_desc->pp21.packet_offset = offset;
178 __le64 val = cpu_to_le64(addr);
180 tx_desc->pp22.buf_dma_addr_ptp &= ~cpu_to_le64(MVPP2_DESC_DMA_MASK);
181 tx_desc->pp22.buf_dma_addr_ptp |= val;
182 tx_desc->pp22.packet_offset = offset;
186 static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
187 struct mvpp2_tx_desc *tx_desc)
189 if (port->priv->hw_version == MVPP21)
190 return le16_to_cpu(tx_desc->pp21.data_size);
192 return le16_to_cpu(tx_desc->pp22.data_size);
195 static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
196 struct mvpp2_tx_desc *tx_desc,
199 if (port->priv->hw_version == MVPP21)
200 tx_desc->pp21.data_size = cpu_to_le16(size);
202 tx_desc->pp22.data_size = cpu_to_le16(size);
205 static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
206 struct mvpp2_tx_desc *tx_desc,
209 if (port->priv->hw_version == MVPP21)
210 tx_desc->pp21.phys_txq = txq;
212 tx_desc->pp22.phys_txq = txq;
215 static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
216 struct mvpp2_tx_desc *tx_desc,
217 unsigned int command)
219 if (port->priv->hw_version == MVPP21)
220 tx_desc->pp21.command = cpu_to_le32(command);
222 tx_desc->pp22.command = cpu_to_le32(command);
225 static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
226 struct mvpp2_tx_desc *tx_desc)
228 if (port->priv->hw_version == MVPP21)
229 return tx_desc->pp21.packet_offset;
231 return tx_desc->pp22.packet_offset;
234 static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
235 struct mvpp2_rx_desc *rx_desc)
237 if (port->priv->hw_version == MVPP21)
238 return le32_to_cpu(rx_desc->pp21.buf_dma_addr);
240 return le64_to_cpu(rx_desc->pp22.buf_dma_addr_key_hash) &
244 static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
245 struct mvpp2_rx_desc *rx_desc)
247 if (port->priv->hw_version == MVPP21)
248 return le32_to_cpu(rx_desc->pp21.buf_cookie);
250 return le64_to_cpu(rx_desc->pp22.buf_cookie_misc) &
254 static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
255 struct mvpp2_rx_desc *rx_desc)
257 if (port->priv->hw_version == MVPP21)
258 return le16_to_cpu(rx_desc->pp21.data_size);
260 return le16_to_cpu(rx_desc->pp22.data_size);
263 static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
264 struct mvpp2_rx_desc *rx_desc)
266 if (port->priv->hw_version == MVPP21)
267 return le32_to_cpu(rx_desc->pp21.status);
269 return le32_to_cpu(rx_desc->pp22.status);
272 static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)
274 txq_pcpu->txq_get_index++;
275 if (txq_pcpu->txq_get_index == txq_pcpu->size)
276 txq_pcpu->txq_get_index = 0;
279 static void mvpp2_txq_inc_put(struct mvpp2_port *port,
280 struct mvpp2_txq_pcpu *txq_pcpu,
282 struct mvpp2_tx_desc *tx_desc)
284 struct mvpp2_txq_pcpu_buf *tx_buf =
285 txq_pcpu->buffs + txq_pcpu->txq_put_index;
287 tx_buf->size = mvpp2_txdesc_size_get(port, tx_desc);
288 tx_buf->dma = mvpp2_txdesc_dma_addr_get(port, tx_desc) +
289 mvpp2_txdesc_offset_get(port, tx_desc);
290 txq_pcpu->txq_put_index++;
291 if (txq_pcpu->txq_put_index == txq_pcpu->size)
292 txq_pcpu->txq_put_index = 0;
295 /* Get number of physical egress port */
296 static inline int mvpp2_egress_port(struct mvpp2_port *port)
298 return MVPP2_MAX_TCONT + port->id;
301 /* Get number of physical TXQ */
302 static inline int mvpp2_txq_phys(int port, int txq)
304 return (MVPP2_MAX_TCONT + port) * MVPP2_MAX_TXQ + txq;
307 static void *mvpp2_frag_alloc(const struct mvpp2_bm_pool *pool)
309 if (likely(pool->frag_size <= PAGE_SIZE))
310 return netdev_alloc_frag(pool->frag_size);
312 return kmalloc(pool->frag_size, GFP_ATOMIC);
315 static void mvpp2_frag_free(const struct mvpp2_bm_pool *pool, void *data)
317 if (likely(pool->frag_size <= PAGE_SIZE))
323 /* Buffer Manager configuration routines */
326 static int mvpp2_bm_pool_create(struct platform_device *pdev,
328 struct mvpp2_bm_pool *bm_pool, int size)
332 /* Number of buffer pointers must be a multiple of 16, as per
333 * hardware constraints
335 if (!IS_ALIGNED(size, 16))
338 /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
339 * bytes per buffer pointer
341 if (priv->hw_version == MVPP21)
342 bm_pool->size_bytes = 2 * sizeof(u32) * size;
344 bm_pool->size_bytes = 2 * sizeof(u64) * size;
346 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, bm_pool->size_bytes,
349 if (!bm_pool->virt_addr)
352 if (!IS_ALIGNED((unsigned long)bm_pool->virt_addr,
353 MVPP2_BM_POOL_PTR_ALIGN)) {
354 dma_free_coherent(&pdev->dev, bm_pool->size_bytes,
355 bm_pool->virt_addr, bm_pool->dma_addr);
356 dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
357 bm_pool->id, MVPP2_BM_POOL_PTR_ALIGN);
361 mvpp2_write(priv, MVPP2_BM_POOL_BASE_REG(bm_pool->id),
362 lower_32_bits(bm_pool->dma_addr));
363 mvpp2_write(priv, MVPP2_BM_POOL_SIZE_REG(bm_pool->id), size);
365 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
366 val |= MVPP2_BM_START_MASK;
367 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
369 bm_pool->size = size;
370 bm_pool->pkt_size = 0;
371 bm_pool->buf_num = 0;
376 /* Set pool buffer size */
377 static void mvpp2_bm_pool_bufsize_set(struct mvpp2 *priv,
378 struct mvpp2_bm_pool *bm_pool,
383 bm_pool->buf_size = buf_size;
385 val = ALIGN(buf_size, 1 << MVPP2_POOL_BUF_SIZE_OFFSET);
386 mvpp2_write(priv, MVPP2_POOL_BUF_SIZE_REG(bm_pool->id), val);
389 static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
390 struct mvpp2_bm_pool *bm_pool,
391 dma_addr_t *dma_addr,
392 phys_addr_t *phys_addr)
394 unsigned int thread = mvpp2_cpu_to_thread(priv, get_cpu());
396 *dma_addr = mvpp2_thread_read(priv, thread,
397 MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
398 *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
400 if (priv->hw_version == MVPP22) {
402 u32 dma_addr_highbits, phys_addr_highbits;
404 val = mvpp2_thread_read(priv, thread, MVPP22_BM_ADDR_HIGH_ALLOC);
405 dma_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_PHYS_MASK);
406 phys_addr_highbits = (val & MVPP22_BM_ADDR_HIGH_VIRT_MASK) >>
407 MVPP22_BM_ADDR_HIGH_VIRT_SHIFT;
409 if (sizeof(dma_addr_t) == 8)
410 *dma_addr |= (u64)dma_addr_highbits << 32;
412 if (sizeof(phys_addr_t) == 8)
413 *phys_addr |= (u64)phys_addr_highbits << 32;
419 /* Free all buffers from the pool */
420 static void mvpp2_bm_bufs_free(struct device *dev, struct mvpp2 *priv,
421 struct mvpp2_bm_pool *bm_pool, int buf_num)
425 if (buf_num > bm_pool->buf_num) {
426 WARN(1, "Pool does not have so many bufs pool(%d) bufs(%d)\n",
427 bm_pool->id, buf_num);
428 buf_num = bm_pool->buf_num;
431 for (i = 0; i < buf_num; i++) {
432 dma_addr_t buf_dma_addr;
433 phys_addr_t buf_phys_addr;
436 mvpp2_bm_bufs_get_addrs(dev, priv, bm_pool,
437 &buf_dma_addr, &buf_phys_addr);
439 dma_unmap_single(dev, buf_dma_addr,
440 bm_pool->buf_size, DMA_FROM_DEVICE);
442 data = (void *)phys_to_virt(buf_phys_addr);
446 mvpp2_frag_free(bm_pool, data);
449 /* Update BM driver with number of buffers removed from pool */
450 bm_pool->buf_num -= i;
453 /* Check number of buffers in BM pool */
454 static int mvpp2_check_hw_buf_num(struct mvpp2 *priv, struct mvpp2_bm_pool *bm_pool)
458 buf_num += mvpp2_read(priv, MVPP2_BM_POOL_PTRS_NUM_REG(bm_pool->id)) &
459 MVPP22_BM_POOL_PTRS_NUM_MASK;
460 buf_num += mvpp2_read(priv, MVPP2_BM_BPPI_PTRS_NUM_REG(bm_pool->id)) &
461 MVPP2_BM_BPPI_PTR_NUM_MASK;
463 /* HW has one buffer ready which is not reflected in the counters */
471 static int mvpp2_bm_pool_destroy(struct platform_device *pdev,
473 struct mvpp2_bm_pool *bm_pool)
478 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
479 mvpp2_bm_bufs_free(&pdev->dev, priv, bm_pool, buf_num);
481 /* Check buffer counters after free */
482 buf_num = mvpp2_check_hw_buf_num(priv, bm_pool);
484 WARN(1, "cannot free all buffers in pool %d, buf_num left %d\n",
485 bm_pool->id, bm_pool->buf_num);
489 val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
490 val |= MVPP2_BM_STOP_MASK;
491 mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
493 dma_free_coherent(&pdev->dev, bm_pool->size_bytes,
499 static int mvpp2_bm_pools_init(struct platform_device *pdev,
503 struct mvpp2_bm_pool *bm_pool;
505 /* Create all pools with maximum size */
506 size = MVPP2_BM_POOL_SIZE_MAX;
507 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
508 bm_pool = &priv->bm_pools[i];
510 err = mvpp2_bm_pool_create(pdev, priv, bm_pool, size);
512 goto err_unroll_pools;
513 mvpp2_bm_pool_bufsize_set(priv, bm_pool, 0);
518 dev_err(&pdev->dev, "failed to create BM pool %d, size %d\n", i, size);
519 for (i = i - 1; i >= 0; i--)
520 mvpp2_bm_pool_destroy(pdev, priv, &priv->bm_pools[i]);
524 static int mvpp2_bm_init(struct platform_device *pdev, struct mvpp2 *priv)
528 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
529 /* Mask BM all interrupts */
530 mvpp2_write(priv, MVPP2_BM_INTR_MASK_REG(i), 0);
531 /* Clear BM cause register */
532 mvpp2_write(priv, MVPP2_BM_INTR_CAUSE_REG(i), 0);
535 /* Allocate and initialize BM pools */
536 priv->bm_pools = devm_kcalloc(&pdev->dev, MVPP2_BM_POOLS_NUM,
537 sizeof(*priv->bm_pools), GFP_KERNEL);
541 err = mvpp2_bm_pools_init(pdev, priv);
547 static void mvpp2_setup_bm_pool(void)
550 mvpp2_pools[MVPP2_BM_SHORT].buf_num = MVPP2_BM_SHORT_BUF_NUM;
551 mvpp2_pools[MVPP2_BM_SHORT].pkt_size = MVPP2_BM_SHORT_PKT_SIZE;
554 mvpp2_pools[MVPP2_BM_LONG].buf_num = MVPP2_BM_LONG_BUF_NUM;
555 mvpp2_pools[MVPP2_BM_LONG].pkt_size = MVPP2_BM_LONG_PKT_SIZE;
558 mvpp2_pools[MVPP2_BM_JUMBO].buf_num = MVPP2_BM_JUMBO_BUF_NUM;
559 mvpp2_pools[MVPP2_BM_JUMBO].pkt_size = MVPP2_BM_JUMBO_PKT_SIZE;
562 /* Attach long pool to rxq */
563 static void mvpp2_rxq_long_pool_set(struct mvpp2_port *port,
564 int lrxq, int long_pool)
569 /* Get queue physical ID */
570 prxq = port->rxqs[lrxq]->id;
572 if (port->priv->hw_version == MVPP21)
573 mask = MVPP21_RXQ_POOL_LONG_MASK;
575 mask = MVPP22_RXQ_POOL_LONG_MASK;
577 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
579 val |= (long_pool << MVPP2_RXQ_POOL_LONG_OFFS) & mask;
580 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
583 /* Attach short pool to rxq */
584 static void mvpp2_rxq_short_pool_set(struct mvpp2_port *port,
585 int lrxq, int short_pool)
590 /* Get queue physical ID */
591 prxq = port->rxqs[lrxq]->id;
593 if (port->priv->hw_version == MVPP21)
594 mask = MVPP21_RXQ_POOL_SHORT_MASK;
596 mask = MVPP22_RXQ_POOL_SHORT_MASK;
598 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
600 val |= (short_pool << MVPP2_RXQ_POOL_SHORT_OFFS) & mask;
601 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
604 static void *mvpp2_buf_alloc(struct mvpp2_port *port,
605 struct mvpp2_bm_pool *bm_pool,
606 dma_addr_t *buf_dma_addr,
607 phys_addr_t *buf_phys_addr,
613 data = mvpp2_frag_alloc(bm_pool);
617 dma_addr = dma_map_single(port->dev->dev.parent, data,
618 MVPP2_RX_BUF_SIZE(bm_pool->pkt_size),
620 if (unlikely(dma_mapping_error(port->dev->dev.parent, dma_addr))) {
621 mvpp2_frag_free(bm_pool, data);
624 *buf_dma_addr = dma_addr;
625 *buf_phys_addr = virt_to_phys(data);
630 /* Release buffer to BM */
631 static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
632 dma_addr_t buf_dma_addr,
633 phys_addr_t buf_phys_addr)
635 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
636 unsigned long flags = 0;
638 if (test_bit(thread, &port->priv->lock_map))
639 spin_lock_irqsave(&port->bm_lock[thread], flags);
641 if (port->priv->hw_version == MVPP22) {
644 if (sizeof(dma_addr_t) == 8)
645 val |= upper_32_bits(buf_dma_addr) &
646 MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK;
648 if (sizeof(phys_addr_t) == 8)
649 val |= (upper_32_bits(buf_phys_addr)
650 << MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT) &
651 MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK;
653 mvpp2_thread_write_relaxed(port->priv, thread,
654 MVPP22_BM_ADDR_HIGH_RLS_REG, val);
657 /* MVPP2_BM_VIRT_RLS_REG is not interpreted by HW, and simply
658 * returned in the "cookie" field of the RX
659 * descriptor. Instead of storing the virtual address, we
660 * store the physical address
662 mvpp2_thread_write_relaxed(port->priv, thread,
663 MVPP2_BM_VIRT_RLS_REG, buf_phys_addr);
664 mvpp2_thread_write_relaxed(port->priv, thread,
665 MVPP2_BM_PHY_RLS_REG(pool), buf_dma_addr);
667 if (test_bit(thread, &port->priv->lock_map))
668 spin_unlock_irqrestore(&port->bm_lock[thread], flags);
673 /* Allocate buffers for the pool */
674 static int mvpp2_bm_bufs_add(struct mvpp2_port *port,
675 struct mvpp2_bm_pool *bm_pool, int buf_num)
677 int i, buf_size, total_size;
679 phys_addr_t phys_addr;
682 buf_size = MVPP2_RX_BUF_SIZE(bm_pool->pkt_size);
683 total_size = MVPP2_RX_TOTAL_SIZE(buf_size);
686 (buf_num + bm_pool->buf_num > bm_pool->size)) {
687 netdev_err(port->dev,
688 "cannot allocate %d buffers for pool %d\n",
689 buf_num, bm_pool->id);
693 for (i = 0; i < buf_num; i++) {
694 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr,
695 &phys_addr, GFP_KERNEL);
699 mvpp2_bm_pool_put(port, bm_pool->id, dma_addr,
703 /* Update BM driver with number of buffers added to pool */
704 bm_pool->buf_num += i;
706 netdev_dbg(port->dev,
707 "pool %d: pkt_size=%4d, buf_size=%4d, total_size=%4d\n",
708 bm_pool->id, bm_pool->pkt_size, buf_size, total_size);
710 netdev_dbg(port->dev,
711 "pool %d: %d of %d buffers added\n",
712 bm_pool->id, i, buf_num);
716 /* Notify the driver that BM pool is being used as specific type and return the
717 * pool pointer on success
719 static struct mvpp2_bm_pool *
720 mvpp2_bm_pool_use(struct mvpp2_port *port, unsigned pool, int pkt_size)
722 struct mvpp2_bm_pool *new_pool = &port->priv->bm_pools[pool];
725 if (pool >= MVPP2_BM_POOLS_NUM) {
726 netdev_err(port->dev, "Invalid pool %d\n", pool);
730 /* Allocate buffers in case BM pool is used as long pool, but packet
731 * size doesn't match MTU or BM pool hasn't being used yet
733 if (new_pool->pkt_size == 0) {
736 /* Set default buffer number or free all the buffers in case
737 * the pool is not empty
739 pkts_num = new_pool->buf_num;
741 pkts_num = mvpp2_pools[pool].buf_num;
743 mvpp2_bm_bufs_free(port->dev->dev.parent,
744 port->priv, new_pool, pkts_num);
746 new_pool->pkt_size = pkt_size;
747 new_pool->frag_size =
748 SKB_DATA_ALIGN(MVPP2_RX_BUF_SIZE(pkt_size)) +
749 MVPP2_SKB_SHINFO_SIZE;
751 /* Allocate buffers for this pool */
752 num = mvpp2_bm_bufs_add(port, new_pool, pkts_num);
753 if (num != pkts_num) {
754 WARN(1, "pool %d: %d of %d allocated\n",
755 new_pool->id, num, pkts_num);
760 mvpp2_bm_pool_bufsize_set(port->priv, new_pool,
761 MVPP2_RX_BUF_SIZE(new_pool->pkt_size));
766 /* Initialize pools for swf */
767 static int mvpp2_swf_bm_pool_init(struct mvpp2_port *port)
770 enum mvpp2_bm_pool_log_num long_log_pool, short_log_pool;
772 /* If port pkt_size is higher than 1518B:
773 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
774 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
776 if (port->pkt_size > MVPP2_BM_LONG_PKT_SIZE) {
777 long_log_pool = MVPP2_BM_JUMBO;
778 short_log_pool = MVPP2_BM_LONG;
780 long_log_pool = MVPP2_BM_LONG;
781 short_log_pool = MVPP2_BM_SHORT;
784 if (!port->pool_long) {
786 mvpp2_bm_pool_use(port, long_log_pool,
787 mvpp2_pools[long_log_pool].pkt_size);
788 if (!port->pool_long)
791 port->pool_long->port_map |= BIT(port->id);
793 for (rxq = 0; rxq < port->nrxqs; rxq++)
794 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
797 if (!port->pool_short) {
799 mvpp2_bm_pool_use(port, short_log_pool,
800 mvpp2_pools[short_log_pool].pkt_size);
801 if (!port->pool_short)
804 port->pool_short->port_map |= BIT(port->id);
806 for (rxq = 0; rxq < port->nrxqs; rxq++)
807 mvpp2_rxq_short_pool_set(port, rxq,
808 port->pool_short->id);
814 static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)
816 struct mvpp2_port *port = netdev_priv(dev);
817 enum mvpp2_bm_pool_log_num new_long_pool;
818 int pkt_size = MVPP2_RX_PKT_SIZE(mtu);
820 /* If port MTU is higher than 1518B:
821 * HW Long pool - SW Jumbo pool, HW Short pool - SW Long pool
822 * else: HW Long pool - SW Long pool, HW Short pool - SW Short pool
824 if (pkt_size > MVPP2_BM_LONG_PKT_SIZE)
825 new_long_pool = MVPP2_BM_JUMBO;
827 new_long_pool = MVPP2_BM_LONG;
829 if (new_long_pool != port->pool_long->id) {
830 /* Remove port from old short & long pool */
831 port->pool_long = mvpp2_bm_pool_use(port, port->pool_long->id,
832 port->pool_long->pkt_size);
833 port->pool_long->port_map &= ~BIT(port->id);
834 port->pool_long = NULL;
836 port->pool_short = mvpp2_bm_pool_use(port, port->pool_short->id,
837 port->pool_short->pkt_size);
838 port->pool_short->port_map &= ~BIT(port->id);
839 port->pool_short = NULL;
841 port->pkt_size = pkt_size;
843 /* Add port to new short & long pool */
844 mvpp2_swf_bm_pool_init(port);
846 /* Update L4 checksum when jumbo enable/disable on port */
847 if (new_long_pool == MVPP2_BM_JUMBO && port->id != 0) {
848 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
849 dev->hw_features &= ~(NETIF_F_IP_CSUM |
852 dev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
853 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
858 dev->wanted_features = dev->features;
860 netdev_update_features(dev);
864 static inline void mvpp2_interrupts_enable(struct mvpp2_port *port)
866 int i, sw_thread_mask = 0;
868 for (i = 0; i < port->nqvecs; i++)
869 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
871 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
872 MVPP2_ISR_ENABLE_INTERRUPT(sw_thread_mask));
875 static inline void mvpp2_interrupts_disable(struct mvpp2_port *port)
877 int i, sw_thread_mask = 0;
879 for (i = 0; i < port->nqvecs; i++)
880 sw_thread_mask |= port->qvecs[i].sw_thread_mask;
882 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
883 MVPP2_ISR_DISABLE_INTERRUPT(sw_thread_mask));
886 static inline void mvpp2_qvec_interrupt_enable(struct mvpp2_queue_vector *qvec)
888 struct mvpp2_port *port = qvec->port;
890 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
891 MVPP2_ISR_ENABLE_INTERRUPT(qvec->sw_thread_mask));
894 static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
896 struct mvpp2_port *port = qvec->port;
898 mvpp2_write(port->priv, MVPP2_ISR_ENABLE_REG(port->id),
899 MVPP2_ISR_DISABLE_INTERRUPT(qvec->sw_thread_mask));
902 /* Mask the current thread's Rx/Tx interrupts
903 * Called by on_each_cpu(), guaranteed to run with migration disabled,
904 * using smp_processor_id() is OK.
906 static void mvpp2_interrupts_mask(void *arg)
908 struct mvpp2_port *port = arg;
910 /* If the thread isn't used, don't do anything */
911 if (smp_processor_id() > port->priv->nthreads)
914 mvpp2_thread_write(port->priv,
915 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
916 MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
919 /* Unmask the current thread's Rx/Tx interrupts.
920 * Called by on_each_cpu(), guaranteed to run with migration disabled,
921 * using smp_processor_id() is OK.
923 static void mvpp2_interrupts_unmask(void *arg)
925 struct mvpp2_port *port = arg;
928 /* If the thread isn't used, don't do anything */
929 if (smp_processor_id() > port->priv->nthreads)
932 val = MVPP2_CAUSE_MISC_SUM_MASK |
933 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
934 if (port->has_tx_irqs)
935 val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
937 mvpp2_thread_write(port->priv,
938 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
939 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
943 mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
948 if (port->priv->hw_version != MVPP22)
954 val = MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(MVPP22);
956 for (i = 0; i < port->nqvecs; i++) {
957 struct mvpp2_queue_vector *v = port->qvecs + i;
959 if (v->type != MVPP2_QUEUE_VECTOR_SHARED)
962 mvpp2_thread_write(port->priv, v->sw_thread_id,
963 MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
967 /* Port configuration routines */
969 static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
971 struct mvpp2 *priv = port->priv;
974 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
975 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
976 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
978 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
979 if (port->gop_id == 2)
980 val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII;
981 else if (port->gop_id == 3)
982 val |= GENCONF_CTRL0_PORT1_RGMII_MII;
983 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
986 static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
988 struct mvpp2 *priv = port->priv;
991 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
992 val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
993 GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;
994 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
996 if (port->gop_id > 1) {
997 regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
998 if (port->gop_id == 2)
999 val &= ~GENCONF_CTRL0_PORT0_RGMII;
1000 else if (port->gop_id == 3)
1001 val &= ~GENCONF_CTRL0_PORT1_RGMII_MII;
1002 regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
1006 static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
1008 struct mvpp2 *priv = port->priv;
1009 void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
1010 void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
1014 val = readl(xpcs + MVPP22_XPCS_CFG0);
1015 val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
1016 MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
1017 val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
1018 writel(val, xpcs + MVPP22_XPCS_CFG0);
1021 val = readl(mpcs + MVPP22_MPCS_CTRL);
1022 val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;
1023 writel(val, mpcs + MVPP22_MPCS_CTRL);
1025 val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
1026 val &= ~(MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7) | MAC_CLK_RESET_MAC |
1027 MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);
1028 val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
1029 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1031 val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;
1032 val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX;
1033 writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
1036 static int mvpp22_gop_init(struct mvpp2_port *port)
1038 struct mvpp2 *priv = port->priv;
1041 if (!priv->sysctrl_base)
1044 switch (port->phy_interface) {
1045 case PHY_INTERFACE_MODE_RGMII:
1046 case PHY_INTERFACE_MODE_RGMII_ID:
1047 case PHY_INTERFACE_MODE_RGMII_RXID:
1048 case PHY_INTERFACE_MODE_RGMII_TXID:
1049 if (port->gop_id == 0)
1051 mvpp22_gop_init_rgmii(port);
1053 case PHY_INTERFACE_MODE_SGMII:
1054 case PHY_INTERFACE_MODE_1000BASEX:
1055 case PHY_INTERFACE_MODE_2500BASEX:
1056 mvpp22_gop_init_sgmii(port);
1058 case PHY_INTERFACE_MODE_10GKR:
1059 if (port->gop_id != 0)
1061 mvpp22_gop_init_10gkr(port);
1064 goto unsupported_conf;
1067 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);
1068 val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |
1069 GENCONF_PORT_CTRL1_EN(port->gop_id);
1070 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);
1072 regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
1073 val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
1074 regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
1076 regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);
1077 val |= GENCONF_SOFT_RESET1_GOP;
1078 regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
1084 netdev_err(port->dev, "Invalid port configuration\n");
1088 static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
1092 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1093 port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
1094 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1095 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
1096 /* Enable the GMAC link status irq for this port */
1097 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1098 val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1099 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1102 if (port->gop_id == 0) {
1103 /* Enable the XLG/GIG irqs for this port */
1104 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1105 if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)
1106 val |= MVPP22_XLG_EXT_INT_MASK_XLG;
1108 val |= MVPP22_XLG_EXT_INT_MASK_GIG;
1109 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1113 static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
1117 if (port->gop_id == 0) {
1118 val = readl(port->base + MVPP22_XLG_EXT_INT_MASK);
1119 val &= ~(MVPP22_XLG_EXT_INT_MASK_XLG |
1120 MVPP22_XLG_EXT_INT_MASK_GIG);
1121 writel(val, port->base + MVPP22_XLG_EXT_INT_MASK);
1124 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1125 port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
1126 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1127 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
1128 val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
1129 val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
1130 writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
1134 static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
1138 if (phy_interface_mode_is_rgmii(port->phy_interface) ||
1139 port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
1140 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1141 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
1142 val = readl(port->base + MVPP22_GMAC_INT_MASK);
1143 val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
1144 writel(val, port->base + MVPP22_GMAC_INT_MASK);
1147 if (port->gop_id == 0) {
1148 val = readl(port->base + MVPP22_XLG_INT_MASK);
1149 val |= MVPP22_XLG_INT_MASK_LINK;
1150 writel(val, port->base + MVPP22_XLG_INT_MASK);
1153 mvpp22_gop_unmask_irq(port);
1156 /* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
1158 * The PHY mode used by the PPv2 driver comes from the network subsystem, while
1159 * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
1162 * The COMPHY configures the serdes lanes regardless of the actual use of the
1163 * lanes by the physical layer. This is why configurations like
1164 * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
1166 static int mvpp22_comphy_init(struct mvpp2_port *port)
1174 switch (port->phy_interface) {
1175 case PHY_INTERFACE_MODE_SGMII:
1176 case PHY_INTERFACE_MODE_1000BASEX:
1177 mode = PHY_MODE_SGMII;
1179 case PHY_INTERFACE_MODE_2500BASEX:
1180 mode = PHY_MODE_2500SGMII;
1182 case PHY_INTERFACE_MODE_10GKR:
1183 mode = PHY_MODE_10GKR;
1189 ret = phy_set_mode(port->comphy, mode);
1193 return phy_power_on(port->comphy);
1196 static void mvpp2_port_enable(struct mvpp2_port *port)
1200 /* Only GOP port 0 has an XLG MAC */
1201 if (port->gop_id == 0 &&
1202 (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
1203 port->phy_interface == PHY_INTERFACE_MODE_10GKR)) {
1204 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1205 val |= MVPP22_XLG_CTRL0_PORT_EN |
1206 MVPP22_XLG_CTRL0_MAC_RESET_DIS;
1207 val &= ~MVPP22_XLG_CTRL0_MIB_CNT_DIS;
1208 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1210 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1211 val |= MVPP2_GMAC_PORT_EN_MASK;
1212 val |= MVPP2_GMAC_MIB_CNTR_EN_MASK;
1213 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1217 static void mvpp2_port_disable(struct mvpp2_port *port)
1221 /* Only GOP port 0 has an XLG MAC */
1222 if (port->gop_id == 0 &&
1223 (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
1224 port->phy_interface == PHY_INTERFACE_MODE_10GKR)) {
1225 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
1226 val &= ~MVPP22_XLG_CTRL0_PORT_EN;
1227 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1229 /* Disable & reset should be done separately */
1230 val &= ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
1231 writel(val, port->base + MVPP22_XLG_CTRL0_REG);
1233 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1234 val &= ~(MVPP2_GMAC_PORT_EN_MASK);
1235 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1239 /* Set IEEE 802.3x Flow Control Xon Packet Transmission Mode */
1240 static void mvpp2_port_periodic_xon_disable(struct mvpp2_port *port)
1244 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG) &
1245 ~MVPP2_GMAC_PERIODIC_XON_EN_MASK;
1246 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1249 /* Configure loopback port */
1250 static void mvpp2_port_loopback_set(struct mvpp2_port *port,
1251 const struct phylink_link_state *state)
1255 val = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
1257 if (state->speed == 1000)
1258 val |= MVPP2_GMAC_GMII_LB_EN_MASK;
1260 val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
1262 if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
1263 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
1264 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
1265 val |= MVPP2_GMAC_PCS_LB_EN_MASK;
1267 val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
1269 writel(val, port->base + MVPP2_GMAC_CTRL_1_REG);
1272 struct mvpp2_ethtool_counter {
1273 unsigned int offset;
1274 const char string[ETH_GSTRING_LEN];
1278 static u64 mvpp2_read_count(struct mvpp2_port *port,
1279 const struct mvpp2_ethtool_counter *counter)
1283 val = readl(port->stats_base + counter->offset);
1284 if (counter->reg_is_64b)
1285 val += (u64)readl(port->stats_base + counter->offset + 4) << 32;
1290 /* Due to the fact that software statistics and hardware statistics are, by
1291 * design, incremented at different moments in the chain of packet processing,
1292 * it is very likely that incoming packets could have been dropped after being
1293 * counted by hardware but before reaching software statistics (most probably
1294 * multicast packets), and in the oppposite way, during transmission, FCS bytes
1295 * are added in between as well as TSO skb will be split and header bytes added.
1296 * Hence, statistics gathered from userspace with ifconfig (software) and
1297 * ethtool (hardware) cannot be compared.
1299 static const struct mvpp2_ethtool_counter mvpp2_ethtool_regs[] = {
1300 { MVPP2_MIB_GOOD_OCTETS_RCVD, "good_octets_received", true },
1301 { MVPP2_MIB_BAD_OCTETS_RCVD, "bad_octets_received" },
1302 { MVPP2_MIB_CRC_ERRORS_SENT, "crc_errors_sent" },
1303 { MVPP2_MIB_UNICAST_FRAMES_RCVD, "unicast_frames_received" },
1304 { MVPP2_MIB_BROADCAST_FRAMES_RCVD, "broadcast_frames_received" },
1305 { MVPP2_MIB_MULTICAST_FRAMES_RCVD, "multicast_frames_received" },
1306 { MVPP2_MIB_FRAMES_64_OCTETS, "frames_64_octets" },
1307 { MVPP2_MIB_FRAMES_65_TO_127_OCTETS, "frames_65_to_127_octet" },
1308 { MVPP2_MIB_FRAMES_128_TO_255_OCTETS, "frames_128_to_255_octet" },
1309 { MVPP2_MIB_FRAMES_256_TO_511_OCTETS, "frames_256_to_511_octet" },
1310 { MVPP2_MIB_FRAMES_512_TO_1023_OCTETS, "frames_512_to_1023_octet" },
1311 { MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS, "frames_1024_to_max_octet" },
1312 { MVPP2_MIB_GOOD_OCTETS_SENT, "good_octets_sent", true },
1313 { MVPP2_MIB_UNICAST_FRAMES_SENT, "unicast_frames_sent" },
1314 { MVPP2_MIB_MULTICAST_FRAMES_SENT, "multicast_frames_sent" },
1315 { MVPP2_MIB_BROADCAST_FRAMES_SENT, "broadcast_frames_sent" },
1316 { MVPP2_MIB_FC_SENT, "fc_sent" },
1317 { MVPP2_MIB_FC_RCVD, "fc_received" },
1318 { MVPP2_MIB_RX_FIFO_OVERRUN, "rx_fifo_overrun" },
1319 { MVPP2_MIB_UNDERSIZE_RCVD, "undersize_received" },
1320 { MVPP2_MIB_FRAGMENTS_RCVD, "fragments_received" },
1321 { MVPP2_MIB_OVERSIZE_RCVD, "oversize_received" },
1322 { MVPP2_MIB_JABBER_RCVD, "jabber_received" },
1323 { MVPP2_MIB_MAC_RCV_ERROR, "mac_receive_error" },
1324 { MVPP2_MIB_BAD_CRC_EVENT, "bad_crc_event" },
1325 { MVPP2_MIB_COLLISION, "collision" },
1326 { MVPP2_MIB_LATE_COLLISION, "late_collision" },
1329 static void mvpp2_ethtool_get_strings(struct net_device *netdev, u32 sset,
1332 if (sset == ETH_SS_STATS) {
1335 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1336 memcpy(data + i * ETH_GSTRING_LEN,
1337 &mvpp2_ethtool_regs[i].string, ETH_GSTRING_LEN);
1341 static void mvpp2_gather_hw_statistics(struct work_struct *work)
1343 struct delayed_work *del_work = to_delayed_work(work);
1344 struct mvpp2_port *port = container_of(del_work, struct mvpp2_port,
1349 mutex_lock(&port->gather_stats_lock);
1351 pstats = port->ethtool_stats;
1352 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1353 *pstats++ += mvpp2_read_count(port, &mvpp2_ethtool_regs[i]);
1355 /* No need to read again the counters right after this function if it
1356 * was called asynchronously by the user (ie. use of ethtool).
1358 cancel_delayed_work(&port->stats_work);
1359 queue_delayed_work(port->priv->stats_queue, &port->stats_work,
1360 MVPP2_MIB_COUNTERS_STATS_DELAY);
1362 mutex_unlock(&port->gather_stats_lock);
1365 static void mvpp2_ethtool_get_stats(struct net_device *dev,
1366 struct ethtool_stats *stats, u64 *data)
1368 struct mvpp2_port *port = netdev_priv(dev);
1370 /* Update statistics for the given port, then take the lock to avoid
1371 * concurrent accesses on the ethtool_stats structure during its copy.
1373 mvpp2_gather_hw_statistics(&port->stats_work.work);
1375 mutex_lock(&port->gather_stats_lock);
1376 memcpy(data, port->ethtool_stats,
1377 sizeof(u64) * ARRAY_SIZE(mvpp2_ethtool_regs));
1378 mutex_unlock(&port->gather_stats_lock);
1381 static int mvpp2_ethtool_get_sset_count(struct net_device *dev, int sset)
1383 if (sset == ETH_SS_STATS)
1384 return ARRAY_SIZE(mvpp2_ethtool_regs);
1389 static void mvpp2_port_reset(struct mvpp2_port *port)
1394 /* Read the GOP statistics to reset the hardware counters */
1395 for (i = 0; i < ARRAY_SIZE(mvpp2_ethtool_regs); i++)
1396 mvpp2_read_count(port, &mvpp2_ethtool_regs[i]);
1398 val = readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
1399 ~MVPP2_GMAC_PORT_RESET_MASK;
1400 writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
1402 while (readl(port->base + MVPP2_GMAC_CTRL_2_REG) &
1403 MVPP2_GMAC_PORT_RESET_MASK)
1407 /* Change maximum receive size of the port */
1408 static inline void mvpp2_gmac_max_rx_size_set(struct mvpp2_port *port)
1412 val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
1413 val &= ~MVPP2_GMAC_MAX_RX_SIZE_MASK;
1414 val |= (((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
1415 MVPP2_GMAC_MAX_RX_SIZE_OFFS);
1416 writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
1419 /* Change maximum receive size of the port */
1420 static inline void mvpp2_xlg_max_rx_size_set(struct mvpp2_port *port)
1424 val = readl(port->base + MVPP22_XLG_CTRL1_REG);
1425 val &= ~MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK;
1426 val |= ((port->pkt_size - MVPP2_MH_SIZE) / 2) <<
1427 MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS;
1428 writel(val, port->base + MVPP22_XLG_CTRL1_REG);
1431 /* Set defaults to the MVPP2 port */
1432 static void mvpp2_defaults_set(struct mvpp2_port *port)
1434 int tx_port_num, val, queue, ptxq, lrxq;
1436 if (port->priv->hw_version == MVPP21) {
1437 /* Update TX FIFO MIN Threshold */
1438 val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1439 val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
1440 /* Min. TX threshold must be less than minimal packet length */
1441 val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(64 - 4 - 2);
1442 writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
1445 /* Disable Legacy WRR, Disable EJP, Release from reset */
1446 tx_port_num = mvpp2_egress_port(port);
1447 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG,
1449 mvpp2_write(port->priv, MVPP2_TXP_SCHED_CMD_1_REG, 0);
1451 /* Set TXQ scheduling to Round-Robin */
1452 mvpp2_write(port->priv, MVPP2_TXP_SCHED_FIXED_PRIO_REG, 0);
1454 /* Close bandwidth for all queues */
1455 for (queue = 0; queue < MVPP2_MAX_TXQ; queue++) {
1456 ptxq = mvpp2_txq_phys(port->id, queue);
1457 mvpp2_write(port->priv,
1458 MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(ptxq), 0);
1461 /* Set refill period to 1 usec, refill tokens
1462 * and bucket size to maximum
1464 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PERIOD_REG,
1465 port->priv->tclk / USEC_PER_SEC);
1466 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_REFILL_REG);
1467 val &= ~MVPP2_TXP_REFILL_PERIOD_ALL_MASK;
1468 val |= MVPP2_TXP_REFILL_PERIOD_MASK(1);
1469 val |= MVPP2_TXP_REFILL_TOKENS_ALL_MASK;
1470 mvpp2_write(port->priv, MVPP2_TXP_SCHED_REFILL_REG, val);
1471 val = MVPP2_TXP_TOKEN_SIZE_MAX;
1472 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1474 /* Set MaximumLowLatencyPacketSize value to 256 */
1475 mvpp2_write(port->priv, MVPP2_RX_CTRL_REG(port->id),
1476 MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK |
1477 MVPP2_RX_LOW_LATENCY_PKT_SIZE(256));
1479 /* Enable Rx cache snoop */
1480 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1481 queue = port->rxqs[lrxq]->id;
1482 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1483 val |= MVPP2_SNOOP_PKT_SIZE_MASK |
1484 MVPP2_SNOOP_BUF_HDR_MASK;
1485 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1488 /* At default, mask all interrupts to all present cpus */
1489 mvpp2_interrupts_disable(port);
1492 /* Enable/disable receiving packets */
1493 static void mvpp2_ingress_enable(struct mvpp2_port *port)
1498 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1499 queue = port->rxqs[lrxq]->id;
1500 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1501 val &= ~MVPP2_RXQ_DISABLE_MASK;
1502 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1506 static void mvpp2_ingress_disable(struct mvpp2_port *port)
1511 for (lrxq = 0; lrxq < port->nrxqs; lrxq++) {
1512 queue = port->rxqs[lrxq]->id;
1513 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(queue));
1514 val |= MVPP2_RXQ_DISABLE_MASK;
1515 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(queue), val);
1519 /* Enable transmit via physical egress queue
1520 * - HW starts take descriptors from DRAM
1522 static void mvpp2_egress_enable(struct mvpp2_port *port)
1526 int tx_port_num = mvpp2_egress_port(port);
1528 /* Enable all initialized TXs. */
1530 for (queue = 0; queue < port->ntxqs; queue++) {
1531 struct mvpp2_tx_queue *txq = port->txqs[queue];
1534 qmap |= (1 << queue);
1537 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1538 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG, qmap);
1541 /* Disable transmit via physical egress queue
1542 * - HW doesn't take descriptors from DRAM
1544 static void mvpp2_egress_disable(struct mvpp2_port *port)
1548 int tx_port_num = mvpp2_egress_port(port);
1550 /* Issue stop command for active channels only */
1551 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1552 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) &
1553 MVPP2_TXP_SCHED_ENQ_MASK;
1555 mvpp2_write(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG,
1556 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET));
1558 /* Wait for all Tx activity to terminate. */
1561 if (delay >= MVPP2_TX_DISABLE_TIMEOUT_MSEC) {
1562 netdev_warn(port->dev,
1563 "Tx stop timed out, status=0x%08x\n",
1570 /* Check port TX Command register that all
1571 * Tx queues are stopped
1573 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG);
1574 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK);
1577 /* Rx descriptors helper methods */
1579 /* Get number of Rx descriptors occupied by received packets */
1581 mvpp2_rxq_received(struct mvpp2_port *port, int rxq_id)
1583 u32 val = mvpp2_read(port->priv, MVPP2_RXQ_STATUS_REG(rxq_id));
1585 return val & MVPP2_RXQ_OCCUPIED_MASK;
1588 /* Update Rx queue status with the number of occupied and available
1589 * Rx descriptor slots.
1592 mvpp2_rxq_status_update(struct mvpp2_port *port, int rxq_id,
1593 int used_count, int free_count)
1595 /* Decrement the number of used descriptors and increment count
1596 * increment the number of free descriptors.
1598 u32 val = used_count | (free_count << MVPP2_RXQ_NUM_NEW_OFFSET);
1600 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_UPDATE_REG(rxq_id), val);
1603 /* Get pointer to next RX descriptor to be processed by SW */
1604 static inline struct mvpp2_rx_desc *
1605 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
1607 int rx_desc = rxq->next_desc_to_proc;
1609 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
1610 prefetch(rxq->descs + rxq->next_desc_to_proc);
1611 return rxq->descs + rx_desc;
1614 /* Set rx queue offset */
1615 static void mvpp2_rxq_offset_set(struct mvpp2_port *port,
1616 int prxq, int offset)
1620 /* Convert offset from bytes to units of 32 bytes */
1621 offset = offset >> 5;
1623 val = mvpp2_read(port->priv, MVPP2_RXQ_CONFIG_REG(prxq));
1624 val &= ~MVPP2_RXQ_PACKET_OFFSET_MASK;
1627 val |= ((offset << MVPP2_RXQ_PACKET_OFFSET_OFFS) &
1628 MVPP2_RXQ_PACKET_OFFSET_MASK);
1630 mvpp2_write(port->priv, MVPP2_RXQ_CONFIG_REG(prxq), val);
1633 /* Tx descriptors helper methods */
1635 /* Get pointer to next Tx descriptor to be processed (send) by HW */
1636 static struct mvpp2_tx_desc *
1637 mvpp2_txq_next_desc_get(struct mvpp2_tx_queue *txq)
1639 int tx_desc = txq->next_desc_to_proc;
1641 txq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(txq, tx_desc);
1642 return txq->descs + tx_desc;
1645 /* Update HW with number of aggregated Tx descriptors to be sent
1647 * Called only from mvpp2_tx(), so migration is disabled, using
1648 * smp_processor_id() is OK.
1650 static void mvpp2_aggr_txq_pend_desc_add(struct mvpp2_port *port, int pending)
1652 /* aggregated access - relevant TXQ number is written in TX desc */
1653 mvpp2_thread_write(port->priv,
1654 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
1655 MVPP2_AGGR_TXQ_UPDATE_REG, pending);
1658 /* Check if there are enough free descriptors in aggregated txq.
1659 * If not, update the number of occupied descriptors and repeat the check.
1661 * Called only from mvpp2_tx(), so migration is disabled, using
1662 * smp_processor_id() is OK.
1664 static int mvpp2_aggr_desc_num_check(struct mvpp2_port *port,
1665 struct mvpp2_tx_queue *aggr_txq, int num)
1667 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE) {
1668 /* Update number of occupied aggregated Tx descriptors */
1669 unsigned int thread =
1670 mvpp2_cpu_to_thread(port->priv, smp_processor_id());
1671 u32 val = mvpp2_read_relaxed(port->priv,
1672 MVPP2_AGGR_TXQ_STATUS_REG(thread));
1674 aggr_txq->count = val & MVPP2_AGGR_TXQ_PENDING_MASK;
1676 if ((aggr_txq->count + num) > MVPP2_AGGR_TXQ_SIZE)
1682 /* Reserved Tx descriptors allocation request
1684 * Called only from mvpp2_txq_reserved_desc_num_proc(), itself called
1685 * only by mvpp2_tx(), so migration is disabled, using
1686 * smp_processor_id() is OK.
1688 static int mvpp2_txq_alloc_reserved_desc(struct mvpp2_port *port,
1689 struct mvpp2_tx_queue *txq, int num)
1691 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
1692 struct mvpp2 *priv = port->priv;
1695 val = (txq->id << MVPP2_TXQ_RSVD_REQ_Q_OFFSET) | num;
1696 mvpp2_thread_write_relaxed(priv, thread, MVPP2_TXQ_RSVD_REQ_REG, val);
1698 val = mvpp2_thread_read_relaxed(priv, thread, MVPP2_TXQ_RSVD_RSLT_REG);
1700 return val & MVPP2_TXQ_RSVD_RSLT_MASK;
1703 /* Check if there are enough reserved descriptors for transmission.
1704 * If not, request chunk of reserved descriptors and check again.
1706 static int mvpp2_txq_reserved_desc_num_proc(struct mvpp2_port *port,
1707 struct mvpp2_tx_queue *txq,
1708 struct mvpp2_txq_pcpu *txq_pcpu,
1711 int req, desc_count;
1712 unsigned int thread;
1714 if (txq_pcpu->reserved_num >= num)
1717 /* Not enough descriptors reserved! Update the reserved descriptor
1718 * count and check again.
1722 /* Compute total of used descriptors */
1723 for (thread = 0; thread < port->priv->nthreads; thread++) {
1724 struct mvpp2_txq_pcpu *txq_pcpu_aux;
1726 txq_pcpu_aux = per_cpu_ptr(txq->pcpu, thread);
1727 desc_count += txq_pcpu_aux->count;
1728 desc_count += txq_pcpu_aux->reserved_num;
1731 req = max(MVPP2_CPU_DESC_CHUNK, num - txq_pcpu->reserved_num);
1735 (txq->size - (MVPP2_MAX_THREADS * MVPP2_CPU_DESC_CHUNK)))
1738 txq_pcpu->reserved_num += mvpp2_txq_alloc_reserved_desc(port, txq, req);
1740 /* OK, the descriptor could have been updated: check again. */
1741 if (txq_pcpu->reserved_num < num)
1746 /* Release the last allocated Tx descriptor. Useful to handle DMA
1747 * mapping failures in the Tx path.
1749 static void mvpp2_txq_desc_put(struct mvpp2_tx_queue *txq)
1751 if (txq->next_desc_to_proc == 0)
1752 txq->next_desc_to_proc = txq->last_desc - 1;
1754 txq->next_desc_to_proc--;
1757 /* Set Tx descriptors fields relevant for CSUM calculation */
1758 static u32 mvpp2_txq_desc_csum(int l3_offs, __be16 l3_proto,
1759 int ip_hdr_len, int l4_proto)
1763 /* fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1764 * G_L4_chk, L4_type required only for checksum calculation
1766 command = (l3_offs << MVPP2_TXD_L3_OFF_SHIFT);
1767 command |= (ip_hdr_len << MVPP2_TXD_IP_HLEN_SHIFT);
1768 command |= MVPP2_TXD_IP_CSUM_DISABLE;
1770 if (l3_proto == htons(ETH_P_IP)) {
1771 command &= ~MVPP2_TXD_IP_CSUM_DISABLE; /* enable IPv4 csum */
1772 command &= ~MVPP2_TXD_L3_IP6; /* enable IPv4 */
1774 command |= MVPP2_TXD_L3_IP6; /* enable IPv6 */
1777 if (l4_proto == IPPROTO_TCP) {
1778 command &= ~MVPP2_TXD_L4_UDP; /* enable TCP */
1779 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
1780 } else if (l4_proto == IPPROTO_UDP) {
1781 command |= MVPP2_TXD_L4_UDP; /* enable UDP */
1782 command &= ~MVPP2_TXD_L4_CSUM_FRAG; /* generate L4 csum */
1784 command |= MVPP2_TXD_L4_CSUM_NOT;
1790 /* Get number of sent descriptors and decrement counter.
1791 * The number of sent descriptors is returned.
1794 * Called only from mvpp2_txq_done(), called from mvpp2_tx()
1795 * (migration disabled) and from the TX completion tasklet (migration
1796 * disabled) so using smp_processor_id() is OK.
1798 static inline int mvpp2_txq_sent_desc_proc(struct mvpp2_port *port,
1799 struct mvpp2_tx_queue *txq)
1803 /* Reading status reg resets transmitted descriptor counter */
1804 val = mvpp2_thread_read_relaxed(port->priv,
1805 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
1806 MVPP2_TXQ_SENT_REG(txq->id));
1808 return (val & MVPP2_TRANSMITTED_COUNT_MASK) >>
1809 MVPP2_TRANSMITTED_COUNT_OFFSET;
1812 /* Called through on_each_cpu(), so runs on all CPUs, with migration
1813 * disabled, therefore using smp_processor_id() is OK.
1815 static void mvpp2_txq_sent_counter_clear(void *arg)
1817 struct mvpp2_port *port = arg;
1820 /* If the thread isn't used, don't do anything */
1821 if (smp_processor_id() > port->priv->nthreads)
1824 for (queue = 0; queue < port->ntxqs; queue++) {
1825 int id = port->txqs[queue]->id;
1827 mvpp2_thread_read(port->priv,
1828 mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
1829 MVPP2_TXQ_SENT_REG(id));
1833 /* Set max sizes for Tx queues */
1834 static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
1837 int txq, tx_port_num;
1839 mtu = port->pkt_size * 8;
1840 if (mtu > MVPP2_TXP_MTU_MAX)
1841 mtu = MVPP2_TXP_MTU_MAX;
1843 /* WA for wrong Token bucket update: Set MTU value = 3*real MTU value */
1846 /* Indirect access to registers */
1847 tx_port_num = mvpp2_egress_port(port);
1848 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
1851 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_MTU_REG);
1852 val &= ~MVPP2_TXP_MTU_MAX;
1854 mvpp2_write(port->priv, MVPP2_TXP_SCHED_MTU_REG, val);
1856 /* TXP token size and all TXQs token size must be larger that MTU */
1857 val = mvpp2_read(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG);
1858 size = val & MVPP2_TXP_TOKEN_SIZE_MAX;
1861 val &= ~MVPP2_TXP_TOKEN_SIZE_MAX;
1863 mvpp2_write(port->priv, MVPP2_TXP_SCHED_TOKEN_SIZE_REG, val);
1866 for (txq = 0; txq < port->ntxqs; txq++) {
1867 val = mvpp2_read(port->priv,
1868 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq));
1869 size = val & MVPP2_TXQ_TOKEN_SIZE_MAX;
1873 val &= ~MVPP2_TXQ_TOKEN_SIZE_MAX;
1875 mvpp2_write(port->priv,
1876 MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq),
1882 /* Set the number of packets that will be received before Rx interrupt
1883 * will be generated by HW.
1885 static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
1886 struct mvpp2_rx_queue *rxq)
1888 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
1890 if (rxq->pkts_coal > MVPP2_OCCUPIED_THRESH_MASK)
1891 rxq->pkts_coal = MVPP2_OCCUPIED_THRESH_MASK;
1893 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
1894 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_THRESH_REG,
1900 /* For some reason in the LSP this is done on each CPU. Why ? */
1901 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
1902 struct mvpp2_tx_queue *txq)
1904 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
1907 if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
1908 txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
1910 val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
1911 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
1912 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);
1917 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)
1919 u64 tmp = (u64)clk_hz * usec;
1921 do_div(tmp, USEC_PER_SEC);
1923 return tmp > U32_MAX ? U32_MAX : tmp;
1926 static u32 mvpp2_cycles_to_usec(u32 cycles, unsigned long clk_hz)
1928 u64 tmp = (u64)cycles * USEC_PER_SEC;
1930 do_div(tmp, clk_hz);
1932 return tmp > U32_MAX ? U32_MAX : tmp;
1935 /* Set the time delay in usec before Rx interrupt */
1936 static void mvpp2_rx_time_coal_set(struct mvpp2_port *port,
1937 struct mvpp2_rx_queue *rxq)
1939 unsigned long freq = port->priv->tclk;
1940 u32 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
1942 if (val > MVPP2_MAX_ISR_RX_THRESHOLD) {
1944 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_RX_THRESHOLD, freq);
1946 /* re-evaluate to get actual register value */
1947 val = mvpp2_usec_to_cycles(rxq->time_coal, freq);
1950 mvpp2_write(port->priv, MVPP2_ISR_RX_THRESHOLD_REG(rxq->id), val);
1953 static void mvpp2_tx_time_coal_set(struct mvpp2_port *port)
1955 unsigned long freq = port->priv->tclk;
1956 u32 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
1958 if (val > MVPP2_MAX_ISR_TX_THRESHOLD) {
1959 port->tx_time_coal =
1960 mvpp2_cycles_to_usec(MVPP2_MAX_ISR_TX_THRESHOLD, freq);
1962 /* re-evaluate to get actual register value */
1963 val = mvpp2_usec_to_cycles(port->tx_time_coal, freq);
1966 mvpp2_write(port->priv, MVPP2_ISR_TX_THRESHOLD_REG(port->id), val);
1969 /* Free Tx queue skbuffs */
1970 static void mvpp2_txq_bufs_free(struct mvpp2_port *port,
1971 struct mvpp2_tx_queue *txq,
1972 struct mvpp2_txq_pcpu *txq_pcpu, int num)
1976 for (i = 0; i < num; i++) {
1977 struct mvpp2_txq_pcpu_buf *tx_buf =
1978 txq_pcpu->buffs + txq_pcpu->txq_get_index;
1980 if (!IS_TSO_HEADER(txq_pcpu, tx_buf->dma))
1981 dma_unmap_single(port->dev->dev.parent, tx_buf->dma,
1982 tx_buf->size, DMA_TO_DEVICE);
1984 dev_kfree_skb_any(tx_buf->skb);
1986 mvpp2_txq_inc_get(txq_pcpu);
1990 static inline struct mvpp2_rx_queue *mvpp2_get_rx_queue(struct mvpp2_port *port,
1993 int queue = fls(cause) - 1;
1995 return port->rxqs[queue];
1998 static inline struct mvpp2_tx_queue *mvpp2_get_tx_queue(struct mvpp2_port *port,
2001 int queue = fls(cause) - 1;
2003 return port->txqs[queue];
2006 /* Handle end of transmission */
2007 static void mvpp2_txq_done(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
2008 struct mvpp2_txq_pcpu *txq_pcpu)
2010 struct netdev_queue *nq = netdev_get_tx_queue(port->dev, txq->log_id);
2013 if (txq_pcpu->thread != mvpp2_cpu_to_thread(port->priv, smp_processor_id()))
2014 netdev_err(port->dev, "wrong cpu on the end of Tx processing\n");
2016 tx_done = mvpp2_txq_sent_desc_proc(port, txq);
2019 mvpp2_txq_bufs_free(port, txq, txq_pcpu, tx_done);
2021 txq_pcpu->count -= tx_done;
2023 if (netif_tx_queue_stopped(nq))
2024 if (txq_pcpu->count <= txq_pcpu->wake_threshold)
2025 netif_tx_wake_queue(nq);
2028 static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,
2029 unsigned int thread)
2031 struct mvpp2_tx_queue *txq;
2032 struct mvpp2_txq_pcpu *txq_pcpu;
2033 unsigned int tx_todo = 0;
2036 txq = mvpp2_get_tx_queue(port, cause);
2040 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2042 if (txq_pcpu->count) {
2043 mvpp2_txq_done(port, txq, txq_pcpu);
2044 tx_todo += txq_pcpu->count;
2047 cause &= ~(1 << txq->log_id);
2052 /* Rx/Tx queue initialization/cleanup methods */
2054 /* Allocate and initialize descriptors for aggr TXQ */
2055 static int mvpp2_aggr_txq_init(struct platform_device *pdev,
2056 struct mvpp2_tx_queue *aggr_txq,
2057 unsigned int thread, struct mvpp2 *priv)
2061 /* Allocate memory for TX descriptors */
2062 aggr_txq->descs = dma_zalloc_coherent(&pdev->dev,
2063 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
2064 &aggr_txq->descs_dma, GFP_KERNEL);
2065 if (!aggr_txq->descs)
2068 aggr_txq->last_desc = MVPP2_AGGR_TXQ_SIZE - 1;
2070 /* Aggr TXQ no reset WA */
2071 aggr_txq->next_desc_to_proc = mvpp2_read(priv,
2072 MVPP2_AGGR_TXQ_INDEX_REG(thread));
2074 /* Set Tx descriptors queue starting address indirect
2077 if (priv->hw_version == MVPP21)
2078 txq_dma = aggr_txq->descs_dma;
2080 txq_dma = aggr_txq->descs_dma >>
2081 MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
2083 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(thread), txq_dma);
2084 mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(thread),
2085 MVPP2_AGGR_TXQ_SIZE);
2090 /* Create a specified Rx queue */
2091 static int mvpp2_rxq_init(struct mvpp2_port *port,
2092 struct mvpp2_rx_queue *rxq)
2095 unsigned int thread;
2098 rxq->size = port->rx_ring_size;
2100 /* Allocate memory for RX descriptors */
2101 rxq->descs = dma_alloc_coherent(port->dev->dev.parent,
2102 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2103 &rxq->descs_dma, GFP_KERNEL);
2107 rxq->last_desc = rxq->size - 1;
2109 /* Zero occupied and non-occupied counters - direct access */
2110 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2112 /* Set Rx descriptors queue starting address - indirect access */
2113 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2114 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2115 if (port->priv->hw_version == MVPP21)
2116 rxq_dma = rxq->descs_dma;
2118 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
2119 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, rxq_dma);
2120 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
2121 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_INDEX_REG, 0);
2125 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
2127 /* Set coalescing pkts and time */
2128 mvpp2_rx_pkts_coal_set(port, rxq);
2129 mvpp2_rx_time_coal_set(port, rxq);
2131 /* Add number of descriptors ready for receiving packets */
2132 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
2137 /* Push packets received by the RXQ to BM pool */
2138 static void mvpp2_rxq_drop_pkts(struct mvpp2_port *port,
2139 struct mvpp2_rx_queue *rxq)
2143 rx_received = mvpp2_rxq_received(port, rxq->id);
2147 for (i = 0; i < rx_received; i++) {
2148 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
2149 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2152 pool = (status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2153 MVPP2_RXD_BM_POOL_ID_OFFS;
2155 mvpp2_bm_pool_put(port, pool,
2156 mvpp2_rxdesc_dma_addr_get(port, rx_desc),
2157 mvpp2_rxdesc_cookie_get(port, rx_desc));
2159 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
2162 /* Cleanup Rx queue */
2163 static void mvpp2_rxq_deinit(struct mvpp2_port *port,
2164 struct mvpp2_rx_queue *rxq)
2166 unsigned int thread;
2168 mvpp2_rxq_drop_pkts(port, rxq);
2171 dma_free_coherent(port->dev->dev.parent,
2172 rxq->size * MVPP2_DESC_ALIGNED_SIZE,
2178 rxq->next_desc_to_proc = 0;
2181 /* Clear Rx descriptors queue starting address and size;
2182 * free descriptor number
2184 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
2185 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2186 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_NUM_REG, rxq->id);
2187 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_ADDR_REG, 0);
2188 mvpp2_thread_write(port->priv, thread, MVPP2_RXQ_DESC_SIZE_REG, 0);
2192 /* Create and initialize a Tx queue */
2193 static int mvpp2_txq_init(struct mvpp2_port *port,
2194 struct mvpp2_tx_queue *txq)
2197 unsigned int thread;
2198 int desc, desc_per_txq, tx_port_num;
2199 struct mvpp2_txq_pcpu *txq_pcpu;
2201 txq->size = port->tx_ring_size;
2203 /* Allocate memory for Tx descriptors */
2204 txq->descs = dma_alloc_coherent(port->dev->dev.parent,
2205 txq->size * MVPP2_DESC_ALIGNED_SIZE,
2206 &txq->descs_dma, GFP_KERNEL);
2210 txq->last_desc = txq->size - 1;
2212 /* Set Tx descriptors queue starting address - indirect access */
2213 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2214 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2215 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG,
2217 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG,
2218 txq->size & MVPP2_TXQ_DESC_SIZE_MASK);
2219 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_INDEX_REG, 0);
2220 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_RSVD_CLR_REG,
2221 txq->id << MVPP2_TXQ_RSVD_CLR_OFFSET);
2222 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PENDING_REG);
2223 val &= ~MVPP2_TXQ_PENDING_MASK;
2224 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PENDING_REG, val);
2226 /* Calculate base address in prefetch buffer. We reserve 16 descriptors
2227 * for each existing TXQ.
2228 * TCONTS for PON port must be continuous from 0 to MVPP2_MAX_TCONT
2229 * GBE ports assumed to be continuous from 0 to MVPP2_MAX_PORTS
2232 desc = (port->id * MVPP2_MAX_TXQ * desc_per_txq) +
2233 (txq->log_id * desc_per_txq);
2235 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG,
2236 MVPP2_PREF_BUF_PTR(desc) | MVPP2_PREF_BUF_SIZE_16 |
2237 MVPP2_PREF_BUF_THRESH(desc_per_txq / 2));
2240 /* WRR / EJP configuration - indirect access */
2241 tx_port_num = mvpp2_egress_port(port);
2242 mvpp2_write(port->priv, MVPP2_TXP_SCHED_PORT_INDEX_REG, tx_port_num);
2244 val = mvpp2_read(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id));
2245 val &= ~MVPP2_TXQ_REFILL_PERIOD_ALL_MASK;
2246 val |= MVPP2_TXQ_REFILL_PERIOD_MASK(1);
2247 val |= MVPP2_TXQ_REFILL_TOKENS_ALL_MASK;
2248 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_REFILL_REG(txq->log_id), val);
2250 val = MVPP2_TXQ_TOKEN_SIZE_MAX;
2251 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(txq->log_id),
2254 for (thread = 0; thread < port->priv->nthreads; thread++) {
2255 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2256 txq_pcpu->size = txq->size;
2257 txq_pcpu->buffs = kmalloc_array(txq_pcpu->size,
2258 sizeof(*txq_pcpu->buffs),
2260 if (!txq_pcpu->buffs)
2263 txq_pcpu->count = 0;
2264 txq_pcpu->reserved_num = 0;
2265 txq_pcpu->txq_put_index = 0;
2266 txq_pcpu->txq_get_index = 0;
2267 txq_pcpu->tso_headers = NULL;
2269 txq_pcpu->stop_threshold = txq->size - MVPP2_MAX_SKB_DESCS;
2270 txq_pcpu->wake_threshold = txq_pcpu->stop_threshold / 2;
2272 txq_pcpu->tso_headers =
2273 dma_alloc_coherent(port->dev->dev.parent,
2274 txq_pcpu->size * TSO_HEADER_SIZE,
2275 &txq_pcpu->tso_headers_dma,
2277 if (!txq_pcpu->tso_headers)
2284 /* Free allocated TXQ resources */
2285 static void mvpp2_txq_deinit(struct mvpp2_port *port,
2286 struct mvpp2_tx_queue *txq)
2288 struct mvpp2_txq_pcpu *txq_pcpu;
2289 unsigned int thread;
2291 for (thread = 0; thread < port->priv->nthreads; thread++) {
2292 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2293 kfree(txq_pcpu->buffs);
2295 if (txq_pcpu->tso_headers)
2296 dma_free_coherent(port->dev->dev.parent,
2297 txq_pcpu->size * TSO_HEADER_SIZE,
2298 txq_pcpu->tso_headers,
2299 txq_pcpu->tso_headers_dma);
2301 txq_pcpu->tso_headers = NULL;
2305 dma_free_coherent(port->dev->dev.parent,
2306 txq->size * MVPP2_DESC_ALIGNED_SIZE,
2307 txq->descs, txq->descs_dma);
2311 txq->next_desc_to_proc = 0;
2314 /* Set minimum bandwidth for disabled TXQs */
2315 mvpp2_write(port->priv, MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(txq->id), 0);
2317 /* Set Tx descriptors queue starting address and size */
2318 thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2319 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2320 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_ADDR_REG, 0);
2321 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_DESC_SIZE_REG, 0);
2325 /* Cleanup Tx ports */
2326 static void mvpp2_txq_clean(struct mvpp2_port *port, struct mvpp2_tx_queue *txq)
2328 struct mvpp2_txq_pcpu *txq_pcpu;
2330 unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
2333 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
2334 val = mvpp2_thread_read(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG);
2335 val |= MVPP2_TXQ_DRAIN_EN_MASK;
2336 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
2338 /* The napi queue has been stopped so wait for all packets
2339 * to be transmitted.
2343 if (delay >= MVPP2_TX_PENDING_TIMEOUT_MSEC) {
2344 netdev_warn(port->dev,
2345 "port %d: cleaning queue %d timed out\n",
2346 port->id, txq->log_id);
2352 pending = mvpp2_thread_read(port->priv, thread,
2353 MVPP2_TXQ_PENDING_REG);
2354 pending &= MVPP2_TXQ_PENDING_MASK;
2357 val &= ~MVPP2_TXQ_DRAIN_EN_MASK;
2358 mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_PREF_BUF_REG, val);
2361 for (thread = 0; thread < port->priv->nthreads; thread++) {
2362 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2364 /* Release all packets */
2365 mvpp2_txq_bufs_free(port, txq, txq_pcpu, txq_pcpu->count);
2368 txq_pcpu->count = 0;
2369 txq_pcpu->txq_put_index = 0;
2370 txq_pcpu->txq_get_index = 0;
2374 /* Cleanup all Tx queues */
2375 static void mvpp2_cleanup_txqs(struct mvpp2_port *port)
2377 struct mvpp2_tx_queue *txq;
2381 val = mvpp2_read(port->priv, MVPP2_TX_PORT_FLUSH_REG);
2383 /* Reset Tx ports and delete Tx queues */
2384 val |= MVPP2_TX_PORT_FLUSH_MASK(port->id);
2385 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2387 for (queue = 0; queue < port->ntxqs; queue++) {
2388 txq = port->txqs[queue];
2389 mvpp2_txq_clean(port, txq);
2390 mvpp2_txq_deinit(port, txq);
2393 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2395 val &= ~MVPP2_TX_PORT_FLUSH_MASK(port->id);
2396 mvpp2_write(port->priv, MVPP2_TX_PORT_FLUSH_REG, val);
2399 /* Cleanup all Rx queues */
2400 static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
2404 for (queue = 0; queue < port->nrxqs; queue++)
2405 mvpp2_rxq_deinit(port, port->rxqs[queue]);
2408 /* Init all Rx queues for port */
2409 static int mvpp2_setup_rxqs(struct mvpp2_port *port)
2413 for (queue = 0; queue < port->nrxqs; queue++) {
2414 err = mvpp2_rxq_init(port, port->rxqs[queue]);
2421 mvpp2_cleanup_rxqs(port);
2425 /* Init all tx queues for port */
2426 static int mvpp2_setup_txqs(struct mvpp2_port *port)
2428 struct mvpp2_tx_queue *txq;
2429 int queue, err, cpu;
2431 for (queue = 0; queue < port->ntxqs; queue++) {
2432 txq = port->txqs[queue];
2433 err = mvpp2_txq_init(port, txq);
2437 /* Assign this queue to a CPU */
2438 cpu = queue % num_present_cpus();
2439 netif_set_xps_queue(port->dev, cpumask_of(cpu), queue);
2442 if (port->has_tx_irqs) {
2443 mvpp2_tx_time_coal_set(port);
2444 for (queue = 0; queue < port->ntxqs; queue++) {
2445 txq = port->txqs[queue];
2446 mvpp2_tx_pkts_coal_set(port, txq);
2450 on_each_cpu(mvpp2_txq_sent_counter_clear, port, 1);
2454 mvpp2_cleanup_txqs(port);
2458 /* The callback for per-port interrupt */
2459 static irqreturn_t mvpp2_isr(int irq, void *dev_id)
2461 struct mvpp2_queue_vector *qv = dev_id;
2463 mvpp2_qvec_interrupt_disable(qv);
2465 napi_schedule(&qv->napi);
2470 /* Per-port interrupt for link status changes */
2471 static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
2473 struct mvpp2_port *port = (struct mvpp2_port *)dev_id;
2474 struct net_device *dev = port->dev;
2475 bool event = false, link = false;
2478 mvpp22_gop_mask_irq(port);
2480 if (port->gop_id == 0 &&
2481 port->phy_interface == PHY_INTERFACE_MODE_10GKR) {
2482 val = readl(port->base + MVPP22_XLG_INT_STAT);
2483 if (val & MVPP22_XLG_INT_STAT_LINK) {
2485 val = readl(port->base + MVPP22_XLG_STATUS);
2486 if (val & MVPP22_XLG_STATUS_LINK_UP)
2489 } else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
2490 port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
2491 port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
2492 port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
2493 val = readl(port->base + MVPP22_GMAC_INT_STAT);
2494 if (val & MVPP22_GMAC_INT_STAT_LINK) {
2496 val = readl(port->base + MVPP2_GMAC_STATUS0);
2497 if (val & MVPP2_GMAC_STATUS0_LINK_UP)
2502 if (port->phylink) {
2503 phylink_mac_change(port->phylink, link);
2507 if (!netif_running(dev) || !event)
2511 mvpp2_interrupts_enable(port);
2513 mvpp2_egress_enable(port);
2514 mvpp2_ingress_enable(port);
2515 netif_carrier_on(dev);
2516 netif_tx_wake_all_queues(dev);
2518 netif_tx_stop_all_queues(dev);
2519 netif_carrier_off(dev);
2520 mvpp2_ingress_disable(port);
2521 mvpp2_egress_disable(port);
2523 mvpp2_interrupts_disable(port);
2527 mvpp22_gop_unmask_irq(port);
2531 static void mvpp2_timer_set(struct mvpp2_port_pcpu *port_pcpu)
2535 if (!port_pcpu->timer_scheduled) {
2536 port_pcpu->timer_scheduled = true;
2537 interval = MVPP2_TXDONE_HRTIMER_PERIOD_NS;
2538 hrtimer_start(&port_pcpu->tx_done_timer, interval,
2539 HRTIMER_MODE_REL_PINNED);
2543 static void mvpp2_tx_proc_cb(unsigned long data)
2545 struct net_device *dev = (struct net_device *)data;
2546 struct mvpp2_port *port = netdev_priv(dev);
2547 struct mvpp2_port_pcpu *port_pcpu;
2548 unsigned int tx_todo, cause;
2550 port_pcpu = per_cpu_ptr(port->pcpu,
2551 mvpp2_cpu_to_thread(port->priv, smp_processor_id()));
2553 if (!netif_running(dev))
2555 port_pcpu->timer_scheduled = false;
2557 /* Process all the Tx queues */
2558 cause = (1 << port->ntxqs) - 1;
2559 tx_todo = mvpp2_tx_done(port, cause,
2560 mvpp2_cpu_to_thread(port->priv, smp_processor_id()));
2562 /* Set the timer in case not all the packets were processed */
2564 mvpp2_timer_set(port_pcpu);
2567 static enum hrtimer_restart mvpp2_hr_timer_cb(struct hrtimer *timer)
2569 struct mvpp2_port_pcpu *port_pcpu = container_of(timer,
2570 struct mvpp2_port_pcpu,
2573 tasklet_schedule(&port_pcpu->tx_done_tasklet);
2575 return HRTIMER_NORESTART;
2578 /* Main RX/TX processing routines */
2580 /* Display more error info */
2581 static void mvpp2_rx_error(struct mvpp2_port *port,
2582 struct mvpp2_rx_desc *rx_desc)
2584 u32 status = mvpp2_rxdesc_status_get(port, rx_desc);
2585 size_t sz = mvpp2_rxdesc_size_get(port, rx_desc);
2586 char *err_str = NULL;
2588 switch (status & MVPP2_RXD_ERR_CODE_MASK) {
2589 case MVPP2_RXD_ERR_CRC:
2592 case MVPP2_RXD_ERR_OVERRUN:
2593 err_str = "overrun";
2595 case MVPP2_RXD_ERR_RESOURCE:
2596 err_str = "resource";
2599 if (err_str && net_ratelimit())
2600 netdev_err(port->dev,
2601 "bad rx status %08x (%s error), size=%zu\n",
2602 status, err_str, sz);
2605 /* Handle RX checksum offload */
2606 static void mvpp2_rx_csum(struct mvpp2_port *port, u32 status,
2607 struct sk_buff *skb)
2609 if (((status & MVPP2_RXD_L3_IP4) &&
2610 !(status & MVPP2_RXD_IP4_HEADER_ERR)) ||
2611 (status & MVPP2_RXD_L3_IP6))
2612 if (((status & MVPP2_RXD_L4_UDP) ||
2613 (status & MVPP2_RXD_L4_TCP)) &&
2614 (status & MVPP2_RXD_L4_CSUM_OK)) {
2616 skb->ip_summed = CHECKSUM_UNNECESSARY;
2620 skb->ip_summed = CHECKSUM_NONE;
2623 /* Reuse skb if possible, or allocate a new skb and add it to BM pool */
2624 static int mvpp2_rx_refill(struct mvpp2_port *port,
2625 struct mvpp2_bm_pool *bm_pool, int pool)
2627 dma_addr_t dma_addr;
2628 phys_addr_t phys_addr;
2631 /* No recycle or too many buffers are in use, so allocate a new skb */
2632 buf = mvpp2_buf_alloc(port, bm_pool, &dma_addr, &phys_addr,
2637 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2642 /* Handle tx checksum */
2643 static u32 mvpp2_skb_tx_csum(struct mvpp2_port *port, struct sk_buff *skb)
2645 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2648 __be16 l3_proto = vlan_get_protocol(skb);
2650 if (l3_proto == htons(ETH_P_IP)) {
2651 struct iphdr *ip4h = ip_hdr(skb);
2653 /* Calculate IPv4 checksum and L4 checksum */
2654 ip_hdr_len = ip4h->ihl;
2655 l4_proto = ip4h->protocol;
2656 } else if (l3_proto == htons(ETH_P_IPV6)) {
2657 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2659 /* Read l4_protocol from one of IPv6 extra headers */
2660 if (skb_network_header_len(skb) > 0)
2661 ip_hdr_len = (skb_network_header_len(skb) >> 2);
2662 l4_proto = ip6h->nexthdr;
2664 return MVPP2_TXD_L4_CSUM_NOT;
2667 return mvpp2_txq_desc_csum(skb_network_offset(skb),
2668 l3_proto, ip_hdr_len, l4_proto);
2671 return MVPP2_TXD_L4_CSUM_NOT | MVPP2_TXD_IP_CSUM_DISABLE;
2674 /* Main rx processing */
2675 static int mvpp2_rx(struct mvpp2_port *port, struct napi_struct *napi,
2676 int rx_todo, struct mvpp2_rx_queue *rxq)
2678 struct net_device *dev = port->dev;
2684 /* Get number of received packets and clamp the to-do */
2685 rx_received = mvpp2_rxq_received(port, rxq->id);
2686 if (rx_todo > rx_received)
2687 rx_todo = rx_received;
2689 while (rx_done < rx_todo) {
2690 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
2691 struct mvpp2_bm_pool *bm_pool;
2692 struct sk_buff *skb;
2693 unsigned int frag_size;
2694 dma_addr_t dma_addr;
2695 phys_addr_t phys_addr;
2697 int pool, rx_bytes, err;
2701 rx_status = mvpp2_rxdesc_status_get(port, rx_desc);
2702 rx_bytes = mvpp2_rxdesc_size_get(port, rx_desc);
2703 rx_bytes -= MVPP2_MH_SIZE;
2704 dma_addr = mvpp2_rxdesc_dma_addr_get(port, rx_desc);
2705 phys_addr = mvpp2_rxdesc_cookie_get(port, rx_desc);
2706 data = (void *)phys_to_virt(phys_addr);
2708 pool = (rx_status & MVPP2_RXD_BM_POOL_ID_MASK) >>
2709 MVPP2_RXD_BM_POOL_ID_OFFS;
2710 bm_pool = &port->priv->bm_pools[pool];
2712 /* In case of an error, release the requested buffer pointer
2713 * to the Buffer Manager. This request process is controlled
2714 * by the hardware, and the information about the buffer is
2715 * comprised by the RX descriptor.
2717 if (rx_status & MVPP2_RXD_ERR_SUMMARY) {
2719 dev->stats.rx_errors++;
2720 mvpp2_rx_error(port, rx_desc);
2721 /* Return the buffer to the pool */
2722 mvpp2_bm_pool_put(port, pool, dma_addr, phys_addr);
2726 if (bm_pool->frag_size > PAGE_SIZE)
2729 frag_size = bm_pool->frag_size;
2731 skb = build_skb(data, frag_size);
2733 netdev_warn(port->dev, "skb build failed\n");
2734 goto err_drop_frame;
2737 err = mvpp2_rx_refill(port, bm_pool, pool);
2739 netdev_err(port->dev, "failed to refill BM pools\n");
2740 goto err_drop_frame;
2743 dma_unmap_single(dev->dev.parent, dma_addr,
2744 bm_pool->buf_size, DMA_FROM_DEVICE);
2747 rcvd_bytes += rx_bytes;
2749 skb_reserve(skb, MVPP2_MH_SIZE + NET_SKB_PAD);
2750 skb_put(skb, rx_bytes);
2751 skb->protocol = eth_type_trans(skb, dev);
2752 mvpp2_rx_csum(port, rx_status, skb);
2754 napi_gro_receive(napi, skb);
2758 struct mvpp2_pcpu_stats *stats = this_cpu_ptr(port->stats);
2760 u64_stats_update_begin(&stats->syncp);
2761 stats->rx_packets += rcvd_pkts;
2762 stats->rx_bytes += rcvd_bytes;
2763 u64_stats_update_end(&stats->syncp);
2766 /* Update Rx queue management counters */
2768 mvpp2_rxq_status_update(port, rxq->id, rx_done, rx_done);
2774 tx_desc_unmap_put(struct mvpp2_port *port, struct mvpp2_tx_queue *txq,
2775 struct mvpp2_tx_desc *desc)
2777 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2778 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2780 dma_addr_t buf_dma_addr =
2781 mvpp2_txdesc_dma_addr_get(port, desc);
2783 mvpp2_txdesc_size_get(port, desc);
2784 if (!IS_TSO_HEADER(txq_pcpu, buf_dma_addr))
2785 dma_unmap_single(port->dev->dev.parent, buf_dma_addr,
2786 buf_sz, DMA_TO_DEVICE);
2787 mvpp2_txq_desc_put(txq);
2790 /* Handle tx fragmentation processing */
2791 static int mvpp2_tx_frag_process(struct mvpp2_port *port, struct sk_buff *skb,
2792 struct mvpp2_tx_queue *aggr_txq,
2793 struct mvpp2_tx_queue *txq)
2795 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2796 struct mvpp2_txq_pcpu *txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2797 struct mvpp2_tx_desc *tx_desc;
2799 dma_addr_t buf_dma_addr;
2801 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2802 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2803 void *addr = page_address(frag->page.p) + frag->page_offset;
2805 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2806 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2807 mvpp2_txdesc_size_set(port, tx_desc, frag->size);
2809 buf_dma_addr = dma_map_single(port->dev->dev.parent, addr,
2810 frag->size, DMA_TO_DEVICE);
2811 if (dma_mapping_error(port->dev->dev.parent, buf_dma_addr)) {
2812 mvpp2_txq_desc_put(txq);
2816 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
2818 if (i == (skb_shinfo(skb)->nr_frags - 1)) {
2819 /* Last descriptor */
2820 mvpp2_txdesc_cmd_set(port, tx_desc,
2822 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
2824 /* Descriptor in the middle: Not First, Not Last */
2825 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
2826 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2832 /* Release all descriptors that were used to map fragments of
2833 * this packet, as well as the corresponding DMA mappings
2835 for (i = i - 1; i >= 0; i--) {
2836 tx_desc = txq->descs + i;
2837 tx_desc_unmap_put(port, txq, tx_desc);
2843 static inline void mvpp2_tso_put_hdr(struct sk_buff *skb,
2844 struct net_device *dev,
2845 struct mvpp2_tx_queue *txq,
2846 struct mvpp2_tx_queue *aggr_txq,
2847 struct mvpp2_txq_pcpu *txq_pcpu,
2850 struct mvpp2_port *port = netdev_priv(dev);
2851 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2854 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2855 mvpp2_txdesc_size_set(port, tx_desc, hdr_sz);
2857 addr = txq_pcpu->tso_headers_dma +
2858 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
2859 mvpp2_txdesc_dma_addr_set(port, tx_desc, addr);
2861 mvpp2_txdesc_cmd_set(port, tx_desc, mvpp2_skb_tx_csum(port, skb) |
2863 MVPP2_TXD_PADDING_DISABLE);
2864 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2867 static inline int mvpp2_tso_put_data(struct sk_buff *skb,
2868 struct net_device *dev, struct tso_t *tso,
2869 struct mvpp2_tx_queue *txq,
2870 struct mvpp2_tx_queue *aggr_txq,
2871 struct mvpp2_txq_pcpu *txq_pcpu,
2872 int sz, bool left, bool last)
2874 struct mvpp2_port *port = netdev_priv(dev);
2875 struct mvpp2_tx_desc *tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2876 dma_addr_t buf_dma_addr;
2878 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2879 mvpp2_txdesc_size_set(port, tx_desc, sz);
2881 buf_dma_addr = dma_map_single(dev->dev.parent, tso->data, sz,
2883 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
2884 mvpp2_txq_desc_put(txq);
2888 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
2891 mvpp2_txdesc_cmd_set(port, tx_desc, MVPP2_TXD_L_DESC);
2893 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
2897 mvpp2_txdesc_cmd_set(port, tx_desc, 0);
2900 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
2904 static int mvpp2_tx_tso(struct sk_buff *skb, struct net_device *dev,
2905 struct mvpp2_tx_queue *txq,
2906 struct mvpp2_tx_queue *aggr_txq,
2907 struct mvpp2_txq_pcpu *txq_pcpu)
2909 struct mvpp2_port *port = netdev_priv(dev);
2911 int hdr_sz = skb_transport_offset(skb) + tcp_hdrlen(skb);
2912 int i, len, descs = 0;
2914 /* Check number of available descriptors */
2915 if (mvpp2_aggr_desc_num_check(port, aggr_txq, tso_count_descs(skb)) ||
2916 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu,
2917 tso_count_descs(skb)))
2920 tso_start(skb, &tso);
2921 len = skb->len - hdr_sz;
2923 int left = min_t(int, skb_shinfo(skb)->gso_size, len);
2924 char *hdr = txq_pcpu->tso_headers +
2925 txq_pcpu->txq_put_index * TSO_HEADER_SIZE;
2930 tso_build_hdr(skb, hdr, &tso, left, len == 0);
2931 mvpp2_tso_put_hdr(skb, dev, txq, aggr_txq, txq_pcpu, hdr_sz);
2934 int sz = min_t(int, tso.size, left);
2938 if (mvpp2_tso_put_data(skb, dev, &tso, txq, aggr_txq,
2939 txq_pcpu, sz, left, len == 0))
2941 tso_build_data(skb, &tso, sz);
2948 for (i = descs - 1; i >= 0; i--) {
2949 struct mvpp2_tx_desc *tx_desc = txq->descs + i;
2950 tx_desc_unmap_put(port, txq, tx_desc);
2955 /* Main tx processing */
2956 static netdev_tx_t mvpp2_tx(struct sk_buff *skb, struct net_device *dev)
2958 struct mvpp2_port *port = netdev_priv(dev);
2959 struct mvpp2_tx_queue *txq, *aggr_txq;
2960 struct mvpp2_txq_pcpu *txq_pcpu;
2961 struct mvpp2_tx_desc *tx_desc;
2962 dma_addr_t buf_dma_addr;
2963 unsigned long flags = 0;
2964 unsigned int thread;
2969 thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
2971 txq_id = skb_get_queue_mapping(skb);
2972 txq = port->txqs[txq_id];
2973 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
2974 aggr_txq = &port->priv->aggr_txqs[thread];
2976 if (test_bit(thread, &port->priv->lock_map))
2977 spin_lock_irqsave(&port->tx_lock[thread], flags);
2979 if (skb_is_gso(skb)) {
2980 frags = mvpp2_tx_tso(skb, dev, txq, aggr_txq, txq_pcpu);
2983 frags = skb_shinfo(skb)->nr_frags + 1;
2985 /* Check number of available descriptors */
2986 if (mvpp2_aggr_desc_num_check(port, aggr_txq, frags) ||
2987 mvpp2_txq_reserved_desc_num_proc(port, txq, txq_pcpu, frags)) {
2992 /* Get a descriptor for the first part of the packet */
2993 tx_desc = mvpp2_txq_next_desc_get(aggr_txq);
2994 mvpp2_txdesc_txq_set(port, tx_desc, txq->id);
2995 mvpp2_txdesc_size_set(port, tx_desc, skb_headlen(skb));
2997 buf_dma_addr = dma_map_single(dev->dev.parent, skb->data,
2998 skb_headlen(skb), DMA_TO_DEVICE);
2999 if (unlikely(dma_mapping_error(dev->dev.parent, buf_dma_addr))) {
3000 mvpp2_txq_desc_put(txq);
3005 mvpp2_txdesc_dma_addr_set(port, tx_desc, buf_dma_addr);
3007 tx_cmd = mvpp2_skb_tx_csum(port, skb);
3010 /* First and Last descriptor */
3011 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_L_DESC;
3012 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3013 mvpp2_txq_inc_put(port, txq_pcpu, skb, tx_desc);
3015 /* First but not Last */
3016 tx_cmd |= MVPP2_TXD_F_DESC | MVPP2_TXD_PADDING_DISABLE;
3017 mvpp2_txdesc_cmd_set(port, tx_desc, tx_cmd);
3018 mvpp2_txq_inc_put(port, txq_pcpu, NULL, tx_desc);
3020 /* Continue with other skb fragments */
3021 if (mvpp2_tx_frag_process(port, skb, aggr_txq, txq)) {
3022 tx_desc_unmap_put(port, txq, tx_desc);
3029 struct mvpp2_pcpu_stats *stats = per_cpu_ptr(port->stats, thread);
3030 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
3032 txq_pcpu->reserved_num -= frags;
3033 txq_pcpu->count += frags;
3034 aggr_txq->count += frags;
3036 /* Enable transmit */
3038 mvpp2_aggr_txq_pend_desc_add(port, frags);
3040 if (txq_pcpu->count >= txq_pcpu->stop_threshold)
3041 netif_tx_stop_queue(nq);
3043 u64_stats_update_begin(&stats->syncp);
3044 stats->tx_packets++;
3045 stats->tx_bytes += skb->len;
3046 u64_stats_update_end(&stats->syncp);
3048 dev->stats.tx_dropped++;
3049 dev_kfree_skb_any(skb);
3052 /* Finalize TX processing */
3053 if (!port->has_tx_irqs && txq_pcpu->count >= txq->done_pkts_coal)
3054 mvpp2_txq_done(port, txq, txq_pcpu);
3056 /* Set the timer in case not all frags were processed */
3057 if (!port->has_tx_irqs && txq_pcpu->count <= frags &&
3058 txq_pcpu->count > 0) {
3059 struct mvpp2_port_pcpu *port_pcpu = per_cpu_ptr(port->pcpu, thread);
3061 mvpp2_timer_set(port_pcpu);
3064 if (test_bit(thread, &port->priv->lock_map))
3065 spin_unlock_irqrestore(&port->tx_lock[thread], flags);
3067 return NETDEV_TX_OK;
3070 static inline void mvpp2_cause_error(struct net_device *dev, int cause)
3072 if (cause & MVPP2_CAUSE_FCS_ERR_MASK)
3073 netdev_err(dev, "FCS error\n");
3074 if (cause & MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK)
3075 netdev_err(dev, "rx fifo overrun error\n");
3076 if (cause & MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK)
3077 netdev_err(dev, "tx fifo underrun error\n");
3080 static int mvpp2_poll(struct napi_struct *napi, int budget)
3082 u32 cause_rx_tx, cause_rx, cause_tx, cause_misc;
3084 struct mvpp2_port *port = netdev_priv(napi->dev);
3085 struct mvpp2_queue_vector *qv;
3086 unsigned int thread = mvpp2_cpu_to_thread(port->priv, smp_processor_id());
3088 qv = container_of(napi, struct mvpp2_queue_vector, napi);
3090 /* Rx/Tx cause register
3092 * Bits 0-15: each bit indicates received packets on the Rx queue
3093 * (bit 0 is for Rx queue 0).
3095 * Bits 16-23: each bit indicates transmitted packets on the Tx queue
3096 * (bit 16 is for Tx queue 0).
3098 * Each CPU has its own Rx/Tx cause register
3100 cause_rx_tx = mvpp2_thread_read_relaxed(port->priv, qv->sw_thread_id,
3101 MVPP2_ISR_RX_TX_CAUSE_REG(port->id));
3103 cause_misc = cause_rx_tx & MVPP2_CAUSE_MISC_SUM_MASK;
3105 mvpp2_cause_error(port->dev, cause_misc);
3107 /* Clear the cause register */
3108 mvpp2_write(port->priv, MVPP2_ISR_MISC_CAUSE_REG, 0);
3109 mvpp2_thread_write(port->priv, thread,
3110 MVPP2_ISR_RX_TX_CAUSE_REG(port->id),
3111 cause_rx_tx & ~MVPP2_CAUSE_MISC_SUM_MASK);
3114 if (port->has_tx_irqs) {
3115 cause_tx = cause_rx_tx & MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
3117 cause_tx >>= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET;
3118 mvpp2_tx_done(port, cause_tx, qv->sw_thread_id);
3122 /* Process RX packets */
3123 cause_rx = cause_rx_tx &
3124 MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
3125 cause_rx <<= qv->first_rxq;
3126 cause_rx |= qv->pending_cause_rx;
3127 while (cause_rx && budget > 0) {
3129 struct mvpp2_rx_queue *rxq;
3131 rxq = mvpp2_get_rx_queue(port, cause_rx);
3135 count = mvpp2_rx(port, napi, budget, rxq);
3139 /* Clear the bit associated to this Rx queue
3140 * so that next iteration will continue from
3141 * the next Rx queue.
3143 cause_rx &= ~(1 << rxq->logic_rxq);
3149 napi_complete_done(napi, rx_done);
3151 mvpp2_qvec_interrupt_enable(qv);
3153 qv->pending_cause_rx = cause_rx;
3157 static void mvpp22_mode_reconfigure(struct mvpp2_port *port)
3161 /* comphy reconfiguration */
3162 mvpp22_comphy_init(port);
3164 /* gop reconfiguration */
3165 mvpp22_gop_init(port);
3167 /* Only GOP port 0 has an XLG MAC */
3168 if (port->gop_id == 0) {
3169 ctrl3 = readl(port->base + MVPP22_XLG_CTRL3_REG);
3170 ctrl3 &= ~MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
3172 if (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
3173 port->phy_interface == PHY_INTERFACE_MODE_10GKR)
3174 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_10G;
3176 ctrl3 |= MVPP22_XLG_CTRL3_MACMODESELECT_GMAC;
3178 writel(ctrl3, port->base + MVPP22_XLG_CTRL3_REG);
3181 if (port->gop_id == 0 &&
3182 (port->phy_interface == PHY_INTERFACE_MODE_XAUI ||
3183 port->phy_interface == PHY_INTERFACE_MODE_10GKR))
3184 mvpp2_xlg_max_rx_size_set(port);
3186 mvpp2_gmac_max_rx_size_set(port);
3189 /* Set hw internals when starting port */
3190 static void mvpp2_start_dev(struct mvpp2_port *port)
3194 mvpp2_txp_max_tx_size_set(port);
3196 for (i = 0; i < port->nqvecs; i++)
3197 napi_enable(&port->qvecs[i].napi);
3199 /* Enable interrupts on all threads */
3200 mvpp2_interrupts_enable(port);
3202 if (port->priv->hw_version == MVPP22)
3203 mvpp22_mode_reconfigure(port);
3205 if (port->phylink) {
3206 phylink_start(port->phylink);
3208 /* Phylink isn't used as of now for ACPI, so the MAC has to be
3209 * configured manually when the interface is started. This will
3210 * be removed as soon as the phylink ACPI support lands in.
3212 struct phylink_link_state state = {
3213 .interface = port->phy_interface,
3215 mvpp2_mac_config(port->dev, MLO_AN_INBAND, &state);
3216 mvpp2_mac_link_up(port->dev, MLO_AN_INBAND, port->phy_interface,
3220 netif_tx_start_all_queues(port->dev);
3223 /* Set hw internals when stopping port */
3224 static void mvpp2_stop_dev(struct mvpp2_port *port)
3228 /* Disable interrupts on all threads */
3229 mvpp2_interrupts_disable(port);
3231 for (i = 0; i < port->nqvecs; i++)
3232 napi_disable(&port->qvecs[i].napi);
3235 phylink_stop(port->phylink);
3236 phy_power_off(port->comphy);
3239 static int mvpp2_check_ringparam_valid(struct net_device *dev,
3240 struct ethtool_ringparam *ring)
3242 u16 new_rx_pending = ring->rx_pending;
3243 u16 new_tx_pending = ring->tx_pending;
3245 if (ring->rx_pending == 0 || ring->tx_pending == 0)
3248 if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
3249 new_rx_pending = MVPP2_MAX_RXD_MAX;
3250 else if (!IS_ALIGNED(ring->rx_pending, 16))
3251 new_rx_pending = ALIGN(ring->rx_pending, 16);
3253 if (ring->tx_pending > MVPP2_MAX_TXD_MAX)
3254 new_tx_pending = MVPP2_MAX_TXD_MAX;
3255 else if (!IS_ALIGNED(ring->tx_pending, 32))
3256 new_tx_pending = ALIGN(ring->tx_pending, 32);
3258 /* The Tx ring size cannot be smaller than the minimum number of
3259 * descriptors needed for TSO.
3261 if (new_tx_pending < MVPP2_MAX_SKB_DESCS)
3262 new_tx_pending = ALIGN(MVPP2_MAX_SKB_DESCS, 32);
3264 if (ring->rx_pending != new_rx_pending) {
3265 netdev_info(dev, "illegal Rx ring size value %d, round to %d\n",
3266 ring->rx_pending, new_rx_pending);
3267 ring->rx_pending = new_rx_pending;
3270 if (ring->tx_pending != new_tx_pending) {
3271 netdev_info(dev, "illegal Tx ring size value %d, round to %d\n",
3272 ring->tx_pending, new_tx_pending);
3273 ring->tx_pending = new_tx_pending;
3279 static void mvpp21_get_mac_address(struct mvpp2_port *port, unsigned char *addr)
3281 u32 mac_addr_l, mac_addr_m, mac_addr_h;
3283 mac_addr_l = readl(port->base + MVPP2_GMAC_CTRL_1_REG);
3284 mac_addr_m = readl(port->priv->lms_base + MVPP2_SRC_ADDR_MIDDLE);
3285 mac_addr_h = readl(port->priv->lms_base + MVPP2_SRC_ADDR_HIGH);
3286 addr[0] = (mac_addr_h >> 24) & 0xFF;
3287 addr[1] = (mac_addr_h >> 16) & 0xFF;
3288 addr[2] = (mac_addr_h >> 8) & 0xFF;
3289 addr[3] = mac_addr_h & 0xFF;
3290 addr[4] = mac_addr_m & 0xFF;
3291 addr[5] = (mac_addr_l >> MVPP2_GMAC_SA_LOW_OFFS) & 0xFF;
3294 static int mvpp2_irqs_init(struct mvpp2_port *port)
3298 for (i = 0; i < port->nqvecs; i++) {
3299 struct mvpp2_queue_vector *qv = port->qvecs + i;
3301 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
3302 qv->mask = kzalloc(cpumask_size(), GFP_KERNEL);
3308 irq_set_status_flags(qv->irq, IRQ_NO_BALANCING);
3311 err = request_irq(qv->irq, mvpp2_isr, 0, port->dev->name, qv);
3315 if (qv->type == MVPP2_QUEUE_VECTOR_PRIVATE) {
3318 for_each_present_cpu(cpu) {
3319 if (mvpp2_cpu_to_thread(port->priv, cpu) ==
3321 cpumask_set_cpu(cpu, qv->mask);
3324 irq_set_affinity_hint(qv->irq, qv->mask);
3330 for (i = 0; i < port->nqvecs; i++) {
3331 struct mvpp2_queue_vector *qv = port->qvecs + i;
3333 irq_set_affinity_hint(qv->irq, NULL);
3336 free_irq(qv->irq, qv);
3342 static void mvpp2_irqs_deinit(struct mvpp2_port *port)
3346 for (i = 0; i < port->nqvecs; i++) {
3347 struct mvpp2_queue_vector *qv = port->qvecs + i;
3349 irq_set_affinity_hint(qv->irq, NULL);
3352 irq_clear_status_flags(qv->irq, IRQ_NO_BALANCING);
3353 free_irq(qv->irq, qv);
3357 static bool mvpp22_rss_is_supported(void)
3359 return queue_mode == MVPP2_QDIST_MULTI_MODE;
3362 static int mvpp2_open(struct net_device *dev)
3364 struct mvpp2_port *port = netdev_priv(dev);
3365 struct mvpp2 *priv = port->priv;
3366 unsigned char mac_bcast[ETH_ALEN] = {
3367 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3371 err = mvpp2_prs_mac_da_accept(port, mac_bcast, true);
3373 netdev_err(dev, "mvpp2_prs_mac_da_accept BC failed\n");
3376 err = mvpp2_prs_mac_da_accept(port, dev->dev_addr, true);
3378 netdev_err(dev, "mvpp2_prs_mac_da_accept own addr failed\n");
3381 err = mvpp2_prs_tag_mode_set(port->priv, port->id, MVPP2_TAG_TYPE_MH);
3383 netdev_err(dev, "mvpp2_prs_tag_mode_set failed\n");
3386 err = mvpp2_prs_def_flow(port);
3388 netdev_err(dev, "mvpp2_prs_def_flow failed\n");
3392 /* Allocate the Rx/Tx queues */
3393 err = mvpp2_setup_rxqs(port);
3395 netdev_err(port->dev, "cannot allocate Rx queues\n");
3399 err = mvpp2_setup_txqs(port);
3401 netdev_err(port->dev, "cannot allocate Tx queues\n");
3402 goto err_cleanup_rxqs;
3405 err = mvpp2_irqs_init(port);
3407 netdev_err(port->dev, "cannot init IRQs\n");
3408 goto err_cleanup_txqs;
3411 /* Phylink isn't supported yet in ACPI mode */
3412 if (port->of_node) {
3413 err = phylink_of_phy_connect(port->phylink, port->of_node, 0);
3415 netdev_err(port->dev, "could not attach PHY (%d)\n",
3423 if (priv->hw_version == MVPP22 && port->link_irq && !port->phylink) {
3424 err = request_irq(port->link_irq, mvpp2_link_status_isr, 0,
3427 netdev_err(port->dev, "cannot request link IRQ %d\n",
3432 mvpp22_gop_setup_irq(port);
3434 /* In default link is down */
3435 netif_carrier_off(port->dev);
3443 netdev_err(port->dev,
3444 "invalid configuration: no dt or link IRQ");
3448 /* Unmask interrupts on all CPUs */
3449 on_each_cpu(mvpp2_interrupts_unmask, port, 1);
3450 mvpp2_shared_interrupt_mask_unmask(port, false);
3452 mvpp2_start_dev(port);
3454 /* Start hardware statistics gathering */
3455 queue_delayed_work(priv->stats_queue, &port->stats_work,
3456 MVPP2_MIB_COUNTERS_STATS_DELAY);
3461 mvpp2_irqs_deinit(port);
3463 mvpp2_cleanup_txqs(port);
3465 mvpp2_cleanup_rxqs(port);
3469 static int mvpp2_stop(struct net_device *dev)
3471 struct mvpp2_port *port = netdev_priv(dev);
3472 struct mvpp2_port_pcpu *port_pcpu;
3473 unsigned int thread;
3475 mvpp2_stop_dev(port);
3477 /* Mask interrupts on all threads */
3478 on_each_cpu(mvpp2_interrupts_mask, port, 1);
3479 mvpp2_shared_interrupt_mask_unmask(port, true);
3482 phylink_disconnect_phy(port->phylink);
3484 free_irq(port->link_irq, port);
3486 mvpp2_irqs_deinit(port);
3487 if (!port->has_tx_irqs) {
3488 for (thread = 0; thread < port->priv->nthreads; thread++) {
3489 port_pcpu = per_cpu_ptr(port->pcpu, thread);
3491 hrtimer_cancel(&port_pcpu->tx_done_timer);
3492 port_pcpu->timer_scheduled = false;
3493 tasklet_kill(&port_pcpu->tx_done_tasklet);
3496 mvpp2_cleanup_rxqs(port);
3497 mvpp2_cleanup_txqs(port);
3499 cancel_delayed_work_sync(&port->stats_work);
3504 static int mvpp2_prs_mac_da_accept_list(struct mvpp2_port *port,
3505 struct netdev_hw_addr_list *list)
3507 struct netdev_hw_addr *ha;
3510 netdev_hw_addr_list_for_each(ha, list) {
3511 ret = mvpp2_prs_mac_da_accept(port, ha->addr, true);
3519 static void mvpp2_set_rx_promisc(struct mvpp2_port *port, bool enable)
3521 if (!enable && (port->dev->features & NETIF_F_HW_VLAN_CTAG_FILTER))
3522 mvpp2_prs_vid_enable_filtering(port);
3524 mvpp2_prs_vid_disable_filtering(port);
3526 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3527 MVPP2_PRS_L2_UNI_CAST, enable);
3529 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3530 MVPP2_PRS_L2_MULTI_CAST, enable);
3533 static void mvpp2_set_rx_mode(struct net_device *dev)
3535 struct mvpp2_port *port = netdev_priv(dev);
3537 /* Clear the whole UC and MC list */
3538 mvpp2_prs_mac_del_all(port);
3540 if (dev->flags & IFF_PROMISC) {
3541 mvpp2_set_rx_promisc(port, true);
3545 mvpp2_set_rx_promisc(port, false);
3547 if (netdev_uc_count(dev) > MVPP2_PRS_MAC_UC_FILT_MAX ||
3548 mvpp2_prs_mac_da_accept_list(port, &dev->uc))
3549 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3550 MVPP2_PRS_L2_UNI_CAST, true);
3552 if (dev->flags & IFF_ALLMULTI) {
3553 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3554 MVPP2_PRS_L2_MULTI_CAST, true);
3558 if (netdev_mc_count(dev) > MVPP2_PRS_MAC_MC_FILT_MAX ||
3559 mvpp2_prs_mac_da_accept_list(port, &dev->mc))
3560 mvpp2_prs_mac_promisc_set(port->priv, port->id,
3561 MVPP2_PRS_L2_MULTI_CAST, true);
3564 static int mvpp2_set_mac_address(struct net_device *dev, void *p)
3566 const struct sockaddr *addr = p;
3569 if (!is_valid_ether_addr(addr->sa_data))
3570 return -EADDRNOTAVAIL;
3572 err = mvpp2_prs_update_mac_da(dev, addr->sa_data);
3574 /* Reconfigure parser accept the original MAC address */
3575 mvpp2_prs_update_mac_da(dev, dev->dev_addr);
3576 netdev_err(dev, "failed to change MAC address\n");
3581 static int mvpp2_change_mtu(struct net_device *dev, int mtu)
3583 struct mvpp2_port *port = netdev_priv(dev);
3586 if (!IS_ALIGNED(MVPP2_RX_PKT_SIZE(mtu), 8)) {
3587 netdev_info(dev, "illegal MTU value %d, round to %d\n", mtu,
3588 ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8));
3589 mtu = ALIGN(MVPP2_RX_PKT_SIZE(mtu), 8);
3592 if (!netif_running(dev)) {
3593 err = mvpp2_bm_update_mtu(dev, mtu);
3595 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3599 /* Reconfigure BM to the original MTU */
3600 err = mvpp2_bm_update_mtu(dev, dev->mtu);
3605 mvpp2_stop_dev(port);
3607 err = mvpp2_bm_update_mtu(dev, mtu);
3609 port->pkt_size = MVPP2_RX_PKT_SIZE(mtu);
3613 /* Reconfigure BM to the original MTU */
3614 err = mvpp2_bm_update_mtu(dev, dev->mtu);
3619 mvpp2_start_dev(port);
3620 mvpp2_egress_enable(port);
3621 mvpp2_ingress_enable(port);
3625 netdev_err(dev, "failed to change MTU\n");
3630 mvpp2_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
3632 struct mvpp2_port *port = netdev_priv(dev);
3636 for_each_possible_cpu(cpu) {
3637 struct mvpp2_pcpu_stats *cpu_stats;
3643 cpu_stats = per_cpu_ptr(port->stats, cpu);
3645 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
3646 rx_packets = cpu_stats->rx_packets;
3647 rx_bytes = cpu_stats->rx_bytes;
3648 tx_packets = cpu_stats->tx_packets;
3649 tx_bytes = cpu_stats->tx_bytes;
3650 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
3652 stats->rx_packets += rx_packets;
3653 stats->rx_bytes += rx_bytes;
3654 stats->tx_packets += tx_packets;
3655 stats->tx_bytes += tx_bytes;
3658 stats->rx_errors = dev->stats.rx_errors;
3659 stats->rx_dropped = dev->stats.rx_dropped;
3660 stats->tx_dropped = dev->stats.tx_dropped;
3663 static int mvpp2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3665 struct mvpp2_port *port = netdev_priv(dev);
3670 return phylink_mii_ioctl(port->phylink, ifr, cmd);
3673 static int mvpp2_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid)
3675 struct mvpp2_port *port = netdev_priv(dev);
3678 ret = mvpp2_prs_vid_entry_add(port, vid);
3680 netdev_err(dev, "rx-vlan-filter offloading cannot accept more than %d VIDs per port\n",
3681 MVPP2_PRS_VLAN_FILT_MAX - 1);
3685 static int mvpp2_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid)
3687 struct mvpp2_port *port = netdev_priv(dev);
3689 mvpp2_prs_vid_entry_remove(port, vid);
3693 static int mvpp2_set_features(struct net_device *dev,
3694 netdev_features_t features)
3696 netdev_features_t changed = dev->features ^ features;
3697 struct mvpp2_port *port = netdev_priv(dev);
3699 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) {
3700 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) {
3701 mvpp2_prs_vid_enable_filtering(port);
3703 /* Invalidate all registered VID filters for this
3706 mvpp2_prs_vid_remove_all(port);
3708 mvpp2_prs_vid_disable_filtering(port);
3712 if (changed & NETIF_F_RXHASH) {
3713 if (features & NETIF_F_RXHASH)
3714 mvpp22_rss_enable(port);
3716 mvpp22_rss_disable(port);
3722 /* Ethtool methods */
3724 static int mvpp2_ethtool_nway_reset(struct net_device *dev)
3726 struct mvpp2_port *port = netdev_priv(dev);
3731 return phylink_ethtool_nway_reset(port->phylink);
3734 /* Set interrupt coalescing for ethtools */
3735 static int mvpp2_ethtool_set_coalesce(struct net_device *dev,
3736 struct ethtool_coalesce *c)
3738 struct mvpp2_port *port = netdev_priv(dev);
3741 for (queue = 0; queue < port->nrxqs; queue++) {
3742 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
3744 rxq->time_coal = c->rx_coalesce_usecs;
3745 rxq->pkts_coal = c->rx_max_coalesced_frames;
3746 mvpp2_rx_pkts_coal_set(port, rxq);
3747 mvpp2_rx_time_coal_set(port, rxq);
3750 if (port->has_tx_irqs) {
3751 port->tx_time_coal = c->tx_coalesce_usecs;
3752 mvpp2_tx_time_coal_set(port);
3755 for (queue = 0; queue < port->ntxqs; queue++) {
3756 struct mvpp2_tx_queue *txq = port->txqs[queue];
3758 txq->done_pkts_coal = c->tx_max_coalesced_frames;
3760 if (port->has_tx_irqs)
3761 mvpp2_tx_pkts_coal_set(port, txq);
3767 /* get coalescing for ethtools */
3768 static int mvpp2_ethtool_get_coalesce(struct net_device *dev,
3769 struct ethtool_coalesce *c)
3771 struct mvpp2_port *port = netdev_priv(dev);
3773 c->rx_coalesce_usecs = port->rxqs[0]->time_coal;
3774 c->rx_max_coalesced_frames = port->rxqs[0]->pkts_coal;
3775 c->tx_max_coalesced_frames = port->txqs[0]->done_pkts_coal;
3776 c->tx_coalesce_usecs = port->tx_time_coal;
3780 static void mvpp2_ethtool_get_drvinfo(struct net_device *dev,
3781 struct ethtool_drvinfo *drvinfo)
3783 strlcpy(drvinfo->driver, MVPP2_DRIVER_NAME,
3784 sizeof(drvinfo->driver));
3785 strlcpy(drvinfo->version, MVPP2_DRIVER_VERSION,
3786 sizeof(drvinfo->version));
3787 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
3788 sizeof(drvinfo->bus_info));
3791 static void mvpp2_ethtool_get_ringparam(struct net_device *dev,
3792 struct ethtool_ringparam *ring)
3794 struct mvpp2_port *port = netdev_priv(dev);
3796 ring->rx_max_pending = MVPP2_MAX_RXD_MAX;
3797 ring->tx_max_pending = MVPP2_MAX_TXD_MAX;
3798 ring->rx_pending = port->rx_ring_size;
3799 ring->tx_pending = port->tx_ring_size;
3802 static int mvpp2_ethtool_set_ringparam(struct net_device *dev,
3803 struct ethtool_ringparam *ring)
3805 struct mvpp2_port *port = netdev_priv(dev);
3806 u16 prev_rx_ring_size = port->rx_ring_size;
3807 u16 prev_tx_ring_size = port->tx_ring_size;
3810 err = mvpp2_check_ringparam_valid(dev, ring);
3814 if (!netif_running(dev)) {
3815 port->rx_ring_size = ring->rx_pending;
3816 port->tx_ring_size = ring->tx_pending;
3820 /* The interface is running, so we have to force a
3821 * reallocation of the queues
3823 mvpp2_stop_dev(port);
3824 mvpp2_cleanup_rxqs(port);
3825 mvpp2_cleanup_txqs(port);
3827 port->rx_ring_size = ring->rx_pending;
3828 port->tx_ring_size = ring->tx_pending;
3830 err = mvpp2_setup_rxqs(port);
3832 /* Reallocate Rx queues with the original ring size */
3833 port->rx_ring_size = prev_rx_ring_size;
3834 ring->rx_pending = prev_rx_ring_size;
3835 err = mvpp2_setup_rxqs(port);
3839 err = mvpp2_setup_txqs(port);
3841 /* Reallocate Tx queues with the original ring size */
3842 port->tx_ring_size = prev_tx_ring_size;
3843 ring->tx_pending = prev_tx_ring_size;
3844 err = mvpp2_setup_txqs(port);
3846 goto err_clean_rxqs;
3849 mvpp2_start_dev(port);
3850 mvpp2_egress_enable(port);
3851 mvpp2_ingress_enable(port);
3856 mvpp2_cleanup_rxqs(port);
3858 netdev_err(dev, "failed to change ring parameters");
3862 static void mvpp2_ethtool_get_pause_param(struct net_device *dev,
3863 struct ethtool_pauseparam *pause)
3865 struct mvpp2_port *port = netdev_priv(dev);
3870 phylink_ethtool_get_pauseparam(port->phylink, pause);
3873 static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
3874 struct ethtool_pauseparam *pause)
3876 struct mvpp2_port *port = netdev_priv(dev);
3881 return phylink_ethtool_set_pauseparam(port->phylink, pause);
3884 static int mvpp2_ethtool_get_link_ksettings(struct net_device *dev,
3885 struct ethtool_link_ksettings *cmd)
3887 struct mvpp2_port *port = netdev_priv(dev);
3892 return phylink_ethtool_ksettings_get(port->phylink, cmd);
3895 static int mvpp2_ethtool_set_link_ksettings(struct net_device *dev,
3896 const struct ethtool_link_ksettings *cmd)
3898 struct mvpp2_port *port = netdev_priv(dev);
3903 return phylink_ethtool_ksettings_set(port->phylink, cmd);
3906 static int mvpp2_ethtool_get_rxnfc(struct net_device *dev,
3907 struct ethtool_rxnfc *info, u32 *rules)
3909 struct mvpp2_port *port = netdev_priv(dev);
3912 if (!mvpp22_rss_is_supported())
3915 switch (info->cmd) {
3917 ret = mvpp2_ethtool_rxfh_get(port, info);
3919 case ETHTOOL_GRXRINGS:
3920 info->data = port->nrxqs;
3929 static int mvpp2_ethtool_set_rxnfc(struct net_device *dev,
3930 struct ethtool_rxnfc *info)
3932 struct mvpp2_port *port = netdev_priv(dev);
3935 if (!mvpp22_rss_is_supported())
3938 switch (info->cmd) {
3940 ret = mvpp2_ethtool_rxfh_set(port, info);
3948 static u32 mvpp2_ethtool_get_rxfh_indir_size(struct net_device *dev)
3950 return mvpp22_rss_is_supported() ? MVPP22_RSS_TABLE_ENTRIES : 0;
3953 static int mvpp2_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3956 struct mvpp2_port *port = netdev_priv(dev);
3958 if (!mvpp22_rss_is_supported())
3962 memcpy(indir, port->indir,
3963 ARRAY_SIZE(port->indir) * sizeof(port->indir[0]));
3966 *hfunc = ETH_RSS_HASH_CRC32;
3971 static int mvpp2_ethtool_set_rxfh(struct net_device *dev, const u32 *indir,
3972 const u8 *key, const u8 hfunc)
3974 struct mvpp2_port *port = netdev_priv(dev);
3976 if (!mvpp22_rss_is_supported())
3979 if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_CRC32)
3986 memcpy(port->indir, indir,
3987 ARRAY_SIZE(port->indir) * sizeof(port->indir[0]));
3988 mvpp22_rss_fill_table(port, port->id);
3996 static const struct net_device_ops mvpp2_netdev_ops = {
3997 .ndo_open = mvpp2_open,
3998 .ndo_stop = mvpp2_stop,
3999 .ndo_start_xmit = mvpp2_tx,
4000 .ndo_set_rx_mode = mvpp2_set_rx_mode,
4001 .ndo_set_mac_address = mvpp2_set_mac_address,
4002 .ndo_change_mtu = mvpp2_change_mtu,
4003 .ndo_get_stats64 = mvpp2_get_stats64,
4004 .ndo_do_ioctl = mvpp2_ioctl,
4005 .ndo_vlan_rx_add_vid = mvpp2_vlan_rx_add_vid,
4006 .ndo_vlan_rx_kill_vid = mvpp2_vlan_rx_kill_vid,
4007 .ndo_set_features = mvpp2_set_features,
4010 static const struct ethtool_ops mvpp2_eth_tool_ops = {
4011 .nway_reset = mvpp2_ethtool_nway_reset,
4012 .get_link = ethtool_op_get_link,
4013 .set_coalesce = mvpp2_ethtool_set_coalesce,
4014 .get_coalesce = mvpp2_ethtool_get_coalesce,
4015 .get_drvinfo = mvpp2_ethtool_get_drvinfo,
4016 .get_ringparam = mvpp2_ethtool_get_ringparam,
4017 .set_ringparam = mvpp2_ethtool_set_ringparam,
4018 .get_strings = mvpp2_ethtool_get_strings,
4019 .get_ethtool_stats = mvpp2_ethtool_get_stats,
4020 .get_sset_count = mvpp2_ethtool_get_sset_count,
4021 .get_pauseparam = mvpp2_ethtool_get_pause_param,
4022 .set_pauseparam = mvpp2_ethtool_set_pause_param,
4023 .get_link_ksettings = mvpp2_ethtool_get_link_ksettings,
4024 .set_link_ksettings = mvpp2_ethtool_set_link_ksettings,
4025 .get_rxnfc = mvpp2_ethtool_get_rxnfc,
4026 .set_rxnfc = mvpp2_ethtool_set_rxnfc,
4027 .get_rxfh_indir_size = mvpp2_ethtool_get_rxfh_indir_size,
4028 .get_rxfh = mvpp2_ethtool_get_rxfh,
4029 .set_rxfh = mvpp2_ethtool_set_rxfh,
4033 /* Used for PPv2.1, or PPv2.2 with the old Device Tree binding that
4034 * had a single IRQ defined per-port.
4036 static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port,
4037 struct device_node *port_node)
4039 struct mvpp2_queue_vector *v = &port->qvecs[0];
4042 v->nrxqs = port->nrxqs;
4043 v->type = MVPP2_QUEUE_VECTOR_SHARED;
4044 v->sw_thread_id = 0;
4045 v->sw_thread_mask = *cpumask_bits(cpu_online_mask);
4047 v->irq = irq_of_parse_and_map(port_node, 0);
4050 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
4058 static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
4059 struct device_node *port_node)
4061 struct mvpp2 *priv = port->priv;
4062 struct mvpp2_queue_vector *v;
4065 switch (queue_mode) {
4066 case MVPP2_QDIST_SINGLE_MODE:
4067 port->nqvecs = priv->nthreads + 1;
4069 case MVPP2_QDIST_MULTI_MODE:
4070 port->nqvecs = priv->nthreads;
4074 for (i = 0; i < port->nqvecs; i++) {
4077 v = port->qvecs + i;
4080 v->type = MVPP2_QUEUE_VECTOR_PRIVATE;
4081 v->sw_thread_id = i;
4082 v->sw_thread_mask = BIT(i);
4084 if (port->flags & MVPP2_F_DT_COMPAT)
4085 snprintf(irqname, sizeof(irqname), "tx-cpu%d", i);
4087 snprintf(irqname, sizeof(irqname), "hif%d", i);
4089 if (queue_mode == MVPP2_QDIST_MULTI_MODE) {
4090 v->first_rxq = i * MVPP2_DEFAULT_RXQ;
4091 v->nrxqs = MVPP2_DEFAULT_RXQ;
4092 } else if (queue_mode == MVPP2_QDIST_SINGLE_MODE &&
4093 i == (port->nqvecs - 1)) {
4095 v->nrxqs = port->nrxqs;
4096 v->type = MVPP2_QUEUE_VECTOR_SHARED;
4098 if (port->flags & MVPP2_F_DT_COMPAT)
4099 strncpy(irqname, "rx-shared", sizeof(irqname));
4103 v->irq = of_irq_get_byname(port_node, irqname);
4105 v->irq = fwnode_irq_get(port->fwnode, i);
4111 netif_napi_add(port->dev, &v->napi, mvpp2_poll,
4118 for (i = 0; i < port->nqvecs; i++)
4119 irq_dispose_mapping(port->qvecs[i].irq);
4123 static int mvpp2_queue_vectors_init(struct mvpp2_port *port,
4124 struct device_node *port_node)
4126 if (port->has_tx_irqs)
4127 return mvpp2_multi_queue_vectors_init(port, port_node);
4129 return mvpp2_simple_queue_vectors_init(port, port_node);
4132 static void mvpp2_queue_vectors_deinit(struct mvpp2_port *port)
4136 for (i = 0; i < port->nqvecs; i++)
4137 irq_dispose_mapping(port->qvecs[i].irq);
4140 /* Configure Rx queue group interrupt for this port */
4141 static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)
4143 struct mvpp2 *priv = port->priv;
4147 if (priv->hw_version == MVPP21) {
4148 mvpp2_write(priv, MVPP21_ISR_RXQ_GROUP_REG(port->id),
4153 /* Handle the more complicated PPv2.2 case */
4154 for (i = 0; i < port->nqvecs; i++) {
4155 struct mvpp2_queue_vector *qv = port->qvecs + i;
4160 val = qv->sw_thread_id;
4161 val |= port->id << MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET;
4162 mvpp2_write(priv, MVPP22_ISR_RXQ_GROUP_INDEX_REG, val);
4164 val = qv->first_rxq;
4165 val |= qv->nrxqs << MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET;
4166 mvpp2_write(priv, MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG, val);
4170 /* Initialize port HW */
4171 static int mvpp2_port_init(struct mvpp2_port *port)
4173 struct device *dev = port->dev->dev.parent;
4174 struct mvpp2 *priv = port->priv;
4175 struct mvpp2_txq_pcpu *txq_pcpu;
4176 unsigned int thread;
4179 /* Checks for hardware constraints */
4180 if (port->first_rxq + port->nrxqs >
4181 MVPP2_MAX_PORTS * priv->max_port_rxqs)
4184 if (port->nrxqs % MVPP2_DEFAULT_RXQ ||
4185 port->nrxqs > priv->max_port_rxqs || port->ntxqs > MVPP2_MAX_TXQ)
4189 mvpp2_egress_disable(port);
4190 mvpp2_port_disable(port);
4192 port->tx_time_coal = MVPP2_TXDONE_COAL_USEC;
4194 port->txqs = devm_kcalloc(dev, port->ntxqs, sizeof(*port->txqs),
4199 /* Associate physical Tx queues to this port and initialize.
4200 * The mapping is predefined.
4202 for (queue = 0; queue < port->ntxqs; queue++) {
4203 int queue_phy_id = mvpp2_txq_phys(port->id, queue);
4204 struct mvpp2_tx_queue *txq;
4206 txq = devm_kzalloc(dev, sizeof(*txq), GFP_KERNEL);
4209 goto err_free_percpu;
4212 txq->pcpu = alloc_percpu(struct mvpp2_txq_pcpu);
4215 goto err_free_percpu;
4218 txq->id = queue_phy_id;
4219 txq->log_id = queue;
4220 txq->done_pkts_coal = MVPP2_TXDONE_COAL_PKTS_THRESH;
4221 for (thread = 0; thread < priv->nthreads; thread++) {
4222 txq_pcpu = per_cpu_ptr(txq->pcpu, thread);
4223 txq_pcpu->thread = thread;
4226 port->txqs[queue] = txq;
4229 port->rxqs = devm_kcalloc(dev, port->nrxqs, sizeof(*port->rxqs),
4233 goto err_free_percpu;
4236 /* Allocate and initialize Rx queue for this port */
4237 for (queue = 0; queue < port->nrxqs; queue++) {
4238 struct mvpp2_rx_queue *rxq;
4240 /* Map physical Rx queue to port's logical Rx queue */
4241 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
4244 goto err_free_percpu;
4246 /* Map this Rx queue to a physical queue */
4247 rxq->id = port->first_rxq + queue;
4248 rxq->port = port->id;
4249 rxq->logic_rxq = queue;
4251 port->rxqs[queue] = rxq;
4254 mvpp2_rx_irqs_setup(port);
4256 /* Create Rx descriptor rings */
4257 for (queue = 0; queue < port->nrxqs; queue++) {
4258 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4260 rxq->size = port->rx_ring_size;
4261 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4262 rxq->time_coal = MVPP2_RX_COAL_USEC;
4265 mvpp2_ingress_disable(port);
4267 /* Port default configuration */
4268 mvpp2_defaults_set(port);
4270 /* Port's classifier configuration */
4271 mvpp2_cls_oversize_rxq_set(port);
4272 mvpp2_cls_port_config(port);
4274 if (mvpp22_rss_is_supported())
4275 mvpp22_rss_port_init(port);
4277 /* Provide an initial Rx packet size */
4278 port->pkt_size = MVPP2_RX_PKT_SIZE(port->dev->mtu);
4280 /* Initialize pools for swf */
4281 err = mvpp2_swf_bm_pool_init(port);
4283 goto err_free_percpu;
4288 for (queue = 0; queue < port->ntxqs; queue++) {
4289 if (!port->txqs[queue])
4291 free_percpu(port->txqs[queue]->pcpu);
4296 static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node,
4297 unsigned long *flags)
4299 char *irqs[5] = { "rx-shared", "tx-cpu0", "tx-cpu1", "tx-cpu2",
4303 for (i = 0; i < 5; i++)
4304 if (of_property_match_string(port_node, "interrupt-names",
4308 *flags |= MVPP2_F_DT_COMPAT;
4312 /* Checks if the port dt description has the required Tx interrupts:
4313 * - PPv2.1: there are no such interrupts.
4315 * - The old DTs have: "rx-shared", "tx-cpuX" with X in [0...3]
4316 * - The new ones have: "hifX" with X in [0..8]
4318 * All those variants are supported to keep the backward compatibility.
4320 static bool mvpp2_port_has_irqs(struct mvpp2 *priv,
4321 struct device_node *port_node,
4322 unsigned long *flags)
4331 if (priv->hw_version == MVPP21)
4334 if (mvpp22_port_has_legacy_tx_irqs(port_node, flags))
4337 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
4338 snprintf(name, 5, "hif%d", i);
4339 if (of_property_match_string(port_node, "interrupt-names",
4347 static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
4348 struct fwnode_handle *fwnode,
4351 struct mvpp2_port *port = netdev_priv(dev);
4352 char hw_mac_addr[ETH_ALEN] = {0};
4353 char fw_mac_addr[ETH_ALEN];
4355 if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) {
4356 *mac_from = "firmware node";
4357 ether_addr_copy(dev->dev_addr, fw_mac_addr);
4361 if (priv->hw_version == MVPP21) {
4362 mvpp21_get_mac_address(port, hw_mac_addr);
4363 if (is_valid_ether_addr(hw_mac_addr)) {
4364 *mac_from = "hardware";
4365 ether_addr_copy(dev->dev_addr, hw_mac_addr);
4370 *mac_from = "random";
4371 eth_hw_addr_random(dev);
4374 static void mvpp2_phylink_validate(struct net_device *dev,
4375 unsigned long *supported,
4376 struct phylink_link_state *state)
4378 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
4380 phylink_set(mask, Autoneg);
4381 phylink_set_port_modes(mask);
4382 phylink_set(mask, Pause);
4383 phylink_set(mask, Asym_Pause);
4385 switch (state->interface) {
4386 case PHY_INTERFACE_MODE_10GKR:
4387 phylink_set(mask, 10000baseCR_Full);
4388 phylink_set(mask, 10000baseSR_Full);
4389 phylink_set(mask, 10000baseLR_Full);
4390 phylink_set(mask, 10000baseLRM_Full);
4391 phylink_set(mask, 10000baseER_Full);
4392 phylink_set(mask, 10000baseKR_Full);
4395 phylink_set(mask, 10baseT_Half);
4396 phylink_set(mask, 10baseT_Full);
4397 phylink_set(mask, 100baseT_Half);
4398 phylink_set(mask, 100baseT_Full);
4399 phylink_set(mask, 10000baseT_Full);
4401 case PHY_INTERFACE_MODE_1000BASEX:
4402 case PHY_INTERFACE_MODE_2500BASEX:
4403 phylink_set(mask, 1000baseT_Full);
4404 phylink_set(mask, 1000baseX_Full);
4405 phylink_set(mask, 2500baseX_Full);
4408 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
4409 bitmap_and(state->advertising, state->advertising, mask,
4410 __ETHTOOL_LINK_MODE_MASK_NBITS);
4413 static void mvpp22_xlg_link_state(struct mvpp2_port *port,
4414 struct phylink_link_state *state)
4418 state->speed = SPEED_10000;
4420 state->an_complete = 1;
4422 val = readl(port->base + MVPP22_XLG_STATUS);
4423 state->link = !!(val & MVPP22_XLG_STATUS_LINK_UP);
4426 val = readl(port->base + MVPP22_XLG_CTRL0_REG);
4427 if (val & MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN)
4428 state->pause |= MLO_PAUSE_TX;
4429 if (val & MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN)
4430 state->pause |= MLO_PAUSE_RX;
4433 static void mvpp2_gmac_link_state(struct mvpp2_port *port,
4434 struct phylink_link_state *state)
4438 val = readl(port->base + MVPP2_GMAC_STATUS0);
4440 state->an_complete = !!(val & MVPP2_GMAC_STATUS0_AN_COMPLETE);
4441 state->link = !!(val & MVPP2_GMAC_STATUS0_LINK_UP);
4442 state->duplex = !!(val & MVPP2_GMAC_STATUS0_FULL_DUPLEX);
4444 switch (port->phy_interface) {
4445 case PHY_INTERFACE_MODE_1000BASEX:
4446 state->speed = SPEED_1000;
4448 case PHY_INTERFACE_MODE_2500BASEX:
4449 state->speed = SPEED_2500;
4452 if (val & MVPP2_GMAC_STATUS0_GMII_SPEED)
4453 state->speed = SPEED_1000;
4454 else if (val & MVPP2_GMAC_STATUS0_MII_SPEED)
4455 state->speed = SPEED_100;
4457 state->speed = SPEED_10;
4461 if (val & MVPP2_GMAC_STATUS0_RX_PAUSE)
4462 state->pause |= MLO_PAUSE_RX;
4463 if (val & MVPP2_GMAC_STATUS0_TX_PAUSE)
4464 state->pause |= MLO_PAUSE_TX;
4467 static int mvpp2_phylink_mac_link_state(struct net_device *dev,
4468 struct phylink_link_state *state)
4470 struct mvpp2_port *port = netdev_priv(dev);
4472 if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
4473 u32 mode = readl(port->base + MVPP22_XLG_CTRL3_REG);
4474 mode &= MVPP22_XLG_CTRL3_MACMODESELECT_MASK;
4476 if (mode == MVPP22_XLG_CTRL3_MACMODESELECT_10G) {
4477 mvpp22_xlg_link_state(port, state);
4482 mvpp2_gmac_link_state(port, state);
4486 static void mvpp2_mac_an_restart(struct net_device *dev)
4488 struct mvpp2_port *port = netdev_priv(dev);
4491 if (port->phy_interface != PHY_INTERFACE_MODE_SGMII)
4494 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4495 /* The RESTART_AN bit is cleared by the h/w after restarting the AN
4498 val |= MVPP2_GMAC_IN_BAND_RESTART_AN | MVPP2_GMAC_IN_BAND_AUTONEG;
4499 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4502 static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
4503 const struct phylink_link_state *state)
4507 ctrl0 = readl(port->base + MVPP22_XLG_CTRL0_REG);
4508 ctrl4 = readl(port->base + MVPP22_XLG_CTRL4_REG);
4510 if (state->pause & MLO_PAUSE_TX)
4511 ctrl0 |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
4512 if (state->pause & MLO_PAUSE_RX)
4513 ctrl0 |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
4515 ctrl4 &= ~MVPP22_XLG_CTRL4_MACMODSELECT_GMAC;
4516 ctrl4 |= MVPP22_XLG_CTRL4_FWD_FC | MVPP22_XLG_CTRL4_FWD_PFC |
4517 MVPP22_XLG_CTRL4_EN_IDLE_CHECK;
4519 writel(ctrl0, port->base + MVPP22_XLG_CTRL0_REG);
4520 writel(ctrl4, port->base + MVPP22_XLG_CTRL4_REG);
4523 static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
4524 const struct phylink_link_state *state)
4526 u32 an, ctrl0, ctrl2, ctrl4;
4528 an = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4529 ctrl0 = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
4530 ctrl2 = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
4531 ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
4533 /* Force link down */
4534 an &= ~MVPP2_GMAC_FORCE_LINK_PASS;
4535 an |= MVPP2_GMAC_FORCE_LINK_DOWN;
4536 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4538 /* Set the GMAC in a reset state */
4539 ctrl2 |= MVPP2_GMAC_PORT_RESET_MASK;
4540 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
4542 an &= ~(MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_CONFIG_GMII_SPEED |
4543 MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FC_ADV_EN |
4544 MVPP2_GMAC_FC_ADV_ASM_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG |
4545 MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_AN_DUPLEX_EN |
4546 MVPP2_GMAC_FORCE_LINK_DOWN);
4547 ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
4548 ctrl2 &= ~(MVPP2_GMAC_PORT_RESET_MASK | MVPP2_GMAC_PCS_ENABLE_MASK);
4550 if (state->interface == PHY_INTERFACE_MODE_1000BASEX ||
4551 state->interface == PHY_INTERFACE_MODE_2500BASEX) {
4552 /* 1000BaseX and 2500BaseX ports cannot negotiate speed nor can
4553 * they negotiate duplex: they are always operating with a fixed
4554 * speed of 1000/2500Mbps in full duplex, so force 1000/2500
4555 * speed and full duplex here.
4557 ctrl0 |= MVPP2_GMAC_PORT_TYPE_MASK;
4558 an |= MVPP2_GMAC_CONFIG_GMII_SPEED |
4559 MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4560 } else if (!phy_interface_mode_is_rgmii(state->interface)) {
4561 an |= MVPP2_GMAC_AN_SPEED_EN | MVPP2_GMAC_FLOW_CTRL_AUTONEG;
4565 an |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
4566 if (phylink_test(state->advertising, Pause))
4567 an |= MVPP2_GMAC_FC_ADV_EN;
4568 if (phylink_test(state->advertising, Asym_Pause))
4569 an |= MVPP2_GMAC_FC_ADV_ASM_EN;
4571 if (state->interface == PHY_INTERFACE_MODE_SGMII ||
4572 state->interface == PHY_INTERFACE_MODE_1000BASEX ||
4573 state->interface == PHY_INTERFACE_MODE_2500BASEX) {
4574 an |= MVPP2_GMAC_IN_BAND_AUTONEG;
4575 ctrl2 |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
4577 ctrl4 &= ~(MVPP22_CTRL4_EXT_PIN_GMII_SEL |
4578 MVPP22_CTRL4_RX_FC_EN | MVPP22_CTRL4_TX_FC_EN);
4579 ctrl4 |= MVPP22_CTRL4_SYNC_BYPASS_DIS |
4580 MVPP22_CTRL4_DP_CLK_SEL |
4581 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4583 if (state->pause & MLO_PAUSE_TX)
4584 ctrl4 |= MVPP22_CTRL4_TX_FC_EN;
4585 if (state->pause & MLO_PAUSE_RX)
4586 ctrl4 |= MVPP22_CTRL4_RX_FC_EN;
4587 } else if (phy_interface_mode_is_rgmii(state->interface)) {
4588 an |= MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS;
4590 if (state->speed == SPEED_1000)
4591 an |= MVPP2_GMAC_CONFIG_GMII_SPEED;
4592 else if (state->speed == SPEED_100)
4593 an |= MVPP2_GMAC_CONFIG_MII_SPEED;
4595 ctrl4 &= ~MVPP22_CTRL4_DP_CLK_SEL;
4596 ctrl4 |= MVPP22_CTRL4_EXT_PIN_GMII_SEL |
4597 MVPP22_CTRL4_SYNC_BYPASS_DIS |
4598 MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
4601 writel(ctrl0, port->base + MVPP2_GMAC_CTRL_0_REG);
4602 writel(ctrl2, port->base + MVPP2_GMAC_CTRL_2_REG);
4603 writel(ctrl4, port->base + MVPP22_GMAC_CTRL_4_REG);
4604 writel(an, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4607 static void mvpp2_mac_config(struct net_device *dev, unsigned int mode,
4608 const struct phylink_link_state *state)
4610 struct mvpp2_port *port = netdev_priv(dev);
4612 /* Check for invalid configuration */
4613 if (state->interface == PHY_INTERFACE_MODE_10GKR && port->gop_id != 0) {
4614 netdev_err(dev, "Invalid mode on %s\n", dev->name);
4618 /* Make sure the port is disabled when reconfiguring the mode */
4619 mvpp2_port_disable(port);
4621 if (port->priv->hw_version == MVPP22 &&
4622 port->phy_interface != state->interface) {
4623 port->phy_interface = state->interface;
4625 /* Reconfigure the serdes lanes */
4626 phy_power_off(port->comphy);
4627 mvpp22_mode_reconfigure(port);
4630 /* mac (re)configuration */
4631 if (state->interface == PHY_INTERFACE_MODE_10GKR)
4632 mvpp2_xlg_config(port, mode, state);
4633 else if (phy_interface_mode_is_rgmii(state->interface) ||
4634 state->interface == PHY_INTERFACE_MODE_SGMII ||
4635 state->interface == PHY_INTERFACE_MODE_1000BASEX ||
4636 state->interface == PHY_INTERFACE_MODE_2500BASEX)
4637 mvpp2_gmac_config(port, mode, state);
4639 if (port->priv->hw_version == MVPP21 && port->flags & MVPP2_F_LOOPBACK)
4640 mvpp2_port_loopback_set(port, state);
4642 mvpp2_port_enable(port);
4645 static void mvpp2_mac_link_up(struct net_device *dev, unsigned int mode,
4646 phy_interface_t interface, struct phy_device *phy)
4648 struct mvpp2_port *port = netdev_priv(dev);
4651 if (!phylink_autoneg_inband(mode) &&
4652 interface != PHY_INTERFACE_MODE_10GKR) {
4653 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4654 val &= ~MVPP2_GMAC_FORCE_LINK_DOWN;
4655 if (phy_interface_mode_is_rgmii(interface))
4656 val |= MVPP2_GMAC_FORCE_LINK_PASS;
4657 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4660 mvpp2_port_enable(port);
4662 mvpp2_egress_enable(port);
4663 mvpp2_ingress_enable(port);
4664 netif_tx_wake_all_queues(dev);
4667 static void mvpp2_mac_link_down(struct net_device *dev, unsigned int mode,
4668 phy_interface_t interface)
4670 struct mvpp2_port *port = netdev_priv(dev);
4673 if (!phylink_autoneg_inband(mode) &&
4674 interface != PHY_INTERFACE_MODE_10GKR) {
4675 val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4676 val &= ~MVPP2_GMAC_FORCE_LINK_PASS;
4677 val |= MVPP2_GMAC_FORCE_LINK_DOWN;
4678 writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
4681 netif_tx_stop_all_queues(dev);
4682 mvpp2_egress_disable(port);
4683 mvpp2_ingress_disable(port);
4685 /* When using link interrupts to notify phylink of a MAC state change,
4686 * we do not want the port to be disabled (we want to receive further
4687 * interrupts, to be notified when the port will have a link later).
4692 mvpp2_port_disable(port);
4695 static const struct phylink_mac_ops mvpp2_phylink_ops = {
4696 .validate = mvpp2_phylink_validate,
4697 .mac_link_state = mvpp2_phylink_mac_link_state,
4698 .mac_an_restart = mvpp2_mac_an_restart,
4699 .mac_config = mvpp2_mac_config,
4700 .mac_link_up = mvpp2_mac_link_up,
4701 .mac_link_down = mvpp2_mac_link_down,
4704 /* Ports initialization */
4705 static int mvpp2_port_probe(struct platform_device *pdev,
4706 struct fwnode_handle *port_fwnode,
4709 struct phy *comphy = NULL;
4710 struct mvpp2_port *port;
4711 struct mvpp2_port_pcpu *port_pcpu;
4712 struct device_node *port_node = to_of_node(port_fwnode);
4713 struct net_device *dev;
4714 struct resource *res;
4715 struct phylink *phylink;
4716 char *mac_from = "";
4717 unsigned int ntxqs, nrxqs, thread;
4718 unsigned long flags = 0;
4725 has_tx_irqs = mvpp2_port_has_irqs(priv, port_node, &flags);
4726 if (!has_tx_irqs && queue_mode == MVPP2_QDIST_MULTI_MODE) {
4728 "not enough IRQs to support multi queue mode\n");
4732 ntxqs = MVPP2_MAX_TXQ;
4733 if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_MULTI_MODE)
4734 nrxqs = MVPP2_DEFAULT_RXQ * num_possible_cpus();
4736 nrxqs = MVPP2_DEFAULT_RXQ;
4738 dev = alloc_etherdev_mqs(sizeof(*port), ntxqs, nrxqs);
4742 phy_mode = fwnode_get_phy_mode(port_fwnode);
4744 dev_err(&pdev->dev, "incorrect phy mode\n");
4746 goto err_free_netdev;
4750 comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
4751 if (IS_ERR(comphy)) {
4752 if (PTR_ERR(comphy) == -EPROBE_DEFER) {
4753 err = -EPROBE_DEFER;
4754 goto err_free_netdev;
4760 if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
4762 dev_err(&pdev->dev, "missing port-id value\n");
4763 goto err_free_netdev;
4766 dev->tx_queue_len = MVPP2_MAX_TXD_MAX;
4767 dev->watchdog_timeo = 5 * HZ;
4768 dev->netdev_ops = &mvpp2_netdev_ops;
4769 dev->ethtool_ops = &mvpp2_eth_tool_ops;
4771 port = netdev_priv(dev);
4773 port->fwnode = port_fwnode;
4774 port->has_phy = !!of_find_property(port_node, "phy", NULL);
4775 port->ntxqs = ntxqs;
4776 port->nrxqs = nrxqs;
4778 port->has_tx_irqs = has_tx_irqs;
4779 port->flags = flags;
4781 err = mvpp2_queue_vectors_init(port, port_node);
4783 goto err_free_netdev;
4786 port->link_irq = of_irq_get_byname(port_node, "link");
4788 port->link_irq = fwnode_irq_get(port_fwnode, port->nqvecs + 1);
4789 if (port->link_irq == -EPROBE_DEFER) {
4790 err = -EPROBE_DEFER;
4791 goto err_deinit_qvecs;
4793 if (port->link_irq <= 0)
4794 /* the link irq is optional */
4797 if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
4798 port->flags |= MVPP2_F_LOOPBACK;
4801 if (priv->hw_version == MVPP21)
4802 port->first_rxq = port->id * port->nrxqs;
4804 port->first_rxq = port->id * priv->max_port_rxqs;
4806 port->of_node = port_node;
4807 port->phy_interface = phy_mode;
4808 port->comphy = comphy;
4810 if (priv->hw_version == MVPP21) {
4811 res = platform_get_resource(pdev, IORESOURCE_MEM, 2 + id);
4812 port->base = devm_ioremap_resource(&pdev->dev, res);
4813 if (IS_ERR(port->base)) {
4814 err = PTR_ERR(port->base);
4818 port->stats_base = port->priv->lms_base +
4819 MVPP21_MIB_COUNTERS_OFFSET +
4820 port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ;
4822 if (fwnode_property_read_u32(port_fwnode, "gop-port-id",
4825 dev_err(&pdev->dev, "missing gop-port-id value\n");
4826 goto err_deinit_qvecs;
4829 port->base = priv->iface_base + MVPP22_GMAC_BASE(port->gop_id);
4830 port->stats_base = port->priv->iface_base +
4831 MVPP22_MIB_COUNTERS_OFFSET +
4832 port->gop_id * MVPP22_MIB_COUNTERS_PORT_SZ;
4835 /* Alloc per-cpu and ethtool stats */
4836 port->stats = netdev_alloc_pcpu_stats(struct mvpp2_pcpu_stats);
4842 port->ethtool_stats = devm_kcalloc(&pdev->dev,
4843 ARRAY_SIZE(mvpp2_ethtool_regs),
4844 sizeof(u64), GFP_KERNEL);
4845 if (!port->ethtool_stats) {
4847 goto err_free_stats;
4850 mutex_init(&port->gather_stats_lock);
4851 INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics);
4853 mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from);
4855 port->tx_ring_size = MVPP2_MAX_TXD_DFLT;
4856 port->rx_ring_size = MVPP2_MAX_RXD_DFLT;
4857 SET_NETDEV_DEV(dev, &pdev->dev);
4859 err = mvpp2_port_init(port);
4861 dev_err(&pdev->dev, "failed to init port %d\n", id);
4862 goto err_free_stats;
4865 mvpp2_port_periodic_xon_disable(port);
4867 mvpp2_port_reset(port);
4869 port->pcpu = alloc_percpu(struct mvpp2_port_pcpu);
4872 goto err_free_txq_pcpu;
4875 if (!port->has_tx_irqs) {
4876 for (thread = 0; thread < priv->nthreads; thread++) {
4877 port_pcpu = per_cpu_ptr(port->pcpu, thread);
4879 hrtimer_init(&port_pcpu->tx_done_timer, CLOCK_MONOTONIC,
4880 HRTIMER_MODE_REL_PINNED);
4881 port_pcpu->tx_done_timer.function = mvpp2_hr_timer_cb;
4882 port_pcpu->timer_scheduled = false;
4884 tasklet_init(&port_pcpu->tx_done_tasklet,
4886 (unsigned long)dev);
4890 features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4892 dev->features = features | NETIF_F_RXCSUM;
4893 dev->hw_features |= features | NETIF_F_RXCSUM | NETIF_F_GRO |
4894 NETIF_F_HW_VLAN_CTAG_FILTER;
4896 if (mvpp22_rss_is_supported())
4897 dev->hw_features |= NETIF_F_RXHASH;
4899 if (port->pool_long->id == MVPP2_BM_JUMBO && port->id != 0) {
4900 dev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
4901 dev->hw_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
4904 dev->vlan_features |= features;
4905 dev->gso_max_segs = MVPP2_MAX_TSO_SEGS;
4906 dev->priv_flags |= IFF_UNICAST_FLT;
4908 /* MTU range: 68 - 9704 */
4909 dev->min_mtu = ETH_MIN_MTU;
4910 /* 9704 == 9728 - 20 and rounding to 8 */
4911 dev->max_mtu = MVPP2_BM_JUMBO_PKT_SIZE;
4912 dev->dev.of_node = port_node;
4914 /* Phylink isn't used w/ ACPI as of now */
4916 phylink = phylink_create(dev, port_fwnode, phy_mode,
4917 &mvpp2_phylink_ops);
4918 if (IS_ERR(phylink)) {
4919 err = PTR_ERR(phylink);
4920 goto err_free_port_pcpu;
4922 port->phylink = phylink;
4924 port->phylink = NULL;
4927 err = register_netdev(dev);
4929 dev_err(&pdev->dev, "failed to register netdev\n");
4932 netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
4934 priv->port_list[priv->port_count++] = port;
4940 phylink_destroy(port->phylink);
4942 free_percpu(port->pcpu);
4944 for (i = 0; i < port->ntxqs; i++)
4945 free_percpu(port->txqs[i]->pcpu);
4947 free_percpu(port->stats);
4950 irq_dispose_mapping(port->link_irq);
4952 mvpp2_queue_vectors_deinit(port);
4958 /* Ports removal routine */
4959 static void mvpp2_port_remove(struct mvpp2_port *port)
4963 unregister_netdev(port->dev);
4965 phylink_destroy(port->phylink);
4966 free_percpu(port->pcpu);
4967 free_percpu(port->stats);
4968 for (i = 0; i < port->ntxqs; i++)
4969 free_percpu(port->txqs[i]->pcpu);
4970 mvpp2_queue_vectors_deinit(port);
4972 irq_dispose_mapping(port->link_irq);
4973 free_netdev(port->dev);
4976 /* Initialize decoding windows */
4977 static void mvpp2_conf_mbus_windows(const struct mbus_dram_target_info *dram,
4983 for (i = 0; i < 6; i++) {
4984 mvpp2_write(priv, MVPP2_WIN_BASE(i), 0);
4985 mvpp2_write(priv, MVPP2_WIN_SIZE(i), 0);
4988 mvpp2_write(priv, MVPP2_WIN_REMAP(i), 0);
4993 for (i = 0; i < dram->num_cs; i++) {
4994 const struct mbus_dram_window *cs = dram->cs + i;
4996 mvpp2_write(priv, MVPP2_WIN_BASE(i),
4997 (cs->base & 0xffff0000) | (cs->mbus_attr << 8) |
4998 dram->mbus_dram_target_id);
5000 mvpp2_write(priv, MVPP2_WIN_SIZE(i),
5001 (cs->size - 1) & 0xffff0000);
5003 win_enable |= (1 << i);
5006 mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);
5009 /* Initialize Rx FIFO's */
5010 static void mvpp2_rx_fifo_init(struct mvpp2 *priv)
5014 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
5015 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
5016 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
5017 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
5018 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
5021 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
5022 MVPP2_RX_FIFO_PORT_MIN_PKT);
5023 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
5026 static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
5030 /* The FIFO size parameters are set depending on the maximum speed a
5031 * given port can handle:
5034 * - Ports 2 and 3: 1Gbps
5037 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(0),
5038 MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB);
5039 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(0),
5040 MVPP2_RX_FIFO_PORT_ATTR_SIZE_32KB);
5042 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(1),
5043 MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB);
5044 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(1),
5045 MVPP2_RX_FIFO_PORT_ATTR_SIZE_8KB);
5047 for (port = 2; port < MVPP2_MAX_PORTS; port++) {
5048 mvpp2_write(priv, MVPP2_RX_DATA_FIFO_SIZE_REG(port),
5049 MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB);
5050 mvpp2_write(priv, MVPP2_RX_ATTR_FIFO_SIZE_REG(port),
5051 MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB);
5054 mvpp2_write(priv, MVPP2_RX_MIN_PKT_SIZE_REG,
5055 MVPP2_RX_FIFO_PORT_MIN_PKT);
5056 mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
5059 /* Initialize Tx FIFO's: the total FIFO size is 19kB on PPv2.2 and 10G
5060 * interfaces must have a Tx FIFO size of 10kB. As only port 0 can do 10G,
5061 * configure its Tx FIFO size to 10kB and the others ports Tx FIFO size to 3kB.
5063 static void mvpp22_tx_fifo_init(struct mvpp2 *priv)
5065 int port, size, thrs;
5067 for (port = 0; port < MVPP2_MAX_PORTS; port++) {
5069 size = MVPP22_TX_FIFO_DATA_SIZE_10KB;
5070 thrs = MVPP2_TX_FIFO_THRESHOLD_10KB;
5072 size = MVPP22_TX_FIFO_DATA_SIZE_3KB;
5073 thrs = MVPP2_TX_FIFO_THRESHOLD_3KB;
5075 mvpp2_write(priv, MVPP22_TX_FIFO_SIZE_REG(port), size);
5076 mvpp2_write(priv, MVPP22_TX_FIFO_THRESH_REG(port), thrs);
5080 static void mvpp2_axi_init(struct mvpp2 *priv)
5082 u32 val, rdval, wrval;
5084 mvpp2_write(priv, MVPP22_BM_ADDR_HIGH_RLS_REG, 0x0);
5086 /* AXI Bridge Configuration */
5088 rdval = MVPP22_AXI_CODE_CACHE_RD_CACHE
5089 << MVPP22_AXI_ATTR_CACHE_OFFS;
5090 rdval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5091 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
5093 wrval = MVPP22_AXI_CODE_CACHE_WR_CACHE
5094 << MVPP22_AXI_ATTR_CACHE_OFFS;
5095 wrval |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5096 << MVPP22_AXI_ATTR_DOMAIN_OFFS;
5099 mvpp2_write(priv, MVPP22_AXI_BM_WR_ATTR_REG, wrval);
5100 mvpp2_write(priv, MVPP22_AXI_BM_RD_ATTR_REG, rdval);
5103 mvpp2_write(priv, MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG, rdval);
5104 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG, wrval);
5105 mvpp2_write(priv, MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG, rdval);
5106 mvpp2_write(priv, MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG, wrval);
5109 mvpp2_write(priv, MVPP22_AXI_TX_DATA_RD_ATTR_REG, rdval);
5110 mvpp2_write(priv, MVPP22_AXI_RX_DATA_WR_ATTR_REG, wrval);
5112 val = MVPP22_AXI_CODE_CACHE_NON_CACHE
5113 << MVPP22_AXI_CODE_CACHE_OFFS;
5114 val |= MVPP22_AXI_CODE_DOMAIN_SYSTEM
5115 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5116 mvpp2_write(priv, MVPP22_AXI_RD_NORMAL_CODE_REG, val);
5117 mvpp2_write(priv, MVPP22_AXI_WR_NORMAL_CODE_REG, val);
5119 val = MVPP22_AXI_CODE_CACHE_RD_CACHE
5120 << MVPP22_AXI_CODE_CACHE_OFFS;
5121 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5122 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5124 mvpp2_write(priv, MVPP22_AXI_RD_SNOOP_CODE_REG, val);
5126 val = MVPP22_AXI_CODE_CACHE_WR_CACHE
5127 << MVPP22_AXI_CODE_CACHE_OFFS;
5128 val |= MVPP22_AXI_CODE_DOMAIN_OUTER_DOM
5129 << MVPP22_AXI_CODE_DOMAIN_OFFS;
5131 mvpp2_write(priv, MVPP22_AXI_WR_SNOOP_CODE_REG, val);
5134 /* Initialize network controller common part HW */
5135 static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
5137 const struct mbus_dram_target_info *dram_target_info;
5141 /* MBUS windows configuration */
5142 dram_target_info = mv_mbus_dram_info();
5143 if (dram_target_info)
5144 mvpp2_conf_mbus_windows(dram_target_info, priv);
5146 if (priv->hw_version == MVPP22)
5147 mvpp2_axi_init(priv);
5149 /* Disable HW PHY polling */
5150 if (priv->hw_version == MVPP21) {
5151 val = readl(priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5152 val |= MVPP2_PHY_AN_STOP_SMI0_MASK;
5153 writel(val, priv->lms_base + MVPP2_PHY_AN_CFG0_REG);
5155 val = readl(priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5156 val &= ~MVPP22_SMI_POLLING_EN;
5157 writel(val, priv->iface_base + MVPP22_SMI_MISC_CFG_REG);
5160 /* Allocate and initialize aggregated TXQs */
5161 priv->aggr_txqs = devm_kcalloc(&pdev->dev, MVPP2_MAX_THREADS,
5162 sizeof(*priv->aggr_txqs),
5164 if (!priv->aggr_txqs)
5167 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
5168 priv->aggr_txqs[i].id = i;
5169 priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
5170 err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv);
5176 if (priv->hw_version == MVPP21) {
5177 mvpp2_rx_fifo_init(priv);
5179 mvpp22_rx_fifo_init(priv);
5180 mvpp22_tx_fifo_init(priv);
5183 if (priv->hw_version == MVPP21)
5184 writel(MVPP2_EXT_GLOBAL_CTRL_DEFAULT,
5185 priv->lms_base + MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG);
5187 /* Allow cache snoop when transmiting packets */
5188 mvpp2_write(priv, MVPP2_TX_SNOOP_REG, 0x1);
5190 /* Buffer Manager initialization */
5191 err = mvpp2_bm_init(pdev, priv);
5195 /* Parser default initialization */
5196 err = mvpp2_prs_default_init(pdev, priv);
5200 /* Classifier default initialization */
5201 mvpp2_cls_init(priv);
5206 static int mvpp2_probe(struct platform_device *pdev)
5208 const struct acpi_device_id *acpi_id;
5209 struct fwnode_handle *fwnode = pdev->dev.fwnode;
5210 struct fwnode_handle *port_fwnode;
5212 struct resource *res;
5217 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
5221 if (has_acpi_companion(&pdev->dev)) {
5222 acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
5224 priv->hw_version = (unsigned long)acpi_id->driver_data;
5227 (unsigned long)of_device_get_match_data(&pdev->dev);
5230 /* multi queue mode isn't supported on PPV2.1, fallback to single
5233 if (priv->hw_version == MVPP21)
5234 queue_mode = MVPP2_QDIST_SINGLE_MODE;
5236 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5237 base = devm_ioremap_resource(&pdev->dev, res);
5239 return PTR_ERR(base);
5241 if (priv->hw_version == MVPP21) {
5242 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
5243 priv->lms_base = devm_ioremap_resource(&pdev->dev, res);
5244 if (IS_ERR(priv->lms_base))
5245 return PTR_ERR(priv->lms_base);
5247 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
5248 if (has_acpi_companion(&pdev->dev)) {
5249 /* In case the MDIO memory region is declared in
5250 * the ACPI, it can already appear as 'in-use'
5251 * in the OS. Because it is overlapped by second
5252 * region of the network controller, make
5253 * sure it is released, before requesting it again.
5254 * The care is taken by mvpp2 driver to avoid
5255 * concurrent access to this memory region.
5257 release_resource(res);
5259 priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
5260 if (IS_ERR(priv->iface_base))
5261 return PTR_ERR(priv->iface_base);
5264 if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
5265 priv->sysctrl_base =
5266 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
5267 "marvell,system-controller");
5268 if (IS_ERR(priv->sysctrl_base))
5269 /* The system controller regmap is optional for dt
5270 * compatibility reasons. When not provided, the
5271 * configuration of the GoP relies on the
5272 * firmware/bootloader.
5274 priv->sysctrl_base = NULL;
5277 mvpp2_setup_bm_pool();
5280 priv->nthreads = min_t(unsigned int, num_present_cpus(),
5283 shared = num_present_cpus() - priv->nthreads;
5285 bitmap_fill(&priv->lock_map,
5286 min_t(int, shared, MVPP2_MAX_THREADS));
5288 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
5291 addr_space_sz = (priv->hw_version == MVPP21 ?
5292 MVPP21_ADDR_SPACE_SZ : MVPP22_ADDR_SPACE_SZ);
5293 priv->swth_base[i] = base + i * addr_space_sz;
5296 if (priv->hw_version == MVPP21)
5297 priv->max_port_rxqs = 8;
5299 priv->max_port_rxqs = 32;
5301 if (dev_of_node(&pdev->dev)) {
5302 priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
5303 if (IS_ERR(priv->pp_clk))
5304 return PTR_ERR(priv->pp_clk);
5305 err = clk_prepare_enable(priv->pp_clk);
5309 priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
5310 if (IS_ERR(priv->gop_clk)) {
5311 err = PTR_ERR(priv->gop_clk);
5314 err = clk_prepare_enable(priv->gop_clk);
5318 if (priv->hw_version == MVPP22) {
5319 priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
5320 if (IS_ERR(priv->mg_clk)) {
5321 err = PTR_ERR(priv->mg_clk);
5325 err = clk_prepare_enable(priv->mg_clk);
5329 priv->mg_core_clk = devm_clk_get(&pdev->dev, "mg_core_clk");
5330 if (IS_ERR(priv->mg_core_clk)) {
5331 priv->mg_core_clk = NULL;
5333 err = clk_prepare_enable(priv->mg_core_clk);
5339 priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
5340 if (IS_ERR(priv->axi_clk)) {
5341 err = PTR_ERR(priv->axi_clk);
5342 if (err == -EPROBE_DEFER)
5343 goto err_mg_core_clk;
5344 priv->axi_clk = NULL;
5346 err = clk_prepare_enable(priv->axi_clk);
5348 goto err_mg_core_clk;
5351 /* Get system's tclk rate */
5352 priv->tclk = clk_get_rate(priv->pp_clk);
5353 } else if (device_property_read_u32(&pdev->dev, "clock-frequency",
5355 dev_err(&pdev->dev, "missing clock-frequency value\n");
5359 if (priv->hw_version == MVPP22) {
5360 err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
5363 /* Sadly, the BM pools all share the same register to
5364 * store the high 32 bits of their address. So they
5365 * must all have the same high 32 bits, which forces
5366 * us to restrict coherent memory to DMA_BIT_MASK(32).
5368 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
5373 /* Initialize network controller */
5374 err = mvpp2_init(pdev, priv);
5376 dev_err(&pdev->dev, "failed to initialize controller\n");
5380 /* Initialize ports */
5381 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
5382 err = mvpp2_port_probe(pdev, port_fwnode, priv);
5384 goto err_port_probe;
5387 if (priv->port_count == 0) {
5388 dev_err(&pdev->dev, "no ports enabled\n");
5393 /* Statistics must be gathered regularly because some of them (like
5394 * packets counters) are 32-bit registers and could overflow quite
5395 * quickly. For instance, a 10Gb link used at full bandwidth with the
5396 * smallest packets (64B) will overflow a 32-bit counter in less than
5397 * 30 seconds. Then, use a workqueue to fill 64-bit counters.
5399 snprintf(priv->queue_name, sizeof(priv->queue_name),
5400 "stats-wq-%s%s", netdev_name(priv->port_list[0]->dev),
5401 priv->port_count > 1 ? "+" : "");
5402 priv->stats_queue = create_singlethread_workqueue(priv->queue_name);
5403 if (!priv->stats_queue) {
5405 goto err_port_probe;
5408 mvpp2_dbgfs_init(priv, pdev->name);
5410 platform_set_drvdata(pdev, priv);
5415 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
5416 if (priv->port_list[i])
5417 mvpp2_port_remove(priv->port_list[i]);
5421 clk_disable_unprepare(priv->axi_clk);
5424 if (priv->hw_version == MVPP22)
5425 clk_disable_unprepare(priv->mg_core_clk);
5427 if (priv->hw_version == MVPP22)
5428 clk_disable_unprepare(priv->mg_clk);
5430 clk_disable_unprepare(priv->gop_clk);
5432 clk_disable_unprepare(priv->pp_clk);
5436 static int mvpp2_remove(struct platform_device *pdev)
5438 struct mvpp2 *priv = platform_get_drvdata(pdev);
5439 struct fwnode_handle *fwnode = pdev->dev.fwnode;
5440 struct fwnode_handle *port_fwnode;
5443 mvpp2_dbgfs_cleanup(priv);
5445 flush_workqueue(priv->stats_queue);
5446 destroy_workqueue(priv->stats_queue);
5448 fwnode_for_each_available_child_node(fwnode, port_fwnode) {
5449 if (priv->port_list[i]) {
5450 mutex_destroy(&priv->port_list[i]->gather_stats_lock);
5451 mvpp2_port_remove(priv->port_list[i]);
5456 for (i = 0; i < MVPP2_BM_POOLS_NUM; i++) {
5457 struct mvpp2_bm_pool *bm_pool = &priv->bm_pools[i];
5459 mvpp2_bm_pool_destroy(pdev, priv, bm_pool);
5462 for (i = 0; i < MVPP2_MAX_THREADS; i++) {
5463 struct mvpp2_tx_queue *aggr_txq = &priv->aggr_txqs[i];
5465 dma_free_coherent(&pdev->dev,
5466 MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
5468 aggr_txq->descs_dma);
5471 if (is_acpi_node(port_fwnode))
5474 clk_disable_unprepare(priv->axi_clk);
5475 clk_disable_unprepare(priv->mg_core_clk);
5476 clk_disable_unprepare(priv->mg_clk);
5477 clk_disable_unprepare(priv->pp_clk);
5478 clk_disable_unprepare(priv->gop_clk);
5483 static const struct of_device_id mvpp2_match[] = {
5485 .compatible = "marvell,armada-375-pp2",
5486 .data = (void *)MVPP21,
5489 .compatible = "marvell,armada-7k-pp22",
5490 .data = (void *)MVPP22,
5494 MODULE_DEVICE_TABLE(of, mvpp2_match);
5496 static const struct acpi_device_id mvpp2_acpi_match[] = {
5497 { "MRVL0110", MVPP22 },
5500 MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match);
5502 static struct platform_driver mvpp2_driver = {
5503 .probe = mvpp2_probe,
5504 .remove = mvpp2_remove,
5506 .name = MVPP2_DRIVER_NAME,
5507 .of_match_table = mvpp2_match,
5508 .acpi_match_table = ACPI_PTR(mvpp2_acpi_match),
5512 module_platform_driver(mvpp2_driver);
5514 MODULE_DESCRIPTION("Marvell PPv2 Ethernet Driver - www.marvell.com");
5515 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
5516 MODULE_LICENSE("GPL v2");