1 /* SPDX-License-Identifier: GPL-2.0
2 * Marvell OcteonTx2 RVU Admin Function driver
4 * Copyright (C) 2018 Marvell International Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
14 #include <linux/pci.h>
15 #include "rvu_struct.h"
20 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
22 /* Subsystem Device ID */
23 #define PCI_SUBSYS_DEVID_96XX 0xB200
26 #define PCI_AF_REG_BAR_NUM 0
27 #define PCI_PF_REG_BAR_NUM 2
28 #define PCI_MBOX_BAR_NUM 4
33 #define RVU_PFVF_PF_SHIFT 10
34 #define RVU_PFVF_PF_MASK 0x3F
35 #define RVU_PFVF_FUNC_SHIFT 0
36 #define RVU_PFVF_FUNC_MASK 0x3FF
38 #ifdef CONFIG_DEBUG_FS
47 struct dentry *cgx_root;
52 struct dump_ctx npa_aura_ctx;
53 struct dump_ctx npa_pool_ctx;
54 struct dump_ctx nix_cq_ctx;
55 struct dump_ctx nix_rq_ctx;
56 struct dump_ctx nix_sq_ctx;
63 struct work_struct work;
68 unsigned long *bmap; /* Pointer to resource bitmap */
69 u16 max; /* Max resource id or count */
74 struct admin_queue *aq; /* NIX/NPA AQ */
75 u16 *fn_map; /* LF to pcifunc mapping */
78 u8 addr; /* RVU_BLOCK_ADDR_E */
79 u8 type; /* RVU_BLOCK_TYPE_E */
87 unsigned char name[NAME_SIZE];
92 struct qmem *mcast_buf;
95 struct mutex mce_lock; /* Serialize MCE updates */
99 struct hlist_head head;
105 struct rsrc_bmap counters;
106 struct mutex lock; /* MCAM entries and counters update lock */
107 unsigned long *bmap; /* bitmap, 0 => bmap_entries */
108 unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */
109 u16 bmap_entries; /* Number of unreserved MCAM entries */
110 u16 bmap_fcnt; /* MCAM entries free count */
115 u8 keysize; /* MCAM keysize 112/224/448 bits */
116 u8 banks; /* Number of MCAM banks */
117 u8 banks_per_entry;/* Number of keywords in key */
118 u16 banksize; /* Number of MCAM entries in each bank */
119 u16 total_entries; /* Total number of MCAM entries */
120 u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */
121 u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */
128 /* Structure for per RVU func info ie PF/VF */
130 bool npalf; /* Only one NPALF per RVU_FUNC */
131 bool nixlf; /* Only one NIXLF per RVU_FUNC */
138 /* Block LF's MSIX vector info */
139 struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */
140 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
141 u16 *msix_lfmap; /* Vector to block LF mapping */
144 struct qmem *aura_ctx;
145 struct qmem *pool_ctx;
146 struct qmem *npa_qints_ctx;
147 unsigned long *aura_bmap;
148 unsigned long *pool_bmap;
154 struct qmem *rss_ctx;
155 struct qmem *cq_ints_ctx;
156 struct qmem *nix_qints_ctx;
157 unsigned long *sq_bmap;
158 unsigned long *rq_bmap;
159 unsigned long *cq_bmap;
163 u8 rx_chan_cnt; /* total number of RX channels */
164 u8 tx_chan_cnt; /* total number of TX channels */
168 u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
170 /* Broadcast pkt replication info */
172 struct nix_mce_list bcast_mce_list;
175 struct mcam_entry entry;
181 struct rsrc_bmap schq;
183 #define NIX_TXSCHQ_TL1_CFG_DONE BIT_ULL(0)
184 #define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF)
185 #define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16)
186 #define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16))
190 struct nix_mark_format {
197 struct rsrc_bmap rsrc;
202 #define NIX_FLOW_KEY_ALG_MAX 32
203 u32 flowkey[NIX_FLOW_KEY_ALG_MAX];
213 struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
214 struct nix_mcast mcast;
215 struct nix_flowkey flowkey;
216 struct nix_mark_format mark_format;
221 u8 total_pfs; /* MAX RVU PFs HW supports */
222 u16 total_vfs; /* Max RVU VFs HW supports */
223 u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */
229 u8 npc_kpus; /* No of parser units */
232 struct rvu_block block[BLK_COUNT]; /* Block info */
234 struct npc_pkind pkind;
235 struct npc_mcam mcam;
238 struct mbox_wq_info {
239 struct otx2_mbox mbox;
240 struct rvu_work *mbox_wrk;
242 struct otx2_mbox mbox_up;
243 struct rvu_work *mbox_wrk_up;
245 struct workqueue_struct *mbox_wq;
249 void __iomem *afreg_base;
250 void __iomem *pfreg_base;
251 struct pci_dev *pdev;
253 struct rvu_hwinfo *hw;
255 struct rvu_pfvf *hwvf;
256 struct mutex rsrc_lock; /* Serialize resource alloc/free */
257 int vfs; /* Number of VFs attached to RVU */
260 struct mbox_wq_info afpf_wq_info;
261 struct mbox_wq_info afvf_wq_info;
264 struct rvu_work *flr_wrk;
265 struct workqueue_struct *flr_wq;
266 struct mutex flr_lock; /* Serialize FLRs */
272 dma_addr_t msix_base_iova;
275 #define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */
277 u8 cgx_cnt_max; /* CGX port count max */
278 u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */
279 u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for
280 * every cgx lmac port
282 unsigned long pf_notify_bmap; /* Flags for PF notification */
283 void **cgx_idmap; /* cgx id to cgx data map table */
284 struct work_struct cgx_evh_work;
285 struct workqueue_struct *cgx_evh_wq;
286 spinlock_t cgx_evq_lock; /* cgx event queue lock */
287 struct list_head cgx_evq_head; /* cgx event queue head */
289 char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */
291 #ifdef CONFIG_DEBUG_FS
292 struct rvu_debugfs rvu_dbg;
296 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
298 writeq(val, rvu->afreg_base + ((block << 28) | offset));
301 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
303 return readq(rvu->afreg_base + ((block << 28) | offset));
306 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
308 writeq(val, rvu->pfreg_base + offset);
311 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
313 return readq(rvu->pfreg_base + offset);
316 static inline bool is_rvu_9xxx_A0(struct rvu *rvu)
318 struct pci_dev *pdev = rvu->pdev;
320 return (pdev->revision == 0x00) &&
321 (pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX);
324 /* Function Prototypes
327 static inline int is_afvf(u16 pcifunc)
329 return !(pcifunc & ~RVU_PFVF_FUNC_MASK);
332 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
333 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
334 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
335 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
336 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
337 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
338 int rvu_get_pf(u16 pcifunc);
339 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
340 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
341 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
342 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype);
343 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
344 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
345 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
346 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
348 /* RVU HW reg validation */
354 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
356 /* NPA/NIX AQ APIs */
357 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
358 int qsize, int inst_size, int res_size);
359 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
362 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
364 return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs);
367 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
369 *cgx_id = (map >> 4) & 0xF;
370 *lmac_id = (map & 0xF);
373 int rvu_cgx_init(struct rvu *rvu);
374 int rvu_cgx_exit(struct rvu *rvu);
375 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
376 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
377 int rvu_mbox_handler_cgx_start_rxtx(struct rvu *rvu, struct msg_req *req,
378 struct msg_rsp *rsp);
379 int rvu_mbox_handler_cgx_stop_rxtx(struct rvu *rvu, struct msg_req *req,
380 struct msg_rsp *rsp);
381 int rvu_mbox_handler_cgx_stats(struct rvu *rvu, struct msg_req *req,
382 struct cgx_stats_rsp *rsp);
383 int rvu_mbox_handler_cgx_mac_addr_set(struct rvu *rvu,
384 struct cgx_mac_addr_set_or_get *req,
385 struct cgx_mac_addr_set_or_get *rsp);
386 int rvu_mbox_handler_cgx_mac_addr_get(struct rvu *rvu,
387 struct cgx_mac_addr_set_or_get *req,
388 struct cgx_mac_addr_set_or_get *rsp);
389 int rvu_mbox_handler_cgx_promisc_enable(struct rvu *rvu, struct msg_req *req,
390 struct msg_rsp *rsp);
391 int rvu_mbox_handler_cgx_promisc_disable(struct rvu *rvu, struct msg_req *req,
392 struct msg_rsp *rsp);
393 int rvu_mbox_handler_cgx_start_linkevents(struct rvu *rvu, struct msg_req *req,
394 struct msg_rsp *rsp);
395 int rvu_mbox_handler_cgx_stop_linkevents(struct rvu *rvu, struct msg_req *req,
396 struct msg_rsp *rsp);
397 int rvu_mbox_handler_cgx_get_linkinfo(struct rvu *rvu, struct msg_req *req,
398 struct cgx_link_info_msg *rsp);
399 int rvu_mbox_handler_cgx_intlbk_enable(struct rvu *rvu, struct msg_req *req,
400 struct msg_rsp *rsp);
401 int rvu_mbox_handler_cgx_intlbk_disable(struct rvu *rvu, struct msg_req *req,
402 struct msg_rsp *rsp);
405 int rvu_npa_init(struct rvu *rvu);
406 void rvu_npa_freemem(struct rvu *rvu);
407 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf);
408 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
409 struct npa_aq_enq_rsp *rsp);
410 int rvu_mbox_handler_npa_aq_enq(struct rvu *rvu,
411 struct npa_aq_enq_req *req,
412 struct npa_aq_enq_rsp *rsp);
413 int rvu_mbox_handler_npa_hwctx_disable(struct rvu *rvu,
414 struct hwctx_disable_req *req,
415 struct msg_rsp *rsp);
416 int rvu_mbox_handler_npa_lf_alloc(struct rvu *rvu,
417 struct npa_lf_alloc_req *req,
418 struct npa_lf_alloc_rsp *rsp);
419 int rvu_mbox_handler_npa_lf_free(struct rvu *rvu, struct msg_req *req,
420 struct msg_rsp *rsp);
423 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc);
424 int rvu_nix_init(struct rvu *rvu);
425 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
426 int blkaddr, u32 cfg);
427 void rvu_nix_freemem(struct rvu *rvu);
428 int rvu_get_nixlf_count(struct rvu *rvu);
429 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
430 int rvu_mbox_handler_nix_lf_alloc(struct rvu *rvu,
431 struct nix_lf_alloc_req *req,
432 struct nix_lf_alloc_rsp *rsp);
433 int rvu_mbox_handler_nix_lf_free(struct rvu *rvu, struct msg_req *req,
434 struct msg_rsp *rsp);
435 int rvu_mbox_handler_nix_aq_enq(struct rvu *rvu,
436 struct nix_aq_enq_req *req,
437 struct nix_aq_enq_rsp *rsp);
438 int rvu_mbox_handler_nix_hwctx_disable(struct rvu *rvu,
439 struct hwctx_disable_req *req,
440 struct msg_rsp *rsp);
441 int rvu_mbox_handler_nix_txsch_alloc(struct rvu *rvu,
442 struct nix_txsch_alloc_req *req,
443 struct nix_txsch_alloc_rsp *rsp);
444 int rvu_mbox_handler_nix_txsch_free(struct rvu *rvu,
445 struct nix_txsch_free_req *req,
446 struct msg_rsp *rsp);
447 int rvu_mbox_handler_nix_txschq_cfg(struct rvu *rvu,
448 struct nix_txschq_config *req,
449 struct msg_rsp *rsp);
450 int rvu_mbox_handler_nix_stats_rst(struct rvu *rvu, struct msg_req *req,
451 struct msg_rsp *rsp);
452 int rvu_mbox_handler_nix_vtag_cfg(struct rvu *rvu,
453 struct nix_vtag_config *req,
454 struct msg_rsp *rsp);
455 int rvu_mbox_handler_nix_rxvlan_alloc(struct rvu *rvu, struct msg_req *req,
456 struct msg_rsp *rsp);
457 int rvu_mbox_handler_nix_rss_flowkey_cfg(struct rvu *rvu,
458 struct nix_rss_flowkey_cfg *req,
459 struct nix_rss_flowkey_cfg_rsp *rsp);
460 int rvu_mbox_handler_nix_set_mac_addr(struct rvu *rvu,
461 struct nix_set_mac_addr *req,
462 struct msg_rsp *rsp);
463 int rvu_mbox_handler_nix_set_rx_mode(struct rvu *rvu, struct nix_rx_mode *req,
464 struct msg_rsp *rsp);
465 int rvu_mbox_handler_nix_set_hw_frs(struct rvu *rvu, struct nix_frs_cfg *req,
466 struct msg_rsp *rsp);
467 int rvu_mbox_handler_nix_lf_start_rx(struct rvu *rvu, struct msg_req *req,
468 struct msg_rsp *rsp);
469 int rvu_mbox_handler_nix_lf_stop_rx(struct rvu *rvu, struct msg_req *req,
470 struct msg_rsp *rsp);
471 int rvu_mbox_handler_nix_mark_format_cfg(struct rvu *rvu,
472 struct nix_mark_format_cfg *req,
473 struct nix_mark_format_cfg_rsp *rsp);
474 int rvu_mbox_handler_nix_set_rx_cfg(struct rvu *rvu, struct nix_rx_cfg *req,
475 struct msg_rsp *rsp);
476 int rvu_mbox_handler_nix_lso_format_cfg(struct rvu *rvu,
477 struct nix_lso_format_cfg *req,
478 struct nix_lso_format_cfg_rsp *rsp);
481 int rvu_npc_init(struct rvu *rvu);
482 void rvu_npc_freemem(struct rvu *rvu);
483 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
484 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
485 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
486 int nixlf, u64 chan, u8 *mac_addr);
487 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
488 int nixlf, u64 chan, bool allmulti);
489 void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf);
490 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf);
491 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
492 int nixlf, u64 chan);
493 int rvu_npc_update_rxvlan(struct rvu *rvu, u16 pcifunc, int nixlf);
494 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
495 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
496 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
497 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
498 int group, int alg_idx, int mcam_index);
499 int rvu_mbox_handler_npc_mcam_alloc_entry(struct rvu *rvu,
500 struct npc_mcam_alloc_entry_req *req,
501 struct npc_mcam_alloc_entry_rsp *rsp);
502 int rvu_mbox_handler_npc_mcam_free_entry(struct rvu *rvu,
503 struct npc_mcam_free_entry_req *req,
504 struct msg_rsp *rsp);
505 int rvu_mbox_handler_npc_mcam_write_entry(struct rvu *rvu,
506 struct npc_mcam_write_entry_req *req,
507 struct msg_rsp *rsp);
508 int rvu_mbox_handler_npc_mcam_ena_entry(struct rvu *rvu,
509 struct npc_mcam_ena_dis_entry_req *req,
510 struct msg_rsp *rsp);
511 int rvu_mbox_handler_npc_mcam_dis_entry(struct rvu *rvu,
512 struct npc_mcam_ena_dis_entry_req *req,
513 struct msg_rsp *rsp);
514 int rvu_mbox_handler_npc_mcam_shift_entry(struct rvu *rvu,
515 struct npc_mcam_shift_entry_req *req,
516 struct npc_mcam_shift_entry_rsp *rsp);
517 int rvu_mbox_handler_npc_mcam_alloc_counter(struct rvu *rvu,
518 struct npc_mcam_alloc_counter_req *req,
519 struct npc_mcam_alloc_counter_rsp *rsp);
520 int rvu_mbox_handler_npc_mcam_free_counter(struct rvu *rvu,
521 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp);
522 int rvu_mbox_handler_npc_mcam_clear_counter(struct rvu *rvu,
523 struct npc_mcam_oper_counter_req *req, struct msg_rsp *rsp);
524 int rvu_mbox_handler_npc_mcam_unmap_counter(struct rvu *rvu,
525 struct npc_mcam_unmap_counter_req *req, struct msg_rsp *rsp);
526 int rvu_mbox_handler_npc_mcam_counter_stats(struct rvu *rvu,
527 struct npc_mcam_oper_counter_req *req,
528 struct npc_mcam_oper_counter_rsp *rsp);
529 int rvu_mbox_handler_npc_mcam_alloc_and_write_entry(struct rvu *rvu,
530 struct npc_mcam_alloc_and_write_entry_req *req,
531 struct npc_mcam_alloc_and_write_entry_rsp *rsp);
532 int rvu_mbox_handler_npc_get_kex_cfg(struct rvu *rvu, struct msg_req *req,
533 struct npc_get_kex_cfg_rsp *rsp);
535 #ifdef CONFIG_DEBUG_FS
536 void rvu_dbg_init(struct rvu *rvu);
537 void rvu_dbg_exit(struct rvu *rvu);
539 static inline void rvu_dbg_init(struct rvu *rvu) {}
540 static inline void rvu_dbg_exit(struct rvu *rvu) {}