2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
37 #include <linux/slab.h>
39 #include <linux/tcp.h>
41 #include <linux/delay.h>
42 #include <linux/workqueue.h>
43 #include <linux/if_vlan.h>
44 #include <linux/prefetch.h>
45 #include <linux/debugfs.h>
46 #include <linux/mii.h>
47 #include <linux/of_device.h>
48 #include <linux/of_net.h>
49 #include <linux/dmi.h>
55 #define DRV_NAME "sky2"
56 #define DRV_VERSION "1.30"
59 * The Yukon II chipset takes 64 bit command blocks (called list elements)
60 * that are organized into three (receive, transmit, status) different rings
64 #define RX_LE_SIZE 1024
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
69 /* This is the worst case number of transmit list elements for a single skb:
70 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
71 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
72 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
73 #define TX_MAX_PENDING 1024
74 #define TX_DEF_PENDING 63
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
82 #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93 static int copybreak __read_mostly = 128;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97 static int disable_msi = -1;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101 static int legacy_pme = 0;
102 module_param(legacy_pme, int, 0);
103 MODULE_PARM_DESC(legacy_pme, "Legacy power management");
105 static const struct pci_device_id sky2_id_table[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
108 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
111 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
112 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
144 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
145 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
146 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
147 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4382) }, /* 88E8079 */
151 MODULE_DEVICE_TABLE(pci, sky2_id_table);
153 /* Avoid conditionals by using array */
154 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
155 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
156 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
158 static void sky2_set_multicast(struct net_device *dev);
159 static irqreturn_t sky2_intr(int irq, void *dev_id);
161 /* Access to PHY via serial interconnect */
162 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
166 gma_write16(hw, port, GM_SMI_DATA, val);
167 gma_write16(hw, port, GM_SMI_CTRL,
168 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
170 for (i = 0; i < PHY_RETRIES; i++) {
171 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
175 if (!(ctrl & GM_SMI_CT_BUSY))
181 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
185 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
189 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
193 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
194 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
196 for (i = 0; i < PHY_RETRIES; i++) {
197 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
201 if (ctrl & GM_SMI_CT_RD_VAL) {
202 *val = gma_read16(hw, port, GM_SMI_DATA);
209 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
212 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
216 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
219 __gm_phy_read(hw, port, reg, &v);
224 static void sky2_power_on(struct sky2_hw *hw)
226 /* switch power to VCC (WA for VAUX problem) */
227 sky2_write8(hw, B0_POWER_CTRL,
228 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
230 /* disable Core Clock Division, */
231 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
233 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
234 /* enable bits are inverted */
235 sky2_write8(hw, B2_Y2_CLK_GATE,
236 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
237 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
238 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
240 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
242 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
245 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
247 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
248 /* set all bits to 0 except bits 15..12 and 8 */
249 reg &= P_ASPM_CONTROL_MSK;
250 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
252 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
253 /* set all bits to 0 except bits 28 & 27 */
254 reg &= P_CTL_TIM_VMAIN_AV_MSK;
255 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
257 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
259 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
261 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
262 reg = sky2_read32(hw, B2_GP_IO);
263 reg |= GLB_GPIO_STAT_RACE_DIS;
264 sky2_write32(hw, B2_GP_IO, reg);
266 sky2_read32(hw, B2_GP_IO);
269 /* Turn on "driver loaded" LED */
270 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
273 static void sky2_power_aux(struct sky2_hw *hw)
275 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
276 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
278 /* enable bits are inverted */
279 sky2_write8(hw, B2_Y2_CLK_GATE,
280 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
281 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
282 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
284 /* switch power to VAUX if supported and PME from D3cold */
285 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
286 pci_pme_capable(hw->pdev, PCI_D3cold))
287 sky2_write8(hw, B0_POWER_CTRL,
288 (PC_VAUX_ENA | PC_VCC_ENA |
289 PC_VAUX_ON | PC_VCC_OFF));
291 /* turn off "driver loaded LED" */
292 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
295 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
299 /* disable all GMAC IRQ's */
300 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
302 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
303 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
304 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
305 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
307 reg = gma_read16(hw, port, GM_RX_CTRL);
308 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
309 gma_write16(hw, port, GM_RX_CTRL, reg);
312 /* flow control to advertise bits */
313 static const u16 copper_fc_adv[] = {
315 [FC_TX] = PHY_M_AN_ASP,
316 [FC_RX] = PHY_M_AN_PC,
317 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
320 /* flow control to advertise bits when using 1000BaseX */
321 static const u16 fiber_fc_adv[] = {
322 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
323 [FC_TX] = PHY_M_P_ASYM_MD_X,
324 [FC_RX] = PHY_M_P_SYM_MD_X,
325 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
328 /* flow control to GMA disable bits */
329 static const u16 gm_fc_disable[] = {
330 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
331 [FC_TX] = GM_GPCR_FC_RX_DIS,
332 [FC_RX] = GM_GPCR_FC_TX_DIS,
337 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
339 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
340 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
342 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
343 !(hw->flags & SKY2_HW_NEWER_PHY)) {
344 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
346 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
348 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
350 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
351 if (hw->chip_id == CHIP_ID_YUKON_EC)
352 /* set downshift counter to 3x and enable downshift */
353 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
355 /* set master & slave downshift counter to 1x */
356 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
358 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
361 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
362 if (sky2_is_copper(hw)) {
363 if (!(hw->flags & SKY2_HW_GIGABIT)) {
364 /* enable automatic crossover */
365 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
367 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
368 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
371 /* Enable Class A driver for FE+ A0 */
372 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
373 spec |= PHY_M_FESC_SEL_CL_A;
374 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
377 /* disable energy detect */
378 ctrl &= ~PHY_M_PC_EN_DET_MSK;
380 /* enable automatic crossover */
381 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
383 /* downshift on PHY 88E1112 and 88E1149 is changed */
384 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
385 (hw->flags & SKY2_HW_NEWER_PHY)) {
386 /* set downshift counter to 3x and enable downshift */
387 ctrl &= ~PHY_M_PC_DSC_MSK;
388 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
392 /* workaround for deviation #4.88 (CRC errors) */
393 /* disable Automatic Crossover */
395 ctrl &= ~PHY_M_PC_MDIX_MSK;
398 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
400 /* special setup for PHY 88E1112 Fiber */
401 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
402 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
404 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
406 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
407 ctrl &= ~PHY_M_MAC_MD_MSK;
408 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
409 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
411 if (hw->pmd_type == 'P') {
412 /* select page 1 to access Fiber registers */
413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
415 /* for SFP-module set SIGDET polarity to low */
416 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
417 ctrl |= PHY_M_FIB_SIGD_POL;
418 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
421 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
429 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
430 if (sky2_is_copper(hw)) {
431 if (sky2->advertising & ADVERTISED_1000baseT_Full)
432 ct1000 |= PHY_M_1000C_AFD;
433 if (sky2->advertising & ADVERTISED_1000baseT_Half)
434 ct1000 |= PHY_M_1000C_AHD;
435 if (sky2->advertising & ADVERTISED_100baseT_Full)
436 adv |= PHY_M_AN_100_FD;
437 if (sky2->advertising & ADVERTISED_100baseT_Half)
438 adv |= PHY_M_AN_100_HD;
439 if (sky2->advertising & ADVERTISED_10baseT_Full)
440 adv |= PHY_M_AN_10_FD;
441 if (sky2->advertising & ADVERTISED_10baseT_Half)
442 adv |= PHY_M_AN_10_HD;
444 } else { /* special defines for FIBER (88E1040S only) */
445 if (sky2->advertising & ADVERTISED_1000baseT_Full)
446 adv |= PHY_M_AN_1000X_AFD;
447 if (sky2->advertising & ADVERTISED_1000baseT_Half)
448 adv |= PHY_M_AN_1000X_AHD;
451 /* Restart Auto-negotiation */
452 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
454 /* forced speed/duplex settings */
455 ct1000 = PHY_M_1000C_MSE;
457 /* Disable auto update for duplex flow control and duplex */
458 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
460 switch (sky2->speed) {
462 ctrl |= PHY_CT_SP1000;
463 reg |= GM_GPCR_SPEED_1000;
466 ctrl |= PHY_CT_SP100;
467 reg |= GM_GPCR_SPEED_100;
471 if (sky2->duplex == DUPLEX_FULL) {
472 reg |= GM_GPCR_DUP_FULL;
473 ctrl |= PHY_CT_DUP_MD;
474 } else if (sky2->speed < SPEED_1000)
475 sky2->flow_mode = FC_NONE;
478 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
479 if (sky2_is_copper(hw))
480 adv |= copper_fc_adv[sky2->flow_mode];
482 adv |= fiber_fc_adv[sky2->flow_mode];
484 reg |= GM_GPCR_AU_FCT_DIS;
485 reg |= gm_fc_disable[sky2->flow_mode];
487 /* Forward pause packets to GMAC? */
488 if (sky2->flow_mode & FC_RX)
489 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
491 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
494 gma_write16(hw, port, GM_GP_CTRL, reg);
496 if (hw->flags & SKY2_HW_GIGABIT)
497 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
499 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
500 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
502 /* Setup Phy LED's */
503 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
506 switch (hw->chip_id) {
507 case CHIP_ID_YUKON_FE:
508 /* on 88E3082 these bits are at 11..9 (shifted left) */
509 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
511 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
513 /* delete ACT LED control bits */
514 ctrl &= ~PHY_M_FELP_LED1_MSK;
515 /* change ACT LED control to blink mode */
516 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
517 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
520 case CHIP_ID_YUKON_FE_P:
521 /* Enable Link Partner Next Page */
522 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
523 ctrl |= PHY_M_PC_ENA_LIP_NP;
525 /* disable Energy Detect and enable scrambler */
526 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
527 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
529 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
530 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
531 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
532 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
534 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
537 case CHIP_ID_YUKON_XL:
538 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
540 /* select page 3 to access LED control register */
541 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
543 /* set LED Function Control register */
544 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
545 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
546 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
547 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
548 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
550 /* set Polarity Control register */
551 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
552 (PHY_M_POLC_LS1_P_MIX(4) |
553 PHY_M_POLC_IS0_P_MIX(4) |
554 PHY_M_POLC_LOS_CTRL(2) |
555 PHY_M_POLC_INIT_CTRL(2) |
556 PHY_M_POLC_STA1_CTRL(2) |
557 PHY_M_POLC_STA0_CTRL(2)));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
563 case CHIP_ID_YUKON_EC_U:
564 case CHIP_ID_YUKON_EX:
565 case CHIP_ID_YUKON_SUPR:
566 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
568 /* select page 3 to access LED control register */
569 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
571 /* set LED Function Control register */
572 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
573 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
574 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
575 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
576 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
578 /* set Blink Rate in LED Timer Control Register */
579 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
580 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
581 /* restore page register */
582 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
586 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
587 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
589 /* turn off the Rx LED (LED_RX) */
590 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
593 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
594 /* apply fixes in PHY AFE */
595 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
597 /* increase differential signal amplitude in 10BASE-T */
598 gm_phy_write(hw, port, 0x18, 0xaa99);
599 gm_phy_write(hw, port, 0x17, 0x2011);
601 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
602 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
603 gm_phy_write(hw, port, 0x18, 0xa204);
604 gm_phy_write(hw, port, 0x17, 0x2002);
607 /* set page register to 0 */
608 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
609 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
610 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
611 /* apply workaround for integrated resistors calibration */
612 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
613 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
614 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
615 /* apply fixes in PHY AFE */
616 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
618 /* apply RDAC termination workaround */
619 gm_phy_write(hw, port, 24, 0x2800);
620 gm_phy_write(hw, port, 23, 0x2001);
622 /* set page register back to 0 */
623 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
624 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
625 hw->chip_id < CHIP_ID_YUKON_SUPR) {
626 /* no effect on Yukon-XL */
627 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
629 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
630 sky2->speed == SPEED_100) {
631 /* turn on 100 Mbps LED (LED_LINK100) */
632 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
636 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
638 } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
639 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
641 /* This a phy register setup workaround copied from vendor driver. */
642 static const struct {
648 /* { 0x155, 0x130b },*/
654 /* { 0x154, 0x2f39 },*/
658 /* { 0x158, 0x1223 },*/
665 /* Start Workaround for OptimaEEE Rev.Z0 */
666 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
668 gm_phy_write(hw, port, 1, 0x4099);
669 gm_phy_write(hw, port, 3, 0x1120);
670 gm_phy_write(hw, port, 11, 0x113c);
671 gm_phy_write(hw, port, 14, 0x8100);
672 gm_phy_write(hw, port, 15, 0x112a);
673 gm_phy_write(hw, port, 17, 0x1008);
675 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
676 gm_phy_write(hw, port, 1, 0x20b0);
678 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
680 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
681 /* apply AFE settings */
682 gm_phy_write(hw, port, 17, eee_afe[i].val);
683 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
686 /* End Workaround for OptimaEEE */
687 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
689 /* Enable 10Base-Te (EEE) */
690 if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
691 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
692 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
693 reg | PHY_M_10B_TE_ENABLE);
697 /* Enable phy interrupt on auto-negotiation complete (or link up) */
698 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
699 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
701 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
704 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
705 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
707 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
711 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
712 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
713 reg1 &= ~phy_power[port];
715 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
716 reg1 |= coma_mode[port];
718 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
719 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
720 sky2_pci_read32(hw, PCI_DEV_REG1);
722 if (hw->chip_id == CHIP_ID_YUKON_FE)
723 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
724 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
725 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
728 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
733 /* release GPHY Control reset */
734 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
736 /* release GMAC reset */
737 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
739 if (hw->flags & SKY2_HW_NEWER_PHY) {
740 /* select page 2 to access MAC control register */
741 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
743 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
744 /* allow GMII Power Down */
745 ctrl &= ~PHY_M_MAC_GMIF_PUP;
746 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
748 /* set page register back to 0 */
749 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
752 /* setup General Purpose Control Register */
753 gma_write16(hw, port, GM_GP_CTRL,
754 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
755 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
758 if (hw->chip_id != CHIP_ID_YUKON_EC) {
759 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
760 /* select page 2 to access MAC control register */
761 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
763 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
764 /* enable Power Down */
765 ctrl |= PHY_M_PC_POW_D_ENA;
766 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
768 /* set page register back to 0 */
769 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
772 /* set IEEE compatible Power Down Mode (dev. #4.99) */
773 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
776 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
777 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
778 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
779 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
780 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
783 /* configure IPG according to used link speed */
784 static void sky2_set_ipg(struct sky2_port *sky2)
788 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
789 reg &= ~GM_SMOD_IPG_MSK;
790 if (sky2->speed > SPEED_100)
791 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
793 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
794 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
798 static void sky2_enable_rx_tx(struct sky2_port *sky2)
800 struct sky2_hw *hw = sky2->hw;
801 unsigned port = sky2->port;
804 reg = gma_read16(hw, port, GM_GP_CTRL);
805 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
806 gma_write16(hw, port, GM_GP_CTRL, reg);
809 /* Force a renegotiation */
810 static void sky2_phy_reinit(struct sky2_port *sky2)
812 spin_lock_bh(&sky2->phy_lock);
813 sky2_phy_init(sky2->hw, sky2->port);
814 sky2_enable_rx_tx(sky2);
815 spin_unlock_bh(&sky2->phy_lock);
818 /* Put device in state to listen for Wake On Lan */
819 static void sky2_wol_init(struct sky2_port *sky2)
821 struct sky2_hw *hw = sky2->hw;
822 unsigned port = sky2->port;
823 enum flow_control save_mode;
826 /* Bring hardware out of reset */
827 sky2_write16(hw, B0_CTST, CS_RST_CLR);
828 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
830 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
831 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
834 * sky2_reset will re-enable on resume
836 save_mode = sky2->flow_mode;
837 ctrl = sky2->advertising;
839 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
840 sky2->flow_mode = FC_NONE;
842 spin_lock_bh(&sky2->phy_lock);
843 sky2_phy_power_up(hw, port);
844 sky2_phy_init(hw, port);
845 spin_unlock_bh(&sky2->phy_lock);
847 sky2->flow_mode = save_mode;
848 sky2->advertising = ctrl;
850 /* Set GMAC to no flow control and auto update for speed/duplex */
851 gma_write16(hw, port, GM_GP_CTRL,
852 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
853 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
855 /* Set WOL address */
856 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
857 sky2->netdev->dev_addr, ETH_ALEN);
859 /* Turn on appropriate WOL control bits */
860 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
862 if (sky2->wol & WAKE_PHY)
863 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
865 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
867 if (sky2->wol & WAKE_MAGIC)
868 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
870 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
872 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
873 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
875 /* Disable PiG firmware */
876 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
878 /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */
880 u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
881 reg1 |= PCI_Y2_PME_LEGACY;
882 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
886 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
887 sky2_read32(hw, B0_CTST);
890 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
892 struct net_device *dev = hw->dev[port];
894 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
895 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
896 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
897 /* Yukon-Extreme B0 and further Extreme devices */
898 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
899 } else if (dev->mtu > ETH_DATA_LEN) {
900 /* set Tx GMAC FIFO Almost Empty Threshold */
901 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
902 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
904 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
906 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
909 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
911 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
915 const u8 *addr = hw->dev[port]->dev_addr;
917 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
918 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
920 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
922 if (hw->chip_id == CHIP_ID_YUKON_XL &&
923 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
925 /* WA DEV_472 -- looks like crossed wires on port 2 */
926 /* clear GMAC 1 Control reset */
927 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
929 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
930 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
931 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
932 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
933 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
936 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
938 /* Enable Transmit FIFO Underrun */
939 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
941 spin_lock_bh(&sky2->phy_lock);
942 sky2_phy_power_up(hw, port);
943 sky2_phy_init(hw, port);
944 spin_unlock_bh(&sky2->phy_lock);
947 reg = gma_read16(hw, port, GM_PHY_ADDR);
948 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
950 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
951 gma_read16(hw, port, i);
952 gma_write16(hw, port, GM_PHY_ADDR, reg);
954 /* transmit control */
955 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
957 /* receive control reg: unicast + multicast + no FCS */
958 gma_write16(hw, port, GM_RX_CTRL,
959 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
961 /* transmit flow control */
962 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
964 /* transmit parameter */
965 gma_write16(hw, port, GM_TX_PARAM,
966 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
967 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
968 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
969 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
971 /* serial mode register */
972 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
973 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
975 if (hw->dev[port]->mtu > ETH_DATA_LEN)
976 reg |= GM_SMOD_JUMBO_ENA;
978 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
979 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
980 reg |= GM_NEW_FLOW_CTRL;
982 gma_write16(hw, port, GM_SERIAL_MODE, reg);
984 /* virtual address for data */
985 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
987 /* physical address: used for pause frames */
988 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
990 /* ignore counter overflows */
991 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
992 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
993 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
995 /* Configure Rx MAC FIFO */
996 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
997 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
998 if (hw->chip_id == CHIP_ID_YUKON_EX ||
999 hw->chip_id == CHIP_ID_YUKON_FE_P)
1000 rx_reg |= GMF_RX_OVER_ON;
1002 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
1004 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1005 /* Hardware errata - clear flush mask */
1006 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
1008 /* Flush Rx MAC FIFO on any flow control or error */
1009 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
1012 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
1013 reg = RX_GMF_FL_THR_DEF + 1;
1014 /* Another magic mystery workaround from sk98lin */
1015 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1016 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1018 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
1020 /* Configure Tx MAC FIFO */
1021 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1022 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1024 /* On chips without ram buffer, pause is controlled by MAC level */
1025 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
1026 /* Pause threshold is scaled by 8 in bytes */
1027 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1028 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1032 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1033 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
1035 sky2_set_tx_stfwd(hw, port);
1038 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1039 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1040 /* disable dynamic watermark */
1041 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1042 reg &= ~TX_DYN_WM_ENA;
1043 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1047 /* Assign Ram Buffer allocation to queue */
1048 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
1052 /* convert from K bytes to qwords used for hw register */
1055 end = start + space - 1;
1057 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1058 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1059 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1060 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1061 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1063 if (q == Q_R1 || q == Q_R2) {
1064 u32 tp = space - space/4;
1066 /* On receive queue's set the thresholds
1067 * give receiver priority when > 3/4 full
1068 * send pause when down to 2K
1070 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1071 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1073 tp = space - 8192/8;
1074 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1075 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1077 /* Enable store & forward on Tx queue's because
1078 * Tx FIFO is only 1K on Yukon
1080 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1083 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
1084 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1087 /* Setup Bus Memory Interface */
1088 static void sky2_qset(struct sky2_hw *hw, u16 q)
1090 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1091 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1092 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1093 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1096 /* Setup prefetch unit registers. This is the interface between
1097 * hardware and driver list elements
1099 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1100 dma_addr_t addr, u32 last)
1102 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1103 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1104 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1105 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1106 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1107 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1109 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1112 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1114 struct sky2_tx_le *le = sky2->tx_le + *slot;
1116 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1121 static void tx_init(struct sky2_port *sky2)
1123 struct sky2_tx_le *le;
1125 sky2->tx_prod = sky2->tx_cons = 0;
1126 sky2->tx_tcpsum = 0;
1127 sky2->tx_last_mss = 0;
1128 netdev_reset_queue(sky2->netdev);
1130 le = get_tx_le(sky2, &sky2->tx_prod);
1132 le->opcode = OP_ADDR64 | HW_OWNER;
1133 sky2->tx_last_upper = 0;
1136 /* Update chip's next pointer */
1137 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1139 /* Make sure write' to descriptors are complete before we tell hardware */
1141 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1145 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1147 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1148 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1153 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1157 /* Space needed for frame data + headers rounded up */
1158 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1160 /* Stopping point for hardware truncation */
1161 return (size - 8) / sizeof(u32);
1164 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1166 struct rx_ring_info *re;
1169 /* Space needed for frame data + headers rounded up */
1170 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1172 sky2->rx_nfrags = size >> PAGE_SHIFT;
1173 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1175 /* Compute residue after pages */
1176 size -= sky2->rx_nfrags << PAGE_SHIFT;
1178 /* Optimize to handle small packets and headers */
1179 if (size < copybreak)
1181 if (size < ETH_HLEN)
1187 /* Build description to hardware for one receive segment */
1188 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1189 dma_addr_t map, unsigned len)
1191 struct sky2_rx_le *le;
1193 if (sizeof(dma_addr_t) > sizeof(u32)) {
1194 le = sky2_next_rx(sky2);
1195 le->addr = cpu_to_le32(upper_32_bits(map));
1196 le->opcode = OP_ADDR64 | HW_OWNER;
1199 le = sky2_next_rx(sky2);
1200 le->addr = cpu_to_le32(lower_32_bits(map));
1201 le->length = cpu_to_le16(len);
1202 le->opcode = op | HW_OWNER;
1205 /* Build description to hardware for one possibly fragmented skb */
1206 static void sky2_rx_submit(struct sky2_port *sky2,
1207 const struct rx_ring_info *re)
1211 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1213 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1214 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1218 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1221 struct sk_buff *skb = re->skb;
1224 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1225 if (pci_dma_mapping_error(pdev, re->data_addr))
1228 dma_unmap_len_set(re, data_size, size);
1230 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1231 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1233 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0,
1234 skb_frag_size(frag),
1237 if (dma_mapping_error(&pdev->dev, re->frag_addr[i]))
1238 goto map_page_error;
1244 pci_unmap_page(pdev, re->frag_addr[i],
1245 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1246 PCI_DMA_FROMDEVICE);
1249 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1250 PCI_DMA_FROMDEVICE);
1253 if (net_ratelimit())
1254 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1259 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1261 struct sk_buff *skb = re->skb;
1264 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1265 PCI_DMA_FROMDEVICE);
1267 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1268 pci_unmap_page(pdev, re->frag_addr[i],
1269 skb_frag_size(&skb_shinfo(skb)->frags[i]),
1270 PCI_DMA_FROMDEVICE);
1273 /* Tell chip where to start receive checksum.
1274 * Actually has two checksums, but set both same to avoid possible byte
1277 static void rx_set_checksum(struct sky2_port *sky2)
1279 struct sky2_rx_le *le = sky2_next_rx(sky2);
1281 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1283 le->opcode = OP_TCPSTART | HW_OWNER;
1285 sky2_write32(sky2->hw,
1286 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1287 (sky2->netdev->features & NETIF_F_RXCSUM)
1288 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1291 /* Enable/disable receive hash calculation (RSS) */
1292 static void rx_set_rss(struct net_device *dev, netdev_features_t features)
1294 struct sky2_port *sky2 = netdev_priv(dev);
1295 struct sky2_hw *hw = sky2->hw;
1298 /* Supports IPv6 and other modes */
1299 if (hw->flags & SKY2_HW_NEW_LE) {
1301 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1304 /* Program RSS initial values */
1305 if (features & NETIF_F_RXHASH) {
1308 netdev_rss_key_fill(rss_key, sizeof(rss_key));
1309 for (i = 0; i < nkeys; i++)
1310 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1313 /* Need to turn on (undocumented) flag to make hashing work */
1314 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1317 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1318 BMU_ENA_RX_RSS_HASH);
1320 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1321 BMU_DIS_RX_RSS_HASH);
1325 * The RX Stop command will not work for Yukon-2 if the BMU does not
1326 * reach the end of packet and since we can't make sure that we have
1327 * incoming data, we must reset the BMU while it is not doing a DMA
1328 * transfer. Since it is possible that the RX path is still active,
1329 * the RX RAM buffer will be stopped first, so any possible incoming
1330 * data will not trigger a DMA. After the RAM buffer is stopped, the
1331 * BMU is polled until any DMA in progress is ended and only then it
1334 static void sky2_rx_stop(struct sky2_port *sky2)
1336 struct sky2_hw *hw = sky2->hw;
1337 unsigned rxq = rxqaddr[sky2->port];
1340 /* disable the RAM Buffer receive queue */
1341 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1343 for (i = 0; i < 0xffff; i++)
1344 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1345 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1348 netdev_warn(sky2->netdev, "receiver stop failed\n");
1350 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1352 /* reset the Rx prefetch unit */
1353 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1356 /* Clean out receive buffer area, assumes receiver hardware stopped */
1357 static void sky2_rx_clean(struct sky2_port *sky2)
1362 memset(sky2->rx_le, 0, RX_LE_BYTES);
1364 for (i = 0; i < sky2->rx_pending; i++) {
1365 struct rx_ring_info *re = sky2->rx_ring + i;
1368 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1375 /* Basic MII support */
1376 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1378 struct mii_ioctl_data *data = if_mii(ifr);
1379 struct sky2_port *sky2 = netdev_priv(dev);
1380 struct sky2_hw *hw = sky2->hw;
1381 int err = -EOPNOTSUPP;
1383 if (!netif_running(dev))
1384 return -ENODEV; /* Phy still in reset */
1388 data->phy_id = PHY_ADDR_MARV;
1394 spin_lock_bh(&sky2->phy_lock);
1395 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1396 spin_unlock_bh(&sky2->phy_lock);
1398 data->val_out = val;
1403 spin_lock_bh(&sky2->phy_lock);
1404 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1406 spin_unlock_bh(&sky2->phy_lock);
1412 #define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
1414 static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features)
1416 struct sky2_port *sky2 = netdev_priv(dev);
1417 struct sky2_hw *hw = sky2->hw;
1418 u16 port = sky2->port;
1420 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1421 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1424 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1427 if (features & NETIF_F_HW_VLAN_CTAG_TX) {
1428 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1431 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1433 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1436 /* Can't do transmit offload of vlan without hw vlan */
1437 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
1441 /* Amount of required worst case padding in rx buffer */
1442 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1444 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1448 * Allocate an skb for receiving. If the MTU is large enough
1449 * make the skb non-linear with a fragment list of pages.
1451 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
1453 struct sk_buff *skb;
1456 skb = __netdev_alloc_skb(sky2->netdev,
1457 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1462 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1463 unsigned char *start;
1465 * Workaround for a bug in FIFO that cause hang
1466 * if the FIFO if the receive buffer is not 64 byte aligned.
1467 * The buffer returned from netdev_alloc_skb is
1468 * aligned except if slab debugging is enabled.
1470 start = PTR_ALIGN(skb->data, 8);
1471 skb_reserve(skb, start - skb->data);
1473 skb_reserve(skb, NET_IP_ALIGN);
1475 for (i = 0; i < sky2->rx_nfrags; i++) {
1476 struct page *page = alloc_page(gfp);
1480 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1490 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1492 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1495 static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1497 struct sky2_hw *hw = sky2->hw;
1500 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1503 for (i = 0; i < sky2->rx_pending; i++) {
1504 struct rx_ring_info *re = sky2->rx_ring + i;
1506 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
1510 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1511 dev_kfree_skb(re->skb);
1520 * Setup receiver buffer pool.
1521 * Normal case this ends up creating one list element for skb
1522 * in the receive ring. Worst case if using large MTU and each
1523 * allocation falls on a different 64 bit region, that results
1524 * in 6 list elements per ring entry.
1525 * One element is used for checksum enable/disable, and one
1526 * extra to avoid wrap.
1528 static void sky2_rx_start(struct sky2_port *sky2)
1530 struct sky2_hw *hw = sky2->hw;
1531 struct rx_ring_info *re;
1532 unsigned rxq = rxqaddr[sky2->port];
1535 sky2->rx_put = sky2->rx_next = 0;
1538 /* On PCI express lowering the watermark gives better performance */
1539 if (pci_is_pcie(hw->pdev))
1540 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1542 /* These chips have no ram buffer?
1543 * MAC Rx RAM Read is controlled by hardware */
1544 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1545 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1546 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1548 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1550 if (!(hw->flags & SKY2_HW_NEW_LE))
1551 rx_set_checksum(sky2);
1553 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1554 rx_set_rss(sky2->netdev, sky2->netdev->features);
1556 /* submit Rx ring */
1557 for (i = 0; i < sky2->rx_pending; i++) {
1558 re = sky2->rx_ring + i;
1559 sky2_rx_submit(sky2, re);
1563 * The receiver hangs if it receives frames larger than the
1564 * packet buffer. As a workaround, truncate oversize frames, but
1565 * the register is limited to 9 bits, so if you do frames > 2052
1566 * you better get the MTU right!
1568 thresh = sky2_get_rx_threshold(sky2);
1570 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1572 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1573 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1576 /* Tell chip about available buffers */
1577 sky2_rx_update(sky2, rxq);
1579 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1580 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1582 * Disable flushing of non ASF packets;
1583 * must be done after initializing the BMUs;
1584 * drivers without ASF support should do this too, otherwise
1585 * it may happen that they cannot run on ASF devices;
1586 * remember that the MAC FIFO isn't reset during initialization.
1588 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1591 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1592 /* Enable RX Home Address & Routing Header checksum fix */
1593 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1594 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1596 /* Enable TX Home Address & Routing Header checksum fix */
1597 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1598 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1602 static int sky2_alloc_buffers(struct sky2_port *sky2)
1604 struct sky2_hw *hw = sky2->hw;
1606 /* must be power of 2 */
1607 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1608 sky2->tx_ring_size *
1609 sizeof(struct sky2_tx_le),
1614 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1619 sky2->rx_le = pci_zalloc_consistent(hw->pdev, RX_LE_BYTES,
1624 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1629 return sky2_alloc_rx_skbs(sky2);
1634 static void sky2_free_buffers(struct sky2_port *sky2)
1636 struct sky2_hw *hw = sky2->hw;
1638 sky2_rx_clean(sky2);
1641 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1642 sky2->rx_le, sky2->rx_le_map);
1646 pci_free_consistent(hw->pdev,
1647 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1648 sky2->tx_le, sky2->tx_le_map);
1651 kfree(sky2->tx_ring);
1652 kfree(sky2->rx_ring);
1654 sky2->tx_ring = NULL;
1655 sky2->rx_ring = NULL;
1658 static void sky2_hw_up(struct sky2_port *sky2)
1660 struct sky2_hw *hw = sky2->hw;
1661 unsigned port = sky2->port;
1664 struct net_device *otherdev = hw->dev[sky2->port^1];
1669 * On dual port PCI-X card, there is an problem where status
1670 * can be received out of order due to split transactions
1672 if (otherdev && netif_running(otherdev) &&
1673 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1676 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1677 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1678 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1681 sky2_mac_init(hw, port);
1683 /* Register is number of 4K blocks on internal RAM buffer. */
1684 ramsize = sky2_read8(hw, B2_E_0) * 4;
1688 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1690 rxspace = ramsize / 2;
1692 rxspace = 8 + (2*(ramsize - 16))/3;
1694 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1695 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1697 /* Make sure SyncQ is disabled */
1698 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1702 sky2_qset(hw, txqaddr[port]);
1704 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1705 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1706 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1708 /* Set almost empty threshold */
1709 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1710 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1711 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1713 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1714 sky2->tx_ring_size - 1);
1716 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1717 netdev_update_features(sky2->netdev);
1719 sky2_rx_start(sky2);
1722 /* Setup device IRQ and enable napi to process */
1723 static int sky2_setup_irq(struct sky2_hw *hw, const char *name)
1725 struct pci_dev *pdev = hw->pdev;
1728 err = request_irq(pdev->irq, sky2_intr,
1729 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
1732 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
1734 hw->flags |= SKY2_HW_IRQ_SETUP;
1736 napi_enable(&hw->napi);
1737 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
1738 sky2_read32(hw, B0_IMSK);
1745 /* Bring up network interface. */
1746 static int sky2_open(struct net_device *dev)
1748 struct sky2_port *sky2 = netdev_priv(dev);
1749 struct sky2_hw *hw = sky2->hw;
1750 unsigned port = sky2->port;
1754 netif_carrier_off(dev);
1756 err = sky2_alloc_buffers(sky2);
1760 /* With single port, IRQ is setup when device is brought up */
1761 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name)))
1766 /* Enable interrupts from phy/mac for port */
1767 imask = sky2_read32(hw, B0_IMSK);
1769 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
1770 hw->chip_id == CHIP_ID_YUKON_PRM ||
1771 hw->chip_id == CHIP_ID_YUKON_OP_2)
1772 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */
1774 imask |= portirq_msk[port];
1775 sky2_write32(hw, B0_IMSK, imask);
1776 sky2_read32(hw, B0_IMSK);
1778 netif_info(sky2, ifup, dev, "enabling interface\n");
1783 sky2_free_buffers(sky2);
1787 /* Modular subtraction in ring */
1788 static inline int tx_inuse(const struct sky2_port *sky2)
1790 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1793 /* Number of list elements available for next tx */
1794 static inline int tx_avail(const struct sky2_port *sky2)
1796 return sky2->tx_pending - tx_inuse(sky2);
1799 /* Estimate of number of transmit list elements required */
1800 static unsigned tx_le_req(const struct sk_buff *skb)
1804 count = (skb_shinfo(skb)->nr_frags + 1)
1805 * (sizeof(dma_addr_t) / sizeof(u32));
1807 if (skb_is_gso(skb))
1809 else if (sizeof(dma_addr_t) == sizeof(u32))
1810 ++count; /* possible vlan */
1812 if (skb->ip_summed == CHECKSUM_PARTIAL)
1818 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1820 if (re->flags & TX_MAP_SINGLE)
1821 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1822 dma_unmap_len(re, maplen),
1824 else if (re->flags & TX_MAP_PAGE)
1825 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1826 dma_unmap_len(re, maplen),
1832 * Put one packet in ring for transmit.
1833 * A single packet can generate multiple list elements, and
1834 * the number of ring elements will probably be less than the number
1835 * of list elements used.
1837 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1838 struct net_device *dev)
1840 struct sky2_port *sky2 = netdev_priv(dev);
1841 struct sky2_hw *hw = sky2->hw;
1842 struct sky2_tx_le *le = NULL;
1843 struct tx_ring_info *re;
1851 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1852 return NETDEV_TX_BUSY;
1854 len = skb_headlen(skb);
1855 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1857 if (pci_dma_mapping_error(hw->pdev, mapping))
1860 slot = sky2->tx_prod;
1861 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1862 "tx queued, slot %u, len %d\n", slot, skb->len);
1864 /* Send high bits if needed */
1865 upper = upper_32_bits(mapping);
1866 if (upper != sky2->tx_last_upper) {
1867 le = get_tx_le(sky2, &slot);
1868 le->addr = cpu_to_le32(upper);
1869 sky2->tx_last_upper = upper;
1870 le->opcode = OP_ADDR64 | HW_OWNER;
1873 /* Check for TCP Segmentation Offload */
1874 mss = skb_shinfo(skb)->gso_size;
1877 if (!(hw->flags & SKY2_HW_NEW_LE))
1878 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1880 if (mss != sky2->tx_last_mss) {
1881 le = get_tx_le(sky2, &slot);
1882 le->addr = cpu_to_le32(mss);
1884 if (hw->flags & SKY2_HW_NEW_LE)
1885 le->opcode = OP_MSS | HW_OWNER;
1887 le->opcode = OP_LRGLEN | HW_OWNER;
1888 sky2->tx_last_mss = mss;
1894 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1895 if (skb_vlan_tag_present(skb)) {
1897 le = get_tx_le(sky2, &slot);
1899 le->opcode = OP_VLAN|HW_OWNER;
1901 le->opcode |= OP_VLAN;
1902 le->length = cpu_to_be16(skb_vlan_tag_get(skb));
1906 /* Handle TCP checksum offload */
1907 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1908 /* On Yukon EX (some versions) encoding change. */
1909 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1910 ctrl |= CALSUM; /* auto checksum */
1912 const unsigned offset = skb_transport_offset(skb);
1915 tcpsum = offset << 16; /* sum start */
1916 tcpsum |= offset + skb->csum_offset; /* sum write */
1918 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1919 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1922 if (tcpsum != sky2->tx_tcpsum) {
1923 sky2->tx_tcpsum = tcpsum;
1925 le = get_tx_le(sky2, &slot);
1926 le->addr = cpu_to_le32(tcpsum);
1927 le->length = 0; /* initial checksum value */
1928 le->ctrl = 1; /* one packet */
1929 le->opcode = OP_TCPLISW | HW_OWNER;
1934 re = sky2->tx_ring + slot;
1935 re->flags = TX_MAP_SINGLE;
1936 dma_unmap_addr_set(re, mapaddr, mapping);
1937 dma_unmap_len_set(re, maplen, len);
1939 le = get_tx_le(sky2, &slot);
1940 le->addr = cpu_to_le32(lower_32_bits(mapping));
1941 le->length = cpu_to_le16(len);
1943 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1946 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1947 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1949 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
1950 skb_frag_size(frag), DMA_TO_DEVICE);
1952 if (dma_mapping_error(&hw->pdev->dev, mapping))
1953 goto mapping_unwind;
1955 upper = upper_32_bits(mapping);
1956 if (upper != sky2->tx_last_upper) {
1957 le = get_tx_le(sky2, &slot);
1958 le->addr = cpu_to_le32(upper);
1959 sky2->tx_last_upper = upper;
1960 le->opcode = OP_ADDR64 | HW_OWNER;
1963 re = sky2->tx_ring + slot;
1964 re->flags = TX_MAP_PAGE;
1965 dma_unmap_addr_set(re, mapaddr, mapping);
1966 dma_unmap_len_set(re, maplen, skb_frag_size(frag));
1968 le = get_tx_le(sky2, &slot);
1969 le->addr = cpu_to_le32(lower_32_bits(mapping));
1970 le->length = cpu_to_le16(skb_frag_size(frag));
1972 le->opcode = OP_BUFFER | HW_OWNER;
1978 sky2->tx_prod = slot;
1980 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1981 netif_stop_queue(dev);
1983 netdev_sent_queue(dev, skb->len);
1984 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1986 return NETDEV_TX_OK;
1989 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1990 re = sky2->tx_ring + i;
1992 sky2_tx_unmap(hw->pdev, re);
1996 if (net_ratelimit())
1997 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1998 dev_kfree_skb_any(skb);
1999 return NETDEV_TX_OK;
2003 * Free ring elements from starting at tx_cons until "done"
2006 * 1. The hardware will tell us about partial completion of multi-part
2007 * buffers so make sure not to free skb to early.
2008 * 2. This may run in parallel start_xmit because the it only
2009 * looks at the tail of the queue of FIFO (tx_cons), not
2010 * the head (tx_prod)
2012 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
2014 struct net_device *dev = sky2->netdev;
2016 unsigned int bytes_compl = 0, pkts_compl = 0;
2018 BUG_ON(done >= sky2->tx_ring_size);
2020 for (idx = sky2->tx_cons; idx != done;
2021 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
2022 struct tx_ring_info *re = sky2->tx_ring + idx;
2023 struct sk_buff *skb = re->skb;
2025 sky2_tx_unmap(sky2->hw->pdev, re);
2028 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
2029 "tx done %u\n", idx);
2032 bytes_compl += skb->len;
2035 dev_kfree_skb_any(skb);
2037 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
2041 sky2->tx_cons = idx;
2044 netdev_completed_queue(dev, pkts_compl, bytes_compl);
2046 u64_stats_update_begin(&sky2->tx_stats.syncp);
2047 sky2->tx_stats.packets += pkts_compl;
2048 sky2->tx_stats.bytes += bytes_compl;
2049 u64_stats_update_end(&sky2->tx_stats.syncp);
2052 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
2054 /* Disable Force Sync bit and Enable Alloc bit */
2055 sky2_write8(hw, SK_REG(port, TXA_CTRL),
2056 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2058 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2059 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2060 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2062 /* Reset the PCI FIFO of the async Tx queue */
2063 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2064 BMU_RST_SET | BMU_FIFO_RST);
2066 /* Reset the Tx prefetch units */
2067 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2070 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2071 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2073 sky2_read32(hw, B0_CTST);
2076 static void sky2_hw_down(struct sky2_port *sky2)
2078 struct sky2_hw *hw = sky2->hw;
2079 unsigned port = sky2->port;
2082 /* Force flow control off */
2083 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2085 /* Stop transmitter */
2086 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2087 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2089 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2090 RB_RST_SET | RB_DIS_OP_MD);
2092 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2093 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
2094 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2096 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2098 /* Workaround shared GMAC reset */
2099 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2100 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
2101 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2103 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2105 /* Force any delayed status interrupt and NAPI */
2106 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2107 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2108 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2109 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2113 spin_lock_bh(&sky2->phy_lock);
2114 sky2_phy_power_down(hw, port);
2115 spin_unlock_bh(&sky2->phy_lock);
2117 sky2_tx_reset(hw, port);
2119 /* Free any pending frames stuck in HW queue */
2120 sky2_tx_complete(sky2, sky2->tx_prod);
2123 /* Network shutdown */
2124 static int sky2_close(struct net_device *dev)
2126 struct sky2_port *sky2 = netdev_priv(dev);
2127 struct sky2_hw *hw = sky2->hw;
2129 /* Never really got started! */
2133 netif_info(sky2, ifdown, dev, "disabling interface\n");
2135 if (hw->ports == 1) {
2136 sky2_write32(hw, B0_IMSK, 0);
2137 sky2_read32(hw, B0_IMSK);
2139 napi_disable(&hw->napi);
2140 free_irq(hw->pdev->irq, hw);
2141 hw->flags &= ~SKY2_HW_IRQ_SETUP;
2145 /* Disable port IRQ */
2146 imask = sky2_read32(hw, B0_IMSK);
2147 imask &= ~portirq_msk[sky2->port];
2148 sky2_write32(hw, B0_IMSK, imask);
2149 sky2_read32(hw, B0_IMSK);
2151 synchronize_irq(hw->pdev->irq);
2152 napi_synchronize(&hw->napi);
2157 sky2_free_buffers(sky2);
2162 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2164 if (hw->flags & SKY2_HW_FIBRE_PHY)
2167 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2168 if (aux & PHY_M_PS_SPEED_100)
2174 switch (aux & PHY_M_PS_SPEED_MSK) {
2175 case PHY_M_PS_SPEED_1000:
2177 case PHY_M_PS_SPEED_100:
2184 static void sky2_link_up(struct sky2_port *sky2)
2186 struct sky2_hw *hw = sky2->hw;
2187 unsigned port = sky2->port;
2188 static const char *fc_name[] = {
2197 sky2_enable_rx_tx(sky2);
2199 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2201 netif_carrier_on(sky2->netdev);
2203 mod_timer(&hw->watchdog_timer, jiffies + 1);
2205 /* Turn on link LED */
2206 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2207 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2209 netif_info(sky2, link, sky2->netdev,
2210 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2212 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2213 fc_name[sky2->flow_status]);
2216 static void sky2_link_down(struct sky2_port *sky2)
2218 struct sky2_hw *hw = sky2->hw;
2219 unsigned port = sky2->port;
2222 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2224 reg = gma_read16(hw, port, GM_GP_CTRL);
2225 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2226 gma_write16(hw, port, GM_GP_CTRL, reg);
2228 netif_carrier_off(sky2->netdev);
2230 /* Turn off link LED */
2231 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2233 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2235 sky2_phy_init(hw, port);
2238 static enum flow_control sky2_flow(int rx, int tx)
2241 return tx ? FC_BOTH : FC_RX;
2243 return tx ? FC_TX : FC_NONE;
2246 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2248 struct sky2_hw *hw = sky2->hw;
2249 unsigned port = sky2->port;
2252 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2253 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2254 if (lpa & PHY_M_AN_RF) {
2255 netdev_err(sky2->netdev, "remote fault\n");
2259 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2260 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2264 sky2->speed = sky2_phy_speed(hw, aux);
2265 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2267 /* Since the pause result bits seem to in different positions on
2268 * different chips. look at registers.
2270 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2271 /* Shift for bits in fiber PHY */
2272 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2273 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2275 if (advert & ADVERTISE_1000XPAUSE)
2276 advert |= ADVERTISE_PAUSE_CAP;
2277 if (advert & ADVERTISE_1000XPSE_ASYM)
2278 advert |= ADVERTISE_PAUSE_ASYM;
2279 if (lpa & LPA_1000XPAUSE)
2280 lpa |= LPA_PAUSE_CAP;
2281 if (lpa & LPA_1000XPAUSE_ASYM)
2282 lpa |= LPA_PAUSE_ASYM;
2285 sky2->flow_status = FC_NONE;
2286 if (advert & ADVERTISE_PAUSE_CAP) {
2287 if (lpa & LPA_PAUSE_CAP)
2288 sky2->flow_status = FC_BOTH;
2289 else if (advert & ADVERTISE_PAUSE_ASYM)
2290 sky2->flow_status = FC_RX;
2291 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2292 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2293 sky2->flow_status = FC_TX;
2296 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2297 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2298 sky2->flow_status = FC_NONE;
2300 if (sky2->flow_status & FC_TX)
2301 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2303 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2308 /* Interrupt from PHY */
2309 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2311 struct net_device *dev = hw->dev[port];
2312 struct sky2_port *sky2 = netdev_priv(dev);
2313 u16 istatus, phystat;
2315 if (!netif_running(dev))
2318 spin_lock(&sky2->phy_lock);
2319 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2320 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2322 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2325 if (istatus & PHY_M_IS_AN_COMPL) {
2326 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2327 !netif_carrier_ok(dev))
2332 if (istatus & PHY_M_IS_LSP_CHANGE)
2333 sky2->speed = sky2_phy_speed(hw, phystat);
2335 if (istatus & PHY_M_IS_DUP_CHANGE)
2337 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2339 if (istatus & PHY_M_IS_LST_CHANGE) {
2340 if (phystat & PHY_M_PS_LINK_UP)
2343 sky2_link_down(sky2);
2346 spin_unlock(&sky2->phy_lock);
2349 /* Special quick link interrupt (Yukon-2 Optima only) */
2350 static void sky2_qlink_intr(struct sky2_hw *hw)
2352 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2357 imask = sky2_read32(hw, B0_IMSK);
2358 imask &= ~Y2_IS_PHY_QLNK;
2359 sky2_write32(hw, B0_IMSK, imask);
2361 /* reset PHY Link Detect */
2362 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2363 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2364 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2365 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2370 /* Transmit timeout is only called if we are running, carrier is up
2371 * and tx queue is full (stopped).
2373 static void sky2_tx_timeout(struct net_device *dev)
2375 struct sky2_port *sky2 = netdev_priv(dev);
2376 struct sky2_hw *hw = sky2->hw;
2378 netif_err(sky2, timer, dev, "tx timeout\n");
2380 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2381 sky2->tx_cons, sky2->tx_prod,
2382 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2383 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2385 /* can't restart safely under softirq */
2386 schedule_work(&hw->restart_work);
2389 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2391 struct sky2_port *sky2 = netdev_priv(dev);
2392 struct sky2_hw *hw = sky2->hw;
2393 unsigned port = sky2->port;
2398 if (!netif_running(dev)) {
2400 netdev_update_features(dev);
2404 imask = sky2_read32(hw, B0_IMSK);
2405 sky2_write32(hw, B0_IMSK, 0);
2406 sky2_read32(hw, B0_IMSK);
2408 netif_trans_update(dev); /* prevent tx timeout */
2409 napi_disable(&hw->napi);
2410 netif_tx_disable(dev);
2412 synchronize_irq(hw->pdev->irq);
2414 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2415 sky2_set_tx_stfwd(hw, port);
2417 ctl = gma_read16(hw, port, GM_GP_CTRL);
2418 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2420 sky2_rx_clean(sky2);
2423 netdev_update_features(dev);
2425 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
2426 if (sky2->speed > SPEED_100)
2427 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2429 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
2431 if (dev->mtu > ETH_DATA_LEN)
2432 mode |= GM_SMOD_JUMBO_ENA;
2434 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2436 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2438 err = sky2_alloc_rx_skbs(sky2);
2440 sky2_rx_start(sky2);
2442 sky2_rx_clean(sky2);
2443 sky2_write32(hw, B0_IMSK, imask);
2445 sky2_read32(hw, B0_Y2_SP_LISR);
2446 napi_enable(&hw->napi);
2451 gma_write16(hw, port, GM_GP_CTRL, ctl);
2453 netif_wake_queue(dev);
2459 static inline bool needs_copy(const struct rx_ring_info *re,
2462 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2463 /* Some architectures need the IP header to be aligned */
2464 if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32)))
2467 return length < copybreak;
2470 /* For small just reuse existing skb for next receive */
2471 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2472 const struct rx_ring_info *re,
2475 struct sk_buff *skb;
2477 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2479 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2480 length, PCI_DMA_FROMDEVICE);
2481 skb_copy_from_linear_data(re->skb, skb->data, length);
2482 skb->ip_summed = re->skb->ip_summed;
2483 skb->csum = re->skb->csum;
2484 skb_copy_hash(skb, re->skb);
2485 __vlan_hwaccel_copy_tag(skb, re->skb);
2487 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2488 length, PCI_DMA_FROMDEVICE);
2489 __vlan_hwaccel_clear_tag(re->skb);
2490 skb_clear_hash(re->skb);
2491 re->skb->ip_summed = CHECKSUM_NONE;
2492 skb_put(skb, length);
2497 /* Adjust length of skb with fragments to match received data */
2498 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2499 unsigned int length)
2504 /* put header into skb */
2505 size = min(length, hdr_space);
2510 num_frags = skb_shinfo(skb)->nr_frags;
2511 for (i = 0; i < num_frags; i++) {
2512 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2515 /* don't need this page */
2516 __skb_frag_unref(frag);
2517 --skb_shinfo(skb)->nr_frags;
2519 size = min(length, (unsigned) PAGE_SIZE);
2521 skb_frag_size_set(frag, size);
2522 skb->data_len += size;
2523 skb->truesize += PAGE_SIZE;
2530 /* Normal packet - take skb from ring element and put in a new one */
2531 static struct sk_buff *receive_new(struct sky2_port *sky2,
2532 struct rx_ring_info *re,
2533 unsigned int length)
2535 struct sk_buff *skb;
2536 struct rx_ring_info nre;
2537 unsigned hdr_space = sky2->rx_data_size;
2539 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
2540 if (unlikely(!nre.skb))
2543 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2547 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2548 prefetch(skb->data);
2551 if (skb_shinfo(skb)->nr_frags)
2552 skb_put_frags(skb, hdr_space, length);
2554 skb_put(skb, length);
2558 dev_kfree_skb(nre.skb);
2564 * Receive one packet.
2565 * For larger packets, get new buffer.
2567 static struct sk_buff *sky2_receive(struct net_device *dev,
2568 u16 length, u32 status)
2570 struct sky2_port *sky2 = netdev_priv(dev);
2571 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2572 struct sk_buff *skb = NULL;
2573 u16 count = (status & GMR_FS_LEN) >> 16;
2575 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2576 "rx slot %u status 0x%x len %d\n",
2577 sky2->rx_next, status, length);
2579 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2580 prefetch(sky2->rx_ring + sky2->rx_next);
2582 if (skb_vlan_tag_present(re->skb))
2583 count -= VLAN_HLEN; /* Account for vlan tag */
2585 /* This chip has hardware problems that generates bogus status.
2586 * So do only marginal checking and expect higher level protocols
2587 * to handle crap frames.
2589 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2590 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2594 if (status & GMR_FS_ANY_ERR)
2597 if (!(status & GMR_FS_RX_OK))
2600 /* if length reported by DMA does not match PHY, packet was truncated */
2601 if (length != count)
2605 if (needs_copy(re, length))
2606 skb = receive_copy(sky2, re, length);
2608 skb = receive_new(sky2, re, length);
2610 dev->stats.rx_dropped += (skb == NULL);
2613 sky2_rx_submit(sky2, re);
2618 ++dev->stats.rx_errors;
2620 if (net_ratelimit())
2621 netif_info(sky2, rx_err, dev,
2622 "rx error, status 0x%x length %d\n", status, length);
2627 /* Transmit complete */
2628 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2630 struct sky2_port *sky2 = netdev_priv(dev);
2632 if (netif_running(dev)) {
2633 sky2_tx_complete(sky2, last);
2635 /* Wake unless it's detached, and called e.g. from sky2_close() */
2636 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2637 netif_wake_queue(dev);
2641 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2642 struct sk_buff *skb)
2644 if (skb->ip_summed == CHECKSUM_NONE)
2645 netif_receive_skb(skb);
2647 napi_gro_receive(&sky2->hw->napi, skb);
2650 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2651 unsigned packets, unsigned bytes)
2653 struct net_device *dev = hw->dev[port];
2654 struct sky2_port *sky2 = netdev_priv(dev);
2659 u64_stats_update_begin(&sky2->rx_stats.syncp);
2660 sky2->rx_stats.packets += packets;
2661 sky2->rx_stats.bytes += bytes;
2662 u64_stats_update_end(&sky2->rx_stats.syncp);
2664 sky2->last_rx = jiffies;
2665 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2668 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2670 /* If this happens then driver assuming wrong format for chip type */
2671 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2673 /* Both checksum counters are programmed to start at
2674 * the same offset, so unless there is a problem they
2675 * should match. This failure is an early indication that
2676 * hardware receive checksumming won't work.
2678 if (likely((u16)(status >> 16) == (u16)status)) {
2679 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2680 skb->ip_summed = CHECKSUM_COMPLETE;
2681 skb->csum = le16_to_cpu(status);
2683 dev_notice(&sky2->hw->pdev->dev,
2684 "%s: receive checksum problem (status = %#x)\n",
2685 sky2->netdev->name, status);
2687 /* Disable checksum offload
2688 * It will be reenabled on next ndo_set_features, but if it's
2689 * really broken, will get disabled again
2691 sky2->netdev->features &= ~NETIF_F_RXCSUM;
2692 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2697 static void sky2_rx_tag(struct sky2_port *sky2, u16 length)
2699 struct sk_buff *skb;
2701 skb = sky2->rx_ring[sky2->rx_next].skb;
2702 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(length));
2705 static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2707 struct sk_buff *skb;
2709 skb = sky2->rx_ring[sky2->rx_next].skb;
2710 skb_set_hash(skb, le32_to_cpu(status), PKT_HASH_TYPE_L3);
2713 /* Process status response ring */
2714 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2717 unsigned int total_bytes[2] = { 0 };
2718 unsigned int total_packets[2] = { 0 };
2725 struct sky2_port *sky2;
2726 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2728 struct net_device *dev;
2729 struct sk_buff *skb;
2732 u8 opcode = le->opcode;
2734 if (!(opcode & HW_OWNER))
2737 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2739 port = le->css & CSS_LINK_BIT;
2740 dev = hw->dev[port];
2741 sky2 = netdev_priv(dev);
2742 length = le16_to_cpu(le->length);
2743 status = le32_to_cpu(le->status);
2746 switch (opcode & ~HW_OWNER) {
2748 total_packets[port]++;
2749 total_bytes[port] += length;
2751 skb = sky2_receive(dev, length, status);
2755 /* This chip reports checksum status differently */
2756 if (hw->flags & SKY2_HW_NEW_LE) {
2757 if ((dev->features & NETIF_F_RXCSUM) &&
2758 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2759 (le->css & CSS_TCPUDPCSOK))
2760 skb->ip_summed = CHECKSUM_UNNECESSARY;
2762 skb->ip_summed = CHECKSUM_NONE;
2765 skb->protocol = eth_type_trans(skb, dev);
2766 sky2_skb_rx(sky2, skb);
2768 /* Stop after net poll weight */
2769 if (++work_done >= to_do)
2774 sky2_rx_tag(sky2, length);
2778 sky2_rx_tag(sky2, length);
2781 if (likely(dev->features & NETIF_F_RXCSUM))
2782 sky2_rx_checksum(sky2, status);
2786 sky2_rx_hash(sky2, status);
2790 /* TX index reports status for both ports */
2791 sky2_tx_done(hw->dev[0], status & 0xfff);
2793 sky2_tx_done(hw->dev[1],
2794 ((status >> 24) & 0xff)
2795 | (u16)(length & 0xf) << 8);
2799 if (net_ratelimit())
2800 pr_warn("unknown status opcode 0x%x\n", opcode);
2802 } while (hw->st_idx != idx);
2804 /* Fully processed status ring so clear irq */
2805 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2808 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2809 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2814 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2816 struct net_device *dev = hw->dev[port];
2818 if (net_ratelimit())
2819 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2821 if (status & Y2_IS_PAR_RD1) {
2822 if (net_ratelimit())
2823 netdev_err(dev, "ram data read parity error\n");
2825 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2828 if (status & Y2_IS_PAR_WR1) {
2829 if (net_ratelimit())
2830 netdev_err(dev, "ram data write parity error\n");
2832 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2835 if (status & Y2_IS_PAR_MAC1) {
2836 if (net_ratelimit())
2837 netdev_err(dev, "MAC parity error\n");
2838 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2841 if (status & Y2_IS_PAR_RX1) {
2842 if (net_ratelimit())
2843 netdev_err(dev, "RX parity error\n");
2844 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2847 if (status & Y2_IS_TCP_TXA1) {
2848 if (net_ratelimit())
2849 netdev_err(dev, "TCP segmentation error\n");
2850 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2854 static void sky2_hw_intr(struct sky2_hw *hw)
2856 struct pci_dev *pdev = hw->pdev;
2857 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2858 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2862 if (status & Y2_IS_TIST_OV)
2863 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2865 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2868 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2869 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2870 if (net_ratelimit())
2871 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2874 sky2_pci_write16(hw, PCI_STATUS,
2875 pci_err | PCI_STATUS_ERROR_BITS);
2876 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2879 if (status & Y2_IS_PCI_EXP) {
2880 /* PCI-Express uncorrectable Error occurred */
2883 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2884 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2885 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2887 if (net_ratelimit())
2888 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2890 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2891 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2894 if (status & Y2_HWE_L1_MASK)
2895 sky2_hw_error(hw, 0, status);
2897 if (status & Y2_HWE_L1_MASK)
2898 sky2_hw_error(hw, 1, status);
2901 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2903 struct net_device *dev = hw->dev[port];
2904 struct sky2_port *sky2 = netdev_priv(dev);
2905 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2907 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2909 if (status & GM_IS_RX_CO_OV)
2910 gma_read16(hw, port, GM_RX_IRQ_SRC);
2912 if (status & GM_IS_TX_CO_OV)
2913 gma_read16(hw, port, GM_TX_IRQ_SRC);
2915 if (status & GM_IS_RX_FF_OR) {
2916 ++dev->stats.rx_fifo_errors;
2917 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2920 if (status & GM_IS_TX_FF_UR) {
2921 ++dev->stats.tx_fifo_errors;
2922 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2926 /* This should never happen it is a bug. */
2927 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2929 struct net_device *dev = hw->dev[port];
2930 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2932 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2933 dev->name, (unsigned) q, (unsigned) idx,
2934 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2936 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2939 static int sky2_rx_hung(struct net_device *dev)
2941 struct sky2_port *sky2 = netdev_priv(dev);
2942 struct sky2_hw *hw = sky2->hw;
2943 unsigned port = sky2->port;
2944 unsigned rxq = rxqaddr[port];
2945 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2946 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2947 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2948 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2950 /* If idle and MAC or PCI is stuck */
2951 if (sky2->check.last == sky2->last_rx &&
2952 ((mac_rp == sky2->check.mac_rp &&
2953 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2954 /* Check if the PCI RX hang */
2955 (fifo_rp == sky2->check.fifo_rp &&
2956 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2957 netdev_printk(KERN_DEBUG, dev,
2958 "hung mac %d:%d fifo %d (%d:%d)\n",
2959 mac_lev, mac_rp, fifo_lev,
2960 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2963 sky2->check.last = sky2->last_rx;
2964 sky2->check.mac_rp = mac_rp;
2965 sky2->check.mac_lev = mac_lev;
2966 sky2->check.fifo_rp = fifo_rp;
2967 sky2->check.fifo_lev = fifo_lev;
2972 static void sky2_watchdog(struct timer_list *t)
2974 struct sky2_hw *hw = from_timer(hw, t, watchdog_timer);
2976 /* Check for lost IRQ once a second */
2977 if (sky2_read32(hw, B0_ISRC)) {
2978 napi_schedule(&hw->napi);
2982 for (i = 0; i < hw->ports; i++) {
2983 struct net_device *dev = hw->dev[i];
2984 if (!netif_running(dev))
2988 /* For chips with Rx FIFO, check if stuck */
2989 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2990 sky2_rx_hung(dev)) {
2991 netdev_info(dev, "receiver hang detected\n");
2992 schedule_work(&hw->restart_work);
3001 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
3004 /* Hardware/software error handling */
3005 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
3007 if (net_ratelimit())
3008 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
3010 if (status & Y2_IS_HW_ERR)
3013 if (status & Y2_IS_IRQ_MAC1)
3014 sky2_mac_intr(hw, 0);
3016 if (status & Y2_IS_IRQ_MAC2)
3017 sky2_mac_intr(hw, 1);
3019 if (status & Y2_IS_CHK_RX1)
3020 sky2_le_error(hw, 0, Q_R1);
3022 if (status & Y2_IS_CHK_RX2)
3023 sky2_le_error(hw, 1, Q_R2);
3025 if (status & Y2_IS_CHK_TXA1)
3026 sky2_le_error(hw, 0, Q_XA1);
3028 if (status & Y2_IS_CHK_TXA2)
3029 sky2_le_error(hw, 1, Q_XA2);
3032 static int sky2_poll(struct napi_struct *napi, int work_limit)
3034 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
3035 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
3039 if (unlikely(status & Y2_IS_ERROR))
3040 sky2_err_intr(hw, status);
3042 if (status & Y2_IS_IRQ_PHY1)
3043 sky2_phy_intr(hw, 0);
3045 if (status & Y2_IS_IRQ_PHY2)
3046 sky2_phy_intr(hw, 1);
3048 if (status & Y2_IS_PHY_QLNK)
3049 sky2_qlink_intr(hw);
3051 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
3052 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
3054 if (work_done >= work_limit)
3058 napi_complete_done(napi, work_done);
3059 sky2_read32(hw, B0_Y2_SP_LISR);
3065 static irqreturn_t sky2_intr(int irq, void *dev_id)
3067 struct sky2_hw *hw = dev_id;
3070 /* Reading this mask interrupts as side effect */
3071 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3072 if (status == 0 || status == ~0) {
3073 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3077 prefetch(&hw->st_le[hw->st_idx]);
3079 napi_schedule(&hw->napi);
3084 #ifdef CONFIG_NET_POLL_CONTROLLER
3085 static void sky2_netpoll(struct net_device *dev)
3087 struct sky2_port *sky2 = netdev_priv(dev);
3089 napi_schedule(&sky2->hw->napi);
3093 /* Chip internal frequency for clock calculations */
3094 static u32 sky2_mhz(const struct sky2_hw *hw)
3096 switch (hw->chip_id) {
3097 case CHIP_ID_YUKON_EC:
3098 case CHIP_ID_YUKON_EC_U:
3099 case CHIP_ID_YUKON_EX:
3100 case CHIP_ID_YUKON_SUPR:
3101 case CHIP_ID_YUKON_UL_2:
3102 case CHIP_ID_YUKON_OPT:
3103 case CHIP_ID_YUKON_PRM:
3104 case CHIP_ID_YUKON_OP_2:
3107 case CHIP_ID_YUKON_FE:
3110 case CHIP_ID_YUKON_FE_P:
3113 case CHIP_ID_YUKON_XL:
3121 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
3123 return sky2_mhz(hw) * us;
3126 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
3128 return clk / sky2_mhz(hw);
3132 static int sky2_init(struct sky2_hw *hw)
3136 /* Enable all clocks and check for bad PCI access */
3137 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3139 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3141 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
3142 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3144 switch (hw->chip_id) {
3145 case CHIP_ID_YUKON_XL:
3146 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
3147 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3148 hw->flags |= SKY2_HW_RSS_BROKEN;
3151 case CHIP_ID_YUKON_EC_U:
3152 hw->flags = SKY2_HW_GIGABIT
3154 | SKY2_HW_ADV_POWER_CTL;
3157 case CHIP_ID_YUKON_EX:
3158 hw->flags = SKY2_HW_GIGABIT
3161 | SKY2_HW_ADV_POWER_CTL
3162 | SKY2_HW_RSS_CHKSUM;
3164 /* New transmit checksum */
3165 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3166 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3169 case CHIP_ID_YUKON_EC:
3170 /* This rev is really old, and requires untested workarounds */
3171 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3172 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3175 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3178 case CHIP_ID_YUKON_FE:
3179 hw->flags = SKY2_HW_RSS_BROKEN;
3182 case CHIP_ID_YUKON_FE_P:
3183 hw->flags = SKY2_HW_NEWER_PHY
3185 | SKY2_HW_AUTO_TX_SUM
3186 | SKY2_HW_ADV_POWER_CTL;
3188 /* The workaround for status conflicts VLAN tag detection. */
3189 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
3190 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
3193 case CHIP_ID_YUKON_SUPR:
3194 hw->flags = SKY2_HW_GIGABIT
3197 | SKY2_HW_AUTO_TX_SUM
3198 | SKY2_HW_ADV_POWER_CTL;
3200 if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3201 hw->flags |= SKY2_HW_RSS_CHKSUM;
3204 case CHIP_ID_YUKON_UL_2:
3205 hw->flags = SKY2_HW_GIGABIT
3206 | SKY2_HW_ADV_POWER_CTL;
3209 case CHIP_ID_YUKON_OPT:
3210 case CHIP_ID_YUKON_PRM:
3211 case CHIP_ID_YUKON_OP_2:
3212 hw->flags = SKY2_HW_GIGABIT
3214 | SKY2_HW_ADV_POWER_CTL;
3218 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3223 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3224 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3225 hw->flags |= SKY2_HW_FIBRE_PHY;
3228 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3229 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3230 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3234 if (sky2_read8(hw, B2_E_0))
3235 hw->flags |= SKY2_HW_RAM_BUFFER;
3240 static void sky2_reset(struct sky2_hw *hw)
3242 struct pci_dev *pdev = hw->pdev;
3245 u32 hwe_mask = Y2_HWE_ALL_MASK;
3248 if (hw->chip_id == CHIP_ID_YUKON_EX
3249 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3250 sky2_write32(hw, CPU_WDOG, 0);
3251 status = sky2_read16(hw, HCU_CCSR);
3252 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3253 HCU_CCSR_UC_STATE_MSK);
3255 * CPU clock divider shouldn't be used because
3256 * - ASF firmware may malfunction
3257 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3259 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3260 sky2_write16(hw, HCU_CCSR, status);
3261 sky2_write32(hw, CPU_WDOG, 0);
3263 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3264 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3267 sky2_write8(hw, B0_CTST, CS_RST_SET);
3268 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3270 /* allow writes to PCI config */
3271 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3273 /* clear PCI errors, if any */
3274 status = sky2_pci_read16(hw, PCI_STATUS);
3275 status |= PCI_STATUS_ERROR_BITS;
3276 sky2_pci_write16(hw, PCI_STATUS, status);
3278 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3280 if (pci_is_pcie(pdev)) {
3281 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3284 /* If error bit is stuck on ignore it */
3285 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3286 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3288 hwe_mask |= Y2_IS_PCI_EXP;
3292 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3294 for (i = 0; i < hw->ports; i++) {
3295 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3296 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3298 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3299 hw->chip_id == CHIP_ID_YUKON_SUPR)
3300 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3301 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3306 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3307 /* enable MACSec clock gating */
3308 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3311 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3312 hw->chip_id == CHIP_ID_YUKON_PRM ||
3313 hw->chip_id == CHIP_ID_YUKON_OP_2) {
3316 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
3317 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3318 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3320 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3323 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3324 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3326 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3330 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3331 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
3333 /* reset PHY Link Detect */
3334 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3335 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3337 /* check if PSMv2 was running before */
3338 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3339 if (reg & PCI_EXP_LNKCTL_ASPMC)
3340 /* restore the PCIe Link Control register */
3341 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3344 if (hw->chip_id == CHIP_ID_YUKON_PRM &&
3345 hw->chip_rev == CHIP_REV_YU_PRM_A0) {
3346 /* change PHY Interrupt polarity to low active */
3347 reg = sky2_read16(hw, GPHY_CTRL);
3348 sky2_write16(hw, GPHY_CTRL, reg | GPC_INTPOL);
3350 /* adapt HW for low active PHY Interrupt */
3351 reg = sky2_read16(hw, Y2_CFG_SPC + PCI_LDO_CTRL);
3352 sky2_write16(hw, Y2_CFG_SPC + PCI_LDO_CTRL, reg | PHY_M_UNDOC1);
3355 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3357 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3358 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3361 /* Clear I2C IRQ noise */
3362 sky2_write32(hw, B2_I2C_IRQ, 1);
3364 /* turn off hardware timer (unused) */
3365 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3366 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3368 /* Turn off descriptor polling */
3369 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3371 /* Turn off receive timestamp */
3372 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3373 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3375 /* enable the Tx Arbiters */
3376 for (i = 0; i < hw->ports; i++)
3377 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3379 /* Initialize ram interface */
3380 for (i = 0; i < hw->ports; i++) {
3381 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3383 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3384 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3385 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3386 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3387 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3388 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3389 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3390 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3391 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3392 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3393 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3394 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3397 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3399 for (i = 0; i < hw->ports; i++)
3400 sky2_gmac_reset(hw, i);
3402 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3405 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3406 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3408 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3409 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3411 /* Set the list last index */
3412 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3414 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3415 sky2_write8(hw, STAT_FIFO_WM, 16);
3417 /* set Status-FIFO ISR watermark */
3418 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3419 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3421 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3423 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3424 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3425 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3427 /* enable status unit */
3428 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3430 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3431 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3432 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3435 /* Take device down (offline).
3436 * Equivalent to doing dev_stop() but this does not
3437 * inform upper layers of the transition.
3439 static void sky2_detach(struct net_device *dev)
3441 if (netif_running(dev)) {
3443 netif_device_detach(dev); /* stop txq */
3444 netif_tx_unlock(dev);
3449 /* Bring device back after doing sky2_detach */
3450 static int sky2_reattach(struct net_device *dev)
3454 if (netif_running(dev)) {
3455 err = sky2_open(dev);
3457 netdev_info(dev, "could not restart %d\n", err);
3460 netif_device_attach(dev);
3461 sky2_set_multicast(dev);
3468 static void sky2_all_down(struct sky2_hw *hw)
3472 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3473 sky2_write32(hw, B0_IMSK, 0);
3474 sky2_read32(hw, B0_IMSK);
3476 synchronize_irq(hw->pdev->irq);
3477 napi_disable(&hw->napi);
3480 for (i = 0; i < hw->ports; i++) {
3481 struct net_device *dev = hw->dev[i];
3482 struct sky2_port *sky2 = netdev_priv(dev);
3484 if (!netif_running(dev))
3487 netif_carrier_off(dev);
3488 netif_tx_disable(dev);
3493 static void sky2_all_up(struct sky2_hw *hw)
3495 u32 imask = Y2_IS_BASE;
3498 for (i = 0; i < hw->ports; i++) {
3499 struct net_device *dev = hw->dev[i];
3500 struct sky2_port *sky2 = netdev_priv(dev);
3502 if (!netif_running(dev))
3506 sky2_set_multicast(dev);
3507 imask |= portirq_msk[i];
3508 netif_wake_queue(dev);
3511 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3512 sky2_write32(hw, B0_IMSK, imask);
3513 sky2_read32(hw, B0_IMSK);
3514 sky2_read32(hw, B0_Y2_SP_LISR);
3515 napi_enable(&hw->napi);
3519 static void sky2_restart(struct work_struct *work)
3521 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3532 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3534 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3537 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3539 const struct sky2_port *sky2 = netdev_priv(dev);
3541 wol->supported = sky2_wol_supported(sky2->hw);
3542 wol->wolopts = sky2->wol;
3545 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3547 struct sky2_port *sky2 = netdev_priv(dev);
3548 struct sky2_hw *hw = sky2->hw;
3549 bool enable_wakeup = false;
3552 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3553 !device_can_wakeup(&hw->pdev->dev))
3556 sky2->wol = wol->wolopts;
3558 for (i = 0; i < hw->ports; i++) {
3559 struct net_device *dev = hw->dev[i];
3560 struct sky2_port *sky2 = netdev_priv(dev);
3563 enable_wakeup = true;
3565 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3570 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3572 if (sky2_is_copper(hw)) {
3573 u32 modes = SUPPORTED_10baseT_Half
3574 | SUPPORTED_10baseT_Full
3575 | SUPPORTED_100baseT_Half
3576 | SUPPORTED_100baseT_Full;
3578 if (hw->flags & SKY2_HW_GIGABIT)
3579 modes |= SUPPORTED_1000baseT_Half
3580 | SUPPORTED_1000baseT_Full;
3583 return SUPPORTED_1000baseT_Half
3584 | SUPPORTED_1000baseT_Full;
3587 static int sky2_get_link_ksettings(struct net_device *dev,
3588 struct ethtool_link_ksettings *cmd)
3590 struct sky2_port *sky2 = netdev_priv(dev);
3591 struct sky2_hw *hw = sky2->hw;
3592 u32 supported, advertising;
3594 supported = sky2_supported_modes(hw);
3595 cmd->base.phy_address = PHY_ADDR_MARV;
3596 if (sky2_is_copper(hw)) {
3597 cmd->base.port = PORT_TP;
3598 cmd->base.speed = sky2->speed;
3599 supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
3601 cmd->base.speed = SPEED_1000;
3602 cmd->base.port = PORT_FIBRE;
3603 supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
3606 advertising = sky2->advertising;
3607 cmd->base.autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3608 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3609 cmd->base.duplex = sky2->duplex;
3611 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
3613 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
3619 static int sky2_set_link_ksettings(struct net_device *dev,
3620 const struct ethtool_link_ksettings *cmd)
3622 struct sky2_port *sky2 = netdev_priv(dev);
3623 const struct sky2_hw *hw = sky2->hw;
3624 u32 supported = sky2_supported_modes(hw);
3625 u32 new_advertising;
3627 ethtool_convert_link_mode_to_legacy_u32(&new_advertising,
3628 cmd->link_modes.advertising);
3630 if (cmd->base.autoneg == AUTONEG_ENABLE) {
3631 if (new_advertising & ~supported)
3634 if (sky2_is_copper(hw))
3635 sky2->advertising = new_advertising |
3639 sky2->advertising = new_advertising |
3643 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3648 u32 speed = cmd->base.speed;
3652 if (cmd->base.duplex == DUPLEX_FULL)
3653 setting = SUPPORTED_1000baseT_Full;
3654 else if (cmd->base.duplex == DUPLEX_HALF)
3655 setting = SUPPORTED_1000baseT_Half;
3660 if (cmd->base.duplex == DUPLEX_FULL)
3661 setting = SUPPORTED_100baseT_Full;
3662 else if (cmd->base.duplex == DUPLEX_HALF)
3663 setting = SUPPORTED_100baseT_Half;
3669 if (cmd->base.duplex == DUPLEX_FULL)
3670 setting = SUPPORTED_10baseT_Full;
3671 else if (cmd->base.duplex == DUPLEX_HALF)
3672 setting = SUPPORTED_10baseT_Half;
3680 if ((setting & supported) == 0)
3683 sky2->speed = speed;
3684 sky2->duplex = cmd->base.duplex;
3685 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3688 if (netif_running(dev)) {
3689 sky2_phy_reinit(sky2);
3690 sky2_set_multicast(dev);
3696 static void sky2_get_drvinfo(struct net_device *dev,
3697 struct ethtool_drvinfo *info)
3699 struct sky2_port *sky2 = netdev_priv(dev);
3701 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
3702 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
3703 strlcpy(info->bus_info, pci_name(sky2->hw->pdev),
3704 sizeof(info->bus_info));
3707 static const struct sky2_stat {
3708 char name[ETH_GSTRING_LEN];
3711 { "tx_bytes", GM_TXO_OK_HI },
3712 { "rx_bytes", GM_RXO_OK_HI },
3713 { "tx_broadcast", GM_TXF_BC_OK },
3714 { "rx_broadcast", GM_RXF_BC_OK },
3715 { "tx_multicast", GM_TXF_MC_OK },
3716 { "rx_multicast", GM_RXF_MC_OK },
3717 { "tx_unicast", GM_TXF_UC_OK },
3718 { "rx_unicast", GM_RXF_UC_OK },
3719 { "tx_mac_pause", GM_TXF_MPAUSE },
3720 { "rx_mac_pause", GM_RXF_MPAUSE },
3721 { "collisions", GM_TXF_COL },
3722 { "late_collision",GM_TXF_LAT_COL },
3723 { "aborted", GM_TXF_ABO_COL },
3724 { "single_collisions", GM_TXF_SNG_COL },
3725 { "multi_collisions", GM_TXF_MUL_COL },
3727 { "rx_short", GM_RXF_SHT },
3728 { "rx_runt", GM_RXE_FRAG },
3729 { "rx_64_byte_packets", GM_RXF_64B },
3730 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3731 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3732 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3733 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3734 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3735 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3736 { "rx_too_long", GM_RXF_LNG_ERR },
3737 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3738 { "rx_jabber", GM_RXF_JAB_PKT },
3739 { "rx_fcs_error", GM_RXF_FCS_ERR },
3741 { "tx_64_byte_packets", GM_TXF_64B },
3742 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3743 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3744 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3745 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3746 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3747 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3748 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3751 static u32 sky2_get_msglevel(struct net_device *netdev)
3753 struct sky2_port *sky2 = netdev_priv(netdev);
3754 return sky2->msg_enable;
3757 static int sky2_nway_reset(struct net_device *dev)
3759 struct sky2_port *sky2 = netdev_priv(dev);
3761 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3764 sky2_phy_reinit(sky2);
3765 sky2_set_multicast(dev);
3770 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3772 struct sky2_hw *hw = sky2->hw;
3773 unsigned port = sky2->port;
3776 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3777 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3779 for (i = 2; i < count; i++)
3780 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3783 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3785 struct sky2_port *sky2 = netdev_priv(netdev);
3786 sky2->msg_enable = value;
3789 static int sky2_get_sset_count(struct net_device *dev, int sset)
3793 return ARRAY_SIZE(sky2_stats);
3799 static void sky2_get_ethtool_stats(struct net_device *dev,
3800 struct ethtool_stats *stats, u64 * data)
3802 struct sky2_port *sky2 = netdev_priv(dev);
3804 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3807 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3811 switch (stringset) {
3813 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3814 memcpy(data + i * ETH_GSTRING_LEN,
3815 sky2_stats[i].name, ETH_GSTRING_LEN);
3820 static int sky2_set_mac_address(struct net_device *dev, void *p)
3822 struct sky2_port *sky2 = netdev_priv(dev);
3823 struct sky2_hw *hw = sky2->hw;
3824 unsigned port = sky2->port;
3825 const struct sockaddr *addr = p;
3827 if (!is_valid_ether_addr(addr->sa_data))
3828 return -EADDRNOTAVAIL;
3830 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3831 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3832 dev->dev_addr, ETH_ALEN);
3833 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3834 dev->dev_addr, ETH_ALEN);
3836 /* virtual address for data */
3837 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3839 /* physical address: used for pause frames */
3840 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3845 static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3849 bit = ether_crc(ETH_ALEN, addr) & 63;
3850 filter[bit >> 3] |= 1 << (bit & 7);
3853 static void sky2_set_multicast(struct net_device *dev)
3855 struct sky2_port *sky2 = netdev_priv(dev);
3856 struct sky2_hw *hw = sky2->hw;
3857 unsigned port = sky2->port;
3858 struct netdev_hw_addr *ha;
3862 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3864 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3865 memset(filter, 0, sizeof(filter));
3867 reg = gma_read16(hw, port, GM_RX_CTRL);
3868 reg |= GM_RXCR_UCF_ENA;
3870 if (dev->flags & IFF_PROMISC) /* promiscuous */
3871 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3872 else if (dev->flags & IFF_ALLMULTI)
3873 memset(filter, 0xff, sizeof(filter));
3874 else if (netdev_mc_empty(dev) && !rx_pause)
3875 reg &= ~GM_RXCR_MCF_ENA;
3877 reg |= GM_RXCR_MCF_ENA;
3880 sky2_add_filter(filter, pause_mc_addr);
3882 netdev_for_each_mc_addr(ha, dev)
3883 sky2_add_filter(filter, ha->addr);
3886 gma_write16(hw, port, GM_MC_ADDR_H1,
3887 (u16) filter[0] | ((u16) filter[1] << 8));
3888 gma_write16(hw, port, GM_MC_ADDR_H2,
3889 (u16) filter[2] | ((u16) filter[3] << 8));
3890 gma_write16(hw, port, GM_MC_ADDR_H3,
3891 (u16) filter[4] | ((u16) filter[5] << 8));
3892 gma_write16(hw, port, GM_MC_ADDR_H4,
3893 (u16) filter[6] | ((u16) filter[7] << 8));
3895 gma_write16(hw, port, GM_RX_CTRL, reg);
3898 static void sky2_get_stats(struct net_device *dev,
3899 struct rtnl_link_stats64 *stats)
3901 struct sky2_port *sky2 = netdev_priv(dev);
3902 struct sky2_hw *hw = sky2->hw;
3903 unsigned port = sky2->port;
3905 u64 _bytes, _packets;
3908 start = u64_stats_fetch_begin_irq(&sky2->rx_stats.syncp);
3909 _bytes = sky2->rx_stats.bytes;
3910 _packets = sky2->rx_stats.packets;
3911 } while (u64_stats_fetch_retry_irq(&sky2->rx_stats.syncp, start));
3913 stats->rx_packets = _packets;
3914 stats->rx_bytes = _bytes;
3917 start = u64_stats_fetch_begin_irq(&sky2->tx_stats.syncp);
3918 _bytes = sky2->tx_stats.bytes;
3919 _packets = sky2->tx_stats.packets;
3920 } while (u64_stats_fetch_retry_irq(&sky2->tx_stats.syncp, start));
3922 stats->tx_packets = _packets;
3923 stats->tx_bytes = _bytes;
3925 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3926 + get_stats32(hw, port, GM_RXF_BC_OK);
3928 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3930 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3931 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3932 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3933 + get_stats32(hw, port, GM_RXE_FRAG);
3934 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3936 stats->rx_dropped = dev->stats.rx_dropped;
3937 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3938 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3941 /* Can have one global because blinking is controlled by
3942 * ethtool and that is always under RTNL mutex
3944 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3946 struct sky2_hw *hw = sky2->hw;
3947 unsigned port = sky2->port;
3949 spin_lock_bh(&sky2->phy_lock);
3950 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3951 hw->chip_id == CHIP_ID_YUKON_EX ||
3952 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3954 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3955 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3959 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3960 PHY_M_LEDC_LOS_CTRL(8) |
3961 PHY_M_LEDC_INIT_CTRL(8) |
3962 PHY_M_LEDC_STA1_CTRL(8) |
3963 PHY_M_LEDC_STA0_CTRL(8));
3966 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3967 PHY_M_LEDC_LOS_CTRL(9) |
3968 PHY_M_LEDC_INIT_CTRL(9) |
3969 PHY_M_LEDC_STA1_CTRL(9) |
3970 PHY_M_LEDC_STA0_CTRL(9));
3973 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3974 PHY_M_LEDC_LOS_CTRL(0xa) |
3975 PHY_M_LEDC_INIT_CTRL(0xa) |
3976 PHY_M_LEDC_STA1_CTRL(0xa) |
3977 PHY_M_LEDC_STA0_CTRL(0xa));
3980 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3981 PHY_M_LEDC_LOS_CTRL(1) |
3982 PHY_M_LEDC_INIT_CTRL(8) |
3983 PHY_M_LEDC_STA1_CTRL(7) |
3984 PHY_M_LEDC_STA0_CTRL(7));
3987 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3989 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3990 PHY_M_LED_MO_DUP(mode) |
3991 PHY_M_LED_MO_10(mode) |
3992 PHY_M_LED_MO_100(mode) |
3993 PHY_M_LED_MO_1000(mode) |
3994 PHY_M_LED_MO_RX(mode) |
3995 PHY_M_LED_MO_TX(mode));
3997 spin_unlock_bh(&sky2->phy_lock);
4000 /* blink LED's for finding board */
4001 static int sky2_set_phys_id(struct net_device *dev,
4002 enum ethtool_phys_id_state state)
4004 struct sky2_port *sky2 = netdev_priv(dev);
4007 case ETHTOOL_ID_ACTIVE:
4008 return 1; /* cycle on/off once per second */
4009 case ETHTOOL_ID_INACTIVE:
4010 sky2_led(sky2, MO_LED_NORM);
4013 sky2_led(sky2, MO_LED_ON);
4015 case ETHTOOL_ID_OFF:
4016 sky2_led(sky2, MO_LED_OFF);
4023 static void sky2_get_pauseparam(struct net_device *dev,
4024 struct ethtool_pauseparam *ecmd)
4026 struct sky2_port *sky2 = netdev_priv(dev);
4028 switch (sky2->flow_mode) {
4030 ecmd->tx_pause = ecmd->rx_pause = 0;
4033 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
4036 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
4039 ecmd->tx_pause = ecmd->rx_pause = 1;
4042 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
4043 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
4046 static int sky2_set_pauseparam(struct net_device *dev,
4047 struct ethtool_pauseparam *ecmd)
4049 struct sky2_port *sky2 = netdev_priv(dev);
4051 if (ecmd->autoneg == AUTONEG_ENABLE)
4052 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
4054 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
4056 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
4058 if (netif_running(dev))
4059 sky2_phy_reinit(sky2);
4064 static int sky2_get_coalesce(struct net_device *dev,
4065 struct ethtool_coalesce *ecmd)
4067 struct sky2_port *sky2 = netdev_priv(dev);
4068 struct sky2_hw *hw = sky2->hw;
4070 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
4071 ecmd->tx_coalesce_usecs = 0;
4073 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
4074 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
4076 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
4078 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
4079 ecmd->rx_coalesce_usecs = 0;
4081 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
4082 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
4084 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
4086 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
4087 ecmd->rx_coalesce_usecs_irq = 0;
4089 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
4090 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
4093 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4098 /* Note: this affect both ports */
4099 static int sky2_set_coalesce(struct net_device *dev,
4100 struct ethtool_coalesce *ecmd)
4102 struct sky2_port *sky2 = netdev_priv(dev);
4103 struct sky2_hw *hw = sky2->hw;
4104 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
4106 if (ecmd->tx_coalesce_usecs > tmax ||
4107 ecmd->rx_coalesce_usecs > tmax ||
4108 ecmd->rx_coalesce_usecs_irq > tmax)
4111 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
4113 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
4115 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
4118 if (ecmd->tx_coalesce_usecs == 0)
4119 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4121 sky2_write32(hw, STAT_TX_TIMER_INI,
4122 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4123 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4125 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4127 if (ecmd->rx_coalesce_usecs == 0)
4128 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4130 sky2_write32(hw, STAT_LEV_TIMER_INI,
4131 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4132 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4134 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4136 if (ecmd->rx_coalesce_usecs_irq == 0)
4137 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4139 sky2_write32(hw, STAT_ISR_TIMER_INI,
4140 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4141 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4143 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4148 * Hardware is limited to min of 128 and max of 2048 for ring size
4149 * and rounded up to next power of two
4150 * to avoid division in modulus calclation
4152 static unsigned long roundup_ring_size(unsigned long pending)
4154 return max(128ul, roundup_pow_of_two(pending+1));
4157 static void sky2_get_ringparam(struct net_device *dev,
4158 struct ethtool_ringparam *ering)
4160 struct sky2_port *sky2 = netdev_priv(dev);
4162 ering->rx_max_pending = RX_MAX_PENDING;
4163 ering->tx_max_pending = TX_MAX_PENDING;
4165 ering->rx_pending = sky2->rx_pending;
4166 ering->tx_pending = sky2->tx_pending;
4169 static int sky2_set_ringparam(struct net_device *dev,
4170 struct ethtool_ringparam *ering)
4172 struct sky2_port *sky2 = netdev_priv(dev);
4174 if (ering->rx_pending > RX_MAX_PENDING ||
4175 ering->rx_pending < 8 ||
4176 ering->tx_pending < TX_MIN_PENDING ||
4177 ering->tx_pending > TX_MAX_PENDING)
4182 sky2->rx_pending = ering->rx_pending;
4183 sky2->tx_pending = ering->tx_pending;
4184 sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending);
4186 return sky2_reattach(dev);
4189 static int sky2_get_regs_len(struct net_device *dev)
4194 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4196 /* This complicated switch statement is to make sure and
4197 * only access regions that are unreserved.
4198 * Some blocks are only valid on dual port cards.
4202 case 5: /* Tx Arbiter 2 */
4204 case 14 ... 15: /* TX2 */
4205 case 17: case 19: /* Ram Buffer 2 */
4206 case 22 ... 23: /* Tx Ram Buffer 2 */
4207 case 25: /* Rx MAC Fifo 1 */
4208 case 27: /* Tx MAC Fifo 2 */
4209 case 31: /* GPHY 2 */
4210 case 40 ... 47: /* Pattern Ram 2 */
4211 case 52: case 54: /* TCP Segmentation 2 */
4212 case 112 ... 116: /* GMAC 2 */
4213 return hw->ports > 1;
4215 case 0: /* Control */
4216 case 2: /* Mac address */
4217 case 4: /* Tx Arbiter 1 */
4218 case 7: /* PCI express reg */
4220 case 12 ... 13: /* TX1 */
4221 case 16: case 18:/* Rx Ram Buffer 1 */
4222 case 20 ... 21: /* Tx Ram Buffer 1 */
4223 case 24: /* Rx MAC Fifo 1 */
4224 case 26: /* Tx MAC Fifo 1 */
4225 case 28 ... 29: /* Descriptor and status unit */
4226 case 30: /* GPHY 1*/
4227 case 32 ... 39: /* Pattern Ram 1 */
4228 case 48: case 50: /* TCP Segmentation 1 */
4229 case 56 ... 60: /* PCI space */
4230 case 80 ... 84: /* GMAC 1 */
4239 * Returns copy of control register region
4240 * Note: ethtool_get_regs always provides full size (16k) buffer
4242 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4245 const struct sky2_port *sky2 = netdev_priv(dev);
4246 const void __iomem *io = sky2->hw->regs;
4251 for (b = 0; b < 128; b++) {
4252 /* skip poisonous diagnostic ram region in block 3 */
4254 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4255 else if (sky2_reg_access_ok(sky2->hw, b))
4256 memcpy_fromio(p, io, 128);
4265 static int sky2_get_eeprom_len(struct net_device *dev)
4267 struct sky2_port *sky2 = netdev_priv(dev);
4268 struct sky2_hw *hw = sky2->hw;
4271 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4272 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4275 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4277 unsigned long start = jiffies;
4279 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4280 /* Can take up to 10.6 ms for write */
4281 if (time_after(jiffies, start + HZ/4)) {
4282 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
4291 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4292 u16 offset, size_t length)
4296 while (length > 0) {
4299 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4300 rc = sky2_vpd_wait(hw, cap, 0);
4304 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4306 memcpy(data, &val, min(sizeof(val), length));
4307 offset += sizeof(u32);
4308 data += sizeof(u32);
4309 length -= sizeof(u32);
4315 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4316 u16 offset, unsigned int length)
4321 for (i = 0; i < length; i += sizeof(u32)) {
4322 u32 val = *(u32 *)(data + i);
4324 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4325 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4327 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4334 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4337 struct sky2_port *sky2 = netdev_priv(dev);
4338 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4343 eeprom->magic = SKY2_EEPROM_MAGIC;
4345 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4348 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4351 struct sky2_port *sky2 = netdev_priv(dev);
4352 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4357 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4360 /* Partial writes not supported */
4361 if ((eeprom->offset & 3) || (eeprom->len & 3))
4364 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4367 static netdev_features_t sky2_fix_features(struct net_device *dev,
4368 netdev_features_t features)
4370 const struct sky2_port *sky2 = netdev_priv(dev);
4371 const struct sky2_hw *hw = sky2->hw;
4373 /* In order to do Jumbo packets on these chips, need to turn off the
4374 * transmit store/forward. Therefore checksum offload won't work.
4376 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4377 netdev_info(dev, "checksum offload not possible with jumbo frames\n");
4378 features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_CSUM_MASK);
4381 /* Some hardware requires receive checksum for RSS to work. */
4382 if ( (features & NETIF_F_RXHASH) &&
4383 !(features & NETIF_F_RXCSUM) &&
4384 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4385 netdev_info(dev, "receive hashing forces receive checksum\n");
4386 features |= NETIF_F_RXCSUM;
4392 static int sky2_set_features(struct net_device *dev, netdev_features_t features)
4394 struct sky2_port *sky2 = netdev_priv(dev);
4395 netdev_features_t changed = dev->features ^ features;
4397 if ((changed & NETIF_F_RXCSUM) &&
4398 !(sky2->hw->flags & SKY2_HW_NEW_LE)) {
4399 sky2_write32(sky2->hw,
4400 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4401 (features & NETIF_F_RXCSUM)
4402 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4405 if (changed & NETIF_F_RXHASH)
4406 rx_set_rss(dev, features);
4408 if (changed & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX))
4409 sky2_vlan_mode(dev, features);
4414 static const struct ethtool_ops sky2_ethtool_ops = {
4415 .get_drvinfo = sky2_get_drvinfo,
4416 .get_wol = sky2_get_wol,
4417 .set_wol = sky2_set_wol,
4418 .get_msglevel = sky2_get_msglevel,
4419 .set_msglevel = sky2_set_msglevel,
4420 .nway_reset = sky2_nway_reset,
4421 .get_regs_len = sky2_get_regs_len,
4422 .get_regs = sky2_get_regs,
4423 .get_link = ethtool_op_get_link,
4424 .get_eeprom_len = sky2_get_eeprom_len,
4425 .get_eeprom = sky2_get_eeprom,
4426 .set_eeprom = sky2_set_eeprom,
4427 .get_strings = sky2_get_strings,
4428 .get_coalesce = sky2_get_coalesce,
4429 .set_coalesce = sky2_set_coalesce,
4430 .get_ringparam = sky2_get_ringparam,
4431 .set_ringparam = sky2_set_ringparam,
4432 .get_pauseparam = sky2_get_pauseparam,
4433 .set_pauseparam = sky2_set_pauseparam,
4434 .set_phys_id = sky2_set_phys_id,
4435 .get_sset_count = sky2_get_sset_count,
4436 .get_ethtool_stats = sky2_get_ethtool_stats,
4437 .get_link_ksettings = sky2_get_link_ksettings,
4438 .set_link_ksettings = sky2_set_link_ksettings,
4441 #ifdef CONFIG_SKY2_DEBUG
4443 static struct dentry *sky2_debug;
4447 * Read and parse the first part of Vital Product Data
4449 #define VPD_SIZE 128
4450 #define VPD_MAGIC 0x82
4452 static const struct vpd_tag {
4456 { "PN", "Part Number" },
4457 { "EC", "Engineering Level" },
4458 { "MN", "Manufacturer" },
4459 { "SN", "Serial Number" },
4460 { "YA", "Asset Tag" },
4461 { "VL", "First Error Log Message" },
4462 { "VF", "Second Error Log Message" },
4463 { "VB", "Boot Agent ROM Configuration" },
4464 { "VE", "EFI UNDI Configuration" },
4467 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4475 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4476 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4478 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4479 buf = kmalloc(vpd_size, GFP_KERNEL);
4481 seq_puts(seq, "no memory!\n");
4485 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4486 seq_puts(seq, "VPD read failed\n");
4490 if (buf[0] != VPD_MAGIC) {
4491 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4495 if (len == 0 || len > vpd_size - 4) {
4496 seq_printf(seq, "Invalid id length: %d\n", len);
4500 seq_printf(seq, "%.*s\n", len, buf + 3);
4503 while (offs < vpd_size - 4) {
4506 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4508 len = buf[offs + 2];
4509 if (offs + len + 3 >= vpd_size)
4512 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4513 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4514 seq_printf(seq, " %s: %.*s\n",
4515 vpd_tags[i].label, len, buf + offs + 3);
4525 static int sky2_debug_show(struct seq_file *seq, void *v)
4527 struct net_device *dev = seq->private;
4528 const struct sky2_port *sky2 = netdev_priv(dev);
4529 struct sky2_hw *hw = sky2->hw;
4530 unsigned port = sky2->port;
4534 sky2_show_vpd(seq, hw);
4536 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4537 sky2_read32(hw, B0_ISRC),
4538 sky2_read32(hw, B0_IMSK),
4539 sky2_read32(hw, B0_Y2_SP_ICR));
4541 if (!netif_running(dev)) {
4542 seq_puts(seq, "network not running\n");
4546 napi_disable(&hw->napi);
4547 last = sky2_read16(hw, STAT_PUT_IDX);
4549 seq_printf(seq, "Status ring %u\n", hw->st_size);
4550 if (hw->st_idx == last)
4551 seq_puts(seq, "Status ring (empty)\n");
4553 seq_puts(seq, "Status ring\n");
4554 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4555 idx = RING_NEXT(idx, hw->st_size)) {
4556 const struct sky2_status_le *le = hw->st_le + idx;
4557 seq_printf(seq, "[%d] %#x %d %#x\n",
4558 idx, le->opcode, le->length, le->status);
4560 seq_puts(seq, "\n");
4563 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4564 sky2->tx_cons, sky2->tx_prod,
4565 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4566 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4568 /* Dump contents of tx ring */
4570 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4571 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4572 const struct sky2_tx_le *le = sky2->tx_le + idx;
4573 u32 a = le32_to_cpu(le->addr);
4576 seq_printf(seq, "%u:", idx);
4579 switch (le->opcode & ~HW_OWNER) {
4581 seq_printf(seq, " %#x:", a);
4584 seq_printf(seq, " mtu=%d", a);
4587 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4590 seq_printf(seq, " csum=%#x", a);
4593 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4596 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4599 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4602 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4603 a, le16_to_cpu(le->length));
4606 if (le->ctrl & EOP) {
4607 seq_putc(seq, '\n');
4612 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4613 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4614 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4615 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4617 sky2_read32(hw, B0_Y2_SP_LISR);
4618 napi_enable(&hw->napi);
4621 DEFINE_SHOW_ATTRIBUTE(sky2_debug);
4624 * Use network device events to create/remove/rename
4625 * debugfs file entries
4627 static int sky2_device_event(struct notifier_block *unused,
4628 unsigned long event, void *ptr)
4630 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
4631 struct sky2_port *sky2 = netdev_priv(dev);
4633 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug)
4637 case NETDEV_CHANGENAME:
4638 if (sky2->debugfs) {
4639 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4640 sky2_debug, dev->name);
4644 case NETDEV_GOING_DOWN:
4645 if (sky2->debugfs) {
4646 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4647 debugfs_remove(sky2->debugfs);
4648 sky2->debugfs = NULL;
4653 sky2->debugfs = debugfs_create_file(dev->name, 0444,
4656 if (IS_ERR(sky2->debugfs))
4657 sky2->debugfs = NULL;
4663 static struct notifier_block sky2_notifier = {
4664 .notifier_call = sky2_device_event,
4668 static __init void sky2_debug_init(void)
4672 ent = debugfs_create_dir("sky2", NULL);
4673 if (!ent || IS_ERR(ent))
4677 register_netdevice_notifier(&sky2_notifier);
4680 static __exit void sky2_debug_cleanup(void)
4683 unregister_netdevice_notifier(&sky2_notifier);
4684 debugfs_remove(sky2_debug);
4690 #define sky2_debug_init()
4691 #define sky2_debug_cleanup()
4694 /* Two copies of network device operations to handle special case of
4695 not allowing netpoll on second port */
4696 static const struct net_device_ops sky2_netdev_ops[2] = {
4698 .ndo_open = sky2_open,
4699 .ndo_stop = sky2_close,
4700 .ndo_start_xmit = sky2_xmit_frame,
4701 .ndo_do_ioctl = sky2_ioctl,
4702 .ndo_validate_addr = eth_validate_addr,
4703 .ndo_set_mac_address = sky2_set_mac_address,
4704 .ndo_set_rx_mode = sky2_set_multicast,
4705 .ndo_change_mtu = sky2_change_mtu,
4706 .ndo_fix_features = sky2_fix_features,
4707 .ndo_set_features = sky2_set_features,
4708 .ndo_tx_timeout = sky2_tx_timeout,
4709 .ndo_get_stats64 = sky2_get_stats,
4710 #ifdef CONFIG_NET_POLL_CONTROLLER
4711 .ndo_poll_controller = sky2_netpoll,
4715 .ndo_open = sky2_open,
4716 .ndo_stop = sky2_close,
4717 .ndo_start_xmit = sky2_xmit_frame,
4718 .ndo_do_ioctl = sky2_ioctl,
4719 .ndo_validate_addr = eth_validate_addr,
4720 .ndo_set_mac_address = sky2_set_mac_address,
4721 .ndo_set_rx_mode = sky2_set_multicast,
4722 .ndo_change_mtu = sky2_change_mtu,
4723 .ndo_fix_features = sky2_fix_features,
4724 .ndo_set_features = sky2_set_features,
4725 .ndo_tx_timeout = sky2_tx_timeout,
4726 .ndo_get_stats64 = sky2_get_stats,
4730 /* Initialize network device */
4731 static struct net_device *sky2_init_netdev(struct sky2_hw *hw, unsigned port,
4732 int highmem, int wol)
4734 struct sky2_port *sky2;
4735 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4741 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4742 dev->irq = hw->pdev->irq;
4743 dev->ethtool_ops = &sky2_ethtool_ops;
4744 dev->watchdog_timeo = TX_WATCHDOG;
4745 dev->netdev_ops = &sky2_netdev_ops[port];
4747 sky2 = netdev_priv(dev);
4750 sky2->msg_enable = netif_msg_init(debug, default_msg);
4752 u64_stats_init(&sky2->tx_stats.syncp);
4753 u64_stats_init(&sky2->rx_stats.syncp);
4755 /* Auto speed and flow control */
4756 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4757 if (hw->chip_id != CHIP_ID_YUKON_XL)
4758 dev->hw_features |= NETIF_F_RXCSUM;
4760 sky2->flow_mode = FC_BOTH;
4764 sky2->advertising = sky2_supported_modes(hw);
4767 spin_lock_init(&sky2->phy_lock);
4769 sky2->tx_pending = TX_DEF_PENDING;
4770 sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING);
4771 sky2->rx_pending = RX_DEF_PENDING;
4773 hw->dev[port] = dev;
4777 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
4780 dev->features |= NETIF_F_HIGHDMA;
4782 /* Enable receive hashing unless hardware is known broken */
4783 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4784 dev->hw_features |= NETIF_F_RXHASH;
4786 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4787 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
4788 NETIF_F_HW_VLAN_CTAG_RX;
4789 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4792 dev->features |= dev->hw_features;
4794 /* MTU range: 60 - 1500 or 9000 */
4795 dev->min_mtu = ETH_ZLEN;
4796 if (hw->chip_id == CHIP_ID_YUKON_FE ||
4797 hw->chip_id == CHIP_ID_YUKON_FE_P)
4798 dev->max_mtu = ETH_DATA_LEN;
4800 dev->max_mtu = ETH_JUMBO_MTU;
4802 /* try to get mac address in the following order:
4803 * 1) from device tree data
4804 * 2) from internal registers set by bootloader
4806 iap = of_get_mac_address(hw->pdev->dev.of_node);
4808 memcpy(dev->dev_addr, iap, ETH_ALEN);
4810 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8,
4813 /* if the address is invalid, use a random value */
4814 if (!is_valid_ether_addr(dev->dev_addr)) {
4815 struct sockaddr sa = { AF_UNSPEC };
4818 "Invalid MAC address, defaulting to random\n");
4819 eth_hw_addr_random(dev);
4820 memcpy(sa.sa_data, dev->dev_addr, ETH_ALEN);
4821 if (sky2_set_mac_address(dev, &sa))
4822 netdev_warn(dev, "Failed to set MAC address.\n");
4828 static void sky2_show_addr(struct net_device *dev)
4830 const struct sky2_port *sky2 = netdev_priv(dev);
4832 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4835 /* Handle software interrupt used during MSI test */
4836 static irqreturn_t sky2_test_intr(int irq, void *dev_id)
4838 struct sky2_hw *hw = dev_id;
4839 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4844 if (status & Y2_IS_IRQ_SW) {
4845 hw->flags |= SKY2_HW_USE_MSI;
4846 wake_up(&hw->msi_wait);
4847 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4849 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4854 /* Test interrupt path by forcing a a software IRQ */
4855 static int sky2_test_msi(struct sky2_hw *hw)
4857 struct pci_dev *pdev = hw->pdev;
4860 init_waitqueue_head(&hw->msi_wait);
4862 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4864 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4868 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4870 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4871 sky2_read8(hw, B0_CTST);
4873 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4875 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4876 /* MSI test failed, go back to INTx mode */
4877 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4878 "switching to INTx mode.\n");
4881 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4884 sky2_write32(hw, B0_IMSK, 0);
4885 sky2_read32(hw, B0_IMSK);
4887 free_irq(pdev->irq, hw);
4892 /* This driver supports yukon2 chipset only */
4893 static const char *sky2_name(u8 chipid, char *buf, int sz)
4895 const char *name[] = {
4897 "EC Ultra", /* 0xb4 */
4898 "Extreme", /* 0xb5 */
4902 "Supreme", /* 0xb9 */
4904 "Unknown", /* 0xbb */
4905 "Optima", /* 0xbc */
4906 "OptimaEEE", /* 0xbd */
4907 "Optima 2", /* 0xbe */
4910 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2)
4911 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4913 snprintf(buf, sz, "(chip %#x)", chipid);
4917 static const struct dmi_system_id msi_blacklist[] = {
4919 .ident = "Dell Inspiron 1545",
4921 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
4922 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 1545"),
4926 .ident = "Gateway P-79",
4928 DMI_MATCH(DMI_SYS_VENDOR, "Gateway"),
4929 DMI_MATCH(DMI_PRODUCT_NAME, "P-79"),
4935 static int sky2_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4937 struct net_device *dev, *dev1;
4939 int err, using_dac = 0, wol_default;
4943 err = pci_enable_device(pdev);
4945 dev_err(&pdev->dev, "cannot enable PCI device\n");
4949 /* Get configuration information
4950 * Note: only regular PCI config access once to test for HW issues
4951 * other PCI access through shared memory for speed and to
4952 * avoid MMCONFIG problems.
4954 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4956 dev_err(&pdev->dev, "PCI read config failed\n");
4957 goto err_out_disable;
4961 dev_err(&pdev->dev, "PCI configuration read error\n");
4963 goto err_out_disable;
4966 err = pci_request_regions(pdev, DRV_NAME);
4968 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4969 goto err_out_disable;
4972 pci_set_master(pdev);
4974 if (sizeof(dma_addr_t) > sizeof(u32) &&
4975 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4977 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4979 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4980 "for consistent allocations\n");
4981 goto err_out_free_regions;
4984 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4986 dev_err(&pdev->dev, "no usable DMA configuration\n");
4987 goto err_out_free_regions;
4993 /* The sk98lin vendor driver uses hardware byte swapping but
4994 * this driver uses software swapping.
4996 reg &= ~PCI_REV_DESC;
4997 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4999 dev_err(&pdev->dev, "PCI write config failed\n");
5000 goto err_out_free_regions;
5004 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
5008 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
5009 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
5011 goto err_out_free_regions;
5014 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
5016 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
5018 dev_err(&pdev->dev, "cannot map device registers\n");
5019 goto err_out_free_hw;
5022 err = sky2_init(hw);
5024 goto err_out_iounmap;
5026 /* ring for status responses */
5027 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
5028 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5035 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
5036 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
5040 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
5043 goto err_out_free_pci;
5046 if (disable_msi == -1)
5047 disable_msi = !!dmi_check_system(msi_blacklist);
5049 if (!disable_msi && pci_enable_msi(pdev) == 0) {
5050 err = sky2_test_msi(hw);
5052 pci_disable_msi(pdev);
5053 if (err != -EOPNOTSUPP)
5054 goto err_out_free_netdev;
5058 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
5060 err = register_netdev(dev);
5062 dev_err(&pdev->dev, "cannot register net device\n");
5063 goto err_out_free_netdev;
5066 netif_carrier_off(dev);
5068 sky2_show_addr(dev);
5070 if (hw->ports > 1) {
5071 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
5074 goto err_out_unregister;
5077 err = register_netdev(dev1);
5079 dev_err(&pdev->dev, "cannot register second net device\n");
5080 goto err_out_free_dev1;
5083 err = sky2_setup_irq(hw, hw->irq_name);
5085 goto err_out_unregister_dev1;
5087 sky2_show_addr(dev1);
5090 timer_setup(&hw->watchdog_timer, sky2_watchdog, 0);
5091 INIT_WORK(&hw->restart_work, sky2_restart);
5093 pci_set_drvdata(pdev, hw);
5094 pdev->d3_delay = 300;
5098 err_out_unregister_dev1:
5099 unregister_netdev(dev1);
5103 unregister_netdev(dev);
5104 err_out_free_netdev:
5105 if (hw->flags & SKY2_HW_USE_MSI)
5106 pci_disable_msi(pdev);
5109 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5110 hw->st_le, hw->st_dma);
5112 sky2_write8(hw, B0_CTST, CS_RST_SET);
5117 err_out_free_regions:
5118 pci_release_regions(pdev);
5120 pci_disable_device(pdev);
5125 static void sky2_remove(struct pci_dev *pdev)
5127 struct sky2_hw *hw = pci_get_drvdata(pdev);
5133 del_timer_sync(&hw->watchdog_timer);
5134 cancel_work_sync(&hw->restart_work);
5136 for (i = hw->ports-1; i >= 0; --i)
5137 unregister_netdev(hw->dev[i]);
5139 sky2_write32(hw, B0_IMSK, 0);
5140 sky2_read32(hw, B0_IMSK);
5144 sky2_write8(hw, B0_CTST, CS_RST_SET);
5145 sky2_read8(hw, B0_CTST);
5147 if (hw->ports > 1) {
5148 napi_disable(&hw->napi);
5149 free_irq(pdev->irq, hw);
5152 if (hw->flags & SKY2_HW_USE_MSI)
5153 pci_disable_msi(pdev);
5154 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5155 hw->st_le, hw->st_dma);
5156 pci_release_regions(pdev);
5157 pci_disable_device(pdev);
5159 for (i = hw->ports-1; i >= 0; --i)
5160 free_netdev(hw->dev[i]);
5166 static int sky2_suspend(struct device *dev)
5168 struct pci_dev *pdev = to_pci_dev(dev);
5169 struct sky2_hw *hw = pci_get_drvdata(pdev);
5175 del_timer_sync(&hw->watchdog_timer);
5176 cancel_work_sync(&hw->restart_work);
5181 for (i = 0; i < hw->ports; i++) {
5182 struct net_device *dev = hw->dev[i];
5183 struct sky2_port *sky2 = netdev_priv(dev);
5186 sky2_wol_init(sky2);
5195 #ifdef CONFIG_PM_SLEEP
5196 static int sky2_resume(struct device *dev)
5198 struct pci_dev *pdev = to_pci_dev(dev);
5199 struct sky2_hw *hw = pci_get_drvdata(pdev);
5205 /* Re-enable all clocks */
5206 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
5208 dev_err(&pdev->dev, "PCI write config failed\n");
5220 dev_err(&pdev->dev, "resume failed (%d)\n", err);
5221 pci_disable_device(pdev);
5225 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5226 #define SKY2_PM_OPS (&sky2_pm_ops)
5230 #define SKY2_PM_OPS NULL
5233 static void sky2_shutdown(struct pci_dev *pdev)
5235 struct sky2_hw *hw = pci_get_drvdata(pdev);
5238 for (port = 0; port < hw->ports; port++) {
5239 struct net_device *ndev = hw->dev[port];
5242 if (netif_running(ndev)) {
5244 netif_device_detach(ndev);
5248 sky2_suspend(&pdev->dev);
5249 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5250 pci_set_power_state(pdev, PCI_D3hot);
5253 static struct pci_driver sky2_driver = {
5255 .id_table = sky2_id_table,
5256 .probe = sky2_probe,
5257 .remove = sky2_remove,
5258 .shutdown = sky2_shutdown,
5259 .driver.pm = SKY2_PM_OPS,
5262 static int __init sky2_init_module(void)
5264 pr_info("driver version " DRV_VERSION "\n");
5267 return pci_register_driver(&sky2_driver);
5270 static void __exit sky2_cleanup_module(void)
5272 pci_unregister_driver(&sky2_driver);
5273 sky2_debug_cleanup();
5276 module_init(sky2_init_module);
5277 module_exit(sky2_cleanup_module);
5279 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5280 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5281 MODULE_LICENSE("GPL");
5282 MODULE_VERSION(DRV_VERSION);