1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/if_vlan.h>
23 #include <linux/reset.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26 #include <linux/pinctrl/devinfo.h>
28 #include "mtk_eth_soc.h"
30 static int mtk_msg_level = -1;
31 module_param_named(msg_level, mtk_msg_level, int, 0);
32 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
34 #define MTK_ETHTOOL_STAT(x) { #x, \
35 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
37 /* strings used by ethtool */
38 static const struct mtk_ethtool_stats {
39 char str[ETH_GSTRING_LEN];
41 } mtk_ethtool_stats[] = {
42 MTK_ETHTOOL_STAT(tx_bytes),
43 MTK_ETHTOOL_STAT(tx_packets),
44 MTK_ETHTOOL_STAT(tx_skip),
45 MTK_ETHTOOL_STAT(tx_collisions),
46 MTK_ETHTOOL_STAT(rx_bytes),
47 MTK_ETHTOOL_STAT(rx_packets),
48 MTK_ETHTOOL_STAT(rx_overflow),
49 MTK_ETHTOOL_STAT(rx_fcs_errors),
50 MTK_ETHTOOL_STAT(rx_short_errors),
51 MTK_ETHTOOL_STAT(rx_long_errors),
52 MTK_ETHTOOL_STAT(rx_checksum_errors),
53 MTK_ETHTOOL_STAT(rx_flow_control_packets),
56 static const char * const mtk_clks_source_name[] = {
57 "ethif", "esw", "gp0", "gp1", "gp2", "trgpll", "sgmii_tx250m",
58 "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll"
61 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
63 __raw_writel(val, eth->base + reg);
66 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
68 return __raw_readl(eth->base + reg);
71 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
73 unsigned long t_start = jiffies;
76 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
78 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
83 dev_err(eth->dev, "mdio: MDIO timeout\n");
87 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
88 u32 phy_register, u32 write_data)
90 if (mtk_mdio_busy_wait(eth))
95 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
96 (phy_register << PHY_IAC_REG_SHIFT) |
97 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
100 if (mtk_mdio_busy_wait(eth))
106 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
110 if (mtk_mdio_busy_wait(eth))
113 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
114 (phy_reg << PHY_IAC_REG_SHIFT) |
115 (phy_addr << PHY_IAC_ADDR_SHIFT),
118 if (mtk_mdio_busy_wait(eth))
121 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
126 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
127 int phy_reg, u16 val)
129 struct mtk_eth *eth = bus->priv;
131 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
134 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
136 struct mtk_eth *eth = bus->priv;
138 return _mtk_mdio_read(eth, phy_addr, phy_reg);
141 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
146 val = (speed == SPEED_1000) ?
147 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
148 mtk_w32(eth, val, INTF_MODE);
150 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
151 ETHSYS_TRGMII_CLK_SEL362_5,
152 ETHSYS_TRGMII_CLK_SEL362_5);
154 val = (speed == SPEED_1000) ? 250000000 : 500000000;
155 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
157 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
159 val = (speed == SPEED_1000) ?
160 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
161 mtk_w32(eth, val, TRGMII_RCK_CTRL);
163 val = (speed == SPEED_1000) ?
164 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
165 mtk_w32(eth, val, TRGMII_TCK_CTRL);
168 static void mtk_gmac_sgmii_hw_setup(struct mtk_eth *eth, int mac_id)
172 /* Setup the link timer and QPHY power up inside SGMIISYS */
173 regmap_write(eth->sgmiisys, SGMSYS_PCS_LINK_TIMER,
174 SGMII_LINK_TIMER_DEFAULT);
176 regmap_read(eth->sgmiisys, SGMSYS_SGMII_MODE, &val);
177 val |= SGMII_REMOTE_FAULT_DIS;
178 regmap_write(eth->sgmiisys, SGMSYS_SGMII_MODE, val);
180 regmap_read(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, &val);
181 val |= SGMII_AN_RESTART;
182 regmap_write(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, val);
184 regmap_read(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
185 val &= ~SGMII_PHYA_PWD;
186 regmap_write(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, val);
188 /* Determine MUX for which GMAC uses the SGMII interface */
189 if (MTK_HAS_CAPS(eth->soc->caps, MTK_DUAL_GMAC_SHARED_SGMII)) {
190 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
191 val &= ~SYSCFG0_SGMII_MASK;
192 val |= !mac_id ? SYSCFG0_SGMII_GMAC1 : SYSCFG0_SGMII_GMAC2;
193 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
195 dev_info(eth->dev, "setup shared sgmii for gmac=%d\n",
199 /* Setup the GMAC1 going through SGMII path when SoC also support
202 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC1_ESW | MTK_GMAC1_SGMII) &&
204 mtk_w32(eth, 0, MTK_MAC_MISC);
205 dev_info(eth->dev, "setup gmac1 going through sgmii");
209 static void mtk_phy_link_adjust(struct net_device *dev)
211 struct mtk_mac *mac = netdev_priv(dev);
212 u16 lcl_adv = 0, rmt_adv = 0;
214 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
215 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
216 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
219 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
222 switch (dev->phydev->speed) {
224 mcr |= MAC_MCR_SPEED_1000;
227 mcr |= MAC_MCR_SPEED_100;
231 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) &&
232 !mac->id && !mac->trgmii)
233 mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed);
235 if (dev->phydev->link)
236 mcr |= MAC_MCR_FORCE_LINK;
238 if (dev->phydev->duplex) {
239 mcr |= MAC_MCR_FORCE_DPX;
241 if (dev->phydev->pause)
242 rmt_adv = LPA_PAUSE_CAP;
243 if (dev->phydev->asym_pause)
244 rmt_adv |= LPA_PAUSE_ASYM;
246 lcl_adv = linkmode_adv_to_lcl_adv_t(dev->phydev->advertising);
247 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
249 if (flowctrl & FLOW_CTRL_TX)
250 mcr |= MAC_MCR_FORCE_TX_FC;
251 if (flowctrl & FLOW_CTRL_RX)
252 mcr |= MAC_MCR_FORCE_RX_FC;
254 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
255 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
256 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
259 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
261 if (!of_phy_is_fixed_link(mac->of_node))
262 phy_print_status(dev->phydev);
265 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
266 struct device_node *phy_node)
268 struct phy_device *phydev;
271 phy_mode = of_get_phy_mode(phy_node);
273 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
277 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
278 mtk_phy_link_adjust, 0, phy_mode);
280 dev_err(eth->dev, "could not connect to PHY\n");
285 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
286 mac->id, phydev_name(phydev), phydev->phy_id,
292 static int mtk_phy_connect(struct net_device *dev)
294 struct mtk_mac *mac = netdev_priv(dev);
296 struct device_node *np;
300 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
301 if (!np && of_phy_is_fixed_link(mac->of_node))
302 if (!of_phy_register_fixed_link(mac->of_node))
303 np = of_node_get(mac->of_node);
308 switch (of_get_phy_mode(np)) {
309 case PHY_INTERFACE_MODE_TRGMII:
311 case PHY_INTERFACE_MODE_RGMII_TXID:
312 case PHY_INTERFACE_MODE_RGMII_RXID:
313 case PHY_INTERFACE_MODE_RGMII_ID:
314 case PHY_INTERFACE_MODE_RGMII:
316 case PHY_INTERFACE_MODE_SGMII:
317 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII))
318 mtk_gmac_sgmii_hw_setup(eth, mac->id);
320 case PHY_INTERFACE_MODE_MII:
323 case PHY_INTERFACE_MODE_REVMII:
326 case PHY_INTERFACE_MODE_RMII:
335 /* put the gmac into the right mode */
336 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
337 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
338 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
339 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
341 /* couple phydev to net_device */
342 if (mtk_phy_connect_node(eth, mac, np))
350 if (of_phy_is_fixed_link(mac->of_node))
351 of_phy_deregister_fixed_link(mac->of_node);
353 dev_err(eth->dev, "%s: invalid phy\n", __func__);
357 static int mtk_mdio_init(struct mtk_eth *eth)
359 struct device_node *mii_np;
362 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
364 dev_err(eth->dev, "no %s child node found", "mdio-bus");
368 if (!of_device_is_available(mii_np)) {
373 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
379 eth->mii_bus->name = "mdio";
380 eth->mii_bus->read = mtk_mdio_read;
381 eth->mii_bus->write = mtk_mdio_write;
382 eth->mii_bus->priv = eth;
383 eth->mii_bus->parent = eth->dev;
385 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
386 ret = of_mdiobus_register(eth->mii_bus, mii_np);
393 static void mtk_mdio_cleanup(struct mtk_eth *eth)
398 mdiobus_unregister(eth->mii_bus);
401 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
406 spin_lock_irqsave(ð->tx_irq_lock, flags);
407 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
408 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
409 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
412 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
417 spin_lock_irqsave(ð->tx_irq_lock, flags);
418 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
419 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
420 spin_unlock_irqrestore(ð->tx_irq_lock, flags);
423 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
428 spin_lock_irqsave(ð->rx_irq_lock, flags);
429 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
430 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK);
431 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
434 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
439 spin_lock_irqsave(ð->rx_irq_lock, flags);
440 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
441 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK);
442 spin_unlock_irqrestore(ð->rx_irq_lock, flags);
445 static int mtk_set_mac_address(struct net_device *dev, void *p)
447 int ret = eth_mac_addr(dev, p);
448 struct mtk_mac *mac = netdev_priv(dev);
449 const char *macaddr = dev->dev_addr;
454 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
457 spin_lock_bh(&mac->hw->page_lock);
458 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
459 MTK_GDMA_MAC_ADRH(mac->id));
460 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
461 (macaddr[4] << 8) | macaddr[5],
462 MTK_GDMA_MAC_ADRL(mac->id));
463 spin_unlock_bh(&mac->hw->page_lock);
468 void mtk_stats_update_mac(struct mtk_mac *mac)
470 struct mtk_hw_stats *hw_stats = mac->hw_stats;
471 unsigned int base = MTK_GDM1_TX_GBCNT;
474 base += hw_stats->reg_offset;
476 u64_stats_update_begin(&hw_stats->syncp);
478 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
479 stats = mtk_r32(mac->hw, base + 0x04);
481 hw_stats->rx_bytes += (stats << 32);
482 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
483 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
484 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
485 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
486 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
487 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
488 hw_stats->rx_flow_control_packets +=
489 mtk_r32(mac->hw, base + 0x24);
490 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
491 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
492 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
493 stats = mtk_r32(mac->hw, base + 0x34);
495 hw_stats->tx_bytes += (stats << 32);
496 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
497 u64_stats_update_end(&hw_stats->syncp);
500 static void mtk_stats_update(struct mtk_eth *eth)
504 for (i = 0; i < MTK_MAC_COUNT; i++) {
505 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
507 if (spin_trylock(ð->mac[i]->hw_stats->stats_lock)) {
508 mtk_stats_update_mac(eth->mac[i]);
509 spin_unlock(ð->mac[i]->hw_stats->stats_lock);
514 static void mtk_get_stats64(struct net_device *dev,
515 struct rtnl_link_stats64 *storage)
517 struct mtk_mac *mac = netdev_priv(dev);
518 struct mtk_hw_stats *hw_stats = mac->hw_stats;
521 if (netif_running(dev) && netif_device_present(dev)) {
522 if (spin_trylock_bh(&hw_stats->stats_lock)) {
523 mtk_stats_update_mac(mac);
524 spin_unlock_bh(&hw_stats->stats_lock);
529 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
530 storage->rx_packets = hw_stats->rx_packets;
531 storage->tx_packets = hw_stats->tx_packets;
532 storage->rx_bytes = hw_stats->rx_bytes;
533 storage->tx_bytes = hw_stats->tx_bytes;
534 storage->collisions = hw_stats->tx_collisions;
535 storage->rx_length_errors = hw_stats->rx_short_errors +
536 hw_stats->rx_long_errors;
537 storage->rx_over_errors = hw_stats->rx_overflow;
538 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
539 storage->rx_errors = hw_stats->rx_checksum_errors;
540 storage->tx_aborted_errors = hw_stats->tx_skip;
541 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
543 storage->tx_errors = dev->stats.tx_errors;
544 storage->rx_dropped = dev->stats.rx_dropped;
545 storage->tx_dropped = dev->stats.tx_dropped;
548 static inline int mtk_max_frag_size(int mtu)
550 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
551 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
552 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
554 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
555 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
558 static inline int mtk_max_buf_size(int frag_size)
560 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
561 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
563 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
568 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
569 struct mtk_rx_dma *dma_rxd)
571 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
572 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
573 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
574 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
577 /* the qdma core needs scratch memory to be setup */
578 static int mtk_init_fq_dma(struct mtk_eth *eth)
580 dma_addr_t phy_ring_tail;
581 int cnt = MTK_DMA_SIZE;
585 eth->scratch_ring = dma_alloc_coherent(eth->dev,
586 cnt * sizeof(struct mtk_tx_dma),
587 ð->phy_scratch_ring,
589 if (unlikely(!eth->scratch_ring))
592 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
594 if (unlikely(!eth->scratch_head))
597 dma_addr = dma_map_single(eth->dev,
598 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
600 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
603 phy_ring_tail = eth->phy_scratch_ring +
604 (sizeof(struct mtk_tx_dma) * (cnt - 1));
606 for (i = 0; i < cnt; i++) {
607 eth->scratch_ring[i].txd1 =
608 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
610 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
611 ((i + 1) * sizeof(struct mtk_tx_dma)));
612 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
615 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
616 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
617 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
618 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
623 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
625 void *ret = ring->dma;
627 return ret + (desc - ring->phys);
630 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
631 struct mtk_tx_dma *txd)
633 int idx = txd - ring->dma;
635 return &ring->buf[idx];
638 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
640 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
641 dma_unmap_single(eth->dev,
642 dma_unmap_addr(tx_buf, dma_addr0),
643 dma_unmap_len(tx_buf, dma_len0),
645 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
646 dma_unmap_page(eth->dev,
647 dma_unmap_addr(tx_buf, dma_addr0),
648 dma_unmap_len(tx_buf, dma_len0),
653 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
654 dev_kfree_skb_any(tx_buf->skb);
658 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
659 int tx_num, struct mtk_tx_ring *ring, bool gso)
661 struct mtk_mac *mac = netdev_priv(dev);
662 struct mtk_eth *eth = mac->hw;
663 struct mtk_tx_dma *itxd, *txd;
664 struct mtk_tx_buf *itx_buf, *tx_buf;
665 dma_addr_t mapped_addr;
666 unsigned int nr_frags;
670 itxd = ring->next_free;
671 if (itxd == ring->last_free)
674 /* set the forward port */
675 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
678 itx_buf = mtk_desc_to_tx_buf(ring, itxd);
679 memset(itx_buf, 0, sizeof(*itx_buf));
684 /* TX Checksum offload */
685 if (skb->ip_summed == CHECKSUM_PARTIAL)
686 txd4 |= TX_DMA_CHKSUM;
688 /* VLAN header offload */
689 if (skb_vlan_tag_present(skb))
690 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
692 mapped_addr = dma_map_single(eth->dev, skb->data,
693 skb_headlen(skb), DMA_TO_DEVICE);
694 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
697 WRITE_ONCE(itxd->txd1, mapped_addr);
698 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
699 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
701 dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr);
702 dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb));
706 nr_frags = skb_shinfo(skb)->nr_frags;
707 for (i = 0; i < nr_frags; i++) {
708 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
709 unsigned int offset = 0;
710 int frag_size = skb_frag_size(frag);
713 bool last_frag = false;
714 unsigned int frag_map_size;
716 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
717 if (txd == ring->last_free)
721 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
722 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
725 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
728 if (i == nr_frags - 1 &&
729 (frag_size - frag_map_size) == 0)
732 WRITE_ONCE(txd->txd1, mapped_addr);
733 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
734 TX_DMA_PLEN0(frag_map_size) |
735 last_frag * TX_DMA_LS0));
736 WRITE_ONCE(txd->txd4, fport);
738 tx_buf = mtk_desc_to_tx_buf(ring, txd);
739 memset(tx_buf, 0, sizeof(*tx_buf));
740 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
741 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
742 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
745 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
746 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
747 frag_size -= frag_map_size;
748 offset += frag_map_size;
752 /* store skb to cleanup */
755 WRITE_ONCE(itxd->txd4, txd4);
756 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
757 (!nr_frags * TX_DMA_LS0)));
759 netdev_sent_queue(dev, skb->len);
760 skb_tx_timestamp(skb);
762 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
763 atomic_sub(n_desc, &ring->free_count);
765 /* make sure that all changes to the dma ring are flushed before we
770 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) ||
772 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
778 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
781 mtk_tx_unmap(eth, tx_buf);
783 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
784 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
785 } while (itxd != txd);
790 static inline int mtk_cal_txd_req(struct sk_buff *skb)
793 struct skb_frag_struct *frag;
796 if (skb_is_gso(skb)) {
797 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
798 frag = &skb_shinfo(skb)->frags[i];
799 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
802 nfrags += skb_shinfo(skb)->nr_frags;
808 static int mtk_queue_stopped(struct mtk_eth *eth)
812 for (i = 0; i < MTK_MAC_COUNT; i++) {
815 if (netif_queue_stopped(eth->netdev[i]))
822 static void mtk_wake_queue(struct mtk_eth *eth)
826 for (i = 0; i < MTK_MAC_COUNT; i++) {
829 netif_wake_queue(eth->netdev[i]);
833 static void mtk_stop_queue(struct mtk_eth *eth)
837 for (i = 0; i < MTK_MAC_COUNT; i++) {
840 netif_stop_queue(eth->netdev[i]);
844 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
846 struct mtk_mac *mac = netdev_priv(dev);
847 struct mtk_eth *eth = mac->hw;
848 struct mtk_tx_ring *ring = ð->tx_ring;
849 struct net_device_stats *stats = &dev->stats;
853 /* normally we can rely on the stack not calling this more than once,
854 * however we have 2 queues running on the same ring so we need to lock
857 spin_lock(ð->page_lock);
859 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
862 tx_num = mtk_cal_txd_req(skb);
863 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
865 netif_err(eth, tx_queued, dev,
866 "Tx Ring full when queue awake!\n");
867 spin_unlock(ð->page_lock);
868 return NETDEV_TX_BUSY;
871 /* TSO: fill MSS info in tcp checksum field */
872 if (skb_is_gso(skb)) {
873 if (skb_cow_head(skb, 0)) {
874 netif_warn(eth, tx_err, dev,
875 "GSO expand head fail.\n");
879 if (skb_shinfo(skb)->gso_type &
880 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
882 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
886 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
889 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
892 spin_unlock(ð->page_lock);
897 spin_unlock(ð->page_lock);
899 dev_kfree_skb_any(skb);
903 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
906 struct mtk_rx_ring *ring;
910 return ð->rx_ring[0];
912 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
913 ring = ð->rx_ring[i];
914 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
915 if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
916 ring->calc_idx_update = true;
924 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
926 struct mtk_rx_ring *ring;
930 ring = ð->rx_ring[0];
931 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
933 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
934 ring = ð->rx_ring[i];
935 if (ring->calc_idx_update) {
936 ring->calc_idx_update = false;
937 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
943 static int mtk_poll_rx(struct napi_struct *napi, int budget,
946 struct mtk_rx_ring *ring;
950 struct mtk_rx_dma *rxd, trxd;
953 while (done < budget) {
954 struct net_device *netdev;
959 ring = mtk_get_rx_ring(eth);
963 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
964 rxd = &ring->dma[idx];
965 data = ring->data[idx];
967 mtk_rx_get_desc(&trxd, rxd);
968 if (!(trxd.rxd2 & RX_DMA_DONE))
971 /* find out which mac the packet come from. values start at 1 */
972 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
976 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
980 netdev = eth->netdev[mac];
982 if (unlikely(test_bit(MTK_RESETTING, ð->state)))
985 /* alloc new buffer */
986 new_data = napi_alloc_frag(ring->frag_size);
987 if (unlikely(!new_data)) {
988 netdev->stats.rx_dropped++;
991 dma_addr = dma_map_single(eth->dev,
992 new_data + NET_SKB_PAD,
995 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
996 skb_free_frag(new_data);
997 netdev->stats.rx_dropped++;
1002 skb = build_skb(data, ring->frag_size);
1003 if (unlikely(!skb)) {
1004 skb_free_frag(new_data);
1005 netdev->stats.rx_dropped++;
1008 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
1010 dma_unmap_single(eth->dev, trxd.rxd1,
1011 ring->buf_size, DMA_FROM_DEVICE);
1012 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1014 skb_put(skb, pktlen);
1015 if (trxd.rxd4 & RX_DMA_L4_VALID)
1016 skb->ip_summed = CHECKSUM_UNNECESSARY;
1018 skb_checksum_none_assert(skb);
1019 skb->protocol = eth_type_trans(skb, netdev);
1021 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
1022 RX_DMA_VID(trxd.rxd3))
1023 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1024 RX_DMA_VID(trxd.rxd3));
1025 skb_record_rx_queue(skb, 0);
1026 napi_gro_receive(napi, skb);
1028 ring->data[idx] = new_data;
1029 rxd->rxd1 = (unsigned int)dma_addr;
1032 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
1034 ring->calc_idx = idx;
1041 /* make sure that all changes to the dma ring are flushed before
1045 mtk_update_rx_cpu_idx(eth);
1051 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
1053 struct mtk_tx_ring *ring = ð->tx_ring;
1054 struct mtk_tx_dma *desc;
1055 struct sk_buff *skb;
1056 struct mtk_tx_buf *tx_buf;
1057 unsigned int done[MTK_MAX_DEVS];
1058 unsigned int bytes[MTK_MAX_DEVS];
1062 memset(done, 0, sizeof(done));
1063 memset(bytes, 0, sizeof(bytes));
1065 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
1066 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
1068 desc = mtk_qdma_phys_to_virt(ring, cpu);
1070 while ((cpu != dma) && budget) {
1071 u32 next_cpu = desc->txd2;
1074 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
1075 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
1078 tx_buf = mtk_desc_to_tx_buf(ring, desc);
1079 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
1086 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1087 bytes[mac] += skb->len;
1091 mtk_tx_unmap(eth, tx_buf);
1093 ring->last_free = desc;
1094 atomic_inc(&ring->free_count);
1099 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1101 for (i = 0; i < MTK_MAC_COUNT; i++) {
1102 if (!eth->netdev[i] || !done[i])
1104 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1108 if (mtk_queue_stopped(eth) &&
1109 (atomic_read(&ring->free_count) > ring->thresh))
1110 mtk_wake_queue(eth);
1115 static void mtk_handle_status_irq(struct mtk_eth *eth)
1117 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
1119 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
1120 mtk_stats_update(eth);
1121 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
1126 static int mtk_napi_tx(struct napi_struct *napi, int budget)
1128 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
1132 mtk_handle_status_irq(eth);
1133 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
1134 tx_done = mtk_poll_tx(eth, budget);
1136 if (unlikely(netif_msg_intr(eth))) {
1137 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1138 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1140 "done tx %d, intr 0x%08x/0x%x\n",
1141 tx_done, status, mask);
1144 if (tx_done == budget)
1147 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1148 if (status & MTK_TX_DONE_INT)
1151 napi_complete(napi);
1152 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1157 static int mtk_napi_rx(struct napi_struct *napi, int budget)
1159 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1162 int remain_budget = budget;
1164 mtk_handle_status_irq(eth);
1167 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
1168 rx_done = mtk_poll_rx(napi, remain_budget, eth);
1170 if (unlikely(netif_msg_intr(eth))) {
1171 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1172 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
1174 "done rx %d, intr 0x%08x/0x%x\n",
1175 rx_done, status, mask);
1177 if (rx_done == remain_budget)
1180 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1181 if (status & MTK_RX_DONE_INT) {
1182 remain_budget -= rx_done;
1185 napi_complete(napi);
1186 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1188 return rx_done + budget - remain_budget;
1191 static int mtk_tx_alloc(struct mtk_eth *eth)
1193 struct mtk_tx_ring *ring = ð->tx_ring;
1194 int i, sz = sizeof(*ring->dma);
1196 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1201 ring->dma = dma_alloc_coherent(eth->dev, MTK_DMA_SIZE * sz,
1202 &ring->phys, GFP_ATOMIC);
1206 for (i = 0; i < MTK_DMA_SIZE; i++) {
1207 int next = (i + 1) % MTK_DMA_SIZE;
1208 u32 next_ptr = ring->phys + next * sz;
1210 ring->dma[i].txd2 = next_ptr;
1211 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1214 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1215 ring->next_free = &ring->dma[0];
1216 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1217 ring->thresh = MAX_SKB_FRAGS;
1219 /* make sure that all changes to the dma ring are flushed before we
1224 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1225 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1227 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1230 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1232 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1240 static void mtk_tx_clean(struct mtk_eth *eth)
1242 struct mtk_tx_ring *ring = ð->tx_ring;
1246 for (i = 0; i < MTK_DMA_SIZE; i++)
1247 mtk_tx_unmap(eth, &ring->buf[i]);
1253 dma_free_coherent(eth->dev,
1254 MTK_DMA_SIZE * sizeof(*ring->dma),
1261 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
1263 struct mtk_rx_ring *ring;
1264 int rx_data_len, rx_dma_size;
1268 if (rx_flag == MTK_RX_FLAGS_QDMA) {
1271 ring = ð->rx_ring_qdma;
1274 ring = ð->rx_ring[ring_no];
1277 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
1278 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
1279 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
1281 rx_data_len = ETH_DATA_LEN;
1282 rx_dma_size = MTK_DMA_SIZE;
1285 ring->frag_size = mtk_max_frag_size(rx_data_len);
1286 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1287 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
1292 for (i = 0; i < rx_dma_size; i++) {
1293 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1298 ring->dma = dma_alloc_coherent(eth->dev,
1299 rx_dma_size * sizeof(*ring->dma),
1300 &ring->phys, GFP_ATOMIC);
1304 for (i = 0; i < rx_dma_size; i++) {
1305 dma_addr_t dma_addr = dma_map_single(eth->dev,
1306 ring->data[i] + NET_SKB_PAD,
1309 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1311 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1313 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1315 ring->dma_size = rx_dma_size;
1316 ring->calc_idx_update = false;
1317 ring->calc_idx = rx_dma_size - 1;
1318 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
1319 /* make sure that all changes to the dma ring are flushed before we
1324 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);
1325 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);
1326 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);
1327 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);
1332 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
1336 if (ring->data && ring->dma) {
1337 for (i = 0; i < ring->dma_size; i++) {
1340 if (!ring->dma[i].rxd1)
1342 dma_unmap_single(eth->dev,
1346 skb_free_frag(ring->data[i]);
1353 dma_free_coherent(eth->dev,
1354 ring->dma_size * sizeof(*ring->dma),
1361 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
1364 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
1365 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
1367 /* set LRO rings to auto-learn modes */
1368 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
1370 /* validate LRO ring */
1371 ring_ctrl_dw2 |= MTK_RING_VLD;
1373 /* set AGE timer (unit: 20us) */
1374 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
1375 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
1377 /* set max AGG timer (unit: 20us) */
1378 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
1380 /* set max LRO AGG count */
1381 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
1382 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
1384 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1385 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
1386 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
1387 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
1390 /* IPv4 checksum update enable */
1391 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
1393 /* switch priority comparison to packet count mode */
1394 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
1396 /* bandwidth threshold setting */
1397 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
1399 /* auto-learn score delta setting */
1400 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
1402 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1403 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
1404 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
1406 /* set HW LRO mode & the max aggregation count for rx packets */
1407 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
1409 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
1410 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
1413 lro_ctrl_dw0 |= MTK_LRO_EN;
1415 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
1416 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
1421 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
1426 /* relinquish lro rings, flush aggregated packets */
1427 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
1429 /* wait for relinquishments done */
1430 for (i = 0; i < 10; i++) {
1431 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
1432 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
1439 /* invalidate lro rings */
1440 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1441 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
1443 /* disable HW LRO */
1444 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
1447 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
1451 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1453 /* invalidate the IP setting */
1454 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1456 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
1458 /* validate the IP setting */
1459 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1462 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
1466 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1468 /* invalidate the IP setting */
1469 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1471 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
1474 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
1479 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1480 if (mac->hwlro_ip[i])
1487 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
1488 struct ethtool_rxnfc *cmd)
1490 struct ethtool_rx_flow_spec *fsp =
1491 (struct ethtool_rx_flow_spec *)&cmd->fs;
1492 struct mtk_mac *mac = netdev_priv(dev);
1493 struct mtk_eth *eth = mac->hw;
1496 if ((fsp->flow_type != TCP_V4_FLOW) ||
1497 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
1498 (fsp->location > 1))
1501 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
1502 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1504 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1506 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
1511 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
1512 struct ethtool_rxnfc *cmd)
1514 struct ethtool_rx_flow_spec *fsp =
1515 (struct ethtool_rx_flow_spec *)&cmd->fs;
1516 struct mtk_mac *mac = netdev_priv(dev);
1517 struct mtk_eth *eth = mac->hw;
1520 if (fsp->location > 1)
1523 mac->hwlro_ip[fsp->location] = 0;
1524 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1526 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1528 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1533 static void mtk_hwlro_netdev_disable(struct net_device *dev)
1535 struct mtk_mac *mac = netdev_priv(dev);
1536 struct mtk_eth *eth = mac->hw;
1539 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1540 mac->hwlro_ip[i] = 0;
1541 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
1543 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1546 mac->hwlro_ip_cnt = 0;
1549 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
1550 struct ethtool_rxnfc *cmd)
1552 struct mtk_mac *mac = netdev_priv(dev);
1553 struct ethtool_rx_flow_spec *fsp =
1554 (struct ethtool_rx_flow_spec *)&cmd->fs;
1556 /* only tcp dst ipv4 is meaningful, others are meaningless */
1557 fsp->flow_type = TCP_V4_FLOW;
1558 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
1559 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
1561 fsp->h_u.tcp_ip4_spec.ip4src = 0;
1562 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
1563 fsp->h_u.tcp_ip4_spec.psrc = 0;
1564 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
1565 fsp->h_u.tcp_ip4_spec.pdst = 0;
1566 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
1567 fsp->h_u.tcp_ip4_spec.tos = 0;
1568 fsp->m_u.tcp_ip4_spec.tos = 0xff;
1573 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
1574 struct ethtool_rxnfc *cmd,
1577 struct mtk_mac *mac = netdev_priv(dev);
1581 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1582 if (mac->hwlro_ip[i]) {
1588 cmd->rule_cnt = cnt;
1593 static netdev_features_t mtk_fix_features(struct net_device *dev,
1594 netdev_features_t features)
1596 if (!(features & NETIF_F_LRO)) {
1597 struct mtk_mac *mac = netdev_priv(dev);
1598 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1601 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
1603 features |= NETIF_F_LRO;
1610 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
1614 if (!((dev->features ^ features) & NETIF_F_LRO))
1617 if (!(features & NETIF_F_LRO))
1618 mtk_hwlro_netdev_disable(dev);
1623 /* wait for DMA to finish whatever it is doing before we start using it again */
1624 static int mtk_dma_busy_wait(struct mtk_eth *eth)
1626 unsigned long t_start = jiffies;
1629 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1630 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1632 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1636 dev_err(eth->dev, "DMA init timeout\n");
1640 static int mtk_dma_init(struct mtk_eth *eth)
1645 if (mtk_dma_busy_wait(eth))
1648 /* QDMA needs scratch memory for internal reordering of the
1651 err = mtk_init_fq_dma(eth);
1655 err = mtk_tx_alloc(eth);
1659 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
1663 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
1668 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1669 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
1673 err = mtk_hwlro_rx_init(eth);
1678 /* Enable random early drop and set drop threshold automatically */
1679 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1681 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1686 static void mtk_dma_free(struct mtk_eth *eth)
1690 for (i = 0; i < MTK_MAC_COUNT; i++)
1692 netdev_reset_queue(eth->netdev[i]);
1693 if (eth->scratch_ring) {
1694 dma_free_coherent(eth->dev,
1695 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1697 eth->phy_scratch_ring);
1698 eth->scratch_ring = NULL;
1699 eth->phy_scratch_ring = 0;
1702 mtk_rx_clean(eth, ð->rx_ring[0]);
1703 mtk_rx_clean(eth, ð->rx_ring_qdma);
1706 mtk_hwlro_rx_uninit(eth);
1707 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1708 mtk_rx_clean(eth, ð->rx_ring[i]);
1711 kfree(eth->scratch_head);
1714 static void mtk_tx_timeout(struct net_device *dev)
1716 struct mtk_mac *mac = netdev_priv(dev);
1717 struct mtk_eth *eth = mac->hw;
1719 eth->netdev[mac->id]->stats.tx_errors++;
1720 netif_err(eth, tx_err, dev,
1721 "transmit timed out\n");
1722 schedule_work(ð->pending_work);
1725 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
1727 struct mtk_eth *eth = _eth;
1729 if (likely(napi_schedule_prep(ð->rx_napi))) {
1730 __napi_schedule(ð->rx_napi);
1731 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
1737 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1739 struct mtk_eth *eth = _eth;
1741 if (likely(napi_schedule_prep(ð->tx_napi))) {
1742 __napi_schedule(ð->tx_napi);
1743 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1749 static irqreturn_t mtk_handle_irq(int irq, void *_eth)
1751 struct mtk_eth *eth = _eth;
1753 if (mtk_r32(eth, MTK_PDMA_INT_MASK) & MTK_RX_DONE_INT) {
1754 if (mtk_r32(eth, MTK_PDMA_INT_STATUS) & MTK_RX_DONE_INT)
1755 mtk_handle_irq_rx(irq, _eth);
1757 if (mtk_r32(eth, MTK_QDMA_INT_MASK) & MTK_TX_DONE_INT) {
1758 if (mtk_r32(eth, MTK_QMTK_INT_STATUS) & MTK_TX_DONE_INT)
1759 mtk_handle_irq_tx(irq, _eth);
1765 #ifdef CONFIG_NET_POLL_CONTROLLER
1766 static void mtk_poll_controller(struct net_device *dev)
1768 struct mtk_mac *mac = netdev_priv(dev);
1769 struct mtk_eth *eth = mac->hw;
1771 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1772 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
1773 mtk_handle_irq_rx(eth->irq[2], dev);
1774 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1775 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1779 static int mtk_start_dma(struct mtk_eth *eth)
1783 err = mtk_dma_init(eth);
1790 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
1791 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO |
1792 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1797 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1798 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
1804 static int mtk_open(struct net_device *dev)
1806 struct mtk_mac *mac = netdev_priv(dev);
1807 struct mtk_eth *eth = mac->hw;
1809 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1810 if (!refcount_read(ð->dma_refcnt)) {
1811 int err = mtk_start_dma(eth);
1816 napi_enable(ð->tx_napi);
1817 napi_enable(ð->rx_napi);
1818 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1819 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1820 refcount_set(ð->dma_refcnt, 1);
1823 refcount_inc(ð->dma_refcnt);
1825 phy_start(dev->phydev);
1826 netif_start_queue(dev);
1831 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1836 /* stop the dma engine */
1837 spin_lock_bh(ð->page_lock);
1838 val = mtk_r32(eth, glo_cfg);
1839 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1841 spin_unlock_bh(ð->page_lock);
1843 /* wait for dma stop */
1844 for (i = 0; i < 10; i++) {
1845 val = mtk_r32(eth, glo_cfg);
1846 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1854 static int mtk_stop(struct net_device *dev)
1856 struct mtk_mac *mac = netdev_priv(dev);
1857 struct mtk_eth *eth = mac->hw;
1859 netif_tx_disable(dev);
1860 phy_stop(dev->phydev);
1862 /* only shutdown DMA if this is the last user */
1863 if (!refcount_dec_and_test(ð->dma_refcnt))
1866 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1867 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
1868 napi_disable(ð->tx_napi);
1869 napi_disable(ð->rx_napi);
1871 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1872 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG);
1879 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
1881 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1885 usleep_range(1000, 1100);
1886 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1892 static void mtk_clk_disable(struct mtk_eth *eth)
1896 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
1897 clk_disable_unprepare(eth->clks[clk]);
1900 static int mtk_clk_enable(struct mtk_eth *eth)
1904 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
1905 ret = clk_prepare_enable(eth->clks[clk]);
1907 goto err_disable_clks;
1914 clk_disable_unprepare(eth->clks[clk]);
1919 static int mtk_hw_init(struct mtk_eth *eth)
1923 if (test_and_set_bit(MTK_HW_INIT, ð->state))
1926 pm_runtime_enable(eth->dev);
1927 pm_runtime_get_sync(eth->dev);
1929 ret = mtk_clk_enable(eth);
1931 goto err_disable_pm;
1933 ethsys_reset(eth, RSTCTRL_FE);
1934 ethsys_reset(eth, RSTCTRL_PPE);
1936 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
1937 for (i = 0; i < MTK_MAC_COUNT; i++) {
1940 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id);
1941 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id);
1943 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
1946 /* Set GE2 driving and slew rate */
1947 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1950 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1953 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1956 /* Set linkdown as the default for each GMAC. Its own MCR would be set
1957 * up with the more appropriate value when mtk_phy_link_adjust call is
1960 for (i = 0; i < MTK_MAC_COUNT; i++)
1961 mtk_w32(eth, 0, MTK_MAC_MCR(i));
1963 /* Indicates CDM to parse the MTK special tag from CPU
1964 * which also is working out for untag packets.
1966 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
1967 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
1969 /* Enable RX VLan Offloading */
1970 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1972 /* enable interrupt delay for RX */
1973 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
1975 /* disable delay and normal interrupt */
1976 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1977 mtk_tx_irq_disable(eth, ~0);
1978 mtk_rx_irq_disable(eth, ~0);
1979 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1980 mtk_w32(eth, 0, MTK_RST_GL);
1982 /* FE int grouping */
1983 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1984 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1985 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1986 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1987 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
1989 for (i = 0; i < 2; i++) {
1990 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1992 /* setup the forward port to send frame to PDMA */
1995 /* Enable RX checksum */
1996 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1998 /* setup the mac dma */
1999 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
2005 pm_runtime_put_sync(eth->dev);
2006 pm_runtime_disable(eth->dev);
2011 static int mtk_hw_deinit(struct mtk_eth *eth)
2013 if (!test_and_clear_bit(MTK_HW_INIT, ð->state))
2016 mtk_clk_disable(eth);
2018 pm_runtime_put_sync(eth->dev);
2019 pm_runtime_disable(eth->dev);
2024 static int __init mtk_init(struct net_device *dev)
2026 struct mtk_mac *mac = netdev_priv(dev);
2027 struct mtk_eth *eth = mac->hw;
2028 const char *mac_addr;
2030 mac_addr = of_get_mac_address(mac->of_node);
2032 ether_addr_copy(dev->dev_addr, mac_addr);
2034 /* If the mac address is invalid, use random mac address */
2035 if (!is_valid_ether_addr(dev->dev_addr)) {
2036 eth_hw_addr_random(dev);
2037 dev_err(eth->dev, "generated random MAC address %pM\n",
2041 return mtk_phy_connect(dev);
2044 static void mtk_uninit(struct net_device *dev)
2046 struct mtk_mac *mac = netdev_priv(dev);
2047 struct mtk_eth *eth = mac->hw;
2049 phy_disconnect(dev->phydev);
2050 if (of_phy_is_fixed_link(mac->of_node))
2051 of_phy_deregister_fixed_link(mac->of_node);
2052 mtk_tx_irq_disable(eth, ~0);
2053 mtk_rx_irq_disable(eth, ~0);
2056 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2062 return phy_mii_ioctl(dev->phydev, ifr, cmd);
2070 static void mtk_pending_work(struct work_struct *work)
2072 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
2074 unsigned long restart = 0;
2078 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
2080 while (test_and_set_bit_lock(MTK_RESETTING, ð->state))
2083 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
2084 /* stop all devices to make sure that dma is properly shut down */
2085 for (i = 0; i < MTK_MAC_COUNT; i++) {
2086 if (!eth->netdev[i])
2088 mtk_stop(eth->netdev[i]);
2089 __set_bit(i, &restart);
2091 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
2093 /* restart underlying hardware such as power, clock, pin mux
2094 * and the connected phy
2099 pinctrl_select_state(eth->dev->pins->p,
2100 eth->dev->pins->default_state);
2103 for (i = 0; i < MTK_MAC_COUNT; i++) {
2105 of_phy_is_fixed_link(eth->mac[i]->of_node))
2107 err = phy_init_hw(eth->netdev[i]->phydev);
2109 dev_err(eth->dev, "%s: PHY init failed.\n",
2110 eth->netdev[i]->name);
2113 /* restart DMA and enable IRQs */
2114 for (i = 0; i < MTK_MAC_COUNT; i++) {
2115 if (!test_bit(i, &restart))
2117 err = mtk_open(eth->netdev[i]);
2119 netif_alert(eth, ifup, eth->netdev[i],
2120 "Driver up/down cycle failed, closing device.\n");
2121 dev_close(eth->netdev[i]);
2125 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
2127 clear_bit_unlock(MTK_RESETTING, ð->state);
2132 static int mtk_free_dev(struct mtk_eth *eth)
2136 for (i = 0; i < MTK_MAC_COUNT; i++) {
2137 if (!eth->netdev[i])
2139 free_netdev(eth->netdev[i]);
2145 static int mtk_unreg_dev(struct mtk_eth *eth)
2149 for (i = 0; i < MTK_MAC_COUNT; i++) {
2150 if (!eth->netdev[i])
2152 unregister_netdev(eth->netdev[i]);
2158 static int mtk_cleanup(struct mtk_eth *eth)
2162 cancel_work_sync(ð->pending_work);
2167 static int mtk_get_link_ksettings(struct net_device *ndev,
2168 struct ethtool_link_ksettings *cmd)
2170 struct mtk_mac *mac = netdev_priv(ndev);
2172 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2175 phy_ethtool_ksettings_get(ndev->phydev, cmd);
2180 static int mtk_set_link_ksettings(struct net_device *ndev,
2181 const struct ethtool_link_ksettings *cmd)
2183 struct mtk_mac *mac = netdev_priv(ndev);
2185 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2188 return phy_ethtool_ksettings_set(ndev->phydev, cmd);
2191 static void mtk_get_drvinfo(struct net_device *dev,
2192 struct ethtool_drvinfo *info)
2194 struct mtk_mac *mac = netdev_priv(dev);
2196 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
2197 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
2198 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
2201 static u32 mtk_get_msglevel(struct net_device *dev)
2203 struct mtk_mac *mac = netdev_priv(dev);
2205 return mac->hw->msg_enable;
2208 static void mtk_set_msglevel(struct net_device *dev, u32 value)
2210 struct mtk_mac *mac = netdev_priv(dev);
2212 mac->hw->msg_enable = value;
2215 static int mtk_nway_reset(struct net_device *dev)
2217 struct mtk_mac *mac = netdev_priv(dev);
2219 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2222 return genphy_restart_aneg(dev->phydev);
2225 static u32 mtk_get_link(struct net_device *dev)
2227 struct mtk_mac *mac = netdev_priv(dev);
2230 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2233 err = genphy_update_link(dev->phydev);
2235 return ethtool_op_get_link(dev);
2237 return dev->phydev->link;
2240 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2244 switch (stringset) {
2246 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
2247 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
2248 data += ETH_GSTRING_LEN;
2254 static int mtk_get_sset_count(struct net_device *dev, int sset)
2258 return ARRAY_SIZE(mtk_ethtool_stats);
2264 static void mtk_get_ethtool_stats(struct net_device *dev,
2265 struct ethtool_stats *stats, u64 *data)
2267 struct mtk_mac *mac = netdev_priv(dev);
2268 struct mtk_hw_stats *hwstats = mac->hw_stats;
2269 u64 *data_src, *data_dst;
2273 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2276 if (netif_running(dev) && netif_device_present(dev)) {
2277 if (spin_trylock_bh(&hwstats->stats_lock)) {
2278 mtk_stats_update_mac(mac);
2279 spin_unlock_bh(&hwstats->stats_lock);
2283 data_src = (u64 *)hwstats;
2287 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2289 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2290 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2291 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2294 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2297 int ret = -EOPNOTSUPP;
2300 case ETHTOOL_GRXRINGS:
2301 if (dev->features & NETIF_F_LRO) {
2302 cmd->data = MTK_MAX_RX_RING_NUM;
2306 case ETHTOOL_GRXCLSRLCNT:
2307 if (dev->features & NETIF_F_LRO) {
2308 struct mtk_mac *mac = netdev_priv(dev);
2310 cmd->rule_cnt = mac->hwlro_ip_cnt;
2314 case ETHTOOL_GRXCLSRULE:
2315 if (dev->features & NETIF_F_LRO)
2316 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
2318 case ETHTOOL_GRXCLSRLALL:
2319 if (dev->features & NETIF_F_LRO)
2320 ret = mtk_hwlro_get_fdir_all(dev, cmd,
2330 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2332 int ret = -EOPNOTSUPP;
2335 case ETHTOOL_SRXCLSRLINS:
2336 if (dev->features & NETIF_F_LRO)
2337 ret = mtk_hwlro_add_ipaddr(dev, cmd);
2339 case ETHTOOL_SRXCLSRLDEL:
2340 if (dev->features & NETIF_F_LRO)
2341 ret = mtk_hwlro_del_ipaddr(dev, cmd);
2350 static const struct ethtool_ops mtk_ethtool_ops = {
2351 .get_link_ksettings = mtk_get_link_ksettings,
2352 .set_link_ksettings = mtk_set_link_ksettings,
2353 .get_drvinfo = mtk_get_drvinfo,
2354 .get_msglevel = mtk_get_msglevel,
2355 .set_msglevel = mtk_set_msglevel,
2356 .nway_reset = mtk_nway_reset,
2357 .get_link = mtk_get_link,
2358 .get_strings = mtk_get_strings,
2359 .get_sset_count = mtk_get_sset_count,
2360 .get_ethtool_stats = mtk_get_ethtool_stats,
2361 .get_rxnfc = mtk_get_rxnfc,
2362 .set_rxnfc = mtk_set_rxnfc,
2365 static const struct net_device_ops mtk_netdev_ops = {
2366 .ndo_init = mtk_init,
2367 .ndo_uninit = mtk_uninit,
2368 .ndo_open = mtk_open,
2369 .ndo_stop = mtk_stop,
2370 .ndo_start_xmit = mtk_start_xmit,
2371 .ndo_set_mac_address = mtk_set_mac_address,
2372 .ndo_validate_addr = eth_validate_addr,
2373 .ndo_do_ioctl = mtk_do_ioctl,
2374 .ndo_tx_timeout = mtk_tx_timeout,
2375 .ndo_get_stats64 = mtk_get_stats64,
2376 .ndo_fix_features = mtk_fix_features,
2377 .ndo_set_features = mtk_set_features,
2378 #ifdef CONFIG_NET_POLL_CONTROLLER
2379 .ndo_poll_controller = mtk_poll_controller,
2383 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
2385 struct mtk_mac *mac;
2386 const __be32 *_id = of_get_property(np, "reg", NULL);
2390 dev_err(eth->dev, "missing mac id\n");
2394 id = be32_to_cpup(_id);
2395 if (id >= MTK_MAC_COUNT) {
2396 dev_err(eth->dev, "%d is not a valid mac id\n", id);
2400 if (eth->netdev[id]) {
2401 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
2405 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2406 if (!eth->netdev[id]) {
2407 dev_err(eth->dev, "alloc_etherdev failed\n");
2410 mac = netdev_priv(eth->netdev[id]);
2416 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
2417 mac->hwlro_ip_cnt = 0;
2419 mac->hw_stats = devm_kzalloc(eth->dev,
2420 sizeof(*mac->hw_stats),
2422 if (!mac->hw_stats) {
2423 dev_err(eth->dev, "failed to allocate counter memory\n");
2427 spin_lock_init(&mac->hw_stats->stats_lock);
2428 u64_stats_init(&mac->hw_stats->syncp);
2429 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2431 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
2432 eth->netdev[id]->watchdog_timeo = 5 * HZ;
2433 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2434 eth->netdev[id]->base_addr = (unsigned long)eth->base;
2436 eth->netdev[id]->hw_features = MTK_HW_FEATURES;
2438 eth->netdev[id]->hw_features |= NETIF_F_LRO;
2440 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
2441 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2442 eth->netdev[id]->features |= MTK_HW_FEATURES;
2443 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
2445 eth->netdev[id]->irq = eth->irq[0];
2446 eth->netdev[id]->dev.of_node = np;
2451 free_netdev(eth->netdev[id]);
2455 static int mtk_probe(struct platform_device *pdev)
2457 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2458 struct device_node *mac_np;
2459 struct mtk_eth *eth;
2463 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2467 eth->soc = of_device_get_match_data(&pdev->dev);
2469 eth->dev = &pdev->dev;
2470 eth->base = devm_ioremap_resource(&pdev->dev, res);
2471 if (IS_ERR(eth->base))
2472 return PTR_ERR(eth->base);
2474 spin_lock_init(ð->page_lock);
2475 spin_lock_init(ð->tx_irq_lock);
2476 spin_lock_init(ð->rx_irq_lock);
2478 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2480 if (IS_ERR(eth->ethsys)) {
2481 dev_err(&pdev->dev, "no ethsys regmap found\n");
2482 return PTR_ERR(eth->ethsys);
2485 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
2487 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2488 "mediatek,sgmiisys");
2489 if (IS_ERR(eth->sgmiisys)) {
2490 dev_err(&pdev->dev, "no sgmiisys regmap found\n");
2491 return PTR_ERR(eth->sgmiisys);
2495 if (eth->soc->required_pctl) {
2496 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2498 if (IS_ERR(eth->pctl)) {
2499 dev_err(&pdev->dev, "no pctl regmap found\n");
2500 return PTR_ERR(eth->pctl);
2504 for (i = 0; i < 3; i++) {
2505 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
2506 eth->irq[i] = eth->irq[0];
2508 eth->irq[i] = platform_get_irq(pdev, i);
2509 if (eth->irq[i] < 0) {
2510 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
2514 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
2515 eth->clks[i] = devm_clk_get(eth->dev,
2516 mtk_clks_source_name[i]);
2517 if (IS_ERR(eth->clks[i])) {
2518 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
2519 return -EPROBE_DEFER;
2520 if (eth->soc->required_clks & BIT(i)) {
2521 dev_err(&pdev->dev, "clock %s not found\n",
2522 mtk_clks_source_name[i]);
2525 eth->clks[i] = NULL;
2529 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
2530 INIT_WORK(ð->pending_work, mtk_pending_work);
2532 err = mtk_hw_init(eth);
2536 eth->hwlro = MTK_HAS_CAPS(eth->soc->caps, MTK_HWLRO);
2538 for_each_child_of_node(pdev->dev.of_node, mac_np) {
2539 if (!of_device_is_compatible(mac_np,
2540 "mediatek,eth-mac"))
2543 if (!of_device_is_available(mac_np))
2546 err = mtk_add_mac(eth, mac_np);
2551 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
2552 err = devm_request_irq(eth->dev, eth->irq[0],
2554 dev_name(eth->dev), eth);
2556 err = devm_request_irq(eth->dev, eth->irq[1],
2557 mtk_handle_irq_tx, 0,
2558 dev_name(eth->dev), eth);
2562 err = devm_request_irq(eth->dev, eth->irq[2],
2563 mtk_handle_irq_rx, 0,
2564 dev_name(eth->dev), eth);
2569 err = mtk_mdio_init(eth);
2573 for (i = 0; i < MTK_MAX_DEVS; i++) {
2574 if (!eth->netdev[i])
2577 err = register_netdev(eth->netdev[i]);
2579 dev_err(eth->dev, "error bringing up device\n");
2580 goto err_deinit_mdio;
2582 netif_info(eth, probe, eth->netdev[i],
2583 "mediatek frame engine at 0x%08lx, irq %d\n",
2584 eth->netdev[i]->base_addr, eth->irq[0]);
2587 /* we run 2 devices on the same DMA ring so we need a dummy device
2590 init_dummy_netdev(ð->dummy_dev);
2591 netif_napi_add(ð->dummy_dev, ð->tx_napi, mtk_napi_tx,
2593 netif_napi_add(ð->dummy_dev, ð->rx_napi, mtk_napi_rx,
2596 platform_set_drvdata(pdev, eth);
2601 mtk_mdio_cleanup(eth);
2610 static int mtk_remove(struct platform_device *pdev)
2612 struct mtk_eth *eth = platform_get_drvdata(pdev);
2615 /* stop all devices to make sure that dma is properly shut down */
2616 for (i = 0; i < MTK_MAC_COUNT; i++) {
2617 if (!eth->netdev[i])
2619 mtk_stop(eth->netdev[i]);
2624 netif_napi_del(ð->tx_napi);
2625 netif_napi_del(ð->rx_napi);
2627 mtk_mdio_cleanup(eth);
2632 static const struct mtk_soc_data mt2701_data = {
2633 .caps = MTK_GMAC1_TRGMII | MTK_HWLRO,
2634 .required_clks = MT7623_CLKS_BITMAP,
2635 .required_pctl = true,
2638 static const struct mtk_soc_data mt7621_data = {
2639 .caps = MTK_SHARED_INT,
2640 .required_clks = MT7621_CLKS_BITMAP,
2641 .required_pctl = false,
2644 static const struct mtk_soc_data mt7622_data = {
2645 .caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW | MTK_HWLRO,
2646 .required_clks = MT7622_CLKS_BITMAP,
2647 .required_pctl = false,
2650 static const struct mtk_soc_data mt7623_data = {
2651 .caps = MTK_GMAC1_TRGMII | MTK_HWLRO,
2652 .required_clks = MT7623_CLKS_BITMAP,
2653 .required_pctl = true,
2656 const struct of_device_id of_mtk_match[] = {
2657 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
2658 { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data},
2659 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
2660 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
2663 MODULE_DEVICE_TABLE(of, of_mtk_match);
2665 static struct platform_driver mtk_driver = {
2667 .remove = mtk_remove,
2669 .name = "mtk_soc_eth",
2670 .of_match_table = of_mtk_match,
2674 module_platform_driver(mtk_driver);
2676 MODULE_LICENSE("GPL");
2677 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2678 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");