drivers/net/ethernet/mellanox/mlx4/en_rx.c

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #include <net/busy_poll.h>
  35 #include <linux/bpf.h>
  36 #include <linux/mlx4/cq.h>
  37 #include <linux/slab.h>
  38 #include <linux/mlx4/qp.h>
  39 #include <linux/skbuff.h>
  40 #include <linux/rculist.h>
  41 #include <linux/if_ether.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/vmalloc.h>
  44 #include <linux/irq.h>
  45
  46 #if IS_ENABLED(CONFIG_IPV6)
  47 #include <net/ip6_checksum.h>
  48 #endif
  49
  50 #include "mlx4_en.h"
  51
  52 static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
  53                             struct mlx4_en_rx_alloc *page_alloc,
  54                             const struct mlx4_en_frag_info *frag_info,
  55                             gfp_t _gfp)
  56 {
  57         int order;
  58         struct page *page;
  59         dma_addr_t dma;
  60
  61         for (order = frag_info->order; ;) {
  62                 gfp_t gfp = _gfp;
  63
  64                 if (order)
  65                         gfp |= __GFP_COMP | __GFP_NOWARN | __GFP_NOMEMALLOC;
  66                 page = alloc_pages(gfp, order);
  67                 if (likely(page))
  68                         break;
  69                 if (--order < 0 ||
  70                     ((PAGE_SIZE << order) < frag_info->frag_size))
  71                         return -ENOMEM;
  72         }
  73         dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
  74                            frag_info->dma_dir);
  75         if (unlikely(dma_mapping_error(priv->ddev, dma))) {
  76                 put_page(page);
  77                 return -ENOMEM;
  78         }
  79         page_alloc->page_size = PAGE_SIZE << order;
  80         page_alloc->page = page;
  81         page_alloc->dma = dma;
  82         page_alloc->page_offset = 0;
  83         /* Not doing get_page() for each frag is a big win
  84          * on asymetric workloads. Note we can not use atomic_set().
  85          */
  86         page_ref_add(page, page_alloc->page_size / frag_info->frag_stride - 1);
  87         return 0;
  88 }
  89
  90 static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
  91                                struct mlx4_en_rx_desc *rx_desc,
  92                                struct mlx4_en_rx_alloc *frags,
  93                                struct mlx4_en_rx_alloc *ring_alloc,
  94                                gfp_t gfp)
  95 {
  96         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
  97         const struct mlx4_en_frag_info *frag_info;
  98         struct page *page;
  99         int i;
 100
 101         for (i = 0; i < priv->num_frags; i++) {
 102                 frag_info = &priv->frag_info[i];
 103                 page_alloc[i] = ring_alloc[i];
 104                 page_alloc[i].page_offset += frag_info->frag_stride;
 105
 106                 if (page_alloc[i].page_offset + frag_info->frag_stride <=
 107                     ring_alloc[i].page_size)
 108                         continue;
 109
 110                 if (unlikely(mlx4_alloc_pages(priv, &page_alloc[i],
 111                                               frag_info, gfp)))
 112                         goto out;
 113         }
 114
 115         for (i = 0; i < priv->num_frags; i++) {
 116                 frags[i] = ring_alloc[i];
 117                 frags[i].page_offset += priv->frag_info[i].rx_headroom;
 118                 rx_desc->data[i].addr = cpu_to_be64(frags[i].dma +
 119                                                     frags[i].page_offset);
 120                 ring_alloc[i] = page_alloc[i];
 121         }
 122
 123         return 0;
 124
 125 out:
 126         while (i--) {
 127                 if (page_alloc[i].page != ring_alloc[i].page) {
 128                         dma_unmap_page(priv->ddev, page_alloc[i].dma,
 129                                 page_alloc[i].page_size,
 130                                 priv->frag_info[i].dma_dir);
 131                         page = page_alloc[i].page;
 132                         /* Revert changes done by mlx4_alloc_pages */
 133                         page_ref_sub(page, page_alloc[i].page_size /
 134                                            priv->frag_info[i].frag_stride - 1);
 135                         put_page(page);
 136                 }
 137         }
 138         return -ENOMEM;
 139 }
 140
 141 static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
 142                               struct mlx4_en_rx_alloc *frags,
 143                               int i)
 144 {
 145         const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 146         u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride;
 147
 148
 149         if (next_frag_end > frags[i].page_size)
 150                 dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
 151                                frag_info->dma_dir);
 152
 153         if (frags[i].page)
 154                 put_page(frags[i].page);
 155 }
 156
 157 static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
 158                                   struct mlx4_en_rx_ring *ring)
 159 {
 160         int i;
 161         struct mlx4_en_rx_alloc *page_alloc;
 162
 163         for (i = 0; i < priv->num_frags; i++) {
 164                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 165
 166                 if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
 167                                      frag_info, GFP_KERNEL | __GFP_COLD))
 168                         goto out;
 169
 170                 en_dbg(DRV, priv, "  frag %d allocator: - size:%d frags:%d\n",
 171                        i, ring->page_alloc[i].page_size,
 172                        page_ref_count(ring->page_alloc[i].page));
 173         }
 174         return 0;
 175
 176 out:
 177         while (i--) {
 178                 struct page *page;
 179
 180                 page_alloc = &ring->page_alloc[i];
 181                 dma_unmap_page(priv->ddev, page_alloc->dma,
 182                                page_alloc->page_size,
 183                                priv->frag_info[i].dma_dir);
 184                 page = page_alloc->page;
 185                 /* Revert changes done by mlx4_alloc_pages */
 186                 page_ref_sub(page, page_alloc->page_size /
 187                                    priv->frag_info[i].frag_stride - 1);
 188                 put_page(page);
 189                 page_alloc->page = NULL;
 190         }
 191         return -ENOMEM;
 192 }
 193
 194 static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
 195                                       struct mlx4_en_rx_ring *ring)
 196 {
 197         struct mlx4_en_rx_alloc *page_alloc;
 198         int i;
 199
 200         for (i = 0; i < priv->num_frags; i++) {
 201                 const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
 202
 203                 page_alloc = &ring->page_alloc[i];
 204                 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
 205                        i, page_count(page_alloc->page));
 206
 207                 dma_unmap_page(priv->ddev, page_alloc->dma,
 208                                 page_alloc->page_size, frag_info->dma_dir);
 209                 while (page_alloc->page_offset + frag_info->frag_stride <
 210                        page_alloc->page_size) {
 211                         put_page(page_alloc->page);
 212                         page_alloc->page_offset += frag_info->frag_stride;
 213                 }
 214                 page_alloc->page = NULL;
 215         }
 216 }
 217
 218 static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
 219                                  struct mlx4_en_rx_ring *ring, int index)
 220 {
 221         struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
 222         int possible_frags;
 223         int i;
 224
 225         /* Set size and memtype fields */
 226         for (i = 0; i < priv->num_frags; i++) {
 227                 rx_desc->data[i].byte_count =
 228                         cpu_to_be32(priv->frag_info[i].frag_size);
 229                 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
 230         }
 231
 232         /* If the number of used fragments does not fill up the ring stride,
 233          * remaining (unused) fragments must be padded with null address/size
 234          * and a special memory key */
 235         possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
 236         for (i = priv->num_frags; i < possible_frags; i++) {
 237                 rx_desc->data[i].byte_count = 0;
 238                 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
 239                 rx_desc->data[i].addr = 0;
 240         }
 241 }
 242
 243 static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
 244                                    struct mlx4_en_rx_ring *ring, int index,
 245                                    gfp_t gfp)
 246 {
 247         struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
 248         struct mlx4_en_rx_alloc *frags = ring->rx_info +
 249                                         (index << priv->log_rx_info);
 250
 251         if (ring->page_cache.index > 0) {
 252                 frags[0] = ring->page_cache.buf[--ring->page_cache.index];
 253                 rx_desc->data[0].addr = cpu_to_be64(frags[0].dma +
 254                                                     frags[0].page_offset);
 255                 return 0;
 256         }
 257
 258         return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
 259 }
 260
 261 static inline bool mlx4_en_is_ring_empty(struct mlx4_en_rx_ring *ring)
 262 {
 263         return ring->prod == ring->cons;
 264 }
 265
 266 static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
 267 {
 268         *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
 269 }
 270
 271 static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
 272                                  struct mlx4_en_rx_ring *ring,
 273                                  int index)
 274 {
 275         struct mlx4_en_rx_alloc *frags;
 276         int nr;
 277
 278         frags = ring->rx_info + (index << priv->log_rx_info);
 279         for (nr = 0; nr < priv->num_frags; nr++) {
 280                 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
 281                 mlx4_en_free_frag(priv, frags, nr);
 282         }
 283 }
 284
 285 static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
 286 {
 287         struct mlx4_en_rx_ring *ring;
 288         int ring_ind;
 289         int buf_ind;
 290         int new_size;
 291
 292         for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
 293                 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 294                         ring = priv->rx_ring[ring_ind];
 295
 296                         if (mlx4_en_prepare_rx_desc(priv, ring,
 297                                                     ring->actual_size,
 298                                                     GFP_KERNEL | __GFP_COLD)) {
 299                                 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
 300                                         en_err(priv, "Failed to allocate enough rx buffers\n");
 301                                         return -ENOMEM;
 302                                 } else {
 303                                         new_size = rounddown_pow_of_two(ring->actual_size);
 304                                         en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n",
 305                                                 ring->actual_size, new_size);
 306                                         goto reduce_rings;
 307                                 }
 308                         }
 309                         ring->actual_size++;
 310                         ring->prod++;
 311                 }
 312         }
 313         return 0;
 314
 315 reduce_rings:
 316         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 317                 ring = priv->rx_ring[ring_ind];
 318                 while (ring->actual_size > new_size) {
 319                         ring->actual_size--;
 320                         ring->prod--;
 321                         mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
 322                 }
 323         }
 324
 325         return 0;
 326 }
 327
 328 static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
 329                                 struct mlx4_en_rx_ring *ring)
 330 {
 331         int index;
 332
 333         en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
 334                ring->cons, ring->prod);
 335
 336         /* Unmap and free Rx buffers */
 337         while (!mlx4_en_is_ring_empty(ring)) {
 338                 index = ring->cons & ring->size_mask;
 339                 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
 340                 mlx4_en_free_rx_desc(priv, ring, index);
 341                 ++ring->cons;
 342         }
 343 }
 344
 345 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev)
 346 {
 347         int i;
 348         int num_of_eqs;
 349         int num_rx_rings;
 350         struct mlx4_dev *dev = mdev->dev;
 351
 352         mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
 353                 num_of_eqs = max_t(int, MIN_RX_RINGS,
 354                                    min_t(int,
 355                                          mlx4_get_eqs_per_port(mdev->dev, i),
 356                                          DEF_RX_RINGS));
 357
 358                 num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS :
 359                         min_t(int, num_of_eqs,
 360                               netif_get_num_default_rss_queues());
 361                 mdev->profile.prof[i].rx_ring_num =
 362                         rounddown_pow_of_two(num_rx_rings);
 363         }
 364 }
 365
 366 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 367                            struct mlx4_en_rx_ring **pring,
 368                            u32 size, u16 stride, int node)
 369 {
 370         struct mlx4_en_dev *mdev = priv->mdev;
 371         struct mlx4_en_rx_ring *ring;
 372         int err = -ENOMEM;
 373         int tmp;
 374
 375         ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node);
 376         if (!ring) {
 377                 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 378                 if (!ring) {
 379                         en_err(priv, "Failed to allocate RX ring structure\n");
 380                         return -ENOMEM;
 381                 }
 382         }
 383
 384         ring->prod = 0;
 385         ring->cons = 0;
 386         ring->size = size;
 387         ring->size_mask = size - 1;
 388         ring->stride = stride;
 389         ring->log_stride = ffs(ring->stride) - 1;
 390         ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
 391
 392         tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
 393                                         sizeof(struct mlx4_en_rx_alloc));
 394         ring->rx_info = vmalloc_node(tmp, node);
 395         if (!ring->rx_info) {
 396                 ring->rx_info = vmalloc(tmp);
 397                 if (!ring->rx_info) {
 398                         err = -ENOMEM;
 399                         goto err_ring;
 400                 }
 401         }
 402
 403         en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
 404                  ring->rx_info, tmp);
 405
 406         /* Allocate HW buffers on provided NUMA node */
 407         set_dev_node(&mdev->dev->persist->pdev->dev, node);
 408         err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
 409         set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node);
 410         if (err)
 411                 goto err_info;
 412
 413         ring->buf = ring->wqres.buf.direct.buf;
 414
 415         ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
 416
 417         *pring = ring;
 418         return 0;
 419
 420 err_info:
 421         vfree(ring->rx_info);
 422         ring->rx_info = NULL;
 423 err_ring:
 424         kfree(ring);
 425         *pring = NULL;
 426
 427         return err;
 428 }
 429
 430 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
 431 {
 432         struct mlx4_en_rx_ring *ring;
 433         int i;
 434         int ring_ind;
 435         int err;
 436         int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
 437                                         DS_SIZE * priv->num_frags);
 438
 439         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 440                 ring = priv->rx_ring[ring_ind];
 441
 442                 ring->prod = 0;
 443                 ring->cons = 0;
 444                 ring->actual_size = 0;
 445                 ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn;
 446
 447                 ring->stride = stride;
 448                 if (ring->stride <= TXBB_SIZE)
 449                         ring->buf += TXBB_SIZE;
 450
 451                 ring->log_stride = ffs(ring->stride) - 1;
 452                 ring->buf_size = ring->size * ring->stride;
 453
 454                 memset(ring->buf, 0, ring->buf_size);
 455                 mlx4_en_update_rx_prod_db(ring);
 456
 457                 /* Initialize all descriptors */
 458                 for (i = 0; i < ring->size; i++)
 459                         mlx4_en_init_rx_desc(priv, ring, i);
 460
 461                 /* Initialize page allocators */
 462                 err = mlx4_en_init_allocator(priv, ring);
 463                 if (err) {
 464                         en_err(priv, "Failed initializing ring allocator\n");
 465                         if (ring->stride <= TXBB_SIZE)
 466                                 ring->buf -= TXBB_SIZE;
 467                         ring_ind--;
 468                         goto err_allocator;
 469                 }
 470         }
 471         err = mlx4_en_fill_rx_buffers(priv);
 472         if (err)
 473                 goto err_buffers;
 474
 475         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
 476                 ring = priv->rx_ring[ring_ind];
 477
 478                 ring->size_mask = ring->actual_size - 1;
 479                 mlx4_en_update_rx_prod_db(ring);
 480         }
 481
 482         return 0;
 483
 484 err_buffers:
 485         for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
 486                 mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]);
 487
 488         ring_ind = priv->rx_ring_num - 1;
 489 err_allocator:
 490         while (ring_ind >= 0) {
 491                 if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE)
 492                         priv->rx_ring[ring_ind]->buf -= TXBB_SIZE;
 493                 mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]);
 494                 ring_ind--;
 495         }
 496         return err;
 497 }
 498
 499 /* We recover from out of memory by scheduling our napi poll
 500  * function (mlx4_en_process_cq), which tries to allocate
 501  * all missing RX buffers (call to mlx4_en_refill_rx_buffers).
 502  */
 503 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv)
 504 {
 505         int ring;
 506
 507         if (!priv->port_up)
 508                 return;
 509
 510         for (ring = 0; ring < priv->rx_ring_num; ring++) {
 511                 if (mlx4_en_is_ring_empty(priv->rx_ring[ring]))
 512                         napi_reschedule(&priv->rx_cq[ring]->napi);
 513         }
 514 }
 515
 516 /* When the rx ring is running in page-per-packet mode, a released frame can go
 517  * directly into a small cache, to avoid unmapping or touching the page
 518  * allocator. In bpf prog performance scenarios, buffers are either forwarded
 519  * or dropped, never converted to skbs, so every page can come directly from
 520  * this cache when it is sized to be a multiple of the napi budget.
 521  */
 522 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
 523                         struct mlx4_en_rx_alloc *frame)
 524 {
 525         struct mlx4_en_page_cache *cache = &ring->page_cache;
 526
 527         if (cache->index >= MLX4_EN_CACHE_SIZE)
 528                 return false;
 529
 530         cache->buf[cache->index++] = *frame;
 531         return true;
 532 }
 533
 534 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 535                              struct mlx4_en_rx_ring **pring,
 536                              u32 size, u16 stride)
 537 {
 538         struct mlx4_en_dev *mdev = priv->mdev;
 539         struct mlx4_en_rx_ring *ring = *pring;
 540         struct bpf_prog *old_prog;
 541
 542         old_prog = rcu_dereference_protected(
 543                                         ring->xdp_prog,
 544                                         lockdep_is_held(&mdev->state_lock));
 545         if (old_prog)
 546                 bpf_prog_put(old_prog);
 547         mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
 548         vfree(ring->rx_info);
 549         ring->rx_info = NULL;
 550         kfree(ring);
 551         *pring = NULL;
 552 }
 553
 554 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 555                                 struct mlx4_en_rx_ring *ring)
 556 {
 557         int i;
 558
 559         for (i = 0; i < ring->page_cache.index; i++) {
 560                 struct mlx4_en_rx_alloc *frame = &ring->page_cache.buf[i];
 561
 562                 dma_unmap_page(priv->ddev, frame->dma, frame->page_size,
 563                                priv->frag_info[0].dma_dir);
 564                 put_page(frame->page);
 565         }
 566         ring->page_cache.index = 0;
 567         mlx4_en_free_rx_buf(priv, ring);
 568         if (ring->stride <= TXBB_SIZE)
 569                 ring->buf -= TXBB_SIZE;
 570         mlx4_en_destroy_allocator(priv, ring);
 571 }
 572
 573
 574 static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
 575                                     struct mlx4_en_rx_desc *rx_desc,
 576                                     struct mlx4_en_rx_alloc *frags,
 577                                     struct sk_buff *skb,
 578                                     int length)
 579 {
 580         struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
 581         struct mlx4_en_frag_info *frag_info;
 582         int nr;
 583         dma_addr_t dma;
 584
 585         /* Collect used fragments while replacing them in the HW descriptors */
 586         for (nr = 0; nr < priv->num_frags; nr++) {
 587                 frag_info = &priv->frag_info[nr];
 588                 if (length <= frag_info->frag_prefix_size)
 589                         break;
 590                 if (unlikely(!frags[nr].page))
 591                         goto fail;
 592
 593                 dma = be64_to_cpu(rx_desc->data[nr].addr);
 594                 dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
 595                                         DMA_FROM_DEVICE);
 596
 597                 /* Save page reference in skb */
 598                 __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
 599                 skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
 600                 skb_frags_rx[nr].page_offset = frags[nr].page_offset;
 601                 skb->truesize += frag_info->frag_stride;
 602                 frags[nr].page = NULL;
 603         }
 604         /* Adjust size of last fragment to match actual length */
 605         if (nr > 0)
 606                 skb_frag_size_set(&skb_frags_rx[nr - 1],
 607                         length - priv->frag_info[nr - 1].frag_prefix_size);
 608         return nr;
 609
 610 fail:
 611         while (nr > 0) {
 612                 nr--;
 613                 __skb_frag_unref(&skb_frags_rx[nr]);
 614         }
 615         return 0;
 616 }
 617
 618
 619 static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
 620                                       struct mlx4_en_rx_desc *rx_desc,
 621                                       struct mlx4_en_rx_alloc *frags,
 622                                       unsigned int length)
 623 {
 624         struct sk_buff *skb;
 625         void *va;
 626         int used_frags;
 627         dma_addr_t dma;
 628
 629         skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
 630         if (unlikely(!skb)) {
 631                 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
 632                 return NULL;
 633         }
 634         skb_reserve(skb, NET_IP_ALIGN);
 635         skb->len = length;
 636
 637         /* Get pointer to first fragment so we could copy the headers into the
 638          * (linear part of the) skb */
 639         va = page_address(frags[0].page) + frags[0].page_offset;
 640
 641         if (length <= SMALL_PACKET_SIZE) {
 642                 /* We are copying all relevant data to the skb - temporarily
 643                  * sync buffers for the copy */
 644                 dma = be64_to_cpu(rx_desc->data[0].addr);
 645                 dma_sync_single_for_cpu(priv->ddev, dma, length,
 646                                         DMA_FROM_DEVICE);
 647                 skb_copy_to_linear_data(skb, va, length);
 648                 skb->tail += length;
 649         } else {
 650                 unsigned int pull_len;
 651
 652                 /* Move relevant fragments to skb */
 653                 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
 654                                                         skb, length);
 655                 if (unlikely(!used_frags)) {
 656                         kfree_skb(skb);
 657                         return NULL;
 658                 }
 659                 skb_shinfo(skb)->nr_frags = used_frags;
 660
 661                 pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
 662                 /* Copy headers into the skb linear buffer */
 663                 memcpy(skb->data, va, pull_len);
 664                 skb->tail += pull_len;
 665
 666                 /* Skip headers in first fragment */
 667                 skb_shinfo(skb)->frags[0].page_offset += pull_len;
 668
 669                 /* Adjust size of first fragment */
 670                 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
 671                 skb->data_len = length - pull_len;
 672         }
 673         return skb;
 674 }
 675
 676 static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
 677 {
 678         int i;
 679         int offset = ETH_HLEN;
 680
 681         for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
 682                 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
 683                         goto out_loopback;
 684         }
 685         /* Loopback found */
 686         priv->loopback_ok = 1;
 687
 688 out_loopback:
 689         dev_kfree_skb_any(skb);
 690 }
 691
 692 static bool mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
 693                                       struct mlx4_en_rx_ring *ring)
 694 {
 695         u32 missing = ring->actual_size - (ring->prod - ring->cons);
 696
 697         /* Try to batch allocations, but not too much. */
 698         if (missing < 8)
 699                 return false;
 700         do {
 701                 if (mlx4_en_prepare_rx_desc(priv, ring,
 702                                             ring->prod & ring->size_mask,
 703                                             GFP_ATOMIC | __GFP_COLD))
 704                         break;
 705                 ring->prod++;
 706         } while (--missing);
 707
 708         return true;
 709 }
 710
 711 /* When hardware doesn't strip the vlan, we need to calculate the checksum
 712  * over it and add it to the hardware's checksum calculation
 713  */
 714 static inline __wsum get_fixed_vlan_csum(__wsum hw_checksum,
 715                                          struct vlan_hdr *vlanh)
 716 {
 717         return csum_add(hw_checksum, *(__wsum *)vlanh);
 718 }
 719
 720 /* Although the stack expects checksum which doesn't include the pseudo
 721  * header, the HW adds it. To address that, we are subtracting the pseudo
 722  * header checksum from the checksum value provided by the HW.
 723  */
 724 static void get_fixed_ipv4_csum(__wsum hw_checksum, struct sk_buff *skb,
 725                                 struct iphdr *iph)
 726 {
 727         __u16 length_for_csum = 0;
 728         __wsum csum_pseudo_header = 0;
 729
 730         length_for_csum = (be16_to_cpu(iph->tot_len) - (iph->ihl << 2));
 731         csum_pseudo_header = csum_tcpudp_nofold(iph->saddr, iph->daddr,
 732                                                 length_for_csum, iph->protocol, 0);
 733         skb->csum = csum_sub(hw_checksum, csum_pseudo_header);
 734 }
 735
 736 #if IS_ENABLED(CONFIG_IPV6)
 737 /* In IPv6 packets, besides subtracting the pseudo header checksum,
 738  * we also compute/add the IP header checksum which
 739  * is not added by the HW.
 740  */
 741 static int get_fixed_ipv6_csum(__wsum hw_checksum, struct sk_buff *skb,
 742                                struct ipv6hdr *ipv6h)
 743 {
 744         __wsum csum_pseudo_hdr = 0;
 745
 746         if (unlikely(ipv6h->nexthdr == IPPROTO_FRAGMENT ||
 747                      ipv6h->nexthdr == IPPROTO_HOPOPTS))
 748                 return -1;
 749         hw_checksum = csum_add(hw_checksum, (__force __wsum)htons(ipv6h->nexthdr));
 750
 751         csum_pseudo_hdr = csum_partial(&ipv6h->saddr,
 752                                        sizeof(ipv6h->saddr) + sizeof(ipv6h->daddr), 0);
 753         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ipv6h->payload_len);
 754         csum_pseudo_hdr = csum_add(csum_pseudo_hdr, (__force __wsum)ntohs(ipv6h->nexthdr));
 755
 756         skb->csum = csum_sub(hw_checksum, csum_pseudo_hdr);
 757         skb->csum = csum_add(skb->csum, csum_partial(ipv6h, sizeof(struct ipv6hdr), 0));
 758         return 0;
 759 }
 760 #endif
 761 static int check_csum(struct mlx4_cqe *cqe, struct sk_buff *skb, void *va,
 762                       netdev_features_t dev_features)
 763 {
 764         __wsum hw_checksum = 0;
 765
 766         void *hdr = (u8 *)va + sizeof(struct ethhdr);
 767
 768         hw_checksum = csum_unfold((__force __sum16)cqe->checksum);
 769
 770         if (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK) &&
 771             !(dev_features & NETIF_F_HW_VLAN_CTAG_RX)) {
 772                 hw_checksum = get_fixed_vlan_csum(hw_checksum, hdr);
 773                 hdr += sizeof(struct vlan_hdr);
 774         }
 775
 776         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4))
 777                 get_fixed_ipv4_csum(hw_checksum, skb, hdr);
 778 #if IS_ENABLED(CONFIG_IPV6)
 779         else if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV6))
 780                 if (unlikely(get_fixed_ipv6_csum(hw_checksum, skb, hdr)))
 781                         return -1;
 782 #endif
 783         return 0;
 784 }
 785
 786 int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
 787 {
 788         struct mlx4_en_priv *priv = netdev_priv(dev);
 789         struct mlx4_en_dev *mdev = priv->mdev;
 790         struct mlx4_cqe *cqe;
 791         struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring];
 792         struct mlx4_en_rx_alloc *frags;
 793         struct mlx4_en_rx_desc *rx_desc;
 794         struct bpf_prog *xdp_prog;
 795         int doorbell_pending;
 796         struct sk_buff *skb;
 797         int index;
 798         int nr;
 799         unsigned int length;
 800         int polled = 0;
 801         int ip_summed;
 802         int factor = priv->cqe_factor;
 803         u64 timestamp;
 804         bool l2_tunnel;
 805
 806         if (unlikely(!priv->port_up))
 807                 return 0;
 808
 809         if (unlikely(budget <= 0))
 810                 return polled;
 811
 812         /* Protect accesses to: ring->xdp_prog, priv->mac_hash list */
 813         rcu_read_lock();
 814         xdp_prog = rcu_dereference(ring->xdp_prog);
 815         doorbell_pending = 0;
 816
 817         /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
 818          * descriptor offset can be deduced from the CQE index instead of
 819          * reading 'cqe->index' */
 820         index = cq->mcq.cons_index & ring->size_mask;
 821         cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
 822
 823         /* Process all completed CQEs */
 824         while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
 825                     cq->mcq.cons_index & cq->size)) {
 826
 827                 frags = ring->rx_info + (index << priv->log_rx_info);
 828                 rx_desc = ring->buf + (index << ring->log_stride);
 829
 830                 /*
 831                  * make sure we read the CQE after we read the ownership bit
 832                  */
 833                 dma_rmb();
 834
 835                 /* Drop packet on bad receive or bad checksum */
 836                 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 837                                                 MLX4_CQE_OPCODE_ERROR)) {
 838                         en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n",
 839                                ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome,
 840                                ((struct mlx4_err_cqe *)cqe)->syndrome);
 841                         goto next;
 842                 }
 843                 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
 844                         en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
 845                         goto next;
 846                 }
 847
 848                 /* Check if we need to drop the packet if SRIOV is not enabled
 849                  * and not performing the selftest or flb disabled
 850                  */
 851                 if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
 852                         struct ethhdr *ethh;
 853                         dma_addr_t dma;
 854                         /* Get pointer to first fragment since we haven't
 855                          * skb yet and cast it to ethhdr struct
 856                          */
 857                         dma = be64_to_cpu(rx_desc->data[0].addr);
 858                         dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
 859                                                 DMA_FROM_DEVICE);
 860                         ethh = (struct ethhdr *)(page_address(frags[0].page) +
 861                                                  frags[0].page_offset);
 862
 863                         if (is_multicast_ether_addr(ethh->h_dest)) {
 864                                 struct mlx4_mac_entry *entry;
 865                                 struct hlist_head *bucket;
 866                                 unsigned int mac_hash;
 867
 868                                 /* Drop the packet, since HW loopback-ed it */
 869                                 mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
 870                                 bucket = &priv->mac_hash[mac_hash];
 871                                 hlist_for_each_entry_rcu(entry, bucket, hlist) {
 872                                         if (ether_addr_equal_64bits(entry->mac,
 873                                                                     ethh->h_source))
 874                                                 goto next;
 875                                 }
 876                         }
 877                 }
 878
 879                 /*
 880                  * Packet is OK - process it.
 881                  */
 882                 length = be32_to_cpu(cqe->byte_cnt);
 883                 length -= ring->fcs_del;
 884                 l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) &&
 885                         (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL));
 886
 887                 /* A bpf program gets first chance to drop the packet. It may
 888                  * read bytes but not past the end of the frag.
 889                  */
 890                 if (xdp_prog) {
 891                         struct xdp_buff xdp;
 892                         dma_addr_t dma;
 893                         void *orig_data;
 894                         u32 act;
 895
 896                         dma = be64_to_cpu(rx_desc->data[0].addr);
 897                         dma_sync_single_for_cpu(priv->ddev, dma,
 898                                                 priv->frag_info[0].frag_size,
 899                                                 DMA_FROM_DEVICE);
 900
 901                         xdp.data_hard_start = page_address(frags[0].page);
 902                         xdp.data = xdp.data_hard_start + frags[0].page_offset;
 903                         xdp.data_end = xdp.data + length;
 904                         orig_data = xdp.data;
 905
 906                         act = bpf_prog_run_xdp(xdp_prog, &xdp);
 907
 908                         if (xdp.data != orig_data) {
 909                                 length = xdp.data_end - xdp.data;
 910                                 frags[0].page_offset = xdp.data -
 911                                         xdp.data_hard_start;
 912                         }
 913
 914                         switch (act) {
 915                         case XDP_PASS:
 916                                 break;
 917                         case XDP_TX:
 918                                 if (likely(!mlx4_en_xmit_frame(ring, frags, dev,
 919                                                         length, cq->ring,
 920                                                         &doorbell_pending)))
 921                                         goto consumed;
 922                                 goto xdp_drop_no_cnt; /* Drop on xmit failure */
 923                         default:
 924                                 bpf_warn_invalid_xdp_action(act);
 925                         case XDP_ABORTED:
 926                         case XDP_DROP:
 927                                 ring->xdp_drop++;
 928 xdp_drop_no_cnt:
 929                                 if (likely(mlx4_en_rx_recycle(ring, frags)))
 930                                         goto consumed;
 931                                 goto next;
 932                         }
 933                 }
 934
 935                 ring->bytes += length;
 936                 ring->packets++;
 937
 938                 if (likely(dev->features & NETIF_F_RXCSUM)) {
 939                         if (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_TCP |
 940                                                       MLX4_CQE_STATUS_UDP)) {
 941                                 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
 942                                     cqe->checksum == cpu_to_be16(0xffff)) {
 943                                         ip_summed = CHECKSUM_UNNECESSARY;
 944                                         ring->csum_ok++;
 945                                 } else {
 946                                         ip_summed = CHECKSUM_NONE;
 947                                         ring->csum_none++;
 948                                 }
 949                         } else {
 950                                 if (priv->flags & MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP &&
 951                                     (cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
 952                                                                MLX4_CQE_STATUS_IPV6))) {
 953                                         ip_summed = CHECKSUM_COMPLETE;
 954                                         ring->csum_complete++;
 955                                 } else {
 956                                         ip_summed = CHECKSUM_NONE;
 957                                         ring->csum_none++;
 958                                 }
 959                         }
 960                 } else {
 961                         ip_summed = CHECKSUM_NONE;
 962                         ring->csum_none++;
 963                 }
 964
 965                 /* This packet is eligible for GRO if it is:
 966                  * - DIX Ethernet (type interpretation)
 967                  * - TCP/IP (v4)
 968                  * - without IP options
 969                  * - not an IP fragment
 970                  */
 971                 if (dev->features & NETIF_F_GRO) {
 972                         struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
 973                         if (!gro_skb)
 974                                 goto next;
 975
 976                         nr = mlx4_en_complete_rx_desc(priv,
 977                                 rx_desc, frags, gro_skb,
 978                                 length);
 979                         if (!nr)
 980                                 goto next;
 981
 982                         if (ip_summed == CHECKSUM_COMPLETE) {
 983                                 void *va = skb_frag_address(skb_shinfo(gro_skb)->frags);
 984                                 if (check_csum(cqe, gro_skb, va,
 985                                                dev->features)) {
 986                                         ip_summed = CHECKSUM_NONE;
 987                                         ring->csum_none++;
 988                                         ring->csum_complete--;
 989                                 }
 990                         }
 991
 992                         skb_shinfo(gro_skb)->nr_frags = nr;
 993                         gro_skb->len = length;
 994                         gro_skb->data_len = length;
 995                         gro_skb->ip_summed = ip_summed;
 996
 997                         if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
 998                                 gro_skb->csum_level = 1;
 999
1000                         if ((cqe->vlan_my_qpn &
1001                             cpu_to_be32(MLX4_CQE_CVLAN_PRESENT_MASK)) &&
1002                             (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1003                                 u16 vid = be16_to_cpu(cqe->sl_vid);
1004
1005                                 __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
1006                         } else if ((be32_to_cpu(cqe->vlan_my_qpn) &
1007                                   MLX4_CQE_SVLAN_PRESENT_MASK) &&
1008                                  (dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
1009                                 __vlan_hwaccel_put_tag(gro_skb,
1010                                                        htons(ETH_P_8021AD),
1011                                                        be16_to_cpu(cqe->sl_vid));
1012                         }
1013
1014                         if (dev->features & NETIF_F_RXHASH)
1015                                 skb_set_hash(gro_skb,
1016                                              be32_to_cpu(cqe->immed_rss_invalid),
1017                                              (ip_summed == CHECKSUM_UNNECESSARY) ?
1018                                                 PKT_HASH_TYPE_L4 :
1019                                                 PKT_HASH_TYPE_L3);
1020
1021                         skb_record_rx_queue(gro_skb, cq->ring);
1022
1023                         if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
1024                                 timestamp = mlx4_en_get_cqe_ts(cqe);
1025                                 mlx4_en_fill_hwtstamps(mdev,
1026                                                        skb_hwtstamps(gro_skb),
1027                                                        timestamp);
1028                         }
1029
1030                         napi_gro_frags(&cq->napi);
1031                         goto next;
1032                 }
1033
1034                 /* GRO not possible, complete processing here */
1035                 skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
1036                 if (unlikely(!skb)) {
1037                         ring->dropped++;
1038                         goto next;
1039                 }
1040
1041                 if (unlikely(priv->validate_loopback)) {
1042                         validate_loopback(priv, skb);
1043                         goto next;
1044                 }
1045
1046                 if (ip_summed == CHECKSUM_COMPLETE) {
1047                         if (check_csum(cqe, skb, skb->data, dev->features)) {
1048                                 ip_summed = CHECKSUM_NONE;
1049                                 ring->csum_complete--;
1050                                 ring->csum_none++;
1051                         }
1052                 }
1053
1054                 skb->ip_summed = ip_summed;
1055                 skb->protocol = eth_type_trans(skb, dev);
1056                 skb_record_rx_queue(skb, cq->ring);
1057
1058                 if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
1059                         skb->csum_level = 1;
1060
1061                 if (dev->features & NETIF_F_RXHASH)
1062                         skb_set_hash(skb,
1063                                      be32_to_cpu(cqe->immed_rss_invalid),
1064                                      (ip_summed == CHECKSUM_UNNECESSARY) ?
1065                                         PKT_HASH_TYPE_L4 :
1066                                         PKT_HASH_TYPE_L3);
1067
1068                 if ((be32_to_cpu(cqe->vlan_my_qpn) &
1069                     MLX4_CQE_CVLAN_PRESENT_MASK) &&
1070                     (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
1071                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
1072                 else if ((be32_to_cpu(cqe->vlan_my_qpn) &
1073                           MLX4_CQE_SVLAN_PRESENT_MASK) &&
1074                          (dev->features & NETIF_F_HW_VLAN_STAG_RX))
1075                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
1076                                                be16_to_cpu(cqe->sl_vid));
1077
1078                 if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
1079                         timestamp = mlx4_en_get_cqe_ts(cqe);
1080                         mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
1081                                                timestamp);
1082                 }
1083
1084                 napi_gro_receive(&cq->napi, skb);
1085 next:
1086                 for (nr = 0; nr < priv->num_frags; nr++)
1087                         mlx4_en_free_frag(priv, frags, nr);
1088
1089 consumed:
1090                 ++cq->mcq.cons_index;
1091                 index = (cq->mcq.cons_index) & ring->size_mask;
1092                 cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor;
1093                 if (++polled == budget)
1094                         goto out;
1095         }
1096
1097 out:
1098         rcu_read_unlock();
1099
1100         if (polled) {
1101                 if (doorbell_pending)
1102                         mlx4_en_xmit_doorbell(priv->tx_ring[TX_XDP][cq->ring]);
1103
1104                 mlx4_cq_set_ci(&cq->mcq);
1105                 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
1106                 ring->cons = cq->mcq.cons_index;
1107         }
1108         AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
1109
1110         if (mlx4_en_refill_rx_buffers(priv, ring))
1111                 mlx4_en_update_rx_prod_db(ring);
1112
1113         return polled;
1114 }
1115
1116
1117 void mlx4_en_rx_irq(struct mlx4_cq *mcq)
1118 {
1119         struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
1120         struct mlx4_en_priv *priv = netdev_priv(cq->dev);
1121
1122         if (likely(priv->port_up))
1123                 napi_schedule_irqoff(&cq->napi);
1124         else
1125                 mlx4_en_arm_cq(priv, cq);
1126 }
1127
1128 /* Rx CQ polling - called by NAPI */
1129 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
1130 {
1131         struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
1132         struct net_device *dev = cq->dev;
1133         struct mlx4_en_priv *priv = netdev_priv(dev);
1134         int done;
1135
1136         done = mlx4_en_process_rx_cq(dev, cq, budget);
1137
1138         /* If we used up all the quota - we're probably not done yet... */
1139         if (done == budget) {
1140                 const struct cpumask *aff;
1141                 struct irq_data *idata;
1142                 int cpu_curr;
1143
1144                 INC_PERF_COUNTER(priv->pstats.napi_quota);
1145
1146                 cpu_curr = smp_processor_id();
1147                 idata = irq_desc_get_irq_data(cq->irq_desc);
1148                 aff = irq_data_get_affinity_mask(idata);
1149
1150                 if (likely(cpumask_test_cpu(cpu_curr, aff)))
1151                         return budget;
1152
1153                 /* Current cpu is not according to smp_irq_affinity -
1154                  * probably affinity changed. Need to stop this NAPI
1155                  * poll, and restart it on the right CPU.
1156                  * Try to avoid returning a too small value (like 0),
1157                  * to not fool net_rx_action() and its netdev_budget
1158                  */
1159                 if (done)
1160                         done--;
1161         }
1162         /* Done for now */
1163         if (napi_complete_done(napi, done))
1164                 mlx4_en_arm_cq(priv, cq);
1165         return done;
1166 }
1167
1168 static const int frag_sizes[] = {
1169         FRAG_SZ0,
1170         FRAG_SZ1,
1171         FRAG_SZ2,
1172         FRAG_SZ3
1173 };
1174
1175 void mlx4_en_calc_rx_buf(struct net_device *dev)
1176 {
1177         struct mlx4_en_priv *priv = netdev_priv(dev);
1178         int eff_mtu = MLX4_EN_EFF_MTU(dev->mtu);
1179         int i = 0;
1180
1181         /* bpf requires buffers to be set up as 1 packet per page.
1182          * This only works when num_frags == 1.
1183          */
1184         if (priv->tx_ring_num[TX_XDP]) {
1185                 priv->frag_info[0].order = 0;
1186                 priv->frag_info[0].frag_size = eff_mtu;
1187                 priv->frag_info[0].frag_prefix_size = 0;
1188                 /* This will gain efficient xdp frame recycling at the
1189                  * expense of more costly truesize accounting
1190                  */
1191                 priv->frag_info[0].frag_stride = PAGE_SIZE;
1192                 priv->frag_info[0].dma_dir = PCI_DMA_BIDIRECTIONAL;
1193                 priv->frag_info[0].rx_headroom = XDP_PACKET_HEADROOM;
1194                 i = 1;
1195         } else {
1196                 int buf_size = 0;
1197
1198                 while (buf_size < eff_mtu) {
1199                         priv->frag_info[i].order = MLX4_EN_ALLOC_PREFER_ORDER;
1200                         priv->frag_info[i].frag_size =
1201                                 (eff_mtu > buf_size + frag_sizes[i]) ?
1202                                         frag_sizes[i] : eff_mtu - buf_size;
1203                         priv->frag_info[i].frag_prefix_size = buf_size;
1204                         priv->frag_info[i].frag_stride =
1205                                 ALIGN(priv->frag_info[i].frag_size,
1206                                       SMP_CACHE_BYTES);
1207                         priv->frag_info[i].dma_dir = PCI_DMA_FROMDEVICE;
1208                         priv->frag_info[i].rx_headroom = 0;
1209                         buf_size += priv->frag_info[i].frag_size;
1210                         i++;
1211                 }
1212         }
1213
1214         priv->num_frags = i;
1215         priv->rx_skb_size = eff_mtu;
1216         priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
1217
1218         en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n",
1219                eff_mtu, priv->num_frags);
1220         for (i = 0; i < priv->num_frags; i++) {
1221                 en_err(priv,
1222                        "  frag:%d - size:%d prefix:%d stride:%d\n",
1223                        i,
1224                        priv->frag_info[i].frag_size,
1225                        priv->frag_info[i].frag_prefix_size,
1226                        priv->frag_info[i].frag_stride);
1227         }
1228 }
1229
1230 /* RSS related functions */
1231
1232 static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
1233                                  struct mlx4_en_rx_ring *ring,
1234                                  enum mlx4_qp_state *state,
1235                                  struct mlx4_qp *qp)
1236 {
1237         struct mlx4_en_dev *mdev = priv->mdev;
1238         struct mlx4_qp_context *context;
1239         int err = 0;
1240
1241         context = kmalloc(sizeof(*context), GFP_KERNEL);
1242         if (!context)
1243                 return -ENOMEM;
1244
1245         err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL);
1246         if (err) {
1247                 en_err(priv, "Failed to allocate qp #%x\n", qpn);
1248                 goto out;
1249         }
1250         qp->event = mlx4_en_sqp_event;
1251
1252         memset(context, 0, sizeof *context);
1253         mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
1254                                 qpn, ring->cqn, -1, context);
1255         context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
1256
1257         /* Cancel FCS removal if FW allows */
1258         if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
1259                 context->param3 |= cpu_to_be32(1 << 29);
1260                 if (priv->dev->features & NETIF_F_RXFCS)
1261                         ring->fcs_del = 0;
1262                 else
1263                         ring->fcs_del = ETH_FCS_LEN;
1264         } else
1265                 ring->fcs_del = 0;
1266
1267         err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
1268         if (err) {
1269                 mlx4_qp_remove(mdev->dev, qp);
1270                 mlx4_qp_free(mdev->dev, qp);
1271         }
1272         mlx4_en_update_rx_prod_db(ring);
1273 out:
1274         kfree(context);
1275         return err;
1276 }
1277
1278 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
1279 {
1280         int err;
1281         u32 qpn;
1282
1283         err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn,
1284                                     MLX4_RESERVE_A0_QP);
1285         if (err) {
1286                 en_err(priv, "Failed reserving drop qpn\n");
1287                 return err;
1288         }
1289         err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL);
1290         if (err) {
1291                 en_err(priv, "Failed allocating drop qp\n");
1292                 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1293                 return err;
1294         }
1295
1296         return 0;
1297 }
1298
1299 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
1300 {
1301         u32 qpn;
1302
1303         qpn = priv->drop_qp.qpn;
1304         mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
1305         mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
1306         mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
1307 }
1308
1309 /* Allocate rx qp's and configure them according to rss map */
1310 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
1311 {
1312         struct mlx4_en_dev *mdev = priv->mdev;
1313         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1314         struct mlx4_qp_context context;
1315         struct mlx4_rss_context *rss_context;
1316         int rss_rings;
1317         void *ptr;
1318         u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1319                         MLX4_RSS_TCP_IPV6);
1320         int i, qpn;
1321         int err = 0;
1322         int good_qps = 0;
1323
1324         en_dbg(DRV, priv, "Configuring rss steering\n");
1325         err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
1326                                     priv->rx_ring_num,
1327                                     &rss_map->base_qpn, 0);
1328         if (err) {
1329                 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
1330                 return err;
1331         }
1332
1333         for (i = 0; i < priv->rx_ring_num; i++) {
1334                 qpn = rss_map->base_qpn + i;
1335                 err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i],
1336                                             &rss_map->state[i],
1337                                             &rss_map->qps[i]);
1338                 if (err)
1339                         goto rss_err;
1340
1341                 ++good_qps;
1342         }
1343
1344         /* Configure RSS indirection qp */
1345         err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL);
1346         if (err) {
1347                 en_err(priv, "Failed to allocate RSS indirection QP\n");
1348                 goto rss_err;
1349         }
1350         rss_map->indir_qp.event = mlx4_en_sqp_event;
1351         mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
1352                                 priv->rx_ring[0]->cqn, -1, &context);
1353
1354         if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
1355                 rss_rings = priv->rx_ring_num;
1356         else
1357                 rss_rings = priv->prof->rss_rings;
1358
1359         ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
1360                                         + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
1361         rss_context = ptr;
1362         rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
1363                                             (rss_map->base_qpn));
1364         rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1365         if (priv->mdev->profile.udp_rss) {
1366                 rss_mask |=  MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
1367                 rss_context->base_qpn_udp = rss_context->default_qpn;
1368         }
1369
1370         if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1371                 en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n");
1372                 rss_mask |= MLX4_RSS_BY_INNER_HEADERS;
1373         }
1374
1375         rss_context->flags = rss_mask;
1376         rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1377         if (priv->rss_hash_fn == ETH_RSS_HASH_XOR) {
1378                 rss_context->hash_fn = MLX4_RSS_HASH_XOR;
1379         } else if (priv->rss_hash_fn == ETH_RSS_HASH_TOP) {
1380                 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
1381                 memcpy(rss_context->rss_key, priv->rss_key,
1382                        MLX4_EN_RSS_KEY_SIZE);
1383         } else {
1384                 en_err(priv, "Unknown RSS hash function requested\n");
1385                 err = -EINVAL;
1386                 goto indir_err;
1387         }
1388         err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
1389                                &rss_map->indir_qp, &rss_map->indir_state);
1390         if (err)
1391                 goto indir_err;
1392
1393         return 0;
1394
1395 indir_err:
1396         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1397                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1398         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1399         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1400 rss_err:
1401         for (i = 0; i < good_qps; i++) {
1402                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1403                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1404                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1405                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1406         }
1407         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1408         return err;
1409 }
1410
1411 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
1412 {
1413         struct mlx4_en_dev *mdev = priv->mdev;
1414         struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1415         int i;
1416
1417         mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
1418                        MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
1419         mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
1420         mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
1421
1422         for (i = 0; i < priv->rx_ring_num; i++) {
1423                 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
1424                                MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
1425                 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
1426                 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
1427         }
1428         mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
1429 }