2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/string.h>
35 #include <linux/etherdevice.h>
37 #include <linux/mlx4/cmd.h>
38 #include <linux/export.h>
42 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev)
44 return 1 << dev->oper_log_mgm_entry_size;
47 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev)
49 return 4 * (mlx4_get_mgm_entry_size(dev) / 16 - 2);
52 static int mlx4_QP_FLOW_STEERING_ATTACH(struct mlx4_dev *dev,
53 struct mlx4_cmd_mailbox *mailbox,
60 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, size, 0,
61 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
70 static int mlx4_QP_FLOW_STEERING_DETACH(struct mlx4_dev *dev, u64 regid)
74 err = mlx4_cmd(dev, regid, 0, 0,
75 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
81 static int mlx4_READ_ENTRY(struct mlx4_dev *dev, int index,
82 struct mlx4_cmd_mailbox *mailbox)
84 return mlx4_cmd_box(dev, 0, mailbox->dma, index, 0, MLX4_CMD_READ_MCG,
85 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
88 static int mlx4_WRITE_ENTRY(struct mlx4_dev *dev, int index,
89 struct mlx4_cmd_mailbox *mailbox)
91 return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG,
92 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
95 static int mlx4_WRITE_PROMISC(struct mlx4_dev *dev, u8 port, u8 steer,
96 struct mlx4_cmd_mailbox *mailbox)
100 in_mod = (u32) port << 16 | steer << 1;
101 return mlx4_cmd(dev, mailbox->dma, in_mod, 0x1,
102 MLX4_CMD_WRITE_MCG, MLX4_CMD_TIME_CLASS_A,
106 static int mlx4_GID_HASH(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
107 u16 *hash, u8 op_mod)
112 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, 0, op_mod,
113 MLX4_CMD_MGID_HASH, MLX4_CMD_TIME_CLASS_A,
122 static struct mlx4_promisc_qp *get_promisc_qp(struct mlx4_dev *dev, u8 port,
123 enum mlx4_steer_type steer,
126 struct mlx4_steer *s_steer;
127 struct mlx4_promisc_qp *pqp;
129 if (port < 1 || port > dev->caps.num_ports)
132 s_steer = &mlx4_priv(dev)->steer[port - 1];
134 list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) {
143 * Add new entry to steering data structure.
144 * All promisc QPs should be added as well
146 static int new_steering_entry(struct mlx4_dev *dev, u8 port,
147 enum mlx4_steer_type steer,
148 unsigned int index, u32 qpn)
150 struct mlx4_steer *s_steer;
151 struct mlx4_cmd_mailbox *mailbox;
152 struct mlx4_mgm *mgm;
154 struct mlx4_steer_index *new_entry;
155 struct mlx4_promisc_qp *pqp;
156 struct mlx4_promisc_qp *dqp = NULL;
160 if (port < 1 || port > dev->caps.num_ports)
163 s_steer = &mlx4_priv(dev)->steer[port - 1];
164 new_entry = kzalloc(sizeof *new_entry, GFP_KERNEL);
168 INIT_LIST_HEAD(&new_entry->duplicates);
169 new_entry->index = index;
170 list_add_tail(&new_entry->list, &s_steer->steer_entries[steer]);
172 /* If the given qpn is also a promisc qp,
173 * it should be inserted to duplicates list
175 pqp = get_promisc_qp(dev, port, steer, qpn);
177 dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
183 list_add_tail(&dqp->list, &new_entry->duplicates);
186 /* if no promisc qps for this vep, we are done */
187 if (list_empty(&s_steer->promisc_qps[steer]))
190 /* now need to add all the promisc qps to the new
191 * steering entry, as they should also receive the packets
192 * destined to this address */
193 mailbox = mlx4_alloc_cmd_mailbox(dev);
194 if (IS_ERR(mailbox)) {
200 err = mlx4_READ_ENTRY(dev, index, mailbox);
204 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
205 prot = be32_to_cpu(mgm->members_count) >> 30;
206 list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) {
207 /* don't add already existing qpn */
210 if (members_count == dev->caps.num_qp_per_mgm) {
217 mgm->qp[members_count++] = cpu_to_be32(pqp->qpn & MGM_QPN_MASK);
219 /* update the qps count and update the entry with all the promisc qps*/
220 mgm->members_count = cpu_to_be32(members_count | (prot << 30));
221 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
224 mlx4_free_cmd_mailbox(dev, mailbox);
229 list_del(&dqp->list);
232 list_del(&new_entry->list);
237 /* update the data structures with existing steering entry */
238 static int existing_steering_entry(struct mlx4_dev *dev, u8 port,
239 enum mlx4_steer_type steer,
240 unsigned int index, u32 qpn)
242 struct mlx4_steer *s_steer;
243 struct mlx4_steer_index *tmp_entry, *entry = NULL;
244 struct mlx4_promisc_qp *pqp;
245 struct mlx4_promisc_qp *dqp;
247 if (port < 1 || port > dev->caps.num_ports)
250 s_steer = &mlx4_priv(dev)->steer[port - 1];
252 pqp = get_promisc_qp(dev, port, steer, qpn);
254 return 0; /* nothing to do */
256 list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) {
257 if (tmp_entry->index == index) {
262 if (unlikely(!entry)) {
263 mlx4_warn(dev, "Steering entry at index %x is not registered\n", index);
267 /* the given qpn is listed as a promisc qpn
268 * we need to add it as a duplicate to this entry
269 * for future references */
270 list_for_each_entry(dqp, &entry->duplicates, list) {
272 return 0; /* qp is already duplicated */
275 /* add the qp as a duplicate on this index */
276 dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
280 list_add_tail(&dqp->list, &entry->duplicates);
285 /* Check whether a qpn is a duplicate on steering entry
286 * If so, it should not be removed from mgm */
287 static bool check_duplicate_entry(struct mlx4_dev *dev, u8 port,
288 enum mlx4_steer_type steer,
289 unsigned int index, u32 qpn)
291 struct mlx4_steer *s_steer;
292 struct mlx4_steer_index *tmp_entry, *entry = NULL;
293 struct mlx4_promisc_qp *dqp, *tmp_dqp;
295 if (port < 1 || port > dev->caps.num_ports)
298 s_steer = &mlx4_priv(dev)->steer[port - 1];
300 /* if qp is not promisc, it cannot be duplicated */
301 if (!get_promisc_qp(dev, port, steer, qpn))
304 /* The qp is promisc qp so it is a duplicate on this index
305 * Find the index entry, and remove the duplicate */
306 list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) {
307 if (tmp_entry->index == index) {
312 if (unlikely(!entry)) {
313 mlx4_warn(dev, "Steering entry for index %x is not registered\n", index);
316 list_for_each_entry_safe(dqp, tmp_dqp, &entry->duplicates, list) {
317 if (dqp->qpn == qpn) {
318 list_del(&dqp->list);
325 /* Returns true if all the QPs != tqpn contained in this entry
326 * are Promisc QPs. Returns false otherwise.
328 static bool promisc_steering_entry(struct mlx4_dev *dev, u8 port,
329 enum mlx4_steer_type steer,
330 unsigned int index, u32 tqpn,
333 struct mlx4_cmd_mailbox *mailbox;
334 struct mlx4_mgm *mgm;
339 if (port < 1 || port > dev->caps.num_ports)
342 mailbox = mlx4_alloc_cmd_mailbox(dev);
347 if (mlx4_READ_ENTRY(dev, index, mailbox))
349 m_count = be32_to_cpu(mgm->members_count) & 0xffffff;
351 *members_count = m_count;
353 for (i = 0; i < m_count; i++) {
354 u32 qpn = be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK;
355 if (!get_promisc_qp(dev, port, steer, qpn) && qpn != tqpn) {
356 /* the qp is not promisc, the entry can't be removed */
362 mlx4_free_cmd_mailbox(dev, mailbox);
366 /* IF a steering entry contains only promisc QPs, it can be removed. */
367 static bool can_remove_steering_entry(struct mlx4_dev *dev, u8 port,
368 enum mlx4_steer_type steer,
369 unsigned int index, u32 tqpn)
371 struct mlx4_steer *s_steer;
372 struct mlx4_steer_index *entry = NULL, *tmp_entry;
376 if (port < 1 || port > dev->caps.num_ports)
379 s_steer = &mlx4_priv(dev)->steer[port - 1];
381 if (!promisc_steering_entry(dev, port, steer, index,
382 tqpn, &members_count))
385 /* All the qps currently registered for this entry are promiscuous,
386 * Checking for duplicates */
388 list_for_each_entry_safe(entry, tmp_entry, &s_steer->steer_entries[steer], list) {
389 if (entry->index == index) {
390 if (list_empty(&entry->duplicates) ||
391 members_count == 1) {
392 struct mlx4_promisc_qp *pqp, *tmp_pqp;
393 /* If there is only 1 entry in duplicates then
394 * this is the QP we want to delete, going over
395 * the list and deleting the entry.
397 list_del(&entry->list);
398 list_for_each_entry_safe(pqp, tmp_pqp,
401 list_del(&pqp->list);
406 /* This entry contains duplicates so it shouldn't be removed */
417 static int add_promisc_qp(struct mlx4_dev *dev, u8 port,
418 enum mlx4_steer_type steer, u32 qpn)
420 struct mlx4_steer *s_steer;
421 struct mlx4_cmd_mailbox *mailbox;
422 struct mlx4_mgm *mgm;
423 struct mlx4_steer_index *entry;
424 struct mlx4_promisc_qp *pqp;
425 struct mlx4_promisc_qp *dqp;
431 struct mlx4_priv *priv = mlx4_priv(dev);
433 if (port < 1 || port > dev->caps.num_ports)
436 s_steer = &mlx4_priv(dev)->steer[port - 1];
438 mutex_lock(&priv->mcg_table.mutex);
440 if (get_promisc_qp(dev, port, steer, qpn)) {
441 err = 0; /* Noting to do, already exists */
445 pqp = kmalloc(sizeof *pqp, GFP_KERNEL);
452 mailbox = mlx4_alloc_cmd_mailbox(dev);
453 if (IS_ERR(mailbox)) {
459 if (!(mlx4_is_mfunc(dev) && steer == MLX4_UC_STEER)) {
460 /* The promisc QP needs to be added for each one of the steering
461 * entries. If it already exists, needs to be added as
462 * a duplicate for this entry.
464 list_for_each_entry(entry,
465 &s_steer->steer_entries[steer],
467 err = mlx4_READ_ENTRY(dev, entry->index, mailbox);
471 members_count = be32_to_cpu(mgm->members_count) &
473 prot = be32_to_cpu(mgm->members_count) >> 30;
475 for (i = 0; i < members_count; i++) {
476 if ((be32_to_cpu(mgm->qp[i]) &
477 MGM_QPN_MASK) == qpn) {
478 /* Entry already exists.
481 dqp = kmalloc(sizeof(*dqp), GFP_KERNEL);
487 list_add_tail(&dqp->list,
493 /* Need to add the qpn to mgm */
495 dev->caps.num_qp_per_mgm) {
500 mgm->qp[members_count++] =
501 cpu_to_be32(qpn & MGM_QPN_MASK);
503 cpu_to_be32(members_count |
505 err = mlx4_WRITE_ENTRY(dev, entry->index,
513 /* add the new qpn to list of promisc qps */
514 list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]);
515 /* now need to add all the promisc qps to default entry */
516 memset(mgm, 0, sizeof *mgm);
518 list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list) {
519 if (members_count == dev->caps.num_qp_per_mgm) {
524 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK);
526 mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30);
528 err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox);
532 mlx4_free_cmd_mailbox(dev, mailbox);
533 mutex_unlock(&priv->mcg_table.mutex);
537 list_del(&pqp->list);
539 mlx4_free_cmd_mailbox(dev, mailbox);
543 mutex_unlock(&priv->mcg_table.mutex);
547 static int remove_promisc_qp(struct mlx4_dev *dev, u8 port,
548 enum mlx4_steer_type steer, u32 qpn)
550 struct mlx4_priv *priv = mlx4_priv(dev);
551 struct mlx4_steer *s_steer;
552 struct mlx4_cmd_mailbox *mailbox;
553 struct mlx4_mgm *mgm;
554 struct mlx4_steer_index *entry, *tmp_entry;
555 struct mlx4_promisc_qp *pqp;
556 struct mlx4_promisc_qp *dqp;
559 bool back_to_list = false;
563 if (port < 1 || port > dev->caps.num_ports)
566 s_steer = &mlx4_priv(dev)->steer[port - 1];
567 mutex_lock(&priv->mcg_table.mutex);
569 pqp = get_promisc_qp(dev, port, steer, qpn);
570 if (unlikely(!pqp)) {
571 mlx4_warn(dev, "QP %x is not promiscuous QP\n", qpn);
577 /*remove from list of promisc qps */
578 list_del(&pqp->list);
580 /* set the default entry not to include the removed one */
581 mailbox = mlx4_alloc_cmd_mailbox(dev);
582 if (IS_ERR(mailbox)) {
589 list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list)
590 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK);
591 mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30);
593 err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox);
597 if (!(mlx4_is_mfunc(dev) && steer == MLX4_UC_STEER)) {
598 /* Remove the QP from all the steering entries */
599 list_for_each_entry_safe(entry, tmp_entry,
600 &s_steer->steer_entries[steer],
603 list_for_each_entry(dqp, &entry->duplicates, list) {
604 if (dqp->qpn == qpn) {
610 /* A duplicate, no need to change the MGM,
611 * only update the duplicates list
613 list_del(&dqp->list);
618 err = mlx4_READ_ENTRY(dev,
624 be32_to_cpu(mgm->members_count) &
626 if (!members_count) {
627 mlx4_warn(dev, "QP %06x wasn't found in entry %x mcount=0. deleting entry...\n",
629 list_del(&entry->list);
634 for (i = 0; i < members_count; ++i)
635 if ((be32_to_cpu(mgm->qp[i]) &
636 MGM_QPN_MASK) == qpn) {
642 mlx4_err(dev, "QP %06x wasn't found in entry %d\n",
648 /* Copy the last QP in this MGM
651 mgm->qp[loc] = mgm->qp[members_count - 1];
652 mgm->qp[members_count - 1] = 0;
654 cpu_to_be32(--members_count |
655 (MLX4_PROT_ETH << 30));
657 err = mlx4_WRITE_ENTRY(dev,
667 mlx4_free_cmd_mailbox(dev, mailbox);
670 list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]);
674 mutex_unlock(&priv->mcg_table.mutex);
679 * Caller must hold MCG table semaphore. gid and mgm parameters must
680 * be properly aligned for command interface.
682 * Returns 0 unless a firmware command error occurs.
684 * If GID is found in MGM or MGM is empty, *index = *hash, *prev = -1
685 * and *mgm holds MGM entry.
687 * if GID is found in AMGM, *index = index in AMGM, *prev = index of
688 * previous entry in hash chain and *mgm holds AMGM entry.
690 * If no AMGM exists for given gid, *index = -1, *prev = index of last
691 * entry in hash chain and *mgm holds end of hash chain.
693 static int find_entry(struct mlx4_dev *dev, u8 port,
694 u8 *gid, enum mlx4_protocol prot,
695 struct mlx4_cmd_mailbox *mgm_mailbox,
696 int *prev, int *index)
698 struct mlx4_cmd_mailbox *mailbox;
699 struct mlx4_mgm *mgm = mgm_mailbox->buf;
703 u8 op_mod = (prot == MLX4_PROT_ETH) ?
704 !!(dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) : 0;
706 mailbox = mlx4_alloc_cmd_mailbox(dev);
711 memcpy(mgid, gid, 16);
713 err = mlx4_GID_HASH(dev, mailbox, &hash, op_mod);
714 mlx4_free_cmd_mailbox(dev, mailbox);
719 mlx4_dbg(dev, "Hash for %pI6 is %04x\n", gid, hash);
725 err = mlx4_READ_ENTRY(dev, *index, mgm_mailbox);
729 if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) {
730 if (*index != hash) {
731 mlx4_err(dev, "Found zero MGID in AMGM\n");
737 if (!memcmp(mgm->gid, gid, 16) &&
738 be32_to_cpu(mgm->members_count) >> 30 == prot)
742 *index = be32_to_cpu(mgm->next_gid_index) >> 6;
749 static const u8 __promisc_mode[] = {
750 [MLX4_FS_REGULAR] = 0x0,
751 [MLX4_FS_ALL_DEFAULT] = 0x1,
752 [MLX4_FS_MC_DEFAULT] = 0x3,
753 [MLX4_FS_MIRROR_RX_PORT] = 0x4,
754 [MLX4_FS_MIRROR_SX_PORT] = 0x5,
755 [MLX4_FS_UC_SNIFFER] = 0x6,
756 [MLX4_FS_MC_SNIFFER] = 0x7,
759 int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev,
760 enum mlx4_net_trans_promisc_mode flow_type)
762 if (flow_type >= MLX4_FS_MODE_NUM) {
763 mlx4_err(dev, "Invalid flow type. type = %d\n", flow_type);
766 return __promisc_mode[flow_type];
768 EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_mode);
770 static void trans_rule_ctrl_to_hw(struct mlx4_net_trans_rule *ctrl,
771 struct mlx4_net_trans_rule_hw_ctrl *hw)
775 flags = ctrl->queue_mode == MLX4_NET_TRANS_Q_LIFO ? 1 : 0;
776 flags |= ctrl->exclusive ? (1 << 2) : 0;
777 flags |= ctrl->allow_loopback ? (1 << 3) : 0;
780 hw->type = __promisc_mode[ctrl->promisc_mode];
781 hw->prio = cpu_to_be16(ctrl->priority);
782 hw->port = ctrl->port;
783 hw->qpn = cpu_to_be32(ctrl->qpn);
786 const u16 __sw_id_hw[] = {
787 [MLX4_NET_TRANS_RULE_ID_ETH] = 0xE001,
788 [MLX4_NET_TRANS_RULE_ID_IB] = 0xE005,
789 [MLX4_NET_TRANS_RULE_ID_IPV6] = 0xE003,
790 [MLX4_NET_TRANS_RULE_ID_IPV4] = 0xE002,
791 [MLX4_NET_TRANS_RULE_ID_TCP] = 0xE004,
792 [MLX4_NET_TRANS_RULE_ID_UDP] = 0xE006,
793 [MLX4_NET_TRANS_RULE_ID_VXLAN] = 0xE008
796 int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev,
797 enum mlx4_net_trans_rule_id id)
799 if (id >= MLX4_NET_TRANS_RULE_NUM) {
800 mlx4_err(dev, "Invalid network rule id. id = %d\n", id);
803 return __sw_id_hw[id];
805 EXPORT_SYMBOL_GPL(mlx4_map_sw_to_hw_steering_id);
807 static const int __rule_hw_sz[] = {
808 [MLX4_NET_TRANS_RULE_ID_ETH] =
809 sizeof(struct mlx4_net_trans_rule_hw_eth),
810 [MLX4_NET_TRANS_RULE_ID_IB] =
811 sizeof(struct mlx4_net_trans_rule_hw_ib),
812 [MLX4_NET_TRANS_RULE_ID_IPV6] = 0,
813 [MLX4_NET_TRANS_RULE_ID_IPV4] =
814 sizeof(struct mlx4_net_trans_rule_hw_ipv4),
815 [MLX4_NET_TRANS_RULE_ID_TCP] =
816 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp),
817 [MLX4_NET_TRANS_RULE_ID_UDP] =
818 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp),
819 [MLX4_NET_TRANS_RULE_ID_VXLAN] =
820 sizeof(struct mlx4_net_trans_rule_hw_vxlan)
823 int mlx4_hw_rule_sz(struct mlx4_dev *dev,
824 enum mlx4_net_trans_rule_id id)
826 if (id >= MLX4_NET_TRANS_RULE_NUM) {
827 mlx4_err(dev, "Invalid network rule id. id = %d\n", id);
831 return __rule_hw_sz[id];
833 EXPORT_SYMBOL_GPL(mlx4_hw_rule_sz);
835 static int parse_trans_rule(struct mlx4_dev *dev, struct mlx4_spec_list *spec,
836 struct _rule_hw *rule_hw)
838 if (mlx4_hw_rule_sz(dev, spec->id) < 0)
840 memset(rule_hw, 0, mlx4_hw_rule_sz(dev, spec->id));
841 rule_hw->id = cpu_to_be16(__sw_id_hw[spec->id]);
842 rule_hw->size = mlx4_hw_rule_sz(dev, spec->id) >> 2;
845 case MLX4_NET_TRANS_RULE_ID_ETH:
846 memcpy(rule_hw->eth.dst_mac, spec->eth.dst_mac, ETH_ALEN);
847 memcpy(rule_hw->eth.dst_mac_msk, spec->eth.dst_mac_msk,
849 memcpy(rule_hw->eth.src_mac, spec->eth.src_mac, ETH_ALEN);
850 memcpy(rule_hw->eth.src_mac_msk, spec->eth.src_mac_msk,
852 if (spec->eth.ether_type_enable) {
853 rule_hw->eth.ether_type_enable = 1;
854 rule_hw->eth.ether_type = spec->eth.ether_type;
856 rule_hw->eth.vlan_tag = spec->eth.vlan_id;
857 rule_hw->eth.vlan_tag_msk = spec->eth.vlan_id_msk;
860 case MLX4_NET_TRANS_RULE_ID_IB:
861 rule_hw->ib.l3_qpn = spec->ib.l3_qpn;
862 rule_hw->ib.qpn_mask = spec->ib.qpn_msk;
863 memcpy(&rule_hw->ib.dst_gid, &spec->ib.dst_gid, 16);
864 memcpy(&rule_hw->ib.dst_gid_msk, &spec->ib.dst_gid_msk, 16);
867 case MLX4_NET_TRANS_RULE_ID_IPV6:
870 case MLX4_NET_TRANS_RULE_ID_IPV4:
871 rule_hw->ipv4.src_ip = spec->ipv4.src_ip;
872 rule_hw->ipv4.src_ip_msk = spec->ipv4.src_ip_msk;
873 rule_hw->ipv4.dst_ip = spec->ipv4.dst_ip;
874 rule_hw->ipv4.dst_ip_msk = spec->ipv4.dst_ip_msk;
877 case MLX4_NET_TRANS_RULE_ID_TCP:
878 case MLX4_NET_TRANS_RULE_ID_UDP:
879 rule_hw->tcp_udp.dst_port = spec->tcp_udp.dst_port;
880 rule_hw->tcp_udp.dst_port_msk = spec->tcp_udp.dst_port_msk;
881 rule_hw->tcp_udp.src_port = spec->tcp_udp.src_port;
882 rule_hw->tcp_udp.src_port_msk = spec->tcp_udp.src_port_msk;
885 case MLX4_NET_TRANS_RULE_ID_VXLAN:
887 cpu_to_be32(be32_to_cpu(spec->vxlan.vni) << 8);
888 rule_hw->vxlan.vni_mask =
889 cpu_to_be32(be32_to_cpu(spec->vxlan.vni_mask) << 8);
896 return __rule_hw_sz[spec->id];
899 static void mlx4_err_rule(struct mlx4_dev *dev, char *str,
900 struct mlx4_net_trans_rule *rule)
903 struct mlx4_spec_list *cur;
907 mlx4_err(dev, "%s", str);
908 len += snprintf(buf + len, BUF_SIZE - len,
909 "port = %d prio = 0x%x qp = 0x%x ",
910 rule->port, rule->priority, rule->qpn);
912 list_for_each_entry(cur, &rule->list, list) {
914 case MLX4_NET_TRANS_RULE_ID_ETH:
915 len += snprintf(buf + len, BUF_SIZE - len,
916 "dmac = %pM ", &cur->eth.dst_mac);
917 if (cur->eth.ether_type)
918 len += snprintf(buf + len, BUF_SIZE - len,
920 be16_to_cpu(cur->eth.ether_type));
921 if (cur->eth.vlan_id)
922 len += snprintf(buf + len, BUF_SIZE - len,
924 be16_to_cpu(cur->eth.vlan_id));
927 case MLX4_NET_TRANS_RULE_ID_IPV4:
928 if (cur->ipv4.src_ip)
929 len += snprintf(buf + len, BUF_SIZE - len,
932 if (cur->ipv4.dst_ip)
933 len += snprintf(buf + len, BUF_SIZE - len,
938 case MLX4_NET_TRANS_RULE_ID_TCP:
939 case MLX4_NET_TRANS_RULE_ID_UDP:
940 if (cur->tcp_udp.src_port)
941 len += snprintf(buf + len, BUF_SIZE - len,
943 be16_to_cpu(cur->tcp_udp.src_port));
944 if (cur->tcp_udp.dst_port)
945 len += snprintf(buf + len, BUF_SIZE - len,
947 be16_to_cpu(cur->tcp_udp.dst_port));
950 case MLX4_NET_TRANS_RULE_ID_IB:
951 len += snprintf(buf + len, BUF_SIZE - len,
952 "dst-gid = %pI6\n", cur->ib.dst_gid);
953 len += snprintf(buf + len, BUF_SIZE - len,
954 "dst-gid-mask = %pI6\n",
955 cur->ib.dst_gid_msk);
958 case MLX4_NET_TRANS_RULE_ID_VXLAN:
959 len += snprintf(buf + len, BUF_SIZE - len,
960 "VNID = %d ", be32_to_cpu(cur->vxlan.vni));
962 case MLX4_NET_TRANS_RULE_ID_IPV6:
969 len += snprintf(buf + len, BUF_SIZE - len, "\n");
970 mlx4_err(dev, "%s", buf);
973 mlx4_err(dev, "Network rule error message was truncated, print buffer is too small\n");
976 int mlx4_flow_attach(struct mlx4_dev *dev,
977 struct mlx4_net_trans_rule *rule, u64 *reg_id)
979 struct mlx4_cmd_mailbox *mailbox;
980 struct mlx4_spec_list *cur;
984 mailbox = mlx4_alloc_cmd_mailbox(dev);
986 return PTR_ERR(mailbox);
988 trans_rule_ctrl_to_hw(rule, mailbox->buf);
990 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
992 list_for_each_entry(cur, &rule->list, list) {
993 ret = parse_trans_rule(dev, cur, mailbox->buf + size);
995 mlx4_free_cmd_mailbox(dev, mailbox);
1001 ret = mlx4_QP_FLOW_STEERING_ATTACH(dev, mailbox, size >> 2, reg_id);
1002 if (ret == -ENOMEM) {
1004 "mcg table is full. Fail to register network rule\n",
1007 if (ret == -ENXIO) {
1008 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED)
1010 "DMFS is not enabled, "
1011 "failed to register network rule.\n",
1015 "Rule exceeds the dmfs_high_rate_mode limitations, "
1016 "failed to register network rule.\n",
1020 mlx4_err_rule(dev, "Fail to register network rule.\n", rule);
1024 mlx4_free_cmd_mailbox(dev, mailbox);
1028 EXPORT_SYMBOL_GPL(mlx4_flow_attach);
1030 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id)
1034 err = mlx4_QP_FLOW_STEERING_DETACH(dev, reg_id);
1036 mlx4_err(dev, "Fail to detach network rule. registration id = 0x%llx\n",
1040 EXPORT_SYMBOL_GPL(mlx4_flow_detach);
1042 int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr,
1043 int port, int qpn, u16 prio, u64 *reg_id)
1046 struct mlx4_spec_list spec_eth_outer = { {NULL} };
1047 struct mlx4_spec_list spec_vxlan = { {NULL} };
1048 struct mlx4_spec_list spec_eth_inner = { {NULL} };
1050 struct mlx4_net_trans_rule rule = {
1051 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1053 .allow_loopback = 1,
1054 .promisc_mode = MLX4_FS_REGULAR,
1057 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
1061 rule.priority = prio;
1062 INIT_LIST_HEAD(&rule.list);
1064 spec_eth_outer.id = MLX4_NET_TRANS_RULE_ID_ETH;
1065 memcpy(spec_eth_outer.eth.dst_mac, addr, ETH_ALEN);
1066 memcpy(spec_eth_outer.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
1068 spec_vxlan.id = MLX4_NET_TRANS_RULE_ID_VXLAN; /* any vxlan header */
1069 spec_eth_inner.id = MLX4_NET_TRANS_RULE_ID_ETH; /* any inner eth header */
1071 list_add_tail(&spec_eth_outer.list, &rule.list);
1072 list_add_tail(&spec_vxlan.list, &rule.list);
1073 list_add_tail(&spec_eth_inner.list, &rule.list);
1075 err = mlx4_flow_attach(dev, &rule, reg_id);
1078 EXPORT_SYMBOL(mlx4_tunnel_steer_add);
1080 int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn,
1086 in_param = ((u64) min_range_qpn) << 32;
1087 in_param |= ((u64) max_range_qpn) & 0xFFFFFFFF;
1089 err = mlx4_cmd(dev, in_param, 0, 0,
1090 MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1091 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1095 EXPORT_SYMBOL_GPL(mlx4_FLOW_STEERING_IB_UC_QP_RANGE);
1097 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1098 int block_mcast_loopback, enum mlx4_protocol prot,
1099 enum mlx4_steer_type steer)
1101 struct mlx4_priv *priv = mlx4_priv(dev);
1102 struct mlx4_cmd_mailbox *mailbox;
1103 struct mlx4_mgm *mgm;
1105 int index = -1, prev;
1112 mailbox = mlx4_alloc_cmd_mailbox(dev);
1113 if (IS_ERR(mailbox))
1114 return PTR_ERR(mailbox);
1117 mutex_lock(&priv->mcg_table.mutex);
1118 err = find_entry(dev, port, gid, prot,
1119 mailbox, &prev, &index);
1124 if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) {
1126 memcpy(mgm->gid, gid, 16);
1131 index = mlx4_bitmap_alloc(&priv->mcg_table.bitmap);
1133 mlx4_err(dev, "No AMGM entries left\n");
1137 index += dev->caps.num_mgms;
1140 memset(mgm, 0, sizeof *mgm);
1141 memcpy(mgm->gid, gid, 16);
1144 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
1145 if (members_count == dev->caps.num_qp_per_mgm) {
1146 mlx4_err(dev, "MGM at index %x is full\n", index);
1151 for (i = 0; i < members_count; ++i)
1152 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn) {
1153 mlx4_dbg(dev, "QP %06x already a member of MGM\n", qp->qpn);
1158 if (block_mcast_loopback)
1159 mgm->qp[members_count++] = cpu_to_be32((qp->qpn & MGM_QPN_MASK) |
1160 (1U << MGM_BLCK_LB_BIT));
1162 mgm->qp[members_count++] = cpu_to_be32(qp->qpn & MGM_QPN_MASK);
1164 mgm->members_count = cpu_to_be32(members_count | (u32) prot << 30);
1166 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1173 err = mlx4_READ_ENTRY(dev, prev, mailbox);
1177 mgm->next_gid_index = cpu_to_be32(index << 6);
1179 err = mlx4_WRITE_ENTRY(dev, prev, mailbox);
1184 if (prot == MLX4_PROT_ETH && index != -1) {
1185 /* manage the steering entry for promisc mode */
1187 err = new_steering_entry(dev, port, steer,
1190 err = existing_steering_entry(dev, port, steer,
1193 if (err && link && index != -1) {
1194 if (index < dev->caps.num_mgms)
1195 mlx4_warn(dev, "Got AMGM index %d < %d\n",
1196 index, dev->caps.num_mgms);
1198 mlx4_bitmap_free(&priv->mcg_table.bitmap,
1199 index - dev->caps.num_mgms, MLX4_USE_RR);
1201 mutex_unlock(&priv->mcg_table.mutex);
1203 mlx4_free_cmd_mailbox(dev, mailbox);
1207 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1208 enum mlx4_protocol prot, enum mlx4_steer_type steer)
1210 struct mlx4_priv *priv = mlx4_priv(dev);
1211 struct mlx4_cmd_mailbox *mailbox;
1212 struct mlx4_mgm *mgm;
1218 bool removed_entry = false;
1220 mailbox = mlx4_alloc_cmd_mailbox(dev);
1221 if (IS_ERR(mailbox))
1222 return PTR_ERR(mailbox);
1225 mutex_lock(&priv->mcg_table.mutex);
1227 err = find_entry(dev, port, gid, prot,
1228 mailbox, &prev, &index);
1233 mlx4_err(dev, "MGID %pI6 not found\n", gid);
1238 /* If this QP is also a promisc QP, it shouldn't be removed only if
1239 * at least one none promisc QP is also attached to this MCG
1241 if (prot == MLX4_PROT_ETH &&
1242 check_duplicate_entry(dev, port, steer, index, qp->qpn) &&
1243 !promisc_steering_entry(dev, port, steer, index, qp->qpn, NULL))
1246 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
1247 for (i = 0; i < members_count; ++i)
1248 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn) {
1254 mlx4_err(dev, "QP %06x not found in MGM\n", qp->qpn);
1259 /* copy the last QP in this MGM over removed QP */
1260 mgm->qp[loc] = mgm->qp[members_count - 1];
1261 mgm->qp[members_count - 1] = 0;
1262 mgm->members_count = cpu_to_be32(--members_count | (u32) prot << 30);
1264 if (prot == MLX4_PROT_ETH)
1265 removed_entry = can_remove_steering_entry(dev, port, steer,
1267 if (members_count && (prot != MLX4_PROT_ETH || !removed_entry)) {
1268 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1272 /* We are going to delete the entry, members count should be 0 */
1273 mgm->members_count = cpu_to_be32((u32) prot << 30);
1276 /* Remove entry from MGM */
1277 int amgm_index = be32_to_cpu(mgm->next_gid_index) >> 6;
1279 err = mlx4_READ_ENTRY(dev, amgm_index, mailbox);
1283 memset(mgm->gid, 0, 16);
1285 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1290 if (amgm_index < dev->caps.num_mgms)
1291 mlx4_warn(dev, "MGM entry %d had AMGM index %d < %d\n",
1292 index, amgm_index, dev->caps.num_mgms);
1294 mlx4_bitmap_free(&priv->mcg_table.bitmap,
1295 amgm_index - dev->caps.num_mgms, MLX4_USE_RR);
1298 /* Remove entry from AMGM */
1299 int cur_next_index = be32_to_cpu(mgm->next_gid_index) >> 6;
1300 err = mlx4_READ_ENTRY(dev, prev, mailbox);
1304 mgm->next_gid_index = cpu_to_be32(cur_next_index << 6);
1306 err = mlx4_WRITE_ENTRY(dev, prev, mailbox);
1310 if (index < dev->caps.num_mgms)
1311 mlx4_warn(dev, "entry %d had next AMGM index %d < %d\n",
1312 prev, index, dev->caps.num_mgms);
1314 mlx4_bitmap_free(&priv->mcg_table.bitmap,
1315 index - dev->caps.num_mgms, MLX4_USE_RR);
1319 mutex_unlock(&priv->mcg_table.mutex);
1321 mlx4_free_cmd_mailbox(dev, mailbox);
1322 if (err && dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
1323 /* In case device is under an error, return success as a closing command */
1328 static int mlx4_QP_ATTACH(struct mlx4_dev *dev, struct mlx4_qp *qp,
1329 u8 gid[16], u8 attach, u8 block_loopback,
1330 enum mlx4_protocol prot)
1332 struct mlx4_cmd_mailbox *mailbox;
1336 if (!mlx4_is_mfunc(dev))
1339 mailbox = mlx4_alloc_cmd_mailbox(dev);
1340 if (IS_ERR(mailbox))
1341 return PTR_ERR(mailbox);
1343 memcpy(mailbox->buf, gid, 16);
1345 qpn |= (prot << 28);
1346 if (attach && block_loopback)
1349 err = mlx4_cmd(dev, mailbox->dma, qpn, attach,
1350 MLX4_CMD_QP_ATTACH, MLX4_CMD_TIME_CLASS_A,
1353 mlx4_free_cmd_mailbox(dev, mailbox);
1354 if (err && !attach &&
1355 dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
1360 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1361 u8 gid[16], u8 port,
1362 int block_mcast_loopback,
1363 enum mlx4_protocol prot, u64 *reg_id)
1365 struct mlx4_spec_list spec = { {NULL} };
1366 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
1368 struct mlx4_net_trans_rule rule = {
1369 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1371 .promisc_mode = MLX4_FS_REGULAR,
1372 .priority = MLX4_DOMAIN_NIC,
1375 rule.allow_loopback = !block_mcast_loopback;
1378 INIT_LIST_HEAD(&rule.list);
1382 spec.id = MLX4_NET_TRANS_RULE_ID_ETH;
1383 memcpy(spec.eth.dst_mac, &gid[10], ETH_ALEN);
1384 memcpy(spec.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
1387 case MLX4_PROT_IB_IPV6:
1388 spec.id = MLX4_NET_TRANS_RULE_ID_IB;
1389 memcpy(spec.ib.dst_gid, gid, 16);
1390 memset(&spec.ib.dst_gid_msk, 0xff, 16);
1395 list_add_tail(&spec.list, &rule.list);
1397 return mlx4_flow_attach(dev, &rule, reg_id);
1400 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1401 u8 port, int block_mcast_loopback,
1402 enum mlx4_protocol prot, u64 *reg_id)
1404 switch (dev->caps.steering_mode) {
1405 case MLX4_STEERING_MODE_A0:
1406 if (prot == MLX4_PROT_ETH)
1409 case MLX4_STEERING_MODE_B0:
1410 if (prot == MLX4_PROT_ETH)
1411 gid[7] |= (MLX4_MC_STEER << 1);
1413 if (mlx4_is_mfunc(dev))
1414 return mlx4_QP_ATTACH(dev, qp, gid, 1,
1415 block_mcast_loopback, prot);
1416 return mlx4_qp_attach_common(dev, qp, gid,
1417 block_mcast_loopback, prot,
1420 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1421 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port,
1422 block_mcast_loopback,
1428 EXPORT_SYMBOL_GPL(mlx4_multicast_attach);
1430 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1431 enum mlx4_protocol prot, u64 reg_id)
1433 switch (dev->caps.steering_mode) {
1434 case MLX4_STEERING_MODE_A0:
1435 if (prot == MLX4_PROT_ETH)
1438 case MLX4_STEERING_MODE_B0:
1439 if (prot == MLX4_PROT_ETH)
1440 gid[7] |= (MLX4_MC_STEER << 1);
1442 if (mlx4_is_mfunc(dev))
1443 return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot);
1445 return mlx4_qp_detach_common(dev, qp, gid, prot,
1448 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1449 return mlx4_flow_detach(dev, reg_id);
1455 EXPORT_SYMBOL_GPL(mlx4_multicast_detach);
1457 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port,
1458 u32 qpn, enum mlx4_net_trans_promisc_mode mode)
1460 struct mlx4_net_trans_rule rule;
1464 case MLX4_FS_ALL_DEFAULT:
1465 regid_p = &dev->regid_promisc_array[port];
1467 case MLX4_FS_MC_DEFAULT:
1468 regid_p = &dev->regid_allmulti_array[port];
1477 rule.promisc_mode = mode;
1480 INIT_LIST_HEAD(&rule.list);
1481 mlx4_err(dev, "going promisc on %x\n", port);
1483 return mlx4_flow_attach(dev, &rule, regid_p);
1485 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_add);
1487 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1488 enum mlx4_net_trans_promisc_mode mode)
1494 case MLX4_FS_ALL_DEFAULT:
1495 regid_p = &dev->regid_promisc_array[port];
1497 case MLX4_FS_MC_DEFAULT:
1498 regid_p = &dev->regid_allmulti_array[port];
1507 ret = mlx4_flow_detach(dev, *regid_p);
1513 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_remove);
1515 int mlx4_unicast_attach(struct mlx4_dev *dev,
1516 struct mlx4_qp *qp, u8 gid[16],
1517 int block_mcast_loopback, enum mlx4_protocol prot)
1519 if (prot == MLX4_PROT_ETH)
1520 gid[7] |= (MLX4_UC_STEER << 1);
1522 if (mlx4_is_mfunc(dev))
1523 return mlx4_QP_ATTACH(dev, qp, gid, 1,
1524 block_mcast_loopback, prot);
1526 return mlx4_qp_attach_common(dev, qp, gid, block_mcast_loopback,
1527 prot, MLX4_UC_STEER);
1529 EXPORT_SYMBOL_GPL(mlx4_unicast_attach);
1531 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1532 u8 gid[16], enum mlx4_protocol prot)
1534 if (prot == MLX4_PROT_ETH)
1535 gid[7] |= (MLX4_UC_STEER << 1);
1537 if (mlx4_is_mfunc(dev))
1538 return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot);
1540 return mlx4_qp_detach_common(dev, qp, gid, prot, MLX4_UC_STEER);
1542 EXPORT_SYMBOL_GPL(mlx4_unicast_detach);
1544 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1545 struct mlx4_vhcr *vhcr,
1546 struct mlx4_cmd_mailbox *inbox,
1547 struct mlx4_cmd_mailbox *outbox,
1548 struct mlx4_cmd_info *cmd)
1550 u32 qpn = (u32) vhcr->in_param & 0xffffffff;
1551 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_param >> 62);
1552 enum mlx4_steer_type steer = vhcr->in_modifier;
1557 /* Promiscuous unicast is not allowed in mfunc */
1558 if (mlx4_is_mfunc(dev) && steer == MLX4_UC_STEER)
1561 if (vhcr->op_modifier)
1562 return add_promisc_qp(dev, port, steer, qpn);
1564 return remove_promisc_qp(dev, port, steer, qpn);
1567 static int mlx4_PROMISC(struct mlx4_dev *dev, u32 qpn,
1568 enum mlx4_steer_type steer, u8 add, u8 port)
1570 return mlx4_cmd(dev, (u64) qpn | (u64) port << 62, (u32) steer, add,
1571 MLX4_CMD_PROMISC, MLX4_CMD_TIME_CLASS_A,
1575 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port)
1577 if (mlx4_is_mfunc(dev))
1578 return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 1, port);
1580 return add_promisc_qp(dev, port, MLX4_MC_STEER, qpn);
1582 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_add);
1584 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port)
1586 if (mlx4_is_mfunc(dev))
1587 return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 0, port);
1589 return remove_promisc_qp(dev, port, MLX4_MC_STEER, qpn);
1591 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_remove);
1593 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port)
1595 if (mlx4_is_mfunc(dev))
1596 return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 1, port);
1598 return add_promisc_qp(dev, port, MLX4_UC_STEER, qpn);
1600 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_add);
1602 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port)
1604 if (mlx4_is_mfunc(dev))
1605 return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 0, port);
1607 return remove_promisc_qp(dev, port, MLX4_UC_STEER, qpn);
1609 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_remove);
1611 int mlx4_init_mcg_table(struct mlx4_dev *dev)
1613 struct mlx4_priv *priv = mlx4_priv(dev);
1616 /* No need for mcg_table when fw managed the mcg table*/
1617 if (dev->caps.steering_mode ==
1618 MLX4_STEERING_MODE_DEVICE_MANAGED)
1620 err = mlx4_bitmap_init(&priv->mcg_table.bitmap, dev->caps.num_amgms,
1621 dev->caps.num_amgms - 1, 0, 0);
1625 mutex_init(&priv->mcg_table.mutex);
1630 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev)
1632 if (dev->caps.steering_mode !=
1633 MLX4_STEERING_MODE_DEVICE_MANAGED)
1634 mlx4_bitmap_cleanup(&mlx4_priv(dev)->mcg_table.bitmap);