2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/string.h>
35 #include <linux/etherdevice.h>
37 #include <linux/mlx4/cmd.h>
38 #include <linux/export.h>
42 #define MGM_QPN_MASK 0x00FFFFFF
43 #define MGM_BLCK_LB_BIT 30
45 static const u8 zero_gid[16]; /* automatically initialized to 0 */
48 __be32 next_gid_index;
52 __be32 qp[MLX4_MAX_QP_PER_MGM];
55 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev)
57 return 1 << dev->oper_log_mgm_entry_size;
60 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev)
62 return 4 * (mlx4_get_mgm_entry_size(dev) / 16 - 2);
65 static int mlx4_QP_FLOW_STEERING_ATTACH(struct mlx4_dev *dev,
66 struct mlx4_cmd_mailbox *mailbox,
73 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, size, 0,
74 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
83 static int mlx4_QP_FLOW_STEERING_DETACH(struct mlx4_dev *dev, u64 regid)
87 err = mlx4_cmd(dev, regid, 0, 0,
88 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
94 static int mlx4_READ_ENTRY(struct mlx4_dev *dev, int index,
95 struct mlx4_cmd_mailbox *mailbox)
97 return mlx4_cmd_box(dev, 0, mailbox->dma, index, 0, MLX4_CMD_READ_MCG,
98 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
101 static int mlx4_WRITE_ENTRY(struct mlx4_dev *dev, int index,
102 struct mlx4_cmd_mailbox *mailbox)
104 return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG,
105 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
108 static int mlx4_WRITE_PROMISC(struct mlx4_dev *dev, u8 port, u8 steer,
109 struct mlx4_cmd_mailbox *mailbox)
113 in_mod = (u32) port << 16 | steer << 1;
114 return mlx4_cmd(dev, mailbox->dma, in_mod, 0x1,
115 MLX4_CMD_WRITE_MCG, MLX4_CMD_TIME_CLASS_A,
119 static int mlx4_GID_HASH(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
120 u16 *hash, u8 op_mod)
125 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, 0, op_mod,
126 MLX4_CMD_MGID_HASH, MLX4_CMD_TIME_CLASS_A,
135 static struct mlx4_promisc_qp *get_promisc_qp(struct mlx4_dev *dev, u8 port,
136 enum mlx4_steer_type steer,
139 struct mlx4_steer *s_steer = &mlx4_priv(dev)->steer[port - 1];
140 struct mlx4_promisc_qp *pqp;
142 list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) {
151 * Add new entry to steering data structure.
152 * All promisc QPs should be added as well
154 static int new_steering_entry(struct mlx4_dev *dev, u8 port,
155 enum mlx4_steer_type steer,
156 unsigned int index, u32 qpn)
158 struct mlx4_steer *s_steer;
159 struct mlx4_cmd_mailbox *mailbox;
160 struct mlx4_mgm *mgm;
162 struct mlx4_steer_index *new_entry;
163 struct mlx4_promisc_qp *pqp;
164 struct mlx4_promisc_qp *dqp = NULL;
168 s_steer = &mlx4_priv(dev)->steer[port - 1];
169 new_entry = kzalloc(sizeof *new_entry, GFP_KERNEL);
173 INIT_LIST_HEAD(&new_entry->duplicates);
174 new_entry->index = index;
175 list_add_tail(&new_entry->list, &s_steer->steer_entries[steer]);
177 /* If the given qpn is also a promisc qp,
178 * it should be inserted to duplicates list
180 pqp = get_promisc_qp(dev, port, steer, qpn);
182 dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
188 list_add_tail(&dqp->list, &new_entry->duplicates);
191 /* if no promisc qps for this vep, we are done */
192 if (list_empty(&s_steer->promisc_qps[steer]))
195 /* now need to add all the promisc qps to the new
196 * steering entry, as they should also receive the packets
197 * destined to this address */
198 mailbox = mlx4_alloc_cmd_mailbox(dev);
199 if (IS_ERR(mailbox)) {
205 err = mlx4_READ_ENTRY(dev, index, mailbox);
209 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
210 prot = be32_to_cpu(mgm->members_count) >> 30;
211 list_for_each_entry(pqp, &s_steer->promisc_qps[steer], list) {
212 /* don't add already existing qpn */
215 if (members_count == dev->caps.num_qp_per_mgm) {
222 mgm->qp[members_count++] = cpu_to_be32(pqp->qpn & MGM_QPN_MASK);
224 /* update the qps count and update the entry with all the promisc qps*/
225 mgm->members_count = cpu_to_be32(members_count | (prot << 30));
226 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
229 mlx4_free_cmd_mailbox(dev, mailbox);
234 list_del(&dqp->list);
237 list_del(&new_entry->list);
242 /* update the data structures with existing steering entry */
243 static int existing_steering_entry(struct mlx4_dev *dev, u8 port,
244 enum mlx4_steer_type steer,
245 unsigned int index, u32 qpn)
247 struct mlx4_steer *s_steer;
248 struct mlx4_steer_index *tmp_entry, *entry = NULL;
249 struct mlx4_promisc_qp *pqp;
250 struct mlx4_promisc_qp *dqp;
252 s_steer = &mlx4_priv(dev)->steer[port - 1];
254 pqp = get_promisc_qp(dev, port, steer, qpn);
256 return 0; /* nothing to do */
258 list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) {
259 if (tmp_entry->index == index) {
264 if (unlikely(!entry)) {
265 mlx4_warn(dev, "Steering entry at index %x is not registered\n", index);
269 /* the given qpn is listed as a promisc qpn
270 * we need to add it as a duplicate to this entry
271 * for future references */
272 list_for_each_entry(dqp, &entry->duplicates, list) {
274 return 0; /* qp is already duplicated */
277 /* add the qp as a duplicate on this index */
278 dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
282 list_add_tail(&dqp->list, &entry->duplicates);
287 /* Check whether a qpn is a duplicate on steering entry
288 * If so, it should not be removed from mgm */
289 static bool check_duplicate_entry(struct mlx4_dev *dev, u8 port,
290 enum mlx4_steer_type steer,
291 unsigned int index, u32 qpn)
293 struct mlx4_steer *s_steer;
294 struct mlx4_steer_index *tmp_entry, *entry = NULL;
295 struct mlx4_promisc_qp *dqp, *tmp_dqp;
297 s_steer = &mlx4_priv(dev)->steer[port - 1];
299 /* if qp is not promisc, it cannot be duplicated */
300 if (!get_promisc_qp(dev, port, steer, qpn))
303 /* The qp is promisc qp so it is a duplicate on this index
304 * Find the index entry, and remove the duplicate */
305 list_for_each_entry(tmp_entry, &s_steer->steer_entries[steer], list) {
306 if (tmp_entry->index == index) {
311 if (unlikely(!entry)) {
312 mlx4_warn(dev, "Steering entry for index %x is not registered\n", index);
315 list_for_each_entry_safe(dqp, tmp_dqp, &entry->duplicates, list) {
316 if (dqp->qpn == qpn) {
317 list_del(&dqp->list);
324 /* I a steering entry contains only promisc QPs, it can be removed. */
325 static bool can_remove_steering_entry(struct mlx4_dev *dev, u8 port,
326 enum mlx4_steer_type steer,
327 unsigned int index, u32 tqpn)
329 struct mlx4_steer *s_steer;
330 struct mlx4_cmd_mailbox *mailbox;
331 struct mlx4_mgm *mgm;
332 struct mlx4_steer_index *entry = NULL, *tmp_entry;
338 s_steer = &mlx4_priv(dev)->steer[port - 1];
340 mailbox = mlx4_alloc_cmd_mailbox(dev);
345 if (mlx4_READ_ENTRY(dev, index, mailbox))
347 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
348 for (i = 0; i < members_count; i++) {
349 qpn = be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK;
350 if (!get_promisc_qp(dev, port, steer, qpn) && qpn != tqpn) {
351 /* the qp is not promisc, the entry can't be removed */
355 /* All the qps currently registered for this entry are promiscuous,
356 * Checking for duplicates */
358 list_for_each_entry_safe(entry, tmp_entry, &s_steer->steer_entries[steer], list) {
359 if (entry->index == index) {
360 if (list_empty(&entry->duplicates)) {
361 list_del(&entry->list);
364 /* This entry contains duplicates so it shouldn't be removed */
372 mlx4_free_cmd_mailbox(dev, mailbox);
376 static int add_promisc_qp(struct mlx4_dev *dev, u8 port,
377 enum mlx4_steer_type steer, u32 qpn)
379 struct mlx4_steer *s_steer;
380 struct mlx4_cmd_mailbox *mailbox;
381 struct mlx4_mgm *mgm;
382 struct mlx4_steer_index *entry;
383 struct mlx4_promisc_qp *pqp;
384 struct mlx4_promisc_qp *dqp;
390 struct mlx4_priv *priv = mlx4_priv(dev);
392 s_steer = &mlx4_priv(dev)->steer[port - 1];
394 mutex_lock(&priv->mcg_table.mutex);
396 if (get_promisc_qp(dev, port, steer, qpn)) {
397 err = 0; /* Noting to do, already exists */
401 pqp = kmalloc(sizeof *pqp, GFP_KERNEL);
408 mailbox = mlx4_alloc_cmd_mailbox(dev);
409 if (IS_ERR(mailbox)) {
415 /* the promisc qp needs to be added for each one of the steering
416 * entries, if it already exists, needs to be added as a duplicate
418 list_for_each_entry(entry, &s_steer->steer_entries[steer], list) {
419 err = mlx4_READ_ENTRY(dev, entry->index, mailbox);
423 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
424 prot = be32_to_cpu(mgm->members_count) >> 30;
426 for (i = 0; i < members_count; i++) {
427 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qpn) {
428 /* Entry already exists, add to duplicates */
429 dqp = kmalloc(sizeof *dqp, GFP_KERNEL);
435 list_add_tail(&dqp->list, &entry->duplicates);
440 /* Need to add the qpn to mgm */
441 if (members_count == dev->caps.num_qp_per_mgm) {
446 mgm->qp[members_count++] = cpu_to_be32(qpn & MGM_QPN_MASK);
447 mgm->members_count = cpu_to_be32(members_count | (prot << 30));
448 err = mlx4_WRITE_ENTRY(dev, entry->index, mailbox);
454 /* add the new qpn to list of promisc qps */
455 list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]);
456 /* now need to add all the promisc qps to default entry */
457 memset(mgm, 0, sizeof *mgm);
459 list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list)
460 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK);
461 mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30);
463 err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox);
467 mlx4_free_cmd_mailbox(dev, mailbox);
468 mutex_unlock(&priv->mcg_table.mutex);
472 list_del(&pqp->list);
474 mlx4_free_cmd_mailbox(dev, mailbox);
478 mutex_unlock(&priv->mcg_table.mutex);
482 static int remove_promisc_qp(struct mlx4_dev *dev, u8 port,
483 enum mlx4_steer_type steer, u32 qpn)
485 struct mlx4_priv *priv = mlx4_priv(dev);
486 struct mlx4_steer *s_steer;
487 struct mlx4_cmd_mailbox *mailbox;
488 struct mlx4_mgm *mgm;
489 struct mlx4_steer_index *entry;
490 struct mlx4_promisc_qp *pqp;
491 struct mlx4_promisc_qp *dqp;
494 bool back_to_list = false;
498 s_steer = &mlx4_priv(dev)->steer[port - 1];
499 mutex_lock(&priv->mcg_table.mutex);
501 pqp = get_promisc_qp(dev, port, steer, qpn);
502 if (unlikely(!pqp)) {
503 mlx4_warn(dev, "QP %x is not promiscuous QP\n", qpn);
509 /*remove from list of promisc qps */
510 list_del(&pqp->list);
512 /* set the default entry not to include the removed one */
513 mailbox = mlx4_alloc_cmd_mailbox(dev);
514 if (IS_ERR(mailbox)) {
520 memset(mgm, 0, sizeof *mgm);
522 list_for_each_entry(dqp, &s_steer->promisc_qps[steer], list)
523 mgm->qp[members_count++] = cpu_to_be32(dqp->qpn & MGM_QPN_MASK);
524 mgm->members_count = cpu_to_be32(members_count | MLX4_PROT_ETH << 30);
526 err = mlx4_WRITE_PROMISC(dev, port, steer, mailbox);
530 /* remove the qp from all the steering entries*/
531 list_for_each_entry(entry, &s_steer->steer_entries[steer], list) {
533 list_for_each_entry(dqp, &entry->duplicates, list) {
534 if (dqp->qpn == qpn) {
540 /* a duplicate, no need to change the mgm,
541 * only update the duplicates list */
542 list_del(&dqp->list);
545 err = mlx4_READ_ENTRY(dev, entry->index, mailbox);
548 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
549 for (loc = -1, i = 0; i < members_count; ++i)
550 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qpn)
553 mgm->members_count = cpu_to_be32(--members_count |
554 (MLX4_PROT_ETH << 30));
555 mgm->qp[loc] = mgm->qp[i - 1];
558 err = mlx4_WRITE_ENTRY(dev, entry->index, mailbox);
566 mlx4_free_cmd_mailbox(dev, mailbox);
569 list_add_tail(&pqp->list, &s_steer->promisc_qps[steer]);
573 mutex_unlock(&priv->mcg_table.mutex);
578 * Caller must hold MCG table semaphore. gid and mgm parameters must
579 * be properly aligned for command interface.
581 * Returns 0 unless a firmware command error occurs.
583 * If GID is found in MGM or MGM is empty, *index = *hash, *prev = -1
584 * and *mgm holds MGM entry.
586 * if GID is found in AMGM, *index = index in AMGM, *prev = index of
587 * previous entry in hash chain and *mgm holds AMGM entry.
589 * If no AMGM exists for given gid, *index = -1, *prev = index of last
590 * entry in hash chain and *mgm holds end of hash chain.
592 static int find_entry(struct mlx4_dev *dev, u8 port,
593 u8 *gid, enum mlx4_protocol prot,
594 struct mlx4_cmd_mailbox *mgm_mailbox,
595 int *prev, int *index)
597 struct mlx4_cmd_mailbox *mailbox;
598 struct mlx4_mgm *mgm = mgm_mailbox->buf;
602 u8 op_mod = (prot == MLX4_PROT_ETH) ?
603 !!(dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) : 0;
605 mailbox = mlx4_alloc_cmd_mailbox(dev);
610 memcpy(mgid, gid, 16);
612 err = mlx4_GID_HASH(dev, mailbox, &hash, op_mod);
613 mlx4_free_cmd_mailbox(dev, mailbox);
618 mlx4_dbg(dev, "Hash for %pI6 is %04x\n", gid, hash);
624 err = mlx4_READ_ENTRY(dev, *index, mgm_mailbox);
628 if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) {
629 if (*index != hash) {
630 mlx4_err(dev, "Found zero MGID in AMGM.\n");
636 if (!memcmp(mgm->gid, gid, 16) &&
637 be32_to_cpu(mgm->members_count) >> 30 == prot)
641 *index = be32_to_cpu(mgm->next_gid_index) >> 6;
648 static void trans_rule_ctrl_to_hw(struct mlx4_net_trans_rule *ctrl,
649 struct mlx4_net_trans_rule_hw_ctrl *hw)
651 static const u8 __promisc_mode[] = {
652 [MLX4_FS_PROMISC_NONE] = 0x0,
653 [MLX4_FS_PROMISC_UPLINK] = 0x1,
654 [MLX4_FS_PROMISC_FUNCTION_PORT] = 0x2,
655 [MLX4_FS_PROMISC_ALL_MULTI] = 0x3,
660 dw = ctrl->queue_mode == MLX4_NET_TRANS_Q_LIFO ? 1 : 0;
661 dw |= ctrl->exclusive ? (1 << 2) : 0;
662 dw |= ctrl->allow_loopback ? (1 << 3) : 0;
663 dw |= __promisc_mode[ctrl->promisc_mode] << 8;
664 dw |= ctrl->priority << 16;
666 hw->ctrl = cpu_to_be32(dw);
667 hw->port = ctrl->port;
668 hw->qpn = cpu_to_be32(ctrl->qpn);
671 const u16 __sw_id_hw[] = {
672 [MLX4_NET_TRANS_RULE_ID_ETH] = 0xE001,
673 [MLX4_NET_TRANS_RULE_ID_IB] = 0xE005,
674 [MLX4_NET_TRANS_RULE_ID_IPV6] = 0xE003,
675 [MLX4_NET_TRANS_RULE_ID_IPV4] = 0xE002,
676 [MLX4_NET_TRANS_RULE_ID_TCP] = 0xE004,
677 [MLX4_NET_TRANS_RULE_ID_UDP] = 0xE006
680 static int parse_trans_rule(struct mlx4_dev *dev, struct mlx4_spec_list *spec,
681 struct _rule_hw *rule_hw)
683 static const size_t __rule_hw_sz[] = {
684 [MLX4_NET_TRANS_RULE_ID_ETH] =
685 sizeof(struct mlx4_net_trans_rule_hw_eth),
686 [MLX4_NET_TRANS_RULE_ID_IB] =
687 sizeof(struct mlx4_net_trans_rule_hw_ib),
688 [MLX4_NET_TRANS_RULE_ID_IPV6] = 0,
689 [MLX4_NET_TRANS_RULE_ID_IPV4] =
690 sizeof(struct mlx4_net_trans_rule_hw_ipv4),
691 [MLX4_NET_TRANS_RULE_ID_TCP] =
692 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp),
693 [MLX4_NET_TRANS_RULE_ID_UDP] =
694 sizeof(struct mlx4_net_trans_rule_hw_tcp_udp)
696 if (spec->id >= MLX4_NET_TRANS_RULE_NUM) {
697 mlx4_err(dev, "Invalid network rule id. id = %d\n", spec->id);
700 memset(rule_hw, 0, __rule_hw_sz[spec->id]);
701 rule_hw->id = cpu_to_be16(__sw_id_hw[spec->id]);
702 rule_hw->size = __rule_hw_sz[spec->id] >> 2;
705 case MLX4_NET_TRANS_RULE_ID_ETH:
706 memcpy(rule_hw->eth.dst_mac, spec->eth.dst_mac, ETH_ALEN);
707 memcpy(rule_hw->eth.dst_mac_msk, spec->eth.dst_mac_msk,
709 memcpy(rule_hw->eth.src_mac, spec->eth.src_mac, ETH_ALEN);
710 memcpy(rule_hw->eth.src_mac_msk, spec->eth.src_mac_msk,
712 if (spec->eth.ether_type_enable) {
713 rule_hw->eth.ether_type_enable = 1;
714 rule_hw->eth.ether_type = spec->eth.ether_type;
716 rule_hw->eth.vlan_id = spec->eth.vlan_id;
717 rule_hw->eth.vlan_id_msk = spec->eth.vlan_id_msk;
720 case MLX4_NET_TRANS_RULE_ID_IB:
721 rule_hw->ib.qpn = spec->ib.r_qpn;
722 rule_hw->ib.qpn_mask = spec->ib.qpn_msk;
723 memcpy(&rule_hw->ib.dst_gid, &spec->ib.dst_gid, 16);
724 memcpy(&rule_hw->ib.dst_gid_msk, &spec->ib.dst_gid_msk, 16);
727 case MLX4_NET_TRANS_RULE_ID_IPV6:
730 case MLX4_NET_TRANS_RULE_ID_IPV4:
731 rule_hw->ipv4.src_ip = spec->ipv4.src_ip;
732 rule_hw->ipv4.src_ip_msk = spec->ipv4.src_ip_msk;
733 rule_hw->ipv4.dst_ip = spec->ipv4.dst_ip;
734 rule_hw->ipv4.dst_ip_msk = spec->ipv4.dst_ip_msk;
737 case MLX4_NET_TRANS_RULE_ID_TCP:
738 case MLX4_NET_TRANS_RULE_ID_UDP:
739 rule_hw->tcp_udp.dst_port = spec->tcp_udp.dst_port;
740 rule_hw->tcp_udp.dst_port_msk = spec->tcp_udp.dst_port_msk;
741 rule_hw->tcp_udp.src_port = spec->tcp_udp.src_port;
742 rule_hw->tcp_udp.src_port_msk = spec->tcp_udp.src_port_msk;
749 return __rule_hw_sz[spec->id];
752 static void mlx4_err_rule(struct mlx4_dev *dev, char *str,
753 struct mlx4_net_trans_rule *rule)
756 struct mlx4_spec_list *cur;
760 mlx4_err(dev, "%s", str);
761 len += snprintf(buf + len, BUF_SIZE - len,
762 "port = %d prio = 0x%x qp = 0x%x ",
763 rule->port, rule->priority, rule->qpn);
765 list_for_each_entry(cur, &rule->list, list) {
767 case MLX4_NET_TRANS_RULE_ID_ETH:
768 len += snprintf(buf + len, BUF_SIZE - len,
769 "dmac = %pM ", &cur->eth.dst_mac);
770 if (cur->eth.ether_type)
771 len += snprintf(buf + len, BUF_SIZE - len,
773 be16_to_cpu(cur->eth.ether_type));
774 if (cur->eth.vlan_id)
775 len += snprintf(buf + len, BUF_SIZE - len,
777 be16_to_cpu(cur->eth.vlan_id));
780 case MLX4_NET_TRANS_RULE_ID_IPV4:
781 if (cur->ipv4.src_ip)
782 len += snprintf(buf + len, BUF_SIZE - len,
785 if (cur->ipv4.dst_ip)
786 len += snprintf(buf + len, BUF_SIZE - len,
791 case MLX4_NET_TRANS_RULE_ID_TCP:
792 case MLX4_NET_TRANS_RULE_ID_UDP:
793 if (cur->tcp_udp.src_port)
794 len += snprintf(buf + len, BUF_SIZE - len,
796 be16_to_cpu(cur->tcp_udp.src_port));
797 if (cur->tcp_udp.dst_port)
798 len += snprintf(buf + len, BUF_SIZE - len,
800 be16_to_cpu(cur->tcp_udp.dst_port));
803 case MLX4_NET_TRANS_RULE_ID_IB:
804 len += snprintf(buf + len, BUF_SIZE - len,
805 "dst-gid = %pI6\n", cur->ib.dst_gid);
806 len += snprintf(buf + len, BUF_SIZE - len,
807 "dst-gid-mask = %pI6\n",
808 cur->ib.dst_gid_msk);
811 case MLX4_NET_TRANS_RULE_ID_IPV6:
818 len += snprintf(buf + len, BUF_SIZE - len, "\n");
819 mlx4_err(dev, "%s", buf);
822 mlx4_err(dev, "Network rule error message was truncated, print buffer is too small.\n");
825 int mlx4_flow_attach(struct mlx4_dev *dev,
826 struct mlx4_net_trans_rule *rule, u64 *reg_id)
828 struct mlx4_cmd_mailbox *mailbox;
829 struct mlx4_spec_list *cur;
833 mailbox = mlx4_alloc_cmd_mailbox(dev);
835 return PTR_ERR(mailbox);
837 memset(mailbox->buf, 0, sizeof(struct mlx4_net_trans_rule_hw_ctrl));
838 trans_rule_ctrl_to_hw(rule, mailbox->buf);
840 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
842 list_for_each_entry(cur, &rule->list, list) {
843 ret = parse_trans_rule(dev, cur, mailbox->buf + size);
845 mlx4_free_cmd_mailbox(dev, mailbox);
851 ret = mlx4_QP_FLOW_STEERING_ATTACH(dev, mailbox, size >> 2, reg_id);
854 "mcg table is full. Fail to register network rule.\n",
857 mlx4_err_rule(dev, "Fail to register network rule.\n", rule);
859 mlx4_free_cmd_mailbox(dev, mailbox);
863 EXPORT_SYMBOL_GPL(mlx4_flow_attach);
865 int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id)
869 err = mlx4_QP_FLOW_STEERING_DETACH(dev, reg_id);
871 mlx4_err(dev, "Fail to detach network rule. registration id = 0x%llx\n",
875 EXPORT_SYMBOL_GPL(mlx4_flow_detach);
877 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
878 int block_mcast_loopback, enum mlx4_protocol prot,
879 enum mlx4_steer_type steer)
881 struct mlx4_priv *priv = mlx4_priv(dev);
882 struct mlx4_cmd_mailbox *mailbox;
883 struct mlx4_mgm *mgm;
892 mailbox = mlx4_alloc_cmd_mailbox(dev);
894 return PTR_ERR(mailbox);
897 mutex_lock(&priv->mcg_table.mutex);
898 err = find_entry(dev, port, gid, prot,
899 mailbox, &prev, &index);
904 if (!(be32_to_cpu(mgm->members_count) & 0xffffff)) {
906 memcpy(mgm->gid, gid, 16);
911 index = mlx4_bitmap_alloc(&priv->mcg_table.bitmap);
913 mlx4_err(dev, "No AMGM entries left\n");
917 index += dev->caps.num_mgms;
920 memset(mgm, 0, sizeof *mgm);
921 memcpy(mgm->gid, gid, 16);
924 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
925 if (members_count == dev->caps.num_qp_per_mgm) {
926 mlx4_err(dev, "MGM at index %x is full.\n", index);
931 for (i = 0; i < members_count; ++i)
932 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn) {
933 mlx4_dbg(dev, "QP %06x already a member of MGM\n", qp->qpn);
938 if (block_mcast_loopback)
939 mgm->qp[members_count++] = cpu_to_be32((qp->qpn & MGM_QPN_MASK) |
940 (1U << MGM_BLCK_LB_BIT));
942 mgm->qp[members_count++] = cpu_to_be32(qp->qpn & MGM_QPN_MASK);
944 mgm->members_count = cpu_to_be32(members_count | (u32) prot << 30);
946 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
953 err = mlx4_READ_ENTRY(dev, prev, mailbox);
957 mgm->next_gid_index = cpu_to_be32(index << 6);
959 err = mlx4_WRITE_ENTRY(dev, prev, mailbox);
964 if (prot == MLX4_PROT_ETH) {
965 /* manage the steering entry for promisc mode */
967 new_steering_entry(dev, port, steer, index, qp->qpn);
969 existing_steering_entry(dev, port, steer,
972 if (err && link && index != -1) {
973 if (index < dev->caps.num_mgms)
974 mlx4_warn(dev, "Got AMGM index %d < %d",
975 index, dev->caps.num_mgms);
977 mlx4_bitmap_free(&priv->mcg_table.bitmap,
978 index - dev->caps.num_mgms);
980 mutex_unlock(&priv->mcg_table.mutex);
982 mlx4_free_cmd_mailbox(dev, mailbox);
986 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
987 enum mlx4_protocol prot, enum mlx4_steer_type steer)
989 struct mlx4_priv *priv = mlx4_priv(dev);
990 struct mlx4_cmd_mailbox *mailbox;
991 struct mlx4_mgm *mgm;
997 bool removed_entry = false;
999 mailbox = mlx4_alloc_cmd_mailbox(dev);
1000 if (IS_ERR(mailbox))
1001 return PTR_ERR(mailbox);
1004 mutex_lock(&priv->mcg_table.mutex);
1006 err = find_entry(dev, port, gid, prot,
1007 mailbox, &prev, &index);
1012 mlx4_err(dev, "MGID %pI6 not found\n", gid);
1017 /* if this pq is also a promisc qp, it shouldn't be removed */
1018 if (prot == MLX4_PROT_ETH &&
1019 check_duplicate_entry(dev, port, steer, index, qp->qpn))
1022 members_count = be32_to_cpu(mgm->members_count) & 0xffffff;
1023 for (loc = -1, i = 0; i < members_count; ++i)
1024 if ((be32_to_cpu(mgm->qp[i]) & MGM_QPN_MASK) == qp->qpn)
1028 mlx4_err(dev, "QP %06x not found in MGM\n", qp->qpn);
1034 mgm->members_count = cpu_to_be32(--members_count | (u32) prot << 30);
1035 mgm->qp[loc] = mgm->qp[i - 1];
1038 if (prot == MLX4_PROT_ETH)
1039 removed_entry = can_remove_steering_entry(dev, port, steer,
1041 if (i != 1 && (prot != MLX4_PROT_ETH || !removed_entry)) {
1042 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1046 /* We are going to delete the entry, members count should be 0 */
1047 mgm->members_count = cpu_to_be32((u32) prot << 30);
1050 /* Remove entry from MGM */
1051 int amgm_index = be32_to_cpu(mgm->next_gid_index) >> 6;
1053 err = mlx4_READ_ENTRY(dev, amgm_index, mailbox);
1057 memset(mgm->gid, 0, 16);
1059 err = mlx4_WRITE_ENTRY(dev, index, mailbox);
1064 if (amgm_index < dev->caps.num_mgms)
1065 mlx4_warn(dev, "MGM entry %d had AMGM index %d < %d",
1066 index, amgm_index, dev->caps.num_mgms);
1068 mlx4_bitmap_free(&priv->mcg_table.bitmap,
1069 amgm_index - dev->caps.num_mgms);
1072 /* Remove entry from AMGM */
1073 int cur_next_index = be32_to_cpu(mgm->next_gid_index) >> 6;
1074 err = mlx4_READ_ENTRY(dev, prev, mailbox);
1078 mgm->next_gid_index = cpu_to_be32(cur_next_index << 6);
1080 err = mlx4_WRITE_ENTRY(dev, prev, mailbox);
1084 if (index < dev->caps.num_mgms)
1085 mlx4_warn(dev, "entry %d had next AMGM index %d < %d",
1086 prev, index, dev->caps.num_mgms);
1088 mlx4_bitmap_free(&priv->mcg_table.bitmap,
1089 index - dev->caps.num_mgms);
1093 mutex_unlock(&priv->mcg_table.mutex);
1095 mlx4_free_cmd_mailbox(dev, mailbox);
1099 static int mlx4_QP_ATTACH(struct mlx4_dev *dev, struct mlx4_qp *qp,
1100 u8 gid[16], u8 attach, u8 block_loopback,
1101 enum mlx4_protocol prot)
1103 struct mlx4_cmd_mailbox *mailbox;
1107 if (!mlx4_is_mfunc(dev))
1110 mailbox = mlx4_alloc_cmd_mailbox(dev);
1111 if (IS_ERR(mailbox))
1112 return PTR_ERR(mailbox);
1114 memcpy(mailbox->buf, gid, 16);
1116 qpn |= (prot << 28);
1117 if (attach && block_loopback)
1120 err = mlx4_cmd(dev, mailbox->dma, qpn, attach,
1121 MLX4_CMD_QP_ATTACH, MLX4_CMD_TIME_CLASS_A,
1124 mlx4_free_cmd_mailbox(dev, mailbox);
1128 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1129 u8 gid[16], u8 port,
1130 int block_mcast_loopback,
1131 enum mlx4_protocol prot, u64 *reg_id)
1133 struct mlx4_spec_list spec = { {NULL} };
1134 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
1136 struct mlx4_net_trans_rule rule = {
1137 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1139 .promisc_mode = MLX4_FS_PROMISC_NONE,
1140 .priority = MLX4_DOMAIN_NIC,
1143 rule.allow_loopback = !block_mcast_loopback;
1146 INIT_LIST_HEAD(&rule.list);
1150 spec.id = MLX4_NET_TRANS_RULE_ID_ETH;
1151 memcpy(spec.eth.dst_mac, &gid[10], ETH_ALEN);
1152 memcpy(spec.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
1155 case MLX4_PROT_IB_IPV6:
1156 spec.id = MLX4_NET_TRANS_RULE_ID_IB;
1157 memcpy(spec.ib.dst_gid, gid, 16);
1158 memset(&spec.ib.dst_gid_msk, 0xff, 16);
1163 list_add_tail(&spec.list, &rule.list);
1165 return mlx4_flow_attach(dev, &rule, reg_id);
1168 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1169 u8 port, int block_mcast_loopback,
1170 enum mlx4_protocol prot, u64 *reg_id)
1172 switch (dev->caps.steering_mode) {
1173 case MLX4_STEERING_MODE_A0:
1174 if (prot == MLX4_PROT_ETH)
1177 case MLX4_STEERING_MODE_B0:
1178 if (prot == MLX4_PROT_ETH)
1179 gid[7] |= (MLX4_MC_STEER << 1);
1181 if (mlx4_is_mfunc(dev))
1182 return mlx4_QP_ATTACH(dev, qp, gid, 1,
1183 block_mcast_loopback, prot);
1184 return mlx4_qp_attach_common(dev, qp, gid,
1185 block_mcast_loopback, prot,
1188 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1189 return mlx4_trans_to_dmfs_attach(dev, qp, gid, port,
1190 block_mcast_loopback,
1196 EXPORT_SYMBOL_GPL(mlx4_multicast_attach);
1198 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1199 enum mlx4_protocol prot, u64 reg_id)
1201 switch (dev->caps.steering_mode) {
1202 case MLX4_STEERING_MODE_A0:
1203 if (prot == MLX4_PROT_ETH)
1206 case MLX4_STEERING_MODE_B0:
1207 if (prot == MLX4_PROT_ETH)
1208 gid[7] |= (MLX4_MC_STEER << 1);
1210 if (mlx4_is_mfunc(dev))
1211 return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot);
1213 return mlx4_qp_detach_common(dev, qp, gid, prot,
1216 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1217 return mlx4_flow_detach(dev, reg_id);
1223 EXPORT_SYMBOL_GPL(mlx4_multicast_detach);
1225 int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port,
1226 u32 qpn, enum mlx4_net_trans_promisc_mode mode)
1228 struct mlx4_net_trans_rule rule;
1232 case MLX4_FS_PROMISC_UPLINK:
1233 case MLX4_FS_PROMISC_FUNCTION_PORT:
1234 regid_p = &dev->regid_promisc_array[port];
1236 case MLX4_FS_PROMISC_ALL_MULTI:
1237 regid_p = &dev->regid_allmulti_array[port];
1246 rule.promisc_mode = mode;
1249 INIT_LIST_HEAD(&rule.list);
1250 mlx4_err(dev, "going promisc on %x\n", port);
1252 return mlx4_flow_attach(dev, &rule, regid_p);
1254 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_add);
1256 int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
1257 enum mlx4_net_trans_promisc_mode mode)
1263 case MLX4_FS_PROMISC_UPLINK:
1264 case MLX4_FS_PROMISC_FUNCTION_PORT:
1265 regid_p = &dev->regid_promisc_array[port];
1267 case MLX4_FS_PROMISC_ALL_MULTI:
1268 regid_p = &dev->regid_allmulti_array[port];
1277 ret = mlx4_flow_detach(dev, *regid_p);
1283 EXPORT_SYMBOL_GPL(mlx4_flow_steer_promisc_remove);
1285 int mlx4_unicast_attach(struct mlx4_dev *dev,
1286 struct mlx4_qp *qp, u8 gid[16],
1287 int block_mcast_loopback, enum mlx4_protocol prot)
1289 if (prot == MLX4_PROT_ETH)
1290 gid[7] |= (MLX4_UC_STEER << 1);
1292 if (mlx4_is_mfunc(dev))
1293 return mlx4_QP_ATTACH(dev, qp, gid, 1,
1294 block_mcast_loopback, prot);
1296 return mlx4_qp_attach_common(dev, qp, gid, block_mcast_loopback,
1297 prot, MLX4_UC_STEER);
1299 EXPORT_SYMBOL_GPL(mlx4_unicast_attach);
1301 int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1302 u8 gid[16], enum mlx4_protocol prot)
1304 if (prot == MLX4_PROT_ETH)
1305 gid[7] |= (MLX4_UC_STEER << 1);
1307 if (mlx4_is_mfunc(dev))
1308 return mlx4_QP_ATTACH(dev, qp, gid, 0, 0, prot);
1310 return mlx4_qp_detach_common(dev, qp, gid, prot, MLX4_UC_STEER);
1312 EXPORT_SYMBOL_GPL(mlx4_unicast_detach);
1314 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1315 struct mlx4_vhcr *vhcr,
1316 struct mlx4_cmd_mailbox *inbox,
1317 struct mlx4_cmd_mailbox *outbox,
1318 struct mlx4_cmd_info *cmd)
1320 u32 qpn = (u32) vhcr->in_param & 0xffffffff;
1321 u8 port = vhcr->in_param >> 62;
1322 enum mlx4_steer_type steer = vhcr->in_modifier;
1324 /* Promiscuous unicast is not allowed in mfunc */
1325 if (mlx4_is_mfunc(dev) && steer == MLX4_UC_STEER)
1328 if (vhcr->op_modifier)
1329 return add_promisc_qp(dev, port, steer, qpn);
1331 return remove_promisc_qp(dev, port, steer, qpn);
1334 static int mlx4_PROMISC(struct mlx4_dev *dev, u32 qpn,
1335 enum mlx4_steer_type steer, u8 add, u8 port)
1337 return mlx4_cmd(dev, (u64) qpn | (u64) port << 62, (u32) steer, add,
1338 MLX4_CMD_PROMISC, MLX4_CMD_TIME_CLASS_A,
1342 int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port)
1344 if (mlx4_is_mfunc(dev))
1345 return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 1, port);
1347 return add_promisc_qp(dev, port, MLX4_MC_STEER, qpn);
1349 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_add);
1351 int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port)
1353 if (mlx4_is_mfunc(dev))
1354 return mlx4_PROMISC(dev, qpn, MLX4_MC_STEER, 0, port);
1356 return remove_promisc_qp(dev, port, MLX4_MC_STEER, qpn);
1358 EXPORT_SYMBOL_GPL(mlx4_multicast_promisc_remove);
1360 int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port)
1362 if (mlx4_is_mfunc(dev))
1363 return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 1, port);
1365 return add_promisc_qp(dev, port, MLX4_UC_STEER, qpn);
1367 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_add);
1369 int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port)
1371 if (mlx4_is_mfunc(dev))
1372 return mlx4_PROMISC(dev, qpn, MLX4_UC_STEER, 0, port);
1374 return remove_promisc_qp(dev, port, MLX4_UC_STEER, qpn);
1376 EXPORT_SYMBOL_GPL(mlx4_unicast_promisc_remove);
1378 int mlx4_init_mcg_table(struct mlx4_dev *dev)
1380 struct mlx4_priv *priv = mlx4_priv(dev);
1383 /* No need for mcg_table when fw managed the mcg table*/
1384 if (dev->caps.steering_mode ==
1385 MLX4_STEERING_MODE_DEVICE_MANAGED)
1387 err = mlx4_bitmap_init(&priv->mcg_table.bitmap, dev->caps.num_amgms,
1388 dev->caps.num_amgms - 1, 0, 0);
1392 mutex_init(&priv->mcg_table.mutex);
1397 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev)
1399 if (dev->caps.steering_mode !=
1400 MLX4_STEERING_MODE_DEVICE_MANAGED)
1401 mlx4_bitmap_cleanup(&mlx4_priv(dev)->mcg_table.bitmap);