2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/mutex.h>
41 #include <linux/radix-tree.h>
42 #include <linux/rbtree.h>
43 #include <linux/timer.h>
44 #include <linux/semaphore.h>
45 #include <linux/workqueue.h>
46 #include <linux/interrupt.h>
47 #include <linux/spinlock.h>
48 #include <net/devlink.h>
49 #include <linux/rwsem.h>
51 #include <linux/mlx4/device.h>
52 #include <linux/mlx4/driver.h>
53 #include <linux/mlx4/doorbell.h>
54 #include <linux/mlx4/cmd.h>
57 #define DRV_NAME "mlx4_core"
58 #define PFX DRV_NAME ": "
59 #define DRV_VERSION "4.0-0"
61 #define MLX4_FS_UDP_UC_EN (1 << 1)
62 #define MLX4_FS_TCP_UC_EN (1 << 2)
63 #define MLX4_FS_NUM_OF_L2_ADDR 8
64 #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
65 #define MLX4_FS_NUM_MCG (1 << 17)
67 #define INIT_HCA_TPT_MW_ENABLE (1 << 7)
69 #define MLX4_QUERY_IF_STAT_RESET BIT(31)
72 MLX4_HCR_BASE = 0x80680,
73 MLX4_HCR_SIZE = 0x0001c,
74 MLX4_CLR_INT_SIZE = 0x00008,
75 MLX4_SLAVE_COMM_BASE = 0x0,
76 MLX4_COMM_PAGESIZE = 0x1000,
77 MLX4_CLOCK_SIZE = 0x00008,
78 MLX4_COMM_CHAN_CAPS = 0x8,
79 MLX4_COMM_CHAN_FLAGS = 0xc
83 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
84 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
85 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
86 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
87 MLX4_MTT_ENTRY_PER_SEG = 8,
91 MLX4_NUM_PDS = 1 << 15
95 MLX4_CMPT_TYPE_QP = 0,
96 MLX4_CMPT_TYPE_SRQ = 1,
97 MLX4_CMPT_TYPE_CQ = 2,
98 MLX4_CMPT_TYPE_EQ = 3,
103 MLX4_CMPT_SHIFT = 24,
104 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
107 enum mlx4_mpt_state {
108 MLX4_MPT_DISABLED = 0,
113 #define MLX4_COMM_TIME 10000
114 #define MLX4_COMM_OFFLINE_TIME_OUT 30000
115 #define MLX4_COMM_CMD_NA_OP 0x0
123 MLX4_COMM_CMD_VHCR_EN,
124 MLX4_COMM_CMD_VHCR_POST,
125 MLX4_COMM_CMD_FLR = 254
129 MLX4_VF_SMI_DISABLED,
133 /*The flag indicates that the slave should delay the RESET cmd*/
134 #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
135 /*indicates how many retries will be done if we are in the middle of FLR*/
136 #define NUM_OF_RESET_RETRIES 10
137 #define SLEEP_TIME_IN_RESET (2 * 1000)
151 MLX4_NUM_OF_RESOURCE_TYPE
154 enum mlx4_alloc_mode {
156 RES_OP_RESERVE_AND_MAP,
160 enum mlx4_res_tracker_free_type {
162 RES_TR_FREE_SLAVES_ONLY,
163 RES_TR_FREE_STRUCTS_ONLY,
167 *Virtual HCR structures.
168 * mlx4_vhcr is the sw representation, in machine endianness
170 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
171 * to FW to go through communication channel.
172 * It is big endian, and has the same structure as the physical HCR
173 * used by command interface
186 struct mlx4_vhcr_cmd {
198 struct mlx4_cmd_info {
203 bool encode_slave_id;
204 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
205 struct mlx4_cmd_mailbox *inbox);
206 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
207 struct mlx4_cmd_mailbox *inbox,
208 struct mlx4_cmd_mailbox *outbox,
209 struct mlx4_cmd_info *cmd);
212 #ifdef CONFIG_MLX4_DEBUG
213 extern int mlx4_debug_level;
214 #else /* CONFIG_MLX4_DEBUG */
215 #define mlx4_debug_level (0)
216 #endif /* CONFIG_MLX4_DEBUG */
218 #define mlx4_dbg(mdev, format, ...) \
220 if (mlx4_debug_level) \
221 dev_printk(KERN_DEBUG, \
222 &(mdev)->persist->pdev->dev, format, \
226 #define mlx4_err(mdev, format, ...) \
227 dev_err(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
228 #define mlx4_info(mdev, format, ...) \
229 dev_info(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
230 #define mlx4_warn(mdev, format, ...) \
231 dev_warn(&(mdev)->persist->pdev->dev, format, ##__VA_ARGS__)
233 extern int log_mtts_per_seg;
234 extern int mlx4_internal_err_reset;
236 #define MLX4_MAX_NUM_SLAVES (min(MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF, \
238 #define ALL_SLAVES 0xff
249 unsigned long *table;
253 unsigned long **bits;
254 unsigned int *num_free;
261 struct mlx4_icm_table {
269 struct mlx4_icm **icm;
272 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
273 #define MLX4_MPT_FLAG_FREE (0x3UL << 28)
274 #define MLX4_MPT_FLAG_MIO (1 << 17)
275 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
276 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
277 #define MLX4_MPT_FLAG_REGION (1 << 8)
279 #define MLX4_MPT_PD_MASK (0x1FFFFUL)
280 #define MLX4_MPT_PD_VF_MASK (0xFE0000UL)
281 #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
282 #define MLX4_MPT_PD_FLAG_RAE (1 << 28)
283 #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
285 #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
287 #define MLX4_MPT_STATUS_SW 0xF0
288 #define MLX4_MPT_STATUS_HW 0x00
290 #define MLX4_CQE_SIZE_MASK_STRIDE 0x3
291 #define MLX4_EQE_SIZE_MASK_STRIDE 0x30
293 #define MLX4_EQ_ASYNC 0
294 #define MLX4_EQ_TO_CQ_VECTOR(vector) ((vector) - \
295 !!((int)(vector) >= MLX4_EQ_ASYNC))
296 #define MLX4_CQ_TO_EQ_VECTOR(vector) ((vector) + \
297 !!((int)(vector) >= MLX4_EQ_ASYNC))
300 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
302 struct mlx4_mpt_entry {
316 __be32 first_byte_offset;
320 * Must be packed because start is 64 bits but only aligned to 32 bits.
322 struct mlx4_eq_context {
336 __be32 mtt_base_addr_l;
338 __be32 consumer_index;
339 __be32 producer_index;
343 struct mlx4_cq_context {
347 __be32 logsize_usrpage;
355 __be32 mtt_base_addr_l;
356 __be32 last_notified_index;
357 __be32 solicit_producer_index;
358 __be32 consumer_index;
359 __be32 producer_index;
364 struct mlx4_srq_context {
365 __be32 state_logsize_srqn;
369 __be32 pg_offset_cqn;
374 __be32 mtt_base_addr_l;
376 __be16 limit_watermark;
384 struct mlx4_eq_tasklet {
385 struct list_head list;
386 struct list_head process_list;
387 struct tasklet_struct task;
388 /* lock on completion tasklet list */
393 struct mlx4_dev *dev;
394 void __iomem *doorbell;
400 struct mlx4_buf_list *page_list;
402 struct mlx4_eq_tasklet tasklet_ctx;
403 struct mlx4_active_ports actv_ports;
405 cpumask_var_t affinity_mask;
408 struct mlx4_slave_eqe {
414 struct mlx4_slave_event_eq_info {
419 struct mlx4_profile {
434 struct mlx4_icm *fw_icm;
435 struct mlx4_icm *aux_icm;
450 MLX4_MCAST_CONFIG = 0,
451 MLX4_MCAST_DISABLE = 1,
452 MLX4_MCAST_ENABLE = 2,
455 #define VLAN_FLTR_SIZE 128
457 struct mlx4_vlan_fltr {
458 __be32 entry[VLAN_FLTR_SIZE];
461 struct mlx4_mcast_entry {
462 struct list_head list;
466 struct mlx4_promisc_qp {
467 struct list_head list;
471 struct mlx4_steer_index {
472 struct list_head list;
474 struct list_head duplicates;
477 #define MLX4_EVENT_TYPES_NUM 64
479 struct mlx4_slave_state {
485 bool vst_qinq_supported;
488 u16 user_mtu[MLX4_MAX_PORTS + 1];
489 u16 mtu[MLX4_MAX_PORTS + 1];
490 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
491 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
492 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
493 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
494 /* event type to eq number lookup */
495 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
499 /*initialized via the kzalloc*/
500 u8 is_slave_going_down;
502 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
505 #define MLX4_VGT 4095
508 struct mlx4_vport_state {
520 struct mlx4_vf_admin_state {
521 struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1];
522 u8 enable_smi[MLX4_MAX_PORTS + 1];
525 struct mlx4_vport_oper_state {
526 struct mlx4_vport_state state;
531 struct mlx4_vf_oper_state {
532 struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1];
533 u8 smi_enabled[MLX4_MAX_PORTS + 1];
538 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
541 struct resource_allocator {
542 spinlock_t alloc_lock; /* protect quotas */
545 int res_port_rsvd[MLX4_MAX_PORTS];
549 int res_port_free[MLX4_MAX_PORTS];
556 struct mlx4_resource_tracker {
558 /* tree for each resources */
559 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
560 /* num_of_slave's lists, one per slave */
561 struct slave_list *slave_list;
562 struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE];
565 #define SLAVE_EVENT_EQ_SIZE 128
566 struct mlx4_slave_event_eq {
570 spinlock_t event_lock;
571 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
574 struct mlx4_qos_manager {
576 DECLARE_BITMAP(priority_bm, MLX4_NUM_UP);
579 struct mlx4_master_qp0_state {
580 int proxy_qp0_active;
585 struct mlx4_mfunc_master_ctx {
586 struct mlx4_slave_state *slave_state;
587 struct mlx4_vf_admin_state *vf_admin;
588 struct mlx4_vf_oper_state *vf_oper;
589 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
590 int init_port_ref[MLX4_MAX_PORTS + 1];
591 u16 max_mtu[MLX4_MAX_PORTS + 1];
592 u16 max_user_mtu[MLX4_MAX_PORTS + 1];
595 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
596 struct mlx4_resource_tracker res_tracker;
597 struct workqueue_struct *comm_wq;
598 struct work_struct comm_work;
599 struct work_struct slave_event_work;
600 struct work_struct slave_flr_event_work;
601 spinlock_t slave_state_lock;
602 __be32 comm_arm_bit_vector[4];
603 struct mlx4_eqe cmd_eqe;
604 struct mlx4_slave_event_eq slave_eq;
605 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
606 struct mlx4_qos_manager qos_ctl[MLX4_MAX_PORTS + 1];
610 struct mlx4_comm __iomem *comm;
611 struct mlx4_vhcr_cmd *vhcr;
614 struct mlx4_mfunc_master_ctx master;
617 #define MGM_QPN_MASK 0x00FFFFFF
618 #define MGM_BLCK_LB_BIT 30
621 __be32 next_gid_index;
622 __be32 members_count;
625 __be32 qp[MLX4_MAX_QP_PER_MGM];
629 struct pci_pool *pool;
631 struct mutex slave_cmd_mutex;
632 struct semaphore poll_sem;
633 struct semaphore event_sem;
634 struct rw_semaphore switch_sem;
636 spinlock_t context_lock;
638 struct mlx4_cmd_context *context;
647 MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0,
648 MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1,
649 MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2,
651 struct mlx4_vf_immed_vlan_work {
652 struct work_struct work;
653 struct mlx4_priv *priv;
667 struct mlx4_uar_table {
668 struct mlx4_bitmap bitmap;
671 struct mlx4_mr_table {
672 struct mlx4_bitmap mpt_bitmap;
673 struct mlx4_buddy mtt_buddy;
676 struct mlx4_icm_table mtt_table;
677 struct mlx4_icm_table dmpt_table;
680 struct mlx4_cq_table {
681 struct mlx4_bitmap bitmap;
683 struct radix_tree_root tree;
684 struct mlx4_icm_table table;
685 struct mlx4_icm_table cmpt_table;
688 struct mlx4_eq_table {
689 struct mlx4_bitmap bitmap;
691 void __iomem *clr_int;
692 void __iomem **uar_map;
695 struct mlx4_icm_table table;
696 struct mlx4_icm_table cmpt_table;
701 struct mlx4_srq_table {
702 struct mlx4_bitmap bitmap;
704 struct radix_tree_root tree;
705 struct mlx4_icm_table table;
706 struct mlx4_icm_table cmpt_table;
709 enum mlx4_qp_table_zones {
710 MLX4_QP_TABLE_ZONE_GENERAL,
711 MLX4_QP_TABLE_ZONE_RSS,
712 MLX4_QP_TABLE_ZONE_RAW_ETH,
713 MLX4_QP_TABLE_ZONE_NUM
716 struct mlx4_qp_table {
717 struct mlx4_bitmap *bitmap_gen;
718 struct mlx4_zone_allocator *zones;
719 u32 zones_uids[MLX4_QP_TABLE_ZONE_NUM];
723 struct mlx4_icm_table qp_table;
724 struct mlx4_icm_table auxc_table;
725 struct mlx4_icm_table altc_table;
726 struct mlx4_icm_table rdmarc_table;
727 struct mlx4_icm_table cmpt_table;
730 struct mlx4_mcg_table {
732 struct mlx4_bitmap bitmap;
733 struct mlx4_icm_table table;
736 struct mlx4_catas_err {
738 struct timer_list timer;
739 struct list_head list;
742 #define MLX4_MAX_MAC_NUM 128
743 #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
745 struct mlx4_mac_table {
746 __be64 entries[MLX4_MAX_MAC_NUM];
747 int refs[MLX4_MAX_MAC_NUM];
748 bool is_dup[MLX4_MAX_MAC_NUM];
754 #define MLX4_ROCE_GID_ENTRY_SIZE 16
756 struct mlx4_roce_gid_entry {
757 u8 raw[MLX4_ROCE_GID_ENTRY_SIZE];
760 struct mlx4_roce_gid_table {
761 struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS];
765 #define MLX4_MAX_VLAN_NUM 128
766 #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
768 struct mlx4_vlan_table {
769 __be32 entries[MLX4_MAX_VLAN_NUM];
770 int refs[MLX4_MAX_VLAN_NUM];
771 int is_dup[MLX4_MAX_VLAN_NUM];
777 #define SET_PORT_GEN_ALL_VALID (MLX4_FLAG_V_MTU_MASK | \
778 MLX4_FLAG_V_PPRX_MASK | \
779 MLX4_FLAG_V_PPTX_MASK)
780 #define SET_PORT_PROMISC_SHIFT 31
781 #define SET_PORT_MC_PROMISC_SHIFT 30
784 MCAST_DIRECT_ONLY = 0,
790 struct mlx4_set_port_general_context {
812 struct mlx4_set_port_rqp_calc_context {
830 struct mlx4_port_info {
831 struct mlx4_dev *dev;
834 struct device_attribute port_attr;
835 enum mlx4_port_type tmp_type;
836 char dev_mtu_name[16];
837 struct device_attribute port_mtu_attr;
838 struct mlx4_mac_table mac_table;
839 struct mlx4_vlan_table vlan_table;
840 struct mlx4_roce_gid_table gid_table;
842 struct cpu_rmap *rmap;
843 struct devlink_port devlink_port;
847 struct mlx4_dev *dev;
848 u8 do_sense_port[MLX4_MAX_PORTS + 1];
849 u8 sense_allowed[MLX4_MAX_PORTS + 1];
850 struct delayed_work sense_poll;
853 struct mlx4_msix_ctl {
854 DECLARE_BITMAP(pool_bm, MAX_MSIX);
855 struct mutex pool_lock;
859 struct list_head promisc_qps[MLX4_NUM_STEERS];
860 struct list_head steer_entries[MLX4_NUM_STEERS];
864 MLX4_PCI_DEV_IS_VF = 1 << 0,
865 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
876 struct list_head dev_list;
877 struct list_head ctx_list;
883 struct list_head pgdir_list;
884 struct mutex pgdir_mutex;
888 struct mlx4_mfunc mfunc;
890 struct mlx4_bitmap pd_bitmap;
891 struct mlx4_bitmap xrcd_bitmap;
892 struct mlx4_uar_table uar_table;
893 struct mlx4_mr_table mr_table;
894 struct mlx4_cq_table cq_table;
895 struct mlx4_eq_table eq_table;
896 struct mlx4_srq_table srq_table;
897 struct mlx4_qp_table qp_table;
898 struct mlx4_mcg_table mcg_table;
899 struct mlx4_bitmap counters_bitmap;
900 int def_counter[MLX4_MAX_PORTS];
902 struct mlx4_catas_err catas_err;
904 void __iomem *clr_base;
906 struct mlx4_uar driver_uar;
908 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
909 struct mlx4_sense sense;
910 struct mutex port_mutex;
911 struct mlx4_msix_ctl msix_ctl;
912 struct mlx4_steer *steer;
913 struct list_head bf_list;
914 struct mutex bf_mutex;
915 struct io_mapping *bf_mapping;
916 void __iomem *clock_mapping;
919 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
920 struct mlx4_port_map v2p; /* cached port mapping configuration */
921 struct mutex bond_mutex; /* for bond mode */
922 __be64 slave_node_guids[MLX4_MFUNC_MAX];
924 atomic_t opreq_count;
925 struct work_struct opreq_task;
928 static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
930 return container_of(dev, struct mlx4_priv, dev);
933 #define MLX4_SENSE_RANGE (HZ * 3)
935 extern struct workqueue_struct *mlx4_wq;
937 u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
938 void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr);
939 u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt,
940 int align, u32 skip_mask);
941 void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt,
943 u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
944 int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
945 u32 reserved_bot, u32 resetrved_top);
946 void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
948 int mlx4_reset(struct mlx4_dev *dev);
950 int mlx4_alloc_eq_table(struct mlx4_dev *dev);
951 void mlx4_free_eq_table(struct mlx4_dev *dev);
953 int mlx4_init_pd_table(struct mlx4_dev *dev);
954 int mlx4_init_xrcd_table(struct mlx4_dev *dev);
955 int mlx4_init_uar_table(struct mlx4_dev *dev);
956 int mlx4_init_mr_table(struct mlx4_dev *dev);
957 int mlx4_init_eq_table(struct mlx4_dev *dev);
958 int mlx4_init_cq_table(struct mlx4_dev *dev);
959 int mlx4_init_qp_table(struct mlx4_dev *dev);
960 int mlx4_init_srq_table(struct mlx4_dev *dev);
961 int mlx4_init_mcg_table(struct mlx4_dev *dev);
963 void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
964 void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
965 void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
966 void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
967 void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
968 void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
969 void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
970 void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
971 void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
972 int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
973 void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
974 int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
975 void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
976 int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
977 void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
978 int __mlx4_mpt_reserve(struct mlx4_dev *dev);
979 void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
980 int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index);
981 void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
982 u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
983 void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
985 int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
986 struct mlx4_vhcr *vhcr,
987 struct mlx4_cmd_mailbox *inbox,
988 struct mlx4_cmd_mailbox *outbox,
989 struct mlx4_cmd_info *cmd);
990 int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
991 struct mlx4_vhcr *vhcr,
992 struct mlx4_cmd_mailbox *inbox,
993 struct mlx4_cmd_mailbox *outbox,
994 struct mlx4_cmd_info *cmd);
995 int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
996 struct mlx4_vhcr *vhcr,
997 struct mlx4_cmd_mailbox *inbox,
998 struct mlx4_cmd_mailbox *outbox,
999 struct mlx4_cmd_info *cmd);
1000 int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
1001 struct mlx4_vhcr *vhcr,
1002 struct mlx4_cmd_mailbox *inbox,
1003 struct mlx4_cmd_mailbox *outbox,
1004 struct mlx4_cmd_info *cmd);
1005 int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
1006 struct mlx4_vhcr *vhcr,
1007 struct mlx4_cmd_mailbox *inbox,
1008 struct mlx4_cmd_mailbox *outbox,
1009 struct mlx4_cmd_info *cmd);
1010 int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1011 struct mlx4_vhcr *vhcr,
1012 struct mlx4_cmd_mailbox *inbox,
1013 struct mlx4_cmd_mailbox *outbox,
1014 struct mlx4_cmd_info *cmd);
1015 int mlx4_CONFIG_DEV_wrapper(struct mlx4_dev *dev, int slave,
1016 struct mlx4_vhcr *vhcr,
1017 struct mlx4_cmd_mailbox *inbox,
1018 struct mlx4_cmd_mailbox *outbox,
1019 struct mlx4_cmd_info *cmd);
1020 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
1021 struct mlx4_vhcr *vhcr,
1022 struct mlx4_cmd_mailbox *inbox,
1023 struct mlx4_cmd_mailbox *outbox,
1024 struct mlx4_cmd_info *cmd);
1025 int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
1026 int *base, u8 flags);
1027 void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
1028 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1029 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
1030 int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
1031 int start_index, int npages, u64 *page_list);
1032 int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
1033 void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
1034 int mlx4_calc_vf_counters(struct mlx4_dev *dev, int slave, int port,
1035 struct mlx4_counter *data);
1036 int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
1037 void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
1039 void mlx4_start_catas_poll(struct mlx4_dev *dev);
1040 void mlx4_stop_catas_poll(struct mlx4_dev *dev);
1041 int mlx4_catas_init(struct mlx4_dev *dev);
1042 void mlx4_catas_end(struct mlx4_dev *dev);
1043 int mlx4_restart_one(struct pci_dev *pdev);
1044 int mlx4_register_device(struct mlx4_dev *dev);
1045 void mlx4_unregister_device(struct mlx4_dev *dev);
1046 void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
1047 unsigned long param);
1049 struct mlx4_dev_cap;
1050 struct mlx4_init_hca_param;
1052 u64 mlx4_make_profile(struct mlx4_dev *dev,
1053 struct mlx4_profile *request,
1054 struct mlx4_dev_cap *dev_cap,
1055 struct mlx4_init_hca_param *init_hca);
1056 void mlx4_master_comm_channel(struct work_struct *work);
1057 void mlx4_gen_slave_eqe(struct work_struct *work);
1058 void mlx4_master_handle_slave_flr(struct work_struct *work);
1060 int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
1061 struct mlx4_vhcr *vhcr,
1062 struct mlx4_cmd_mailbox *inbox,
1063 struct mlx4_cmd_mailbox *outbox,
1064 struct mlx4_cmd_info *cmd);
1065 int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
1066 struct mlx4_vhcr *vhcr,
1067 struct mlx4_cmd_mailbox *inbox,
1068 struct mlx4_cmd_mailbox *outbox,
1069 struct mlx4_cmd_info *cmd);
1070 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
1071 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
1072 struct mlx4_cmd_mailbox *outbox,
1073 struct mlx4_cmd_info *cmd);
1074 int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
1075 struct mlx4_vhcr *vhcr,
1076 struct mlx4_cmd_mailbox *inbox,
1077 struct mlx4_cmd_mailbox *outbox,
1078 struct mlx4_cmd_info *cmd);
1079 int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
1080 struct mlx4_vhcr *vhcr,
1081 struct mlx4_cmd_mailbox *inbox,
1082 struct mlx4_cmd_mailbox *outbox,
1083 struct mlx4_cmd_info *cmd);
1084 int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
1085 struct mlx4_vhcr *vhcr,
1086 struct mlx4_cmd_mailbox *inbox,
1087 struct mlx4_cmd_mailbox *outbox,
1088 struct mlx4_cmd_info *cmd);
1089 int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1090 struct mlx4_vhcr *vhcr,
1091 struct mlx4_cmd_mailbox *inbox,
1092 struct mlx4_cmd_mailbox *outbox,
1093 struct mlx4_cmd_info *cmd);
1094 int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
1095 struct mlx4_vhcr *vhcr,
1096 struct mlx4_cmd_mailbox *inbox,
1097 struct mlx4_cmd_mailbox *outbox,
1098 struct mlx4_cmd_info *cmd);
1099 int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1100 struct mlx4_vhcr *vhcr,
1101 struct mlx4_cmd_mailbox *inbox,
1102 struct mlx4_cmd_mailbox *outbox,
1103 struct mlx4_cmd_info *cmd);
1104 int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1105 struct mlx4_vhcr *vhcr,
1106 struct mlx4_cmd_mailbox *inbox,
1107 struct mlx4_cmd_mailbox *outbox,
1108 struct mlx4_cmd_info *cmd);
1109 int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1110 struct mlx4_vhcr *vhcr,
1111 struct mlx4_cmd_mailbox *inbox,
1112 struct mlx4_cmd_mailbox *outbox,
1113 struct mlx4_cmd_info *cmd);
1114 int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1115 struct mlx4_vhcr *vhcr,
1116 struct mlx4_cmd_mailbox *inbox,
1117 struct mlx4_cmd_mailbox *outbox,
1118 struct mlx4_cmd_info *cmd);
1119 int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1120 struct mlx4_vhcr *vhcr,
1121 struct mlx4_cmd_mailbox *inbox,
1122 struct mlx4_cmd_mailbox *outbox,
1123 struct mlx4_cmd_info *cmd);
1124 int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1125 struct mlx4_vhcr *vhcr,
1126 struct mlx4_cmd_mailbox *inbox,
1127 struct mlx4_cmd_mailbox *outbox,
1128 struct mlx4_cmd_info *cmd);
1129 int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1130 struct mlx4_vhcr *vhcr,
1131 struct mlx4_cmd_mailbox *inbox,
1132 struct mlx4_cmd_mailbox *outbox,
1133 struct mlx4_cmd_info *cmd);
1134 int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1135 struct mlx4_vhcr *vhcr,
1136 struct mlx4_cmd_mailbox *inbox,
1137 struct mlx4_cmd_mailbox *outbox,
1138 struct mlx4_cmd_info *cmd);
1139 int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1140 struct mlx4_vhcr *vhcr,
1141 struct mlx4_cmd_mailbox *inbox,
1142 struct mlx4_cmd_mailbox *outbox,
1143 struct mlx4_cmd_info *cmd);
1144 int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1145 struct mlx4_vhcr *vhcr,
1146 struct mlx4_cmd_mailbox *inbox,
1147 struct mlx4_cmd_mailbox *outbox,
1148 struct mlx4_cmd_info *cmd);
1149 int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1150 struct mlx4_vhcr *vhcr,
1151 struct mlx4_cmd_mailbox *inbox,
1152 struct mlx4_cmd_mailbox *outbox,
1153 struct mlx4_cmd_info *cmd);
1154 int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1155 struct mlx4_vhcr *vhcr,
1156 struct mlx4_cmd_mailbox *inbox,
1157 struct mlx4_cmd_mailbox *outbox,
1158 struct mlx4_cmd_info *cmd);
1159 int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1160 struct mlx4_vhcr *vhcr,
1161 struct mlx4_cmd_mailbox *inbox,
1162 struct mlx4_cmd_mailbox *outbox,
1163 struct mlx4_cmd_info *cmd);
1164 int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1165 struct mlx4_vhcr *vhcr,
1166 struct mlx4_cmd_mailbox *inbox,
1167 struct mlx4_cmd_mailbox *outbox,
1168 struct mlx4_cmd_info *cmd);
1169 int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1170 struct mlx4_vhcr *vhcr,
1171 struct mlx4_cmd_mailbox *inbox,
1172 struct mlx4_cmd_mailbox *outbox,
1173 struct mlx4_cmd_info *cmd);
1174 int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1175 struct mlx4_vhcr *vhcr,
1176 struct mlx4_cmd_mailbox *inbox,
1177 struct mlx4_cmd_mailbox *outbox,
1178 struct mlx4_cmd_info *cmd);
1179 int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1180 struct mlx4_vhcr *vhcr,
1181 struct mlx4_cmd_mailbox *inbox,
1182 struct mlx4_cmd_mailbox *outbox,
1183 struct mlx4_cmd_info *cmd);
1184 int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1185 struct mlx4_vhcr *vhcr,
1186 struct mlx4_cmd_mailbox *inbox,
1187 struct mlx4_cmd_mailbox *outbox,
1188 struct mlx4_cmd_info *cmd);
1189 int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1190 struct mlx4_vhcr *vhcr,
1191 struct mlx4_cmd_mailbox *inbox,
1192 struct mlx4_cmd_mailbox *outbox,
1193 struct mlx4_cmd_info *cmd);
1195 int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
1198 MLX4_CMD_CLEANUP_STRUCT = 1UL << 0,
1199 MLX4_CMD_CLEANUP_POOL = 1UL << 1,
1200 MLX4_CMD_CLEANUP_HCR = 1UL << 2,
1201 MLX4_CMD_CLEANUP_VHCR = 1UL << 3,
1202 MLX4_CMD_CLEANUP_ALL = (MLX4_CMD_CLEANUP_VHCR << 1) - 1
1205 int mlx4_cmd_init(struct mlx4_dev *dev);
1206 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask);
1207 int mlx4_multi_func_init(struct mlx4_dev *dev);
1208 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev);
1209 void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
1210 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1211 int mlx4_cmd_use_events(struct mlx4_dev *dev);
1212 void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1214 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1215 u16 op, unsigned long timeout);
1217 void mlx4_cq_tasklet_cb(unsigned long data);
1218 void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1219 void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1221 void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1223 void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1225 void mlx4_enter_error_state(struct mlx4_dev_persistent *persist);
1226 int mlx4_comm_internal_err(u32 slave_read);
1228 int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1229 enum mlx4_port_type *type);
1230 void mlx4_do_sense_ports(struct mlx4_dev *dev,
1231 enum mlx4_port_type *stype,
1232 enum mlx4_port_type *defaults);
1233 void mlx4_start_sense(struct mlx4_dev *dev);
1234 void mlx4_stop_sense(struct mlx4_dev *dev);
1235 void mlx4_sense_init(struct mlx4_dev *dev);
1236 int mlx4_check_port_params(struct mlx4_dev *dev,
1237 enum mlx4_port_type *port_type);
1238 int mlx4_change_port_types(struct mlx4_dev *dev,
1239 enum mlx4_port_type *port_types);
1241 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1242 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1243 void mlx4_init_roce_gid_table(struct mlx4_dev *dev,
1244 struct mlx4_roce_gid_table *table);
1245 void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan);
1246 int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
1247 int mlx4_bond_vlan_table(struct mlx4_dev *dev);
1248 int mlx4_unbond_vlan_table(struct mlx4_dev *dev);
1249 int mlx4_bond_mac_table(struct mlx4_dev *dev);
1250 int mlx4_unbond_mac_table(struct mlx4_dev *dev);
1252 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
1253 /* resource tracker functions*/
1254 int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1255 enum mlx4_resource resource_type,
1256 u64 resource_id, int *slave);
1257 void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1258 void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave);
1259 int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1261 void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1262 enum mlx4_res_tracker_free_type type);
1264 int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1265 struct mlx4_vhcr *vhcr,
1266 struct mlx4_cmd_mailbox *inbox,
1267 struct mlx4_cmd_mailbox *outbox,
1268 struct mlx4_cmd_info *cmd);
1269 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1270 struct mlx4_vhcr *vhcr,
1271 struct mlx4_cmd_mailbox *inbox,
1272 struct mlx4_cmd_mailbox *outbox,
1273 struct mlx4_cmd_info *cmd);
1274 int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1275 struct mlx4_vhcr *vhcr,
1276 struct mlx4_cmd_mailbox *inbox,
1277 struct mlx4_cmd_mailbox *outbox,
1278 struct mlx4_cmd_info *cmd);
1279 int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1280 struct mlx4_vhcr *vhcr,
1281 struct mlx4_cmd_mailbox *inbox,
1282 struct mlx4_cmd_mailbox *outbox,
1283 struct mlx4_cmd_info *cmd);
1284 int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1285 struct mlx4_vhcr *vhcr,
1286 struct mlx4_cmd_mailbox *inbox,
1287 struct mlx4_cmd_mailbox *outbox,
1288 struct mlx4_cmd_info *cmd);
1289 int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1290 struct mlx4_vhcr *vhcr,
1291 struct mlx4_cmd_mailbox *inbox,
1292 struct mlx4_cmd_mailbox *outbox,
1293 struct mlx4_cmd_info *cmd);
1294 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
1296 int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1297 int *gid_tbl_len, int *pkey_tbl_len);
1299 int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1300 struct mlx4_vhcr *vhcr,
1301 struct mlx4_cmd_mailbox *inbox,
1302 struct mlx4_cmd_mailbox *outbox,
1303 struct mlx4_cmd_info *cmd);
1305 int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave,
1306 struct mlx4_vhcr *vhcr,
1307 struct mlx4_cmd_mailbox *inbox,
1308 struct mlx4_cmd_mailbox *outbox,
1309 struct mlx4_cmd_info *cmd);
1311 int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1312 struct mlx4_vhcr *vhcr,
1313 struct mlx4_cmd_mailbox *inbox,
1314 struct mlx4_cmd_mailbox *outbox,
1315 struct mlx4_cmd_info *cmd);
1316 int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1317 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1318 int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1319 int block_mcast_loopback, enum mlx4_protocol prot,
1320 enum mlx4_steer_type steer);
1321 int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1322 u8 gid[16], u8 port,
1323 int block_mcast_loopback,
1324 enum mlx4_protocol prot, u64 *reg_id);
1325 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1326 struct mlx4_vhcr *vhcr,
1327 struct mlx4_cmd_mailbox *inbox,
1328 struct mlx4_cmd_mailbox *outbox,
1329 struct mlx4_cmd_info *cmd);
1330 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1331 struct mlx4_vhcr *vhcr,
1332 struct mlx4_cmd_mailbox *inbox,
1333 struct mlx4_cmd_mailbox *outbox,
1334 struct mlx4_cmd_info *cmd);
1335 int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1336 int port, void *buf);
1337 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1338 struct mlx4_vhcr *vhcr,
1339 struct mlx4_cmd_mailbox *inbox,
1340 struct mlx4_cmd_mailbox *outbox,
1341 struct mlx4_cmd_info *cmd);
1342 int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1343 struct mlx4_vhcr *vhcr,
1344 struct mlx4_cmd_mailbox *inbox,
1345 struct mlx4_cmd_mailbox *outbox,
1346 struct mlx4_cmd_info *cmd);
1347 int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1348 struct mlx4_vhcr *vhcr,
1349 struct mlx4_cmd_mailbox *inbox,
1350 struct mlx4_cmd_mailbox *outbox,
1351 struct mlx4_cmd_info *cmd);
1352 int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1353 struct mlx4_vhcr *vhcr,
1354 struct mlx4_cmd_mailbox *inbox,
1355 struct mlx4_cmd_mailbox *outbox,
1356 struct mlx4_cmd_info *cmd);
1357 int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1358 struct mlx4_vhcr *vhcr,
1359 struct mlx4_cmd_mailbox *inbox,
1360 struct mlx4_cmd_mailbox *outbox,
1361 struct mlx4_cmd_info *cmd);
1362 int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
1363 struct mlx4_vhcr *vhcr,
1364 struct mlx4_cmd_mailbox *inbox,
1365 struct mlx4_cmd_mailbox *outbox,
1366 struct mlx4_cmd_info *cmd);
1368 int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1369 int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1371 static inline void set_param_l(u64 *arg, u32 val)
1373 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
1376 static inline void set_param_h(u64 *arg, u32 val)
1378 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1381 static inline u32 get_param_l(u64 *arg)
1383 return (u32) (*arg & 0xffffffff);
1386 static inline u32 get_param_h(u64 *arg)
1388 return (u32)(*arg >> 32);
1391 static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1393 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1396 #define NOT_MASKED_PD_BITS 17
1398 void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work);
1400 void mlx4_init_quotas(struct mlx4_dev *dev);
1402 /* for VFs, replace zero MACs with randomly-generated MACs at driver start */
1403 void mlx4_replace_zero_macs(struct mlx4_dev *dev);
1404 int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port);
1405 /* Returns the VF index of slave */
1406 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave);
1407 int mlx4_config_mad_demux(struct mlx4_dev *dev);
1408 int mlx4_do_bond(struct mlx4_dev *dev, bool enable);
1409 int mlx4_bond_fs_rules(struct mlx4_dev *dev);
1410 int mlx4_unbond_fs_rules(struct mlx4_dev *dev);
1412 enum mlx4_zone_flags {
1413 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO = 1UL << 0,
1414 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO = 1UL << 1,
1415 MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO = 1UL << 2,
1416 MLX4_ZONE_USE_RR = 1UL << 3,
1419 enum mlx4_zone_alloc_flags {
1420 /* No two objects could overlap between zones. UID
1421 * could be left unused. If this flag is given and
1422 * two overlapped zones are used, an object will be free'd
1423 * from the smallest possible matching zone.
1425 MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP = 1UL << 0,
1428 struct mlx4_zone_allocator;
1430 /* Create a new zone allocator */
1431 struct mlx4_zone_allocator *mlx4_zone_allocator_create(enum mlx4_zone_alloc_flags flags);
1433 /* Attach a mlx4_bitmap <bitmap> of priority <priority> to the zone allocator
1434 * <zone_alloc>. Allocating an object from this zone adds an offset <offset>.
1435 * Similarly, when searching for an object to free, this offset it taken into
1436 * account. The use_rr mlx4_ib parameter for allocating objects from this <bitmap>
1437 * is given through the MLX4_ZONE_USE_RR flag in <flags>.
1438 * When an allocation fails, <zone_alloc> tries to allocate from other zones
1439 * according to the policy set by <flags>. <puid> is the unique identifier
1440 * received to this zone.
1442 int mlx4_zone_add_one(struct mlx4_zone_allocator *zone_alloc,
1443 struct mlx4_bitmap *bitmap,
1449 /* Remove bitmap indicated by <uid> from <zone_alloc> */
1450 int mlx4_zone_remove_one(struct mlx4_zone_allocator *zone_alloc, u32 uid);
1452 /* Delete the zone allocator <zone_alloc. This function doesn't destroy
1453 * the attached bitmaps.
1455 void mlx4_zone_allocator_destroy(struct mlx4_zone_allocator *zone_alloc);
1457 /* Allocate <count> objects with align <align> and skip_mask <skip_mask>
1458 * from the mlx4_bitmap whose uid is <uid>. The bitmap which we actually
1459 * allocated from is returned in <puid>. If the allocation fails, a negative
1460 * number is returned. Otherwise, the offset of the first object is returned.
1462 u32 mlx4_zone_alloc_entries(struct mlx4_zone_allocator *zones, u32 uid, int count,
1463 int align, u32 skip_mask, u32 *puid);
1465 /* Free <count> objects, start from <obj> of the uid <uid> from zone_allocator
1468 u32 mlx4_zone_free_entries(struct mlx4_zone_allocator *zones,
1469 u32 uid, u32 obj, u32 count);
1471 /* If <zones> was allocated with MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP, instead of
1472 * specifying the uid when freeing an object, zone allocator could figure it by
1473 * itself. Other parameters are similar to mlx4_zone_free.
1475 u32 mlx4_zone_free_entries_unique(struct mlx4_zone_allocator *zones, u32 obj, u32 count);
1477 /* Returns a pointer to mlx4_bitmap that was attached to <zones> with <uid> */
1478 struct mlx4_bitmap *mlx4_zone_get_bitmap(struct mlx4_zone_allocator *zones, u32 uid);