2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
37 #include <linux/bitops.h>
38 #include <linux/compiler.h>
39 #include <linux/list.h>
40 #include <linux/mutex.h>
41 #include <linux/netdevice.h>
42 #include <linux/if_vlan.h>
43 #include <linux/net_tstamp.h>
44 #ifdef CONFIG_MLX4_EN_DCB
45 #include <linux/dcbnl.h>
47 #include <linux/cpu_rmap.h>
48 #include <linux/ptp_clock_kernel.h>
50 #include <linux/mlx4/device.h>
51 #include <linux/mlx4/qp.h>
52 #include <linux/mlx4/cq.h>
53 #include <linux/mlx4/srq.h>
54 #include <linux/mlx4/doorbell.h>
55 #include <linux/mlx4/cmd.h>
58 #include "mlx4_stats.h"
60 #define DRV_NAME "mlx4_en"
61 #define DRV_VERSION "2.2-1"
62 #define DRV_RELDATE "Feb 2014"
64 #define MLX4_EN_MSG_LEVEL (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
71 #define MLX4_EN_PAGE_SHIFT 12
72 #define MLX4_EN_PAGE_SIZE (1 << MLX4_EN_PAGE_SHIFT)
73 #define DEF_RX_RINGS 16
74 #define MAX_RX_RINGS 128
75 #define MIN_RX_RINGS 4
77 #define HEADROOM (2048 / TXBB_SIZE + 1)
78 #define STAMP_STRIDE 64
79 #define STAMP_DWORDS (STAMP_STRIDE / 4)
80 #define STAMP_SHIFT 31
81 #define STAMP_VAL 0x7fffffff
82 #define STATS_DELAY (HZ / 4)
83 #define SERVICE_TASK_DELAY (HZ / 4)
84 #define MAX_NUM_OF_FS_RULES 256
86 #define MLX4_EN_FILTER_HASH_SHIFT 4
87 #define MLX4_EN_FILTER_EXPIRY_QUOTA 60
89 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
90 #define MAX_DESC_SIZE 512
91 #define MAX_DESC_TXBBS (MAX_DESC_SIZE / TXBB_SIZE)
94 * OS related constants and tunables
97 #define MLX4_EN_PRIV_FLAGS_BLUEFLAME 1
98 #define MLX4_EN_PRIV_FLAGS_PHV 2
100 #define MLX4_EN_WATCHDOG_TIMEOUT (15 * HZ)
102 /* Use the maximum between 16384 and a single page */
103 #define MLX4_EN_ALLOC_SIZE PAGE_ALIGN(16384)
105 #define MLX4_EN_ALLOC_PREFER_ORDER PAGE_ALLOC_COSTLY_ORDER
107 /* Receive fragment sizes; we use at most 3 fragments (for 9600 byte MTU
108 * and 4K allocations) */
110 FRAG_SZ0 = 1536 - NET_IP_ALIGN,
113 FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
115 #define MLX4_EN_MAX_RX_FRAGS 4
117 /* Maximum ring sizes */
118 #define MLX4_EN_MAX_TX_SIZE 8192
119 #define MLX4_EN_MAX_RX_SIZE 8192
121 /* Minimum ring size for our page-allocation scheme to work */
122 #define MLX4_EN_MIN_RX_SIZE (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
123 #define MLX4_EN_MIN_TX_SIZE (4096 / TXBB_SIZE)
125 #define MLX4_EN_SMALL_PKT_SIZE 64
126 #define MLX4_EN_MIN_TX_RING_P_UP 1
127 #define MLX4_EN_MAX_TX_RING_P_UP 32
128 #define MLX4_EN_NUM_UP 8
129 #define MLX4_EN_DEF_TX_RING_SIZE 512
130 #define MLX4_EN_DEF_RX_RING_SIZE 1024
131 #define MAX_TX_RINGS (MLX4_EN_MAX_TX_RING_P_UP * \
134 #define MLX4_EN_DEFAULT_TX_WORK 256
135 #define MLX4_EN_DOORBELL_BUDGET 8
137 /* Target number of packets to coalesce with interrupt moderation */
138 #define MLX4_EN_RX_COAL_TARGET 44
139 #define MLX4_EN_RX_COAL_TIME 0x10
141 #define MLX4_EN_TX_COAL_PKTS 16
142 #define MLX4_EN_TX_COAL_TIME 0x10
144 #define MLX4_EN_RX_RATE_LOW 400000
145 #define MLX4_EN_RX_COAL_TIME_LOW 0
146 #define MLX4_EN_RX_RATE_HIGH 450000
147 #define MLX4_EN_RX_COAL_TIME_HIGH 128
148 #define MLX4_EN_RX_SIZE_THRESH 1024
149 #define MLX4_EN_RX_RATE_THRESH (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
150 #define MLX4_EN_SAMPLE_INTERVAL 0
151 #define MLX4_EN_AVG_PKT_SMALL 256
153 #define MLX4_EN_AUTO_CONF 0xffff
155 #define MLX4_EN_DEF_RX_PAUSE 1
156 #define MLX4_EN_DEF_TX_PAUSE 1
158 /* Interval between successive polls in the Tx routine when polling is used
159 instead of interrupts (in per-core Tx rings) - should be power of 2 */
160 #define MLX4_EN_TX_POLL_MODER 16
161 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
163 #define SMALL_PACKET_SIZE (256 - NET_IP_ALIGN)
164 #define HEADER_COPY_SIZE (128 - NET_IP_ALIGN)
165 #define MLX4_LOOPBACK_TEST_PAYLOAD (HEADER_COPY_SIZE - ETH_HLEN)
167 #define MLX4_EN_MIN_MTU 46
168 /* VLAN_HLEN is added twice,to support skb vlan tagged with multiple
169 * headers. (For example: ETH_P_8021Q and ETH_P_8021AD).
171 #define MLX4_EN_EFF_MTU(mtu) ((mtu) + ETH_HLEN + (2 * VLAN_HLEN))
172 #define ETH_BCAST 0xffffffffffffULL
174 #define MLX4_EN_LOOPBACK_RETRIES 5
175 #define MLX4_EN_LOOPBACK_TIMEOUT 100
177 #ifdef MLX4_EN_PERF_STAT
178 /* Number of samples to 'average' */
180 #define AVG_FACTOR 1024
182 #define INC_PERF_COUNTER(cnt) (++(cnt))
183 #define ADD_PERF_COUNTER(cnt, add) ((cnt) += (add))
184 #define AVG_PERF_COUNTER(cnt, sample) \
185 ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
186 #define GET_PERF_COUNTER(cnt) (cnt)
187 #define GET_AVG_PERF_COUNTER(cnt) ((cnt) / AVG_FACTOR)
191 #define INC_PERF_COUNTER(cnt) do {} while (0)
192 #define ADD_PERF_COUNTER(cnt, add) do {} while (0)
193 #define AVG_PERF_COUNTER(cnt, sample) do {} while (0)
194 #define GET_PERF_COUNTER(cnt) (0)
195 #define GET_AVG_PERF_COUNTER(cnt) (0)
196 #endif /* MLX4_EN_PERF_STAT */
198 /* Constants for TX flow */
200 MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */
210 /* keep tx types first */
213 #define MLX4_EN_NUM_TX_TYPES (TX_XDP + 1)
221 #define ROUNDUP_LOG2(x) ilog2(roundup_pow_of_two(x))
222 #define XNOR(x, y) (!(x) == !(y))
225 struct mlx4_en_tx_info {
239 } ____cacheline_aligned_in_smp;
242 #define MLX4_EN_BIT_DESC_OWN 0x80000000
243 #define CTRL_SIZE sizeof(struct mlx4_wqe_ctrl_seg)
244 #define MLX4_EN_MEMTYPE_PAD 0x100
245 #define DS_SIZE sizeof(struct mlx4_wqe_data_seg)
248 struct mlx4_en_tx_desc {
249 struct mlx4_wqe_ctrl_seg ctrl;
251 struct mlx4_wqe_data_seg data; /* at least one data segment */
252 struct mlx4_wqe_lso_seg lso;
253 struct mlx4_wqe_inline_seg inl;
257 #define MLX4_EN_USE_SRQ 0x01000000
259 #define MLX4_EN_CX3_LOW_ID 0x1000
260 #define MLX4_EN_CX3_HIGH_ID 0x1005
262 struct mlx4_en_rx_alloc {
269 #define MLX4_EN_CACHE_SIZE (2 * NAPI_POLL_WEIGHT)
270 struct mlx4_en_page_cache {
272 struct mlx4_en_rx_alloc buf[MLX4_EN_CACHE_SIZE];
277 struct mlx4_en_tx_ring {
278 /* cache line used and dirtied in tx completion
279 * (mlx4_en_free_tx_buf())
283 unsigned long wake_queue;
284 struct netdev_queue *tx_queue;
285 u32 (*free_tx_desc)(struct mlx4_en_priv *priv,
286 struct mlx4_en_tx_ring *ring,
288 u64 timestamp, int napi_mode);
289 struct mlx4_en_rx_ring *recycle_ring;
291 /* cache line used and dirtied in mlx4_en_xmit() */
292 u32 prod ____cacheline_aligned_in_smp;
293 unsigned int tx_dropped;
295 unsigned long packets;
296 unsigned long tx_csum;
297 unsigned long tso_packets;
298 unsigned long xmit_more;
301 /* Following part should be mostly read */
304 u32 size; /* number of TXBBs */
309 struct mlx4_en_tx_info *tx_info;
317 /* Not used in fast path
318 * Only queue_stopped might be used if BQL is not properly working.
320 unsigned long queue_stopped;
321 struct mlx4_hwq_resources sp_wqres;
322 struct mlx4_qp sp_qp;
323 struct mlx4_qp_context sp_context;
324 cpumask_t sp_affinity_mask;
325 enum mlx4_qp_state sp_qp_state;
327 u16 sp_cqn; /* index of port CQ associated with this ring */
328 } ____cacheline_aligned_in_smp;
330 struct mlx4_en_rx_desc {
331 /* actual number of entries depends on rx ring stride */
332 struct mlx4_wqe_data_seg data[0];
335 struct mlx4_en_rx_ring {
336 struct mlx4_hwq_resources wqres;
337 struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
338 u32 size ; /* number of Rx descs*/
343 u16 cqn; /* index of port CQ associated with this ring */
350 struct bpf_prog __rcu *xdp_prog;
351 struct mlx4_en_page_cache page_cache;
353 unsigned long packets;
354 unsigned long csum_ok;
355 unsigned long csum_none;
356 unsigned long csum_complete;
357 unsigned long xdp_drop;
358 unsigned long xdp_tx;
359 unsigned long xdp_tx_full;
360 unsigned long dropped;
361 int hwtstamp_rx_filter;
362 cpumask_var_t affinity_mask;
367 struct mlx4_hwq_resources wqres;
369 struct net_device *dev;
370 struct napi_struct napi;
377 struct mlx4_cqe *buf;
378 #define MLX4_EN_OPCODE_ERROR 0x1e
380 struct irq_desc *irq_desc;
383 struct mlx4_en_port_profile {
385 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
389 u8 num_tx_rings_p_up;
396 struct hwtstamp_config hwtstamp_config;
399 struct mlx4_en_profile {
405 u8 num_tx_rings_p_up;
406 struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
410 struct mlx4_dev *dev;
411 struct pci_dev *pdev;
412 struct mutex state_lock;
413 struct net_device *pndev[MLX4_MAX_PORTS + 1];
414 struct net_device *upper[MLX4_MAX_PORTS + 1];
417 struct mlx4_en_profile profile;
419 struct workqueue_struct *workqueue;
420 struct device *dma_device;
421 void __iomem *uar_map;
422 struct mlx4_uar priv_uar;
426 u8 mac_removed[MLX4_MAX_PORTS + 1];
429 struct cyclecounter cycles;
430 struct timecounter clock;
431 unsigned long last_overflow_check;
432 unsigned long overflow_period;
433 struct ptp_clock *ptp_clock;
434 struct ptp_clock_info ptp_clock_info;
435 struct notifier_block nb;
439 struct mlx4_en_rss_map {
441 struct mlx4_qp qps[MAX_RX_RINGS];
442 enum mlx4_qp_state state[MAX_RX_RINGS];
443 struct mlx4_qp indir_qp;
444 enum mlx4_qp_state indir_state;
447 enum mlx4_en_port_flag {
448 MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
449 MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
452 struct mlx4_en_port_state {
459 enum mlx4_en_mclist_act {
465 struct mlx4_en_mc_list {
466 struct list_head list;
467 enum mlx4_en_mclist_act action;
473 struct mlx4_en_frag_info {
475 u16 frag_prefix_size;
477 enum dma_data_direction dma_dir;
482 #ifdef CONFIG_MLX4_EN_DCB
483 /* Minimal TC BW - setting to 0 will block traffic */
484 #define MLX4_EN_BW_MIN 1
485 #define MLX4_EN_BW_MAX 100 /* Utilize 100% of the line */
487 #define MLX4_EN_TC_ETS 7
496 struct mlx4_en_cee_config {
498 enum dcb_pfc_type dcb_pfc[MLX4_EN_NUM_UP];
502 struct ethtool_flow_id {
503 struct list_head list;
504 struct ethtool_rx_flow_spec flow_spec;
509 MLX4_EN_FLAG_PROMISC = (1 << 0),
510 MLX4_EN_FLAG_MC_PROMISC = (1 << 1),
511 /* whether we need to enable hardware loopback by putting dmac
514 MLX4_EN_FLAG_ENABLE_HW_LOOPBACK = (1 << 2),
515 /* whether we need to drop packets that hardware loopback-ed */
516 MLX4_EN_FLAG_RX_FILTER_NEEDED = (1 << 3),
517 MLX4_EN_FLAG_FORCE_PROMISC = (1 << 4),
518 MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP = (1 << 5),
519 #ifdef CONFIG_MLX4_EN_DCB
520 MLX4_EN_FLAG_DCB_ENABLED = (1 << 6),
524 #define PORT_BEACON_MAX_LIMIT (65535)
525 #define MLX4_EN_MAC_HASH_SIZE (1 << BITS_PER_BYTE)
526 #define MLX4_EN_MAC_HASH_IDX 5
528 struct mlx4_en_stats_bitmap {
529 DECLARE_BITMAP(bitmap, NUM_ALL_STATS);
530 struct mutex mutex; /* for mutual access to stats bitmap */
533 struct mlx4_en_priv {
534 struct mlx4_en_dev *mdev;
535 struct mlx4_en_port_profile *prof;
536 struct net_device *dev;
537 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
538 struct mlx4_en_port_state port_state;
539 spinlock_t stats_lock;
540 struct ethtool_flow_id ethtool_rules[MAX_NUM_OF_FS_RULES];
541 /* To allow rules removal while port is going down */
542 struct list_head ethtool_list;
544 unsigned long last_moder_packets[MAX_RX_RINGS];
545 unsigned long last_moder_tx_packets;
546 unsigned long last_moder_bytes[MAX_RX_RINGS];
547 unsigned long last_moder_jiffies;
548 int last_moder_time[MAX_RX_RINGS];
558 u16 adaptive_rx_coal;
561 u32 validate_loopback;
563 struct mlx4_hwq_resources res;
571 unsigned char current_mac[ETH_ALEN + 2];
578 struct mlx4_en_rss_map rss_map;
581 u8 num_tx_rings_p_up;
583 u32 tx_ring_num[MLX4_EN_NUM_TX_TYPES];
586 struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
590 struct mlx4_en_tx_ring **tx_ring[MLX4_EN_NUM_TX_TYPES];
591 struct mlx4_en_rx_ring *rx_ring[MAX_RX_RINGS];
592 struct mlx4_en_cq **tx_cq[MLX4_EN_NUM_TX_TYPES];
593 struct mlx4_en_cq *rx_cq[MAX_RX_RINGS];
594 struct mlx4_qp drop_qp;
595 struct work_struct rx_mode_task;
596 struct work_struct watchdog_task;
597 struct work_struct linkstate_task;
598 struct delayed_work stats_task;
599 struct delayed_work service_task;
600 struct work_struct vxlan_add_task;
601 struct work_struct vxlan_del_task;
602 struct mlx4_en_perf_stats pstats;
603 struct mlx4_en_pkt_stats pkstats;
604 struct mlx4_en_counter_stats pf_stats;
605 struct mlx4_en_flow_stats_rx rx_priority_flowstats[MLX4_NUM_PRIORITIES];
606 struct mlx4_en_flow_stats_tx tx_priority_flowstats[MLX4_NUM_PRIORITIES];
607 struct mlx4_en_flow_stats_rx rx_flowstats;
608 struct mlx4_en_flow_stats_tx tx_flowstats;
609 struct mlx4_en_port_stats port_stats;
610 struct mlx4_en_xdp_stats xdp_stats;
611 struct mlx4_en_stats_bitmap stats_bitmap;
612 struct list_head mc_list;
613 struct list_head curr_list;
615 struct mlx4_en_stat_out_mbox hw_stats;
619 struct hlist_head mac_hash[MLX4_EN_MAC_HASH_SIZE];
620 struct hwtstamp_config hwtstamp_config;
623 #ifdef CONFIG_MLX4_EN_DCB
624 #define MLX4_EN_DCB_ENABLED 0x3
626 u16 maxrate[IEEE_8021QAZ_MAX_TCS];
627 enum dcbnl_cndd_states cndd_state[IEEE_8021QAZ_MAX_TCS];
628 struct mlx4_en_cee_config cee_config;
631 #ifdef CONFIG_RFS_ACCEL
632 spinlock_t filters_lock;
634 struct list_head filters;
635 struct hlist_head filter_hash[1 << MLX4_EN_FILTER_HASH_SHIFT];
641 u8 rss_key[MLX4_EN_RSS_KEY_SIZE];
646 MLX4_EN_WOL_MAGIC = (1ULL << 61),
647 MLX4_EN_WOL_ENABLED = (1ULL << 62),
650 struct mlx4_mac_entry {
651 struct hlist_node hlist;
652 unsigned char mac[ETH_ALEN + 2];
657 static inline struct mlx4_cqe *mlx4_en_get_cqe(void *buf, int idx, int cqe_sz)
659 return buf + idx * cqe_sz;
662 #define MLX4_EN_WOL_DO_MODIFY (1ULL << 63)
664 void mlx4_en_init_ptys2ethtool_map(void);
665 void mlx4_en_update_loopback_state(struct net_device *dev,
666 netdev_features_t features);
668 void mlx4_en_destroy_netdev(struct net_device *dev);
669 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
670 struct mlx4_en_port_profile *prof);
672 int mlx4_en_start_port(struct net_device *dev);
673 void mlx4_en_stop_port(struct net_device *dev, int detach);
675 void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
676 struct mlx4_en_stats_bitmap *stats_bitmap,
677 u8 rx_ppp, u8 rx_pause,
678 u8 tx_ppp, u8 tx_pause);
680 int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
681 struct mlx4_en_priv *tmp,
682 struct mlx4_en_port_profile *prof,
683 bool carry_xdp_prog);
684 void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
685 struct mlx4_en_priv *tmp);
687 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq,
688 int entries, int ring, enum cq_type mode, int node);
689 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq);
690 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
692 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
693 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
694 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
696 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
697 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb,
698 void *accel_priv, select_queue_fallback_t fallback);
699 netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
700 netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring,
701 struct mlx4_en_rx_alloc *frame,
702 struct net_device *dev, unsigned int length,
703 int tx_ind, int *doorbell_pending);
704 void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring);
705 bool mlx4_en_rx_recycle(struct mlx4_en_rx_ring *ring,
706 struct mlx4_en_rx_alloc *frame);
708 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,
709 struct mlx4_en_tx_ring **pring,
710 u32 size, u16 stride,
711 int node, int queue_index);
712 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv,
713 struct mlx4_en_tx_ring **pring);
714 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
715 struct mlx4_en_tx_ring *ring,
716 int cq, int user_prio);
717 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
718 struct mlx4_en_tx_ring *ring);
719 void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev);
720 void mlx4_en_recover_from_oom(struct mlx4_en_priv *priv);
721 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
722 struct mlx4_en_rx_ring **pring,
723 u32 size, u16 stride, int node);
724 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
725 struct mlx4_en_rx_ring **pring,
726 u32 size, u16 stride);
727 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
728 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
729 struct mlx4_en_rx_ring *ring);
730 int mlx4_en_process_rx_cq(struct net_device *dev,
731 struct mlx4_en_cq *cq,
733 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
734 int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget);
735 u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
736 struct mlx4_en_tx_ring *ring,
737 int index, u8 owner, u64 timestamp,
739 u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv,
740 struct mlx4_en_tx_ring *ring,
741 int index, u8 owner, u64 timestamp,
743 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
744 int is_tx, int rss, int qpn, int cqn, int user_prio,
745 struct mlx4_qp_context *context);
746 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
747 int mlx4_en_change_mcast_lb(struct mlx4_en_priv *priv, struct mlx4_qp *qp,
749 void mlx4_en_calc_rx_buf(struct net_device *dev);
750 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
751 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
752 int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv);
753 void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv);
754 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
755 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
757 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
758 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, struct mlx4_en_priv *priv);
760 void mlx4_en_fold_software_stats(struct net_device *dev);
761 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
762 int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port);
764 #ifdef CONFIG_MLX4_EN_DCB
765 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_ops;
766 extern const struct dcbnl_rtnl_ops mlx4_en_dcbnl_pfc_ops;
769 int mlx4_en_setup_tc(struct net_device *dev, u8 up);
771 #ifdef CONFIG_RFS_ACCEL
772 void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv);
775 #define MLX4_EN_NUM_SELF_TEST 5
776 void mlx4_en_ex_selftest(struct net_device *dev, u32 *flags, u64 *buf);
777 void mlx4_en_ptp_overflow_check(struct mlx4_en_dev *mdev);
779 #define DEV_FEATURE_CHANGED(dev, new_features, feature) \
780 ((dev->features & feature) ^ (new_features & feature))
782 int mlx4_en_reset_config(struct net_device *dev,
783 struct hwtstamp_config ts_config,
784 netdev_features_t new_features);
785 void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
786 struct mlx4_en_stats_bitmap *stats_bitmap,
787 u8 rx_ppp, u8 rx_pause,
788 u8 tx_ppp, u8 tx_pause);
789 int mlx4_en_netdev_event(struct notifier_block *this,
790 unsigned long event, void *ptr);
793 * Functions for time stamping
795 u64 mlx4_en_get_cqe_ts(struct mlx4_cqe *cqe);
796 void mlx4_en_fill_hwtstamps(struct mlx4_en_dev *mdev,
797 struct skb_shared_hwtstamps *hwts,
799 void mlx4_en_init_timestamp(struct mlx4_en_dev *mdev);
800 void mlx4_en_remove_timestamp(struct mlx4_en_dev *mdev);
804 extern const struct ethtool_ops mlx4_en_ethtool_ops;
809 * printk / logging functions
813 void en_print(const char *level, const struct mlx4_en_priv *priv,
814 const char *format, ...);
816 #define en_dbg(mlevel, priv, format, ...) \
818 if (NETIF_MSG_##mlevel & (priv)->msg_enable) \
819 en_print(KERN_DEBUG, priv, format, ##__VA_ARGS__); \
821 #define en_warn(priv, format, ...) \
822 en_print(KERN_WARNING, priv, format, ##__VA_ARGS__)
823 #define en_err(priv, format, ...) \
824 en_print(KERN_ERR, priv, format, ##__VA_ARGS__)
825 #define en_info(priv, format, ...) \
826 en_print(KERN_INFO, priv, format, ##__VA_ARGS__)
828 #define mlx4_err(mdev, format, ...) \
829 pr_err(DRV_NAME " %s: " format, \
830 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
831 #define mlx4_info(mdev, format, ...) \
832 pr_info(DRV_NAME " %s: " format, \
833 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)
834 #define mlx4_warn(mdev, format, ...) \
835 pr_warn(DRV_NAME " %s: " format, \
836 dev_name(&(mdev)->pdev->dev), ##__VA_ARGS__)