2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/mlx5/eq.h>
44 #include <linux/debugfs.h>
46 #include "mlx5_core.h"
59 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
60 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
61 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
62 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
63 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
64 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
65 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
66 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
67 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
68 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
69 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
72 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
73 struct mlx5_cmd_msg *in,
74 struct mlx5_cmd_msg *out,
75 void *uout, int uout_size,
77 void *context, int page_queue)
79 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
80 struct mlx5_cmd_work_ent *ent;
82 ent = kzalloc(sizeof(*ent), alloc_flags);
84 return ERR_PTR(-ENOMEM);
89 ent->uout_size = uout_size;
91 ent->context = context;
93 ent->page_queue = page_queue;
98 static u8 alloc_token(struct mlx5_cmd *cmd)
102 spin_lock(&cmd->token_lock);
107 spin_unlock(&cmd->token_lock);
112 static int alloc_ent(struct mlx5_cmd *cmd)
117 spin_lock_irqsave(&cmd->alloc_lock, flags);
118 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
119 if (ret < cmd->max_reg_cmds)
120 clear_bit(ret, &cmd->bitmask);
121 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
123 return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
126 static void free_ent(struct mlx5_cmd *cmd, int idx)
130 spin_lock_irqsave(&cmd->alloc_lock, flags);
131 set_bit(idx, &cmd->bitmask);
132 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
135 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
137 return cmd->cmd_buf + (idx << cmd->log_stride);
140 static int mlx5_calc_cmd_blocks(struct mlx5_cmd_msg *msg)
143 int blen = size - min_t(int, sizeof(msg->first.data), size);
145 return DIV_ROUND_UP(blen, MLX5_CMD_DATA_BLOCK_SIZE);
148 static u8 xor8_buf(void *buf, size_t offset, int len)
153 int end = len + offset;
155 for (i = offset; i < end; i++)
161 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
163 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
164 int xor_len = sizeof(*block) - sizeof(block->data) - 1;
166 if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
169 if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
175 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
177 int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
178 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
180 block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
181 block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
184 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
186 struct mlx5_cmd_mailbox *next = msg->next;
187 int n = mlx5_calc_cmd_blocks(msg);
190 for (i = 0; i < n && next; i++) {
191 calc_block_sig(next->buf);
196 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
198 ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay));
200 calc_chain_sig(ent->in);
201 calc_chain_sig(ent->out);
205 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
207 unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
211 own = READ_ONCE(ent->lay->status_own);
212 if (!(own & CMD_OWNER_HW)) {
217 } while (time_before(jiffies, poll_end));
219 ent->ret = -ETIMEDOUT;
222 static void free_cmd(struct mlx5_cmd_work_ent *ent)
227 static int verify_signature(struct mlx5_cmd_work_ent *ent)
229 struct mlx5_cmd_mailbox *next = ent->out->next;
230 int n = mlx5_calc_cmd_blocks(ent->out);
235 sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
239 for (i = 0; i < n && next; i++) {
240 err = verify_block_sig(next->buf);
250 static void dump_buf(void *buf, int size, int data_only, int offset)
255 for (i = 0; i < size; i += 16) {
256 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
257 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
266 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
267 u32 *synd, u8 *status)
273 case MLX5_CMD_OP_TEARDOWN_HCA:
274 case MLX5_CMD_OP_DISABLE_HCA:
275 case MLX5_CMD_OP_MANAGE_PAGES:
276 case MLX5_CMD_OP_DESTROY_MKEY:
277 case MLX5_CMD_OP_DESTROY_EQ:
278 case MLX5_CMD_OP_DESTROY_CQ:
279 case MLX5_CMD_OP_DESTROY_QP:
280 case MLX5_CMD_OP_DESTROY_PSV:
281 case MLX5_CMD_OP_DESTROY_SRQ:
282 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
283 case MLX5_CMD_OP_DESTROY_XRQ:
284 case MLX5_CMD_OP_DESTROY_DCT:
285 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
286 case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
287 case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
288 case MLX5_CMD_OP_DEALLOC_PD:
289 case MLX5_CMD_OP_DEALLOC_UAR:
290 case MLX5_CMD_OP_DETACH_FROM_MCG:
291 case MLX5_CMD_OP_DEALLOC_XRCD:
292 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
293 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
294 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
295 case MLX5_CMD_OP_DESTROY_LAG:
296 case MLX5_CMD_OP_DESTROY_VPORT_LAG:
297 case MLX5_CMD_OP_DESTROY_TIR:
298 case MLX5_CMD_OP_DESTROY_SQ:
299 case MLX5_CMD_OP_DESTROY_RQ:
300 case MLX5_CMD_OP_DESTROY_RMP:
301 case MLX5_CMD_OP_DESTROY_TIS:
302 case MLX5_CMD_OP_DESTROY_RQT:
303 case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
304 case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
305 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
306 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
307 case MLX5_CMD_OP_2ERR_QP:
308 case MLX5_CMD_OP_2RST_QP:
309 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
310 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
311 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
312 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
313 case MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT:
314 case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
315 case MLX5_CMD_OP_FPGA_DESTROY_QP:
316 case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
317 case MLX5_CMD_OP_DEALLOC_MEMIC:
318 case MLX5_CMD_OP_PAGE_FAULT_RESUME:
319 case MLX5_CMD_OP_QUERY_HOST_PARAMS:
320 return MLX5_CMD_STAT_OK;
322 case MLX5_CMD_OP_QUERY_HCA_CAP:
323 case MLX5_CMD_OP_QUERY_ADAPTER:
324 case MLX5_CMD_OP_INIT_HCA:
325 case MLX5_CMD_OP_ENABLE_HCA:
326 case MLX5_CMD_OP_QUERY_PAGES:
327 case MLX5_CMD_OP_SET_HCA_CAP:
328 case MLX5_CMD_OP_QUERY_ISSI:
329 case MLX5_CMD_OP_SET_ISSI:
330 case MLX5_CMD_OP_CREATE_MKEY:
331 case MLX5_CMD_OP_QUERY_MKEY:
332 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
333 case MLX5_CMD_OP_CREATE_EQ:
334 case MLX5_CMD_OP_QUERY_EQ:
335 case MLX5_CMD_OP_GEN_EQE:
336 case MLX5_CMD_OP_CREATE_CQ:
337 case MLX5_CMD_OP_QUERY_CQ:
338 case MLX5_CMD_OP_MODIFY_CQ:
339 case MLX5_CMD_OP_CREATE_QP:
340 case MLX5_CMD_OP_RST2INIT_QP:
341 case MLX5_CMD_OP_INIT2RTR_QP:
342 case MLX5_CMD_OP_RTR2RTS_QP:
343 case MLX5_CMD_OP_RTS2RTS_QP:
344 case MLX5_CMD_OP_SQERR2RTS_QP:
345 case MLX5_CMD_OP_QUERY_QP:
346 case MLX5_CMD_OP_SQD_RTS_QP:
347 case MLX5_CMD_OP_INIT2INIT_QP:
348 case MLX5_CMD_OP_CREATE_PSV:
349 case MLX5_CMD_OP_CREATE_SRQ:
350 case MLX5_CMD_OP_QUERY_SRQ:
351 case MLX5_CMD_OP_ARM_RQ:
352 case MLX5_CMD_OP_CREATE_XRC_SRQ:
353 case MLX5_CMD_OP_QUERY_XRC_SRQ:
354 case MLX5_CMD_OP_ARM_XRC_SRQ:
355 case MLX5_CMD_OP_CREATE_XRQ:
356 case MLX5_CMD_OP_QUERY_XRQ:
357 case MLX5_CMD_OP_ARM_XRQ:
358 case MLX5_CMD_OP_CREATE_DCT:
359 case MLX5_CMD_OP_DRAIN_DCT:
360 case MLX5_CMD_OP_QUERY_DCT:
361 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
362 case MLX5_CMD_OP_QUERY_VPORT_STATE:
363 case MLX5_CMD_OP_MODIFY_VPORT_STATE:
364 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
365 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
366 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
367 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
368 case MLX5_CMD_OP_SET_ROCE_ADDRESS:
369 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
370 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
371 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
372 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
373 case MLX5_CMD_OP_QUERY_VNIC_ENV:
374 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
375 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
376 case MLX5_CMD_OP_QUERY_Q_COUNTER:
377 case MLX5_CMD_OP_SET_MONITOR_COUNTER:
378 case MLX5_CMD_OP_ARM_MONITOR_COUNTER:
379 case MLX5_CMD_OP_SET_PP_RATE_LIMIT:
380 case MLX5_CMD_OP_QUERY_RATE_LIMIT:
381 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
382 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
383 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
384 case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
385 case MLX5_CMD_OP_ALLOC_PD:
386 case MLX5_CMD_OP_ALLOC_UAR:
387 case MLX5_CMD_OP_CONFIG_INT_MODERATION:
388 case MLX5_CMD_OP_ACCESS_REG:
389 case MLX5_CMD_OP_ATTACH_TO_MCG:
390 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
391 case MLX5_CMD_OP_MAD_IFC:
392 case MLX5_CMD_OP_QUERY_MAD_DEMUX:
393 case MLX5_CMD_OP_SET_MAD_DEMUX:
394 case MLX5_CMD_OP_NOP:
395 case MLX5_CMD_OP_ALLOC_XRCD:
396 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
397 case MLX5_CMD_OP_QUERY_CONG_STATUS:
398 case MLX5_CMD_OP_MODIFY_CONG_STATUS:
399 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
400 case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
401 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
402 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
403 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
404 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
405 case MLX5_CMD_OP_CREATE_LAG:
406 case MLX5_CMD_OP_MODIFY_LAG:
407 case MLX5_CMD_OP_QUERY_LAG:
408 case MLX5_CMD_OP_CREATE_VPORT_LAG:
409 case MLX5_CMD_OP_CREATE_TIR:
410 case MLX5_CMD_OP_MODIFY_TIR:
411 case MLX5_CMD_OP_QUERY_TIR:
412 case MLX5_CMD_OP_CREATE_SQ:
413 case MLX5_CMD_OP_MODIFY_SQ:
414 case MLX5_CMD_OP_QUERY_SQ:
415 case MLX5_CMD_OP_CREATE_RQ:
416 case MLX5_CMD_OP_MODIFY_RQ:
417 case MLX5_CMD_OP_QUERY_RQ:
418 case MLX5_CMD_OP_CREATE_RMP:
419 case MLX5_CMD_OP_MODIFY_RMP:
420 case MLX5_CMD_OP_QUERY_RMP:
421 case MLX5_CMD_OP_CREATE_TIS:
422 case MLX5_CMD_OP_MODIFY_TIS:
423 case MLX5_CMD_OP_QUERY_TIS:
424 case MLX5_CMD_OP_CREATE_RQT:
425 case MLX5_CMD_OP_MODIFY_RQT:
426 case MLX5_CMD_OP_QUERY_RQT:
428 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
429 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
430 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
431 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
432 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
433 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
434 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
435 case MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT:
436 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
437 case MLX5_CMD_OP_FPGA_CREATE_QP:
438 case MLX5_CMD_OP_FPGA_MODIFY_QP:
439 case MLX5_CMD_OP_FPGA_QUERY_QP:
440 case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
441 case MLX5_CMD_OP_CREATE_GENERAL_OBJECT:
442 case MLX5_CMD_OP_MODIFY_GENERAL_OBJECT:
443 case MLX5_CMD_OP_QUERY_GENERAL_OBJECT:
444 case MLX5_CMD_OP_ALLOC_MEMIC:
445 *status = MLX5_DRIVER_STATUS_ABORTED;
446 *synd = MLX5_DRIVER_SYND;
449 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
454 const char *mlx5_command_str(int command)
456 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
459 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
460 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
461 MLX5_COMMAND_STR_CASE(INIT_HCA);
462 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
463 MLX5_COMMAND_STR_CASE(ENABLE_HCA);
464 MLX5_COMMAND_STR_CASE(DISABLE_HCA);
465 MLX5_COMMAND_STR_CASE(QUERY_PAGES);
466 MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
467 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
468 MLX5_COMMAND_STR_CASE(QUERY_ISSI);
469 MLX5_COMMAND_STR_CASE(SET_ISSI);
470 MLX5_COMMAND_STR_CASE(SET_DRIVER_VERSION);
471 MLX5_COMMAND_STR_CASE(CREATE_MKEY);
472 MLX5_COMMAND_STR_CASE(QUERY_MKEY);
473 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
474 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
475 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
476 MLX5_COMMAND_STR_CASE(CREATE_EQ);
477 MLX5_COMMAND_STR_CASE(DESTROY_EQ);
478 MLX5_COMMAND_STR_CASE(QUERY_EQ);
479 MLX5_COMMAND_STR_CASE(GEN_EQE);
480 MLX5_COMMAND_STR_CASE(CREATE_CQ);
481 MLX5_COMMAND_STR_CASE(DESTROY_CQ);
482 MLX5_COMMAND_STR_CASE(QUERY_CQ);
483 MLX5_COMMAND_STR_CASE(MODIFY_CQ);
484 MLX5_COMMAND_STR_CASE(CREATE_QP);
485 MLX5_COMMAND_STR_CASE(DESTROY_QP);
486 MLX5_COMMAND_STR_CASE(RST2INIT_QP);
487 MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
488 MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
489 MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
490 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
491 MLX5_COMMAND_STR_CASE(2ERR_QP);
492 MLX5_COMMAND_STR_CASE(2RST_QP);
493 MLX5_COMMAND_STR_CASE(QUERY_QP);
494 MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
495 MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
496 MLX5_COMMAND_STR_CASE(CREATE_PSV);
497 MLX5_COMMAND_STR_CASE(DESTROY_PSV);
498 MLX5_COMMAND_STR_CASE(CREATE_SRQ);
499 MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
500 MLX5_COMMAND_STR_CASE(QUERY_SRQ);
501 MLX5_COMMAND_STR_CASE(ARM_RQ);
502 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
503 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
504 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
505 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
506 MLX5_COMMAND_STR_CASE(CREATE_DCT);
507 MLX5_COMMAND_STR_CASE(DESTROY_DCT);
508 MLX5_COMMAND_STR_CASE(DRAIN_DCT);
509 MLX5_COMMAND_STR_CASE(QUERY_DCT);
510 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
511 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
512 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
513 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
514 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
515 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
516 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
517 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
518 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
519 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
520 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
521 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
522 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
523 MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV);
524 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
525 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
526 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
527 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
528 MLX5_COMMAND_STR_CASE(SET_MONITOR_COUNTER);
529 MLX5_COMMAND_STR_CASE(ARM_MONITOR_COUNTER);
530 MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT);
531 MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
532 MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
533 MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
534 MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
535 MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
536 MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
537 MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
538 MLX5_COMMAND_STR_CASE(ALLOC_PD);
539 MLX5_COMMAND_STR_CASE(DEALLOC_PD);
540 MLX5_COMMAND_STR_CASE(ALLOC_UAR);
541 MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
542 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
543 MLX5_COMMAND_STR_CASE(ACCESS_REG);
544 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
545 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
546 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
547 MLX5_COMMAND_STR_CASE(MAD_IFC);
548 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
549 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
550 MLX5_COMMAND_STR_CASE(NOP);
551 MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
552 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
553 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
554 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
555 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
556 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
557 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
558 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
559 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
560 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
561 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
562 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
563 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
564 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
565 MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
566 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
567 MLX5_COMMAND_STR_CASE(CREATE_LAG);
568 MLX5_COMMAND_STR_CASE(MODIFY_LAG);
569 MLX5_COMMAND_STR_CASE(QUERY_LAG);
570 MLX5_COMMAND_STR_CASE(DESTROY_LAG);
571 MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
572 MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
573 MLX5_COMMAND_STR_CASE(CREATE_TIR);
574 MLX5_COMMAND_STR_CASE(MODIFY_TIR);
575 MLX5_COMMAND_STR_CASE(DESTROY_TIR);
576 MLX5_COMMAND_STR_CASE(QUERY_TIR);
577 MLX5_COMMAND_STR_CASE(CREATE_SQ);
578 MLX5_COMMAND_STR_CASE(MODIFY_SQ);
579 MLX5_COMMAND_STR_CASE(DESTROY_SQ);
580 MLX5_COMMAND_STR_CASE(QUERY_SQ);
581 MLX5_COMMAND_STR_CASE(CREATE_RQ);
582 MLX5_COMMAND_STR_CASE(MODIFY_RQ);
583 MLX5_COMMAND_STR_CASE(DESTROY_RQ);
584 MLX5_COMMAND_STR_CASE(QUERY_RQ);
585 MLX5_COMMAND_STR_CASE(CREATE_RMP);
586 MLX5_COMMAND_STR_CASE(MODIFY_RMP);
587 MLX5_COMMAND_STR_CASE(DESTROY_RMP);
588 MLX5_COMMAND_STR_CASE(QUERY_RMP);
589 MLX5_COMMAND_STR_CASE(CREATE_TIS);
590 MLX5_COMMAND_STR_CASE(MODIFY_TIS);
591 MLX5_COMMAND_STR_CASE(DESTROY_TIS);
592 MLX5_COMMAND_STR_CASE(QUERY_TIS);
593 MLX5_COMMAND_STR_CASE(CREATE_RQT);
594 MLX5_COMMAND_STR_CASE(MODIFY_RQT);
595 MLX5_COMMAND_STR_CASE(DESTROY_RQT);
596 MLX5_COMMAND_STR_CASE(QUERY_RQT);
597 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
598 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
599 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
600 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
601 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
602 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
603 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
604 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
605 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
606 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
607 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
608 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
609 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
610 MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
611 MLX5_COMMAND_STR_CASE(ALLOC_PACKET_REFORMAT_CONTEXT);
612 MLX5_COMMAND_STR_CASE(DEALLOC_PACKET_REFORMAT_CONTEXT);
613 MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
614 MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
615 MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
616 MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
617 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
618 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
619 MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
620 MLX5_COMMAND_STR_CASE(CREATE_XRQ);
621 MLX5_COMMAND_STR_CASE(DESTROY_XRQ);
622 MLX5_COMMAND_STR_CASE(QUERY_XRQ);
623 MLX5_COMMAND_STR_CASE(ARM_XRQ);
624 MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJECT);
625 MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJECT);
626 MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJECT);
627 MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJECT);
628 MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
629 MLX5_COMMAND_STR_CASE(ALLOC_MEMIC);
630 MLX5_COMMAND_STR_CASE(DEALLOC_MEMIC);
631 MLX5_COMMAND_STR_CASE(QUERY_HOST_PARAMS);
632 default: return "unknown command opcode";
636 static const char *cmd_status_str(u8 status)
639 case MLX5_CMD_STAT_OK:
641 case MLX5_CMD_STAT_INT_ERR:
642 return "internal error";
643 case MLX5_CMD_STAT_BAD_OP_ERR:
644 return "bad operation";
645 case MLX5_CMD_STAT_BAD_PARAM_ERR:
646 return "bad parameter";
647 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
648 return "bad system state";
649 case MLX5_CMD_STAT_BAD_RES_ERR:
650 return "bad resource";
651 case MLX5_CMD_STAT_RES_BUSY:
652 return "resource busy";
653 case MLX5_CMD_STAT_LIM_ERR:
654 return "limits exceeded";
655 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
656 return "bad resource state";
657 case MLX5_CMD_STAT_IX_ERR:
659 case MLX5_CMD_STAT_NO_RES_ERR:
660 return "no resources";
661 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
662 return "bad input length";
663 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
664 return "bad output length";
665 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
666 return "bad QP state";
667 case MLX5_CMD_STAT_BAD_PKT_ERR:
668 return "bad packet (discarded)";
669 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
670 return "bad size too many outstanding CQEs";
672 return "unknown status";
676 static int cmd_status_to_err(u8 status)
679 case MLX5_CMD_STAT_OK: return 0;
680 case MLX5_CMD_STAT_INT_ERR: return -EIO;
681 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
682 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
683 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
684 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
685 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
686 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
687 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
688 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
689 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
690 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
691 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
692 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
693 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
694 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
695 default: return -EIO;
699 struct mlx5_ifc_mbox_out_bits {
701 u8 reserved_at_8[0x18];
705 u8 reserved_at_40[0x40];
708 struct mlx5_ifc_mbox_in_bits {
712 u8 reserved_at_20[0x10];
715 u8 reserved_at_40[0x40];
718 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
720 *status = MLX5_GET(mbox_out, out, status);
721 *syndrome = MLX5_GET(mbox_out, out, syndrome);
724 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
732 mlx5_cmd_mbox_status(out, &status, &syndrome);
736 opcode = MLX5_GET(mbox_in, in, opcode);
737 op_mod = MLX5_GET(mbox_in, in, op_mod);
738 uid = MLX5_GET(mbox_in, in, uid);
740 if (!uid && opcode != MLX5_CMD_OP_DESTROY_MKEY)
741 mlx5_core_err_rl(dev,
742 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
743 mlx5_command_str(opcode), opcode, op_mod,
744 cmd_status_str(status), status, syndrome);
747 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
748 mlx5_command_str(opcode),
750 cmd_status_str(status),
754 return cmd_status_to_err(status);
757 static void dump_command(struct mlx5_core_dev *dev,
758 struct mlx5_cmd_work_ent *ent, int input)
760 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
761 u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
762 struct mlx5_cmd_mailbox *next = msg->next;
763 int n = mlx5_calc_cmd_blocks(msg);
769 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
772 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
773 "dump command data %s(0x%x) %s\n",
774 mlx5_command_str(op), op,
775 input ? "INPUT" : "OUTPUT");
777 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
778 mlx5_command_str(op), op,
779 input ? "INPUT" : "OUTPUT");
783 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
784 offset += sizeof(ent->lay->in);
786 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
787 offset += sizeof(ent->lay->out);
790 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
791 offset += sizeof(*ent->lay);
794 for (i = 0; i < n && next; i++) {
796 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
797 dump_buf(next->buf, dump_len, 1, offset);
798 offset += MLX5_CMD_DATA_BLOCK_SIZE;
800 mlx5_core_dbg(dev, "command block:\n");
801 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
802 offset += sizeof(struct mlx5_cmd_prot_block);
811 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
813 return MLX5_GET(mbox_in, in->first.data, opcode);
816 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced);
818 static void cb_timeout_handler(struct work_struct *work)
820 struct delayed_work *dwork = container_of(work, struct delayed_work,
822 struct mlx5_cmd_work_ent *ent = container_of(dwork,
823 struct mlx5_cmd_work_ent,
825 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
828 ent->ret = -ETIMEDOUT;
829 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
830 mlx5_command_str(msg_to_opcode(ent->in)),
831 msg_to_opcode(ent->in));
832 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
835 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
836 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
837 struct mlx5_cmd_msg *msg);
839 static void cmd_work_handler(struct work_struct *work)
841 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
842 struct mlx5_cmd *cmd = ent->cmd;
843 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
844 unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
845 struct mlx5_cmd_layout *lay;
846 struct semaphore *sem;
848 bool poll_cmd = ent->polling;
852 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
854 if (!ent->page_queue) {
855 alloc_ret = alloc_ent(cmd);
857 mlx5_core_err(dev, "failed to allocate command entry\n");
859 ent->callback(-EAGAIN, ent->context);
860 mlx5_free_cmd_msg(dev, ent->out);
861 free_msg(dev, ent->in);
865 complete(&ent->done);
870 ent->idx = alloc_ret;
872 ent->idx = cmd->max_reg_cmds;
873 spin_lock_irqsave(&cmd->alloc_lock, flags);
874 clear_bit(ent->idx, &cmd->bitmask);
875 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
878 cmd->ent_arr[ent->idx] = ent;
879 set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
880 lay = get_inst(cmd, ent->idx);
882 memset(lay, 0, sizeof(*lay));
883 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
884 ent->op = be32_to_cpu(lay->in[0]) >> 16;
886 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
887 lay->inlen = cpu_to_be32(ent->in->len);
889 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
890 lay->outlen = cpu_to_be32(ent->out->len);
891 lay->type = MLX5_PCI_CMD_XPORT;
892 lay->token = ent->token;
893 lay->status_own = CMD_OWNER_HW;
894 set_signature(ent, !cmd->checksum_disabled);
895 dump_command(dev, ent, 1);
896 ent->ts1 = ktime_get_ns();
897 cmd_mode = cmd->mode;
900 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
902 /* Skip sending command to fw if internal error */
903 if (pci_channel_offline(dev->pdev) ||
904 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
908 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
909 MLX5_SET(mbox_out, ent->out, status, status);
910 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
912 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
916 /* ring doorbell after the descriptor is valid */
917 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
919 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
920 /* if not in polling don't use ent after this point */
921 if (cmd_mode == CMD_MODE_POLLING || poll_cmd) {
923 /* make sure we read the descriptor after ownership is SW */
925 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
929 static const char *deliv_status_to_str(u8 status)
932 case MLX5_CMD_DELIVERY_STAT_OK:
934 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
935 return "signature error";
936 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
937 return "token error";
938 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
939 return "bad block number";
940 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
941 return "output pointer not aligned to block size";
942 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
943 return "input pointer not aligned to block size";
944 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
945 return "firmware internal error";
946 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
947 return "command input length error";
948 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
949 return "command output length error";
950 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
951 return "reserved fields not cleared";
952 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
953 return "bad command descriptor type";
955 return "unknown status code";
959 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
961 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
962 struct mlx5_cmd *cmd = &dev->cmd;
965 if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
966 wait_for_completion(&ent->done);
967 } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
968 ent->ret = -ETIMEDOUT;
969 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
974 if (err == -ETIMEDOUT) {
975 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
976 mlx5_command_str(msg_to_opcode(ent->in)),
977 msg_to_opcode(ent->in));
979 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
980 err, deliv_status_to_str(ent->status), ent->status);
986 * 1. Callback functions may not sleep
987 * 2. page queue commands do not support asynchrous completion
989 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
990 struct mlx5_cmd_msg *out, void *uout, int uout_size,
991 mlx5_cmd_cbk_t callback,
992 void *context, int page_queue, u8 *status,
993 u8 token, bool force_polling)
995 struct mlx5_cmd *cmd = &dev->cmd;
996 struct mlx5_cmd_work_ent *ent;
997 struct mlx5_cmd_stats *stats;
1002 if (callback && page_queue)
1005 ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
1008 return PTR_ERR(ent);
1011 ent->polling = force_polling;
1014 init_completion(&ent->done);
1016 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
1017 INIT_WORK(&ent->work, cmd_work_handler);
1019 cmd_work_handler(&ent->work);
1020 } else if (!queue_work(cmd->wq, &ent->work)) {
1021 mlx5_core_warn(dev, "failed to queue work\n");
1029 err = wait_func(dev, ent);
1030 if (err == -ETIMEDOUT)
1033 ds = ent->ts2 - ent->ts1;
1034 op = MLX5_GET(mbox_in, in->first.data, opcode);
1035 if (op < ARRAY_SIZE(cmd->stats)) {
1036 stats = &cmd->stats[op];
1037 spin_lock_irq(&stats->lock);
1040 spin_unlock_irq(&stats->lock);
1042 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1043 "fw exec time for %s is %lld nsec\n",
1044 mlx5_command_str(op), ds);
1045 *status = ent->status;
1053 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1054 size_t count, loff_t *pos)
1056 struct mlx5_core_dev *dev = filp->private_data;
1057 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1061 if (!dbg->in_msg || !dbg->out_msg)
1064 if (count < sizeof(lbuf) - 1)
1067 if (copy_from_user(lbuf, buf, sizeof(lbuf) - 1))
1070 lbuf[sizeof(lbuf) - 1] = 0;
1072 if (strcmp(lbuf, "go"))
1075 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1077 return err ? err : count;
1080 static const struct file_operations fops = {
1081 .owner = THIS_MODULE,
1082 .open = simple_open,
1086 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1089 struct mlx5_cmd_prot_block *block;
1090 struct mlx5_cmd_mailbox *next;
1096 copy = min_t(int, size, sizeof(to->first.data));
1097 memcpy(to->first.data, from, copy);
1108 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1110 memcpy(block->data, from, copy);
1113 block->token = token;
1120 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1122 struct mlx5_cmd_prot_block *block;
1123 struct mlx5_cmd_mailbox *next;
1129 copy = min_t(int, size, sizeof(from->first.data));
1130 memcpy(to, from->first.data, copy);
1141 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1144 memcpy(to, block->data, copy);
1153 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1156 struct mlx5_cmd_mailbox *mailbox;
1158 mailbox = kmalloc(sizeof(*mailbox), flags);
1160 return ERR_PTR(-ENOMEM);
1162 mailbox->buf = dma_pool_zalloc(dev->cmd.pool, flags,
1164 if (!mailbox->buf) {
1165 mlx5_core_dbg(dev, "failed allocation\n");
1167 return ERR_PTR(-ENOMEM);
1169 mailbox->next = NULL;
1174 static void free_cmd_box(struct mlx5_core_dev *dev,
1175 struct mlx5_cmd_mailbox *mailbox)
1177 dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1181 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1182 gfp_t flags, int size,
1185 struct mlx5_cmd_mailbox *tmp, *head = NULL;
1186 struct mlx5_cmd_prot_block *block;
1187 struct mlx5_cmd_msg *msg;
1192 msg = kzalloc(sizeof(*msg), flags);
1194 return ERR_PTR(-ENOMEM);
1197 n = mlx5_calc_cmd_blocks(msg);
1199 for (i = 0; i < n; i++) {
1200 tmp = alloc_cmd_box(dev, flags);
1202 mlx5_core_warn(dev, "failed allocating block\n");
1209 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1210 block->block_num = cpu_to_be32(n - i - 1);
1211 block->token = token;
1220 free_cmd_box(dev, head);
1225 return ERR_PTR(err);
1228 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1229 struct mlx5_cmd_msg *msg)
1231 struct mlx5_cmd_mailbox *head = msg->next;
1232 struct mlx5_cmd_mailbox *next;
1236 free_cmd_box(dev, head);
1242 static ssize_t data_write(struct file *filp, const char __user *buf,
1243 size_t count, loff_t *pos)
1245 struct mlx5_core_dev *dev = filp->private_data;
1246 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1255 ptr = memdup_user(buf, count);
1257 return PTR_ERR(ptr);
1266 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1269 struct mlx5_core_dev *dev = filp->private_data;
1270 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1275 return simple_read_from_buffer(buf, count, pos, dbg->out_msg,
1279 static const struct file_operations dfops = {
1280 .owner = THIS_MODULE,
1281 .open = simple_open,
1282 .write = data_write,
1286 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1289 struct mlx5_core_dev *dev = filp->private_data;
1290 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1294 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1298 return simple_read_from_buffer(buf, count, pos, outlen, err);
1301 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1302 size_t count, loff_t *pos)
1304 struct mlx5_core_dev *dev = filp->private_data;
1305 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1306 char outlen_str[8] = {0};
1311 if (*pos != 0 || count > 6)
1314 kfree(dbg->out_msg);
1315 dbg->out_msg = NULL;
1318 if (copy_from_user(outlen_str, buf, count))
1321 err = sscanf(outlen_str, "%d", &outlen);
1325 ptr = kzalloc(outlen, GFP_KERNEL);
1330 dbg->outlen = outlen;
1337 static const struct file_operations olfops = {
1338 .owner = THIS_MODULE,
1339 .open = simple_open,
1340 .write = outlen_write,
1341 .read = outlen_read,
1344 static void set_wqname(struct mlx5_core_dev *dev)
1346 struct mlx5_cmd *cmd = &dev->cmd;
1348 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1349 dev_name(&dev->pdev->dev));
1352 static void clean_debug_files(struct mlx5_core_dev *dev)
1354 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1356 if (!mlx5_debugfs_root)
1359 mlx5_cmdif_debugfs_cleanup(dev);
1360 debugfs_remove_recursive(dbg->dbg_root);
1363 static int create_debugfs_files(struct mlx5_core_dev *dev)
1365 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1368 if (!mlx5_debugfs_root)
1371 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1375 dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1380 dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1385 dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1387 if (!dbg->dbg_outlen)
1390 dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1392 if (!dbg->dbg_status)
1395 dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1399 mlx5_cmdif_debugfs_init(dev);
1404 clean_debug_files(dev);
1408 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1410 struct mlx5_cmd *cmd = &dev->cmd;
1413 for (i = 0; i < cmd->max_reg_cmds; i++)
1415 down(&cmd->pages_sem);
1419 up(&cmd->pages_sem);
1420 for (i = 0; i < cmd->max_reg_cmds; i++)
1424 static int cmd_comp_notifier(struct notifier_block *nb,
1425 unsigned long type, void *data)
1427 struct mlx5_core_dev *dev;
1428 struct mlx5_cmd *cmd;
1429 struct mlx5_eqe *eqe;
1431 cmd = mlx5_nb_cof(nb, struct mlx5_cmd, nb);
1432 dev = container_of(cmd, struct mlx5_core_dev, cmd);
1435 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector), false);
1439 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1441 MLX5_NB_INIT(&dev->cmd.nb, cmd_comp_notifier, CMD);
1442 mlx5_eq_notifier_register(dev, &dev->cmd.nb);
1443 mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1446 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1448 mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1449 mlx5_eq_notifier_unregister(dev, &dev->cmd.nb);
1452 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1454 unsigned long flags;
1457 spin_lock_irqsave(&msg->parent->lock, flags);
1458 list_add_tail(&msg->list, &msg->parent->head);
1459 spin_unlock_irqrestore(&msg->parent->lock, flags);
1461 mlx5_free_cmd_msg(dev, msg);
1465 static void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1467 struct mlx5_cmd *cmd = &dev->cmd;
1468 struct mlx5_cmd_work_ent *ent;
1469 mlx5_cmd_cbk_t callback;
1474 struct mlx5_cmd_stats *stats;
1475 unsigned long flags;
1476 unsigned long vector;
1478 /* there can be at most 32 command queues */
1479 vector = vec & 0xffffffff;
1480 for (i = 0; i < (1 << cmd->log_sz); i++) {
1481 if (test_bit(i, &vector)) {
1482 struct semaphore *sem;
1484 ent = cmd->ent_arr[i];
1486 /* if we already completed the command, ignore it */
1487 if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1489 /* only real completion can free the cmd slot */
1491 mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1493 free_ent(cmd, ent->idx);
1500 cancel_delayed_work(&ent->cb_timeout_work);
1501 if (ent->page_queue)
1502 sem = &cmd->pages_sem;
1505 ent->ts2 = ktime_get_ns();
1506 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1507 dump_command(dev, ent, 0);
1509 if (!cmd->checksum_disabled)
1510 ent->ret = verify_signature(ent);
1513 if (vec & MLX5_TRIGGERED_CMD_COMP)
1514 ent->status = MLX5_DRIVER_STATUS_ABORTED;
1516 ent->status = ent->lay->status_own >> 1;
1518 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1519 ent->ret, deliv_status_to_str(ent->status), ent->status);
1522 /* only real completion will free the entry slot */
1524 free_ent(cmd, ent->idx);
1526 if (ent->callback) {
1527 ds = ent->ts2 - ent->ts1;
1528 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1529 stats = &cmd->stats[ent->op];
1530 spin_lock_irqsave(&stats->lock, flags);
1533 spin_unlock_irqrestore(&stats->lock, flags);
1536 callback = ent->callback;
1537 context = ent->context;
1540 err = mlx5_copy_from_msg(ent->uout,
1544 err = err ? err : mlx5_cmd_check(dev,
1545 ent->in->first.data,
1549 mlx5_free_cmd_msg(dev, ent->out);
1550 free_msg(dev, ent->in);
1552 err = err ? err : ent->status;
1555 callback(err, context);
1557 complete(&ent->done);
1564 void mlx5_cmd_trigger_completions(struct mlx5_core_dev *dev)
1566 unsigned long flags;
1569 /* wait for pending handlers to complete */
1570 mlx5_eq_synchronize_cmd_irq(dev);
1571 spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
1572 vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
1576 vector |= MLX5_TRIGGERED_CMD_COMP;
1577 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1579 mlx5_core_dbg(dev, "vector 0x%llx\n", vector);
1580 mlx5_cmd_comp_handler(dev, vector, true);
1584 spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1587 void mlx5_cmd_flush(struct mlx5_core_dev *dev)
1589 struct mlx5_cmd *cmd = &dev->cmd;
1592 for (i = 0; i < cmd->max_reg_cmds; i++)
1593 while (down_trylock(&cmd->sem))
1594 mlx5_cmd_trigger_completions(dev);
1596 while (down_trylock(&cmd->pages_sem))
1597 mlx5_cmd_trigger_completions(dev);
1600 up(&cmd->pages_sem);
1601 for (i = 0; i < cmd->max_reg_cmds; i++)
1605 static int status_to_err(u8 status)
1607 return status ? -1 : 0; /* TBD more meaningful codes */
1610 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1613 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1614 struct cmd_msg_cache *ch = NULL;
1615 struct mlx5_cmd *cmd = &dev->cmd;
1621 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1622 ch = &cmd->cache[i];
1623 if (in_size > ch->max_inbox_size)
1625 spin_lock_irq(&ch->lock);
1626 if (list_empty(&ch->head)) {
1627 spin_unlock_irq(&ch->lock);
1630 msg = list_entry(ch->head.next, typeof(*msg), list);
1631 /* For cached lists, we must explicitly state what is
1635 list_del(&msg->list);
1636 spin_unlock_irq(&ch->lock);
1644 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1648 static int is_manage_pages(void *in)
1650 return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1653 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1654 int out_size, mlx5_cmd_cbk_t callback, void *context,
1657 struct mlx5_cmd_msg *inb;
1658 struct mlx5_cmd_msg *outb;
1666 if (pci_channel_offline(dev->pdev) ||
1667 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1668 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1670 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1671 MLX5_SET(mbox_out, out, status, status);
1672 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1676 pages_queue = is_manage_pages(in);
1677 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1679 inb = alloc_msg(dev, in_size, gfp);
1685 token = alloc_token(&dev->cmd);
1687 err = mlx5_copy_to_msg(inb, in, in_size, token);
1689 mlx5_core_warn(dev, "err %d\n", err);
1693 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1695 err = PTR_ERR(outb);
1699 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1700 pages_queue, &status, token, force_polling);
1704 mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1706 err = status_to_err(status);
1711 err = mlx5_copy_from_msg(out, outb, out_size);
1715 mlx5_free_cmd_msg(dev, outb);
1723 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1728 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1729 return err ? : mlx5_cmd_check(dev, in, out);
1731 EXPORT_SYMBOL(mlx5_cmd_exec);
1733 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
1734 struct mlx5_async_ctx *ctx)
1737 /* Starts at 1 to avoid doing wake_up if we are not cleaning up */
1738 atomic_set(&ctx->num_inflight, 1);
1739 init_waitqueue_head(&ctx->wait);
1741 EXPORT_SYMBOL(mlx5_cmd_init_async_ctx);
1744 * mlx5_cmd_cleanup_async_ctx - Clean up an async_ctx
1745 * @ctx: The ctx to clean
1747 * Upon return all callbacks given to mlx5_cmd_exec_cb() have been called. The
1748 * caller must ensure that mlx5_cmd_exec_cb() is not called during or after
1749 * the call mlx5_cleanup_async_ctx().
1751 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx)
1753 atomic_dec(&ctx->num_inflight);
1754 wait_event(ctx->wait, atomic_read(&ctx->num_inflight) == 0);
1756 EXPORT_SYMBOL(mlx5_cmd_cleanup_async_ctx);
1758 static void mlx5_cmd_exec_cb_handler(int status, void *_work)
1760 struct mlx5_async_work *work = _work;
1761 struct mlx5_async_ctx *ctx = work->ctx;
1763 work->user_callback(status, work);
1764 if (atomic_dec_and_test(&ctx->num_inflight))
1765 wake_up(&ctx->wait);
1768 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
1769 void *out, int out_size, mlx5_async_cbk_t callback,
1770 struct mlx5_async_work *work)
1775 work->user_callback = callback;
1776 if (WARN_ON(!atomic_inc_not_zero(&ctx->num_inflight)))
1778 ret = cmd_exec(ctx->dev, in, in_size, out, out_size,
1779 mlx5_cmd_exec_cb_handler, work, false);
1780 if (ret && atomic_dec_and_test(&ctx->num_inflight))
1781 wake_up(&ctx->wait);
1785 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1787 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1788 void *out, int out_size)
1792 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1794 return err ? : mlx5_cmd_check(dev, in, out);
1796 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1798 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1800 struct cmd_msg_cache *ch;
1801 struct mlx5_cmd_msg *msg;
1802 struct mlx5_cmd_msg *n;
1805 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1806 ch = &dev->cmd.cache[i];
1807 list_for_each_entry_safe(msg, n, &ch->head, list) {
1808 list_del(&msg->list);
1809 mlx5_free_cmd_msg(dev, msg);
1814 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1818 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1819 16 + MLX5_CMD_DATA_BLOCK_SIZE,
1820 16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1821 16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1822 16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1823 16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1826 static void create_msg_cache(struct mlx5_core_dev *dev)
1828 struct mlx5_cmd *cmd = &dev->cmd;
1829 struct cmd_msg_cache *ch;
1830 struct mlx5_cmd_msg *msg;
1834 /* Initialize and fill the caches with initial entries */
1835 for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1836 ch = &cmd->cache[k];
1837 spin_lock_init(&ch->lock);
1838 INIT_LIST_HEAD(&ch->head);
1839 ch->num_ent = cmd_cache_num_ent[k];
1840 ch->max_inbox_size = cmd_cache_ent_size[k];
1841 for (i = 0; i < ch->num_ent; i++) {
1842 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1843 ch->max_inbox_size, 0);
1847 list_add_tail(&msg->list, &ch->head);
1852 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1854 struct device *ddev = &dev->pdev->dev;
1856 cmd->cmd_alloc_buf = dma_alloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1857 &cmd->alloc_dma, GFP_KERNEL);
1858 if (!cmd->cmd_alloc_buf)
1861 /* make sure it is aligned to 4K */
1862 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1863 cmd->cmd_buf = cmd->cmd_alloc_buf;
1864 cmd->dma = cmd->alloc_dma;
1865 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1869 dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1871 cmd->cmd_alloc_buf = dma_alloc_coherent(ddev,
1872 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1873 &cmd->alloc_dma, GFP_KERNEL);
1874 if (!cmd->cmd_alloc_buf)
1877 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1878 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1879 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1883 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1885 struct device *ddev = &dev->pdev->dev;
1887 dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1891 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1893 int size = sizeof(struct mlx5_cmd_prot_block);
1894 int align = roundup_pow_of_two(size);
1895 struct mlx5_cmd *cmd = &dev->cmd;
1901 memset(cmd, 0, sizeof(*cmd));
1902 cmd_if_rev = cmdif_rev(dev);
1903 if (cmd_if_rev != CMD_IF_REV) {
1904 dev_err(&dev->pdev->dev,
1905 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1906 CMD_IF_REV, cmd_if_rev);
1910 cmd->pool = dma_pool_create("mlx5_cmd", &dev->pdev->dev, size, align,
1915 err = alloc_cmd_page(dev, cmd);
1919 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1920 cmd->log_sz = cmd_l >> 4 & 0xf;
1921 cmd->log_stride = cmd_l & 0xf;
1922 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1923 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1929 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1930 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1935 cmd->checksum_disabled = 1;
1936 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1937 cmd->bitmask = (1UL << cmd->max_reg_cmds) - 1;
1939 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1940 if (cmd->cmdif_rev > CMD_IF_REV) {
1941 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1942 CMD_IF_REV, cmd->cmdif_rev);
1947 spin_lock_init(&cmd->alloc_lock);
1948 spin_lock_init(&cmd->token_lock);
1949 for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1950 spin_lock_init(&cmd->stats[i].lock);
1952 sema_init(&cmd->sem, cmd->max_reg_cmds);
1953 sema_init(&cmd->pages_sem, 1);
1955 cmd_h = (u32)((u64)(cmd->dma) >> 32);
1956 cmd_l = (u32)(cmd->dma);
1957 if (cmd_l & 0xfff) {
1958 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1963 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1964 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1966 /* Make sure firmware sees the complete address before we proceed */
1969 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1971 cmd->mode = CMD_MODE_POLLING;
1973 create_msg_cache(dev);
1976 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1978 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1983 err = create_debugfs_files(dev);
1992 destroy_workqueue(cmd->wq);
1995 destroy_msg_cache(dev);
1998 free_cmd_page(dev, cmd);
2001 dma_pool_destroy(cmd->pool);
2005 EXPORT_SYMBOL(mlx5_cmd_init);
2007 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
2009 struct mlx5_cmd *cmd = &dev->cmd;
2011 clean_debug_files(dev);
2012 destroy_workqueue(cmd->wq);
2013 destroy_msg_cache(dev);
2014 free_cmd_page(dev, cmd);
2015 dma_pool_destroy(cmd->pool);
2017 EXPORT_SYMBOL(mlx5_cmd_cleanup);