2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/debugfs.h>
45 #include "mlx5_core.h"
57 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
58 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
59 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
60 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
61 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
62 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
63 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
64 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
65 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
66 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
67 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
70 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
71 struct mlx5_cmd_msg *in,
72 struct mlx5_cmd_msg *out,
73 void *uout, int uout_size,
75 void *context, int page_queue)
77 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
78 struct mlx5_cmd_work_ent *ent;
80 ent = kzalloc(sizeof(*ent), alloc_flags);
82 return ERR_PTR(-ENOMEM);
87 ent->uout_size = uout_size;
89 ent->context = context;
91 ent->page_queue = page_queue;
96 static u8 alloc_token(struct mlx5_cmd *cmd)
100 spin_lock(&cmd->token_lock);
105 spin_unlock(&cmd->token_lock);
110 static int alloc_ent(struct mlx5_cmd *cmd)
115 spin_lock_irqsave(&cmd->alloc_lock, flags);
116 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
117 if (ret < cmd->max_reg_cmds)
118 clear_bit(ret, &cmd->bitmask);
119 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
121 return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
124 static void free_ent(struct mlx5_cmd *cmd, int idx)
128 spin_lock_irqsave(&cmd->alloc_lock, flags);
129 set_bit(idx, &cmd->bitmask);
130 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
133 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
135 return cmd->cmd_buf + (idx << cmd->log_stride);
138 static u8 xor8_buf(void *buf, size_t offset, int len)
143 int end = len + offset;
145 for (i = offset; i < end; i++)
151 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
153 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
154 int xor_len = sizeof(*block) - sizeof(block->data) - 1;
156 if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
159 if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
165 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
167 int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
168 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
170 block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
171 block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
174 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
176 struct mlx5_cmd_mailbox *next = msg->next;
178 int blen = size - min_t(int, sizeof(msg->first.data), size);
179 int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
180 / MLX5_CMD_DATA_BLOCK_SIZE;
183 for (i = 0; i < n && next; i++) {
184 calc_block_sig(next->buf);
189 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
191 ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay));
193 calc_chain_sig(ent->in);
194 calc_chain_sig(ent->out);
198 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
200 unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
204 own = ent->lay->status_own;
205 if (!(own & CMD_OWNER_HW)) {
209 usleep_range(5000, 10000);
210 } while (time_before(jiffies, poll_end));
212 ent->ret = -ETIMEDOUT;
215 static void free_cmd(struct mlx5_cmd_work_ent *ent)
220 static int verify_signature(struct mlx5_cmd_work_ent *ent)
222 struct mlx5_cmd_mailbox *next = ent->out->next;
225 int size = ent->out->len;
226 int blen = size - min_t(int, sizeof(ent->out->first.data), size);
227 int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
228 / MLX5_CMD_DATA_BLOCK_SIZE;
231 sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
235 for (i = 0; i < n && next; i++) {
236 err = verify_block_sig(next->buf);
246 static void dump_buf(void *buf, int size, int data_only, int offset)
251 for (i = 0; i < size; i += 16) {
252 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
253 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
262 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
263 u32 *synd, u8 *status)
269 case MLX5_CMD_OP_TEARDOWN_HCA:
270 case MLX5_CMD_OP_DISABLE_HCA:
271 case MLX5_CMD_OP_MANAGE_PAGES:
272 case MLX5_CMD_OP_DESTROY_MKEY:
273 case MLX5_CMD_OP_DESTROY_EQ:
274 case MLX5_CMD_OP_DESTROY_CQ:
275 case MLX5_CMD_OP_DESTROY_QP:
276 case MLX5_CMD_OP_DESTROY_PSV:
277 case MLX5_CMD_OP_DESTROY_SRQ:
278 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
279 case MLX5_CMD_OP_DESTROY_DCT:
280 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
281 case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
282 case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
283 case MLX5_CMD_OP_DEALLOC_PD:
284 case MLX5_CMD_OP_DEALLOC_UAR:
285 case MLX5_CMD_OP_DETACH_FROM_MCG:
286 case MLX5_CMD_OP_DEALLOC_XRCD:
287 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
288 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
289 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
290 case MLX5_CMD_OP_DESTROY_LAG:
291 case MLX5_CMD_OP_DESTROY_VPORT_LAG:
292 case MLX5_CMD_OP_DESTROY_TIR:
293 case MLX5_CMD_OP_DESTROY_SQ:
294 case MLX5_CMD_OP_DESTROY_RQ:
295 case MLX5_CMD_OP_DESTROY_RMP:
296 case MLX5_CMD_OP_DESTROY_TIS:
297 case MLX5_CMD_OP_DESTROY_RQT:
298 case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
299 case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
300 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
301 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
302 case MLX5_CMD_OP_2ERR_QP:
303 case MLX5_CMD_OP_2RST_QP:
304 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
305 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
306 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
307 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
308 case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
309 case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
310 case MLX5_CMD_OP_FPGA_DESTROY_QP:
311 return MLX5_CMD_STAT_OK;
313 case MLX5_CMD_OP_QUERY_HCA_CAP:
314 case MLX5_CMD_OP_QUERY_ADAPTER:
315 case MLX5_CMD_OP_INIT_HCA:
316 case MLX5_CMD_OP_ENABLE_HCA:
317 case MLX5_CMD_OP_QUERY_PAGES:
318 case MLX5_CMD_OP_SET_HCA_CAP:
319 case MLX5_CMD_OP_QUERY_ISSI:
320 case MLX5_CMD_OP_SET_ISSI:
321 case MLX5_CMD_OP_CREATE_MKEY:
322 case MLX5_CMD_OP_QUERY_MKEY:
323 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
324 case MLX5_CMD_OP_PAGE_FAULT_RESUME:
325 case MLX5_CMD_OP_CREATE_EQ:
326 case MLX5_CMD_OP_QUERY_EQ:
327 case MLX5_CMD_OP_GEN_EQE:
328 case MLX5_CMD_OP_CREATE_CQ:
329 case MLX5_CMD_OP_QUERY_CQ:
330 case MLX5_CMD_OP_MODIFY_CQ:
331 case MLX5_CMD_OP_CREATE_QP:
332 case MLX5_CMD_OP_RST2INIT_QP:
333 case MLX5_CMD_OP_INIT2RTR_QP:
334 case MLX5_CMD_OP_RTR2RTS_QP:
335 case MLX5_CMD_OP_RTS2RTS_QP:
336 case MLX5_CMD_OP_SQERR2RTS_QP:
337 case MLX5_CMD_OP_QUERY_QP:
338 case MLX5_CMD_OP_SQD_RTS_QP:
339 case MLX5_CMD_OP_INIT2INIT_QP:
340 case MLX5_CMD_OP_CREATE_PSV:
341 case MLX5_CMD_OP_CREATE_SRQ:
342 case MLX5_CMD_OP_QUERY_SRQ:
343 case MLX5_CMD_OP_ARM_RQ:
344 case MLX5_CMD_OP_CREATE_XRC_SRQ:
345 case MLX5_CMD_OP_QUERY_XRC_SRQ:
346 case MLX5_CMD_OP_ARM_XRC_SRQ:
347 case MLX5_CMD_OP_CREATE_DCT:
348 case MLX5_CMD_OP_DRAIN_DCT:
349 case MLX5_CMD_OP_QUERY_DCT:
350 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
351 case MLX5_CMD_OP_QUERY_VPORT_STATE:
352 case MLX5_CMD_OP_MODIFY_VPORT_STATE:
353 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
354 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
355 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
356 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
357 case MLX5_CMD_OP_SET_ROCE_ADDRESS:
358 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
359 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
360 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
361 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
362 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
363 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
364 case MLX5_CMD_OP_QUERY_Q_COUNTER:
365 case MLX5_CMD_OP_SET_RATE_LIMIT:
366 case MLX5_CMD_OP_QUERY_RATE_LIMIT:
367 case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
368 case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
369 case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
370 case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
371 case MLX5_CMD_OP_ALLOC_PD:
372 case MLX5_CMD_OP_ALLOC_UAR:
373 case MLX5_CMD_OP_CONFIG_INT_MODERATION:
374 case MLX5_CMD_OP_ACCESS_REG:
375 case MLX5_CMD_OP_ATTACH_TO_MCG:
376 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
377 case MLX5_CMD_OP_MAD_IFC:
378 case MLX5_CMD_OP_QUERY_MAD_DEMUX:
379 case MLX5_CMD_OP_SET_MAD_DEMUX:
380 case MLX5_CMD_OP_NOP:
381 case MLX5_CMD_OP_ALLOC_XRCD:
382 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
383 case MLX5_CMD_OP_QUERY_CONG_STATUS:
384 case MLX5_CMD_OP_MODIFY_CONG_STATUS:
385 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
386 case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
387 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
388 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
389 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
390 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
391 case MLX5_CMD_OP_CREATE_LAG:
392 case MLX5_CMD_OP_MODIFY_LAG:
393 case MLX5_CMD_OP_QUERY_LAG:
394 case MLX5_CMD_OP_CREATE_VPORT_LAG:
395 case MLX5_CMD_OP_CREATE_TIR:
396 case MLX5_CMD_OP_MODIFY_TIR:
397 case MLX5_CMD_OP_QUERY_TIR:
398 case MLX5_CMD_OP_CREATE_SQ:
399 case MLX5_CMD_OP_MODIFY_SQ:
400 case MLX5_CMD_OP_QUERY_SQ:
401 case MLX5_CMD_OP_CREATE_RQ:
402 case MLX5_CMD_OP_MODIFY_RQ:
403 case MLX5_CMD_OP_QUERY_RQ:
404 case MLX5_CMD_OP_CREATE_RMP:
405 case MLX5_CMD_OP_MODIFY_RMP:
406 case MLX5_CMD_OP_QUERY_RMP:
407 case MLX5_CMD_OP_CREATE_TIS:
408 case MLX5_CMD_OP_MODIFY_TIS:
409 case MLX5_CMD_OP_QUERY_TIS:
410 case MLX5_CMD_OP_CREATE_RQT:
411 case MLX5_CMD_OP_MODIFY_RQT:
412 case MLX5_CMD_OP_QUERY_RQT:
414 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
415 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
416 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
417 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
418 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
419 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
420 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
421 case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
422 case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
423 case MLX5_CMD_OP_FPGA_CREATE_QP:
424 case MLX5_CMD_OP_FPGA_MODIFY_QP:
425 case MLX5_CMD_OP_FPGA_QUERY_QP:
426 case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
427 *status = MLX5_DRIVER_STATUS_ABORTED;
428 *synd = MLX5_DRIVER_SYND;
431 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
436 const char *mlx5_command_str(int command)
438 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
441 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
442 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
443 MLX5_COMMAND_STR_CASE(INIT_HCA);
444 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
445 MLX5_COMMAND_STR_CASE(ENABLE_HCA);
446 MLX5_COMMAND_STR_CASE(DISABLE_HCA);
447 MLX5_COMMAND_STR_CASE(QUERY_PAGES);
448 MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
449 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
450 MLX5_COMMAND_STR_CASE(QUERY_ISSI);
451 MLX5_COMMAND_STR_CASE(SET_ISSI);
452 MLX5_COMMAND_STR_CASE(CREATE_MKEY);
453 MLX5_COMMAND_STR_CASE(QUERY_MKEY);
454 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
455 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
456 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
457 MLX5_COMMAND_STR_CASE(CREATE_EQ);
458 MLX5_COMMAND_STR_CASE(DESTROY_EQ);
459 MLX5_COMMAND_STR_CASE(QUERY_EQ);
460 MLX5_COMMAND_STR_CASE(GEN_EQE);
461 MLX5_COMMAND_STR_CASE(CREATE_CQ);
462 MLX5_COMMAND_STR_CASE(DESTROY_CQ);
463 MLX5_COMMAND_STR_CASE(QUERY_CQ);
464 MLX5_COMMAND_STR_CASE(MODIFY_CQ);
465 MLX5_COMMAND_STR_CASE(CREATE_QP);
466 MLX5_COMMAND_STR_CASE(DESTROY_QP);
467 MLX5_COMMAND_STR_CASE(RST2INIT_QP);
468 MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
469 MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
470 MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
471 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
472 MLX5_COMMAND_STR_CASE(2ERR_QP);
473 MLX5_COMMAND_STR_CASE(2RST_QP);
474 MLX5_COMMAND_STR_CASE(QUERY_QP);
475 MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
476 MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
477 MLX5_COMMAND_STR_CASE(CREATE_PSV);
478 MLX5_COMMAND_STR_CASE(DESTROY_PSV);
479 MLX5_COMMAND_STR_CASE(CREATE_SRQ);
480 MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
481 MLX5_COMMAND_STR_CASE(QUERY_SRQ);
482 MLX5_COMMAND_STR_CASE(ARM_RQ);
483 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
484 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
485 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
486 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
487 MLX5_COMMAND_STR_CASE(CREATE_DCT);
488 MLX5_COMMAND_STR_CASE(DESTROY_DCT);
489 MLX5_COMMAND_STR_CASE(DRAIN_DCT);
490 MLX5_COMMAND_STR_CASE(QUERY_DCT);
491 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
492 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
493 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
494 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
495 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
496 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
497 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
498 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
499 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
500 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
501 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
502 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
503 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
504 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
505 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
506 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
507 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
508 MLX5_COMMAND_STR_CASE(SET_RATE_LIMIT);
509 MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
510 MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
511 MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
512 MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
513 MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
514 MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
515 MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
516 MLX5_COMMAND_STR_CASE(ALLOC_PD);
517 MLX5_COMMAND_STR_CASE(DEALLOC_PD);
518 MLX5_COMMAND_STR_CASE(ALLOC_UAR);
519 MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
520 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
521 MLX5_COMMAND_STR_CASE(ACCESS_REG);
522 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
523 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
524 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
525 MLX5_COMMAND_STR_CASE(MAD_IFC);
526 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
527 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
528 MLX5_COMMAND_STR_CASE(NOP);
529 MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
530 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
531 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
532 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
533 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
534 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
535 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
536 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
537 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
538 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
539 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
540 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
541 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
542 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
543 MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
544 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
545 MLX5_COMMAND_STR_CASE(CREATE_LAG);
546 MLX5_COMMAND_STR_CASE(MODIFY_LAG);
547 MLX5_COMMAND_STR_CASE(QUERY_LAG);
548 MLX5_COMMAND_STR_CASE(DESTROY_LAG);
549 MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
550 MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
551 MLX5_COMMAND_STR_CASE(CREATE_TIR);
552 MLX5_COMMAND_STR_CASE(MODIFY_TIR);
553 MLX5_COMMAND_STR_CASE(DESTROY_TIR);
554 MLX5_COMMAND_STR_CASE(QUERY_TIR);
555 MLX5_COMMAND_STR_CASE(CREATE_SQ);
556 MLX5_COMMAND_STR_CASE(MODIFY_SQ);
557 MLX5_COMMAND_STR_CASE(DESTROY_SQ);
558 MLX5_COMMAND_STR_CASE(QUERY_SQ);
559 MLX5_COMMAND_STR_CASE(CREATE_RQ);
560 MLX5_COMMAND_STR_CASE(MODIFY_RQ);
561 MLX5_COMMAND_STR_CASE(DESTROY_RQ);
562 MLX5_COMMAND_STR_CASE(QUERY_RQ);
563 MLX5_COMMAND_STR_CASE(CREATE_RMP);
564 MLX5_COMMAND_STR_CASE(MODIFY_RMP);
565 MLX5_COMMAND_STR_CASE(DESTROY_RMP);
566 MLX5_COMMAND_STR_CASE(QUERY_RMP);
567 MLX5_COMMAND_STR_CASE(CREATE_TIS);
568 MLX5_COMMAND_STR_CASE(MODIFY_TIS);
569 MLX5_COMMAND_STR_CASE(DESTROY_TIS);
570 MLX5_COMMAND_STR_CASE(QUERY_TIS);
571 MLX5_COMMAND_STR_CASE(CREATE_RQT);
572 MLX5_COMMAND_STR_CASE(MODIFY_RQT);
573 MLX5_COMMAND_STR_CASE(DESTROY_RQT);
574 MLX5_COMMAND_STR_CASE(QUERY_RQT);
575 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
576 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
577 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
578 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
579 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
580 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
581 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
582 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
583 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
584 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
585 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
586 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
587 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
588 MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
589 MLX5_COMMAND_STR_CASE(ALLOC_ENCAP_HEADER);
590 MLX5_COMMAND_STR_CASE(DEALLOC_ENCAP_HEADER);
591 MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
592 MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
593 MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
594 MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
595 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
596 MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
597 MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
598 default: return "unknown command opcode";
602 static const char *cmd_status_str(u8 status)
605 case MLX5_CMD_STAT_OK:
607 case MLX5_CMD_STAT_INT_ERR:
608 return "internal error";
609 case MLX5_CMD_STAT_BAD_OP_ERR:
610 return "bad operation";
611 case MLX5_CMD_STAT_BAD_PARAM_ERR:
612 return "bad parameter";
613 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
614 return "bad system state";
615 case MLX5_CMD_STAT_BAD_RES_ERR:
616 return "bad resource";
617 case MLX5_CMD_STAT_RES_BUSY:
618 return "resource busy";
619 case MLX5_CMD_STAT_LIM_ERR:
620 return "limits exceeded";
621 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
622 return "bad resource state";
623 case MLX5_CMD_STAT_IX_ERR:
625 case MLX5_CMD_STAT_NO_RES_ERR:
626 return "no resources";
627 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
628 return "bad input length";
629 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
630 return "bad output length";
631 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
632 return "bad QP state";
633 case MLX5_CMD_STAT_BAD_PKT_ERR:
634 return "bad packet (discarded)";
635 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
636 return "bad size too many outstanding CQEs";
638 return "unknown status";
642 static int cmd_status_to_err(u8 status)
645 case MLX5_CMD_STAT_OK: return 0;
646 case MLX5_CMD_STAT_INT_ERR: return -EIO;
647 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
648 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
649 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
650 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
651 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
652 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
653 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
654 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
655 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
656 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
657 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
658 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
659 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
660 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
661 default: return -EIO;
665 struct mlx5_ifc_mbox_out_bits {
667 u8 reserved_at_8[0x18];
671 u8 reserved_at_40[0x40];
674 struct mlx5_ifc_mbox_in_bits {
676 u8 reserved_at_10[0x10];
678 u8 reserved_at_20[0x10];
681 u8 reserved_at_40[0x40];
684 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
686 *status = MLX5_GET(mbox_out, out, status);
687 *syndrome = MLX5_GET(mbox_out, out, syndrome);
690 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
697 mlx5_cmd_mbox_status(out, &status, &syndrome);
701 opcode = MLX5_GET(mbox_in, in, opcode);
702 op_mod = MLX5_GET(mbox_in, in, op_mod);
705 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
706 mlx5_command_str(opcode),
708 cmd_status_str(status),
712 return cmd_status_to_err(status);
715 static void dump_command(struct mlx5_core_dev *dev,
716 struct mlx5_cmd_work_ent *ent, int input)
718 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
719 u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
720 struct mlx5_cmd_mailbox *next = msg->next;
725 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
728 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
729 "dump command data %s(0x%x) %s\n",
730 mlx5_command_str(op), op,
731 input ? "INPUT" : "OUTPUT");
733 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
734 mlx5_command_str(op), op,
735 input ? "INPUT" : "OUTPUT");
739 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
740 offset += sizeof(ent->lay->in);
742 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
743 offset += sizeof(ent->lay->out);
746 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
747 offset += sizeof(*ent->lay);
750 while (next && offset < msg->len) {
752 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
753 dump_buf(next->buf, dump_len, 1, offset);
754 offset += MLX5_CMD_DATA_BLOCK_SIZE;
756 mlx5_core_dbg(dev, "command block:\n");
757 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
758 offset += sizeof(struct mlx5_cmd_prot_block);
767 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
769 return MLX5_GET(mbox_in, in->first.data, opcode);
772 static void cb_timeout_handler(struct work_struct *work)
774 struct delayed_work *dwork = container_of(work, struct delayed_work,
776 struct mlx5_cmd_work_ent *ent = container_of(dwork,
777 struct mlx5_cmd_work_ent,
779 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
782 ent->ret = -ETIMEDOUT;
783 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
784 mlx5_command_str(msg_to_opcode(ent->in)),
785 msg_to_opcode(ent->in));
786 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
789 static void cmd_work_handler(struct work_struct *work)
791 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
792 struct mlx5_cmd *cmd = ent->cmd;
793 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
794 unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
795 struct mlx5_cmd_layout *lay;
796 struct semaphore *sem;
798 bool poll_cmd = ent->polling;
801 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
803 if (!ent->page_queue) {
804 ent->idx = alloc_ent(cmd);
806 mlx5_core_err(dev, "failed to allocate command entry\n");
811 ent->idx = cmd->max_reg_cmds;
812 spin_lock_irqsave(&cmd->alloc_lock, flags);
813 clear_bit(ent->idx, &cmd->bitmask);
814 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
817 cmd->ent_arr[ent->idx] = ent;
818 set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
819 lay = get_inst(cmd, ent->idx);
821 memset(lay, 0, sizeof(*lay));
822 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
823 ent->op = be32_to_cpu(lay->in[0]) >> 16;
825 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
826 lay->inlen = cpu_to_be32(ent->in->len);
828 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
829 lay->outlen = cpu_to_be32(ent->out->len);
830 lay->type = MLX5_PCI_CMD_XPORT;
831 lay->token = ent->token;
832 lay->status_own = CMD_OWNER_HW;
833 set_signature(ent, !cmd->checksum_disabled);
834 dump_command(dev, ent, 1);
835 ent->ts1 = ktime_get_ns();
838 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
840 /* Skip sending command to fw if internal error */
841 if (pci_channel_offline(dev->pdev) ||
842 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
846 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
847 MLX5_SET(mbox_out, ent->out, status, status);
848 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
850 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
854 /* ring doorbell after the descriptor is valid */
855 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
857 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
859 /* if not in polling don't use ent after this point */
860 if (cmd->mode == CMD_MODE_POLLING || poll_cmd) {
862 /* make sure we read the descriptor after ownership is SW */
864 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
868 static const char *deliv_status_to_str(u8 status)
871 case MLX5_CMD_DELIVERY_STAT_OK:
873 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
874 return "signature error";
875 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
876 return "token error";
877 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
878 return "bad block number";
879 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
880 return "output pointer not aligned to block size";
881 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
882 return "input pointer not aligned to block size";
883 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
884 return "firmware internal error";
885 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
886 return "command input length error";
887 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
888 return "command output length error";
889 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
890 return "reserved fields not cleared";
891 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
892 return "bad command descriptor type";
894 return "unknown status code";
898 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
900 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
901 struct mlx5_cmd *cmd = &dev->cmd;
904 if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
905 wait_for_completion(&ent->done);
906 } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
907 ent->ret = -ETIMEDOUT;
908 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
913 if (err == -ETIMEDOUT) {
914 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
915 mlx5_command_str(msg_to_opcode(ent->in)),
916 msg_to_opcode(ent->in));
918 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
919 err, deliv_status_to_str(ent->status), ent->status);
925 * 1. Callback functions may not sleep
926 * 2. page queue commands do not support asynchrous completion
928 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
929 struct mlx5_cmd_msg *out, void *uout, int uout_size,
930 mlx5_cmd_cbk_t callback,
931 void *context, int page_queue, u8 *status,
932 u8 token, bool force_polling)
934 struct mlx5_cmd *cmd = &dev->cmd;
935 struct mlx5_cmd_work_ent *ent;
936 struct mlx5_cmd_stats *stats;
941 if (callback && page_queue)
944 ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
950 ent->polling = force_polling;
953 init_completion(&ent->done);
955 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
956 INIT_WORK(&ent->work, cmd_work_handler);
958 cmd_work_handler(&ent->work);
959 } else if (!queue_work(cmd->wq, &ent->work)) {
960 mlx5_core_warn(dev, "failed to queue work\n");
968 err = wait_func(dev, ent);
969 if (err == -ETIMEDOUT)
972 ds = ent->ts2 - ent->ts1;
973 op = MLX5_GET(mbox_in, in->first.data, opcode);
974 if (op < ARRAY_SIZE(cmd->stats)) {
975 stats = &cmd->stats[op];
976 spin_lock_irq(&stats->lock);
979 spin_unlock_irq(&stats->lock);
981 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
982 "fw exec time for %s is %lld nsec\n",
983 mlx5_command_str(op), ds);
984 *status = ent->status;
992 static ssize_t dbg_write(struct file *filp, const char __user *buf,
993 size_t count, loff_t *pos)
995 struct mlx5_core_dev *dev = filp->private_data;
996 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1000 if (!dbg->in_msg || !dbg->out_msg)
1003 if (copy_from_user(lbuf, buf, sizeof(lbuf)))
1006 lbuf[sizeof(lbuf) - 1] = 0;
1008 if (strcmp(lbuf, "go"))
1011 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1013 return err ? err : count;
1016 static const struct file_operations fops = {
1017 .owner = THIS_MODULE,
1018 .open = simple_open,
1022 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1025 struct mlx5_cmd_prot_block *block;
1026 struct mlx5_cmd_mailbox *next;
1032 copy = min_t(int, size, sizeof(to->first.data));
1033 memcpy(to->first.data, from, copy);
1044 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1046 memcpy(block->data, from, copy);
1049 block->token = token;
1056 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1058 struct mlx5_cmd_prot_block *block;
1059 struct mlx5_cmd_mailbox *next;
1065 copy = min_t(int, size, sizeof(from->first.data));
1066 memcpy(to, from->first.data, copy);
1077 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1080 memcpy(to, block->data, copy);
1089 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1092 struct mlx5_cmd_mailbox *mailbox;
1094 mailbox = kmalloc(sizeof(*mailbox), flags);
1096 return ERR_PTR(-ENOMEM);
1098 mailbox->buf = pci_pool_zalloc(dev->cmd.pool, flags,
1100 if (!mailbox->buf) {
1101 mlx5_core_dbg(dev, "failed allocation\n");
1103 return ERR_PTR(-ENOMEM);
1105 mailbox->next = NULL;
1110 static void free_cmd_box(struct mlx5_core_dev *dev,
1111 struct mlx5_cmd_mailbox *mailbox)
1113 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1117 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1118 gfp_t flags, int size,
1121 struct mlx5_cmd_mailbox *tmp, *head = NULL;
1122 struct mlx5_cmd_prot_block *block;
1123 struct mlx5_cmd_msg *msg;
1129 msg = kzalloc(sizeof(*msg), flags);
1131 return ERR_PTR(-ENOMEM);
1133 blen = size - min_t(int, sizeof(msg->first.data), size);
1134 n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
1136 for (i = 0; i < n; i++) {
1137 tmp = alloc_cmd_box(dev, flags);
1139 mlx5_core_warn(dev, "failed allocating block\n");
1146 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1147 block->block_num = cpu_to_be32(n - i - 1);
1148 block->token = token;
1158 free_cmd_box(dev, head);
1163 return ERR_PTR(err);
1166 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1167 struct mlx5_cmd_msg *msg)
1169 struct mlx5_cmd_mailbox *head = msg->next;
1170 struct mlx5_cmd_mailbox *next;
1174 free_cmd_box(dev, head);
1180 static ssize_t data_write(struct file *filp, const char __user *buf,
1181 size_t count, loff_t *pos)
1183 struct mlx5_core_dev *dev = filp->private_data;
1184 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1193 ptr = memdup_user(buf, count);
1195 return PTR_ERR(ptr);
1204 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1207 struct mlx5_core_dev *dev = filp->private_data;
1208 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1217 copy = min_t(int, count, dbg->outlen);
1218 if (copy_to_user(buf, dbg->out_msg, copy))
1226 static const struct file_operations dfops = {
1227 .owner = THIS_MODULE,
1228 .open = simple_open,
1229 .write = data_write,
1233 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1236 struct mlx5_core_dev *dev = filp->private_data;
1237 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1244 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1248 if (copy_to_user(buf, &outlen, err))
1256 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1257 size_t count, loff_t *pos)
1259 struct mlx5_core_dev *dev = filp->private_data;
1260 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1266 if (*pos != 0 || count > 6)
1269 kfree(dbg->out_msg);
1270 dbg->out_msg = NULL;
1273 if (copy_from_user(outlen_str, buf, count))
1278 err = sscanf(outlen_str, "%d", &outlen);
1282 ptr = kzalloc(outlen, GFP_KERNEL);
1287 dbg->outlen = outlen;
1294 static const struct file_operations olfops = {
1295 .owner = THIS_MODULE,
1296 .open = simple_open,
1297 .write = outlen_write,
1298 .read = outlen_read,
1301 static void set_wqname(struct mlx5_core_dev *dev)
1303 struct mlx5_cmd *cmd = &dev->cmd;
1305 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1306 dev_name(&dev->pdev->dev));
1309 static void clean_debug_files(struct mlx5_core_dev *dev)
1311 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1313 if (!mlx5_debugfs_root)
1316 mlx5_cmdif_debugfs_cleanup(dev);
1317 debugfs_remove_recursive(dbg->dbg_root);
1320 static int create_debugfs_files(struct mlx5_core_dev *dev)
1322 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1325 if (!mlx5_debugfs_root)
1328 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1332 dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1337 dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1342 dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1344 if (!dbg->dbg_outlen)
1347 dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1349 if (!dbg->dbg_status)
1352 dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1356 mlx5_cmdif_debugfs_init(dev);
1361 clean_debug_files(dev);
1365 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1367 struct mlx5_cmd *cmd = &dev->cmd;
1370 for (i = 0; i < cmd->max_reg_cmds; i++)
1372 down(&cmd->pages_sem);
1376 up(&cmd->pages_sem);
1377 for (i = 0; i < cmd->max_reg_cmds; i++)
1381 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1383 mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1386 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1388 mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1391 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1393 unsigned long flags;
1396 spin_lock_irqsave(&msg->parent->lock, flags);
1397 list_add_tail(&msg->list, &msg->parent->head);
1398 spin_unlock_irqrestore(&msg->parent->lock, flags);
1400 mlx5_free_cmd_msg(dev, msg);
1404 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1406 struct mlx5_cmd *cmd = &dev->cmd;
1407 struct mlx5_cmd_work_ent *ent;
1408 mlx5_cmd_cbk_t callback;
1413 struct mlx5_cmd_stats *stats;
1414 unsigned long flags;
1415 unsigned long vector;
1417 /* there can be at most 32 command queues */
1418 vector = vec & 0xffffffff;
1419 for (i = 0; i < (1 << cmd->log_sz); i++) {
1420 if (test_bit(i, &vector)) {
1421 struct semaphore *sem;
1423 ent = cmd->ent_arr[i];
1425 /* if we already completed the command, ignore it */
1426 if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1428 /* only real completion can free the cmd slot */
1430 mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1432 free_ent(cmd, ent->idx);
1438 cancel_delayed_work(&ent->cb_timeout_work);
1439 if (ent->page_queue)
1440 sem = &cmd->pages_sem;
1443 ent->ts2 = ktime_get_ns();
1444 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1445 dump_command(dev, ent, 0);
1447 if (!cmd->checksum_disabled)
1448 ent->ret = verify_signature(ent);
1451 if (vec & MLX5_TRIGGERED_CMD_COMP)
1452 ent->status = MLX5_DRIVER_STATUS_ABORTED;
1454 ent->status = ent->lay->status_own >> 1;
1456 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1457 ent->ret, deliv_status_to_str(ent->status), ent->status);
1460 /* only real completion will free the entry slot */
1462 free_ent(cmd, ent->idx);
1464 if (ent->callback) {
1465 ds = ent->ts2 - ent->ts1;
1466 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1467 stats = &cmd->stats[ent->op];
1468 spin_lock_irqsave(&stats->lock, flags);
1471 spin_unlock_irqrestore(&stats->lock, flags);
1474 callback = ent->callback;
1475 context = ent->context;
1478 err = mlx5_copy_from_msg(ent->uout,
1482 err = err ? err : mlx5_cmd_check(dev,
1483 ent->in->first.data,
1487 mlx5_free_cmd_msg(dev, ent->out);
1488 free_msg(dev, ent->in);
1490 err = err ? err : ent->status;
1492 callback(err, context);
1494 complete(&ent->done);
1500 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1502 static int status_to_err(u8 status)
1504 return status ? -1 : 0; /* TBD more meaningful codes */
1507 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1510 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1511 struct cmd_msg_cache *ch = NULL;
1512 struct mlx5_cmd *cmd = &dev->cmd;
1518 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1519 ch = &cmd->cache[i];
1520 if (in_size > ch->max_inbox_size)
1522 spin_lock_irq(&ch->lock);
1523 if (list_empty(&ch->head)) {
1524 spin_unlock_irq(&ch->lock);
1527 msg = list_entry(ch->head.next, typeof(*msg), list);
1528 /* For cached lists, we must explicitly state what is
1532 list_del(&msg->list);
1533 spin_unlock_irq(&ch->lock);
1541 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1545 static int is_manage_pages(void *in)
1547 return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1550 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1551 int out_size, mlx5_cmd_cbk_t callback, void *context,
1554 struct mlx5_cmd_msg *inb;
1555 struct mlx5_cmd_msg *outb;
1563 if (pci_channel_offline(dev->pdev) ||
1564 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1565 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1567 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1568 MLX5_SET(mbox_out, out, status, status);
1569 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1573 pages_queue = is_manage_pages(in);
1574 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1576 inb = alloc_msg(dev, in_size, gfp);
1582 token = alloc_token(&dev->cmd);
1584 err = mlx5_copy_to_msg(inb, in, in_size, token);
1586 mlx5_core_warn(dev, "err %d\n", err);
1590 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1592 err = PTR_ERR(outb);
1596 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1597 pages_queue, &status, token, force_polling);
1601 mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1603 err = status_to_err(status);
1608 err = mlx5_copy_from_msg(out, outb, out_size);
1612 mlx5_free_cmd_msg(dev, outb);
1620 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1625 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1626 return err ? : mlx5_cmd_check(dev, in, out);
1628 EXPORT_SYMBOL(mlx5_cmd_exec);
1630 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1631 void *out, int out_size, mlx5_cmd_cbk_t callback,
1634 return cmd_exec(dev, in, in_size, out, out_size, callback, context,
1637 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1639 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1640 void *out, int out_size)
1644 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1646 return err ? : mlx5_cmd_check(dev, in, out);
1648 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1650 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1652 struct cmd_msg_cache *ch;
1653 struct mlx5_cmd_msg *msg;
1654 struct mlx5_cmd_msg *n;
1657 for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1658 ch = &dev->cmd.cache[i];
1659 list_for_each_entry_safe(msg, n, &ch->head, list) {
1660 list_del(&msg->list);
1661 mlx5_free_cmd_msg(dev, msg);
1666 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1670 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1671 16 + MLX5_CMD_DATA_BLOCK_SIZE,
1672 16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1673 16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1674 16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1675 16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1678 static void create_msg_cache(struct mlx5_core_dev *dev)
1680 struct mlx5_cmd *cmd = &dev->cmd;
1681 struct cmd_msg_cache *ch;
1682 struct mlx5_cmd_msg *msg;
1686 /* Initialize and fill the caches with initial entries */
1687 for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1688 ch = &cmd->cache[k];
1689 spin_lock_init(&ch->lock);
1690 INIT_LIST_HEAD(&ch->head);
1691 ch->num_ent = cmd_cache_num_ent[k];
1692 ch->max_inbox_size = cmd_cache_ent_size[k];
1693 for (i = 0; i < ch->num_ent; i++) {
1694 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1695 ch->max_inbox_size, 0);
1699 list_add_tail(&msg->list, &ch->head);
1704 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1706 struct device *ddev = &dev->pdev->dev;
1708 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1709 &cmd->alloc_dma, GFP_KERNEL);
1710 if (!cmd->cmd_alloc_buf)
1713 /* make sure it is aligned to 4K */
1714 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1715 cmd->cmd_buf = cmd->cmd_alloc_buf;
1716 cmd->dma = cmd->alloc_dma;
1717 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1721 dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1723 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1724 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1725 &cmd->alloc_dma, GFP_KERNEL);
1726 if (!cmd->cmd_alloc_buf)
1729 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1730 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1731 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1735 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1737 struct device *ddev = &dev->pdev->dev;
1739 dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1743 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1745 int size = sizeof(struct mlx5_cmd_prot_block);
1746 int align = roundup_pow_of_two(size);
1747 struct mlx5_cmd *cmd = &dev->cmd;
1753 memset(cmd, 0, sizeof(*cmd));
1754 cmd_if_rev = cmdif_rev(dev);
1755 if (cmd_if_rev != CMD_IF_REV) {
1756 dev_err(&dev->pdev->dev,
1757 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1758 CMD_IF_REV, cmd_if_rev);
1762 cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1766 err = alloc_cmd_page(dev, cmd);
1770 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1771 cmd->log_sz = cmd_l >> 4 & 0xf;
1772 cmd->log_stride = cmd_l & 0xf;
1773 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1774 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1780 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1781 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1786 cmd->checksum_disabled = 1;
1787 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1788 cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1790 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1791 if (cmd->cmdif_rev > CMD_IF_REV) {
1792 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1793 CMD_IF_REV, cmd->cmdif_rev);
1798 spin_lock_init(&cmd->alloc_lock);
1799 spin_lock_init(&cmd->token_lock);
1800 for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1801 spin_lock_init(&cmd->stats[i].lock);
1803 sema_init(&cmd->sem, cmd->max_reg_cmds);
1804 sema_init(&cmd->pages_sem, 1);
1806 cmd_h = (u32)((u64)(cmd->dma) >> 32);
1807 cmd_l = (u32)(cmd->dma);
1808 if (cmd_l & 0xfff) {
1809 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1814 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1815 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1817 /* Make sure firmware sees the complete address before we proceed */
1820 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1822 cmd->mode = CMD_MODE_POLLING;
1824 create_msg_cache(dev);
1827 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1829 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1834 err = create_debugfs_files(dev);
1843 destroy_workqueue(cmd->wq);
1846 destroy_msg_cache(dev);
1849 free_cmd_page(dev, cmd);
1852 pci_pool_destroy(cmd->pool);
1856 EXPORT_SYMBOL(mlx5_cmd_init);
1858 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1860 struct mlx5_cmd *cmd = &dev->cmd;
1862 clean_debug_files(dev);
1863 destroy_workqueue(cmd->wq);
1864 destroy_msg_cache(dev);
1865 free_cmd_page(dev, cmd);
1866 pci_pool_destroy(cmd->pool);
1868 EXPORT_SYMBOL(mlx5_cmd_cleanup);