2 * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/errno.h>
36 #include <linux/pci.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/random.h>
41 #include <linux/io-mapping.h>
42 #include <linux/mlx5/driver.h>
43 #include <linux/debugfs.h>
45 #include "mlx5_core.h"
59 LONG_LIST_SIZE = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 +
60 MLX5_CMD_DATA_BLOCK_SIZE,
61 MED_LIST_SIZE = 16 + MLX5_CMD_DATA_BLOCK_SIZE,
65 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
66 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
67 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
68 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
69 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
70 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
71 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
72 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
73 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
74 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
75 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
78 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
79 struct mlx5_cmd_msg *in,
80 struct mlx5_cmd_msg *out,
81 void *uout, int uout_size,
83 void *context, int page_queue)
85 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
86 struct mlx5_cmd_work_ent *ent;
88 ent = kzalloc(sizeof(*ent), alloc_flags);
90 return ERR_PTR(-ENOMEM);
95 ent->uout_size = uout_size;
97 ent->context = context;
99 ent->page_queue = page_queue;
104 static u8 alloc_token(struct mlx5_cmd *cmd)
108 spin_lock(&cmd->token_lock);
113 spin_unlock(&cmd->token_lock);
118 static int alloc_ent(struct mlx5_cmd *cmd)
123 spin_lock_irqsave(&cmd->alloc_lock, flags);
124 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
125 if (ret < cmd->max_reg_cmds)
126 clear_bit(ret, &cmd->bitmask);
127 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
129 return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
132 static void free_ent(struct mlx5_cmd *cmd, int idx)
136 spin_lock_irqsave(&cmd->alloc_lock, flags);
137 set_bit(idx, &cmd->bitmask);
138 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
141 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
143 return cmd->cmd_buf + (idx << cmd->log_stride);
146 static u8 xor8_buf(void *buf, size_t offset, int len)
151 int end = len + offset;
153 for (i = offset; i < end; i++)
159 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
161 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
162 int xor_len = sizeof(*block) - sizeof(block->data) - 1;
164 if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
167 if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
173 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
175 int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
176 size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
178 block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
179 block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
182 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
184 struct mlx5_cmd_mailbox *next = msg->next;
186 int blen = size - min_t(int, sizeof(msg->first.data), size);
187 int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
188 / MLX5_CMD_DATA_BLOCK_SIZE;
191 for (i = 0; i < n && next; i++) {
192 calc_block_sig(next->buf);
197 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
199 ent->lay->sig = ~xor8_buf(ent->lay, 0, sizeof(*ent->lay));
201 calc_chain_sig(ent->in);
202 calc_chain_sig(ent->out);
206 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
208 unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
212 own = ent->lay->status_own;
213 if (!(own & CMD_OWNER_HW)) {
217 usleep_range(5000, 10000);
218 } while (time_before(jiffies, poll_end));
220 ent->ret = -ETIMEDOUT;
223 static void free_cmd(struct mlx5_cmd_work_ent *ent)
229 static int verify_signature(struct mlx5_cmd_work_ent *ent)
231 struct mlx5_cmd_mailbox *next = ent->out->next;
234 int size = ent->out->len;
235 int blen = size - min_t(int, sizeof(ent->out->first.data), size);
236 int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
237 / MLX5_CMD_DATA_BLOCK_SIZE;
240 sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
244 for (i = 0; i < n && next; i++) {
245 err = verify_block_sig(next->buf);
255 static void dump_buf(void *buf, int size, int data_only, int offset)
260 for (i = 0; i < size; i += 16) {
261 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
262 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
271 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
272 u32 *synd, u8 *status)
278 case MLX5_CMD_OP_TEARDOWN_HCA:
279 case MLX5_CMD_OP_DISABLE_HCA:
280 case MLX5_CMD_OP_MANAGE_PAGES:
281 case MLX5_CMD_OP_DESTROY_MKEY:
282 case MLX5_CMD_OP_DESTROY_EQ:
283 case MLX5_CMD_OP_DESTROY_CQ:
284 case MLX5_CMD_OP_DESTROY_QP:
285 case MLX5_CMD_OP_DESTROY_PSV:
286 case MLX5_CMD_OP_DESTROY_SRQ:
287 case MLX5_CMD_OP_DESTROY_XRC_SRQ:
288 case MLX5_CMD_OP_DESTROY_DCT:
289 case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
290 case MLX5_CMD_OP_DEALLOC_PD:
291 case MLX5_CMD_OP_DEALLOC_UAR:
292 case MLX5_CMD_OP_DETACH_FROM_MCG:
293 case MLX5_CMD_OP_DEALLOC_XRCD:
294 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
295 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
296 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
297 case MLX5_CMD_OP_DESTROY_LAG:
298 case MLX5_CMD_OP_DESTROY_VPORT_LAG:
299 case MLX5_CMD_OP_DESTROY_TIR:
300 case MLX5_CMD_OP_DESTROY_SQ:
301 case MLX5_CMD_OP_DESTROY_RQ:
302 case MLX5_CMD_OP_DESTROY_RMP:
303 case MLX5_CMD_OP_DESTROY_TIS:
304 case MLX5_CMD_OP_DESTROY_RQT:
305 case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
306 case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
307 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
308 case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
309 case MLX5_CMD_OP_2ERR_QP:
310 case MLX5_CMD_OP_2RST_QP:
311 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
312 case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
313 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
314 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
315 case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
316 return MLX5_CMD_STAT_OK;
318 case MLX5_CMD_OP_QUERY_HCA_CAP:
319 case MLX5_CMD_OP_QUERY_ADAPTER:
320 case MLX5_CMD_OP_INIT_HCA:
321 case MLX5_CMD_OP_ENABLE_HCA:
322 case MLX5_CMD_OP_QUERY_PAGES:
323 case MLX5_CMD_OP_SET_HCA_CAP:
324 case MLX5_CMD_OP_QUERY_ISSI:
325 case MLX5_CMD_OP_SET_ISSI:
326 case MLX5_CMD_OP_CREATE_MKEY:
327 case MLX5_CMD_OP_QUERY_MKEY:
328 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
329 case MLX5_CMD_OP_PAGE_FAULT_RESUME:
330 case MLX5_CMD_OP_CREATE_EQ:
331 case MLX5_CMD_OP_QUERY_EQ:
332 case MLX5_CMD_OP_GEN_EQE:
333 case MLX5_CMD_OP_CREATE_CQ:
334 case MLX5_CMD_OP_QUERY_CQ:
335 case MLX5_CMD_OP_MODIFY_CQ:
336 case MLX5_CMD_OP_CREATE_QP:
337 case MLX5_CMD_OP_RST2INIT_QP:
338 case MLX5_CMD_OP_INIT2RTR_QP:
339 case MLX5_CMD_OP_RTR2RTS_QP:
340 case MLX5_CMD_OP_RTS2RTS_QP:
341 case MLX5_CMD_OP_SQERR2RTS_QP:
342 case MLX5_CMD_OP_QUERY_QP:
343 case MLX5_CMD_OP_SQD_RTS_QP:
344 case MLX5_CMD_OP_INIT2INIT_QP:
345 case MLX5_CMD_OP_CREATE_PSV:
346 case MLX5_CMD_OP_CREATE_SRQ:
347 case MLX5_CMD_OP_QUERY_SRQ:
348 case MLX5_CMD_OP_ARM_RQ:
349 case MLX5_CMD_OP_CREATE_XRC_SRQ:
350 case MLX5_CMD_OP_QUERY_XRC_SRQ:
351 case MLX5_CMD_OP_ARM_XRC_SRQ:
352 case MLX5_CMD_OP_CREATE_DCT:
353 case MLX5_CMD_OP_DRAIN_DCT:
354 case MLX5_CMD_OP_QUERY_DCT:
355 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
356 case MLX5_CMD_OP_QUERY_VPORT_STATE:
357 case MLX5_CMD_OP_MODIFY_VPORT_STATE:
358 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
359 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
360 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
361 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
362 case MLX5_CMD_OP_SET_ROCE_ADDRESS:
363 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
364 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
365 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
366 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
367 case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
368 case MLX5_CMD_OP_ALLOC_Q_COUNTER:
369 case MLX5_CMD_OP_QUERY_Q_COUNTER:
370 case MLX5_CMD_OP_ALLOC_PD:
371 case MLX5_CMD_OP_ALLOC_UAR:
372 case MLX5_CMD_OP_CONFIG_INT_MODERATION:
373 case MLX5_CMD_OP_ACCESS_REG:
374 case MLX5_CMD_OP_ATTACH_TO_MCG:
375 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
376 case MLX5_CMD_OP_MAD_IFC:
377 case MLX5_CMD_OP_QUERY_MAD_DEMUX:
378 case MLX5_CMD_OP_SET_MAD_DEMUX:
379 case MLX5_CMD_OP_NOP:
380 case MLX5_CMD_OP_ALLOC_XRCD:
381 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
382 case MLX5_CMD_OP_QUERY_CONG_STATUS:
383 case MLX5_CMD_OP_MODIFY_CONG_STATUS:
384 case MLX5_CMD_OP_QUERY_CONG_PARAMS:
385 case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
386 case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
387 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
388 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
389 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
390 case MLX5_CMD_OP_CREATE_LAG:
391 case MLX5_CMD_OP_MODIFY_LAG:
392 case MLX5_CMD_OP_QUERY_LAG:
393 case MLX5_CMD_OP_CREATE_VPORT_LAG:
394 case MLX5_CMD_OP_CREATE_TIR:
395 case MLX5_CMD_OP_MODIFY_TIR:
396 case MLX5_CMD_OP_QUERY_TIR:
397 case MLX5_CMD_OP_CREATE_SQ:
398 case MLX5_CMD_OP_MODIFY_SQ:
399 case MLX5_CMD_OP_QUERY_SQ:
400 case MLX5_CMD_OP_CREATE_RQ:
401 case MLX5_CMD_OP_MODIFY_RQ:
402 case MLX5_CMD_OP_QUERY_RQ:
403 case MLX5_CMD_OP_CREATE_RMP:
404 case MLX5_CMD_OP_MODIFY_RMP:
405 case MLX5_CMD_OP_QUERY_RMP:
406 case MLX5_CMD_OP_CREATE_TIS:
407 case MLX5_CMD_OP_MODIFY_TIS:
408 case MLX5_CMD_OP_QUERY_TIS:
409 case MLX5_CMD_OP_CREATE_RQT:
410 case MLX5_CMD_OP_MODIFY_RQT:
411 case MLX5_CMD_OP_QUERY_RQT:
413 case MLX5_CMD_OP_CREATE_FLOW_TABLE:
414 case MLX5_CMD_OP_QUERY_FLOW_TABLE:
415 case MLX5_CMD_OP_CREATE_FLOW_GROUP:
416 case MLX5_CMD_OP_QUERY_FLOW_GROUP:
418 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
419 case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
420 case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
421 case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
422 *status = MLX5_DRIVER_STATUS_ABORTED;
423 *synd = MLX5_DRIVER_SYND;
426 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
431 const char *mlx5_command_str(int command)
433 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
436 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
437 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
438 MLX5_COMMAND_STR_CASE(INIT_HCA);
439 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
440 MLX5_COMMAND_STR_CASE(ENABLE_HCA);
441 MLX5_COMMAND_STR_CASE(DISABLE_HCA);
442 MLX5_COMMAND_STR_CASE(QUERY_PAGES);
443 MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
444 MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
445 MLX5_COMMAND_STR_CASE(QUERY_ISSI);
446 MLX5_COMMAND_STR_CASE(SET_ISSI);
447 MLX5_COMMAND_STR_CASE(CREATE_MKEY);
448 MLX5_COMMAND_STR_CASE(QUERY_MKEY);
449 MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
450 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
451 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
452 MLX5_COMMAND_STR_CASE(CREATE_EQ);
453 MLX5_COMMAND_STR_CASE(DESTROY_EQ);
454 MLX5_COMMAND_STR_CASE(QUERY_EQ);
455 MLX5_COMMAND_STR_CASE(GEN_EQE);
456 MLX5_COMMAND_STR_CASE(CREATE_CQ);
457 MLX5_COMMAND_STR_CASE(DESTROY_CQ);
458 MLX5_COMMAND_STR_CASE(QUERY_CQ);
459 MLX5_COMMAND_STR_CASE(MODIFY_CQ);
460 MLX5_COMMAND_STR_CASE(CREATE_QP);
461 MLX5_COMMAND_STR_CASE(DESTROY_QP);
462 MLX5_COMMAND_STR_CASE(RST2INIT_QP);
463 MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
464 MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
465 MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
466 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
467 MLX5_COMMAND_STR_CASE(2ERR_QP);
468 MLX5_COMMAND_STR_CASE(2RST_QP);
469 MLX5_COMMAND_STR_CASE(QUERY_QP);
470 MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
471 MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
472 MLX5_COMMAND_STR_CASE(CREATE_PSV);
473 MLX5_COMMAND_STR_CASE(DESTROY_PSV);
474 MLX5_COMMAND_STR_CASE(CREATE_SRQ);
475 MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
476 MLX5_COMMAND_STR_CASE(QUERY_SRQ);
477 MLX5_COMMAND_STR_CASE(ARM_RQ);
478 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
479 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
480 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
481 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
482 MLX5_COMMAND_STR_CASE(CREATE_DCT);
483 MLX5_COMMAND_STR_CASE(DESTROY_DCT);
484 MLX5_COMMAND_STR_CASE(DRAIN_DCT);
485 MLX5_COMMAND_STR_CASE(QUERY_DCT);
486 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
487 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
488 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
489 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
490 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
491 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
492 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
493 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
494 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
495 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
496 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
497 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
498 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
499 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
500 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
501 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
502 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
503 MLX5_COMMAND_STR_CASE(ALLOC_PD);
504 MLX5_COMMAND_STR_CASE(DEALLOC_PD);
505 MLX5_COMMAND_STR_CASE(ALLOC_UAR);
506 MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
507 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
508 MLX5_COMMAND_STR_CASE(ACCESS_REG);
509 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
510 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
511 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
512 MLX5_COMMAND_STR_CASE(MAD_IFC);
513 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
514 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
515 MLX5_COMMAND_STR_CASE(NOP);
516 MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
517 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
518 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
519 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
520 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
521 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
522 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
523 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
524 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
525 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
526 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
527 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
528 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
529 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
530 MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
531 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
532 MLX5_COMMAND_STR_CASE(CREATE_LAG);
533 MLX5_COMMAND_STR_CASE(MODIFY_LAG);
534 MLX5_COMMAND_STR_CASE(QUERY_LAG);
535 MLX5_COMMAND_STR_CASE(DESTROY_LAG);
536 MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
537 MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
538 MLX5_COMMAND_STR_CASE(CREATE_TIR);
539 MLX5_COMMAND_STR_CASE(MODIFY_TIR);
540 MLX5_COMMAND_STR_CASE(DESTROY_TIR);
541 MLX5_COMMAND_STR_CASE(QUERY_TIR);
542 MLX5_COMMAND_STR_CASE(CREATE_SQ);
543 MLX5_COMMAND_STR_CASE(MODIFY_SQ);
544 MLX5_COMMAND_STR_CASE(DESTROY_SQ);
545 MLX5_COMMAND_STR_CASE(QUERY_SQ);
546 MLX5_COMMAND_STR_CASE(CREATE_RQ);
547 MLX5_COMMAND_STR_CASE(MODIFY_RQ);
548 MLX5_COMMAND_STR_CASE(DESTROY_RQ);
549 MLX5_COMMAND_STR_CASE(QUERY_RQ);
550 MLX5_COMMAND_STR_CASE(CREATE_RMP);
551 MLX5_COMMAND_STR_CASE(MODIFY_RMP);
552 MLX5_COMMAND_STR_CASE(DESTROY_RMP);
553 MLX5_COMMAND_STR_CASE(QUERY_RMP);
554 MLX5_COMMAND_STR_CASE(CREATE_TIS);
555 MLX5_COMMAND_STR_CASE(MODIFY_TIS);
556 MLX5_COMMAND_STR_CASE(DESTROY_TIS);
557 MLX5_COMMAND_STR_CASE(QUERY_TIS);
558 MLX5_COMMAND_STR_CASE(CREATE_RQT);
559 MLX5_COMMAND_STR_CASE(MODIFY_RQT);
560 MLX5_COMMAND_STR_CASE(DESTROY_RQT);
561 MLX5_COMMAND_STR_CASE(QUERY_RQT);
562 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
563 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
564 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
565 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
566 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
567 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
568 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
569 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
570 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
571 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
572 MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
573 MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
574 MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
575 MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
576 MLX5_COMMAND_STR_CASE(ALLOC_ENCAP_HEADER);
577 MLX5_COMMAND_STR_CASE(DEALLOC_ENCAP_HEADER);
578 default: return "unknown command opcode";
582 static const char *cmd_status_str(u8 status)
585 case MLX5_CMD_STAT_OK:
587 case MLX5_CMD_STAT_INT_ERR:
588 return "internal error";
589 case MLX5_CMD_STAT_BAD_OP_ERR:
590 return "bad operation";
591 case MLX5_CMD_STAT_BAD_PARAM_ERR:
592 return "bad parameter";
593 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
594 return "bad system state";
595 case MLX5_CMD_STAT_BAD_RES_ERR:
596 return "bad resource";
597 case MLX5_CMD_STAT_RES_BUSY:
598 return "resource busy";
599 case MLX5_CMD_STAT_LIM_ERR:
600 return "limits exceeded";
601 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
602 return "bad resource state";
603 case MLX5_CMD_STAT_IX_ERR:
605 case MLX5_CMD_STAT_NO_RES_ERR:
606 return "no resources";
607 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
608 return "bad input length";
609 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
610 return "bad output length";
611 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
612 return "bad QP state";
613 case MLX5_CMD_STAT_BAD_PKT_ERR:
614 return "bad packet (discarded)";
615 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
616 return "bad size too many outstanding CQEs";
618 return "unknown status";
622 static int cmd_status_to_err(u8 status)
625 case MLX5_CMD_STAT_OK: return 0;
626 case MLX5_CMD_STAT_INT_ERR: return -EIO;
627 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
628 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
629 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
630 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
631 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
632 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
633 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
634 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
635 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
636 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
637 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
638 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
639 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
640 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
641 default: return -EIO;
645 struct mlx5_ifc_mbox_out_bits {
647 u8 reserved_at_8[0x18];
651 u8 reserved_at_40[0x40];
654 struct mlx5_ifc_mbox_in_bits {
656 u8 reserved_at_10[0x10];
658 u8 reserved_at_20[0x10];
661 u8 reserved_at_40[0x40];
664 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
666 *status = MLX5_GET(mbox_out, out, status);
667 *syndrome = MLX5_GET(mbox_out, out, syndrome);
670 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
677 mlx5_cmd_mbox_status(out, &status, &syndrome);
681 opcode = MLX5_GET(mbox_in, in, opcode);
682 op_mod = MLX5_GET(mbox_in, in, op_mod);
685 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
686 mlx5_command_str(opcode),
688 cmd_status_str(status),
692 return cmd_status_to_err(status);
695 static void dump_command(struct mlx5_core_dev *dev,
696 struct mlx5_cmd_work_ent *ent, int input)
698 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
699 u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
700 struct mlx5_cmd_mailbox *next = msg->next;
705 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
708 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
709 "dump command data %s(0x%x) %s\n",
710 mlx5_command_str(op), op,
711 input ? "INPUT" : "OUTPUT");
713 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
714 mlx5_command_str(op), op,
715 input ? "INPUT" : "OUTPUT");
719 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
720 offset += sizeof(ent->lay->in);
722 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
723 offset += sizeof(ent->lay->out);
726 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
727 offset += sizeof(*ent->lay);
730 while (next && offset < msg->len) {
732 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
733 dump_buf(next->buf, dump_len, 1, offset);
734 offset += MLX5_CMD_DATA_BLOCK_SIZE;
736 mlx5_core_dbg(dev, "command block:\n");
737 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
738 offset += sizeof(struct mlx5_cmd_prot_block);
747 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
749 return MLX5_GET(mbox_in, in->first.data, opcode);
752 static void cb_timeout_handler(struct work_struct *work)
754 struct delayed_work *dwork = container_of(work, struct delayed_work,
756 struct mlx5_cmd_work_ent *ent = container_of(dwork,
757 struct mlx5_cmd_work_ent,
759 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
762 ent->ret = -ETIMEDOUT;
763 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
764 mlx5_command_str(msg_to_opcode(ent->in)),
765 msg_to_opcode(ent->in));
766 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
769 static void cmd_work_handler(struct work_struct *work)
771 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
772 struct mlx5_cmd *cmd = ent->cmd;
773 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
774 unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
775 struct mlx5_cmd_layout *lay;
776 struct semaphore *sem;
779 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
781 if (!ent->page_queue) {
782 ent->idx = alloc_ent(cmd);
784 mlx5_core_err(dev, "failed to allocate command entry\n");
789 ent->idx = cmd->max_reg_cmds;
790 spin_lock_irqsave(&cmd->alloc_lock, flags);
791 clear_bit(ent->idx, &cmd->bitmask);
792 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
795 cmd->ent_arr[ent->idx] = ent;
796 lay = get_inst(cmd, ent->idx);
798 memset(lay, 0, sizeof(*lay));
799 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
800 ent->op = be32_to_cpu(lay->in[0]) >> 16;
802 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
803 lay->inlen = cpu_to_be32(ent->in->len);
805 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
806 lay->outlen = cpu_to_be32(ent->out->len);
807 lay->type = MLX5_PCI_CMD_XPORT;
808 lay->token = ent->token;
809 lay->status_own = CMD_OWNER_HW;
810 set_signature(ent, !cmd->checksum_disabled);
811 dump_command(dev, ent, 1);
812 ent->ts1 = ktime_get_ns();
815 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
817 /* ring doorbell after the descriptor is valid */
818 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
820 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
822 /* if not in polling don't use ent after this point */
823 if (cmd->mode == CMD_MODE_POLLING) {
825 /* make sure we read the descriptor after ownership is SW */
827 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
831 static const char *deliv_status_to_str(u8 status)
834 case MLX5_CMD_DELIVERY_STAT_OK:
836 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
837 return "signature error";
838 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
839 return "token error";
840 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
841 return "bad block number";
842 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
843 return "output pointer not aligned to block size";
844 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
845 return "input pointer not aligned to block size";
846 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
847 return "firmware internal error";
848 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
849 return "command input length error";
850 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
851 return "command ouput length error";
852 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
853 return "reserved fields not cleared";
854 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
855 return "bad command descriptor type";
857 return "unknown status code";
861 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
863 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
864 struct mlx5_cmd *cmd = &dev->cmd;
867 if (cmd->mode == CMD_MODE_POLLING) {
868 wait_for_completion(&ent->done);
869 } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
870 ent->ret = -ETIMEDOUT;
871 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
876 if (err == -ETIMEDOUT) {
877 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
878 mlx5_command_str(msg_to_opcode(ent->in)),
879 msg_to_opcode(ent->in));
881 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
882 err, deliv_status_to_str(ent->status), ent->status);
888 * 1. Callback functions may not sleep
889 * 2. page queue commands do not support asynchrous completion
891 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
892 struct mlx5_cmd_msg *out, void *uout, int uout_size,
893 mlx5_cmd_cbk_t callback,
894 void *context, int page_queue, u8 *status,
897 struct mlx5_cmd *cmd = &dev->cmd;
898 struct mlx5_cmd_work_ent *ent;
899 struct mlx5_cmd_stats *stats;
904 if (callback && page_queue)
907 ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
915 init_completion(&ent->done);
917 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
918 INIT_WORK(&ent->work, cmd_work_handler);
920 cmd_work_handler(&ent->work);
921 } else if (!queue_work(cmd->wq, &ent->work)) {
922 mlx5_core_warn(dev, "failed to queue work\n");
930 err = wait_func(dev, ent);
931 if (err == -ETIMEDOUT)
934 ds = ent->ts2 - ent->ts1;
935 op = MLX5_GET(mbox_in, in->first.data, opcode);
936 if (op < ARRAY_SIZE(cmd->stats)) {
937 stats = &cmd->stats[op];
938 spin_lock_irq(&stats->lock);
941 spin_unlock_irq(&stats->lock);
943 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
944 "fw exec time for %s is %lld nsec\n",
945 mlx5_command_str(op), ds);
946 *status = ent->status;
954 static ssize_t dbg_write(struct file *filp, const char __user *buf,
955 size_t count, loff_t *pos)
957 struct mlx5_core_dev *dev = filp->private_data;
958 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
962 if (!dbg->in_msg || !dbg->out_msg)
965 if (copy_from_user(lbuf, buf, sizeof(lbuf)))
968 lbuf[sizeof(lbuf) - 1] = 0;
970 if (strcmp(lbuf, "go"))
973 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
975 return err ? err : count;
979 static const struct file_operations fops = {
980 .owner = THIS_MODULE,
985 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
988 struct mlx5_cmd_prot_block *block;
989 struct mlx5_cmd_mailbox *next;
995 copy = min_t(int, size, sizeof(to->first.data));
996 memcpy(to->first.data, from, copy);
1007 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1009 memcpy(block->data, from, copy);
1012 block->token = token;
1019 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1021 struct mlx5_cmd_prot_block *block;
1022 struct mlx5_cmd_mailbox *next;
1028 copy = min_t(int, size, sizeof(from->first.data));
1029 memcpy(to, from->first.data, copy);
1040 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1043 memcpy(to, block->data, copy);
1052 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1055 struct mlx5_cmd_mailbox *mailbox;
1057 mailbox = kmalloc(sizeof(*mailbox), flags);
1059 return ERR_PTR(-ENOMEM);
1061 mailbox->buf = pci_pool_alloc(dev->cmd.pool, flags,
1063 if (!mailbox->buf) {
1064 mlx5_core_dbg(dev, "failed allocation\n");
1066 return ERR_PTR(-ENOMEM);
1068 memset(mailbox->buf, 0, sizeof(struct mlx5_cmd_prot_block));
1069 mailbox->next = NULL;
1074 static void free_cmd_box(struct mlx5_core_dev *dev,
1075 struct mlx5_cmd_mailbox *mailbox)
1077 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1081 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1082 gfp_t flags, int size,
1085 struct mlx5_cmd_mailbox *tmp, *head = NULL;
1086 struct mlx5_cmd_prot_block *block;
1087 struct mlx5_cmd_msg *msg;
1093 msg = kzalloc(sizeof(*msg), flags);
1095 return ERR_PTR(-ENOMEM);
1097 blen = size - min_t(int, sizeof(msg->first.data), size);
1098 n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
1100 for (i = 0; i < n; i++) {
1101 tmp = alloc_cmd_box(dev, flags);
1103 mlx5_core_warn(dev, "failed allocating block\n");
1110 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1111 block->block_num = cpu_to_be32(n - i - 1);
1112 block->token = token;
1122 free_cmd_box(dev, head);
1127 return ERR_PTR(err);
1130 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1131 struct mlx5_cmd_msg *msg)
1133 struct mlx5_cmd_mailbox *head = msg->next;
1134 struct mlx5_cmd_mailbox *next;
1138 free_cmd_box(dev, head);
1144 static ssize_t data_write(struct file *filp, const char __user *buf,
1145 size_t count, loff_t *pos)
1147 struct mlx5_core_dev *dev = filp->private_data;
1148 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1157 ptr = memdup_user(buf, count);
1159 return PTR_ERR(ptr);
1168 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1171 struct mlx5_core_dev *dev = filp->private_data;
1172 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1181 copy = min_t(int, count, dbg->outlen);
1182 if (copy_to_user(buf, dbg->out_msg, copy))
1190 static const struct file_operations dfops = {
1191 .owner = THIS_MODULE,
1192 .open = simple_open,
1193 .write = data_write,
1197 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1200 struct mlx5_core_dev *dev = filp->private_data;
1201 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1208 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1212 if (copy_to_user(buf, &outlen, err))
1220 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1221 size_t count, loff_t *pos)
1223 struct mlx5_core_dev *dev = filp->private_data;
1224 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1230 if (*pos != 0 || count > 6)
1233 kfree(dbg->out_msg);
1234 dbg->out_msg = NULL;
1237 if (copy_from_user(outlen_str, buf, count))
1242 err = sscanf(outlen_str, "%d", &outlen);
1246 ptr = kzalloc(outlen, GFP_KERNEL);
1251 dbg->outlen = outlen;
1258 static const struct file_operations olfops = {
1259 .owner = THIS_MODULE,
1260 .open = simple_open,
1261 .write = outlen_write,
1262 .read = outlen_read,
1265 static void set_wqname(struct mlx5_core_dev *dev)
1267 struct mlx5_cmd *cmd = &dev->cmd;
1269 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1270 dev_name(&dev->pdev->dev));
1273 static void clean_debug_files(struct mlx5_core_dev *dev)
1275 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1277 if (!mlx5_debugfs_root)
1280 mlx5_cmdif_debugfs_cleanup(dev);
1281 debugfs_remove_recursive(dbg->dbg_root);
1284 static int create_debugfs_files(struct mlx5_core_dev *dev)
1286 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1289 if (!mlx5_debugfs_root)
1292 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1296 dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1301 dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1306 dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1308 if (!dbg->dbg_outlen)
1311 dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1313 if (!dbg->dbg_status)
1316 dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1320 mlx5_cmdif_debugfs_init(dev);
1325 clean_debug_files(dev);
1329 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1331 struct mlx5_cmd *cmd = &dev->cmd;
1334 for (i = 0; i < cmd->max_reg_cmds; i++)
1336 down(&cmd->pages_sem);
1340 up(&cmd->pages_sem);
1341 for (i = 0; i < cmd->max_reg_cmds; i++)
1345 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1347 mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1350 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1352 mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1355 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1357 unsigned long flags;
1360 spin_lock_irqsave(&msg->cache->lock, flags);
1361 list_add_tail(&msg->list, &msg->cache->head);
1362 spin_unlock_irqrestore(&msg->cache->lock, flags);
1364 mlx5_free_cmd_msg(dev, msg);
1368 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec)
1370 struct mlx5_cmd *cmd = &dev->cmd;
1371 struct mlx5_cmd_work_ent *ent;
1372 mlx5_cmd_cbk_t callback;
1377 struct mlx5_cmd_stats *stats;
1378 unsigned long flags;
1379 unsigned long vector;
1381 /* there can be at most 32 command queues */
1382 vector = vec & 0xffffffff;
1383 for (i = 0; i < (1 << cmd->log_sz); i++) {
1384 if (test_bit(i, &vector)) {
1385 struct semaphore *sem;
1387 ent = cmd->ent_arr[i];
1389 cancel_delayed_work(&ent->cb_timeout_work);
1390 if (ent->page_queue)
1391 sem = &cmd->pages_sem;
1394 ent->ts2 = ktime_get_ns();
1395 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1396 dump_command(dev, ent, 0);
1398 if (!cmd->checksum_disabled)
1399 ent->ret = verify_signature(ent);
1402 if (vec & MLX5_TRIGGERED_CMD_COMP)
1403 ent->status = MLX5_DRIVER_STATUS_ABORTED;
1405 ent->status = ent->lay->status_own >> 1;
1407 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1408 ent->ret, deliv_status_to_str(ent->status), ent->status);
1410 free_ent(cmd, ent->idx);
1412 if (ent->callback) {
1413 ds = ent->ts2 - ent->ts1;
1414 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1415 stats = &cmd->stats[ent->op];
1416 spin_lock_irqsave(&stats->lock, flags);
1419 spin_unlock_irqrestore(&stats->lock, flags);
1422 callback = ent->callback;
1423 context = ent->context;
1426 err = mlx5_copy_from_msg(ent->uout,
1430 err = err ? err : mlx5_cmd_check(dev,
1431 ent->in->first.data,
1435 mlx5_free_cmd_msg(dev, ent->out);
1436 free_msg(dev, ent->in);
1438 err = err ? err : ent->status;
1440 callback(err, context);
1442 complete(&ent->done);
1448 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1450 static int status_to_err(u8 status)
1452 return status ? -1 : 0; /* TBD more meaningful codes */
1455 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1458 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1459 struct mlx5_cmd *cmd = &dev->cmd;
1460 struct cache_ent *ent = NULL;
1462 if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE)
1463 ent = &cmd->cache.large;
1464 else if (in_size > 16 && in_size <= MED_LIST_SIZE)
1465 ent = &cmd->cache.med;
1468 spin_lock_irq(&ent->lock);
1469 if (!list_empty(&ent->head)) {
1470 msg = list_entry(ent->head.next, typeof(*msg), list);
1471 /* For cached lists, we must explicitly state what is
1475 list_del(&msg->list);
1477 spin_unlock_irq(&ent->lock);
1481 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1486 static int is_manage_pages(void *in)
1488 return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1491 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1492 int out_size, mlx5_cmd_cbk_t callback, void *context)
1494 struct mlx5_cmd_msg *inb;
1495 struct mlx5_cmd_msg *outb;
1503 if (pci_channel_offline(dev->pdev) ||
1504 dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1505 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1507 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1508 MLX5_SET(mbox_out, out, status, status);
1509 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1513 pages_queue = is_manage_pages(in);
1514 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1516 inb = alloc_msg(dev, in_size, gfp);
1522 token = alloc_token(&dev->cmd);
1524 err = mlx5_copy_to_msg(inb, in, in_size, token);
1526 mlx5_core_warn(dev, "err %d\n", err);
1530 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1532 err = PTR_ERR(outb);
1536 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1537 pages_queue, &status, token);
1541 mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1543 err = status_to_err(status);
1548 err = mlx5_copy_from_msg(out, outb, out_size);
1552 mlx5_free_cmd_msg(dev, outb);
1560 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1565 err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1566 return err ? : mlx5_cmd_check(dev, in, out);
1568 EXPORT_SYMBOL(mlx5_cmd_exec);
1570 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1571 void *out, int out_size, mlx5_cmd_cbk_t callback,
1574 return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1576 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1578 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1580 struct mlx5_cmd *cmd = &dev->cmd;
1581 struct mlx5_cmd_msg *msg;
1582 struct mlx5_cmd_msg *n;
1584 list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1585 list_del(&msg->list);
1586 mlx5_free_cmd_msg(dev, msg);
1589 list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1590 list_del(&msg->list);
1591 mlx5_free_cmd_msg(dev, msg);
1595 static int create_msg_cache(struct mlx5_core_dev *dev)
1597 struct mlx5_cmd *cmd = &dev->cmd;
1598 struct mlx5_cmd_msg *msg;
1602 spin_lock_init(&cmd->cache.large.lock);
1603 INIT_LIST_HEAD(&cmd->cache.large.head);
1604 spin_lock_init(&cmd->cache.med.lock);
1605 INIT_LIST_HEAD(&cmd->cache.med.head);
1607 for (i = 0; i < NUM_LONG_LISTS; i++) {
1608 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE, 0);
1613 msg->cache = &cmd->cache.large;
1614 list_add_tail(&msg->list, &cmd->cache.large.head);
1617 for (i = 0; i < NUM_MED_LISTS; i++) {
1618 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE, 0);
1623 msg->cache = &cmd->cache.med;
1624 list_add_tail(&msg->list, &cmd->cache.med.head);
1630 destroy_msg_cache(dev);
1634 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1636 struct device *ddev = &dev->pdev->dev;
1638 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1639 &cmd->alloc_dma, GFP_KERNEL);
1640 if (!cmd->cmd_alloc_buf)
1643 /* make sure it is aligned to 4K */
1644 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1645 cmd->cmd_buf = cmd->cmd_alloc_buf;
1646 cmd->dma = cmd->alloc_dma;
1647 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1651 dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1653 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1654 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1655 &cmd->alloc_dma, GFP_KERNEL);
1656 if (!cmd->cmd_alloc_buf)
1659 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1660 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1661 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1665 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1667 struct device *ddev = &dev->pdev->dev;
1669 dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1673 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1675 int size = sizeof(struct mlx5_cmd_prot_block);
1676 int align = roundup_pow_of_two(size);
1677 struct mlx5_cmd *cmd = &dev->cmd;
1683 memset(cmd, 0, sizeof(*cmd));
1684 cmd_if_rev = cmdif_rev(dev);
1685 if (cmd_if_rev != CMD_IF_REV) {
1686 dev_err(&dev->pdev->dev,
1687 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1688 CMD_IF_REV, cmd_if_rev);
1692 cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1696 err = alloc_cmd_page(dev, cmd);
1700 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1701 cmd->log_sz = cmd_l >> 4 & 0xf;
1702 cmd->log_stride = cmd_l & 0xf;
1703 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1704 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1710 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1711 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1716 cmd->checksum_disabled = 1;
1717 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1718 cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1720 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1721 if (cmd->cmdif_rev > CMD_IF_REV) {
1722 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1723 CMD_IF_REV, cmd->cmdif_rev);
1728 spin_lock_init(&cmd->alloc_lock);
1729 spin_lock_init(&cmd->token_lock);
1730 for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1731 spin_lock_init(&cmd->stats[i].lock);
1733 sema_init(&cmd->sem, cmd->max_reg_cmds);
1734 sema_init(&cmd->pages_sem, 1);
1736 cmd_h = (u32)((u64)(cmd->dma) >> 32);
1737 cmd_l = (u32)(cmd->dma);
1738 if (cmd_l & 0xfff) {
1739 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1744 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1745 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1747 /* Make sure firmware sees the complete address before we proceed */
1750 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1752 cmd->mode = CMD_MODE_POLLING;
1754 err = create_msg_cache(dev);
1756 dev_err(&dev->pdev->dev, "failed to create command cache\n");
1761 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1763 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1768 err = create_debugfs_files(dev);
1777 destroy_workqueue(cmd->wq);
1780 destroy_msg_cache(dev);
1783 free_cmd_page(dev, cmd);
1786 pci_pool_destroy(cmd->pool);
1790 EXPORT_SYMBOL(mlx5_cmd_init);
1792 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1794 struct mlx5_cmd *cmd = &dev->cmd;
1796 clean_debug_files(dev);
1797 destroy_workqueue(cmd->wq);
1798 destroy_msg_cache(dev);
1799 free_cmd_page(dev, cmd);
1800 pci_pool_destroy(cmd->pool);
1802 EXPORT_SYMBOL(mlx5_cmd_cleanup);