2 * Copyright (c) 2018, Mellanox Technologies. All rights reserved.
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32 #ifndef __MLX5_EN_XDP_H__
33 #define __MLX5_EN_XDP_H__
38 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
39 #define MLX5E_XDP_TX_EMPTY_DS_COUNT \
40 (sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS)
41 #define MLX5E_XDP_TX_DS_COUNT (MLX5E_XDP_TX_EMPTY_DS_COUNT + 1 /* SG DS */)
43 #define MLX5E_XDPSQ_STOP_ROOM (MLX5E_SQ_STOP_ROOM)
45 #define MLX5E_XDP_INLINE_WQE_SZ_THRSD (256 - sizeof(struct mlx5_wqe_inline_seg))
46 #define MLX5E_XDP_INLINE_WQE_MAX_DS_CNT \
47 DIV_ROUND_UP(MLX5E_XDP_INLINE_WQE_SZ_THRSD, MLX5_SEND_WQE_DS)
49 /* The mult of MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS
50 * (16 * 4 == 64) does not fit in the 6-bit DS field of Ctrl Segment.
51 * We use a bound lower that MLX5_SEND_WQE_MAX_WQEBBS to let a
52 * full-session WQE be cache-aligned.
54 #if L1_CACHE_BYTES < 128
55 #define MLX5E_XDP_MPW_MAX_WQEBBS (MLX5_SEND_WQE_MAX_WQEBBS - 1)
57 #define MLX5E_XDP_MPW_MAX_WQEBBS (MLX5_SEND_WQE_MAX_WQEBBS - 2)
60 #define MLX5E_XDP_MPW_MAX_NUM_DS \
61 (MLX5E_XDP_MPW_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS)
63 struct mlx5e_xsk_param;
64 int mlx5e_xdp_max_mtu(struct mlx5e_params *params, struct mlx5e_xsk_param *xsk);
65 bool mlx5e_xdp_handle(struct mlx5e_rq *rq, struct mlx5e_dma_info *di,
66 void *va, u16 *rx_headroom, u32 *len, bool xsk);
67 void mlx5e_xdp_mpwqe_complete(struct mlx5e_xdpsq *sq);
68 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq);
69 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq);
70 void mlx5e_set_xmit_fp(struct mlx5e_xdpsq *sq, bool is_mpw);
71 void mlx5e_xdp_rx_poll_complete(struct mlx5e_rq *rq);
72 int mlx5e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
75 static inline void mlx5e_xdp_tx_enable(struct mlx5e_priv *priv)
77 set_bit(MLX5E_STATE_XDP_TX_ENABLED, &priv->state);
80 static inline void mlx5e_xdp_tx_disable(struct mlx5e_priv *priv)
82 clear_bit(MLX5E_STATE_XDP_TX_ENABLED, &priv->state);
83 /* let other device's napi(s) see our new state */
87 static inline bool mlx5e_xdp_tx_is_enabled(struct mlx5e_priv *priv)
89 return test_bit(MLX5E_STATE_XDP_TX_ENABLED, &priv->state);
92 static inline void mlx5e_xdp_set_open(struct mlx5e_priv *priv)
94 set_bit(MLX5E_STATE_XDP_OPEN, &priv->state);
97 static inline void mlx5e_xdp_set_closed(struct mlx5e_priv *priv)
99 clear_bit(MLX5E_STATE_XDP_OPEN, &priv->state);
102 static inline bool mlx5e_xdp_is_open(struct mlx5e_priv *priv)
104 return test_bit(MLX5E_STATE_XDP_OPEN, &priv->state);
107 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq)
109 if (sq->doorbell_cseg) {
110 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, sq->doorbell_cseg);
111 sq->doorbell_cseg = NULL;
115 /* Enable inline WQEs to shift some load from a congested HCA (HW) to
116 * a less congested cpu (SW).
118 static inline void mlx5e_xdp_update_inline_state(struct mlx5e_xdpsq *sq)
120 u16 outstanding = sq->xdpi_fifo_pc - sq->xdpi_fifo_cc;
121 struct mlx5e_xdp_mpwqe *session = &sq->mpwqe;
123 #define MLX5E_XDP_INLINE_WATERMARK_LOW 10
124 #define MLX5E_XDP_INLINE_WATERMARK_HIGH 128
126 if (session->inline_on) {
127 if (outstanding <= MLX5E_XDP_INLINE_WATERMARK_LOW)
128 session->inline_on = 0;
132 /* inline is false */
133 if (outstanding >= MLX5E_XDP_INLINE_WATERMARK_HIGH)
134 session->inline_on = 1;
138 mlx5e_xdp_no_room_for_inline_pkt(struct mlx5e_xdp_mpwqe *session)
140 return session->inline_on &&
141 session->ds_count + MLX5E_XDP_INLINE_WQE_MAX_DS_CNT > MLX5E_XDP_MPW_MAX_NUM_DS;
145 mlx5e_fill_xdpsq_frag_edge(struct mlx5e_xdpsq *sq, struct mlx5_wq_cyc *wq,
148 struct mlx5e_xdp_wqe_info *edge_wi, *wi = &sq->db.wqe_info[pi];
150 edge_wi = wi + nnops;
151 /* fill sq frag edge with nops to avoid wqe wrapping two pages */
152 for (; wi < edge_wi; wi++) {
155 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
158 sq->stats->nops += nnops;
162 mlx5e_xdp_mpwqe_add_dseg(struct mlx5e_xdpsq *sq,
163 struct mlx5e_xdp_xmit_data *xdptxd,
164 struct mlx5e_xdpsq_stats *stats)
166 struct mlx5e_xdp_mpwqe *session = &sq->mpwqe;
167 struct mlx5_wqe_data_seg *dseg =
168 (struct mlx5_wqe_data_seg *)session->wqe + session->ds_count;
169 u32 dma_len = xdptxd->len;
171 session->pkt_count++;
173 if (session->inline_on && dma_len <= MLX5E_XDP_INLINE_WQE_SZ_THRSD) {
174 struct mlx5_wqe_inline_seg *inline_dseg =
175 (struct mlx5_wqe_inline_seg *)dseg;
176 u16 ds_len = sizeof(*inline_dseg) + dma_len;
177 u16 ds_cnt = DIV_ROUND_UP(ds_len, MLX5_SEND_WQE_DS);
179 inline_dseg->byte_count = cpu_to_be32(dma_len | MLX5_INLINE_SEG);
180 memcpy(inline_dseg->data, xdptxd->data, dma_len);
182 session->ds_count += ds_cnt;
187 dseg->addr = cpu_to_be64(xdptxd->dma_addr);
188 dseg->byte_count = cpu_to_be32(dma_len);
189 dseg->lkey = sq->mkey_be;
193 static inline struct mlx5e_tx_wqe *
194 mlx5e_xdpsq_fetch_wqe(struct mlx5e_xdpsq *sq, u16 *pi)
196 struct mlx5_wq_cyc *wq = &sq->wq;
197 struct mlx5e_tx_wqe *wqe;
199 *pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
200 wqe = mlx5_wq_cyc_get_wqe(wq, *pi);
201 memset(wqe, 0, sizeof(*wqe));
207 mlx5e_xdpi_fifo_push(struct mlx5e_xdp_info_fifo *fifo,
208 struct mlx5e_xdp_info *xi)
210 u32 i = (*fifo->pc)++ & fifo->mask;
215 static inline struct mlx5e_xdp_info
216 mlx5e_xdpi_fifo_pop(struct mlx5e_xdp_info_fifo *fifo)
218 return fifo->xi[(*fifo->cc)++ & fifo->mask];