2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/crash_dump.h>
41 #include <linux/mlx5/driver.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/cq.h>
44 #include <linux/mlx5/port.h>
45 #include <linux/mlx5/vport.h>
46 #include <linux/mlx5/transobj.h>
47 #include <linux/rhashtable.h>
48 #include <net/switchdev.h>
50 #include "mlx5_core.h"
53 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
55 #define MLX5E_HW2SW_MTU(hwmtu) ((hwmtu) - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
56 #define MLX5E_SW2HW_MTU(swmtu) ((swmtu) + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
58 #define MLX5E_MAX_NUM_TC 8
60 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
61 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
62 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
64 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
65 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
66 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
68 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
69 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3
70 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
72 #define MLX5_RX_HEADROOM NET_SKB_PAD
74 #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \
75 (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */
76 #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \
77 max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req)
78 #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6)
79 #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8)
81 #define MLX5_MPWRQ_LOG_WQE_SZ 18
82 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
83 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
84 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
85 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
86 MLX5_MPWRQ_WQE_PAGE_ORDER)
88 #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2)
89 #define MLX5E_REQUIRED_MTTS(wqes) \
90 (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8))
91 #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX)
93 #define MLX5_UMR_ALIGN (2048)
94 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (256)
96 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
97 #define MLX5E_DEFAULT_LRO_TIMEOUT 32
98 #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4
100 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
101 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
102 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
103 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
104 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
105 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
106 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
108 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
109 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
110 #define MLX5E_MIN_NUM_CHANNELS 0x1
111 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
112 #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)
113 #define MLX5E_TX_CQ_POLL_BUDGET 128
114 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
116 #define MLX5E_ICOSQ_MAX_WQEBBS \
117 (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB))
119 #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN)
120 #define MLX5E_XDP_TX_DS_COUNT \
121 ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */)
123 #define MLX5E_NUM_MAIN_GROUPS 9
125 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
128 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
129 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
132 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
137 static inline int mlx5_min_log_rq_size(int wq_type)
140 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
141 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
143 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
147 static inline int mlx5_max_log_rq_size(int wq_type)
150 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
151 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
153 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
157 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
159 return is_kdump_kernel() ?
160 MLX5E_MIN_NUM_CHANNELS :
161 min_t(int, mdev->priv.eq_table.num_comp_vectors,
162 MLX5E_MAX_NUM_CHANNELS);
165 struct mlx5e_tx_wqe {
166 struct mlx5_wqe_ctrl_seg ctrl;
167 struct mlx5_wqe_eth_seg eth;
170 struct mlx5e_rx_wqe {
171 struct mlx5_wqe_srq_next_seg next;
172 struct mlx5_wqe_data_seg data;
175 struct mlx5e_umr_wqe {
176 struct mlx5_wqe_ctrl_seg ctrl;
177 struct mlx5_wqe_umr_ctrl_seg uctrl;
178 struct mlx5_mkey_seg mkc;
179 struct mlx5_wqe_data_seg data;
182 extern const char mlx5e_self_tests[][ETH_GSTRING_LEN];
184 static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {
189 enum mlx5e_priv_flag {
190 MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),
191 MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 1),
194 #define MLX5E_SET_PFLAG(params, pflag, enable) \
197 (params)->pflags |= (pflag); \
199 (params)->pflags &= ~(pflag); \
202 #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag)))
204 #ifdef CONFIG_MLX5_CORE_EN_DCB
205 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
208 struct mlx5e_cq_moder {
213 struct mlx5e_params {
216 u8 mpwqe_log_stride_sz;
217 u8 mpwqe_log_num_strides;
221 u8 rx_cq_period_mode;
222 bool rx_cqe_compress_def;
223 struct mlx5e_cq_moder rx_cq_moderation;
224 struct mlx5e_cq_moder tx_cq_moderation;
228 u8 tx_min_inline_mode;
230 u8 toeplitz_hash_key[40];
231 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
232 bool vlan_strip_disable;
237 struct bpf_prog *xdp_prog;
240 #ifdef CONFIG_MLX5_CORE_EN_DCB
241 struct mlx5e_cee_config {
242 /* bw pct for priority group */
243 u8 pg_bw_pct[CEE_DCBX_MAX_PGS];
244 u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO];
245 bool pfc_setting[CEE_DCBX_MAX_PRIO];
252 MLX5_DCB_CHG_NO_RESET,
256 enum mlx5_dcbx_oper_mode mode;
257 struct mlx5e_cee_config cee_cfg; /* pending configuration */
259 /* The only setting that cannot be read from FW */
260 u8 tc_tsa[IEEE_8021QAZ_MAX_TCS];
264 struct mlx5e_tstamp {
266 struct cyclecounter cycles;
267 struct timecounter clock;
268 struct hwtstamp_config hwtstamp_config;
270 unsigned long overflow_period;
271 struct delayed_work overflow_work;
272 struct mlx5_core_dev *mdev;
273 struct ptp_clock *ptp;
274 struct ptp_clock_info ptp_info;
279 MLX5E_RQ_STATE_ENABLED,
280 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
285 /* data path - accessed per cqe */
288 /* data path - accessed per napi poll */
290 struct napi_struct *napi;
291 struct mlx5_core_cq mcq;
292 struct mlx5e_channel *channel;
294 /* cqe decompression */
295 struct mlx5_cqe64 title;
296 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
299 u16 decmprs_wqe_counter;
302 struct mlx5_core_dev *mdev;
303 struct mlx5_frag_wq_ctrl wq_ctrl;
304 } ____cacheline_aligned_in_smp;
306 struct mlx5e_tx_wqe_info {
313 enum mlx5e_dma_map_type {
314 MLX5E_DMA_MAP_SINGLE,
318 struct mlx5e_sq_dma {
321 enum mlx5e_dma_map_type type;
325 MLX5E_SQ_STATE_ENABLED,
328 struct mlx5e_sq_wqe_info {
336 /* dirtied @completion */
341 u16 pc ____cacheline_aligned_in_smp;
343 struct mlx5e_sq_stats stats;
347 /* write@xmit, read@completion */
349 struct mlx5e_sq_dma *dma_fifo;
350 struct mlx5e_tx_wqe_info *wqe_info;
354 struct mlx5_wq_cyc wq;
356 void __iomem *uar_map;
357 struct netdev_queue *txq;
363 struct mlx5e_tstamp *tstamp;
368 struct mlx5_wq_ctrl wq_ctrl;
369 struct mlx5e_channel *channel;
372 } ____cacheline_aligned_in_smp;
377 /* dirtied @rx completion */
383 /* write@xmit, read@completion */
385 struct mlx5e_dma_info *di;
390 struct mlx5_wq_cyc wq;
391 void __iomem *uar_map;
399 struct mlx5_wq_ctrl wq_ctrl;
400 struct mlx5e_channel *channel;
401 } ____cacheline_aligned_in_smp;
406 /* dirtied @completion */
410 u16 pc ____cacheline_aligned_in_smp;
416 /* write@xmit, read@completion */
418 struct mlx5e_sq_wqe_info *ico_wqe;
422 struct mlx5_wq_cyc wq;
423 void __iomem *uar_map;
431 struct mlx5_wq_ctrl wq_ctrl;
432 struct mlx5e_channel *channel;
433 } ____cacheline_aligned_in_smp;
436 mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n)
438 return (((wq->sz_m1 & (cc - pc)) >= n) || (cc == pc));
441 struct mlx5e_dma_info {
446 struct mlx5e_umr_dma_info {
449 struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE];
450 struct mlx5e_umr_wqe wqe;
453 struct mlx5e_mpw_info {
454 struct mlx5e_umr_dma_info umr;
455 u16 consumed_strides;
456 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
459 struct mlx5e_rx_am_stats {
460 int ppms; /* packets per msec */
461 int epms; /* events per msec */
464 struct mlx5e_rx_am_sample {
466 unsigned int pkt_ctr;
470 struct mlx5e_rx_am { /* Adaptive Moderation */
472 struct mlx5e_rx_am_stats prev_stats;
473 struct mlx5e_rx_am_sample start_sample;
474 struct work_struct work;
483 /* a single cache unit is capable to serve one napi call (for non-striding rq)
484 * or a MPWQE (for striding rq).
486 #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \
487 MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT)
488 #define MLX5E_CACHE_SIZE (2 * roundup_pow_of_two(MLX5E_CACHE_UNIT))
489 struct mlx5e_page_cache {
492 struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE];
496 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*);
497 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq*, struct mlx5e_rx_wqe*, u16);
498 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16);
502 struct mlx5_wq_ll wq;
505 struct mlx5e_dma_info *dma_info;
507 struct mlx5e_mpw_info *info;
513 u32 wqe_sz; /* wqe data buffer size */
514 u8 map_dir; /* dma map direction */
519 struct net_device *netdev;
520 struct mlx5e_tstamp *tstamp;
521 struct mlx5e_rq_stats stats;
523 struct mlx5e_page_cache page_cache;
525 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
526 mlx5e_fp_alloc_wqe alloc_wqe;
527 mlx5e_fp_dealloc_wqe dealloc_wqe;
533 struct mlx5e_rx_am am; /* Adaptive Moderation */
536 struct bpf_prog *xdp_prog;
537 struct mlx5e_xdpsq xdpsq;
540 struct mlx5_wq_ctrl wq_ctrl;
543 u32 mpwqe_num_strides;
545 struct mlx5e_channel *channel;
546 struct mlx5_core_dev *mdev;
547 struct mlx5_core_mkey umr_mkey;
548 } ____cacheline_aligned_in_smp;
551 MLX5E_CHANNEL_NAPI_SCHED = 1,
554 struct mlx5e_channel {
557 struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC];
558 struct mlx5e_icosq icosq; /* internal control operations */
560 struct napi_struct napi;
562 struct net_device *netdev;
568 struct mlx5e_priv *priv;
569 struct mlx5_core_dev *mdev;
570 struct mlx5e_tstamp *tstamp;
575 struct mlx5e_channels {
576 struct mlx5e_channel **c;
578 struct mlx5e_params params;
581 enum mlx5e_traffic_types {
586 MLX5E_TT_IPV4_IPSEC_AH,
587 MLX5E_TT_IPV6_IPSEC_AH,
588 MLX5E_TT_IPV4_IPSEC_ESP,
589 MLX5E_TT_IPV6_IPSEC_ESP,
594 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
598 MLX5E_STATE_ASYNC_EVENTS_ENABLED,
600 MLX5E_STATE_DESTROYING,
603 struct mlx5e_vxlan_db {
604 spinlock_t lock; /* protect vxlan table */
605 struct radix_tree_root tree;
608 struct mlx5e_l2_rule {
609 u8 addr[ETH_ALEN + 2];
610 struct mlx5_flow_handle *rule;
613 struct mlx5e_flow_table {
615 struct mlx5_flow_table *t;
616 struct mlx5_flow_group **g;
619 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
621 struct mlx5e_tc_table {
622 struct mlx5_flow_table *t;
624 struct rhashtable_params ht_params;
625 struct rhashtable ht;
628 struct mlx5e_vlan_table {
629 struct mlx5e_flow_table ft;
630 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
631 struct mlx5_flow_handle *active_vlans_rule[VLAN_N_VID];
632 struct mlx5_flow_handle *untagged_rule;
633 struct mlx5_flow_handle *any_cvlan_rule;
634 struct mlx5_flow_handle *any_svlan_rule;
635 bool filter_disabled;
638 struct mlx5e_l2_table {
639 struct mlx5e_flow_table ft;
640 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
641 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
642 struct mlx5e_l2_rule broadcast;
643 struct mlx5e_l2_rule allmulti;
644 struct mlx5e_l2_rule promisc;
645 bool broadcast_enabled;
646 bool allmulti_enabled;
647 bool promisc_enabled;
650 /* L3/L4 traffic type classifier */
651 struct mlx5e_ttc_table {
652 struct mlx5e_flow_table ft;
653 struct mlx5_flow_handle *rules[MLX5E_NUM_TT];
656 #define ARFS_HASH_SHIFT BITS_PER_BYTE
657 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
659 struct mlx5e_flow_table ft;
660 struct mlx5_flow_handle *default_rule;
661 struct hlist_head rules_hash[ARFS_HASH_SIZE];
672 struct mlx5e_arfs_tables {
673 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
674 /* Protect aRFS rules list */
675 spinlock_t arfs_lock;
676 struct list_head rules;
678 struct workqueue_struct *wq;
683 MLX5E_VLAN_FT_LEVEL = 0,
689 struct mlx5e_ethtool_table {
690 struct mlx5_flow_table *ft;
694 #define ETHTOOL_NUM_L3_L4_FTS 7
695 #define ETHTOOL_NUM_L2_FTS 4
697 struct mlx5e_ethtool_steering {
698 struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS];
699 struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS];
700 struct list_head rules;
704 struct mlx5e_flow_steering {
705 struct mlx5_flow_namespace *ns;
706 struct mlx5e_ethtool_steering ethtool;
707 struct mlx5e_tc_table tc;
708 struct mlx5e_vlan_table vlan;
709 struct mlx5e_l2_table l2;
710 struct mlx5e_ttc_table ttc;
711 struct mlx5e_arfs_tables arfs;
721 struct mlx5e_rqt rqt;
722 struct list_head list;
731 /* priv data path fields - start */
732 struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
733 int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
734 /* priv data path fields - end */
737 struct mutex state_lock; /* Protects Interface state */
738 struct mlx5e_rq drop_rq;
740 struct mlx5e_channels channels;
741 u32 tisn[MLX5E_MAX_NUM_TC];
742 struct mlx5e_rqt indir_rqt;
743 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
744 struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
745 u32 tx_rates[MLX5E_MAX_NUM_SQS];
747 struct mlx5e_flow_steering fs;
748 struct mlx5e_vxlan_db vxlan;
750 struct workqueue_struct *wq;
751 struct work_struct update_carrier_work;
752 struct work_struct set_rx_mode_work;
753 struct work_struct tx_timeout_work;
754 struct delayed_work update_stats_work;
756 struct mlx5_core_dev *mdev;
757 struct net_device *netdev;
758 struct mlx5e_stats stats;
759 struct mlx5e_tstamp tstamp;
761 #ifdef CONFIG_MLX5_CORE_EN_DCB
762 struct mlx5e_dcbx dcbx;
765 const struct mlx5e_profile *profile;
769 struct mlx5e_profile {
770 void (*init)(struct mlx5_core_dev *mdev,
771 struct net_device *netdev,
772 const struct mlx5e_profile *profile, void *ppriv);
773 void (*cleanup)(struct mlx5e_priv *priv);
774 int (*init_rx)(struct mlx5e_priv *priv);
775 void (*cleanup_rx)(struct mlx5e_priv *priv);
776 int (*init_tx)(struct mlx5e_priv *priv);
777 void (*cleanup_tx)(struct mlx5e_priv *priv);
778 void (*enable)(struct mlx5e_priv *priv);
779 void (*disable)(struct mlx5e_priv *priv);
780 void (*update_stats)(struct mlx5e_priv *priv);
781 int (*max_nch)(struct mlx5_core_dev *mdev);
783 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
784 mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe;
789 void mlx5e_build_ptys2ethtool_map(void);
791 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
792 void *accel_priv, select_queue_fallback_t fallback);
793 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
795 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
796 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
797 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
798 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
799 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
800 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq);
801 void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq);
802 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq);
804 void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info,
806 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
807 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
808 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
809 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
810 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
811 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
812 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
813 void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq);
814 void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
815 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
817 void mlx5e_rx_am(struct mlx5e_rq *rq);
818 void mlx5e_rx_am_work(struct work_struct *work);
819 struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);
821 void mlx5e_update_stats(struct mlx5e_priv *priv);
823 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
824 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
825 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
826 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
827 int mlx5e_self_test_num(struct mlx5e_priv *priv);
828 void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest,
830 int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info,
832 int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv,
833 struct ethtool_rxnfc *info, u32 *rule_locs);
834 int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv,
835 struct ethtool_rx_flow_spec *fs);
836 int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv,
838 void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv);
839 void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv);
840 void mlx5e_set_rx_mode_work(struct work_struct *work);
842 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
843 struct skb_shared_hwtstamps *hwts);
844 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
845 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
846 void mlx5e_pps_event_handler(struct mlx5e_priv *priv,
847 struct ptp_clock_event *event);
848 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
849 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
850 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val);
852 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
854 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
856 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
857 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
859 struct mlx5e_redirect_rqt_param {
862 u32 rqn; /* Direct RQN (Non-RSS) */
865 struct mlx5e_channels *channels;
866 } rss; /* RSS data */
870 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
871 struct mlx5e_redirect_rqt_param rrp);
872 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
873 enum mlx5e_traffic_types tt,
876 int mlx5e_open_locked(struct net_device *netdev);
877 int mlx5e_close_locked(struct net_device *netdev);
879 int mlx5e_open_channels(struct mlx5e_priv *priv,
880 struct mlx5e_channels *chs);
881 void mlx5e_close_channels(struct mlx5e_channels *chs);
883 /* Function pointer to be used to modify WH settings while
886 typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv);
887 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
888 struct mlx5e_channels *new_chs,
889 mlx5e_fp_hw_modify hw_modify);
890 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv);
891 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv);
893 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
894 u32 *indirection_rqt, int len,
896 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
898 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,
900 void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
901 struct mlx5e_params *params, u8 rq_type);
904 struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc)
906 u16 pi = *pc & wq->sz_m1;
907 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi);
908 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
910 memset(cseg, 0, sizeof(*cseg));
912 cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP);
913 cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01);
921 void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc,
922 void __iomem *uar_map,
923 struct mlx5_wqe_ctrl_seg *ctrl)
925 ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
926 /* ensure wqe is visible to device before updating doorbell record */
929 *wq->db = cpu_to_be32(pc);
931 /* ensure doorbell record is visible to device before ringing the
936 mlx5_write64((__be32 *)ctrl, uar_map, NULL);
939 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
941 struct mlx5_core_cq *mcq;
944 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc);
947 static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix)
949 return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8);
952 extern const struct ethtool_ops mlx5e_ethtool_ops;
953 #ifdef CONFIG_MLX5_CORE_EN_DCB
954 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
955 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
956 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv);
959 #ifndef CONFIG_RFS_ACCEL
960 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
965 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
967 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
972 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
977 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
978 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
979 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
980 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
981 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
982 u16 rxq_index, u32 flow_id);
985 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
986 int mlx5e_create_tir(struct mlx5_core_dev *mdev,
987 struct mlx5e_tir *tir, u32 *in, int inlen);
988 void mlx5e_destroy_tir(struct mlx5_core_dev *mdev,
989 struct mlx5e_tir *tir);
990 int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev);
991 void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev);
992 int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb);
994 /* common netdev helpers */
995 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv);
997 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv);
998 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv);
1000 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv);
1001 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv);
1002 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv);
1003 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv);
1004 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt);
1006 int mlx5e_create_ttc_table(struct mlx5e_priv *priv, u32 underlay_qpn);
1007 void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv);
1009 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
1010 u32 underlay_qpn, u32 *tisn);
1011 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn);
1013 int mlx5e_create_tises(struct mlx5e_priv *priv);
1014 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv);
1015 int mlx5e_close(struct net_device *netdev);
1016 int mlx5e_open(struct net_device *netdev);
1017 void mlx5e_update_stats_work(struct work_struct *work);
1018 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout);
1020 /* mlx5e generic netdev management API */
1022 mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile,
1024 int mlx5e_attach_netdev(struct mlx5e_priv *priv);
1025 void mlx5e_detach_netdev(struct mlx5e_priv *priv);
1026 void mlx5e_destroy_netdev(struct mlx5e_priv *priv);
1027 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
1028 struct mlx5e_params *params,
1031 #endif /* __MLX5_EN_H__ */