2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 #include <linux/device.h>
33 #include <linux/netdevice.h>
36 #define MLX5E_MAX_PRIORITY 8
38 #define MLX5E_100MB (100000)
39 #define MLX5E_1GB (1000000)
41 #define MLX5E_CEE_STATE_UP 1
42 #define MLX5E_CEE_STATE_DOWN 0
44 /* If dcbx mode is non-host set the dcbx mode to host.
46 static int mlx5e_dcbnl_set_dcbx_mode(struct mlx5e_priv *priv,
47 enum mlx5_dcbx_oper_mode mode)
49 struct mlx5_core_dev *mdev = priv->mdev;
50 u32 param[MLX5_ST_SZ_DW(dcbx_param)];
53 err = mlx5_query_port_dcbx_param(mdev, param);
57 MLX5_SET(dcbx_param, param, version_admin, mode);
58 if (mode != MLX5E_DCBX_PARAM_VER_OPER_HOST)
59 MLX5_SET(dcbx_param, param, willing_admin, 1);
61 return mlx5_set_port_dcbx_param(mdev, param);
64 static int mlx5e_dcbnl_switch_to_host_mode(struct mlx5e_priv *priv)
66 struct mlx5e_dcbx *dcbx = &priv->dcbx;
69 if (!MLX5_CAP_GEN(priv->mdev, dcbx))
72 if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_HOST)
75 err = mlx5e_dcbnl_set_dcbx_mode(priv, MLX5E_DCBX_PARAM_VER_OPER_HOST);
79 dcbx->mode = MLX5E_DCBX_PARAM_VER_OPER_HOST;
83 static int mlx5e_dcbnl_ieee_getets(struct net_device *netdev,
86 struct mlx5e_priv *priv = netdev_priv(netdev);
87 struct mlx5_core_dev *mdev = priv->mdev;
91 if (!MLX5_CAP_GEN(priv->mdev, ets))
94 ets->ets_cap = mlx5_max_tc(priv->mdev) + 1;
95 for (i = 0; i < ets->ets_cap; i++) {
96 err = mlx5_query_port_prio_tc(mdev, i, &ets->prio_tc[i]);
101 for (i = 0; i < ets->ets_cap; i++) {
102 err = mlx5_query_port_tc_bw_alloc(mdev, i, &ets->tc_tx_bw[i]);
105 if (ets->tc_tx_bw[i] < MLX5E_MAX_BW_ALLOC)
106 priv->dcbx.tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
109 memcpy(ets->tc_tsa, priv->dcbx.tc_tsa, sizeof(ets->tc_tsa));
115 MLX5E_VENDOR_TC_GROUP_NUM = 7,
116 MLX5E_ETS_TC_GROUP_NUM = 0,
119 static void mlx5e_build_tc_group(struct ieee_ets *ets, u8 *tc_group, int max_tc)
121 bool any_tc_mapped_to_ets = false;
125 for (i = 0; i <= max_tc; i++)
126 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS)
127 any_tc_mapped_to_ets = true;
129 strict_group = any_tc_mapped_to_ets ? 1 : 0;
131 for (i = 0; i <= max_tc; i++) {
132 switch (ets->tc_tsa[i]) {
133 case IEEE_8021QAZ_TSA_VENDOR:
134 tc_group[i] = MLX5E_VENDOR_TC_GROUP_NUM;
136 case IEEE_8021QAZ_TSA_STRICT:
137 tc_group[i] = strict_group++;
139 case IEEE_8021QAZ_TSA_ETS:
140 tc_group[i] = MLX5E_ETS_TC_GROUP_NUM;
146 static void mlx5e_build_tc_tx_bw(struct ieee_ets *ets, u8 *tc_tx_bw,
147 u8 *tc_group, int max_tc)
151 for (i = 0; i <= max_tc; i++) {
152 switch (ets->tc_tsa[i]) {
153 case IEEE_8021QAZ_TSA_VENDOR:
154 tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
156 case IEEE_8021QAZ_TSA_STRICT:
157 tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
159 case IEEE_8021QAZ_TSA_ETS:
160 tc_tx_bw[i] = ets->tc_tx_bw[i];
166 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets)
168 struct mlx5_core_dev *mdev = priv->mdev;
169 u8 tc_tx_bw[IEEE_8021QAZ_MAX_TCS];
170 u8 tc_group[IEEE_8021QAZ_MAX_TCS];
171 int max_tc = mlx5_max_tc(mdev);
174 mlx5e_build_tc_group(ets, tc_group, max_tc);
175 mlx5e_build_tc_tx_bw(ets, tc_tx_bw, tc_group, max_tc);
177 err = mlx5_set_port_prio_tc(mdev, ets->prio_tc);
181 err = mlx5_set_port_tc_group(mdev, tc_group);
185 err = mlx5_set_port_tc_bw_alloc(mdev, tc_tx_bw);
190 memcpy(priv->dcbx.tc_tsa, ets->tc_tsa, sizeof(ets->tc_tsa));
195 static int mlx5e_dbcnl_validate_ets(struct net_device *netdev,
196 struct ieee_ets *ets)
201 /* Validate Priority */
202 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
203 if (ets->prio_tc[i] >= MLX5E_MAX_PRIORITY) {
205 "Failed to validate ETS: priority value greater than max(%d)\n",
211 /* Validate Bandwidth Sum */
212 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
213 if (ets->tc_tsa[i] == IEEE_8021QAZ_TSA_ETS) {
214 if (!ets->tc_tx_bw[i]) {
216 "Failed to validate ETS: BW 0 is illegal\n");
220 bw_sum += ets->tc_tx_bw[i];
224 if (bw_sum != 0 && bw_sum != 100) {
226 "Failed to validate ETS: BW sum is illegal\n");
232 static int mlx5e_dcbnl_ieee_setets(struct net_device *netdev,
233 struct ieee_ets *ets)
235 struct mlx5e_priv *priv = netdev_priv(netdev);
238 if (!MLX5_CAP_GEN(priv->mdev, ets))
241 err = mlx5e_dbcnl_validate_ets(netdev, ets);
245 err = mlx5e_dcbnl_ieee_setets_core(priv, ets);
252 static int mlx5e_dcbnl_ieee_getpfc(struct net_device *dev,
253 struct ieee_pfc *pfc)
255 struct mlx5e_priv *priv = netdev_priv(dev);
256 struct mlx5_core_dev *mdev = priv->mdev;
257 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
260 pfc->pfc_cap = mlx5_max_tc(mdev) + 1;
261 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
262 pfc->requests[i] = PPORT_PER_PRIO_GET(pstats, i, tx_pause);
263 pfc->indications[i] = PPORT_PER_PRIO_GET(pstats, i, rx_pause);
266 return mlx5_query_port_pfc(mdev, &pfc->pfc_en, NULL);
269 static int mlx5e_dcbnl_ieee_setpfc(struct net_device *dev,
270 struct ieee_pfc *pfc)
272 struct mlx5e_priv *priv = netdev_priv(dev);
273 struct mlx5_core_dev *mdev = priv->mdev;
277 mlx5_query_port_pfc(mdev, &curr_pfc_en, NULL);
279 if (pfc->pfc_en == curr_pfc_en)
282 ret = mlx5_set_port_pfc(mdev, pfc->pfc_en, pfc->pfc_en);
283 mlx5_toggle_port_link(mdev);
288 static u8 mlx5e_dcbnl_getdcbx(struct net_device *dev)
290 struct mlx5e_priv *priv = netdev_priv(dev);
291 struct mlx5e_dcbx *dcbx = &priv->dcbx;
292 u8 mode = DCB_CAP_DCBX_VER_IEEE | DCB_CAP_DCBX_VER_CEE;
294 if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_HOST)
295 mode |= DCB_CAP_DCBX_HOST;
300 static u8 mlx5e_dcbnl_setdcbx(struct net_device *dev, u8 mode)
302 struct mlx5e_priv *priv = netdev_priv(dev);
303 struct mlx5e_dcbx *dcbx = &priv->dcbx;
305 if ((!mode) && MLX5_CAP_GEN(priv->mdev, dcbx)) {
306 if (dcbx->mode == MLX5E_DCBX_PARAM_VER_OPER_AUTO)
309 /* set dcbx to fw controlled */
310 if (!mlx5e_dcbnl_set_dcbx_mode(priv, MLX5E_DCBX_PARAM_VER_OPER_AUTO)) {
311 dcbx->mode = MLX5E_DCBX_PARAM_VER_OPER_AUTO;
318 if (mlx5e_dcbnl_switch_to_host_mode(netdev_priv(dev)))
321 if ((mode & DCB_CAP_DCBX_LLD_MANAGED) ||
322 !(mode & DCB_CAP_DCBX_VER_CEE) ||
323 !(mode & DCB_CAP_DCBX_VER_IEEE) ||
324 !(mode & DCB_CAP_DCBX_HOST))
330 static int mlx5e_dcbnl_ieee_getmaxrate(struct net_device *netdev,
331 struct ieee_maxrate *maxrate)
333 struct mlx5e_priv *priv = netdev_priv(netdev);
334 struct mlx5_core_dev *mdev = priv->mdev;
335 u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
336 u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
340 err = mlx5_query_port_ets_rate_limit(mdev, max_bw_value, max_bw_unit);
344 memset(maxrate->tc_maxrate, 0, sizeof(maxrate->tc_maxrate));
346 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
347 switch (max_bw_unit[i]) {
348 case MLX5_100_MBPS_UNIT:
349 maxrate->tc_maxrate[i] = max_bw_value[i] * MLX5E_100MB;
352 maxrate->tc_maxrate[i] = max_bw_value[i] * MLX5E_1GB;
354 case MLX5_BW_NO_LIMIT:
357 WARN(true, "non-supported BW unit");
365 static int mlx5e_dcbnl_ieee_setmaxrate(struct net_device *netdev,
366 struct ieee_maxrate *maxrate)
368 struct mlx5e_priv *priv = netdev_priv(netdev);
369 struct mlx5_core_dev *mdev = priv->mdev;
370 u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
371 u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
372 __u64 upper_limit_mbps = roundup(255 * MLX5E_100MB, MLX5E_1GB);
375 memset(max_bw_value, 0, sizeof(max_bw_value));
376 memset(max_bw_unit, 0, sizeof(max_bw_unit));
378 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
379 if (!maxrate->tc_maxrate[i]) {
380 max_bw_unit[i] = MLX5_BW_NO_LIMIT;
383 if (maxrate->tc_maxrate[i] < upper_limit_mbps) {
384 max_bw_value[i] = div_u64(maxrate->tc_maxrate[i],
386 max_bw_value[i] = max_bw_value[i] ? max_bw_value[i] : 1;
387 max_bw_unit[i] = MLX5_100_MBPS_UNIT;
389 max_bw_value[i] = div_u64(maxrate->tc_maxrate[i],
391 max_bw_unit[i] = MLX5_GBPS_UNIT;
395 return mlx5_modify_port_ets_rate_limit(mdev, max_bw_value, max_bw_unit);
398 static u8 mlx5e_dcbnl_setall(struct net_device *netdev)
400 struct mlx5e_priv *priv = netdev_priv(netdev);
401 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
402 struct mlx5_core_dev *mdev = priv->mdev;
405 int err = -EOPNOTSUPP;
408 if (!MLX5_CAP_GEN(mdev, ets))
411 memset(&ets, 0, sizeof(ets));
412 memset(&pfc, 0, sizeof(pfc));
414 ets.ets_cap = IEEE_8021QAZ_MAX_TCS;
415 for (i = 0; i < CEE_DCBX_MAX_PGS; i++) {
416 ets.tc_tx_bw[i] = cee_cfg->pg_bw_pct[i];
417 ets.tc_rx_bw[i] = cee_cfg->pg_bw_pct[i];
418 ets.tc_tsa[i] = IEEE_8021QAZ_TSA_ETS;
419 ets.prio_tc[i] = cee_cfg->prio_to_pg_map[i];
422 err = mlx5e_dbcnl_validate_ets(netdev, &ets);
425 "%s, Failed to validate ETS: %d\n", __func__, err);
429 err = mlx5e_dcbnl_ieee_setets_core(priv, &ets);
432 "%s, Failed to set ETS: %d\n", __func__, err);
437 pfc.pfc_cap = mlx5_max_tc(mdev) + 1;
438 if (!cee_cfg->pfc_enable)
441 for (i = 0; i < CEE_DCBX_MAX_PRIO; i++)
442 pfc.pfc_en |= cee_cfg->pfc_setting[i] << i;
444 err = mlx5e_dcbnl_ieee_setpfc(netdev, &pfc);
447 "%s, Failed to set PFC: %d\n", __func__, err);
451 return err ? MLX5_DCB_NO_CHG : MLX5_DCB_CHG_RESET;
454 static u8 mlx5e_dcbnl_getstate(struct net_device *netdev)
456 return MLX5E_CEE_STATE_UP;
459 static void mlx5e_dcbnl_getpermhwaddr(struct net_device *netdev,
462 struct mlx5e_priv *priv = netdev_priv(netdev);
467 mlx5_query_nic_vport_mac_address(priv->mdev, 0, perm_addr);
470 static void mlx5e_dcbnl_setpgtccfgtx(struct net_device *netdev,
471 int priority, u8 prio_type,
472 u8 pgid, u8 bw_pct, u8 up_map)
474 struct mlx5e_priv *priv = netdev_priv(netdev);
475 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
477 if (priority >= CEE_DCBX_MAX_PRIO) {
479 "%s, priority is out of range\n", __func__);
483 if (pgid >= CEE_DCBX_MAX_PGS) {
485 "%s, priority group is out of range\n", __func__);
489 cee_cfg->prio_to_pg_map[priority] = pgid;
492 static void mlx5e_dcbnl_setpgbwgcfgtx(struct net_device *netdev,
495 struct mlx5e_priv *priv = netdev_priv(netdev);
496 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
498 if (pgid >= CEE_DCBX_MAX_PGS) {
500 "%s, priority group is out of range\n", __func__);
504 cee_cfg->pg_bw_pct[pgid] = bw_pct;
507 static void mlx5e_dcbnl_getpgtccfgtx(struct net_device *netdev,
508 int priority, u8 *prio_type,
509 u8 *pgid, u8 *bw_pct, u8 *up_map)
511 struct mlx5e_priv *priv = netdev_priv(netdev);
512 struct mlx5_core_dev *mdev = priv->mdev;
514 if (!MLX5_CAP_GEN(priv->mdev, ets)) {
515 netdev_err(netdev, "%s, ets is not supported\n", __func__);
519 if (priority >= CEE_DCBX_MAX_PRIO) {
521 "%s, priority is out of range\n", __func__);
529 if (mlx5_query_port_prio_tc(mdev, priority, pgid))
533 static void mlx5e_dcbnl_getpgbwgcfgtx(struct net_device *netdev,
534 int pgid, u8 *bw_pct)
536 struct mlx5e_priv *priv = netdev_priv(netdev);
537 struct mlx5_core_dev *mdev = priv->mdev;
539 if (pgid >= CEE_DCBX_MAX_PGS) {
541 "%s, priority group is out of range\n", __func__);
545 if (mlx5_query_port_tc_bw_alloc(mdev, pgid, bw_pct))
549 static void mlx5e_dcbnl_setpfccfg(struct net_device *netdev,
550 int priority, u8 setting)
552 struct mlx5e_priv *priv = netdev_priv(netdev);
553 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
555 if (priority >= CEE_DCBX_MAX_PRIO) {
557 "%s, priority is out of range\n", __func__);
564 cee_cfg->pfc_setting[priority] = setting;
568 mlx5e_dcbnl_get_priority_pfc(struct net_device *netdev,
569 int priority, u8 *setting)
574 err = mlx5e_dcbnl_ieee_getpfc(netdev, &pfc);
579 *setting = (pfc.pfc_en >> priority) & 0x01;
584 static void mlx5e_dcbnl_getpfccfg(struct net_device *netdev,
585 int priority, u8 *setting)
587 if (priority >= CEE_DCBX_MAX_PRIO) {
589 "%s, priority is out of range\n", __func__);
596 mlx5e_dcbnl_get_priority_pfc(netdev, priority, setting);
599 static u8 mlx5e_dcbnl_getcap(struct net_device *netdev,
602 struct mlx5e_priv *priv = netdev_priv(netdev);
603 struct mlx5_core_dev *mdev = priv->mdev;
607 case DCB_CAP_ATTR_PG:
610 case DCB_CAP_ATTR_PFC:
613 case DCB_CAP_ATTR_UP2TC:
616 case DCB_CAP_ATTR_PG_TCS:
617 *cap = 1 << mlx5_max_tc(mdev);
619 case DCB_CAP_ATTR_PFC_TCS:
620 *cap = 1 << mlx5_max_tc(mdev);
622 case DCB_CAP_ATTR_GSP:
625 case DCB_CAP_ATTR_BCN:
628 case DCB_CAP_ATTR_DCBX:
629 *cap = (DCB_CAP_DCBX_LLD_MANAGED |
630 DCB_CAP_DCBX_VER_CEE |
631 DCB_CAP_DCBX_STATIC);
642 static int mlx5e_dcbnl_getnumtcs(struct net_device *netdev,
645 struct mlx5e_priv *priv = netdev_priv(netdev);
646 struct mlx5_core_dev *mdev = priv->mdev;
649 case DCB_NUMTCS_ATTR_PG:
650 case DCB_NUMTCS_ATTR_PFC:
651 *num = mlx5_max_tc(mdev) + 1;
660 static u8 mlx5e_dcbnl_getpfcstate(struct net_device *netdev)
664 if (mlx5e_dcbnl_ieee_getpfc(netdev, &pfc))
665 return MLX5E_CEE_STATE_DOWN;
667 return pfc.pfc_en ? MLX5E_CEE_STATE_UP : MLX5E_CEE_STATE_DOWN;
670 static void mlx5e_dcbnl_setpfcstate(struct net_device *netdev, u8 state)
672 struct mlx5e_priv *priv = netdev_priv(netdev);
673 struct mlx5e_cee_config *cee_cfg = &priv->dcbx.cee_cfg;
675 if ((state != MLX5E_CEE_STATE_UP) && (state != MLX5E_CEE_STATE_DOWN))
678 cee_cfg->pfc_enable = state;
681 const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops = {
682 .ieee_getets = mlx5e_dcbnl_ieee_getets,
683 .ieee_setets = mlx5e_dcbnl_ieee_setets,
684 .ieee_getmaxrate = mlx5e_dcbnl_ieee_getmaxrate,
685 .ieee_setmaxrate = mlx5e_dcbnl_ieee_setmaxrate,
686 .ieee_getpfc = mlx5e_dcbnl_ieee_getpfc,
687 .ieee_setpfc = mlx5e_dcbnl_ieee_setpfc,
688 .getdcbx = mlx5e_dcbnl_getdcbx,
689 .setdcbx = mlx5e_dcbnl_setdcbx,
692 .setall = mlx5e_dcbnl_setall,
693 .getstate = mlx5e_dcbnl_getstate,
694 .getpermhwaddr = mlx5e_dcbnl_getpermhwaddr,
696 .setpgtccfgtx = mlx5e_dcbnl_setpgtccfgtx,
697 .setpgbwgcfgtx = mlx5e_dcbnl_setpgbwgcfgtx,
698 .getpgtccfgtx = mlx5e_dcbnl_getpgtccfgtx,
699 .getpgbwgcfgtx = mlx5e_dcbnl_getpgbwgcfgtx,
701 .setpfccfg = mlx5e_dcbnl_setpfccfg,
702 .getpfccfg = mlx5e_dcbnl_getpfccfg,
703 .getcap = mlx5e_dcbnl_getcap,
704 .getnumtcs = mlx5e_dcbnl_getnumtcs,
705 .getpfcstate = mlx5e_dcbnl_getpfcstate,
706 .setpfcstate = mlx5e_dcbnl_setpfcstate,
709 static void mlx5e_dcbnl_query_dcbx_mode(struct mlx5e_priv *priv,
710 enum mlx5_dcbx_oper_mode *mode)
712 u32 out[MLX5_ST_SZ_DW(dcbx_param)];
714 *mode = MLX5E_DCBX_PARAM_VER_OPER_HOST;
716 if (!mlx5_query_port_dcbx_param(priv->mdev, out))
717 *mode = MLX5_GET(dcbx_param, out, version_oper);
719 /* From driver's point of view, we only care if the mode
720 * is host (HOST) or non-host (AUTO)
722 if (*mode != MLX5E_DCBX_PARAM_VER_OPER_HOST)
723 *mode = MLX5E_DCBX_PARAM_VER_OPER_AUTO;
726 static void mlx5e_ets_init(struct mlx5e_priv *priv)
731 if (!MLX5_CAP_GEN(priv->mdev, ets))
734 memset(&ets, 0, sizeof(ets));
735 ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
736 for (i = 0; i < ets.ets_cap; i++) {
737 ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
738 ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
742 memcpy(priv->dcbx.tc_tsa, ets.tc_tsa, sizeof(ets.tc_tsa));
744 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
748 mlx5e_dcbnl_ieee_setets_core(priv, &ets);
751 void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv)
753 struct mlx5e_dcbx *dcbx = &priv->dcbx;
755 if (MLX5_CAP_GEN(priv->mdev, dcbx))
756 mlx5e_dcbnl_query_dcbx_mode(priv, &dcbx->mode);
758 mlx5e_ets_init(priv);