2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
36 struct ethtool_drvinfo *drvinfo)
38 struct mlx5_core_dev *mdev = priv->mdev;
40 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
41 strlcpy(drvinfo->version, DRIVER_VERSION,
42 sizeof(drvinfo->version));
43 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
45 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
47 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
48 sizeof(drvinfo->bus_info));
51 static void mlx5e_get_drvinfo(struct net_device *dev,
52 struct ethtool_drvinfo *drvinfo)
54 struct mlx5e_priv *priv = netdev_priv(dev);
56 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
59 struct ptys2ethtool_config {
60 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
61 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
65 static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
67 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
69 struct ptys2ethtool_config *cfg; \
70 const unsigned int modes[] = { __VA_ARGS__ }; \
72 cfg = &ptys2ethtool_table[reg_]; \
73 cfg->speed = speed_; \
74 bitmap_zero(cfg->supported, \
75 __ETHTOOL_LINK_MODE_MASK_NBITS); \
76 bitmap_zero(cfg->advertised, \
77 __ETHTOOL_LINK_MODE_MASK_NBITS); \
78 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
79 __set_bit(modes[i], cfg->supported); \
80 __set_bit(modes[i], cfg->advertised); \
84 void mlx5e_build_ptys2ethtool_map(void)
86 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000,
87 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
88 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000,
89 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
90 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000,
91 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
92 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000,
93 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000,
95 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000,
97 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000,
99 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000,
101 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000,
103 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000,
105 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000,
107 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000,
109 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000,
111 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000,
113 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000,
115 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000,
117 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000,
119 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000,
121 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000,
123 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000,
125 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000,
127 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
128 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000,
129 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
130 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000,
131 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
132 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000,
133 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
134 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000,
135 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
138 int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
140 int i, num_stats = 0;
144 for (i = 0; i < mlx5e_num_stats_grps; i++)
145 num_stats += mlx5e_stats_grps[i].get_num_stats(priv);
147 case ETH_SS_PRIV_FLAGS:
148 return ARRAY_SIZE(mlx5e_priv_flags);
150 return mlx5e_self_test_num(priv);
157 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
159 struct mlx5e_priv *priv = netdev_priv(dev);
161 return mlx5e_ethtool_get_sset_count(priv, sset);
164 static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, u8 *data)
168 for (i = 0; i < mlx5e_num_stats_grps; i++)
169 idx = mlx5e_stats_grps[i].fill_strings(priv, data, idx);
172 void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
177 case ETH_SS_PRIV_FLAGS:
178 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
179 strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
183 for (i = 0; i < mlx5e_self_test_num(priv); i++)
184 strcpy(data + i * ETH_GSTRING_LEN,
185 mlx5e_self_tests[i]);
189 mlx5e_fill_stats_strings(priv, data);
194 static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
196 struct mlx5e_priv *priv = netdev_priv(dev);
198 mlx5e_ethtool_get_strings(priv, stringset, data);
201 void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
202 struct ethtool_stats *stats, u64 *data)
206 mutex_lock(&priv->state_lock);
207 mlx5e_update_stats(priv);
208 mutex_unlock(&priv->state_lock);
210 for (i = 0; i < mlx5e_num_stats_grps; i++)
211 idx = mlx5e_stats_grps[i].fill_stats(priv, data, idx);
214 static void mlx5e_get_ethtool_stats(struct net_device *dev,
215 struct ethtool_stats *stats,
218 struct mlx5e_priv *priv = netdev_priv(dev);
220 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
223 void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
224 struct ethtool_ringparam *param)
226 param->rx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
227 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
228 param->rx_pending = 1 << priv->channels.params.log_rq_mtu_frames;
229 param->tx_pending = 1 << priv->channels.params.log_sq_size;
232 static void mlx5e_get_ringparam(struct net_device *dev,
233 struct ethtool_ringparam *param)
235 struct mlx5e_priv *priv = netdev_priv(dev);
237 mlx5e_ethtool_get_ringparam(priv, param);
240 int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
241 struct ethtool_ringparam *param)
243 struct mlx5e_channels new_channels = {};
248 if (param->rx_jumbo_pending) {
249 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
253 if (param->rx_mini_pending) {
254 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
259 if (param->rx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
260 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
261 __func__, param->rx_pending,
262 1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
266 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
267 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
268 __func__, param->tx_pending,
269 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
273 log_rq_size = order_base_2(param->rx_pending);
274 log_sq_size = order_base_2(param->tx_pending);
276 if (log_rq_size == priv->channels.params.log_rq_mtu_frames &&
277 log_sq_size == priv->channels.params.log_sq_size)
280 mutex_lock(&priv->state_lock);
282 new_channels.params = priv->channels.params;
283 new_channels.params.log_rq_mtu_frames = log_rq_size;
284 new_channels.params.log_sq_size = log_sq_size;
286 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
287 priv->channels.params = new_channels.params;
291 err = mlx5e_open_channels(priv, &new_channels);
295 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
298 mutex_unlock(&priv->state_lock);
303 static int mlx5e_set_ringparam(struct net_device *dev,
304 struct ethtool_ringparam *param)
306 struct mlx5e_priv *priv = netdev_priv(dev);
308 return mlx5e_ethtool_set_ringparam(priv, param);
311 void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
312 struct ethtool_channels *ch)
314 ch->max_combined = priv->profile->max_nch(priv->mdev);
315 ch->combined_count = priv->channels.params.num_channels;
318 static void mlx5e_get_channels(struct net_device *dev,
319 struct ethtool_channels *ch)
321 struct mlx5e_priv *priv = netdev_priv(dev);
323 mlx5e_ethtool_get_channels(priv, ch);
326 int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
327 struct ethtool_channels *ch)
329 unsigned int count = ch->combined_count;
330 struct mlx5e_channels new_channels = {};
335 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
340 if (priv->channels.params.num_channels == count)
343 mutex_lock(&priv->state_lock);
345 new_channels.params = priv->channels.params;
346 new_channels.params.num_channels = count;
347 if (!netif_is_rxfh_configured(priv->netdev))
348 mlx5e_build_default_indir_rqt(new_channels.params.indirection_rqt,
349 MLX5E_INDIR_RQT_SIZE, count);
351 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
352 priv->channels.params = new_channels.params;
356 /* Create fresh channels with new parameters */
357 err = mlx5e_open_channels(priv, &new_channels);
361 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
363 mlx5e_arfs_disable(priv);
365 /* Switch to new channels, set new parameters and close old ones */
366 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
369 err = mlx5e_arfs_enable(priv);
371 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
376 mutex_unlock(&priv->state_lock);
381 static int mlx5e_set_channels(struct net_device *dev,
382 struct ethtool_channels *ch)
384 struct mlx5e_priv *priv = netdev_priv(dev);
386 return mlx5e_ethtool_set_channels(priv, ch);
389 int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
390 struct ethtool_coalesce *coal)
392 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
395 coal->rx_coalesce_usecs = priv->channels.params.rx_cq_moderation.usec;
396 coal->rx_max_coalesced_frames = priv->channels.params.rx_cq_moderation.pkts;
397 coal->tx_coalesce_usecs = priv->channels.params.tx_cq_moderation.usec;
398 coal->tx_max_coalesced_frames = priv->channels.params.tx_cq_moderation.pkts;
399 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_dim_enabled;
404 static int mlx5e_get_coalesce(struct net_device *netdev,
405 struct ethtool_coalesce *coal)
407 struct mlx5e_priv *priv = netdev_priv(netdev);
409 return mlx5e_ethtool_get_coalesce(priv, coal);
412 #define MLX5E_MAX_COAL_TIME MLX5_MAX_CQ_PERIOD
413 #define MLX5E_MAX_COAL_FRAMES MLX5_MAX_CQ_COUNT
416 mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
418 struct mlx5_core_dev *mdev = priv->mdev;
422 for (i = 0; i < priv->channels.num; ++i) {
423 struct mlx5e_channel *c = priv->channels.c[i];
425 for (tc = 0; tc < c->num_tc; tc++) {
426 mlx5_core_modify_cq_moderation(mdev,
428 coal->tx_coalesce_usecs,
429 coal->tx_max_coalesced_frames);
432 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
433 coal->rx_coalesce_usecs,
434 coal->rx_max_coalesced_frames);
438 int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
439 struct ethtool_coalesce *coal)
441 struct mlx5_core_dev *mdev = priv->mdev;
442 struct mlx5e_channels new_channels = {};
446 if (!MLX5_CAP_GEN(mdev, cq_moderation))
449 if (coal->tx_coalesce_usecs > MLX5E_MAX_COAL_TIME ||
450 coal->rx_coalesce_usecs > MLX5E_MAX_COAL_TIME) {
451 netdev_info(priv->netdev, "%s: maximum coalesce time supported is %lu usecs\n",
452 __func__, MLX5E_MAX_COAL_TIME);
456 if (coal->tx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES ||
457 coal->rx_max_coalesced_frames > MLX5E_MAX_COAL_FRAMES) {
458 netdev_info(priv->netdev, "%s: maximum coalesced frames supported is %lu\n",
459 __func__, MLX5E_MAX_COAL_FRAMES);
463 mutex_lock(&priv->state_lock);
464 new_channels.params = priv->channels.params;
466 new_channels.params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
467 new_channels.params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
468 new_channels.params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
469 new_channels.params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
470 new_channels.params.rx_dim_enabled = !!coal->use_adaptive_rx_coalesce;
472 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
473 priv->channels.params = new_channels.params;
478 reset = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_dim_enabled;
480 mlx5e_set_priv_channels_coalesce(priv, coal);
481 priv->channels.params = new_channels.params;
485 /* open fresh channels with new coal parameters */
486 err = mlx5e_open_channels(priv, &new_channels);
490 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
493 mutex_unlock(&priv->state_lock);
497 static int mlx5e_set_coalesce(struct net_device *netdev,
498 struct ethtool_coalesce *coal)
500 struct mlx5e_priv *priv = netdev_priv(netdev);
502 return mlx5e_ethtool_set_coalesce(priv, coal);
505 static void ptys2ethtool_supported_link(unsigned long *supported_modes,
508 unsigned long proto_cap = eth_proto_cap;
511 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
512 bitmap_or(supported_modes, supported_modes,
513 ptys2ethtool_table[proto].supported,
514 __ETHTOOL_LINK_MODE_MASK_NBITS);
517 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
520 unsigned long proto_cap = eth_proto_cap;
523 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
524 bitmap_or(advertising_modes, advertising_modes,
525 ptys2ethtool_table[proto].advertised,
526 __ETHTOOL_LINK_MODE_MASK_NBITS);
529 static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
533 if (!connector_type || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
534 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
535 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
536 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
537 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
538 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
539 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
540 ethtool_link_ksettings_add_link_mode(link_ksettings,
543 ethtool_link_ksettings_add_link_mode(link_ksettings,
548 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
549 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
550 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
551 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
552 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
553 ethtool_link_ksettings_add_link_mode(link_ksettings,
556 ethtool_link_ksettings_add_link_mode(link_ksettings,
563 switch (connector_type) {
565 ethtool_link_ksettings_add_link_mode(link_ksettings,
567 ethtool_link_ksettings_add_link_mode(link_ksettings,
571 ethtool_link_ksettings_add_link_mode(link_ksettings,
573 ethtool_link_ksettings_add_link_mode(link_ksettings,
577 ethtool_link_ksettings_add_link_mode(link_ksettings,
579 ethtool_link_ksettings_add_link_mode(link_ksettings,
583 ethtool_link_ksettings_add_link_mode(link_ksettings,
585 ethtool_link_ksettings_add_link_mode(link_ksettings,
588 case MLX5E_PORT_FIBRE:
589 ethtool_link_ksettings_add_link_mode(link_ksettings,
591 ethtool_link_ksettings_add_link_mode(link_ksettings,
595 ethtool_link_ksettings_add_link_mode(link_ksettings,
596 supported, Backplane);
597 ethtool_link_ksettings_add_link_mode(link_ksettings,
598 advertising, Backplane);
600 case MLX5E_PORT_NONE:
601 case MLX5E_PORT_OTHER:
607 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
614 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
618 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
619 if (proto_cap & MLX5E_PROT_MASK(i))
620 max_speed = max(max_speed, ptys2ethtool_table[i].speed);
626 static void get_speed_duplex(struct net_device *netdev,
628 struct ethtool_link_ksettings *link_ksettings)
631 u32 speed = SPEED_UNKNOWN;
632 u8 duplex = DUPLEX_UNKNOWN;
634 if (!netif_carrier_ok(netdev))
637 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
638 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
639 speed = ptys2ethtool_table[i].speed;
640 duplex = DUPLEX_FULL;
645 link_ksettings->base.speed = speed;
646 link_ksettings->base.duplex = duplex;
649 static void get_supported(u32 eth_proto_cap,
650 struct ethtool_link_ksettings *link_ksettings)
652 unsigned long *supported = link_ksettings->link_modes.supported;
654 ptys2ethtool_supported_link(supported, eth_proto_cap);
655 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
658 static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
660 struct ethtool_link_ksettings *link_ksettings)
662 unsigned long *advertising = link_ksettings->link_modes.advertising;
664 ptys2ethtool_adver_link(advertising, eth_proto_cap);
666 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
667 if (tx_pause ^ rx_pause)
668 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
671 static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
672 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
673 [MLX5E_PORT_NONE] = PORT_NONE,
674 [MLX5E_PORT_TP] = PORT_TP,
675 [MLX5E_PORT_AUI] = PORT_AUI,
676 [MLX5E_PORT_BNC] = PORT_BNC,
677 [MLX5E_PORT_MII] = PORT_MII,
678 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
679 [MLX5E_PORT_DA] = PORT_DA,
680 [MLX5E_PORT_OTHER] = PORT_OTHER,
683 static u8 get_connector_port(u32 eth_proto, u8 connector_type)
685 if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
686 return ptys2connector_type[connector_type];
689 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
690 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
691 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
692 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
697 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
698 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
699 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
704 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
705 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
706 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
707 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
714 static void get_lp_advertising(u32 eth_proto_lp,
715 struct ethtool_link_ksettings *link_ksettings)
717 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
719 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
722 static int mlx5e_get_link_ksettings(struct net_device *netdev,
723 struct ethtool_link_ksettings *link_ksettings)
725 struct mlx5e_priv *priv = netdev_priv(netdev);
726 struct mlx5_core_dev *mdev = priv->mdev;
727 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
739 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
741 netdev_err(netdev, "%s: query port ptys failed: %d\n",
746 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
747 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
748 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
749 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
750 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
751 an_status = MLX5_GET(ptys_reg, out, an_status);
752 connector_type = MLX5_GET(ptys_reg, out, connector_type);
754 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
756 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
757 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
759 get_supported(eth_proto_cap, link_ksettings);
760 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings);
761 get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
763 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
765 link_ksettings->base.port = get_connector_port(eth_proto_oper,
767 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
769 get_lp_advertising(eth_proto_lp, link_ksettings);
771 if (an_status == MLX5_AN_COMPLETE)
772 ethtool_link_ksettings_add_link_mode(link_ksettings,
773 lp_advertising, Autoneg);
775 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
777 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
779 if (!an_disable_admin)
780 ethtool_link_ksettings_add_link_mode(link_ksettings,
781 advertising, Autoneg);
787 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
789 u32 i, ptys_modes = 0;
791 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
792 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
794 __ETHTOOL_LINK_MODE_MASK_NBITS))
795 ptys_modes |= MLX5E_PROT_MASK(i);
801 static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
803 u32 i, speed_links = 0;
805 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
806 if (ptys2ethtool_table[i].speed == speed)
807 speed_links |= MLX5E_PROT_MASK(i);
813 static int mlx5e_set_link_ksettings(struct net_device *netdev,
814 const struct ethtool_link_ksettings *link_ksettings)
816 struct mlx5e_priv *priv = netdev_priv(netdev);
817 struct mlx5_core_dev *mdev = priv->mdev;
818 u32 eth_proto_cap, eth_proto_admin;
819 bool an_changes = false;
828 speed = link_ksettings->base.speed;
830 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
831 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
832 mlx5e_ethtool2ptys_speed_link(speed);
834 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
836 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
841 link_modes = link_modes & eth_proto_cap;
843 netdev_err(netdev, "%s: Not supported link mode(s) requested",
849 err = mlx5_query_port_proto_admin(mdev, ð_proto_admin, MLX5_PTYS_EN);
851 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
856 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
857 &an_disable_cap, &an_disable_admin);
859 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
860 an_changes = ((!an_disable && an_disable_admin) ||
861 (an_disable && !an_disable_admin));
863 if (!an_changes && link_modes == eth_proto_admin)
866 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
867 mlx5_toggle_port_link(mdev);
873 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
875 struct mlx5e_priv *priv = netdev_priv(netdev);
877 return sizeof(priv->channels.params.toeplitz_hash_key);
880 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
882 return MLX5E_INDIR_RQT_SIZE;
885 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
888 struct mlx5e_priv *priv = netdev_priv(netdev);
891 memcpy(indir, priv->channels.params.indirection_rqt,
892 sizeof(priv->channels.params.indirection_rqt));
895 memcpy(key, priv->channels.params.toeplitz_hash_key,
896 sizeof(priv->channels.params.toeplitz_hash_key));
899 *hfunc = priv->channels.params.rss_hfunc;
904 static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
906 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
907 struct mlx5_core_dev *mdev = priv->mdev;
908 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
911 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
913 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
914 memset(tirc, 0, ctxlen);
915 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
916 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
919 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
922 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
923 memset(tirc, 0, ctxlen);
924 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
925 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in, inlen);
929 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
930 const u8 *key, const u8 hfunc)
932 struct mlx5e_priv *priv = netdev_priv(dev);
933 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
934 bool hash_changed = false;
937 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
938 (hfunc != ETH_RSS_HASH_XOR) &&
939 (hfunc != ETH_RSS_HASH_TOP))
942 in = kvzalloc(inlen, GFP_KERNEL);
946 mutex_lock(&priv->state_lock);
948 if (hfunc != ETH_RSS_HASH_NO_CHANGE &&
949 hfunc != priv->channels.params.rss_hfunc) {
950 priv->channels.params.rss_hfunc = hfunc;
955 memcpy(priv->channels.params.indirection_rqt, indir,
956 sizeof(priv->channels.params.indirection_rqt));
958 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
959 u32 rqtn = priv->indir_rqt.rqtn;
960 struct mlx5e_redirect_rqt_param rrp = {
964 .hfunc = priv->channels.params.rss_hfunc,
965 .channels = &priv->channels,
970 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
975 memcpy(priv->channels.params.toeplitz_hash_key, key,
976 sizeof(priv->channels.params.toeplitz_hash_key));
977 hash_changed = hash_changed ||
978 priv->channels.params.rss_hfunc == ETH_RSS_HASH_TOP;
982 mlx5e_modify_tirs_hash(priv, in, inlen);
984 mutex_unlock(&priv->state_lock);
991 static int mlx5e_get_rxnfc(struct net_device *netdev,
992 struct ethtool_rxnfc *info, u32 *rule_locs)
994 struct mlx5e_priv *priv = netdev_priv(netdev);
998 case ETHTOOL_GRXRINGS:
999 info->data = priv->channels.params.num_channels;
1001 case ETHTOOL_GRXCLSRLCNT:
1002 info->rule_cnt = priv->fs.ethtool.tot_num_rules;
1004 case ETHTOOL_GRXCLSRULE:
1005 err = mlx5e_ethtool_get_flow(priv, info, info->fs.location);
1007 case ETHTOOL_GRXCLSRLALL:
1008 err = mlx5e_ethtool_get_all_flows(priv, info, rule_locs);
1018 #define MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC 100
1019 #define MLX5E_PFC_PREVEN_TOUT_MAX_MSEC 8000
1020 #define MLX5E_PFC_PREVEN_MINOR_PRECENT 85
1021 #define MLX5E_PFC_PREVEN_TOUT_MIN_MSEC 80
1022 #define MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout) \
1023 max_t(u16, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC, \
1024 (critical_tout * MLX5E_PFC_PREVEN_MINOR_PRECENT) / 100)
1026 static int mlx5e_get_pfc_prevention_tout(struct net_device *netdev,
1027 u16 *pfc_prevention_tout)
1029 struct mlx5e_priv *priv = netdev_priv(netdev);
1030 struct mlx5_core_dev *mdev = priv->mdev;
1032 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1033 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1036 return mlx5_query_port_stall_watermark(mdev, pfc_prevention_tout, NULL);
1039 static int mlx5e_set_pfc_prevention_tout(struct net_device *netdev,
1042 struct mlx5e_priv *priv = netdev_priv(netdev);
1043 struct mlx5_core_dev *mdev = priv->mdev;
1047 if (!MLX5_CAP_PCAM_FEATURE((priv)->mdev, pfcc_mask) ||
1048 !MLX5_CAP_DEBUG((priv)->mdev, stall_detect))
1051 critical_tout = (pfc_preven == PFC_STORM_PREVENTION_AUTO) ?
1052 MLX5E_PFC_PREVEN_AUTO_TOUT_MSEC :
1055 if (critical_tout != PFC_STORM_PREVENTION_DISABLE &&
1056 (critical_tout > MLX5E_PFC_PREVEN_TOUT_MAX_MSEC ||
1057 critical_tout < MLX5E_PFC_PREVEN_TOUT_MIN_MSEC)) {
1058 netdev_info(netdev, "%s: pfc prevention tout not in range (%d-%d)\n",
1059 __func__, MLX5E_PFC_PREVEN_TOUT_MIN_MSEC,
1060 MLX5E_PFC_PREVEN_TOUT_MAX_MSEC);
1064 minor = MLX5E_DEVICE_STALL_MINOR_WATERMARK(critical_tout);
1065 return mlx5_set_port_stall_watermark(mdev, critical_tout,
1069 static int mlx5e_get_tunable(struct net_device *dev,
1070 const struct ethtool_tunable *tuna,
1076 case ETHTOOL_PFC_PREVENTION_TOUT:
1077 err = mlx5e_get_pfc_prevention_tout(dev, data);
1087 static int mlx5e_set_tunable(struct net_device *dev,
1088 const struct ethtool_tunable *tuna,
1091 struct mlx5e_priv *priv = netdev_priv(dev);
1094 mutex_lock(&priv->state_lock);
1097 case ETHTOOL_PFC_PREVENTION_TOUT:
1098 err = mlx5e_set_pfc_prevention_tout(dev, *(u16 *)data);
1105 mutex_unlock(&priv->state_lock);
1109 static void mlx5e_get_pauseparam(struct net_device *netdev,
1110 struct ethtool_pauseparam *pauseparam)
1112 struct mlx5e_priv *priv = netdev_priv(netdev);
1113 struct mlx5_core_dev *mdev = priv->mdev;
1116 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1117 &pauseparam->tx_pause);
1119 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1124 static int mlx5e_set_pauseparam(struct net_device *netdev,
1125 struct ethtool_pauseparam *pauseparam)
1127 struct mlx5e_priv *priv = netdev_priv(netdev);
1128 struct mlx5_core_dev *mdev = priv->mdev;
1131 if (pauseparam->autoneg)
1134 err = mlx5_set_port_pause(mdev,
1135 pauseparam->rx_pause ? 1 : 0,
1136 pauseparam->tx_pause ? 1 : 0);
1138 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1145 int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1146 struct ethtool_ts_info *info)
1148 struct mlx5_core_dev *mdev = priv->mdev;
1151 ret = ethtool_op_get_ts_info(priv->netdev, info);
1155 info->phc_index = mdev->clock.ptp ?
1156 ptp_clock_index(mdev->clock.ptp) : -1;
1158 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1161 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1162 SOF_TIMESTAMPING_RX_HARDWARE |
1163 SOF_TIMESTAMPING_RAW_HARDWARE;
1165 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1166 BIT(HWTSTAMP_TX_ON);
1168 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1169 BIT(HWTSTAMP_FILTER_ALL);
1174 static int mlx5e_get_ts_info(struct net_device *dev,
1175 struct ethtool_ts_info *info)
1177 struct mlx5e_priv *priv = netdev_priv(dev);
1179 return mlx5e_ethtool_get_ts_info(priv, info);
1182 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1186 if (MLX5_CAP_GEN(mdev, wol_g))
1189 if (MLX5_CAP_GEN(mdev, wol_s))
1190 ret |= WAKE_MAGICSECURE;
1192 if (MLX5_CAP_GEN(mdev, wol_a))
1195 if (MLX5_CAP_GEN(mdev, wol_b))
1198 if (MLX5_CAP_GEN(mdev, wol_m))
1201 if (MLX5_CAP_GEN(mdev, wol_u))
1204 if (MLX5_CAP_GEN(mdev, wol_p))
1210 static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1214 if (mode & MLX5_WOL_MAGIC)
1217 if (mode & MLX5_WOL_SECURED_MAGIC)
1218 ret |= WAKE_MAGICSECURE;
1220 if (mode & MLX5_WOL_ARP)
1223 if (mode & MLX5_WOL_BROADCAST)
1226 if (mode & MLX5_WOL_MULTICAST)
1229 if (mode & MLX5_WOL_UNICAST)
1232 if (mode & MLX5_WOL_PHY_ACTIVITY)
1238 static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1242 if (mode & WAKE_MAGIC)
1243 ret |= MLX5_WOL_MAGIC;
1245 if (mode & WAKE_MAGICSECURE)
1246 ret |= MLX5_WOL_SECURED_MAGIC;
1248 if (mode & WAKE_ARP)
1249 ret |= MLX5_WOL_ARP;
1251 if (mode & WAKE_BCAST)
1252 ret |= MLX5_WOL_BROADCAST;
1254 if (mode & WAKE_MCAST)
1255 ret |= MLX5_WOL_MULTICAST;
1257 if (mode & WAKE_UCAST)
1258 ret |= MLX5_WOL_UNICAST;
1260 if (mode & WAKE_PHY)
1261 ret |= MLX5_WOL_PHY_ACTIVITY;
1266 static void mlx5e_get_wol(struct net_device *netdev,
1267 struct ethtool_wolinfo *wol)
1269 struct mlx5e_priv *priv = netdev_priv(netdev);
1270 struct mlx5_core_dev *mdev = priv->mdev;
1274 memset(wol, 0, sizeof(*wol));
1276 wol->supported = mlx5e_get_wol_supported(mdev);
1277 if (!wol->supported)
1280 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1284 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1287 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1289 struct mlx5e_priv *priv = netdev_priv(netdev);
1290 struct mlx5_core_dev *mdev = priv->mdev;
1291 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1297 if (wol->wolopts & ~wol_supported)
1300 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1302 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1305 static u32 mlx5e_get_msglevel(struct net_device *dev)
1307 return ((struct mlx5e_priv *)netdev_priv(dev))->msglevel;
1310 static void mlx5e_set_msglevel(struct net_device *dev, u32 val)
1312 ((struct mlx5e_priv *)netdev_priv(dev))->msglevel = val;
1315 static int mlx5e_set_phys_id(struct net_device *dev,
1316 enum ethtool_phys_id_state state)
1318 struct mlx5e_priv *priv = netdev_priv(dev);
1319 struct mlx5_core_dev *mdev = priv->mdev;
1320 u16 beacon_duration;
1322 if (!MLX5_CAP_GEN(mdev, beacon_led))
1326 case ETHTOOL_ID_ACTIVE:
1327 beacon_duration = MLX5_BEACON_DURATION_INF;
1329 case ETHTOOL_ID_INACTIVE:
1330 beacon_duration = MLX5_BEACON_DURATION_OFF;
1336 return mlx5_set_port_beacon(mdev, beacon_duration);
1339 static int mlx5e_get_module_info(struct net_device *netdev,
1340 struct ethtool_modinfo *modinfo)
1342 struct mlx5e_priv *priv = netdev_priv(netdev);
1343 struct mlx5_core_dev *dev = priv->mdev;
1347 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1351 /* data[0] = identifier byte */
1353 case MLX5_MODULE_ID_QSFP:
1354 modinfo->type = ETH_MODULE_SFF_8436;
1355 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1357 case MLX5_MODULE_ID_QSFP_PLUS:
1358 case MLX5_MODULE_ID_QSFP28:
1359 /* data[1] = revision id */
1360 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1361 modinfo->type = ETH_MODULE_SFF_8636;
1362 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1364 modinfo->type = ETH_MODULE_SFF_8436;
1365 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1368 case MLX5_MODULE_ID_SFP:
1369 modinfo->type = ETH_MODULE_SFF_8472;
1370 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1373 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1381 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1382 struct ethtool_eeprom *ee,
1385 struct mlx5e_priv *priv = netdev_priv(netdev);
1386 struct mlx5_core_dev *mdev = priv->mdev;
1387 int offset = ee->offset;
1394 memset(data, 0, ee->len);
1396 while (i < ee->len) {
1397 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1404 if (size_read < 0) {
1405 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1406 __func__, size_read);
1411 offset += size_read;
1417 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1419 static int set_pflag_cqe_based_moder(struct net_device *netdev, bool enable,
1422 struct mlx5e_priv *priv = netdev_priv(netdev);
1423 struct mlx5_core_dev *mdev = priv->mdev;
1424 struct mlx5e_channels new_channels = {};
1426 u8 cq_period_mode, current_cq_period_mode;
1429 cq_period_mode = enable ?
1430 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1431 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1432 current_cq_period_mode = is_rx_cq ?
1433 priv->channels.params.rx_cq_moderation.cq_period_mode :
1434 priv->channels.params.tx_cq_moderation.cq_period_mode;
1435 mode_changed = cq_period_mode != current_cq_period_mode;
1437 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1438 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1444 new_channels.params = priv->channels.params;
1446 mlx5e_set_rx_cq_mode_params(&new_channels.params, cq_period_mode);
1448 mlx5e_set_tx_cq_mode_params(&new_channels.params, cq_period_mode);
1450 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1451 priv->channels.params = new_channels.params;
1455 err = mlx5e_open_channels(priv, &new_channels);
1459 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1463 static int set_pflag_tx_cqe_based_moder(struct net_device *netdev, bool enable)
1465 return set_pflag_cqe_based_moder(netdev, enable, false);
1468 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1470 return set_pflag_cqe_based_moder(netdev, enable, true);
1473 int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1475 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1476 struct mlx5e_channels new_channels = {};
1479 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1480 return new_val ? -EOPNOTSUPP : 0;
1482 if (curr_val == new_val)
1485 new_channels.params = priv->channels.params;
1486 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1488 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1489 priv->channels.params = new_channels.params;
1493 err = mlx5e_open_channels(priv, &new_channels);
1497 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1498 mlx5e_dbg(DRV, priv, "MLX5E: RxCqeCmprss was turned %s\n",
1499 MLX5E_GET_PFLAG(&priv->channels.params,
1500 MLX5E_PFLAG_RX_CQE_COMPRESS) ? "ON" : "OFF");
1505 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1508 struct mlx5e_priv *priv = netdev_priv(netdev);
1509 struct mlx5_core_dev *mdev = priv->mdev;
1511 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1514 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
1515 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1519 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
1520 priv->channels.params.rx_cqe_compress_def = enable;
1525 static int set_pflag_rx_striding_rq(struct net_device *netdev, bool enable)
1527 struct mlx5e_priv *priv = netdev_priv(netdev);
1528 struct mlx5_core_dev *mdev = priv->mdev;
1529 struct mlx5e_channels new_channels = {};
1533 if (!mlx5e_check_fragmented_striding_rq_cap(mdev))
1535 if (!mlx5e_striding_rq_possible(mdev, &priv->channels.params))
1539 new_channels.params = priv->channels.params;
1541 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_STRIDING_RQ, enable);
1542 mlx5e_set_rq_type(mdev, &new_channels.params);
1544 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1545 priv->channels.params = new_channels.params;
1549 err = mlx5e_open_channels(priv, &new_channels);
1553 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
1557 static int mlx5e_handle_pflag(struct net_device *netdev,
1559 enum mlx5e_priv_flag flag,
1560 mlx5e_pflag_handler pflag_handler)
1562 struct mlx5e_priv *priv = netdev_priv(netdev);
1563 bool enable = !!(wanted_flags & flag);
1564 u32 changes = wanted_flags ^ priv->channels.params.pflags;
1567 if (!(changes & flag))
1570 err = pflag_handler(netdev, enable);
1572 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1573 enable ? "Enable" : "Disable", flag, err);
1577 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
1581 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1583 struct mlx5e_priv *priv = netdev_priv(netdev);
1586 mutex_lock(&priv->state_lock);
1587 err = mlx5e_handle_pflag(netdev, pflags,
1588 MLX5E_PFLAG_RX_CQE_BASED_MODER,
1589 set_pflag_rx_cqe_based_moder);
1593 err = mlx5e_handle_pflag(netdev, pflags,
1594 MLX5E_PFLAG_TX_CQE_BASED_MODER,
1595 set_pflag_tx_cqe_based_moder);
1599 err = mlx5e_handle_pflag(netdev, pflags,
1600 MLX5E_PFLAG_RX_CQE_COMPRESS,
1601 set_pflag_rx_cqe_compress);
1605 err = mlx5e_handle_pflag(netdev, pflags,
1606 MLX5E_PFLAG_RX_STRIDING_RQ,
1607 set_pflag_rx_striding_rq);
1610 mutex_unlock(&priv->state_lock);
1614 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1616 struct mlx5e_priv *priv = netdev_priv(netdev);
1618 return priv->channels.params.pflags;
1621 static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1624 struct mlx5e_priv *priv = netdev_priv(dev);
1627 case ETHTOOL_SRXCLSRLINS:
1628 err = mlx5e_ethtool_flow_replace(priv, &cmd->fs);
1630 case ETHTOOL_SRXCLSRLDEL:
1631 err = mlx5e_ethtool_flow_remove(priv, cmd->fs.location);
1641 int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1642 struct ethtool_flash *flash)
1644 struct mlx5_core_dev *mdev = priv->mdev;
1645 struct net_device *dev = priv->netdev;
1646 const struct firmware *fw;
1649 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1652 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1659 err = mlx5_firmware_flash(mdev, fw);
1660 release_firmware(fw);
1667 static int mlx5e_flash_device(struct net_device *dev,
1668 struct ethtool_flash *flash)
1670 struct mlx5e_priv *priv = netdev_priv(dev);
1672 return mlx5e_ethtool_flash_device(priv, flash);
1675 const struct ethtool_ops mlx5e_ethtool_ops = {
1676 .get_drvinfo = mlx5e_get_drvinfo,
1677 .get_link = ethtool_op_get_link,
1678 .get_strings = mlx5e_get_strings,
1679 .get_sset_count = mlx5e_get_sset_count,
1680 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1681 .get_ringparam = mlx5e_get_ringparam,
1682 .set_ringparam = mlx5e_set_ringparam,
1683 .get_channels = mlx5e_get_channels,
1684 .set_channels = mlx5e_set_channels,
1685 .get_coalesce = mlx5e_get_coalesce,
1686 .set_coalesce = mlx5e_set_coalesce,
1687 .get_link_ksettings = mlx5e_get_link_ksettings,
1688 .set_link_ksettings = mlx5e_set_link_ksettings,
1689 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1690 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1691 .get_rxfh = mlx5e_get_rxfh,
1692 .set_rxfh = mlx5e_set_rxfh,
1693 .get_rxnfc = mlx5e_get_rxnfc,
1694 .set_rxnfc = mlx5e_set_rxnfc,
1695 .flash_device = mlx5e_flash_device,
1696 .get_tunable = mlx5e_get_tunable,
1697 .set_tunable = mlx5e_set_tunable,
1698 .get_pauseparam = mlx5e_get_pauseparam,
1699 .set_pauseparam = mlx5e_set_pauseparam,
1700 .get_ts_info = mlx5e_get_ts_info,
1701 .set_phys_id = mlx5e_set_phys_id,
1702 .get_wol = mlx5e_get_wol,
1703 .set_wol = mlx5e_set_wol,
1704 .get_module_info = mlx5e_get_module_info,
1705 .get_module_eeprom = mlx5e_get_module_eeprom,
1706 .get_priv_flags = mlx5e_get_priv_flags,
1707 .set_priv_flags = mlx5e_set_priv_flags,
1708 .self_test = mlx5e_self_test,
1709 .get_msglevel = mlx5e_get_msglevel,
1710 .set_msglevel = mlx5e_set_msglevel,