2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 static void mlx5e_get_drvinfo(struct net_device *dev,
36 struct ethtool_drvinfo *drvinfo)
38 struct mlx5e_priv *priv = netdev_priv(dev);
39 struct mlx5_core_dev *mdev = priv->mdev;
41 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
42 strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")",
43 sizeof(drvinfo->version));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev));
47 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
48 sizeof(drvinfo->bus_info));
55 } ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER] = {
56 [MLX5E_1000BASE_CX_SGMII] = {
57 .supported = SUPPORTED_1000baseKX_Full,
58 .advertised = ADVERTISED_1000baseKX_Full,
61 [MLX5E_1000BASE_KX] = {
62 .supported = SUPPORTED_1000baseKX_Full,
63 .advertised = ADVERTISED_1000baseKX_Full,
66 [MLX5E_10GBASE_CX4] = {
67 .supported = SUPPORTED_10000baseKX4_Full,
68 .advertised = ADVERTISED_10000baseKX4_Full,
71 [MLX5E_10GBASE_KX4] = {
72 .supported = SUPPORTED_10000baseKX4_Full,
73 .advertised = ADVERTISED_10000baseKX4_Full,
76 [MLX5E_10GBASE_KR] = {
77 .supported = SUPPORTED_10000baseKR_Full,
78 .advertised = ADVERTISED_10000baseKR_Full,
81 [MLX5E_20GBASE_KR2] = {
82 .supported = SUPPORTED_20000baseKR2_Full,
83 .advertised = ADVERTISED_20000baseKR2_Full,
86 [MLX5E_40GBASE_CR4] = {
87 .supported = SUPPORTED_40000baseCR4_Full,
88 .advertised = ADVERTISED_40000baseCR4_Full,
91 [MLX5E_40GBASE_KR4] = {
92 .supported = SUPPORTED_40000baseKR4_Full,
93 .advertised = ADVERTISED_40000baseKR4_Full,
96 [MLX5E_56GBASE_R4] = {
97 .supported = SUPPORTED_56000baseKR4_Full,
98 .advertised = ADVERTISED_56000baseKR4_Full,
101 [MLX5E_10GBASE_CR] = {
102 .supported = SUPPORTED_10000baseKR_Full,
103 .advertised = ADVERTISED_10000baseKR_Full,
106 [MLX5E_10GBASE_SR] = {
107 .supported = SUPPORTED_10000baseKR_Full,
108 .advertised = ADVERTISED_10000baseKR_Full,
111 [MLX5E_10GBASE_ER] = {
112 .supported = SUPPORTED_10000baseKR_Full,
113 .advertised = ADVERTISED_10000baseKR_Full,
116 [MLX5E_40GBASE_SR4] = {
117 .supported = SUPPORTED_40000baseSR4_Full,
118 .advertised = ADVERTISED_40000baseSR4_Full,
121 [MLX5E_40GBASE_LR4] = {
122 .supported = SUPPORTED_40000baseLR4_Full,
123 .advertised = ADVERTISED_40000baseLR4_Full,
126 [MLX5E_100GBASE_CR4] = {
129 [MLX5E_100GBASE_SR4] = {
132 [MLX5E_100GBASE_KR4] = {
135 [MLX5E_100GBASE_LR4] = {
138 [MLX5E_100BASE_TX] = {
141 [MLX5E_1000BASE_T] = {
142 .supported = SUPPORTED_1000baseT_Full,
143 .advertised = ADVERTISED_1000baseT_Full,
146 [MLX5E_10GBASE_T] = {
147 .supported = SUPPORTED_10000baseT_Full,
148 .advertised = ADVERTISED_10000baseT_Full,
151 [MLX5E_25GBASE_CR] = {
154 [MLX5E_25GBASE_KR] = {
157 [MLX5E_25GBASE_SR] = {
160 [MLX5E_50GBASE_CR2] = {
163 [MLX5E_50GBASE_KR2] = {
168 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
170 struct mlx5_core_dev *mdev = priv->mdev;
175 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
177 return err ? 0 : pfc_en_tx | pfc_en_rx;
180 #define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
181 #define MLX5E_NUM_RQ_STATS(priv) \
182 (NUM_RQ_STATS * priv->params.num_channels * \
183 test_bit(MLX5E_STATE_OPENED, &priv->state))
184 #define MLX5E_NUM_SQ_STATS(priv) \
185 (NUM_SQ_STATS * priv->params.num_channels * priv->params.num_tc * \
186 test_bit(MLX5E_STATE_OPENED, &priv->state))
187 #define MLX5E_NUM_PFC_COUNTERS(priv) \
188 (hweight8(mlx5e_query_pfc_combined(priv)) * \
189 NUM_PPORT_PER_PRIO_PFC_COUNTERS)
191 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
193 struct mlx5e_priv *priv = netdev_priv(dev);
197 return NUM_SW_COUNTERS +
198 MLX5E_NUM_Q_CNTRS(priv) +
199 NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS +
200 MLX5E_NUM_RQ_STATS(priv) +
201 MLX5E_NUM_SQ_STATS(priv) +
202 MLX5E_NUM_PFC_COUNTERS(priv);
209 static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
211 int i, j, tc, prio, idx = 0;
212 unsigned long pfc_combined;
215 for (i = 0; i < NUM_SW_COUNTERS; i++)
216 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].name);
219 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
220 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].name);
223 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
224 strcpy(data + (idx++) * ETH_GSTRING_LEN,
225 vport_stats_desc[i].name);
228 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
229 strcpy(data + (idx++) * ETH_GSTRING_LEN,
230 pport_802_3_stats_desc[i].name);
232 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
233 strcpy(data + (idx++) * ETH_GSTRING_LEN,
234 pport_2863_stats_desc[i].name);
236 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
237 strcpy(data + (idx++) * ETH_GSTRING_LEN,
238 pport_2819_stats_desc[i].name);
240 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
241 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
242 sprintf(data + (idx++) * ETH_GSTRING_LEN, "prio%d_%s",
244 pport_per_prio_traffic_stats_desc[i].name);
247 pfc_combined = mlx5e_query_pfc_combined(priv);
248 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
249 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
250 sprintf(data + (idx++) * ETH_GSTRING_LEN, "prio%d_%s",
251 prio, pport_per_prio_pfc_stats_desc[i].name);
255 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
258 /* per channel counters */
259 for (i = 0; i < priv->params.num_channels; i++)
260 for (j = 0; j < NUM_RQ_STATS; j++)
261 sprintf(data + (idx++) * ETH_GSTRING_LEN, "rx%d_%s", i,
262 rq_stats_desc[j].name);
264 for (tc = 0; tc < priv->params.num_tc; tc++)
265 for (i = 0; i < priv->params.num_channels; i++)
266 for (j = 0; j < NUM_SQ_STATS; j++)
267 sprintf(data + (idx++) * ETH_GSTRING_LEN,
269 priv->channeltc_to_txq_map[i][tc],
270 sq_stats_desc[j].name);
273 static void mlx5e_get_strings(struct net_device *dev,
274 uint32_t stringset, uint8_t *data)
276 struct mlx5e_priv *priv = netdev_priv(dev);
279 case ETH_SS_PRIV_FLAGS:
286 mlx5e_fill_stats_strings(priv, data);
291 static void mlx5e_get_ethtool_stats(struct net_device *dev,
292 struct ethtool_stats *stats, u64 *data)
294 struct mlx5e_priv *priv = netdev_priv(dev);
295 int i, j, tc, prio, idx = 0;
296 unsigned long pfc_combined;
301 mutex_lock(&priv->state_lock);
302 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
303 mlx5e_update_stats(priv);
304 mutex_unlock(&priv->state_lock);
306 for (i = 0; i < NUM_SW_COUNTERS; i++)
307 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
310 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
311 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
314 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
315 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
316 vport_stats_desc, i);
318 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
319 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
320 pport_802_3_stats_desc, i);
322 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
323 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
324 pport_2863_stats_desc, i);
326 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
327 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
328 pport_2819_stats_desc, i);
330 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
331 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
332 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
333 pport_per_prio_traffic_stats_desc, i);
336 pfc_combined = mlx5e_query_pfc_combined(priv);
337 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
338 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
339 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
340 pport_per_prio_pfc_stats_desc, i);
344 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
347 /* per channel counters */
348 for (i = 0; i < priv->params.num_channels; i++)
349 for (j = 0; j < NUM_RQ_STATS; j++)
351 MLX5E_READ_CTR64_CPU(&priv->channel[i]->rq.stats,
354 for (tc = 0; tc < priv->params.num_tc; tc++)
355 for (i = 0; i < priv->params.num_channels; i++)
356 for (j = 0; j < NUM_SQ_STATS; j++)
357 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->channel[i]->sq[tc].stats,
361 static void mlx5e_get_ringparam(struct net_device *dev,
362 struct ethtool_ringparam *param)
364 struct mlx5e_priv *priv = netdev_priv(dev);
365 int rq_wq_type = priv->params.rq_wq_type;
367 param->rx_max_pending = 1 << mlx5_max_log_rq_size(rq_wq_type);
368 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
369 param->rx_pending = 1 << priv->params.log_rq_size;
370 param->tx_pending = 1 << priv->params.log_sq_size;
373 static int mlx5e_set_ringparam(struct net_device *dev,
374 struct ethtool_ringparam *param)
376 struct mlx5e_priv *priv = netdev_priv(dev);
378 int rq_wq_type = priv->params.rq_wq_type;
384 if (param->rx_jumbo_pending) {
385 netdev_info(dev, "%s: rx_jumbo_pending not supported\n",
389 if (param->rx_mini_pending) {
390 netdev_info(dev, "%s: rx_mini_pending not supported\n",
394 if (param->rx_pending < (1 << mlx5_min_log_rq_size(rq_wq_type))) {
395 netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n",
396 __func__, param->rx_pending,
397 1 << mlx5_min_log_rq_size(rq_wq_type));
400 if (param->rx_pending > (1 << mlx5_max_log_rq_size(rq_wq_type))) {
401 netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n",
402 __func__, param->rx_pending,
403 1 << mlx5_max_log_rq_size(rq_wq_type));
406 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
407 netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n",
408 __func__, param->tx_pending,
409 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
412 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
413 netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n",
414 __func__, param->tx_pending,
415 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
419 log_rq_size = order_base_2(param->rx_pending);
420 log_sq_size = order_base_2(param->tx_pending);
421 min_rx_wqes = mlx5_min_rx_wqes(rq_wq_type, param->rx_pending);
423 if (log_rq_size == priv->params.log_rq_size &&
424 log_sq_size == priv->params.log_sq_size &&
425 min_rx_wqes == priv->params.min_rx_wqes)
428 mutex_lock(&priv->state_lock);
430 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
432 mlx5e_close_locked(dev);
434 priv->params.log_rq_size = log_rq_size;
435 priv->params.log_sq_size = log_sq_size;
436 priv->params.min_rx_wqes = min_rx_wqes;
439 err = mlx5e_open_locked(dev);
441 mutex_unlock(&priv->state_lock);
446 static void mlx5e_get_channels(struct net_device *dev,
447 struct ethtool_channels *ch)
449 struct mlx5e_priv *priv = netdev_priv(dev);
451 ch->max_combined = mlx5e_get_max_num_channels(priv->mdev);
452 ch->combined_count = priv->params.num_channels;
455 static int mlx5e_set_channels(struct net_device *dev,
456 struct ethtool_channels *ch)
458 struct mlx5e_priv *priv = netdev_priv(dev);
459 int ncv = mlx5e_get_max_num_channels(priv->mdev);
460 unsigned int count = ch->combined_count;
466 netdev_info(dev, "%s: combined_count=0 not supported\n",
470 if (ch->rx_count || ch->tx_count) {
471 netdev_info(dev, "%s: separate rx/tx count not supported\n",
476 netdev_info(dev, "%s: count (%d) > max (%d)\n",
477 __func__, count, ncv);
481 if (priv->params.num_channels == count)
484 mutex_lock(&priv->state_lock);
486 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
488 mlx5e_close_locked(dev);
490 arfs_enabled = dev->features & NETIF_F_NTUPLE;
492 mlx5e_arfs_disable(priv);
494 priv->params.num_channels = count;
495 mlx5e_build_default_indir_rqt(priv->mdev, priv->params.indirection_rqt,
496 MLX5E_INDIR_RQT_SIZE, count);
499 err = mlx5e_open_locked(dev);
504 err = mlx5e_arfs_enable(priv);
506 netdev_err(dev, "%s: mlx5e_arfs_enable failed: %d\n",
511 mutex_unlock(&priv->state_lock);
516 static int mlx5e_get_coalesce(struct net_device *netdev,
517 struct ethtool_coalesce *coal)
519 struct mlx5e_priv *priv = netdev_priv(netdev);
521 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
524 coal->rx_coalesce_usecs = priv->params.rx_cq_moderation_usec;
525 coal->rx_max_coalesced_frames = priv->params.rx_cq_moderation_pkts;
526 coal->tx_coalesce_usecs = priv->params.tx_cq_moderation_usec;
527 coal->tx_max_coalesced_frames = priv->params.tx_cq_moderation_pkts;
532 static int mlx5e_set_coalesce(struct net_device *netdev,
533 struct ethtool_coalesce *coal)
535 struct mlx5e_priv *priv = netdev_priv(netdev);
536 struct mlx5_core_dev *mdev = priv->mdev;
537 struct mlx5e_channel *c;
541 if (!MLX5_CAP_GEN(mdev, cq_moderation))
544 mutex_lock(&priv->state_lock);
545 priv->params.tx_cq_moderation_usec = coal->tx_coalesce_usecs;
546 priv->params.tx_cq_moderation_pkts = coal->tx_max_coalesced_frames;
547 priv->params.rx_cq_moderation_usec = coal->rx_coalesce_usecs;
548 priv->params.rx_cq_moderation_pkts = coal->rx_max_coalesced_frames;
550 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
553 for (i = 0; i < priv->params.num_channels; ++i) {
554 c = priv->channel[i];
556 for (tc = 0; tc < c->num_tc; tc++) {
557 mlx5_core_modify_cq_moderation(mdev,
559 coal->tx_coalesce_usecs,
560 coal->tx_max_coalesced_frames);
563 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
564 coal->rx_coalesce_usecs,
565 coal->rx_max_coalesced_frames);
569 mutex_unlock(&priv->state_lock);
573 static u32 ptys2ethtool_supported_link(u32 eth_proto_cap)
576 u32 supported_modes = 0;
578 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
579 if (eth_proto_cap & MLX5E_PROT_MASK(i))
580 supported_modes |= ptys2ethtool_table[i].supported;
582 return supported_modes;
585 static u32 ptys2ethtool_adver_link(u32 eth_proto_cap)
588 u32 advertising_modes = 0;
590 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
591 if (eth_proto_cap & MLX5E_PROT_MASK(i))
592 advertising_modes |= ptys2ethtool_table[i].advertised;
594 return advertising_modes;
597 static u32 ptys2ethtool_supported_port(u32 eth_proto_cap)
599 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
600 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
601 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
602 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
603 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
604 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
605 return SUPPORTED_FIBRE;
608 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
609 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
610 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
611 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
612 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
613 return SUPPORTED_Backplane;
618 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
625 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
629 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
630 if (proto_cap & MLX5E_PROT_MASK(i))
631 max_speed = max(max_speed, ptys2ethtool_table[i].speed);
637 static void get_speed_duplex(struct net_device *netdev,
639 struct ethtool_cmd *cmd)
642 u32 speed = SPEED_UNKNOWN;
643 u8 duplex = DUPLEX_UNKNOWN;
645 if (!netif_carrier_ok(netdev))
648 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
649 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
650 speed = ptys2ethtool_table[i].speed;
651 duplex = DUPLEX_FULL;
656 ethtool_cmd_speed_set(cmd, speed);
657 cmd->duplex = duplex;
660 static void get_supported(u32 eth_proto_cap, u32 *supported)
662 *supported |= ptys2ethtool_supported_port(eth_proto_cap);
663 *supported |= ptys2ethtool_supported_link(eth_proto_cap);
664 *supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
667 static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
668 u8 rx_pause, u32 *advertising)
670 *advertising |= ptys2ethtool_adver_link(eth_proto_cap);
671 *advertising |= tx_pause ? ADVERTISED_Pause : 0;
672 *advertising |= (tx_pause ^ rx_pause) ? ADVERTISED_Asym_Pause : 0;
675 static u8 get_connector_port(u32 eth_proto)
677 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
678 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
679 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
680 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
684 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
685 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
686 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
690 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
691 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
692 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
693 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
700 static void get_lp_advertising(u32 eth_proto_lp, u32 *lp_advertising)
702 *lp_advertising = ptys2ethtool_adver_link(eth_proto_lp);
705 static int mlx5e_get_settings(struct net_device *netdev,
706 struct ethtool_cmd *cmd)
708 struct mlx5e_priv *priv = netdev_priv(netdev);
709 struct mlx5_core_dev *mdev = priv->mdev;
710 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
717 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
720 netdev_err(netdev, "%s: query port ptys failed: %d\n",
725 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
726 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
727 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
728 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
731 cmd->advertising = 0;
733 get_supported(eth_proto_cap, &cmd->supported);
734 get_advertising(eth_proto_admin, 0, 0, &cmd->advertising);
735 get_speed_duplex(netdev, eth_proto_oper, cmd);
737 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
739 cmd->port = get_connector_port(eth_proto_oper);
740 get_lp_advertising(eth_proto_lp, &cmd->lp_advertising);
742 cmd->transceiver = XCVR_INTERNAL;
748 static u32 mlx5e_ethtool2ptys_adver_link(u32 link_modes)
750 u32 i, ptys_modes = 0;
752 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
753 if (ptys2ethtool_table[i].advertised & link_modes)
754 ptys_modes |= MLX5E_PROT_MASK(i);
760 static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
762 u32 i, speed_links = 0;
764 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
765 if (ptys2ethtool_table[i].speed == speed)
766 speed_links |= MLX5E_PROT_MASK(i);
772 static int mlx5e_set_settings(struct net_device *netdev,
773 struct ethtool_cmd *cmd)
775 struct mlx5e_priv *priv = netdev_priv(netdev);
776 struct mlx5_core_dev *mdev = priv->mdev;
779 u32 eth_proto_cap, eth_proto_admin;
780 enum mlx5_port_status ps;
783 speed = ethtool_cmd_speed(cmd);
785 link_modes = cmd->autoneg == AUTONEG_ENABLE ?
786 mlx5e_ethtool2ptys_adver_link(cmd->advertising) :
787 mlx5e_ethtool2ptys_speed_link(speed);
789 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
791 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
796 link_modes = link_modes & eth_proto_cap;
798 netdev_err(netdev, "%s: Not supported link mode(s) requested",
804 err = mlx5_query_port_proto_admin(mdev, ð_proto_admin, MLX5_PTYS_EN);
806 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
811 if (link_modes == eth_proto_admin)
814 mlx5_query_port_admin_status(mdev, &ps);
815 if (ps == MLX5_PORT_UP)
816 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
817 mlx5_set_port_proto(mdev, link_modes, MLX5_PTYS_EN);
818 if (ps == MLX5_PORT_UP)
819 mlx5_set_port_admin_status(mdev, MLX5_PORT_UP);
825 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
827 struct mlx5e_priv *priv = netdev_priv(netdev);
829 return sizeof(priv->params.toeplitz_hash_key);
832 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
834 return MLX5E_INDIR_RQT_SIZE;
837 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
840 struct mlx5e_priv *priv = netdev_priv(netdev);
843 memcpy(indir, priv->params.indirection_rqt,
844 sizeof(priv->params.indirection_rqt));
847 memcpy(key, priv->params.toeplitz_hash_key,
848 sizeof(priv->params.toeplitz_hash_key));
851 *hfunc = priv->params.rss_hfunc;
856 static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
858 struct mlx5_core_dev *mdev = priv->mdev;
859 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
862 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
863 mlx5e_build_tir_ctx_hash(tirc, priv);
865 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
866 mlx5_core_modify_tir(mdev, priv->indir_tirn[i], in, inlen);
869 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
870 const u8 *key, const u8 hfunc)
872 struct mlx5e_priv *priv = netdev_priv(dev);
873 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
876 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
877 (hfunc != ETH_RSS_HASH_XOR) &&
878 (hfunc != ETH_RSS_HASH_TOP))
881 in = mlx5_vzalloc(inlen);
885 mutex_lock(&priv->state_lock);
888 u32 rqtn = priv->indir_rqtn;
890 memcpy(priv->params.indirection_rqt, indir,
891 sizeof(priv->params.indirection_rqt));
892 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
896 memcpy(priv->params.toeplitz_hash_key, key,
897 sizeof(priv->params.toeplitz_hash_key));
899 if (hfunc != ETH_RSS_HASH_NO_CHANGE)
900 priv->params.rss_hfunc = hfunc;
902 mlx5e_modify_tirs_hash(priv, in, inlen);
904 mutex_unlock(&priv->state_lock);
911 static int mlx5e_get_rxnfc(struct net_device *netdev,
912 struct ethtool_rxnfc *info, u32 *rule_locs)
914 struct mlx5e_priv *priv = netdev_priv(netdev);
918 case ETHTOOL_GRXRINGS:
919 info->data = priv->params.num_channels;
929 static int mlx5e_get_tunable(struct net_device *dev,
930 const struct ethtool_tunable *tuna,
933 const struct mlx5e_priv *priv = netdev_priv(dev);
937 case ETHTOOL_TX_COPYBREAK:
938 *(u32 *)data = priv->params.tx_max_inline;
948 static int mlx5e_set_tunable(struct net_device *dev,
949 const struct ethtool_tunable *tuna,
952 struct mlx5e_priv *priv = netdev_priv(dev);
953 struct mlx5_core_dev *mdev = priv->mdev;
959 case ETHTOOL_TX_COPYBREAK:
961 if (val > mlx5e_get_max_inline_cap(mdev)) {
966 mutex_lock(&priv->state_lock);
968 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
970 mlx5e_close_locked(dev);
972 priv->params.tx_max_inline = val;
975 err = mlx5e_open_locked(dev);
977 mutex_unlock(&priv->state_lock);
987 static void mlx5e_get_pauseparam(struct net_device *netdev,
988 struct ethtool_pauseparam *pauseparam)
990 struct mlx5e_priv *priv = netdev_priv(netdev);
991 struct mlx5_core_dev *mdev = priv->mdev;
994 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
995 &pauseparam->tx_pause);
997 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1002 static int mlx5e_set_pauseparam(struct net_device *netdev,
1003 struct ethtool_pauseparam *pauseparam)
1005 struct mlx5e_priv *priv = netdev_priv(netdev);
1006 struct mlx5_core_dev *mdev = priv->mdev;
1009 if (pauseparam->autoneg)
1012 err = mlx5_set_port_pause(mdev,
1013 pauseparam->rx_pause ? 1 : 0,
1014 pauseparam->tx_pause ? 1 : 0);
1016 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1023 static int mlx5e_get_ts_info(struct net_device *dev,
1024 struct ethtool_ts_info *info)
1026 struct mlx5e_priv *priv = netdev_priv(dev);
1029 ret = ethtool_op_get_ts_info(dev, info);
1033 info->phc_index = priv->tstamp.ptp ?
1034 ptp_clock_index(priv->tstamp.ptp) : -1;
1036 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1039 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1040 SOF_TIMESTAMPING_RX_HARDWARE |
1041 SOF_TIMESTAMPING_RAW_HARDWARE;
1043 info->tx_types = (BIT(1) << HWTSTAMP_TX_OFF) |
1044 (BIT(1) << HWTSTAMP_TX_ON);
1046 info->rx_filters = (BIT(1) << HWTSTAMP_FILTER_NONE) |
1047 (BIT(1) << HWTSTAMP_FILTER_ALL);
1052 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1056 if (MLX5_CAP_GEN(mdev, wol_g))
1059 if (MLX5_CAP_GEN(mdev, wol_s))
1060 ret |= WAKE_MAGICSECURE;
1062 if (MLX5_CAP_GEN(mdev, wol_a))
1065 if (MLX5_CAP_GEN(mdev, wol_b))
1068 if (MLX5_CAP_GEN(mdev, wol_m))
1071 if (MLX5_CAP_GEN(mdev, wol_u))
1074 if (MLX5_CAP_GEN(mdev, wol_p))
1080 static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1084 if (mode & MLX5_WOL_MAGIC)
1087 if (mode & MLX5_WOL_SECURED_MAGIC)
1088 ret |= WAKE_MAGICSECURE;
1090 if (mode & MLX5_WOL_ARP)
1093 if (mode & MLX5_WOL_BROADCAST)
1096 if (mode & MLX5_WOL_MULTICAST)
1099 if (mode & MLX5_WOL_UNICAST)
1102 if (mode & MLX5_WOL_PHY_ACTIVITY)
1108 static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1112 if (mode & WAKE_MAGIC)
1113 ret |= MLX5_WOL_MAGIC;
1115 if (mode & WAKE_MAGICSECURE)
1116 ret |= MLX5_WOL_SECURED_MAGIC;
1118 if (mode & WAKE_ARP)
1119 ret |= MLX5_WOL_ARP;
1121 if (mode & WAKE_BCAST)
1122 ret |= MLX5_WOL_BROADCAST;
1124 if (mode & WAKE_MCAST)
1125 ret |= MLX5_WOL_MULTICAST;
1127 if (mode & WAKE_UCAST)
1128 ret |= MLX5_WOL_UNICAST;
1130 if (mode & WAKE_PHY)
1131 ret |= MLX5_WOL_PHY_ACTIVITY;
1136 static void mlx5e_get_wol(struct net_device *netdev,
1137 struct ethtool_wolinfo *wol)
1139 struct mlx5e_priv *priv = netdev_priv(netdev);
1140 struct mlx5_core_dev *mdev = priv->mdev;
1144 memset(wol, 0, sizeof(*wol));
1146 wol->supported = mlx5e_get_wol_supported(mdev);
1147 if (!wol->supported)
1150 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1154 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1157 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1159 struct mlx5e_priv *priv = netdev_priv(netdev);
1160 struct mlx5_core_dev *mdev = priv->mdev;
1161 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1167 if (wol->wolopts & ~wol_supported)
1170 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1172 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1175 static int mlx5e_set_phys_id(struct net_device *dev,
1176 enum ethtool_phys_id_state state)
1178 struct mlx5e_priv *priv = netdev_priv(dev);
1179 struct mlx5_core_dev *mdev = priv->mdev;
1180 u16 beacon_duration;
1182 if (!MLX5_CAP_GEN(mdev, beacon_led))
1186 case ETHTOOL_ID_ACTIVE:
1187 beacon_duration = MLX5_BEACON_DURATION_INF;
1189 case ETHTOOL_ID_INACTIVE:
1190 beacon_duration = MLX5_BEACON_DURATION_OFF;
1196 return mlx5_set_port_beacon(mdev, beacon_duration);
1199 static int mlx5e_get_module_info(struct net_device *netdev,
1200 struct ethtool_modinfo *modinfo)
1202 struct mlx5e_priv *priv = netdev_priv(netdev);
1203 struct mlx5_core_dev *dev = priv->mdev;
1207 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1211 /* data[0] = identifier byte */
1213 case MLX5_MODULE_ID_QSFP:
1214 modinfo->type = ETH_MODULE_SFF_8436;
1215 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1217 case MLX5_MODULE_ID_QSFP_PLUS:
1218 case MLX5_MODULE_ID_QSFP28:
1219 /* data[1] = revision id */
1220 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1221 modinfo->type = ETH_MODULE_SFF_8636;
1222 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1224 modinfo->type = ETH_MODULE_SFF_8436;
1225 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1228 case MLX5_MODULE_ID_SFP:
1229 modinfo->type = ETH_MODULE_SFF_8472;
1230 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1233 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1241 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1242 struct ethtool_eeprom *ee,
1245 struct mlx5e_priv *priv = netdev_priv(netdev);
1246 struct mlx5_core_dev *mdev = priv->mdev;
1247 int offset = ee->offset;
1254 memset(data, 0, ee->len);
1256 while (i < ee->len) {
1257 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1264 if (size_read < 0) {
1265 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1266 __func__, size_read);
1271 offset += size_read;
1277 const struct ethtool_ops mlx5e_ethtool_ops = {
1278 .get_drvinfo = mlx5e_get_drvinfo,
1279 .get_link = ethtool_op_get_link,
1280 .get_strings = mlx5e_get_strings,
1281 .get_sset_count = mlx5e_get_sset_count,
1282 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1283 .get_ringparam = mlx5e_get_ringparam,
1284 .set_ringparam = mlx5e_set_ringparam,
1285 .get_channels = mlx5e_get_channels,
1286 .set_channels = mlx5e_set_channels,
1287 .get_coalesce = mlx5e_get_coalesce,
1288 .set_coalesce = mlx5e_set_coalesce,
1289 .get_settings = mlx5e_get_settings,
1290 .set_settings = mlx5e_set_settings,
1291 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1292 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1293 .get_rxfh = mlx5e_get_rxfh,
1294 .set_rxfh = mlx5e_set_rxfh,
1295 .get_rxnfc = mlx5e_get_rxnfc,
1296 .get_tunable = mlx5e_get_tunable,
1297 .set_tunable = mlx5e_set_tunable,
1298 .get_pauseparam = mlx5e_get_pauseparam,
1299 .set_pauseparam = mlx5e_set_pauseparam,
1300 .get_ts_info = mlx5e_get_ts_info,
1301 .set_phys_id = mlx5e_set_phys_id,
1302 .get_wol = mlx5e_get_wol,
1303 .set_wol = mlx5e_set_wol,
1304 .get_module_info = mlx5e_get_module_info,
1305 .get_module_eeprom = mlx5e_get_module_eeprom,