drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include "en.h"
  34
  35 static void mlx5e_get_drvinfo(struct net_device *dev,
  36                               struct ethtool_drvinfo *drvinfo)
  37 {
  38         struct mlx5e_priv *priv = netdev_priv(dev);
  39         struct mlx5_core_dev *mdev = priv->mdev;
  40
  41         strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
  42         strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")",
  43                 sizeof(drvinfo->version));
  44         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
  45                  "%d.%d.%d",
  46                  fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev));
  47         strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
  48                 sizeof(drvinfo->bus_info));
  49 }
  50
  51 struct ptys2ethtool_config {
  52         __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
  53         __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
  54         u32 speed;
  55 };
  56
  57 static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
  58
  59 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...)               \
  60         ({                                                              \
  61                 struct ptys2ethtool_config *cfg;                        \
  62                 const unsigned int modes[] = { __VA_ARGS__ };           \
  63                 unsigned int i;                                         \
  64                 cfg = &ptys2ethtool_table[reg_];                        \
  65                 cfg->speed = speed_;                                    \
  66                 bitmap_zero(cfg->supported,                             \
  67                             __ETHTOOL_LINK_MODE_MASK_NBITS);            \
  68                 bitmap_zero(cfg->advertised,                            \
  69                             __ETHTOOL_LINK_MODE_MASK_NBITS);            \
  70                 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) {             \
  71                         __set_bit(modes[i], cfg->supported);            \
  72                         __set_bit(modes[i], cfg->advertised);           \
  73                 }                                                       \
  74         })
  75
  76 void mlx5e_build_ptys2ethtool_map(void)
  77 {
  78         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000,
  79                                        ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
  80         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000,
  81                                        ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
  82         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000,
  83                                        ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
  84         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000,
  85                                        ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
  86         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000,
  87                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
  88         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000,
  89                                        ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
  90         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000,
  91                                        ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
  92         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000,
  93                                        ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
  94         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000,
  95                                        ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
  96         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000,
  97                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
  98         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000,
  99                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
 100         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000,
 101                                        ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
 102         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000,
 103                                        ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
 104         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000,
 105                                        ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
 106         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000,
 107                                        ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
 108         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000,
 109                                        ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
 110         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000,
 111                                        ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
 112         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000,
 113                                        ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
 114         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000,
 115                                        ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
 116         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000,
 117                                        ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
 118         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000,
 119                                        ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
 120         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000,
 121                                        ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
 122         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000,
 123                                        ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
 124         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000,
 125                                        ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
 126         MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000,
 127                                        ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
 128 }
 129
 130 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
 131 {
 132         struct mlx5_core_dev *mdev = priv->mdev;
 133         u8 pfc_en_tx;
 134         u8 pfc_en_rx;
 135         int err;
 136
 137         err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
 138
 139         return err ? 0 : pfc_en_tx | pfc_en_rx;
 140 }
 141
 142 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
 143 {
 144         struct mlx5_core_dev *mdev = priv->mdev;
 145         u32 rx_pause;
 146         u32 tx_pause;
 147         int err;
 148
 149         err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
 150
 151         return err ? false : rx_pause | tx_pause;
 152 }
 153
 154 #define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
 155 #define MLX5E_NUM_RQ_STATS(priv) \
 156         (NUM_RQ_STATS * priv->params.num_channels * \
 157          test_bit(MLX5E_STATE_OPENED, &priv->state))
 158 #define MLX5E_NUM_SQ_STATS(priv) \
 159         (NUM_SQ_STATS * priv->params.num_channels * priv->params.num_tc * \
 160          test_bit(MLX5E_STATE_OPENED, &priv->state))
 161 #define MLX5E_NUM_PFC_COUNTERS(priv) \
 162         ((mlx5e_query_global_pause_combined(priv) + hweight8(mlx5e_query_pfc_combined(priv))) * \
 163           NUM_PPORT_PER_PRIO_PFC_COUNTERS)
 164
 165 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
 166 {
 167         struct mlx5e_priv *priv = netdev_priv(dev);
 168
 169         switch (sset) {
 170         case ETH_SS_STATS:
 171                 return NUM_SW_COUNTERS +
 172                        MLX5E_NUM_Q_CNTRS(priv) +
 173                        NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS +
 174                        MLX5E_NUM_RQ_STATS(priv) +
 175                        MLX5E_NUM_SQ_STATS(priv) +
 176                        MLX5E_NUM_PFC_COUNTERS(priv) +
 177                        ARRAY_SIZE(mlx5e_pme_status_desc) +
 178                        ARRAY_SIZE(mlx5e_pme_error_desc);
 179
 180         case ETH_SS_PRIV_FLAGS:
 181                 return ARRAY_SIZE(mlx5e_priv_flags);
 182         case ETH_SS_TEST:
 183                 return mlx5e_self_test_num(priv);
 184         /* fallthrough */
 185         default:
 186                 return -EOPNOTSUPP;
 187         }
 188 }
 189
 190 static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
 191 {
 192         int i, j, tc, prio, idx = 0;
 193         unsigned long pfc_combined;
 194
 195         /* SW counters */
 196         for (i = 0; i < NUM_SW_COUNTERS; i++)
 197                 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
 198
 199         /* Q counters */
 200         for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
 201                 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].format);
 202
 203         /* VPORT counters */
 204         for (i = 0; i < NUM_VPORT_COUNTERS; i++)
 205                 strcpy(data + (idx++) * ETH_GSTRING_LEN,
 206                        vport_stats_desc[i].format);
 207
 208         /* PPORT counters */
 209         for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
 210                 strcpy(data + (idx++) * ETH_GSTRING_LEN,
 211                        pport_802_3_stats_desc[i].format);
 212
 213         for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
 214                 strcpy(data + (idx++) * ETH_GSTRING_LEN,
 215                        pport_2863_stats_desc[i].format);
 216
 217         for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
 218                 strcpy(data + (idx++) * ETH_GSTRING_LEN,
 219                        pport_2819_stats_desc[i].format);
 220
 221         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 222                 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
 223                         sprintf(data + (idx++) * ETH_GSTRING_LEN,
 224                                 pport_per_prio_traffic_stats_desc[i].format, prio);
 225         }
 226
 227         pfc_combined = mlx5e_query_pfc_combined(priv);
 228         for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
 229                 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
 230                         char pfc_string[ETH_GSTRING_LEN];
 231
 232                         snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
 233                         sprintf(data + (idx++) * ETH_GSTRING_LEN,
 234                                 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
 235                 }
 236         }
 237
 238         if (mlx5e_query_global_pause_combined(priv)) {
 239                 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
 240                         sprintf(data + (idx++) * ETH_GSTRING_LEN,
 241                                 pport_per_prio_pfc_stats_desc[i].format, "global");
 242                 }
 243         }
 244
 245         /* port module event counters */
 246         for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
 247                 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
 248
 249         for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
 250                 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
 251
 252         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 253                 return;
 254
 255         /* per channel counters */
 256         for (i = 0; i < priv->params.num_channels; i++)
 257                 for (j = 0; j < NUM_RQ_STATS; j++)
 258                         sprintf(data + (idx++) * ETH_GSTRING_LEN,
 259                                 rq_stats_desc[j].format, i);
 260
 261         for (tc = 0; tc < priv->params.num_tc; tc++)
 262                 for (i = 0; i < priv->params.num_channels; i++)
 263                         for (j = 0; j < NUM_SQ_STATS; j++)
 264                                 sprintf(data + (idx++) * ETH_GSTRING_LEN,
 265                                         sq_stats_desc[j].format,
 266                                         priv->channeltc_to_txq_map[i][tc]);
 267 }
 268
 269 static void mlx5e_get_strings(struct net_device *dev,
 270                               uint32_t stringset, uint8_t *data)
 271 {
 272         struct mlx5e_priv *priv = netdev_priv(dev);
 273         int i;
 274
 275         switch (stringset) {
 276         case ETH_SS_PRIV_FLAGS:
 277                 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
 278                         strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
 279                 break;
 280
 281         case ETH_SS_TEST:
 282                 for (i = 0; i < mlx5e_self_test_num(priv); i++)
 283                         strcpy(data + i * ETH_GSTRING_LEN,
 284                                mlx5e_self_tests[i]);
 285                 break;
 286
 287         case ETH_SS_STATS:
 288                 mlx5e_fill_stats_strings(priv, data);
 289                 break;
 290         }
 291 }
 292
 293 static void mlx5e_get_ethtool_stats(struct net_device *dev,
 294                                     struct ethtool_stats *stats, u64 *data)
 295 {
 296         struct mlx5e_priv *priv = netdev_priv(dev);
 297         struct mlx5_priv *mlx5_priv;
 298         int i, j, tc, prio, idx = 0;
 299         unsigned long pfc_combined;
 300
 301         if (!data)
 302                 return;
 303
 304         mutex_lock(&priv->state_lock);
 305         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 306                 mlx5e_update_stats(priv);
 307         mutex_unlock(&priv->state_lock);
 308
 309         for (i = 0; i < NUM_SW_COUNTERS; i++)
 310                 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
 311                                                    sw_stats_desc, i);
 312
 313         for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
 314                 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
 315                                                    q_stats_desc, i);
 316
 317         for (i = 0; i < NUM_VPORT_COUNTERS; i++)
 318                 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
 319                                                   vport_stats_desc, i);
 320
 321         for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
 322                 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
 323                                                   pport_802_3_stats_desc, i);
 324
 325         for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
 326                 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
 327                                                   pport_2863_stats_desc, i);
 328
 329         for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
 330                 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
 331                                                   pport_2819_stats_desc, i);
 332
 333         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 334                 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
 335                         data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
 336                                                  pport_per_prio_traffic_stats_desc, i);
 337         }
 338
 339         pfc_combined = mlx5e_query_pfc_combined(priv);
 340         for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
 341                 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
 342                         data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
 343                                                           pport_per_prio_pfc_stats_desc, i);
 344                 }
 345         }
 346
 347         if (mlx5e_query_global_pause_combined(priv)) {
 348                 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
 349                         data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
 350                                                           pport_per_prio_pfc_stats_desc, i);
 351                 }
 352         }
 353
 354         /* port module event counters */
 355         mlx5_priv =  &priv->mdev->priv;
 356         for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
 357                 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
 358                                                    mlx5e_pme_status_desc, i);
 359
 360         for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
 361                 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
 362                                                    mlx5e_pme_error_desc, i);
 363
 364         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 365                 return;
 366
 367         /* per channel counters */
 368         for (i = 0; i < priv->params.num_channels; i++)
 369                 for (j = 0; j < NUM_RQ_STATS; j++)
 370                         data[idx++] =
 371                                MLX5E_READ_CTR64_CPU(&priv->channel[i]->rq.stats,
 372                                                     rq_stats_desc, j);
 373
 374         for (tc = 0; tc < priv->params.num_tc; tc++)
 375                 for (i = 0; i < priv->params.num_channels; i++)
 376                         for (j = 0; j < NUM_SQ_STATS; j++)
 377                                 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->channel[i]->sq[tc].stats,
 378                                                                    sq_stats_desc, j);
 379 }
 380
 381 static u32 mlx5e_rx_wqes_to_packets(struct mlx5e_priv *priv, int rq_wq_type,
 382                                     int num_wqe)
 383 {
 384         int packets_per_wqe;
 385         int stride_size;
 386         int num_strides;
 387         int wqe_size;
 388
 389         if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 390                 return num_wqe;
 391
 392         stride_size = 1 << priv->params.mpwqe_log_stride_sz;
 393         num_strides = 1 << priv->params.mpwqe_log_num_strides;
 394         wqe_size = stride_size * num_strides;
 395
 396         packets_per_wqe = wqe_size /
 397                           ALIGN(ETH_DATA_LEN, stride_size);
 398         return (1 << (order_base_2(num_wqe * packets_per_wqe) - 1));
 399 }
 400
 401 static u32 mlx5e_packets_to_rx_wqes(struct mlx5e_priv *priv, int rq_wq_type,
 402                                     int num_packets)
 403 {
 404         int packets_per_wqe;
 405         int stride_size;
 406         int num_strides;
 407         int wqe_size;
 408         int num_wqes;
 409
 410         if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
 411                 return num_packets;
 412
 413         stride_size = 1 << priv->params.mpwqe_log_stride_sz;
 414         num_strides = 1 << priv->params.mpwqe_log_num_strides;
 415         wqe_size = stride_size * num_strides;
 416
 417         num_packets = (1 << order_base_2(num_packets));
 418
 419         packets_per_wqe = wqe_size /
 420                           ALIGN(ETH_DATA_LEN, stride_size);
 421         num_wqes = DIV_ROUND_UP(num_packets, packets_per_wqe);
 422         return 1 << (order_base_2(num_wqes));
 423 }
 424
 425 static void mlx5e_get_ringparam(struct net_device *dev,
 426                                 struct ethtool_ringparam *param)
 427 {
 428         struct mlx5e_priv *priv = netdev_priv(dev);
 429         int rq_wq_type = priv->params.rq_wq_type;
 430
 431         param->rx_max_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
 432                                                          1 << mlx5_max_log_rq_size(rq_wq_type));
 433         param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
 434         param->rx_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
 435                                                      1 << priv->params.log_rq_size);
 436         param->tx_pending     = 1 << priv->params.log_sq_size;
 437 }
 438
 439 static int mlx5e_set_ringparam(struct net_device *dev,
 440                                struct ethtool_ringparam *param)
 441 {
 442         struct mlx5e_priv *priv = netdev_priv(dev);
 443         bool was_opened;
 444         int rq_wq_type = priv->params.rq_wq_type;
 445         u32 rx_pending_wqes;
 446         u32 min_rq_size;
 447         u32 max_rq_size;
 448         u16 min_rx_wqes;
 449         u8 log_rq_size;
 450         u8 log_sq_size;
 451         u32 num_mtts;
 452         int err = 0;
 453
 454         if (param->rx_jumbo_pending) {
 455                 netdev_info(dev, "%s: rx_jumbo_pending not supported\n",
 456                             __func__);
 457                 return -EINVAL;
 458         }
 459         if (param->rx_mini_pending) {
 460                 netdev_info(dev, "%s: rx_mini_pending not supported\n",
 461                             __func__);
 462                 return -EINVAL;
 463         }
 464
 465         min_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
 466                                                1 << mlx5_min_log_rq_size(rq_wq_type));
 467         max_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
 468                                                1 << mlx5_max_log_rq_size(rq_wq_type));
 469         rx_pending_wqes = mlx5e_packets_to_rx_wqes(priv, rq_wq_type,
 470                                                    param->rx_pending);
 471
 472         if (param->rx_pending < min_rq_size) {
 473                 netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n",
 474                             __func__, param->rx_pending,
 475                             min_rq_size);
 476                 return -EINVAL;
 477         }
 478         if (param->rx_pending > max_rq_size) {
 479                 netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n",
 480                             __func__, param->rx_pending,
 481                             max_rq_size);
 482                 return -EINVAL;
 483         }
 484
 485         num_mtts = MLX5E_REQUIRED_MTTS(rx_pending_wqes);
 486         if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
 487             !MLX5E_VALID_NUM_MTTS(num_mtts)) {
 488                 netdev_info(dev, "%s: rx_pending (%d) request can't be satisfied, try to reduce.\n",
 489                             __func__, param->rx_pending);
 490                 return -EINVAL;
 491         }
 492
 493         if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
 494                 netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n",
 495                             __func__, param->tx_pending,
 496                             1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
 497                 return -EINVAL;
 498         }
 499         if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
 500                 netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n",
 501                             __func__, param->tx_pending,
 502                             1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
 503                 return -EINVAL;
 504         }
 505
 506         log_rq_size = order_base_2(rx_pending_wqes);
 507         log_sq_size = order_base_2(param->tx_pending);
 508         min_rx_wqes = mlx5_min_rx_wqes(rq_wq_type, rx_pending_wqes);
 509
 510         if (log_rq_size == priv->params.log_rq_size &&
 511             log_sq_size == priv->params.log_sq_size &&
 512             min_rx_wqes == priv->params.min_rx_wqes)
 513                 return 0;
 514
 515         mutex_lock(&priv->state_lock);
 516
 517         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 518         if (was_opened)
 519                 mlx5e_close_locked(dev);
 520
 521         priv->params.log_rq_size = log_rq_size;
 522         priv->params.log_sq_size = log_sq_size;
 523         priv->params.min_rx_wqes = min_rx_wqes;
 524
 525         if (was_opened)
 526                 err = mlx5e_open_locked(dev);
 527
 528         mutex_unlock(&priv->state_lock);
 529
 530         return err;
 531 }
 532
 533 static void mlx5e_get_channels(struct net_device *dev,
 534                                struct ethtool_channels *ch)
 535 {
 536         struct mlx5e_priv *priv = netdev_priv(dev);
 537
 538         ch->max_combined   = mlx5e_get_max_num_channels(priv->mdev);
 539         ch->combined_count = priv->params.num_channels;
 540 }
 541
 542 static int mlx5e_set_channels(struct net_device *dev,
 543                               struct ethtool_channels *ch)
 544 {
 545         struct mlx5e_priv *priv = netdev_priv(dev);
 546         unsigned int count = ch->combined_count;
 547         bool arfs_enabled;
 548         bool was_opened;
 549         int err = 0;
 550
 551         if (!count) {
 552                 netdev_info(dev, "%s: combined_count=0 not supported\n",
 553                             __func__);
 554                 return -EINVAL;
 555         }
 556
 557         if (priv->params.num_channels == count)
 558                 return 0;
 559
 560         mutex_lock(&priv->state_lock);
 561
 562         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 563         if (was_opened)
 564                 mlx5e_close_locked(dev);
 565
 566         arfs_enabled = dev->features & NETIF_F_NTUPLE;
 567         if (arfs_enabled)
 568                 mlx5e_arfs_disable(priv);
 569
 570         priv->params.num_channels = count;
 571         mlx5e_build_default_indir_rqt(priv->mdev, priv->params.indirection_rqt,
 572                                       MLX5E_INDIR_RQT_SIZE, count);
 573
 574         if (was_opened)
 575                 err = mlx5e_open_locked(dev);
 576         if (err)
 577                 goto out;
 578
 579         if (arfs_enabled) {
 580                 err = mlx5e_arfs_enable(priv);
 581                 if (err)
 582                         netdev_err(dev, "%s: mlx5e_arfs_enable failed: %d\n",
 583                                    __func__, err);
 584         }
 585
 586 out:
 587         mutex_unlock(&priv->state_lock);
 588
 589         return err;
 590 }
 591
 592 static int mlx5e_get_coalesce(struct net_device *netdev,
 593                               struct ethtool_coalesce *coal)
 594 {
 595         struct mlx5e_priv *priv = netdev_priv(netdev);
 596
 597         if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
 598                 return -ENOTSUPP;
 599
 600         coal->rx_coalesce_usecs       = priv->params.rx_cq_moderation.usec;
 601         coal->rx_max_coalesced_frames = priv->params.rx_cq_moderation.pkts;
 602         coal->tx_coalesce_usecs       = priv->params.tx_cq_moderation.usec;
 603         coal->tx_max_coalesced_frames = priv->params.tx_cq_moderation.pkts;
 604         coal->use_adaptive_rx_coalesce = priv->params.rx_am_enabled;
 605
 606         return 0;
 607 }
 608
 609 static int mlx5e_set_coalesce(struct net_device *netdev,
 610                               struct ethtool_coalesce *coal)
 611 {
 612         struct mlx5e_priv *priv    = netdev_priv(netdev);
 613         struct mlx5_core_dev *mdev = priv->mdev;
 614         struct mlx5e_channel *c;
 615         bool restart =
 616                 !!coal->use_adaptive_rx_coalesce != priv->params.rx_am_enabled;
 617         bool was_opened;
 618         int err = 0;
 619         int tc;
 620         int i;
 621
 622         if (!MLX5_CAP_GEN(mdev, cq_moderation))
 623                 return -ENOTSUPP;
 624
 625         mutex_lock(&priv->state_lock);
 626
 627         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 628         if (was_opened && restart) {
 629                 mlx5e_close_locked(netdev);
 630                 priv->params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce;
 631         }
 632
 633         priv->params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
 634         priv->params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
 635         priv->params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
 636         priv->params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
 637
 638         if (!was_opened || restart)
 639                 goto out;
 640
 641         for (i = 0; i < priv->params.num_channels; ++i) {
 642                 c = priv->channel[i];
 643
 644                 for (tc = 0; tc < c->num_tc; tc++) {
 645                         mlx5_core_modify_cq_moderation(mdev,
 646                                                 &c->sq[tc].cq.mcq,
 647                                                 coal->tx_coalesce_usecs,
 648                                                 coal->tx_max_coalesced_frames);
 649                 }
 650
 651                 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
 652                                                coal->rx_coalesce_usecs,
 653                                                coal->rx_max_coalesced_frames);
 654         }
 655
 656 out:
 657         if (was_opened && restart)
 658                 err = mlx5e_open_locked(netdev);
 659
 660         mutex_unlock(&priv->state_lock);
 661         return err;
 662 }
 663
 664 static void ptys2ethtool_supported_link(unsigned long *supported_modes,
 665                                         u32 eth_proto_cap)
 666 {
 667         unsigned long proto_cap = eth_proto_cap;
 668         int proto;
 669
 670         for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
 671                 bitmap_or(supported_modes, supported_modes,
 672                           ptys2ethtool_table[proto].supported,
 673                           __ETHTOOL_LINK_MODE_MASK_NBITS);
 674 }
 675
 676 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
 677                                     u32 eth_proto_cap)
 678 {
 679         unsigned long proto_cap = eth_proto_cap;
 680         int proto;
 681
 682         for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
 683                 bitmap_or(advertising_modes, advertising_modes,
 684                           ptys2ethtool_table[proto].advertised,
 685                           __ETHTOOL_LINK_MODE_MASK_NBITS);
 686 }
 687
 688 static void ptys2ethtool_supported_port(struct ethtool_link_ksettings *link_ksettings,
 689                                         u32 eth_proto_cap)
 690 {
 691         if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
 692                            | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
 693                            | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
 694                            | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
 695                            | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
 696                            | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
 697                 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, FIBRE);
 698         }
 699
 700         if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
 701                            | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
 702                            | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
 703                            | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
 704                            | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
 705                 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Backplane);
 706         }
 707 }
 708
 709 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
 710 {
 711         u32 max_speed = 0;
 712         u32 proto_cap;
 713         int err;
 714         int i;
 715
 716         err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
 717         if (err)
 718                 return err;
 719
 720         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
 721                 if (proto_cap & MLX5E_PROT_MASK(i))
 722                         max_speed = max(max_speed, ptys2ethtool_table[i].speed);
 723
 724         *speed = max_speed;
 725         return 0;
 726 }
 727
 728 static void get_speed_duplex(struct net_device *netdev,
 729                              u32 eth_proto_oper,
 730                              struct ethtool_link_ksettings *link_ksettings)
 731 {
 732         int i;
 733         u32 speed = SPEED_UNKNOWN;
 734         u8 duplex = DUPLEX_UNKNOWN;
 735
 736         if (!netif_carrier_ok(netdev))
 737                 goto out;
 738
 739         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 740                 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
 741                         speed = ptys2ethtool_table[i].speed;
 742                         duplex = DUPLEX_FULL;
 743                         break;
 744                 }
 745         }
 746 out:
 747         link_ksettings->base.speed = speed;
 748         link_ksettings->base.duplex = duplex;
 749 }
 750
 751 static void get_supported(u32 eth_proto_cap,
 752                           struct ethtool_link_ksettings *link_ksettings)
 753 {
 754         unsigned long *supported = link_ksettings->link_modes.supported;
 755
 756         ptys2ethtool_supported_port(link_ksettings, eth_proto_cap);
 757         ptys2ethtool_supported_link(supported, eth_proto_cap);
 758         ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
 759         ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Asym_Pause);
 760 }
 761
 762 static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
 763                             u8 rx_pause,
 764                             struct ethtool_link_ksettings *link_ksettings)
 765 {
 766         unsigned long *advertising = link_ksettings->link_modes.advertising;
 767
 768         ptys2ethtool_adver_link(advertising, eth_proto_cap);
 769         if (tx_pause)
 770                 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
 771         if (tx_pause ^ rx_pause)
 772                 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
 773 }
 774
 775 static u8 get_connector_port(u32 eth_proto)
 776 {
 777         if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
 778                          | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
 779                          | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
 780                          | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
 781                         return PORT_FIBRE;
 782         }
 783
 784         if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
 785                          | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
 786                          | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
 787                         return PORT_DA;
 788         }
 789
 790         if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
 791                          | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
 792                          | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
 793                          | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
 794                         return PORT_NONE;
 795         }
 796
 797         return PORT_OTHER;
 798 }
 799
 800 static void get_lp_advertising(u32 eth_proto_lp,
 801                                struct ethtool_link_ksettings *link_ksettings)
 802 {
 803         unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
 804
 805         ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
 806 }
 807
 808 static int mlx5e_get_link_ksettings(struct net_device *netdev,
 809                                     struct ethtool_link_ksettings *link_ksettings)
 810 {
 811         struct mlx5e_priv *priv    = netdev_priv(netdev);
 812         struct mlx5_core_dev *mdev = priv->mdev;
 813         u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
 814         u32 eth_proto_cap;
 815         u32 eth_proto_admin;
 816         u32 eth_proto_lp;
 817         u32 eth_proto_oper;
 818         u8 an_disable_admin;
 819         u8 an_status;
 820         int err;
 821
 822         err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
 823         if (err) {
 824                 netdev_err(netdev, "%s: query port ptys failed: %d\n",
 825                            __func__, err);
 826                 goto err_query_ptys;
 827         }
 828
 829         eth_proto_cap    = MLX5_GET(ptys_reg, out, eth_proto_capability);
 830         eth_proto_admin  = MLX5_GET(ptys_reg, out, eth_proto_admin);
 831         eth_proto_oper   = MLX5_GET(ptys_reg, out, eth_proto_oper);
 832         eth_proto_lp     = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
 833         an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
 834         an_status        = MLX5_GET(ptys_reg, out, an_status);
 835
 836         ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
 837         ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
 838
 839         get_supported(eth_proto_cap, link_ksettings);
 840         get_advertising(eth_proto_admin, 0, 0, link_ksettings);
 841         get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
 842
 843         eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
 844
 845         link_ksettings->base.port = get_connector_port(eth_proto_oper);
 846         get_lp_advertising(eth_proto_lp, link_ksettings);
 847
 848         if (an_status == MLX5_AN_COMPLETE)
 849                 ethtool_link_ksettings_add_link_mode(link_ksettings,
 850                                                      lp_advertising, Autoneg);
 851
 852         link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
 853                                                           AUTONEG_ENABLE;
 854         ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
 855                                              Autoneg);
 856         if (!an_disable_admin)
 857                 ethtool_link_ksettings_add_link_mode(link_ksettings,
 858                                                      advertising, Autoneg);
 859
 860 err_query_ptys:
 861         return err;
 862 }
 863
 864 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
 865 {
 866         u32 i, ptys_modes = 0;
 867
 868         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 869                 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
 870                                       link_modes,
 871                                       __ETHTOOL_LINK_MODE_MASK_NBITS))
 872                         ptys_modes |= MLX5E_PROT_MASK(i);
 873         }
 874
 875         return ptys_modes;
 876 }
 877
 878 static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
 879 {
 880         u32 i, speed_links = 0;
 881
 882         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 883                 if (ptys2ethtool_table[i].speed == speed)
 884                         speed_links |= MLX5E_PROT_MASK(i);
 885         }
 886
 887         return speed_links;
 888 }
 889
 890 static int mlx5e_set_link_ksettings(struct net_device *netdev,
 891                                     const struct ethtool_link_ksettings *link_ksettings)
 892 {
 893         struct mlx5e_priv *priv    = netdev_priv(netdev);
 894         struct mlx5_core_dev *mdev = priv->mdev;
 895         u32 eth_proto_cap, eth_proto_admin;
 896         bool an_changes = false;
 897         u8 an_disable_admin;
 898         u8 an_disable_cap;
 899         bool an_disable;
 900         u32 link_modes;
 901         u8 an_status;
 902         u32 speed;
 903         int err;
 904
 905         speed = link_ksettings->base.speed;
 906
 907         link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
 908                 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
 909                 mlx5e_ethtool2ptys_speed_link(speed);
 910
 911         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 912         if (err) {
 913                 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
 914                            __func__, err);
 915                 goto out;
 916         }
 917
 918         link_modes = link_modes & eth_proto_cap;
 919         if (!link_modes) {
 920                 netdev_err(netdev, "%s: Not supported link mode(s) requested",
 921                            __func__);
 922                 err = -EINVAL;
 923                 goto out;
 924         }
 925
 926         err = mlx5_query_port_proto_admin(mdev, &eth_proto_admin, MLX5_PTYS_EN);
 927         if (err) {
 928                 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
 929                            __func__, err);
 930                 goto out;
 931         }
 932
 933         mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
 934                                 &an_disable_cap, &an_disable_admin);
 935
 936         an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
 937         an_changes = ((!an_disable && an_disable_admin) ||
 938                       (an_disable && !an_disable_admin));
 939
 940         if (!an_changes && link_modes == eth_proto_admin)
 941                 goto out;
 942
 943         mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
 944         mlx5_toggle_port_link(mdev);
 945
 946 out:
 947         return err;
 948 }
 949
 950 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
 951 {
 952         struct mlx5e_priv *priv = netdev_priv(netdev);
 953
 954         return sizeof(priv->params.toeplitz_hash_key);
 955 }
 956
 957 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
 958 {
 959         return MLX5E_INDIR_RQT_SIZE;
 960 }
 961
 962 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
 963                           u8 *hfunc)
 964 {
 965         struct mlx5e_priv *priv = netdev_priv(netdev);
 966
 967         if (indir)
 968                 memcpy(indir, priv->params.indirection_rqt,
 969                        sizeof(priv->params.indirection_rqt));
 970
 971         if (key)
 972                 memcpy(key, priv->params.toeplitz_hash_key,
 973                        sizeof(priv->params.toeplitz_hash_key));
 974
 975         if (hfunc)
 976                 *hfunc = priv->params.rss_hfunc;
 977
 978         return 0;
 979 }
 980
 981 static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
 982 {
 983         struct mlx5_core_dev *mdev = priv->mdev;
 984         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
 985         int i;
 986
 987         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
 988         mlx5e_build_tir_ctx_hash(tirc, priv);
 989
 990         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
 991                 mlx5_core_modify_tir(mdev, priv->indir_tir[i].tirn, in, inlen);
 992 }
 993
 994 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
 995                           const u8 *key, const u8 hfunc)
 996 {
 997         struct mlx5e_priv *priv = netdev_priv(dev);
 998         int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
 999         void *in;
1000
1001         if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1002             (hfunc != ETH_RSS_HASH_XOR) &&
1003             (hfunc != ETH_RSS_HASH_TOP))
1004                 return -EINVAL;
1005
1006         in = mlx5_vzalloc(inlen);
1007         if (!in)
1008                 return -ENOMEM;
1009
1010         mutex_lock(&priv->state_lock);
1011
1012         if (indir) {
1013                 u32 rqtn = priv->indir_rqt.rqtn;
1014
1015                 memcpy(priv->params.indirection_rqt, indir,
1016                        sizeof(priv->params.indirection_rqt));
1017                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1018         }
1019
1020         if (key)
1021                 memcpy(priv->params.toeplitz_hash_key, key,
1022                        sizeof(priv->params.toeplitz_hash_key));
1023
1024         if (hfunc != ETH_RSS_HASH_NO_CHANGE)
1025                 priv->params.rss_hfunc = hfunc;
1026
1027         mlx5e_modify_tirs_hash(priv, in, inlen);
1028
1029         mutex_unlock(&priv->state_lock);
1030
1031         kvfree(in);
1032
1033         return 0;
1034 }
1035
1036 static int mlx5e_get_rxnfc(struct net_device *netdev,
1037                            struct ethtool_rxnfc *info, u32 *rule_locs)
1038 {
1039         struct mlx5e_priv *priv = netdev_priv(netdev);
1040         int err = 0;
1041
1042         switch (info->cmd) {
1043         case ETHTOOL_GRXRINGS:
1044                 info->data = priv->params.num_channels;
1045                 break;
1046         case ETHTOOL_GRXCLSRLCNT:
1047                 info->rule_cnt = priv->fs.ethtool.tot_num_rules;
1048                 break;
1049         case ETHTOOL_GRXCLSRULE:
1050                 err = mlx5e_ethtool_get_flow(priv, info, info->fs.location);
1051                 break;
1052         case ETHTOOL_GRXCLSRLALL:
1053                 err = mlx5e_ethtool_get_all_flows(priv, info, rule_locs);
1054                 break;
1055         default:
1056                 err = -EOPNOTSUPP;
1057                 break;
1058         }
1059
1060         return err;
1061 }
1062
1063 static int mlx5e_get_tunable(struct net_device *dev,
1064                              const struct ethtool_tunable *tuna,
1065                              void *data)
1066 {
1067         const struct mlx5e_priv *priv = netdev_priv(dev);
1068         int err = 0;
1069
1070         switch (tuna->id) {
1071         case ETHTOOL_TX_COPYBREAK:
1072                 *(u32 *)data = priv->params.tx_max_inline;
1073                 break;
1074         default:
1075                 err = -EINVAL;
1076                 break;
1077         }
1078
1079         return err;
1080 }
1081
1082 static int mlx5e_set_tunable(struct net_device *dev,
1083                              const struct ethtool_tunable *tuna,
1084                              const void *data)
1085 {
1086         struct mlx5e_priv *priv = netdev_priv(dev);
1087         struct mlx5_core_dev *mdev = priv->mdev;
1088         bool was_opened;
1089         u32 val;
1090         int err = 0;
1091
1092         switch (tuna->id) {
1093         case ETHTOOL_TX_COPYBREAK:
1094                 val = *(u32 *)data;
1095                 if (val > mlx5e_get_max_inline_cap(mdev)) {
1096                         err = -EINVAL;
1097                         break;
1098                 }
1099
1100                 mutex_lock(&priv->state_lock);
1101
1102                 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1103                 if (was_opened)
1104                         mlx5e_close_locked(dev);
1105
1106                 priv->params.tx_max_inline = val;
1107
1108                 if (was_opened)
1109                         err = mlx5e_open_locked(dev);
1110
1111                 mutex_unlock(&priv->state_lock);
1112                 break;
1113         default:
1114                 err = -EINVAL;
1115                 break;
1116         }
1117
1118         return err;
1119 }
1120
1121 static void mlx5e_get_pauseparam(struct net_device *netdev,
1122                                  struct ethtool_pauseparam *pauseparam)
1123 {
1124         struct mlx5e_priv *priv    = netdev_priv(netdev);
1125         struct mlx5_core_dev *mdev = priv->mdev;
1126         int err;
1127
1128         err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1129                                     &pauseparam->tx_pause);
1130         if (err) {
1131                 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1132                            __func__, err);
1133         }
1134 }
1135
1136 static int mlx5e_set_pauseparam(struct net_device *netdev,
1137                                 struct ethtool_pauseparam *pauseparam)
1138 {
1139         struct mlx5e_priv *priv    = netdev_priv(netdev);
1140         struct mlx5_core_dev *mdev = priv->mdev;
1141         int err;
1142
1143         if (pauseparam->autoneg)
1144                 return -EINVAL;
1145
1146         err = mlx5_set_port_pause(mdev,
1147                                   pauseparam->rx_pause ? 1 : 0,
1148                                   pauseparam->tx_pause ? 1 : 0);
1149         if (err) {
1150                 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1151                            __func__, err);
1152         }
1153
1154         return err;
1155 }
1156
1157 static int mlx5e_get_ts_info(struct net_device *dev,
1158                              struct ethtool_ts_info *info)
1159 {
1160         struct mlx5e_priv *priv = netdev_priv(dev);
1161         int ret;
1162
1163         ret = ethtool_op_get_ts_info(dev, info);
1164         if (ret)
1165                 return ret;
1166
1167         info->phc_index = priv->tstamp.ptp ?
1168                           ptp_clock_index(priv->tstamp.ptp) : -1;
1169
1170         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1171                 return 0;
1172
1173         info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1174                                  SOF_TIMESTAMPING_RX_HARDWARE |
1175                                  SOF_TIMESTAMPING_RAW_HARDWARE;
1176
1177         info->tx_types = (BIT(1) << HWTSTAMP_TX_OFF) |
1178                          (BIT(1) << HWTSTAMP_TX_ON);
1179
1180         info->rx_filters = (BIT(1) << HWTSTAMP_FILTER_NONE) |
1181                            (BIT(1) << HWTSTAMP_FILTER_ALL);
1182
1183         return 0;
1184 }
1185
1186 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1187 {
1188         __u32 ret = 0;
1189
1190         if (MLX5_CAP_GEN(mdev, wol_g))
1191                 ret |= WAKE_MAGIC;
1192
1193         if (MLX5_CAP_GEN(mdev, wol_s))
1194                 ret |= WAKE_MAGICSECURE;
1195
1196         if (MLX5_CAP_GEN(mdev, wol_a))
1197                 ret |= WAKE_ARP;
1198
1199         if (MLX5_CAP_GEN(mdev, wol_b))
1200                 ret |= WAKE_BCAST;
1201
1202         if (MLX5_CAP_GEN(mdev, wol_m))
1203                 ret |= WAKE_MCAST;
1204
1205         if (MLX5_CAP_GEN(mdev, wol_u))
1206                 ret |= WAKE_UCAST;
1207
1208         if (MLX5_CAP_GEN(mdev, wol_p))
1209                 ret |= WAKE_PHY;
1210
1211         return ret;
1212 }
1213
1214 static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1215 {
1216         __u32 ret = 0;
1217
1218         if (mode & MLX5_WOL_MAGIC)
1219                 ret |= WAKE_MAGIC;
1220
1221         if (mode & MLX5_WOL_SECURED_MAGIC)
1222                 ret |= WAKE_MAGICSECURE;
1223
1224         if (mode & MLX5_WOL_ARP)
1225                 ret |= WAKE_ARP;
1226
1227         if (mode & MLX5_WOL_BROADCAST)
1228                 ret |= WAKE_BCAST;
1229
1230         if (mode & MLX5_WOL_MULTICAST)
1231                 ret |= WAKE_MCAST;
1232
1233         if (mode & MLX5_WOL_UNICAST)
1234                 ret |= WAKE_UCAST;
1235
1236         if (mode & MLX5_WOL_PHY_ACTIVITY)
1237                 ret |= WAKE_PHY;
1238
1239         return ret;
1240 }
1241
1242 static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1243 {
1244         u8 ret = 0;
1245
1246         if (mode & WAKE_MAGIC)
1247                 ret |= MLX5_WOL_MAGIC;
1248
1249         if (mode & WAKE_MAGICSECURE)
1250                 ret |= MLX5_WOL_SECURED_MAGIC;
1251
1252         if (mode & WAKE_ARP)
1253                 ret |= MLX5_WOL_ARP;
1254
1255         if (mode & WAKE_BCAST)
1256                 ret |= MLX5_WOL_BROADCAST;
1257
1258         if (mode & WAKE_MCAST)
1259                 ret |= MLX5_WOL_MULTICAST;
1260
1261         if (mode & WAKE_UCAST)
1262                 ret |= MLX5_WOL_UNICAST;
1263
1264         if (mode & WAKE_PHY)
1265                 ret |= MLX5_WOL_PHY_ACTIVITY;
1266
1267         return ret;
1268 }
1269
1270 static void mlx5e_get_wol(struct net_device *netdev,
1271                           struct ethtool_wolinfo *wol)
1272 {
1273         struct mlx5e_priv *priv = netdev_priv(netdev);
1274         struct mlx5_core_dev *mdev = priv->mdev;
1275         u8 mlx5_wol_mode;
1276         int err;
1277
1278         memset(wol, 0, sizeof(*wol));
1279
1280         wol->supported = mlx5e_get_wol_supported(mdev);
1281         if (!wol->supported)
1282                 return;
1283
1284         err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1285         if (err)
1286                 return;
1287
1288         wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1289 }
1290
1291 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1292 {
1293         struct mlx5e_priv *priv = netdev_priv(netdev);
1294         struct mlx5_core_dev *mdev = priv->mdev;
1295         __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1296         u32 mlx5_wol_mode;
1297
1298         if (!wol_supported)
1299                 return -ENOTSUPP;
1300
1301         if (wol->wolopts & ~wol_supported)
1302                 return -EINVAL;
1303
1304         mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1305
1306         return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1307 }
1308
1309 static int mlx5e_set_phys_id(struct net_device *dev,
1310                              enum ethtool_phys_id_state state)
1311 {
1312         struct mlx5e_priv *priv = netdev_priv(dev);
1313         struct mlx5_core_dev *mdev = priv->mdev;
1314         u16 beacon_duration;
1315
1316         if (!MLX5_CAP_GEN(mdev, beacon_led))
1317                 return -EOPNOTSUPP;
1318
1319         switch (state) {
1320         case ETHTOOL_ID_ACTIVE:
1321                 beacon_duration = MLX5_BEACON_DURATION_INF;
1322                 break;
1323         case ETHTOOL_ID_INACTIVE:
1324                 beacon_duration = MLX5_BEACON_DURATION_OFF;
1325                 break;
1326         default:
1327                 return -EOPNOTSUPP;
1328         }
1329
1330         return mlx5_set_port_beacon(mdev, beacon_duration);
1331 }
1332
1333 static int mlx5e_get_module_info(struct net_device *netdev,
1334                                  struct ethtool_modinfo *modinfo)
1335 {
1336         struct mlx5e_priv *priv = netdev_priv(netdev);
1337         struct mlx5_core_dev *dev = priv->mdev;
1338         int size_read = 0;
1339         u8 data[4];
1340
1341         size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1342         if (size_read < 2)
1343                 return -EIO;
1344
1345         /* data[0] = identifier byte */
1346         switch (data[0]) {
1347         case MLX5_MODULE_ID_QSFP:
1348                 modinfo->type       = ETH_MODULE_SFF_8436;
1349                 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1350                 break;
1351         case MLX5_MODULE_ID_QSFP_PLUS:
1352         case MLX5_MODULE_ID_QSFP28:
1353                 /* data[1] = revision id */
1354                 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1355                         modinfo->type       = ETH_MODULE_SFF_8636;
1356                         modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1357                 } else {
1358                         modinfo->type       = ETH_MODULE_SFF_8436;
1359                         modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1360                 }
1361                 break;
1362         case MLX5_MODULE_ID_SFP:
1363                 modinfo->type       = ETH_MODULE_SFF_8472;
1364                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1365                 break;
1366         default:
1367                 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1368                            __func__, data[0]);
1369                 return -EINVAL;
1370         }
1371
1372         return 0;
1373 }
1374
1375 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1376                                    struct ethtool_eeprom *ee,
1377                                    u8 *data)
1378 {
1379         struct mlx5e_priv *priv = netdev_priv(netdev);
1380         struct mlx5_core_dev *mdev = priv->mdev;
1381         int offset = ee->offset;
1382         int size_read;
1383         int i = 0;
1384
1385         if (!ee->len)
1386                 return -EINVAL;
1387
1388         memset(data, 0, ee->len);
1389
1390         while (i < ee->len) {
1391                 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1392                                                      data + i);
1393
1394                 if (!size_read)
1395                         /* Done reading */
1396                         return 0;
1397
1398                 if (size_read < 0) {
1399                         netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1400                                    __func__, size_read);
1401                         return 0;
1402                 }
1403
1404                 i += size_read;
1405                 offset += size_read;
1406         }
1407
1408         return 0;
1409 }
1410
1411 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1412
1413 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1414 {
1415         struct mlx5e_priv *priv = netdev_priv(netdev);
1416         struct mlx5_core_dev *mdev = priv->mdev;
1417         bool rx_mode_changed;
1418         u8 rx_cq_period_mode;
1419         int err = 0;
1420         bool reset;
1421
1422         rx_cq_period_mode = enable ?
1423                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1424                 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1425         rx_mode_changed = rx_cq_period_mode != priv->params.rx_cq_period_mode;
1426
1427         if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1428             !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1429                 return -ENOTSUPP;
1430
1431         if (!rx_mode_changed)
1432                 return 0;
1433
1434         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
1435         if (reset)
1436                 mlx5e_close_locked(netdev);
1437
1438         mlx5e_set_rx_cq_mode_params(&priv->params, rx_cq_period_mode);
1439
1440         if (reset)
1441                 err = mlx5e_open_locked(netdev);
1442
1443         return err;
1444 }
1445
1446 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1447                                      bool enable)
1448 {
1449         struct mlx5e_priv *priv = netdev_priv(netdev);
1450         struct mlx5_core_dev *mdev = priv->mdev;
1451         int err = 0;
1452         bool reset;
1453
1454         if (!MLX5_CAP_GEN(mdev, cqe_compression))
1455                 return -ENOTSUPP;
1456
1457         if (enable && priv->tstamp.hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
1458                 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1459                 return -EINVAL;
1460         }
1461
1462         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
1463
1464         if (reset)
1465                 mlx5e_close_locked(netdev);
1466
1467         MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, enable);
1468         priv->params.rx_cqe_compress_def = enable;
1469
1470         if (reset)
1471                 err = mlx5e_open_locked(netdev);
1472         return err;
1473 }
1474
1475 static int mlx5e_handle_pflag(struct net_device *netdev,
1476                               u32 wanted_flags,
1477                               enum mlx5e_priv_flag flag,
1478                               mlx5e_pflag_handler pflag_handler)
1479 {
1480         struct mlx5e_priv *priv = netdev_priv(netdev);
1481         bool enable = !!(wanted_flags & flag);
1482         u32 changes = wanted_flags ^ priv->params.pflags;
1483         int err;
1484
1485         if (!(changes & flag))
1486                 return 0;
1487
1488         err = pflag_handler(netdev, enable);
1489         if (err) {
1490                 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1491                            enable ? "Enable" : "Disable", flag, err);
1492                 return err;
1493         }
1494
1495         MLX5E_SET_PFLAG(priv, flag, enable);
1496         return 0;
1497 }
1498
1499 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1500 {
1501         struct mlx5e_priv *priv = netdev_priv(netdev);
1502         int err;
1503
1504         mutex_lock(&priv->state_lock);
1505         err = mlx5e_handle_pflag(netdev, pflags,
1506                                  MLX5E_PFLAG_RX_CQE_BASED_MODER,
1507                                  set_pflag_rx_cqe_based_moder);
1508         if (err)
1509                 goto out;
1510
1511         err = mlx5e_handle_pflag(netdev, pflags,
1512                                  MLX5E_PFLAG_RX_CQE_COMPRESS,
1513                                  set_pflag_rx_cqe_compress);
1514
1515 out:
1516         mutex_unlock(&priv->state_lock);
1517         return err;
1518 }
1519
1520 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1521 {
1522         struct mlx5e_priv *priv = netdev_priv(netdev);
1523
1524         return priv->params.pflags;
1525 }
1526
1527 static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1528 {
1529         int err = 0;
1530         struct mlx5e_priv *priv = netdev_priv(dev);
1531
1532         switch (cmd->cmd) {
1533         case ETHTOOL_SRXCLSRLINS:
1534                 err = mlx5e_ethtool_flow_replace(priv, &cmd->fs);
1535                 break;
1536         case ETHTOOL_SRXCLSRLDEL:
1537                 err = mlx5e_ethtool_flow_remove(priv, cmd->fs.location);
1538                 break;
1539         default:
1540                 err = -EOPNOTSUPP;
1541                 break;
1542         }
1543
1544         return err;
1545 }
1546
1547 const struct ethtool_ops mlx5e_ethtool_ops = {
1548         .get_drvinfo       = mlx5e_get_drvinfo,
1549         .get_link          = ethtool_op_get_link,
1550         .get_strings       = mlx5e_get_strings,
1551         .get_sset_count    = mlx5e_get_sset_count,
1552         .get_ethtool_stats = mlx5e_get_ethtool_stats,
1553         .get_ringparam     = mlx5e_get_ringparam,
1554         .set_ringparam     = mlx5e_set_ringparam,
1555         .get_channels      = mlx5e_get_channels,
1556         .set_channels      = mlx5e_set_channels,
1557         .get_coalesce      = mlx5e_get_coalesce,
1558         .set_coalesce      = mlx5e_set_coalesce,
1559         .get_link_ksettings  = mlx5e_get_link_ksettings,
1560         .set_link_ksettings  = mlx5e_set_link_ksettings,
1561         .get_rxfh_key_size   = mlx5e_get_rxfh_key_size,
1562         .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1563         .get_rxfh          = mlx5e_get_rxfh,
1564         .set_rxfh          = mlx5e_set_rxfh,
1565         .get_rxnfc         = mlx5e_get_rxnfc,
1566         .set_rxnfc         = mlx5e_set_rxnfc,
1567         .get_tunable       = mlx5e_get_tunable,
1568         .set_tunable       = mlx5e_set_tunable,
1569         .get_pauseparam    = mlx5e_get_pauseparam,
1570         .set_pauseparam    = mlx5e_set_pauseparam,
1571         .get_ts_info       = mlx5e_get_ts_info,
1572         .set_phys_id       = mlx5e_set_phys_id,
1573         .get_wol           = mlx5e_get_wol,
1574         .set_wol           = mlx5e_set_wol,
1575         .get_module_info   = mlx5e_get_module_info,
1576         .get_module_eeprom = mlx5e_get_module_eeprom,
1577         .get_priv_flags    = mlx5e_get_priv_flags,
1578         .set_priv_flags    = mlx5e_set_priv_flags,
1579         .self_test         = mlx5e_self_test,
1580 };