2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 static void mlx5e_get_drvinfo(struct net_device *dev,
36 struct ethtool_drvinfo *drvinfo)
38 struct mlx5e_priv *priv = netdev_priv(dev);
39 struct mlx5_core_dev *mdev = priv->mdev;
41 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
42 strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")",
43 sizeof(drvinfo->version));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev));
47 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
48 sizeof(drvinfo->bus_info));
51 struct ptys2ethtool_config {
52 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
53 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
57 static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
59 #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
61 struct ptys2ethtool_config *cfg; \
62 const unsigned int modes[] = { __VA_ARGS__ }; \
64 cfg = &ptys2ethtool_table[reg_]; \
65 cfg->speed = speed_; \
66 bitmap_zero(cfg->supported, \
67 __ETHTOOL_LINK_MODE_MASK_NBITS); \
68 bitmap_zero(cfg->advertised, \
69 __ETHTOOL_LINK_MODE_MASK_NBITS); \
70 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
71 __set_bit(modes[i], cfg->supported); \
72 __set_bit(modes[i], cfg->advertised); \
76 void mlx5e_build_ptys2ethtool_map(void)
78 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000,
79 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
80 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000,
81 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
82 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000,
83 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
84 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000,
85 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
86 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000,
87 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
88 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000,
89 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
90 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000,
91 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
92 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000,
93 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
94 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000,
95 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
96 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000,
97 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
98 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000,
99 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
100 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000,
101 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
102 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000,
103 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
104 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000,
105 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
106 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000,
107 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
108 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000,
109 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
110 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000,
111 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
112 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000,
113 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
114 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000,
115 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
116 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000,
117 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
118 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000,
119 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
120 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000,
121 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
122 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000,
123 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
124 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000,
125 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
126 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000,
127 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
130 static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
132 struct mlx5_core_dev *mdev = priv->mdev;
137 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
139 return err ? 0 : pfc_en_tx | pfc_en_rx;
142 static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
144 struct mlx5_core_dev *mdev = priv->mdev;
149 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
151 return err ? false : rx_pause | tx_pause;
154 #define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
155 #define MLX5E_NUM_RQ_STATS(priv) \
156 (NUM_RQ_STATS * priv->params.num_channels * \
157 test_bit(MLX5E_STATE_OPENED, &priv->state))
158 #define MLX5E_NUM_SQ_STATS(priv) \
159 (NUM_SQ_STATS * priv->params.num_channels * priv->params.num_tc * \
160 test_bit(MLX5E_STATE_OPENED, &priv->state))
161 #define MLX5E_NUM_PFC_COUNTERS(priv) \
162 ((mlx5e_query_global_pause_combined(priv) + hweight8(mlx5e_query_pfc_combined(priv))) * \
163 NUM_PPORT_PER_PRIO_PFC_COUNTERS)
165 static int mlx5e_get_sset_count(struct net_device *dev, int sset)
167 struct mlx5e_priv *priv = netdev_priv(dev);
171 return NUM_SW_COUNTERS +
172 MLX5E_NUM_Q_CNTRS(priv) +
173 NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS +
174 MLX5E_NUM_RQ_STATS(priv) +
175 MLX5E_NUM_SQ_STATS(priv) +
176 MLX5E_NUM_PFC_COUNTERS(priv) +
177 ARRAY_SIZE(mlx5e_pme_status_desc) +
178 ARRAY_SIZE(mlx5e_pme_error_desc);
180 case ETH_SS_PRIV_FLAGS:
181 return ARRAY_SIZE(mlx5e_priv_flags);
183 return mlx5e_self_test_num(priv);
190 static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data)
192 int i, j, tc, prio, idx = 0;
193 unsigned long pfc_combined;
196 for (i = 0; i < NUM_SW_COUNTERS; i++)
197 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
200 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
201 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].format);
204 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
205 strcpy(data + (idx++) * ETH_GSTRING_LEN,
206 vport_stats_desc[i].format);
209 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
210 strcpy(data + (idx++) * ETH_GSTRING_LEN,
211 pport_802_3_stats_desc[i].format);
213 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
214 strcpy(data + (idx++) * ETH_GSTRING_LEN,
215 pport_2863_stats_desc[i].format);
217 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
218 strcpy(data + (idx++) * ETH_GSTRING_LEN,
219 pport_2819_stats_desc[i].format);
221 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
222 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
223 sprintf(data + (idx++) * ETH_GSTRING_LEN,
224 pport_per_prio_traffic_stats_desc[i].format, prio);
227 pfc_combined = mlx5e_query_pfc_combined(priv);
228 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
229 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
230 char pfc_string[ETH_GSTRING_LEN];
232 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
233 sprintf(data + (idx++) * ETH_GSTRING_LEN,
234 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
238 if (mlx5e_query_global_pause_combined(priv)) {
239 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
240 sprintf(data + (idx++) * ETH_GSTRING_LEN,
241 pport_per_prio_pfc_stats_desc[i].format, "global");
245 /* port module event counters */
246 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
247 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
249 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
250 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
252 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
255 /* per channel counters */
256 for (i = 0; i < priv->params.num_channels; i++)
257 for (j = 0; j < NUM_RQ_STATS; j++)
258 sprintf(data + (idx++) * ETH_GSTRING_LEN,
259 rq_stats_desc[j].format, i);
261 for (tc = 0; tc < priv->params.num_tc; tc++)
262 for (i = 0; i < priv->params.num_channels; i++)
263 for (j = 0; j < NUM_SQ_STATS; j++)
264 sprintf(data + (idx++) * ETH_GSTRING_LEN,
265 sq_stats_desc[j].format,
266 priv->channeltc_to_txq_map[i][tc]);
269 static void mlx5e_get_strings(struct net_device *dev,
270 uint32_t stringset, uint8_t *data)
272 struct mlx5e_priv *priv = netdev_priv(dev);
276 case ETH_SS_PRIV_FLAGS:
277 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
278 strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
282 for (i = 0; i < mlx5e_self_test_num(priv); i++)
283 strcpy(data + i * ETH_GSTRING_LEN,
284 mlx5e_self_tests[i]);
288 mlx5e_fill_stats_strings(priv, data);
293 static void mlx5e_get_ethtool_stats(struct net_device *dev,
294 struct ethtool_stats *stats, u64 *data)
296 struct mlx5e_priv *priv = netdev_priv(dev);
297 struct mlx5_priv *mlx5_priv;
298 int i, j, tc, prio, idx = 0;
299 unsigned long pfc_combined;
304 mutex_lock(&priv->state_lock);
305 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
306 mlx5e_update_stats(priv);
307 mutex_unlock(&priv->state_lock);
309 for (i = 0; i < NUM_SW_COUNTERS; i++)
310 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
313 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
314 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
317 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
318 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
319 vport_stats_desc, i);
321 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
322 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
323 pport_802_3_stats_desc, i);
325 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
326 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
327 pport_2863_stats_desc, i);
329 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
330 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
331 pport_2819_stats_desc, i);
333 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
334 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
335 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
336 pport_per_prio_traffic_stats_desc, i);
339 pfc_combined = mlx5e_query_pfc_combined(priv);
340 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
341 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
342 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
343 pport_per_prio_pfc_stats_desc, i);
347 if (mlx5e_query_global_pause_combined(priv)) {
348 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
349 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
350 pport_per_prio_pfc_stats_desc, i);
354 /* port module event counters */
355 mlx5_priv = &priv->mdev->priv;
356 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
357 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
358 mlx5e_pme_status_desc, i);
360 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
361 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
362 mlx5e_pme_error_desc, i);
364 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
367 /* per channel counters */
368 for (i = 0; i < priv->params.num_channels; i++)
369 for (j = 0; j < NUM_RQ_STATS; j++)
371 MLX5E_READ_CTR64_CPU(&priv->channel[i]->rq.stats,
374 for (tc = 0; tc < priv->params.num_tc; tc++)
375 for (i = 0; i < priv->params.num_channels; i++)
376 for (j = 0; j < NUM_SQ_STATS; j++)
377 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->channel[i]->sq[tc].stats,
381 static u32 mlx5e_rx_wqes_to_packets(struct mlx5e_priv *priv, int rq_wq_type,
389 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
392 stride_size = 1 << priv->params.mpwqe_log_stride_sz;
393 num_strides = 1 << priv->params.mpwqe_log_num_strides;
394 wqe_size = stride_size * num_strides;
396 packets_per_wqe = wqe_size /
397 ALIGN(ETH_DATA_LEN, stride_size);
398 return (1 << (order_base_2(num_wqe * packets_per_wqe) - 1));
401 static u32 mlx5e_packets_to_rx_wqes(struct mlx5e_priv *priv, int rq_wq_type,
410 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
413 stride_size = 1 << priv->params.mpwqe_log_stride_sz;
414 num_strides = 1 << priv->params.mpwqe_log_num_strides;
415 wqe_size = stride_size * num_strides;
417 num_packets = (1 << order_base_2(num_packets));
419 packets_per_wqe = wqe_size /
420 ALIGN(ETH_DATA_LEN, stride_size);
421 num_wqes = DIV_ROUND_UP(num_packets, packets_per_wqe);
422 return 1 << (order_base_2(num_wqes));
425 static void mlx5e_get_ringparam(struct net_device *dev,
426 struct ethtool_ringparam *param)
428 struct mlx5e_priv *priv = netdev_priv(dev);
429 int rq_wq_type = priv->params.rq_wq_type;
431 param->rx_max_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
432 1 << mlx5_max_log_rq_size(rq_wq_type));
433 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
434 param->rx_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
435 1 << priv->params.log_rq_size);
436 param->tx_pending = 1 << priv->params.log_sq_size;
439 static int mlx5e_set_ringparam(struct net_device *dev,
440 struct ethtool_ringparam *param)
442 struct mlx5e_priv *priv = netdev_priv(dev);
444 int rq_wq_type = priv->params.rq_wq_type;
454 if (param->rx_jumbo_pending) {
455 netdev_info(dev, "%s: rx_jumbo_pending not supported\n",
459 if (param->rx_mini_pending) {
460 netdev_info(dev, "%s: rx_mini_pending not supported\n",
465 min_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
466 1 << mlx5_min_log_rq_size(rq_wq_type));
467 max_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
468 1 << mlx5_max_log_rq_size(rq_wq_type));
469 rx_pending_wqes = mlx5e_packets_to_rx_wqes(priv, rq_wq_type,
472 if (param->rx_pending < min_rq_size) {
473 netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n",
474 __func__, param->rx_pending,
478 if (param->rx_pending > max_rq_size) {
479 netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n",
480 __func__, param->rx_pending,
485 num_mtts = MLX5E_REQUIRED_MTTS(rx_pending_wqes);
486 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
487 !MLX5E_VALID_NUM_MTTS(num_mtts)) {
488 netdev_info(dev, "%s: rx_pending (%d) request can't be satisfied, try to reduce.\n",
489 __func__, param->rx_pending);
493 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
494 netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n",
495 __func__, param->tx_pending,
496 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
499 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
500 netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n",
501 __func__, param->tx_pending,
502 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
506 log_rq_size = order_base_2(rx_pending_wqes);
507 log_sq_size = order_base_2(param->tx_pending);
508 min_rx_wqes = mlx5_min_rx_wqes(rq_wq_type, rx_pending_wqes);
510 if (log_rq_size == priv->params.log_rq_size &&
511 log_sq_size == priv->params.log_sq_size &&
512 min_rx_wqes == priv->params.min_rx_wqes)
515 mutex_lock(&priv->state_lock);
517 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
519 mlx5e_close_locked(dev);
521 priv->params.log_rq_size = log_rq_size;
522 priv->params.log_sq_size = log_sq_size;
523 priv->params.min_rx_wqes = min_rx_wqes;
526 err = mlx5e_open_locked(dev);
528 mutex_unlock(&priv->state_lock);
533 static void mlx5e_get_channels(struct net_device *dev,
534 struct ethtool_channels *ch)
536 struct mlx5e_priv *priv = netdev_priv(dev);
538 ch->max_combined = mlx5e_get_max_num_channels(priv->mdev);
539 ch->combined_count = priv->params.num_channels;
542 static int mlx5e_set_channels(struct net_device *dev,
543 struct ethtool_channels *ch)
545 struct mlx5e_priv *priv = netdev_priv(dev);
546 unsigned int count = ch->combined_count;
552 netdev_info(dev, "%s: combined_count=0 not supported\n",
557 if (priv->params.num_channels == count)
560 mutex_lock(&priv->state_lock);
562 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
564 mlx5e_close_locked(dev);
566 arfs_enabled = dev->features & NETIF_F_NTUPLE;
568 mlx5e_arfs_disable(priv);
570 priv->params.num_channels = count;
571 mlx5e_build_default_indir_rqt(priv->mdev, priv->params.indirection_rqt,
572 MLX5E_INDIR_RQT_SIZE, count);
575 err = mlx5e_open_locked(dev);
580 err = mlx5e_arfs_enable(priv);
582 netdev_err(dev, "%s: mlx5e_arfs_enable failed: %d\n",
587 mutex_unlock(&priv->state_lock);
592 static int mlx5e_get_coalesce(struct net_device *netdev,
593 struct ethtool_coalesce *coal)
595 struct mlx5e_priv *priv = netdev_priv(netdev);
597 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
600 coal->rx_coalesce_usecs = priv->params.rx_cq_moderation.usec;
601 coal->rx_max_coalesced_frames = priv->params.rx_cq_moderation.pkts;
602 coal->tx_coalesce_usecs = priv->params.tx_cq_moderation.usec;
603 coal->tx_max_coalesced_frames = priv->params.tx_cq_moderation.pkts;
604 coal->use_adaptive_rx_coalesce = priv->params.rx_am_enabled;
609 static int mlx5e_set_coalesce(struct net_device *netdev,
610 struct ethtool_coalesce *coal)
612 struct mlx5e_priv *priv = netdev_priv(netdev);
613 struct mlx5_core_dev *mdev = priv->mdev;
614 struct mlx5e_channel *c;
616 !!coal->use_adaptive_rx_coalesce != priv->params.rx_am_enabled;
622 if (!MLX5_CAP_GEN(mdev, cq_moderation))
625 mutex_lock(&priv->state_lock);
627 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
628 if (was_opened && restart) {
629 mlx5e_close_locked(netdev);
630 priv->params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce;
633 priv->params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
634 priv->params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
635 priv->params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
636 priv->params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
638 if (!was_opened || restart)
641 for (i = 0; i < priv->params.num_channels; ++i) {
642 c = priv->channel[i];
644 for (tc = 0; tc < c->num_tc; tc++) {
645 mlx5_core_modify_cq_moderation(mdev,
647 coal->tx_coalesce_usecs,
648 coal->tx_max_coalesced_frames);
651 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
652 coal->rx_coalesce_usecs,
653 coal->rx_max_coalesced_frames);
657 if (was_opened && restart)
658 err = mlx5e_open_locked(netdev);
660 mutex_unlock(&priv->state_lock);
664 static void ptys2ethtool_supported_link(unsigned long *supported_modes,
667 unsigned long proto_cap = eth_proto_cap;
670 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
671 bitmap_or(supported_modes, supported_modes,
672 ptys2ethtool_table[proto].supported,
673 __ETHTOOL_LINK_MODE_MASK_NBITS);
676 static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
679 unsigned long proto_cap = eth_proto_cap;
682 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
683 bitmap_or(advertising_modes, advertising_modes,
684 ptys2ethtool_table[proto].advertised,
685 __ETHTOOL_LINK_MODE_MASK_NBITS);
688 static void ptys2ethtool_supported_port(struct ethtool_link_ksettings *link_ksettings,
691 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
692 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
693 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
694 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
695 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
696 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
697 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, FIBRE);
700 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
701 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
702 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
703 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
704 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
705 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Backplane);
709 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
716 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
720 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
721 if (proto_cap & MLX5E_PROT_MASK(i))
722 max_speed = max(max_speed, ptys2ethtool_table[i].speed);
728 static void get_speed_duplex(struct net_device *netdev,
730 struct ethtool_link_ksettings *link_ksettings)
733 u32 speed = SPEED_UNKNOWN;
734 u8 duplex = DUPLEX_UNKNOWN;
736 if (!netif_carrier_ok(netdev))
739 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
740 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
741 speed = ptys2ethtool_table[i].speed;
742 duplex = DUPLEX_FULL;
747 link_ksettings->base.speed = speed;
748 link_ksettings->base.duplex = duplex;
751 static void get_supported(u32 eth_proto_cap,
752 struct ethtool_link_ksettings *link_ksettings)
754 unsigned long *supported = link_ksettings->link_modes.supported;
756 ptys2ethtool_supported_port(link_ksettings, eth_proto_cap);
757 ptys2ethtool_supported_link(supported, eth_proto_cap);
758 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
759 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Asym_Pause);
762 static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
764 struct ethtool_link_ksettings *link_ksettings)
766 unsigned long *advertising = link_ksettings->link_modes.advertising;
768 ptys2ethtool_adver_link(advertising, eth_proto_cap);
770 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
771 if (tx_pause ^ rx_pause)
772 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
775 static u8 get_connector_port(u32 eth_proto)
777 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
778 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
779 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
780 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
784 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
785 | MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
786 | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
790 if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
791 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
792 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
793 | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
800 static void get_lp_advertising(u32 eth_proto_lp,
801 struct ethtool_link_ksettings *link_ksettings)
803 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
805 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
808 static int mlx5e_get_link_ksettings(struct net_device *netdev,
809 struct ethtool_link_ksettings *link_ksettings)
811 struct mlx5e_priv *priv = netdev_priv(netdev);
812 struct mlx5_core_dev *mdev = priv->mdev;
813 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
822 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
824 netdev_err(netdev, "%s: query port ptys failed: %d\n",
829 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
830 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
831 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
832 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
833 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
834 an_status = MLX5_GET(ptys_reg, out, an_status);
836 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
837 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
839 get_supported(eth_proto_cap, link_ksettings);
840 get_advertising(eth_proto_admin, 0, 0, link_ksettings);
841 get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
843 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
845 link_ksettings->base.port = get_connector_port(eth_proto_oper);
846 get_lp_advertising(eth_proto_lp, link_ksettings);
848 if (an_status == MLX5_AN_COMPLETE)
849 ethtool_link_ksettings_add_link_mode(link_ksettings,
850 lp_advertising, Autoneg);
852 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
854 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
856 if (!an_disable_admin)
857 ethtool_link_ksettings_add_link_mode(link_ksettings,
858 advertising, Autoneg);
864 static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
866 u32 i, ptys_modes = 0;
868 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
869 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
871 __ETHTOOL_LINK_MODE_MASK_NBITS))
872 ptys_modes |= MLX5E_PROT_MASK(i);
878 static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
880 u32 i, speed_links = 0;
882 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
883 if (ptys2ethtool_table[i].speed == speed)
884 speed_links |= MLX5E_PROT_MASK(i);
890 static int mlx5e_set_link_ksettings(struct net_device *netdev,
891 const struct ethtool_link_ksettings *link_ksettings)
893 struct mlx5e_priv *priv = netdev_priv(netdev);
894 struct mlx5_core_dev *mdev = priv->mdev;
895 u32 eth_proto_cap, eth_proto_admin;
896 bool an_changes = false;
905 speed = link_ksettings->base.speed;
907 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
908 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
909 mlx5e_ethtool2ptys_speed_link(speed);
911 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
913 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
918 link_modes = link_modes & eth_proto_cap;
920 netdev_err(netdev, "%s: Not supported link mode(s) requested",
926 err = mlx5_query_port_proto_admin(mdev, ð_proto_admin, MLX5_PTYS_EN);
928 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
933 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
934 &an_disable_cap, &an_disable_admin);
936 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
937 an_changes = ((!an_disable && an_disable_admin) ||
938 (an_disable && !an_disable_admin));
940 if (!an_changes && link_modes == eth_proto_admin)
943 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
944 mlx5_toggle_port_link(mdev);
950 static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
952 struct mlx5e_priv *priv = netdev_priv(netdev);
954 return sizeof(priv->params.toeplitz_hash_key);
957 static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
959 return MLX5E_INDIR_RQT_SIZE;
962 static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
965 struct mlx5e_priv *priv = netdev_priv(netdev);
968 memcpy(indir, priv->params.indirection_rqt,
969 sizeof(priv->params.indirection_rqt));
972 memcpy(key, priv->params.toeplitz_hash_key,
973 sizeof(priv->params.toeplitz_hash_key));
976 *hfunc = priv->params.rss_hfunc;
981 static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
983 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
984 struct mlx5_core_dev *mdev = priv->mdev;
985 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
988 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
990 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
991 memset(tirc, 0, ctxlen);
992 mlx5e_build_indir_tir_ctx_hash(priv, tirc, tt);
993 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
997 static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
998 const u8 *key, const u8 hfunc)
1000 struct mlx5e_priv *priv = netdev_priv(dev);
1001 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1002 bool hash_changed = false;
1005 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1006 (hfunc != ETH_RSS_HASH_XOR) &&
1007 (hfunc != ETH_RSS_HASH_TOP))
1010 in = mlx5_vzalloc(inlen);
1014 mutex_lock(&priv->state_lock);
1017 u32 rqtn = priv->indir_rqt.rqtn;
1019 memcpy(priv->params.indirection_rqt, indir,
1020 sizeof(priv->params.indirection_rqt));
1021 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1024 if (hfunc != ETH_RSS_HASH_NO_CHANGE &&
1025 hfunc != priv->params.rss_hfunc) {
1026 priv->params.rss_hfunc = hfunc;
1027 hash_changed = true;
1031 memcpy(priv->params.toeplitz_hash_key, key,
1032 sizeof(priv->params.toeplitz_hash_key));
1033 hash_changed = hash_changed ||
1034 priv->params.rss_hfunc == ETH_RSS_HASH_TOP;
1038 mlx5e_modify_tirs_hash(priv, in, inlen);
1040 mutex_unlock(&priv->state_lock);
1047 static int mlx5e_get_rxnfc(struct net_device *netdev,
1048 struct ethtool_rxnfc *info, u32 *rule_locs)
1050 struct mlx5e_priv *priv = netdev_priv(netdev);
1053 switch (info->cmd) {
1054 case ETHTOOL_GRXRINGS:
1055 info->data = priv->params.num_channels;
1057 case ETHTOOL_GRXCLSRLCNT:
1058 info->rule_cnt = priv->fs.ethtool.tot_num_rules;
1060 case ETHTOOL_GRXCLSRULE:
1061 err = mlx5e_ethtool_get_flow(priv, info, info->fs.location);
1063 case ETHTOOL_GRXCLSRLALL:
1064 err = mlx5e_ethtool_get_all_flows(priv, info, rule_locs);
1074 static int mlx5e_get_tunable(struct net_device *dev,
1075 const struct ethtool_tunable *tuna,
1078 const struct mlx5e_priv *priv = netdev_priv(dev);
1082 case ETHTOOL_TX_COPYBREAK:
1083 *(u32 *)data = priv->params.tx_max_inline;
1093 static int mlx5e_set_tunable(struct net_device *dev,
1094 const struct ethtool_tunable *tuna,
1097 struct mlx5e_priv *priv = netdev_priv(dev);
1098 struct mlx5_core_dev *mdev = priv->mdev;
1104 case ETHTOOL_TX_COPYBREAK:
1106 if (val > mlx5e_get_max_inline_cap(mdev)) {
1111 mutex_lock(&priv->state_lock);
1113 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1115 mlx5e_close_locked(dev);
1117 priv->params.tx_max_inline = val;
1120 err = mlx5e_open_locked(dev);
1122 mutex_unlock(&priv->state_lock);
1132 static void mlx5e_get_pauseparam(struct net_device *netdev,
1133 struct ethtool_pauseparam *pauseparam)
1135 struct mlx5e_priv *priv = netdev_priv(netdev);
1136 struct mlx5_core_dev *mdev = priv->mdev;
1139 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1140 &pauseparam->tx_pause);
1142 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1147 static int mlx5e_set_pauseparam(struct net_device *netdev,
1148 struct ethtool_pauseparam *pauseparam)
1150 struct mlx5e_priv *priv = netdev_priv(netdev);
1151 struct mlx5_core_dev *mdev = priv->mdev;
1154 if (pauseparam->autoneg)
1157 err = mlx5_set_port_pause(mdev,
1158 pauseparam->rx_pause ? 1 : 0,
1159 pauseparam->tx_pause ? 1 : 0);
1161 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1168 static int mlx5e_get_ts_info(struct net_device *dev,
1169 struct ethtool_ts_info *info)
1171 struct mlx5e_priv *priv = netdev_priv(dev);
1174 ret = ethtool_op_get_ts_info(dev, info);
1178 info->phc_index = priv->tstamp.ptp ?
1179 ptp_clock_index(priv->tstamp.ptp) : -1;
1181 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1184 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1185 SOF_TIMESTAMPING_RX_HARDWARE |
1186 SOF_TIMESTAMPING_RAW_HARDWARE;
1188 info->tx_types = (BIT(1) << HWTSTAMP_TX_OFF) |
1189 (BIT(1) << HWTSTAMP_TX_ON);
1191 info->rx_filters = (BIT(1) << HWTSTAMP_FILTER_NONE) |
1192 (BIT(1) << HWTSTAMP_FILTER_ALL);
1197 static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1201 if (MLX5_CAP_GEN(mdev, wol_g))
1204 if (MLX5_CAP_GEN(mdev, wol_s))
1205 ret |= WAKE_MAGICSECURE;
1207 if (MLX5_CAP_GEN(mdev, wol_a))
1210 if (MLX5_CAP_GEN(mdev, wol_b))
1213 if (MLX5_CAP_GEN(mdev, wol_m))
1216 if (MLX5_CAP_GEN(mdev, wol_u))
1219 if (MLX5_CAP_GEN(mdev, wol_p))
1225 static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1229 if (mode & MLX5_WOL_MAGIC)
1232 if (mode & MLX5_WOL_SECURED_MAGIC)
1233 ret |= WAKE_MAGICSECURE;
1235 if (mode & MLX5_WOL_ARP)
1238 if (mode & MLX5_WOL_BROADCAST)
1241 if (mode & MLX5_WOL_MULTICAST)
1244 if (mode & MLX5_WOL_UNICAST)
1247 if (mode & MLX5_WOL_PHY_ACTIVITY)
1253 static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1257 if (mode & WAKE_MAGIC)
1258 ret |= MLX5_WOL_MAGIC;
1260 if (mode & WAKE_MAGICSECURE)
1261 ret |= MLX5_WOL_SECURED_MAGIC;
1263 if (mode & WAKE_ARP)
1264 ret |= MLX5_WOL_ARP;
1266 if (mode & WAKE_BCAST)
1267 ret |= MLX5_WOL_BROADCAST;
1269 if (mode & WAKE_MCAST)
1270 ret |= MLX5_WOL_MULTICAST;
1272 if (mode & WAKE_UCAST)
1273 ret |= MLX5_WOL_UNICAST;
1275 if (mode & WAKE_PHY)
1276 ret |= MLX5_WOL_PHY_ACTIVITY;
1281 static void mlx5e_get_wol(struct net_device *netdev,
1282 struct ethtool_wolinfo *wol)
1284 struct mlx5e_priv *priv = netdev_priv(netdev);
1285 struct mlx5_core_dev *mdev = priv->mdev;
1289 memset(wol, 0, sizeof(*wol));
1291 wol->supported = mlx5e_get_wol_supported(mdev);
1292 if (!wol->supported)
1295 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1299 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1302 static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1304 struct mlx5e_priv *priv = netdev_priv(netdev);
1305 struct mlx5_core_dev *mdev = priv->mdev;
1306 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1312 if (wol->wolopts & ~wol_supported)
1315 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1317 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1320 static int mlx5e_set_phys_id(struct net_device *dev,
1321 enum ethtool_phys_id_state state)
1323 struct mlx5e_priv *priv = netdev_priv(dev);
1324 struct mlx5_core_dev *mdev = priv->mdev;
1325 u16 beacon_duration;
1327 if (!MLX5_CAP_GEN(mdev, beacon_led))
1331 case ETHTOOL_ID_ACTIVE:
1332 beacon_duration = MLX5_BEACON_DURATION_INF;
1334 case ETHTOOL_ID_INACTIVE:
1335 beacon_duration = MLX5_BEACON_DURATION_OFF;
1341 return mlx5_set_port_beacon(mdev, beacon_duration);
1344 static int mlx5e_get_module_info(struct net_device *netdev,
1345 struct ethtool_modinfo *modinfo)
1347 struct mlx5e_priv *priv = netdev_priv(netdev);
1348 struct mlx5_core_dev *dev = priv->mdev;
1352 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1356 /* data[0] = identifier byte */
1358 case MLX5_MODULE_ID_QSFP:
1359 modinfo->type = ETH_MODULE_SFF_8436;
1360 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1362 case MLX5_MODULE_ID_QSFP_PLUS:
1363 case MLX5_MODULE_ID_QSFP28:
1364 /* data[1] = revision id */
1365 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1366 modinfo->type = ETH_MODULE_SFF_8636;
1367 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1369 modinfo->type = ETH_MODULE_SFF_8436;
1370 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1373 case MLX5_MODULE_ID_SFP:
1374 modinfo->type = ETH_MODULE_SFF_8472;
1375 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1378 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1386 static int mlx5e_get_module_eeprom(struct net_device *netdev,
1387 struct ethtool_eeprom *ee,
1390 struct mlx5e_priv *priv = netdev_priv(netdev);
1391 struct mlx5_core_dev *mdev = priv->mdev;
1392 int offset = ee->offset;
1399 memset(data, 0, ee->len);
1401 while (i < ee->len) {
1402 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1409 if (size_read < 0) {
1410 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1411 __func__, size_read);
1416 offset += size_read;
1422 typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1424 static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
1426 struct mlx5e_priv *priv = netdev_priv(netdev);
1427 struct mlx5_core_dev *mdev = priv->mdev;
1428 bool rx_mode_changed;
1429 u8 rx_cq_period_mode;
1433 rx_cq_period_mode = enable ?
1434 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1435 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1436 rx_mode_changed = rx_cq_period_mode != priv->params.rx_cq_period_mode;
1438 if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1439 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
1442 if (!rx_mode_changed)
1445 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
1447 mlx5e_close_locked(netdev);
1449 mlx5e_set_rx_cq_mode_params(&priv->params, rx_cq_period_mode);
1452 err = mlx5e_open_locked(netdev);
1457 static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1460 struct mlx5e_priv *priv = netdev_priv(netdev);
1461 struct mlx5_core_dev *mdev = priv->mdev;
1465 if (!MLX5_CAP_GEN(mdev, cqe_compression))
1468 if (enable && priv->tstamp.hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
1469 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1473 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
1476 mlx5e_close_locked(netdev);
1478 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, enable);
1479 priv->params.rx_cqe_compress_def = enable;
1482 err = mlx5e_open_locked(netdev);
1486 static int mlx5e_handle_pflag(struct net_device *netdev,
1488 enum mlx5e_priv_flag flag,
1489 mlx5e_pflag_handler pflag_handler)
1491 struct mlx5e_priv *priv = netdev_priv(netdev);
1492 bool enable = !!(wanted_flags & flag);
1493 u32 changes = wanted_flags ^ priv->params.pflags;
1496 if (!(changes & flag))
1499 err = pflag_handler(netdev, enable);
1501 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1502 enable ? "Enable" : "Disable", flag, err);
1506 MLX5E_SET_PFLAG(priv, flag, enable);
1510 static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1512 struct mlx5e_priv *priv = netdev_priv(netdev);
1515 mutex_lock(&priv->state_lock);
1516 err = mlx5e_handle_pflag(netdev, pflags,
1517 MLX5E_PFLAG_RX_CQE_BASED_MODER,
1518 set_pflag_rx_cqe_based_moder);
1522 err = mlx5e_handle_pflag(netdev, pflags,
1523 MLX5E_PFLAG_RX_CQE_COMPRESS,
1524 set_pflag_rx_cqe_compress);
1527 mutex_unlock(&priv->state_lock);
1531 static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1533 struct mlx5e_priv *priv = netdev_priv(netdev);
1535 return priv->params.pflags;
1538 static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1541 struct mlx5e_priv *priv = netdev_priv(dev);
1544 case ETHTOOL_SRXCLSRLINS:
1545 err = mlx5e_ethtool_flow_replace(priv, &cmd->fs);
1547 case ETHTOOL_SRXCLSRLDEL:
1548 err = mlx5e_ethtool_flow_remove(priv, cmd->fs.location);
1558 const struct ethtool_ops mlx5e_ethtool_ops = {
1559 .get_drvinfo = mlx5e_get_drvinfo,
1560 .get_link = ethtool_op_get_link,
1561 .get_strings = mlx5e_get_strings,
1562 .get_sset_count = mlx5e_get_sset_count,
1563 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1564 .get_ringparam = mlx5e_get_ringparam,
1565 .set_ringparam = mlx5e_set_ringparam,
1566 .get_channels = mlx5e_get_channels,
1567 .set_channels = mlx5e_set_channels,
1568 .get_coalesce = mlx5e_get_coalesce,
1569 .set_coalesce = mlx5e_set_coalesce,
1570 .get_link_ksettings = mlx5e_get_link_ksettings,
1571 .set_link_ksettings = mlx5e_set_link_ksettings,
1572 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1573 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
1574 .get_rxfh = mlx5e_get_rxfh,
1575 .set_rxfh = mlx5e_set_rxfh,
1576 .get_rxnfc = mlx5e_get_rxnfc,
1577 .set_rxnfc = mlx5e_set_rxnfc,
1578 .get_tunable = mlx5e_get_tunable,
1579 .set_tunable = mlx5e_set_tunable,
1580 .get_pauseparam = mlx5e_get_pauseparam,
1581 .set_pauseparam = mlx5e_set_pauseparam,
1582 .get_ts_info = mlx5e_get_ts_info,
1583 .set_phys_id = mlx5e_set_phys_id,
1584 .get_wol = mlx5e_get_wol,
1585 .set_wol = mlx5e_set_wol,
1586 .get_module_info = mlx5e_get_module_info,
1587 .get_module_eeprom = mlx5e_get_module_eeprom,
1588 .get_priv_flags = mlx5e_get_priv_flags,
1589 .set_priv_flags = mlx5e_set_priv_flags,
1590 .self_test = mlx5e_self_test,