drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/mlx5/flow_table.h>
  34 #include "en.h"
  35
  36 struct mlx5e_rq_param {
  37         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  38         struct mlx5_wq_param       wq;
  39 };
  40
  41 struct mlx5e_sq_param {
  42         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  43         struct mlx5_wq_param       wq;
  44 };
  45
  46 struct mlx5e_cq_param {
  47         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  48         struct mlx5_wq_param       wq;
  49         u16                        eq_ix;
  50 };
  51
  52 struct mlx5e_channel_param {
  53         struct mlx5e_rq_param      rq;
  54         struct mlx5e_sq_param      sq;
  55         struct mlx5e_cq_param      rx_cq;
  56         struct mlx5e_cq_param      tx_cq;
  57 };
  58
  59 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  60 {
  61         struct mlx5_core_dev *mdev = priv->mdev;
  62         u8 port_state;
  63
  64         port_state = mlx5_query_vport_state(mdev,
  65                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT);
  66
  67         if (port_state == VPORT_STATE_UP)
  68                 netif_carrier_on(priv->netdev);
  69         else
  70                 netif_carrier_off(priv->netdev);
  71 }
  72
  73 static void mlx5e_update_carrier_work(struct work_struct *work)
  74 {
  75         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  76                                                update_carrier_work);
  77
  78         mutex_lock(&priv->state_lock);
  79         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  80                 mlx5e_update_carrier(priv);
  81         mutex_unlock(&priv->state_lock);
  82 }
  83
  84 void mlx5e_update_stats(struct mlx5e_priv *priv)
  85 {
  86         struct mlx5_core_dev *mdev = priv->mdev;
  87         struct mlx5e_vport_stats *s = &priv->stats.vport;
  88         struct mlx5e_rq_stats *rq_stats;
  89         struct mlx5e_sq_stats *sq_stats;
  90         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
  91         u32 *out;
  92         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
  93         u64 tx_offload_none;
  94         int i, j;
  95
  96         out = mlx5_vzalloc(outlen);
  97         if (!out)
  98                 return;
  99
 100         /* Collect firts the SW counters and then HW for consistency */
 101         s->tso_packets          = 0;
 102         s->tso_bytes            = 0;
 103         s->tx_queue_stopped     = 0;
 104         s->tx_queue_wake        = 0;
 105         s->tx_queue_dropped     = 0;
 106         tx_offload_none         = 0;
 107         s->lro_packets          = 0;
 108         s->lro_bytes            = 0;
 109         s->rx_csum_none         = 0;
 110         s->rx_wqe_err           = 0;
 111         for (i = 0; i < priv->params.num_channels; i++) {
 112                 rq_stats = &priv->channel[i]->rq.stats;
 113
 114                 s->lro_packets  += rq_stats->lro_packets;
 115                 s->lro_bytes    += rq_stats->lro_bytes;
 116                 s->rx_csum_none += rq_stats->csum_none;
 117                 s->rx_wqe_err   += rq_stats->wqe_err;
 118
 119                 for (j = 0; j < priv->num_tc; j++) {
 120                         sq_stats = &priv->channel[i]->sq[j].stats;
 121
 122                         s->tso_packets          += sq_stats->tso_packets;
 123                         s->tso_bytes            += sq_stats->tso_bytes;
 124                         s->tx_queue_stopped     += sq_stats->stopped;
 125                         s->tx_queue_wake        += sq_stats->wake;
 126                         s->tx_queue_dropped     += sq_stats->dropped;
 127                         tx_offload_none         += sq_stats->csum_offload_none;
 128                 }
 129         }
 130
 131         /* HW counters */
 132         memset(in, 0, sizeof(in));
 133
 134         MLX5_SET(query_vport_counter_in, in, opcode,
 135                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 136         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 137         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 138
 139         memset(out, 0, outlen);
 140
 141         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 142                 goto free_out;
 143
 144 #define MLX5_GET_CTR(p, x) \
 145         MLX5_GET64(query_vport_counter_out, p, x)
 146
 147         s->rx_error_packets     =
 148                 MLX5_GET_CTR(out, received_errors.packets);
 149         s->rx_error_bytes       =
 150                 MLX5_GET_CTR(out, received_errors.octets);
 151         s->tx_error_packets     =
 152                 MLX5_GET_CTR(out, transmit_errors.packets);
 153         s->tx_error_bytes       =
 154                 MLX5_GET_CTR(out, transmit_errors.octets);
 155
 156         s->rx_unicast_packets   =
 157                 MLX5_GET_CTR(out, received_eth_unicast.packets);
 158         s->rx_unicast_bytes     =
 159                 MLX5_GET_CTR(out, received_eth_unicast.octets);
 160         s->tx_unicast_packets   =
 161                 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 162         s->tx_unicast_bytes     =
 163                 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 164
 165         s->rx_multicast_packets =
 166                 MLX5_GET_CTR(out, received_eth_multicast.packets);
 167         s->rx_multicast_bytes   =
 168                 MLX5_GET_CTR(out, received_eth_multicast.octets);
 169         s->tx_multicast_packets =
 170                 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 171         s->tx_multicast_bytes   =
 172                 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 173
 174         s->rx_broadcast_packets =
 175                 MLX5_GET_CTR(out, received_eth_broadcast.packets);
 176         s->rx_broadcast_bytes   =
 177                 MLX5_GET_CTR(out, received_eth_broadcast.octets);
 178         s->tx_broadcast_packets =
 179                 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 180         s->tx_broadcast_bytes   =
 181                 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 182
 183         s->rx_packets =
 184                 s->rx_unicast_packets +
 185                 s->rx_multicast_packets +
 186                 s->rx_broadcast_packets;
 187         s->rx_bytes =
 188                 s->rx_unicast_bytes +
 189                 s->rx_multicast_bytes +
 190                 s->rx_broadcast_bytes;
 191         s->tx_packets =
 192                 s->tx_unicast_packets +
 193                 s->tx_multicast_packets +
 194                 s->tx_broadcast_packets;
 195         s->tx_bytes =
 196                 s->tx_unicast_bytes +
 197                 s->tx_multicast_bytes +
 198                 s->tx_broadcast_bytes;
 199
 200         /* Update calculated offload counters */
 201         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 202         s->rx_csum_good    = s->rx_packets - s->rx_csum_none;
 203
 204 free_out:
 205         kvfree(out);
 206 }
 207
 208 static void mlx5e_update_stats_work(struct work_struct *work)
 209 {
 210         struct delayed_work *dwork = to_delayed_work(work);
 211         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 212                                                update_stats_work);
 213         mutex_lock(&priv->state_lock);
 214         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 215                 mlx5e_update_stats(priv);
 216                 schedule_delayed_work(dwork,
 217                                       msecs_to_jiffies(
 218                                               MLX5E_UPDATE_STATS_INTERVAL));
 219         }
 220         mutex_unlock(&priv->state_lock);
 221 }
 222
 223 static void __mlx5e_async_event(struct mlx5e_priv *priv,
 224                                 enum mlx5_dev_event event)
 225 {
 226         switch (event) {
 227         case MLX5_DEV_EVENT_PORT_UP:
 228         case MLX5_DEV_EVENT_PORT_DOWN:
 229                 schedule_work(&priv->update_carrier_work);
 230                 break;
 231
 232         default:
 233                 break;
 234         }
 235 }
 236
 237 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 238                               enum mlx5_dev_event event, unsigned long param)
 239 {
 240         struct mlx5e_priv *priv = vpriv;
 241
 242         spin_lock(&priv->async_events_spinlock);
 243         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 244                 __mlx5e_async_event(priv, event);
 245         spin_unlock(&priv->async_events_spinlock);
 246 }
 247
 248 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 249 {
 250         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 251 }
 252
 253 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 254 {
 255         spin_lock_irq(&priv->async_events_spinlock);
 256         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 257         spin_unlock_irq(&priv->async_events_spinlock);
 258 }
 259
 260 static void mlx5e_send_nop(struct mlx5e_sq *sq)
 261 {
 262         struct mlx5_wq_cyc                *wq  = &sq->wq;
 263
 264         u16 pi = sq->pc & wq->sz_m1;
 265         struct mlx5e_tx_wqe              *wqe  = mlx5_wq_cyc_get_wqe(wq, pi);
 266
 267         struct mlx5_wqe_ctrl_seg         *cseg = &wqe->ctrl;
 268
 269         memset(cseg, 0, sizeof(*cseg));
 270
 271         cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_NOP);
 272         cseg->qpn_ds           = cpu_to_be32((sq->sqn << 8) | 0x01);
 273         cseg->fm_ce_se         = MLX5_WQE_CTRL_CQ_UPDATE;
 274
 275         sq->skb[pi] = NULL;
 276         sq->pc++;
 277         mlx5e_tx_notify_hw(sq, wqe);
 278 }
 279
 280 static int mlx5e_create_rq(struct mlx5e_channel *c,
 281                            struct mlx5e_rq_param *param,
 282                            struct mlx5e_rq *rq)
 283 {
 284         struct mlx5e_priv *priv = c->priv;
 285         struct mlx5_core_dev *mdev = priv->mdev;
 286         void *rqc = param->rqc;
 287         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 288         int wq_sz;
 289         int err;
 290         int i;
 291
 292         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 293                                 &rq->wq_ctrl);
 294         if (err)
 295                 return err;
 296
 297         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 298
 299         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 300         rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 301                                cpu_to_node(c->cpu));
 302         if (!rq->skb) {
 303                 err = -ENOMEM;
 304                 goto err_rq_wq_destroy;
 305         }
 306
 307         rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
 308                                 priv->netdev->mtu + ETH_HLEN + VLAN_HLEN;
 309
 310         for (i = 0; i < wq_sz; i++) {
 311                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 312
 313                 wqe->data.lkey       = c->mkey_be;
 314                 wqe->data.byte_count = cpu_to_be32(rq->wqe_sz);
 315         }
 316
 317         rq->pdev    = c->pdev;
 318         rq->netdev  = c->netdev;
 319         rq->channel = c;
 320         rq->ix      = c->ix;
 321
 322         return 0;
 323
 324 err_rq_wq_destroy:
 325         mlx5_wq_destroy(&rq->wq_ctrl);
 326
 327         return err;
 328 }
 329
 330 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 331 {
 332         kfree(rq->skb);
 333         mlx5_wq_destroy(&rq->wq_ctrl);
 334 }
 335
 336 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 337 {
 338         struct mlx5e_channel *c = rq->channel;
 339         struct mlx5e_priv *priv = c->priv;
 340         struct mlx5_core_dev *mdev = priv->mdev;
 341
 342         void *in;
 343         void *rqc;
 344         void *wq;
 345         int inlen;
 346         int err;
 347
 348         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 349                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 350         in = mlx5_vzalloc(inlen);
 351         if (!in)
 352                 return -ENOMEM;
 353
 354         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 355         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 356
 357         memcpy(rqc, param->rqc, sizeof(param->rqc));
 358
 359         MLX5_SET(rqc,  rqc, cqn,                c->rq.cq.mcq.cqn);
 360         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 361         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 362         MLX5_SET(wq,   wq,  wq_type,            MLX5_WQ_TYPE_LINKED_LIST);
 363         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 364                                                 PAGE_SHIFT);
 365         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 366
 367         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 368                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 369
 370         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 371
 372         kvfree(in);
 373
 374         return err;
 375 }
 376
 377 static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 378 {
 379         struct mlx5e_channel *c = rq->channel;
 380         struct mlx5e_priv *priv = c->priv;
 381         struct mlx5_core_dev *mdev = priv->mdev;
 382
 383         void *in;
 384         void *rqc;
 385         int inlen;
 386         int err;
 387
 388         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 389         in = mlx5_vzalloc(inlen);
 390         if (!in)
 391                 return -ENOMEM;
 392
 393         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 394
 395         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 396         MLX5_SET(rqc, rqc, state, next_state);
 397
 398         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 399
 400         kvfree(in);
 401
 402         return err;
 403 }
 404
 405 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 406 {
 407         struct mlx5e_channel *c = rq->channel;
 408         struct mlx5e_priv *priv = c->priv;
 409         struct mlx5_core_dev *mdev = priv->mdev;
 410
 411         mlx5_core_destroy_rq(mdev, rq->rqn);
 412 }
 413
 414 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 415 {
 416         struct mlx5e_channel *c = rq->channel;
 417         struct mlx5e_priv *priv = c->priv;
 418         struct mlx5_wq_ll *wq = &rq->wq;
 419         int i;
 420
 421         for (i = 0; i < 1000; i++) {
 422                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 423                         return 0;
 424
 425                 msleep(20);
 426         }
 427
 428         return -ETIMEDOUT;
 429 }
 430
 431 static int mlx5e_open_rq(struct mlx5e_channel *c,
 432                          struct mlx5e_rq_param *param,
 433                          struct mlx5e_rq *rq)
 434 {
 435         int err;
 436
 437         err = mlx5e_create_rq(c, param, rq);
 438         if (err)
 439                 return err;
 440
 441         err = mlx5e_enable_rq(rq, param);
 442         if (err)
 443                 goto err_destroy_rq;
 444
 445         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 446         if (err)
 447                 goto err_disable_rq;
 448
 449         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 450         mlx5e_send_nop(&c->sq[0]); /* trigger mlx5e_post_rx_wqes() */
 451
 452         return 0;
 453
 454 err_disable_rq:
 455         mlx5e_disable_rq(rq);
 456 err_destroy_rq:
 457         mlx5e_destroy_rq(rq);
 458
 459         return err;
 460 }
 461
 462 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 463 {
 464         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 465         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 466
 467         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 468         while (!mlx5_wq_ll_is_empty(&rq->wq))
 469                 msleep(20);
 470
 471         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 472         napi_synchronize(&rq->channel->napi);
 473
 474         mlx5e_disable_rq(rq);
 475         mlx5e_destroy_rq(rq);
 476 }
 477
 478 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 479 {
 480         kfree(sq->dma_fifo);
 481         kfree(sq->skb);
 482 }
 483
 484 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 485 {
 486         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 487         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 488
 489         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 490         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 491                                     numa);
 492
 493         if (!sq->skb || !sq->dma_fifo) {
 494                 mlx5e_free_sq_db(sq);
 495                 return -ENOMEM;
 496         }
 497
 498         sq->dma_fifo_mask = df_sz - 1;
 499
 500         return 0;
 501 }
 502
 503 static int mlx5e_create_sq(struct mlx5e_channel *c,
 504                            int tc,
 505                            struct mlx5e_sq_param *param,
 506                            struct mlx5e_sq *sq)
 507 {
 508         struct mlx5e_priv *priv = c->priv;
 509         struct mlx5_core_dev *mdev = priv->mdev;
 510
 511         void *sqc = param->sqc;
 512         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 513         int err;
 514
 515         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 516         if (err)
 517                 return err;
 518
 519         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 520                                  &sq->wq_ctrl);
 521         if (err)
 522                 goto err_unmap_free_uar;
 523
 524         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 525         sq->uar_map     = sq->uar.map;
 526         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 527
 528         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 529         if (err)
 530                 goto err_sq_wq_destroy;
 531
 532         sq->txq = netdev_get_tx_queue(priv->netdev,
 533                                       c->ix + tc * priv->params.num_channels);
 534
 535         sq->pdev    = c->pdev;
 536         sq->mkey_be = c->mkey_be;
 537         sq->channel = c;
 538         sq->tc      = tc;
 539
 540         return 0;
 541
 542 err_sq_wq_destroy:
 543         mlx5_wq_destroy(&sq->wq_ctrl);
 544
 545 err_unmap_free_uar:
 546         mlx5_unmap_free_uar(mdev, &sq->uar);
 547
 548         return err;
 549 }
 550
 551 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 552 {
 553         struct mlx5e_channel *c = sq->channel;
 554         struct mlx5e_priv *priv = c->priv;
 555
 556         mlx5e_free_sq_db(sq);
 557         mlx5_wq_destroy(&sq->wq_ctrl);
 558         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 559 }
 560
 561 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 562 {
 563         struct mlx5e_channel *c = sq->channel;
 564         struct mlx5e_priv *priv = c->priv;
 565         struct mlx5_core_dev *mdev = priv->mdev;
 566
 567         void *in;
 568         void *sqc;
 569         void *wq;
 570         int inlen;
 571         int err;
 572
 573         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 574                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 575         in = mlx5_vzalloc(inlen);
 576         if (!in)
 577                 return -ENOMEM;
 578
 579         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 580         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 581
 582         memcpy(sqc, param->sqc, sizeof(param->sqc));
 583
 584         MLX5_SET(sqc,  sqc, user_index,         sq->tc);
 585         MLX5_SET(sqc,  sqc, tis_num_0,          priv->tisn[sq->tc]);
 586         MLX5_SET(sqc,  sqc, cqn,                c->sq[sq->tc].cq.mcq.cqn);
 587         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 588         MLX5_SET(sqc,  sqc, tis_lst_sz,         1);
 589         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 590
 591         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 592         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 593         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 594                                           PAGE_SHIFT);
 595         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 596
 597         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 598                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 599
 600         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 601
 602         kvfree(in);
 603
 604         return err;
 605 }
 606
 607 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 608 {
 609         struct mlx5e_channel *c = sq->channel;
 610         struct mlx5e_priv *priv = c->priv;
 611         struct mlx5_core_dev *mdev = priv->mdev;
 612
 613         void *in;
 614         void *sqc;
 615         int inlen;
 616         int err;
 617
 618         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 619         in = mlx5_vzalloc(inlen);
 620         if (!in)
 621                 return -ENOMEM;
 622
 623         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 624
 625         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 626         MLX5_SET(sqc, sqc, state, next_state);
 627
 628         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 629
 630         kvfree(in);
 631
 632         return err;
 633 }
 634
 635 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 636 {
 637         struct mlx5e_channel *c = sq->channel;
 638         struct mlx5e_priv *priv = c->priv;
 639         struct mlx5_core_dev *mdev = priv->mdev;
 640
 641         mlx5_core_destroy_sq(mdev, sq->sqn);
 642 }
 643
 644 static int mlx5e_open_sq(struct mlx5e_channel *c,
 645                          int tc,
 646                          struct mlx5e_sq_param *param,
 647                          struct mlx5e_sq *sq)
 648 {
 649         int err;
 650
 651         err = mlx5e_create_sq(c, tc, param, sq);
 652         if (err)
 653                 return err;
 654
 655         err = mlx5e_enable_sq(sq, param);
 656         if (err)
 657                 goto err_destroy_sq;
 658
 659         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 660         if (err)
 661                 goto err_disable_sq;
 662
 663         set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 664         netdev_tx_reset_queue(sq->txq);
 665         netif_tx_start_queue(sq->txq);
 666
 667         return 0;
 668
 669 err_disable_sq:
 670         mlx5e_disable_sq(sq);
 671 err_destroy_sq:
 672         mlx5e_destroy_sq(sq);
 673
 674         return err;
 675 }
 676
 677 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 678 {
 679         __netif_tx_lock_bh(txq);
 680         netif_tx_stop_queue(txq);
 681         __netif_tx_unlock_bh(txq);
 682 }
 683
 684 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 685 {
 686         clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 687         napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
 688         netif_tx_disable_queue(sq->txq);
 689
 690         /* ensure hw is notified of all pending wqes */
 691         if (mlx5e_sq_has_room_for(sq, 1))
 692                 mlx5e_send_nop(sq);
 693
 694         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 695         while (sq->cc != sq->pc) /* wait till sq is empty */
 696                 msleep(20);
 697
 698         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 699         napi_synchronize(&sq->channel->napi);
 700
 701         mlx5e_disable_sq(sq);
 702         mlx5e_destroy_sq(sq);
 703 }
 704
 705 static int mlx5e_create_cq(struct mlx5e_channel *c,
 706                            struct mlx5e_cq_param *param,
 707                            struct mlx5e_cq *cq)
 708 {
 709         struct mlx5e_priv *priv = c->priv;
 710         struct mlx5_core_dev *mdev = priv->mdev;
 711         struct mlx5_core_cq *mcq = &cq->mcq;
 712         int eqn_not_used;
 713         int irqn;
 714         int err;
 715         u32 i;
 716
 717         param->wq.numa = cpu_to_node(c->cpu);
 718         param->eq_ix   = c->ix;
 719
 720         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 721                                &cq->wq_ctrl);
 722         if (err)
 723                 return err;
 724
 725         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 726
 727         cq->napi        = &c->napi;
 728
 729         mcq->cqe_sz     = 64;
 730         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 731         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 732         *mcq->set_ci_db = 0;
 733         *mcq->arm_db    = 0;
 734         mcq->vector     = param->eq_ix;
 735         mcq->comp       = mlx5e_completion_event;
 736         mcq->event      = mlx5e_cq_error_event;
 737         mcq->irqn       = irqn;
 738         mcq->uar        = &priv->cq_uar;
 739
 740         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 741                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 742
 743                 cqe->op_own = 0xf1;
 744         }
 745
 746         cq->channel = c;
 747
 748         return 0;
 749 }
 750
 751 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 752 {
 753         mlx5_wq_destroy(&cq->wq_ctrl);
 754 }
 755
 756 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 757 {
 758         struct mlx5e_channel *c = cq->channel;
 759         struct mlx5e_priv *priv = c->priv;
 760         struct mlx5_core_dev *mdev = priv->mdev;
 761         struct mlx5_core_cq *mcq = &cq->mcq;
 762
 763         void *in;
 764         void *cqc;
 765         int inlen;
 766         int irqn_not_used;
 767         int eqn;
 768         int err;
 769
 770         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 771                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 772         in = mlx5_vzalloc(inlen);
 773         if (!in)
 774                 return -ENOMEM;
 775
 776         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 777
 778         memcpy(cqc, param->cqc, sizeof(param->cqc));
 779
 780         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 781                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 782
 783         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 784
 785         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 786         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 787         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 788                                             PAGE_SHIFT);
 789         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 790
 791         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 792
 793         kvfree(in);
 794
 795         if (err)
 796                 return err;
 797
 798         mlx5e_cq_arm(cq);
 799
 800         return 0;
 801 }
 802
 803 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 804 {
 805         struct mlx5e_channel *c = cq->channel;
 806         struct mlx5e_priv *priv = c->priv;
 807         struct mlx5_core_dev *mdev = priv->mdev;
 808
 809         mlx5_core_destroy_cq(mdev, &cq->mcq);
 810 }
 811
 812 static int mlx5e_open_cq(struct mlx5e_channel *c,
 813                          struct mlx5e_cq_param *param,
 814                          struct mlx5e_cq *cq,
 815                          u16 moderation_usecs,
 816                          u16 moderation_frames)
 817 {
 818         int err;
 819         struct mlx5e_priv *priv = c->priv;
 820         struct mlx5_core_dev *mdev = priv->mdev;
 821
 822         err = mlx5e_create_cq(c, param, cq);
 823         if (err)
 824                 return err;
 825
 826         err = mlx5e_enable_cq(cq, param);
 827         if (err)
 828                 goto err_destroy_cq;
 829
 830         err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 831                                              moderation_usecs,
 832                                              moderation_frames);
 833         if (err)
 834                 goto err_destroy_cq;
 835
 836         return 0;
 837
 838 err_destroy_cq:
 839         mlx5e_destroy_cq(cq);
 840
 841         return err;
 842 }
 843
 844 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 845 {
 846         mlx5e_disable_cq(cq);
 847         mlx5e_destroy_cq(cq);
 848 }
 849
 850 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 851 {
 852         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 853 }
 854
 855 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 856                              struct mlx5e_channel_param *cparam)
 857 {
 858         struct mlx5e_priv *priv = c->priv;
 859         int err;
 860         int tc;
 861
 862         for (tc = 0; tc < c->num_tc; tc++) {
 863                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 864                                     priv->params.tx_cq_moderation_usec,
 865                                     priv->params.tx_cq_moderation_pkts);
 866                 if (err)
 867                         goto err_close_tx_cqs;
 868
 869                 c->sq[tc].cq.sqrq = &c->sq[tc];
 870         }
 871
 872         return 0;
 873
 874 err_close_tx_cqs:
 875         for (tc--; tc >= 0; tc--)
 876                 mlx5e_close_cq(&c->sq[tc].cq);
 877
 878         return err;
 879 }
 880
 881 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 882 {
 883         int tc;
 884
 885         for (tc = 0; tc < c->num_tc; tc++)
 886                 mlx5e_close_cq(&c->sq[tc].cq);
 887 }
 888
 889 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 890                           struct mlx5e_channel_param *cparam)
 891 {
 892         int err;
 893         int tc;
 894
 895         for (tc = 0; tc < c->num_tc; tc++) {
 896                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 897                 if (err)
 898                         goto err_close_sqs;
 899         }
 900
 901         return 0;
 902
 903 err_close_sqs:
 904         for (tc--; tc >= 0; tc--)
 905                 mlx5e_close_sq(&c->sq[tc]);
 906
 907         return err;
 908 }
 909
 910 static void mlx5e_close_sqs(struct mlx5e_channel *c)
 911 {
 912         int tc;
 913
 914         for (tc = 0; tc < c->num_tc; tc++)
 915                 mlx5e_close_sq(&c->sq[tc]);
 916 }
 917
 918 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
 919                               struct mlx5e_channel_param *cparam,
 920                               struct mlx5e_channel **cp)
 921 {
 922         struct net_device *netdev = priv->netdev;
 923         int cpu = mlx5e_get_cpu(priv, ix);
 924         struct mlx5e_channel *c;
 925         int err;
 926
 927         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
 928         if (!c)
 929                 return -ENOMEM;
 930
 931         c->priv     = priv;
 932         c->ix       = ix;
 933         c->cpu      = cpu;
 934         c->pdev     = &priv->mdev->pdev->dev;
 935         c->netdev   = priv->netdev;
 936         c->mkey_be  = cpu_to_be32(priv->mr.key);
 937         c->num_tc   = priv->num_tc;
 938
 939         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
 940
 941         err = mlx5e_open_tx_cqs(c, cparam);
 942         if (err)
 943                 goto err_napi_del;
 944
 945         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
 946                             priv->params.rx_cq_moderation_usec,
 947                             priv->params.rx_cq_moderation_pkts);
 948         if (err)
 949                 goto err_close_tx_cqs;
 950         c->rq.cq.sqrq = &c->rq;
 951
 952         napi_enable(&c->napi);
 953
 954         err = mlx5e_open_sqs(c, cparam);
 955         if (err)
 956                 goto err_disable_napi;
 957
 958         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
 959         if (err)
 960                 goto err_close_sqs;
 961
 962         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
 963         *cp = c;
 964
 965         return 0;
 966
 967 err_close_sqs:
 968         mlx5e_close_sqs(c);
 969
 970 err_disable_napi:
 971         napi_disable(&c->napi);
 972         mlx5e_close_cq(&c->rq.cq);
 973
 974 err_close_tx_cqs:
 975         mlx5e_close_tx_cqs(c);
 976
 977 err_napi_del:
 978         netif_napi_del(&c->napi);
 979         kfree(c);
 980
 981         return err;
 982 }
 983
 984 static void mlx5e_close_channel(struct mlx5e_channel *c)
 985 {
 986         mlx5e_close_rq(&c->rq);
 987         mlx5e_close_sqs(c);
 988         napi_disable(&c->napi);
 989         mlx5e_close_cq(&c->rq.cq);
 990         mlx5e_close_tx_cqs(c);
 991         netif_napi_del(&c->napi);
 992         kfree(c);
 993 }
 994
 995 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
 996                                  struct mlx5e_rq_param *param)
 997 {
 998         void *rqc = param->rqc;
 999         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1000
1001         MLX5_SET(wq, wq, wq_type,          MLX5_WQ_TYPE_LINKED_LIST);
1002         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1003         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1004         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1005         MLX5_SET(wq, wq, pd,               priv->pdn);
1006
1007         param->wq.numa   = dev_to_node(&priv->mdev->pdev->dev);
1008         param->wq.linear = 1;
1009 }
1010
1011 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1012                                  struct mlx5e_sq_param *param)
1013 {
1014         void *sqc = param->sqc;
1015         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1016
1017         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1018         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1019         MLX5_SET(wq, wq, pd,            priv->pdn);
1020
1021         param->wq.numa = dev_to_node(&priv->mdev->pdev->dev);
1022 }
1023
1024 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1025                                         struct mlx5e_cq_param *param)
1026 {
1027         void *cqc = param->cqc;
1028
1029         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1030 }
1031
1032 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1033                                     struct mlx5e_cq_param *param)
1034 {
1035         void *cqc = param->cqc;
1036
1037         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_rq_size);
1038
1039         mlx5e_build_common_cq_param(priv, param);
1040 }
1041
1042 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1043                                     struct mlx5e_cq_param *param)
1044 {
1045         void *cqc = param->cqc;
1046
1047         MLX5_SET(cqc, cqc, log_cq_size,  priv->params.log_sq_size);
1048
1049         mlx5e_build_common_cq_param(priv, param);
1050 }
1051
1052 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1053                                       struct mlx5e_channel_param *cparam)
1054 {
1055         memset(cparam, 0, sizeof(*cparam));
1056
1057         mlx5e_build_rq_param(priv, &cparam->rq);
1058         mlx5e_build_sq_param(priv, &cparam->sq);
1059         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1060         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1061 }
1062
1063 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1064 {
1065         struct mlx5e_channel_param cparam;
1066         int err;
1067         int i;
1068         int j;
1069
1070         priv->channel = kcalloc(priv->params.num_channels,
1071                                 sizeof(struct mlx5e_channel *), GFP_KERNEL);
1072         if (!priv->channel)
1073                 return -ENOMEM;
1074
1075         mlx5e_build_channel_param(priv, &cparam);
1076         for (i = 0; i < priv->params.num_channels; i++) {
1077                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1078                 if (err)
1079                         goto err_close_channels;
1080         }
1081
1082         for (j = 0; j < priv->params.num_channels; j++) {
1083                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1084                 if (err)
1085                         goto err_close_channels;
1086         }
1087
1088         return 0;
1089
1090 err_close_channels:
1091         for (i--; i >= 0; i--)
1092                 mlx5e_close_channel(priv->channel[i]);
1093
1094         kfree(priv->channel);
1095
1096         return err;
1097 }
1098
1099 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1100 {
1101         int i;
1102
1103         for (i = 0; i < priv->params.num_channels; i++)
1104                 mlx5e_close_channel(priv->channel[i]);
1105
1106         kfree(priv->channel);
1107 }
1108
1109 static int mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1110 {
1111         struct mlx5_core_dev *mdev = priv->mdev;
1112         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1113         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1114
1115         memset(in, 0, sizeof(in));
1116
1117         MLX5_SET(tisc, tisc, prio,  tc);
1118
1119         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1120 }
1121
1122 static void mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1123 {
1124         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1125 }
1126
1127 static int mlx5e_open_tises(struct mlx5e_priv *priv)
1128 {
1129         int num_tc = priv->num_tc;
1130         int err;
1131         int tc;
1132
1133         for (tc = 0; tc < num_tc; tc++) {
1134                 err = mlx5e_open_tis(priv, tc);
1135                 if (err)
1136                         goto err_close_tises;
1137         }
1138
1139         return 0;
1140
1141 err_close_tises:
1142         for (tc--; tc >= 0; tc--)
1143                 mlx5e_close_tis(priv, tc);
1144
1145         return err;
1146 }
1147
1148 static void mlx5e_close_tises(struct mlx5e_priv *priv)
1149 {
1150         int num_tc = priv->num_tc;
1151         int tc;
1152
1153         for (tc = 0; tc < num_tc; tc++)
1154                 mlx5e_close_tis(priv, tc);
1155 }
1156
1157 static int mlx5e_open_rqt(struct mlx5e_priv *priv)
1158 {
1159         struct mlx5_core_dev *mdev = priv->mdev;
1160         u32 *in;
1161         u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1162         void *rqtc;
1163         int inlen;
1164         int err;
1165         int sz;
1166         int i;
1167
1168         sz = 1 << priv->params.rx_hash_log_tbl_sz;
1169
1170         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1171         in = mlx5_vzalloc(inlen);
1172         if (!in)
1173                 return -ENOMEM;
1174
1175         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1176
1177         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1178         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1179
1180         for (i = 0; i < sz; i++) {
1181                 int ix = i % priv->params.num_channels;
1182
1183                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1184         }
1185
1186         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1187
1188         memset(out, 0, sizeof(out));
1189         err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1190         if (!err)
1191                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1192
1193         kvfree(in);
1194
1195         return err;
1196 }
1197
1198 static void mlx5e_close_rqt(struct mlx5e_priv *priv)
1199 {
1200         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1201         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1202
1203         memset(in, 0, sizeof(in));
1204
1205         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1206         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1207
1208         mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1209                                    sizeof(out));
1210 }
1211
1212 static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1213 {
1214         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1215
1216 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1217
1218 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1219                           MLX5_HASH_FIELD_SEL_DST_IP)
1220
1221 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1222                           MLX5_HASH_FIELD_SEL_DST_IP   |\
1223                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
1224                           MLX5_HASH_FIELD_SEL_L4_DPORT)
1225
1226         if (priv->params.lro_en) {
1227                 MLX5_SET(tirc, tirc, lro_enable_mask,
1228                          MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1229                          MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1230                 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1231                          (priv->params.lro_wqe_sz -
1232                           ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1233                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1234                          MLX5_CAP_ETH(priv->mdev,
1235                                       lro_timer_supported_periods[3]));
1236         }
1237
1238         switch (tt) {
1239         case MLX5E_TT_ANY:
1240                 MLX5_SET(tirc, tirc, disp_type,
1241                          MLX5_TIRC_DISP_TYPE_DIRECT);
1242                 MLX5_SET(tirc, tirc, inline_rqn,
1243                          priv->channel[0]->rq.rqn);
1244                 break;
1245         default:
1246                 MLX5_SET(tirc, tirc, disp_type,
1247                          MLX5_TIRC_DISP_TYPE_INDIRECT);
1248                 MLX5_SET(tirc, tirc, indirect_table,
1249                          priv->rqtn);
1250                 MLX5_SET(tirc, tirc, rx_hash_fn,
1251                          MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
1252                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1253                 netdev_rss_key_fill(MLX5_ADDR_OF(tirc, tirc,
1254                                                  rx_hash_toeplitz_key),
1255                                     MLX5_FLD_SZ_BYTES(tirc,
1256                                                       rx_hash_toeplitz_key));
1257                 break;
1258         }
1259
1260         switch (tt) {
1261         case MLX5E_TT_IPV4_TCP:
1262                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1263                          MLX5_L3_PROT_TYPE_IPV4);
1264                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1265                          MLX5_L4_PROT_TYPE_TCP);
1266                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1267                          MLX5_HASH_ALL);
1268                 break;
1269
1270         case MLX5E_TT_IPV6_TCP:
1271                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1272                          MLX5_L3_PROT_TYPE_IPV6);
1273                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1274                          MLX5_L4_PROT_TYPE_TCP);
1275                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1276                          MLX5_HASH_ALL);
1277                 break;
1278
1279         case MLX5E_TT_IPV4_UDP:
1280                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1281                          MLX5_L3_PROT_TYPE_IPV4);
1282                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1283                          MLX5_L4_PROT_TYPE_UDP);
1284                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1285                          MLX5_HASH_ALL);
1286                 break;
1287
1288         case MLX5E_TT_IPV6_UDP:
1289                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1290                          MLX5_L3_PROT_TYPE_IPV6);
1291                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1292                          MLX5_L4_PROT_TYPE_UDP);
1293                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1294                          MLX5_HASH_ALL);
1295                 break;
1296
1297         case MLX5E_TT_IPV4:
1298                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1299                          MLX5_L3_PROT_TYPE_IPV4);
1300                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1301                          MLX5_HASH_IP);
1302                 break;
1303
1304         case MLX5E_TT_IPV6:
1305                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1306                          MLX5_L3_PROT_TYPE_IPV6);
1307                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1308                          MLX5_HASH_IP);
1309                 break;
1310         }
1311 }
1312
1313 static int mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
1314 {
1315         struct mlx5_core_dev *mdev = priv->mdev;
1316         u32 *in;
1317         void *tirc;
1318         int inlen;
1319         int err;
1320
1321         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1322         in = mlx5_vzalloc(inlen);
1323         if (!in)
1324                 return -ENOMEM;
1325
1326         tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1327
1328         mlx5e_build_tir_ctx(priv, tirc, tt);
1329
1330         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
1331
1332         kvfree(in);
1333
1334         return err;
1335 }
1336
1337 static void mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
1338 {
1339         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
1340 }
1341
1342 static int mlx5e_open_tirs(struct mlx5e_priv *priv)
1343 {
1344         int err;
1345         int i;
1346
1347         for (i = 0; i < MLX5E_NUM_TT; i++) {
1348                 err = mlx5e_open_tir(priv, i);
1349                 if (err)
1350                         goto err_close_tirs;
1351         }
1352
1353         return 0;
1354
1355 err_close_tirs:
1356         for (i--; i >= 0; i--)
1357                 mlx5e_close_tir(priv, i);
1358
1359         return err;
1360 }
1361
1362 static void mlx5e_close_tirs(struct mlx5e_priv *priv)
1363 {
1364         int i;
1365
1366         for (i = 0; i < MLX5E_NUM_TT; i++)
1367                 mlx5e_close_tir(priv, i);
1368 }
1369
1370 int mlx5e_open_locked(struct net_device *netdev)
1371 {
1372         struct mlx5e_priv *priv = netdev_priv(netdev);
1373         struct mlx5_core_dev *mdev = priv->mdev;
1374         int actual_mtu;
1375         int num_txqs;
1376         int err;
1377
1378         num_txqs = roundup_pow_of_two(priv->params.num_channels) *
1379                    priv->params.num_tc;
1380         netif_set_real_num_tx_queues(netdev, num_txqs);
1381         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1382
1383         err = mlx5_set_port_mtu(mdev, netdev->mtu);
1384         if (err) {
1385                 netdev_err(netdev, "%s: mlx5_set_port_mtu failed %d\n",
1386                            __func__, err);
1387                 return err;
1388         }
1389
1390         err = mlx5_query_port_oper_mtu(mdev, &actual_mtu, 1);
1391         if (err) {
1392                 netdev_err(netdev, "%s: mlx5_query_port_oper_mtu failed %d\n",
1393                            __func__, err);
1394                 return err;
1395         }
1396
1397         if (actual_mtu != netdev->mtu)
1398                 netdev_warn(netdev, "%s: Failed to set MTU to %d\n",
1399                             __func__, netdev->mtu);
1400
1401         netdev->mtu = actual_mtu;
1402
1403         err = mlx5e_open_tises(priv);
1404         if (err) {
1405                 netdev_err(netdev, "%s: mlx5e_open_tises failed, %d\n",
1406                            __func__, err);
1407                 return err;
1408         }
1409
1410         err = mlx5e_open_channels(priv);
1411         if (err) {
1412                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1413                            __func__, err);
1414                 goto err_close_tises;
1415         }
1416
1417         err = mlx5e_open_rqt(priv);
1418         if (err) {
1419                 netdev_err(netdev, "%s: mlx5e_open_rqt failed, %d\n",
1420                            __func__, err);
1421                 goto err_close_channels;
1422         }
1423
1424         err = mlx5e_open_tirs(priv);
1425         if (err) {
1426                 netdev_err(netdev, "%s: mlx5e_open_tir failed, %d\n",
1427                            __func__, err);
1428                 goto err_close_rqls;
1429         }
1430
1431         err = mlx5e_open_flow_table(priv);
1432         if (err) {
1433                 netdev_err(netdev, "%s: mlx5e_open_flow_table failed, %d\n",
1434                            __func__, err);
1435                 goto err_close_tirs;
1436         }
1437
1438         err = mlx5e_add_all_vlan_rules(priv);
1439         if (err) {
1440                 netdev_err(netdev, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
1441                            __func__, err);
1442                 goto err_close_flow_table;
1443         }
1444
1445         mlx5e_init_eth_addr(priv);
1446
1447         set_bit(MLX5E_STATE_OPENED, &priv->state);
1448
1449         mlx5e_update_carrier(priv);
1450         mlx5e_set_rx_mode_core(priv);
1451
1452         schedule_delayed_work(&priv->update_stats_work, 0);
1453         return 0;
1454
1455 err_close_flow_table:
1456         mlx5e_close_flow_table(priv);
1457
1458 err_close_tirs:
1459         mlx5e_close_tirs(priv);
1460
1461 err_close_rqls:
1462         mlx5e_close_rqt(priv);
1463
1464 err_close_channels:
1465         mlx5e_close_channels(priv);
1466
1467 err_close_tises:
1468         mlx5e_close_tises(priv);
1469
1470         return err;
1471 }
1472
1473 static int mlx5e_open(struct net_device *netdev)
1474 {
1475         struct mlx5e_priv *priv = netdev_priv(netdev);
1476         int err;
1477
1478         mutex_lock(&priv->state_lock);
1479         err = mlx5e_open_locked(netdev);
1480         mutex_unlock(&priv->state_lock);
1481
1482         return err;
1483 }
1484
1485 int mlx5e_close_locked(struct net_device *netdev)
1486 {
1487         struct mlx5e_priv *priv = netdev_priv(netdev);
1488
1489         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1490
1491         mlx5e_set_rx_mode_core(priv);
1492         mlx5e_del_all_vlan_rules(priv);
1493         netif_carrier_off(priv->netdev);
1494         mlx5e_close_flow_table(priv);
1495         mlx5e_close_tirs(priv);
1496         mlx5e_close_rqt(priv);
1497         mlx5e_close_channels(priv);
1498         mlx5e_close_tises(priv);
1499
1500         return 0;
1501 }
1502
1503 static int mlx5e_close(struct net_device *netdev)
1504 {
1505         struct mlx5e_priv *priv = netdev_priv(netdev);
1506         int err;
1507
1508         mutex_lock(&priv->state_lock);
1509         err = mlx5e_close_locked(netdev);
1510         mutex_unlock(&priv->state_lock);
1511
1512         return err;
1513 }
1514
1515 int mlx5e_update_priv_params(struct mlx5e_priv *priv,
1516                              struct mlx5e_params *new_params)
1517 {
1518         int err = 0;
1519         int was_opened;
1520
1521         WARN_ON(!mutex_is_locked(&priv->state_lock));
1522
1523         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1524         if (was_opened)
1525                 mlx5e_close_locked(priv->netdev);
1526
1527         priv->params = *new_params;
1528
1529         if (was_opened)
1530                 err = mlx5e_open_locked(priv->netdev);
1531
1532         return err;
1533 }
1534
1535 static struct rtnl_link_stats64 *
1536 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1537 {
1538         struct mlx5e_priv *priv = netdev_priv(dev);
1539         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1540
1541         stats->rx_packets = vstats->rx_packets;
1542         stats->rx_bytes   = vstats->rx_bytes;
1543         stats->tx_packets = vstats->tx_packets;
1544         stats->tx_bytes   = vstats->tx_bytes;
1545         stats->multicast  = vstats->rx_multicast_packets +
1546                             vstats->tx_multicast_packets;
1547         stats->tx_errors  = vstats->tx_error_packets;
1548         stats->rx_errors  = vstats->rx_error_packets;
1549         stats->tx_dropped = vstats->tx_queue_dropped;
1550         stats->rx_crc_errors = 0;
1551         stats->rx_length_errors = 0;
1552
1553         return stats;
1554 }
1555
1556 static void mlx5e_set_rx_mode(struct net_device *dev)
1557 {
1558         struct mlx5e_priv *priv = netdev_priv(dev);
1559
1560         schedule_work(&priv->set_rx_mode_work);
1561 }
1562
1563 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1564 {
1565         struct mlx5e_priv *priv = netdev_priv(netdev);
1566         struct sockaddr *saddr = addr;
1567
1568         if (!is_valid_ether_addr(saddr->sa_data))
1569                 return -EADDRNOTAVAIL;
1570
1571         netif_addr_lock_bh(netdev);
1572         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1573         netif_addr_unlock_bh(netdev);
1574
1575         schedule_work(&priv->set_rx_mode_work);
1576
1577         return 0;
1578 }
1579
1580 static int mlx5e_set_features(struct net_device *netdev,
1581                               netdev_features_t features)
1582 {
1583         struct mlx5e_priv *priv = netdev_priv(netdev);
1584         netdev_features_t changes = features ^ netdev->features;
1585         struct mlx5e_params new_params;
1586         bool update_params = false;
1587
1588         mutex_lock(&priv->state_lock);
1589         new_params = priv->params;
1590
1591         if (changes & NETIF_F_LRO) {
1592                 new_params.lro_en = !!(features & NETIF_F_LRO);
1593                 update_params = true;
1594         }
1595
1596         if (update_params)
1597                 mlx5e_update_priv_params(priv, &new_params);
1598
1599         if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1600                 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1601                         mlx5e_enable_vlan_filter(priv);
1602                 else
1603                         mlx5e_disable_vlan_filter(priv);
1604         }
1605
1606         mutex_unlock(&priv->state_lock);
1607
1608         return 0;
1609 }
1610
1611 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1612 {
1613         struct mlx5e_priv *priv = netdev_priv(netdev);
1614         struct mlx5_core_dev *mdev = priv->mdev;
1615         int max_mtu;
1616         int err = 0;
1617
1618         err = mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
1619         if (err)
1620                 return err;
1621
1622         if (new_mtu > max_mtu || new_mtu < MLX5E_PARAMS_MIN_MTU) {
1623                 netdev_err(netdev, "%s: Bad MTU size, mtu must be [%d-%d]\n",
1624                            __func__, MLX5E_PARAMS_MIN_MTU, max_mtu);
1625                 return -EINVAL;
1626         }
1627
1628         mutex_lock(&priv->state_lock);
1629         netdev->mtu = new_mtu;
1630         err = mlx5e_update_priv_params(priv, &priv->params);
1631         mutex_unlock(&priv->state_lock);
1632
1633         return err;
1634 }
1635
1636 static struct net_device_ops mlx5e_netdev_ops = {
1637         .ndo_open                = mlx5e_open,
1638         .ndo_stop                = mlx5e_close,
1639         .ndo_start_xmit          = mlx5e_xmit,
1640         .ndo_get_stats64         = mlx5e_get_stats,
1641         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
1642         .ndo_set_mac_address     = mlx5e_set_mac,
1643         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
1644         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
1645         .ndo_set_features        = mlx5e_set_features,
1646         .ndo_change_mtu          = mlx5e_change_mtu,
1647 };
1648
1649 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
1650 {
1651         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1652                 return -ENOTSUPP;
1653         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
1654             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
1655             !MLX5_CAP_ETH(mdev, csum_cap) ||
1656             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
1657             !MLX5_CAP_ETH(mdev, vlan_cap) ||
1658             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap)) {
1659                 mlx5_core_warn(mdev,
1660                                "Not creating net device, some required device capabilities are missing\n");
1661                 return -ENOTSUPP;
1662         }
1663         return 0;
1664 }
1665
1666 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
1667                                     struct net_device *netdev,
1668                                     int num_comp_vectors)
1669 {
1670         struct mlx5e_priv *priv = netdev_priv(netdev);
1671
1672         priv->params.log_sq_size           =
1673                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
1674         priv->params.log_rq_size           =
1675                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
1676         priv->params.rx_cq_moderation_usec =
1677                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
1678         priv->params.rx_cq_moderation_pkts =
1679                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
1680         priv->params.tx_cq_moderation_usec =
1681                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
1682         priv->params.tx_cq_moderation_pkts =
1683                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
1684         priv->params.min_rx_wqes           =
1685                 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
1686         priv->params.rx_hash_log_tbl_sz    =
1687                 (order_base_2(num_comp_vectors) >
1688                  MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
1689                 order_base_2(num_comp_vectors)           :
1690                 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
1691         priv->params.num_tc                = 1;
1692         priv->params.default_vlan_prio     = 0;
1693
1694         priv->params.lro_en = false && !!MLX5_CAP_ETH(priv->mdev, lro_cap);
1695         priv->params.lro_wqe_sz            =
1696                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
1697
1698         priv->mdev                         = mdev;
1699         priv->netdev                       = netdev;
1700         priv->params.num_channels          = num_comp_vectors;
1701         priv->order_base_2_num_channels    = order_base_2(num_comp_vectors);
1702         priv->queue_mapping_channel_mask   =
1703                 roundup_pow_of_two(num_comp_vectors) - 1;
1704         priv->num_tc                       = priv->params.num_tc;
1705         priv->default_vlan_prio            = priv->params.default_vlan_prio;
1706
1707         spin_lock_init(&priv->async_events_spinlock);
1708         mutex_init(&priv->state_lock);
1709
1710         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
1711         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
1712         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
1713 }
1714
1715 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
1716 {
1717         struct mlx5e_priv *priv = netdev_priv(netdev);
1718
1719         mlx5_query_nic_vport_mac_address(priv->mdev, netdev->dev_addr);
1720 }
1721
1722 static void mlx5e_build_netdev(struct net_device *netdev)
1723 {
1724         struct mlx5e_priv *priv = netdev_priv(netdev);
1725         struct mlx5_core_dev *mdev = priv->mdev;
1726
1727         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
1728
1729         if (priv->num_tc > 1) {
1730                 mlx5e_netdev_ops.ndo_select_queue = mlx5e_select_queue;
1731                 mlx5e_netdev_ops.ndo_start_xmit   = mlx5e_xmit_multi_tc;
1732         }
1733
1734         netdev->netdev_ops        = &mlx5e_netdev_ops;
1735         netdev->watchdog_timeo    = 15 * HZ;
1736
1737         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
1738
1739         netdev->vlan_features    |= NETIF_F_IP_CSUM;
1740         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
1741         netdev->vlan_features    |= NETIF_F_GRO;
1742         netdev->vlan_features    |= NETIF_F_TSO;
1743         netdev->vlan_features    |= NETIF_F_TSO6;
1744         netdev->vlan_features    |= NETIF_F_RXCSUM;
1745         netdev->vlan_features    |= NETIF_F_RXHASH;
1746
1747         if (!!MLX5_CAP_ETH(mdev, lro_cap))
1748                 netdev->vlan_features    |= NETIF_F_LRO;
1749
1750         netdev->hw_features       = netdev->vlan_features;
1751         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
1752         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
1753         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
1754
1755         netdev->features          = netdev->hw_features;
1756         if (!priv->params.lro_en)
1757                 netdev->features  &= ~NETIF_F_LRO;
1758
1759         netdev->features         |= NETIF_F_HIGHDMA;
1760
1761         netdev->priv_flags       |= IFF_UNICAST_FLT;
1762
1763         mlx5e_set_netdev_dev_addr(netdev);
1764 }
1765
1766 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
1767                              struct mlx5_core_mr *mr)
1768 {
1769         struct mlx5_core_dev *mdev = priv->mdev;
1770         struct mlx5_create_mkey_mbox_in *in;
1771         int err;
1772
1773         in = mlx5_vzalloc(sizeof(*in));
1774         if (!in)
1775                 return -ENOMEM;
1776
1777         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
1778                         MLX5_PERM_LOCAL_READ  |
1779                         MLX5_ACCESS_MODE_PA;
1780         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
1781         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
1782
1783         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
1784                                     NULL);
1785
1786         kvfree(in);
1787
1788         return err;
1789 }
1790
1791 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
1792 {
1793         struct net_device *netdev;
1794         struct mlx5e_priv *priv;
1795         int ncv = mdev->priv.eq_table.num_comp_vectors;
1796         int err;
1797
1798         if (mlx5e_check_required_hca_cap(mdev))
1799                 return NULL;
1800
1801         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
1802                                     roundup_pow_of_two(ncv) * MLX5E_MAX_NUM_TC,
1803                                     ncv);
1804         if (!netdev) {
1805                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
1806                 return NULL;
1807         }
1808
1809         mlx5e_build_netdev_priv(mdev, netdev, ncv);
1810         mlx5e_build_netdev(netdev);
1811
1812         netif_carrier_off(netdev);
1813
1814         priv = netdev_priv(netdev);
1815
1816         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
1817         if (err) {
1818                 netdev_err(netdev, "%s: mlx5_alloc_map_uar failed, %d\n",
1819                            __func__, err);
1820                 goto err_free_netdev;
1821         }
1822
1823         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
1824         if (err) {
1825                 netdev_err(netdev, "%s: mlx5_core_alloc_pd failed, %d\n",
1826                            __func__, err);
1827                 goto err_unmap_free_uar;
1828         }
1829
1830         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
1831         if (err) {
1832                 netdev_err(netdev, "%s: mlx5e_create_mkey failed, %d\n",
1833                            __func__, err);
1834                 goto err_dealloc_pd;
1835         }
1836
1837         err = register_netdev(netdev);
1838         if (err) {
1839                 netdev_err(netdev, "%s: register_netdev failed, %d\n",
1840                            __func__, err);
1841                 goto err_destroy_mkey;
1842         }
1843
1844         mlx5e_enable_async_events(priv);
1845
1846         return priv;
1847
1848 err_destroy_mkey:
1849         mlx5_core_destroy_mkey(mdev, &priv->mr);
1850
1851 err_dealloc_pd:
1852         mlx5_core_dealloc_pd(mdev, priv->pdn);
1853
1854 err_unmap_free_uar:
1855         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
1856
1857 err_free_netdev:
1858         free_netdev(netdev);
1859
1860         return NULL;
1861 }
1862
1863 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
1864 {
1865         struct mlx5e_priv *priv = vpriv;
1866         struct net_device *netdev = priv->netdev;
1867
1868         unregister_netdev(netdev);
1869         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
1870         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
1871         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
1872         mlx5e_disable_async_events(priv);
1873         flush_scheduled_work();
1874         free_netdev(netdev);
1875 }
1876
1877 static void *mlx5e_get_netdev(void *vpriv)
1878 {
1879         struct mlx5e_priv *priv = vpriv;
1880
1881         return priv->netdev;
1882 }
1883
1884 static struct mlx5_interface mlx5e_interface = {
1885         .add       = mlx5e_create_netdev,
1886         .remove    = mlx5e_destroy_netdev,
1887         .event     = mlx5e_async_event,
1888         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
1889         .get_dev   = mlx5e_get_netdev,
1890 };
1891
1892 void mlx5e_init(void)
1893 {
1894         mlx5_register_interface(&mlx5e_interface);
1895 }
1896
1897 void mlx5e_cleanup(void)
1898 {
1899         mlx5_unregister_interface(&mlx5e_interface);
1900 }