2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
44 struct mlx5e_rq_param {
45 u32 rqc[MLX5_ST_SZ_DW(rqc)];
46 struct mlx5_wq_param wq;
49 struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
54 struct mlx5e_cq_param {
55 u32 cqc[MLX5_ST_SZ_DW(cqc)];
56 struct mlx5_wq_param wq;
61 struct mlx5e_channel_param {
62 struct mlx5e_rq_param rq;
63 struct mlx5e_sq_param sq;
64 struct mlx5e_sq_param xdp_sq;
65 struct mlx5e_sq_param icosq;
66 struct mlx5e_cq_param rx_cq;
67 struct mlx5e_cq_param tx_cq;
68 struct mlx5e_cq_param icosq_cq;
71 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
73 return MLX5_CAP_GEN(mdev, striding_rq) &&
74 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
75 MLX5_CAP_ETH(mdev, reg_umr_sq);
78 void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
79 struct mlx5e_params *params, u8 rq_type)
81 params->rq_wq_type = rq_type;
82 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
83 switch (params->rq_wq_type) {
84 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
85 params->log_rq_size = is_kdump_kernel() ?
86 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
87 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
88 params->mpwqe_log_stride_sz =
89 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
90 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
91 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
92 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
93 params->mpwqe_log_stride_sz;
95 default: /* MLX5_WQ_TYPE_LINKED_LIST */
96 params->log_rq_size = is_kdump_kernel() ?
97 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
98 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
100 /* Extra room needed for build_skb */
101 params->lro_wqe_sz -= MLX5_RX_HEADROOM +
102 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
105 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
106 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
107 BIT(params->log_rq_size),
108 BIT(params->mpwqe_log_stride_sz),
109 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
112 static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
114 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
116 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
117 MLX5_WQ_TYPE_LINKED_LIST;
118 mlx5e_set_rq_type_params(mdev, params, rq_type);
121 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
123 struct mlx5_core_dev *mdev = priv->mdev;
126 port_state = mlx5_query_vport_state(mdev,
127 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
129 if (port_state == VPORT_STATE_UP) {
130 netdev_info(priv->netdev, "Link up\n");
131 netif_carrier_on(priv->netdev);
133 netdev_info(priv->netdev, "Link down\n");
134 netif_carrier_off(priv->netdev);
138 static void mlx5e_update_carrier_work(struct work_struct *work)
140 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
141 update_carrier_work);
143 mutex_lock(&priv->state_lock);
144 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
145 mlx5e_update_carrier(priv);
146 mutex_unlock(&priv->state_lock);
149 static void mlx5e_tx_timeout_work(struct work_struct *work)
151 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
156 mutex_lock(&priv->state_lock);
157 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
159 mlx5e_close_locked(priv->netdev);
160 err = mlx5e_open_locked(priv->netdev);
162 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
165 mutex_unlock(&priv->state_lock);
169 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
171 struct mlx5e_sw_stats temp, *s = &temp;
172 struct mlx5e_rq_stats *rq_stats;
173 struct mlx5e_sq_stats *sq_stats;
174 u64 tx_offload_none = 0;
177 memset(s, 0, sizeof(*s));
178 for (i = 0; i < priv->channels.num; i++) {
179 struct mlx5e_channel *c = priv->channels.c[i];
181 rq_stats = &c->rq.stats;
183 s->rx_packets += rq_stats->packets;
184 s->rx_bytes += rq_stats->bytes;
185 s->rx_lro_packets += rq_stats->lro_packets;
186 s->rx_lro_bytes += rq_stats->lro_bytes;
187 s->rx_csum_none += rq_stats->csum_none;
188 s->rx_csum_complete += rq_stats->csum_complete;
189 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
190 s->rx_xdp_drop += rq_stats->xdp_drop;
191 s->rx_xdp_tx += rq_stats->xdp_tx;
192 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
193 s->rx_wqe_err += rq_stats->wqe_err;
194 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
195 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
196 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
197 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
198 s->rx_cache_reuse += rq_stats->cache_reuse;
199 s->rx_cache_full += rq_stats->cache_full;
200 s->rx_cache_empty += rq_stats->cache_empty;
201 s->rx_cache_busy += rq_stats->cache_busy;
203 for (j = 0; j < priv->channels.params.num_tc; j++) {
204 sq_stats = &c->sq[j].stats;
206 s->tx_packets += sq_stats->packets;
207 s->tx_bytes += sq_stats->bytes;
208 s->tx_tso_packets += sq_stats->tso_packets;
209 s->tx_tso_bytes += sq_stats->tso_bytes;
210 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
211 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
212 s->tx_queue_stopped += sq_stats->stopped;
213 s->tx_queue_wake += sq_stats->wake;
214 s->tx_queue_dropped += sq_stats->dropped;
215 s->tx_xmit_more += sq_stats->xmit_more;
216 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
217 tx_offload_none += sq_stats->csum_none;
221 /* Update calculated offload counters */
222 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
223 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
225 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
226 priv->stats.pport.phy_counters,
227 counter_set.phys_layer_cntrs.link_down_events);
228 memcpy(&priv->stats.sw, s, sizeof(*s));
231 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
233 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
234 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
235 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
236 struct mlx5_core_dev *mdev = priv->mdev;
238 MLX5_SET(query_vport_counter_in, in, opcode,
239 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
240 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
241 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
243 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
246 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
248 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
249 struct mlx5_core_dev *mdev = priv->mdev;
250 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
255 in = kvzalloc(sz, GFP_KERNEL);
259 MLX5_SET(ppcnt_reg, in, local_port, 1);
261 out = pstats->IEEE_802_3_counters;
262 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
263 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
265 out = pstats->RFC_2863_counters;
266 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
267 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
269 out = pstats->RFC_2819_counters;
270 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
271 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
273 out = pstats->phy_counters;
274 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
275 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
277 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
278 out = pstats->phy_statistical_counters;
279 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
280 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
283 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
284 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
285 out = pstats->per_prio_counters[prio];
286 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
287 mlx5_core_access_reg(mdev, in, sz, out, sz,
288 MLX5_REG_PPCNT, 0, 0);
294 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
296 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
298 if (!priv->q_counter)
301 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
302 &qcnt->rx_out_of_buffer);
305 static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
307 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
308 struct mlx5_core_dev *mdev = priv->mdev;
309 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
313 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
316 in = kvzalloc(sz, GFP_KERNEL);
320 out = pcie_stats->pcie_perf_counters;
321 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
322 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
327 void mlx5e_update_stats(struct mlx5e_priv *priv)
329 mlx5e_update_pcie_counters(priv);
330 mlx5e_update_pport_counters(priv);
331 mlx5e_update_vport_counters(priv);
332 mlx5e_update_q_counter(priv);
333 mlx5e_update_sw_counters(priv);
336 void mlx5e_update_stats_work(struct work_struct *work)
338 struct delayed_work *dwork = to_delayed_work(work);
339 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
341 mutex_lock(&priv->state_lock);
342 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
343 priv->profile->update_stats(priv);
344 queue_delayed_work(priv->wq, dwork,
345 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
347 mutex_unlock(&priv->state_lock);
350 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
351 enum mlx5_dev_event event, unsigned long param)
353 struct mlx5e_priv *priv = vpriv;
354 struct ptp_clock_event ptp_event;
355 struct mlx5_eqe *eqe = NULL;
357 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
361 case MLX5_DEV_EVENT_PORT_UP:
362 case MLX5_DEV_EVENT_PORT_DOWN:
363 queue_work(priv->wq, &priv->update_carrier_work);
365 case MLX5_DEV_EVENT_PPS:
366 eqe = (struct mlx5_eqe *)param;
367 ptp_event.type = PTP_CLOCK_EXTTS;
368 ptp_event.index = eqe->data.pps.pin;
369 ptp_event.timestamp =
370 timecounter_cyc2time(&priv->tstamp.clock,
371 be64_to_cpu(eqe->data.pps.time_stamp));
372 mlx5e_pps_event_handler(vpriv, &ptp_event);
379 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
381 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
384 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
386 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
387 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
390 static inline int mlx5e_get_wqe_mtt_sz(void)
392 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
393 * To avoid copying garbage after the mtt array, we allocate
396 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
397 MLX5_UMR_MTT_ALIGNMENT);
400 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
401 struct mlx5e_icosq *sq,
402 struct mlx5e_umr_wqe *wqe,
405 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
406 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
407 struct mlx5_wqe_data_seg *dseg = &wqe->data;
408 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
409 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
410 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
412 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
414 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
415 cseg->imm = rq->mkey_be;
417 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
418 ucseg->xlt_octowords =
419 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
420 ucseg->bsf_octowords =
421 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
422 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
424 dseg->lkey = sq->mkey_be;
425 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
428 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
429 struct mlx5e_channel *c)
431 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
432 int mtt_sz = mlx5e_get_wqe_mtt_sz();
433 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
436 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
437 GFP_KERNEL, cpu_to_node(c->cpu));
441 /* We allocate more than mtt_sz as we will align the pointer */
442 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
443 cpu_to_node(c->cpu));
444 if (unlikely(!rq->mpwqe.mtt_no_align))
445 goto err_free_wqe_info;
447 for (i = 0; i < wq_sz; i++) {
448 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
450 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
452 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
454 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
457 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
464 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
466 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
469 kfree(rq->mpwqe.mtt_no_align);
471 kfree(rq->mpwqe.info);
477 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
479 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
480 int mtt_sz = mlx5e_get_wqe_mtt_sz();
483 for (i = 0; i < wq_sz; i++) {
484 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
486 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
489 kfree(rq->mpwqe.mtt_no_align);
490 kfree(rq->mpwqe.info);
493 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
494 u64 npages, u8 page_shift,
495 struct mlx5_core_mkey *umr_mkey)
497 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
502 if (!MLX5E_VALID_NUM_MTTS(npages))
505 in = kvzalloc(inlen, GFP_KERNEL);
509 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
511 MLX5_SET(mkc, mkc, free, 1);
512 MLX5_SET(mkc, mkc, umr_en, 1);
513 MLX5_SET(mkc, mkc, lw, 1);
514 MLX5_SET(mkc, mkc, lr, 1);
515 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
517 MLX5_SET(mkc, mkc, qpn, 0xffffff);
518 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
519 MLX5_SET64(mkc, mkc, len, npages << page_shift);
520 MLX5_SET(mkc, mkc, translations_octword_size,
521 MLX5_MTT_OCTW(npages));
522 MLX5_SET(mkc, mkc, log_page_size, page_shift);
524 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
530 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
532 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
534 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
537 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
538 struct mlx5e_params *params,
539 struct mlx5e_rq_param *rqp,
542 struct mlx5_core_dev *mdev = c->mdev;
543 void *rqc = rqp->rqc;
544 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
552 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
554 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
559 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
561 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
563 rq->wq_type = params->rq_wq_type;
565 rq->netdev = c->netdev;
566 rq->tstamp = c->tstamp;
571 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
572 if (IS_ERR(rq->xdp_prog)) {
573 err = PTR_ERR(rq->xdp_prog);
575 goto err_rq_wq_destroy;
579 rq->buff.map_dir = DMA_BIDIRECTIONAL;
580 rq->rx_headroom = XDP_PACKET_HEADROOM;
582 rq->buff.map_dir = DMA_FROM_DEVICE;
583 rq->rx_headroom = MLX5_RX_HEADROOM;
586 switch (rq->wq_type) {
587 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
589 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
590 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
592 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
593 if (!rq->handle_rx_cqe) {
595 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
596 goto err_rq_wq_destroy;
599 rq->mpwqe_stride_sz = BIT(params->mpwqe_log_stride_sz);
600 rq->mpwqe_num_strides = BIT(params->mpwqe_log_num_strides);
602 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
603 byte_count = rq->buff.wqe_sz;
605 err = mlx5e_create_rq_umr_mkey(mdev, rq);
607 goto err_rq_wq_destroy;
608 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
610 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
612 goto err_destroy_umr_mkey;
614 default: /* MLX5_WQ_TYPE_LINKED_LIST */
615 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
616 GFP_KERNEL, cpu_to_node(c->cpu));
619 goto err_rq_wq_destroy;
621 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
622 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
624 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
625 if (!rq->handle_rx_cqe) {
628 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
629 goto err_rq_wq_destroy;
632 rq->buff.wqe_sz = params->lro_en ?
634 MLX5E_SW2HW_MTU(c->netdev->mtu);
635 byte_count = rq->buff.wqe_sz;
637 /* calc the required page order */
638 frag_sz = rq->rx_headroom +
639 byte_count /* packet data */ +
640 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
641 frag_sz = SKB_DATA_ALIGN(frag_sz);
643 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
644 rq->buff.page_order = order_base_2(npages);
646 byte_count |= MLX5_HW_START_PADDING;
647 rq->mkey_be = c->mkey_be;
650 for (i = 0; i < wq_sz; i++) {
651 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
653 wqe->data.byte_count = cpu_to_be32(byte_count);
654 wqe->data.lkey = rq->mkey_be;
657 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
658 rq->am.mode = params->rx_cq_period_mode;
659 rq->page_cache.head = 0;
660 rq->page_cache.tail = 0;
664 err_destroy_umr_mkey:
665 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
669 bpf_prog_put(rq->xdp_prog);
670 mlx5_wq_destroy(&rq->wq_ctrl);
675 static void mlx5e_free_rq(struct mlx5e_rq *rq)
680 bpf_prog_put(rq->xdp_prog);
682 switch (rq->wq_type) {
683 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
684 mlx5e_rq_free_mpwqe_info(rq);
685 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
687 default: /* MLX5_WQ_TYPE_LINKED_LIST */
691 for (i = rq->page_cache.head; i != rq->page_cache.tail;
692 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
693 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
695 mlx5e_page_release(rq, dma_info, false);
697 mlx5_wq_destroy(&rq->wq_ctrl);
700 static int mlx5e_create_rq(struct mlx5e_rq *rq,
701 struct mlx5e_rq_param *param)
703 struct mlx5_core_dev *mdev = rq->mdev;
711 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
712 sizeof(u64) * rq->wq_ctrl.buf.npages;
713 in = kvzalloc(inlen, GFP_KERNEL);
717 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
718 wq = MLX5_ADDR_OF(rqc, rqc, wq);
720 memcpy(rqc, param->rqc, sizeof(param->rqc));
722 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
723 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
724 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
725 MLX5_ADAPTER_PAGE_SHIFT);
726 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
728 mlx5_fill_page_array(&rq->wq_ctrl.buf,
729 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
731 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
738 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
741 struct mlx5e_channel *c = rq->channel;
742 struct mlx5_core_dev *mdev = c->mdev;
749 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
750 in = kvzalloc(inlen, GFP_KERNEL);
754 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
756 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
757 MLX5_SET(rqc, rqc, state, next_state);
759 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
766 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
768 struct mlx5e_channel *c = rq->channel;
769 struct mlx5e_priv *priv = c->priv;
770 struct mlx5_core_dev *mdev = priv->mdev;
777 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
778 in = kvzalloc(inlen, GFP_KERNEL);
782 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
784 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
785 MLX5_SET64(modify_rq_in, in, modify_bitmask,
786 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
787 MLX5_SET(rqc, rqc, scatter_fcs, enable);
788 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
790 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
797 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
799 struct mlx5e_channel *c = rq->channel;
800 struct mlx5_core_dev *mdev = c->mdev;
806 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
807 in = kvzalloc(inlen, GFP_KERNEL);
811 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
813 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
814 MLX5_SET64(modify_rq_in, in, modify_bitmask,
815 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
816 MLX5_SET(rqc, rqc, vsd, vsd);
817 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
819 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
826 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
828 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
831 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
833 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
834 struct mlx5e_channel *c = rq->channel;
836 struct mlx5_wq_ll *wq = &rq->wq;
837 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
839 while (time_before(jiffies, exp_time)) {
840 if (wq->cur_sz >= min_wqes)
846 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
847 rq->rqn, wq->cur_sz, min_wqes);
851 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
853 struct mlx5_wq_ll *wq = &rq->wq;
854 struct mlx5e_rx_wqe *wqe;
858 /* UMR WQE (if in progress) is always at wq->head */
859 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
860 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
862 while (!mlx5_wq_ll_is_empty(wq)) {
863 wqe_ix_be = *wq->tail_next;
864 wqe_ix = be16_to_cpu(wqe_ix_be);
865 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
866 rq->dealloc_wqe(rq, wqe_ix);
867 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
868 &wqe->next.next_wqe_index);
872 static int mlx5e_open_rq(struct mlx5e_channel *c,
873 struct mlx5e_params *params,
874 struct mlx5e_rq_param *param,
879 err = mlx5e_alloc_rq(c, params, param, rq);
883 err = mlx5e_create_rq(rq, param);
887 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
891 if (params->rx_am_enabled)
892 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
897 mlx5e_destroy_rq(rq);
904 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
906 struct mlx5e_icosq *sq = &rq->channel->icosq;
907 u16 pi = sq->pc & sq->wq.sz_m1;
908 struct mlx5e_tx_wqe *nopwqe;
910 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
911 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
912 sq->db.ico_wqe[pi].num_wqebbs = 1;
913 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
914 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
917 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
919 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
920 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
923 static void mlx5e_close_rq(struct mlx5e_rq *rq)
925 cancel_work_sync(&rq->am.work);
926 mlx5e_destroy_rq(rq);
927 mlx5e_free_rx_descs(rq);
931 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
936 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
938 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
940 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
943 mlx5e_free_xdpsq_db(sq);
950 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
951 struct mlx5e_params *params,
952 struct mlx5e_sq_param *param,
953 struct mlx5e_xdpsq *sq)
955 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
956 struct mlx5_core_dev *mdev = c->mdev;
960 sq->mkey_be = c->mkey_be;
962 sq->uar_map = mdev->mlx5e_res.bfreg.map;
963 sq->min_inline_mode = params->tx_min_inline_mode;
965 param->wq.db_numa_node = cpu_to_node(c->cpu);
966 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
969 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
971 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
973 goto err_sq_wq_destroy;
978 mlx5_wq_destroy(&sq->wq_ctrl);
983 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
985 mlx5e_free_xdpsq_db(sq);
986 mlx5_wq_destroy(&sq->wq_ctrl);
989 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
991 kfree(sq->db.ico_wqe);
994 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
996 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
998 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1000 if (!sq->db.ico_wqe)
1006 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1007 struct mlx5e_sq_param *param,
1008 struct mlx5e_icosq *sq)
1010 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1011 struct mlx5_core_dev *mdev = c->mdev;
1015 sq->mkey_be = c->mkey_be;
1017 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1019 param->wq.db_numa_node = cpu_to_node(c->cpu);
1020 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1023 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1025 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1027 goto err_sq_wq_destroy;
1029 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
1034 mlx5_wq_destroy(&sq->wq_ctrl);
1039 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1041 mlx5e_free_icosq_db(sq);
1042 mlx5_wq_destroy(&sq->wq_ctrl);
1045 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1047 kfree(sq->db.wqe_info);
1048 kfree(sq->db.dma_fifo);
1051 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1053 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1054 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1056 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1058 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1060 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1061 mlx5e_free_txqsq_db(sq);
1065 sq->dma_fifo_mask = df_sz - 1;
1070 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1072 struct mlx5e_params *params,
1073 struct mlx5e_sq_param *param,
1074 struct mlx5e_txqsq *sq)
1076 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
1077 struct mlx5_core_dev *mdev = c->mdev;
1081 sq->tstamp = c->tstamp;
1082 sq->mkey_be = c->mkey_be;
1084 sq->txq_ix = txq_ix;
1085 sq->uar_map = mdev->mlx5e_res.bfreg.map;
1086 sq->max_inline = params->tx_max_inline;
1087 sq->min_inline_mode = params->tx_min_inline_mode;
1089 param->wq.db_numa_node = cpu_to_node(c->cpu);
1090 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1093 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1095 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1097 goto err_sq_wq_destroy;
1099 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
1104 mlx5_wq_destroy(&sq->wq_ctrl);
1109 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1111 mlx5e_free_txqsq_db(sq);
1112 mlx5_wq_destroy(&sq->wq_ctrl);
1115 struct mlx5e_create_sq_param {
1116 struct mlx5_wq_ctrl *wq_ctrl;
1123 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1124 struct mlx5e_sq_param *param,
1125 struct mlx5e_create_sq_param *csp,
1134 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1135 sizeof(u64) * csp->wq_ctrl->buf.npages;
1136 in = kvzalloc(inlen, GFP_KERNEL);
1140 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1141 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1143 memcpy(sqc, param->sqc, sizeof(param->sqc));
1144 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1145 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1146 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1148 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1149 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1151 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1153 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1154 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1155 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1156 MLX5_ADAPTER_PAGE_SHIFT);
1157 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1159 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1161 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1168 struct mlx5e_modify_sq_param {
1175 static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1176 struct mlx5e_modify_sq_param *p)
1183 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1184 in = kvzalloc(inlen, GFP_KERNEL);
1188 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1190 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1191 MLX5_SET(sqc, sqc, state, p->next_state);
1192 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1193 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1194 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1197 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1204 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1206 mlx5_core_destroy_sq(mdev, sqn);
1209 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1210 struct mlx5e_sq_param *param,
1211 struct mlx5e_create_sq_param *csp,
1214 struct mlx5e_modify_sq_param msp = {0};
1217 err = mlx5e_create_sq(mdev, param, csp, sqn);
1221 msp.curr_state = MLX5_SQC_STATE_RST;
1222 msp.next_state = MLX5_SQC_STATE_RDY;
1223 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1225 mlx5e_destroy_sq(mdev, *sqn);
1230 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1231 struct mlx5e_txqsq *sq, u32 rate);
1233 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1236 struct mlx5e_params *params,
1237 struct mlx5e_sq_param *param,
1238 struct mlx5e_txqsq *sq)
1240 struct mlx5e_create_sq_param csp = {};
1244 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1250 csp.cqn = sq->cq.mcq.cqn;
1251 csp.wq_ctrl = &sq->wq_ctrl;
1252 csp.min_inline_mode = sq->min_inline_mode;
1253 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1255 goto err_free_txqsq;
1257 tx_rate = c->priv->tx_rates[sq->txq_ix];
1259 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1264 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1265 mlx5e_free_txqsq(sq);
1270 static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1272 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1273 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1274 netdev_tx_reset_queue(sq->txq);
1275 netif_tx_start_queue(sq->txq);
1278 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1280 __netif_tx_lock_bh(txq);
1281 netif_tx_stop_queue(txq);
1282 __netif_tx_unlock_bh(txq);
1285 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1287 struct mlx5e_channel *c = sq->channel;
1289 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1290 /* prevent netif_tx_wake_queue */
1291 napi_synchronize(&c->napi);
1293 netif_tx_disable_queue(sq->txq);
1295 /* last doorbell out, godspeed .. */
1296 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1297 struct mlx5e_tx_wqe *nop;
1299 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1300 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1301 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1305 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1307 struct mlx5e_channel *c = sq->channel;
1308 struct mlx5_core_dev *mdev = c->mdev;
1310 mlx5e_destroy_sq(mdev, sq->sqn);
1312 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1313 mlx5e_free_txqsq_descs(sq);
1314 mlx5e_free_txqsq(sq);
1317 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1318 struct mlx5e_params *params,
1319 struct mlx5e_sq_param *param,
1320 struct mlx5e_icosq *sq)
1322 struct mlx5e_create_sq_param csp = {};
1325 err = mlx5e_alloc_icosq(c, param, sq);
1329 csp.cqn = sq->cq.mcq.cqn;
1330 csp.wq_ctrl = &sq->wq_ctrl;
1331 csp.min_inline_mode = params->tx_min_inline_mode;
1332 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1333 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1335 goto err_free_icosq;
1340 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1341 mlx5e_free_icosq(sq);
1346 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1348 struct mlx5e_channel *c = sq->channel;
1350 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1351 napi_synchronize(&c->napi);
1353 mlx5e_destroy_sq(c->mdev, sq->sqn);
1354 mlx5e_free_icosq(sq);
1357 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1358 struct mlx5e_params *params,
1359 struct mlx5e_sq_param *param,
1360 struct mlx5e_xdpsq *sq)
1362 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1363 struct mlx5e_create_sq_param csp = {};
1364 unsigned int inline_hdr_sz = 0;
1368 err = mlx5e_alloc_xdpsq(c, params, param, sq);
1373 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
1374 csp.cqn = sq->cq.mcq.cqn;
1375 csp.wq_ctrl = &sq->wq_ctrl;
1376 csp.min_inline_mode = sq->min_inline_mode;
1377 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1378 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1380 goto err_free_xdpsq;
1382 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1383 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1387 /* Pre initialize fixed WQE fields */
1388 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1389 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1390 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1391 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1392 struct mlx5_wqe_data_seg *dseg;
1394 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1395 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1397 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1398 dseg->lkey = sq->mkey_be;
1404 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1405 mlx5e_free_xdpsq(sq);
1410 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1412 struct mlx5e_channel *c = sq->channel;
1414 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1415 napi_synchronize(&c->napi);
1417 mlx5e_destroy_sq(c->mdev, sq->sqn);
1418 mlx5e_free_xdpsq_descs(sq);
1419 mlx5e_free_xdpsq(sq);
1422 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1423 struct mlx5e_cq_param *param,
1424 struct mlx5e_cq *cq)
1426 struct mlx5_core_cq *mcq = &cq->mcq;
1432 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1437 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1440 mcq->set_ci_db = cq->wq_ctrl.db.db;
1441 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1442 *mcq->set_ci_db = 0;
1444 mcq->vector = param->eq_ix;
1445 mcq->comp = mlx5e_completion_event;
1446 mcq->event = mlx5e_cq_error_event;
1449 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1450 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1460 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1461 struct mlx5e_cq_param *param,
1462 struct mlx5e_cq *cq)
1464 struct mlx5_core_dev *mdev = c->priv->mdev;
1467 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1468 param->wq.db_numa_node = cpu_to_node(c->cpu);
1469 param->eq_ix = c->ix;
1471 err = mlx5e_alloc_cq_common(mdev, param, cq);
1473 cq->napi = &c->napi;
1479 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1481 mlx5_cqwq_destroy(&cq->wq_ctrl);
1484 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1486 struct mlx5_core_dev *mdev = cq->mdev;
1487 struct mlx5_core_cq *mcq = &cq->mcq;
1492 unsigned int irqn_not_used;
1496 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1497 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1498 in = kvzalloc(inlen, GFP_KERNEL);
1502 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1504 memcpy(cqc, param->cqc, sizeof(param->cqc));
1506 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1507 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1509 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1511 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1512 MLX5_SET(cqc, cqc, c_eqn, eqn);
1513 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1514 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1515 MLX5_ADAPTER_PAGE_SHIFT);
1516 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1518 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1530 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1532 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1535 static int mlx5e_open_cq(struct mlx5e_channel *c,
1536 struct mlx5e_cq_moder moder,
1537 struct mlx5e_cq_param *param,
1538 struct mlx5e_cq *cq)
1540 struct mlx5_core_dev *mdev = c->mdev;
1543 err = mlx5e_alloc_cq(c, param, cq);
1547 err = mlx5e_create_cq(cq, param);
1551 if (MLX5_CAP_GEN(mdev, cq_moderation))
1552 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1561 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1563 mlx5e_destroy_cq(cq);
1567 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1569 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1572 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1573 struct mlx5e_params *params,
1574 struct mlx5e_channel_param *cparam)
1579 for (tc = 0; tc < c->num_tc; tc++) {
1580 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1581 &cparam->tx_cq, &c->sq[tc].cq);
1583 goto err_close_tx_cqs;
1589 for (tc--; tc >= 0; tc--)
1590 mlx5e_close_cq(&c->sq[tc].cq);
1595 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1599 for (tc = 0; tc < c->num_tc; tc++)
1600 mlx5e_close_cq(&c->sq[tc].cq);
1603 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1604 struct mlx5e_params *params,
1605 struct mlx5e_channel_param *cparam)
1610 for (tc = 0; tc < params->num_tc; tc++) {
1611 int txq_ix = c->ix + tc * params->num_channels;
1613 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1614 params, &cparam->sq, &c->sq[tc]);
1622 for (tc--; tc >= 0; tc--)
1623 mlx5e_close_txqsq(&c->sq[tc]);
1628 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1632 for (tc = 0; tc < c->num_tc; tc++)
1633 mlx5e_close_txqsq(&c->sq[tc]);
1636 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1637 struct mlx5e_txqsq *sq, u32 rate)
1639 struct mlx5e_priv *priv = netdev_priv(dev);
1640 struct mlx5_core_dev *mdev = priv->mdev;
1641 struct mlx5e_modify_sq_param msp = {0};
1645 if (rate == sq->rate_limit)
1650 /* remove current rl index to free space to next ones */
1651 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1656 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1658 netdev_err(dev, "Failed configuring rate %u: %d\n",
1664 msp.curr_state = MLX5_SQC_STATE_RDY;
1665 msp.next_state = MLX5_SQC_STATE_RDY;
1666 msp.rl_index = rl_index;
1667 msp.rl_update = true;
1668 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1670 netdev_err(dev, "Failed configuring rate %u: %d\n",
1672 /* remove the rate from the table */
1674 mlx5_rl_remove_rate(mdev, rate);
1678 sq->rate_limit = rate;
1682 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1684 struct mlx5e_priv *priv = netdev_priv(dev);
1685 struct mlx5_core_dev *mdev = priv->mdev;
1686 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1689 if (!mlx5_rl_is_supported(mdev)) {
1690 netdev_err(dev, "Rate limiting is not supported on this device\n");
1694 /* rate is given in Mb/sec, HW config is in Kb/sec */
1697 /* Check whether rate in valid range, 0 is always valid */
1698 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1699 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1703 mutex_lock(&priv->state_lock);
1704 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1705 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1707 priv->tx_rates[index] = rate;
1708 mutex_unlock(&priv->state_lock);
1713 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1714 struct mlx5e_params *params,
1715 struct mlx5e_channel_param *cparam,
1716 struct mlx5e_channel **cp)
1718 struct mlx5e_cq_moder icocq_moder = {0, 0};
1719 struct net_device *netdev = priv->netdev;
1720 int cpu = mlx5e_get_cpu(priv, ix);
1721 struct mlx5e_channel *c;
1724 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1729 c->mdev = priv->mdev;
1730 c->tstamp = &priv->tstamp;
1733 c->pdev = &priv->mdev->pdev->dev;
1734 c->netdev = priv->netdev;
1735 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1736 c->num_tc = params->num_tc;
1737 c->xdp = !!params->xdp_prog;
1739 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1741 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1745 err = mlx5e_open_tx_cqs(c, params, cparam);
1747 goto err_close_icosq_cq;
1749 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1751 goto err_close_tx_cqs;
1753 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1754 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1755 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1757 goto err_close_rx_cq;
1759 napi_enable(&c->napi);
1761 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1763 goto err_disable_napi;
1765 err = mlx5e_open_sqs(c, params, cparam);
1767 goto err_close_icosq;
1769 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1773 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1775 goto err_close_xdp_sq;
1782 mlx5e_close_xdpsq(&c->rq.xdpsq);
1788 mlx5e_close_icosq(&c->icosq);
1791 napi_disable(&c->napi);
1793 mlx5e_close_cq(&c->rq.xdpsq.cq);
1796 mlx5e_close_cq(&c->rq.cq);
1799 mlx5e_close_tx_cqs(c);
1802 mlx5e_close_cq(&c->icosq.cq);
1805 netif_napi_del(&c->napi);
1811 static void mlx5e_activate_channel(struct mlx5e_channel *c)
1815 for (tc = 0; tc < c->num_tc; tc++)
1816 mlx5e_activate_txqsq(&c->sq[tc]);
1817 mlx5e_activate_rq(&c->rq);
1818 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1821 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1825 mlx5e_deactivate_rq(&c->rq);
1826 for (tc = 0; tc < c->num_tc; tc++)
1827 mlx5e_deactivate_txqsq(&c->sq[tc]);
1830 static void mlx5e_close_channel(struct mlx5e_channel *c)
1832 mlx5e_close_rq(&c->rq);
1834 mlx5e_close_xdpsq(&c->rq.xdpsq);
1836 mlx5e_close_icosq(&c->icosq);
1837 napi_disable(&c->napi);
1839 mlx5e_close_cq(&c->rq.xdpsq.cq);
1840 mlx5e_close_cq(&c->rq.cq);
1841 mlx5e_close_tx_cqs(c);
1842 mlx5e_close_cq(&c->icosq.cq);
1843 netif_napi_del(&c->napi);
1848 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1849 struct mlx5e_params *params,
1850 struct mlx5e_rq_param *param)
1852 void *rqc = param->rqc;
1853 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1855 switch (params->rq_wq_type) {
1856 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1857 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1858 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
1859 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1861 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1862 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1865 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1866 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1867 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
1868 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1869 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1870 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
1871 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
1873 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1874 param->wq.linear = 1;
1877 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1879 void *rqc = param->rqc;
1880 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1882 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1883 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1886 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1887 struct mlx5e_sq_param *param)
1889 void *sqc = param->sqc;
1890 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1892 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1893 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1895 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1898 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1899 struct mlx5e_params *params,
1900 struct mlx5e_sq_param *param)
1902 void *sqc = param->sqc;
1903 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1905 mlx5e_build_sq_param_common(priv, param);
1906 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1909 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1910 struct mlx5e_cq_param *param)
1912 void *cqc = param->cqc;
1914 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1917 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1918 struct mlx5e_params *params,
1919 struct mlx5e_cq_param *param)
1921 void *cqc = param->cqc;
1924 switch (params->rq_wq_type) {
1925 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1926 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
1928 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1929 log_cq_size = params->log_rq_size;
1932 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1933 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1934 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1935 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1938 mlx5e_build_common_cq_param(priv, param);
1941 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1942 struct mlx5e_params *params,
1943 struct mlx5e_cq_param *param)
1945 void *cqc = param->cqc;
1947 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
1949 mlx5e_build_common_cq_param(priv, param);
1951 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1954 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1956 struct mlx5e_cq_param *param)
1958 void *cqc = param->cqc;
1960 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1962 mlx5e_build_common_cq_param(priv, param);
1964 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1967 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1969 struct mlx5e_sq_param *param)
1971 void *sqc = param->sqc;
1972 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1974 mlx5e_build_sq_param_common(priv, param);
1976 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1977 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1980 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1981 struct mlx5e_params *params,
1982 struct mlx5e_sq_param *param)
1984 void *sqc = param->sqc;
1985 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1987 mlx5e_build_sq_param_common(priv, param);
1988 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1991 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1992 struct mlx5e_params *params,
1993 struct mlx5e_channel_param *cparam)
1995 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1997 mlx5e_build_rq_param(priv, params, &cparam->rq);
1998 mlx5e_build_sq_param(priv, params, &cparam->sq);
1999 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2000 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2001 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2002 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2003 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2006 int mlx5e_open_channels(struct mlx5e_priv *priv,
2007 struct mlx5e_channels *chs)
2009 struct mlx5e_channel_param *cparam;
2013 chs->num = chs->params.num_channels;
2015 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2016 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2017 if (!chs->c || !cparam)
2020 mlx5e_build_channel_param(priv, &chs->params, cparam);
2021 for (i = 0; i < chs->num; i++) {
2022 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2024 goto err_close_channels;
2031 for (i--; i >= 0; i--)
2032 mlx5e_close_channel(chs->c[i]);
2041 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2045 for (i = 0; i < chs->num; i++)
2046 mlx5e_activate_channel(chs->c[i]);
2049 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2054 for (i = 0; i < chs->num; i++) {
2055 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2063 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2067 for (i = 0; i < chs->num; i++)
2068 mlx5e_deactivate_channel(chs->c[i]);
2071 void mlx5e_close_channels(struct mlx5e_channels *chs)
2075 for (i = 0; i < chs->num; i++)
2076 mlx5e_close_channel(chs->c[i]);
2083 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2085 struct mlx5_core_dev *mdev = priv->mdev;
2092 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2093 in = kvzalloc(inlen, GFP_KERNEL);
2097 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2099 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2100 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2102 for (i = 0; i < sz; i++)
2103 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2105 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2107 rqt->enabled = true;
2113 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2115 rqt->enabled = false;
2116 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2119 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2121 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2124 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2126 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2130 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2132 struct mlx5e_rqt *rqt;
2136 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2137 rqt = &priv->direct_tir[ix].rqt;
2138 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2140 goto err_destroy_rqts;
2146 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2147 for (ix--; ix >= 0; ix--)
2148 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2153 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2157 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2158 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2161 static int mlx5e_rx_hash_fn(int hfunc)
2163 return (hfunc == ETH_RSS_HASH_TOP) ?
2164 MLX5_RX_HASH_FN_TOEPLITZ :
2165 MLX5_RX_HASH_FN_INVERTED_XOR8;
2168 static int mlx5e_bits_invert(unsigned long a, int size)
2173 for (i = 0; i < size; i++)
2174 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2179 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2180 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2184 for (i = 0; i < sz; i++) {
2190 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2191 ix = mlx5e_bits_invert(i, ilog2(sz));
2193 ix = priv->channels.params.indirection_rqt[ix];
2194 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2198 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2202 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2203 struct mlx5e_redirect_rqt_param rrp)
2205 struct mlx5_core_dev *mdev = priv->mdev;
2211 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2212 in = kvzalloc(inlen, GFP_KERNEL);
2216 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2218 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2219 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2220 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2221 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2227 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2228 struct mlx5e_redirect_rqt_param rrp)
2233 if (ix >= rrp.rss.channels->num)
2234 return priv->drop_rq.rqn;
2236 return rrp.rss.channels->c[ix]->rq.rqn;
2239 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2240 struct mlx5e_redirect_rqt_param rrp)
2245 if (priv->indir_rqt.enabled) {
2247 rqtn = priv->indir_rqt.rqtn;
2248 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2251 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2252 struct mlx5e_redirect_rqt_param direct_rrp = {
2255 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2259 /* Direct RQ Tables */
2260 if (!priv->direct_tir[ix].rqt.enabled)
2263 rqtn = priv->direct_tir[ix].rqt.rqtn;
2264 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2268 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2269 struct mlx5e_channels *chs)
2271 struct mlx5e_redirect_rqt_param rrp = {
2276 .hfunc = chs->params.rss_hfunc,
2281 mlx5e_redirect_rqts(priv, rrp);
2284 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2286 struct mlx5e_redirect_rqt_param drop_rrp = {
2289 .rqn = priv->drop_rq.rqn,
2293 mlx5e_redirect_rqts(priv, drop_rrp);
2296 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2298 if (!params->lro_en)
2301 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2303 MLX5_SET(tirc, tirc, lro_enable_mask,
2304 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2305 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2306 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2307 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2308 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2311 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2312 enum mlx5e_traffic_types tt,
2315 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2317 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2318 MLX5_HASH_FIELD_SEL_DST_IP)
2320 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2321 MLX5_HASH_FIELD_SEL_DST_IP |\
2322 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2323 MLX5_HASH_FIELD_SEL_L4_DPORT)
2325 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2326 MLX5_HASH_FIELD_SEL_DST_IP |\
2327 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2329 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2330 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2331 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2332 rx_hash_toeplitz_key);
2333 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2334 rx_hash_toeplitz_key);
2336 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2337 memcpy(rss_key, params->toeplitz_hash_key, len);
2341 case MLX5E_TT_IPV4_TCP:
2342 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2343 MLX5_L3_PROT_TYPE_IPV4);
2344 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2345 MLX5_L4_PROT_TYPE_TCP);
2346 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2347 MLX5_HASH_IP_L4PORTS);
2350 case MLX5E_TT_IPV6_TCP:
2351 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2352 MLX5_L3_PROT_TYPE_IPV6);
2353 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2354 MLX5_L4_PROT_TYPE_TCP);
2355 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2356 MLX5_HASH_IP_L4PORTS);
2359 case MLX5E_TT_IPV4_UDP:
2360 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2361 MLX5_L3_PROT_TYPE_IPV4);
2362 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2363 MLX5_L4_PROT_TYPE_UDP);
2364 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2365 MLX5_HASH_IP_L4PORTS);
2368 case MLX5E_TT_IPV6_UDP:
2369 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2370 MLX5_L3_PROT_TYPE_IPV6);
2371 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2372 MLX5_L4_PROT_TYPE_UDP);
2373 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2374 MLX5_HASH_IP_L4PORTS);
2377 case MLX5E_TT_IPV4_IPSEC_AH:
2378 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2379 MLX5_L3_PROT_TYPE_IPV4);
2380 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2381 MLX5_HASH_IP_IPSEC_SPI);
2384 case MLX5E_TT_IPV6_IPSEC_AH:
2385 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2386 MLX5_L3_PROT_TYPE_IPV6);
2387 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2388 MLX5_HASH_IP_IPSEC_SPI);
2391 case MLX5E_TT_IPV4_IPSEC_ESP:
2392 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2393 MLX5_L3_PROT_TYPE_IPV4);
2394 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2395 MLX5_HASH_IP_IPSEC_SPI);
2398 case MLX5E_TT_IPV6_IPSEC_ESP:
2399 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2400 MLX5_L3_PROT_TYPE_IPV6);
2401 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2402 MLX5_HASH_IP_IPSEC_SPI);
2406 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2407 MLX5_L3_PROT_TYPE_IPV4);
2408 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2413 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2414 MLX5_L3_PROT_TYPE_IPV6);
2415 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2419 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2423 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2425 struct mlx5_core_dev *mdev = priv->mdev;
2434 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2435 in = kvzalloc(inlen, GFP_KERNEL);
2439 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2440 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2442 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2444 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2445 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2451 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2452 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2464 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
2466 struct mlx5_core_dev *mdev = priv->mdev;
2467 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
2470 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2474 /* Update vport context MTU */
2475 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2479 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2481 struct mlx5_core_dev *mdev = priv->mdev;
2485 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2486 if (err || !hw_mtu) /* fallback to port oper mtu */
2487 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2489 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2492 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2494 struct net_device *netdev = priv->netdev;
2498 err = mlx5e_set_mtu(priv, netdev->mtu);
2502 mlx5e_query_mtu(priv, &mtu);
2503 if (mtu != netdev->mtu)
2504 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2505 __func__, mtu, netdev->mtu);
2511 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2513 struct mlx5e_priv *priv = netdev_priv(netdev);
2514 int nch = priv->channels.params.num_channels;
2515 int ntc = priv->channels.params.num_tc;
2518 netdev_reset_tc(netdev);
2523 netdev_set_num_tc(netdev, ntc);
2525 /* Map netdev TCs to offset 0
2526 * We have our own UP to TXQ mapping for QoS
2528 for (tc = 0; tc < ntc; tc++)
2529 netdev_set_tc_queue(netdev, tc, nch, 0);
2532 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2534 struct mlx5e_channel *c;
2535 struct mlx5e_txqsq *sq;
2538 for (i = 0; i < priv->channels.num; i++)
2539 for (tc = 0; tc < priv->profile->max_tc; tc++)
2540 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2542 for (i = 0; i < priv->channels.num; i++) {
2543 c = priv->channels.c[i];
2544 for (tc = 0; tc < c->num_tc; tc++) {
2546 priv->txq2sq[sq->txq_ix] = sq;
2551 static bool mlx5e_is_eswitch_vport_mngr(struct mlx5_core_dev *mdev)
2553 return (MLX5_CAP_GEN(mdev, vport_group_manager) &&
2554 MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH);
2557 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2559 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2560 struct net_device *netdev = priv->netdev;
2562 mlx5e_netdev_set_tcs(netdev);
2563 netif_set_real_num_tx_queues(netdev, num_txqs);
2564 netif_set_real_num_rx_queues(netdev, priv->channels.num);
2566 mlx5e_build_channels_tx_maps(priv);
2567 mlx5e_activate_channels(&priv->channels);
2568 netif_tx_start_all_queues(priv->netdev);
2570 if (mlx5e_is_eswitch_vport_mngr(priv->mdev))
2571 mlx5e_add_sqs_fwd_rules(priv);
2573 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2574 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2577 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2579 mlx5e_redirect_rqts_to_drop(priv);
2581 if (mlx5e_is_eswitch_vport_mngr(priv->mdev))
2582 mlx5e_remove_sqs_fwd_rules(priv);
2584 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2585 * polling for inactive tx queues.
2587 netif_tx_stop_all_queues(priv->netdev);
2588 netif_tx_disable(priv->netdev);
2589 mlx5e_deactivate_channels(&priv->channels);
2592 void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2593 struct mlx5e_channels *new_chs,
2594 mlx5e_fp_hw_modify hw_modify)
2596 struct net_device *netdev = priv->netdev;
2599 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2601 netif_carrier_off(netdev);
2603 if (new_num_txqs < netdev->real_num_tx_queues)
2604 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2606 mlx5e_deactivate_priv_channels(priv);
2607 mlx5e_close_channels(&priv->channels);
2609 priv->channels = *new_chs;
2611 /* New channels are ready to roll, modify HW settings if needed */
2615 mlx5e_refresh_tirs(priv, false);
2616 mlx5e_activate_priv_channels(priv);
2618 mlx5e_update_carrier(priv);
2621 int mlx5e_open_locked(struct net_device *netdev)
2623 struct mlx5e_priv *priv = netdev_priv(netdev);
2626 set_bit(MLX5E_STATE_OPENED, &priv->state);
2628 err = mlx5e_open_channels(priv, &priv->channels);
2630 goto err_clear_state_opened_flag;
2632 mlx5e_refresh_tirs(priv, false);
2633 mlx5e_activate_priv_channels(priv);
2634 mlx5e_update_carrier(priv);
2635 mlx5e_timestamp_init(priv);
2637 if (priv->profile->update_stats)
2638 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2642 err_clear_state_opened_flag:
2643 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2647 int mlx5e_open(struct net_device *netdev)
2649 struct mlx5e_priv *priv = netdev_priv(netdev);
2652 mutex_lock(&priv->state_lock);
2653 err = mlx5e_open_locked(netdev);
2654 mutex_unlock(&priv->state_lock);
2659 int mlx5e_close_locked(struct net_device *netdev)
2661 struct mlx5e_priv *priv = netdev_priv(netdev);
2663 /* May already be CLOSED in case a previous configuration operation
2664 * (e.g RX/TX queue size change) that involves close&open failed.
2666 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2669 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2671 mlx5e_timestamp_cleanup(priv);
2672 netif_carrier_off(priv->netdev);
2673 mlx5e_deactivate_priv_channels(priv);
2674 mlx5e_close_channels(&priv->channels);
2679 int mlx5e_close(struct net_device *netdev)
2681 struct mlx5e_priv *priv = netdev_priv(netdev);
2684 if (!netif_device_present(netdev))
2687 mutex_lock(&priv->state_lock);
2688 err = mlx5e_close_locked(netdev);
2689 mutex_unlock(&priv->state_lock);
2694 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2695 struct mlx5e_rq *rq,
2696 struct mlx5e_rq_param *param)
2698 void *rqc = param->rqc;
2699 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2702 param->wq.db_numa_node = param->wq.buf_numa_node;
2704 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
2714 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2715 struct mlx5e_cq *cq,
2716 struct mlx5e_cq_param *param)
2718 return mlx5e_alloc_cq_common(mdev, param, cq);
2721 static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2722 struct mlx5e_rq *drop_rq)
2724 struct mlx5e_cq_param cq_param = {};
2725 struct mlx5e_rq_param rq_param = {};
2726 struct mlx5e_cq *cq = &drop_rq->cq;
2729 mlx5e_build_drop_rq_param(&rq_param);
2731 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2735 err = mlx5e_create_cq(cq, &cq_param);
2739 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2741 goto err_destroy_cq;
2743 err = mlx5e_create_rq(drop_rq, &rq_param);
2750 mlx5e_free_rq(drop_rq);
2753 mlx5e_destroy_cq(cq);
2761 static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2763 mlx5e_destroy_rq(drop_rq);
2764 mlx5e_free_rq(drop_rq);
2765 mlx5e_destroy_cq(&drop_rq->cq);
2766 mlx5e_free_cq(&drop_rq->cq);
2769 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2770 u32 underlay_qpn, u32 *tisn)
2772 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2773 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2775 MLX5_SET(tisc, tisc, prio, tc << 1);
2776 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2777 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2779 if (mlx5_lag_is_lacp_owner(mdev))
2780 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2782 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2785 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2787 mlx5_core_destroy_tis(mdev, tisn);
2790 int mlx5e_create_tises(struct mlx5e_priv *priv)
2795 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2796 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2798 goto err_close_tises;
2804 for (tc--; tc >= 0; tc--)
2805 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2810 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2814 for (tc = 0; tc < priv->profile->max_tc; tc++)
2815 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2818 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2819 enum mlx5e_traffic_types tt,
2822 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2824 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2826 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2827 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2828 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc);
2831 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2833 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2835 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2837 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2838 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2839 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2842 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2844 struct mlx5e_tir *tir;
2851 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2852 in = kvzalloc(inlen, GFP_KERNEL);
2856 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2857 memset(in, 0, inlen);
2858 tir = &priv->indir_tir[tt];
2859 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2860 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2861 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2863 goto err_destroy_tirs;
2871 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2872 for (tt--; tt >= 0; tt--)
2873 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2880 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2882 int nch = priv->profile->max_nch(priv->mdev);
2883 struct mlx5e_tir *tir;
2890 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2891 in = kvzalloc(inlen, GFP_KERNEL);
2895 for (ix = 0; ix < nch; ix++) {
2896 memset(in, 0, inlen);
2897 tir = &priv->direct_tir[ix];
2898 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2899 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2900 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2902 goto err_destroy_ch_tirs;
2909 err_destroy_ch_tirs:
2910 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
2911 for (ix--; ix >= 0; ix--)
2912 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2919 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2923 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2924 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2927 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2929 int nch = priv->profile->max_nch(priv->mdev);
2932 for (i = 0; i < nch; i++)
2933 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2936 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
2941 for (i = 0; i < chs->num; i++) {
2942 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
2950 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
2955 for (i = 0; i < chs->num; i++) {
2956 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
2964 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2966 struct mlx5e_priv *priv = netdev_priv(netdev);
2967 struct mlx5e_channels new_channels = {};
2970 if (tc && tc != MLX5E_MAX_NUM_TC)
2973 mutex_lock(&priv->state_lock);
2975 new_channels.params = priv->channels.params;
2976 new_channels.params.num_tc = tc ? tc : 1;
2978 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
2979 priv->channels.params = new_channels.params;
2983 err = mlx5e_open_channels(priv, &new_channels);
2987 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
2989 mutex_unlock(&priv->state_lock);
2993 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2994 u32 chain_index, __be16 proto,
2995 struct tc_to_netdev *tc)
2997 struct mlx5e_priv *priv = netdev_priv(dev);
2999 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
3006 case TC_SETUP_CLSFLOWER:
3007 switch (tc->cls_flower->command) {
3008 case TC_CLSFLOWER_REPLACE:
3009 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
3010 case TC_CLSFLOWER_DESTROY:
3011 return mlx5e_delete_flower(priv, tc->cls_flower);
3012 case TC_CLSFLOWER_STATS:
3013 return mlx5e_stats_flower(priv, tc->cls_flower);
3020 if (tc->type != TC_SETUP_MQPRIO)
3023 tc->mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3025 return mlx5e_setup_tc(dev, tc->mqprio->num_tc);
3029 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3031 struct mlx5e_priv *priv = netdev_priv(dev);
3032 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3033 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3034 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3036 if (mlx5e_is_uplink_rep(priv)) {
3037 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3038 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3039 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3040 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3042 stats->rx_packets = sstats->rx_packets;
3043 stats->rx_bytes = sstats->rx_bytes;
3044 stats->tx_packets = sstats->tx_packets;
3045 stats->tx_bytes = sstats->tx_bytes;
3046 stats->tx_dropped = sstats->tx_queue_dropped;
3049 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3051 stats->rx_length_errors =
3052 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3053 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3054 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3055 stats->rx_crc_errors =
3056 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3057 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3058 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3059 stats->tx_carrier_errors =
3060 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
3061 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3062 stats->rx_frame_errors;
3063 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3065 /* vport multicast also counts packets that are dropped due to steering
3066 * or rx out of buffer
3069 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3073 static void mlx5e_set_rx_mode(struct net_device *dev)
3075 struct mlx5e_priv *priv = netdev_priv(dev);
3077 queue_work(priv->wq, &priv->set_rx_mode_work);
3080 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3082 struct mlx5e_priv *priv = netdev_priv(netdev);
3083 struct sockaddr *saddr = addr;
3085 if (!is_valid_ether_addr(saddr->sa_data))
3086 return -EADDRNOTAVAIL;
3088 netif_addr_lock_bh(netdev);
3089 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3090 netif_addr_unlock_bh(netdev);
3092 queue_work(priv->wq, &priv->set_rx_mode_work);
3097 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
3100 netdev->features |= feature; \
3102 netdev->features &= ~feature; \
3105 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3107 static int set_feature_lro(struct net_device *netdev, bool enable)
3109 struct mlx5e_priv *priv = netdev_priv(netdev);
3110 struct mlx5e_channels new_channels = {};
3114 mutex_lock(&priv->state_lock);
3116 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3117 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3119 new_channels.params = priv->channels.params;
3120 new_channels.params.lro_en = enable;
3123 priv->channels.params = new_channels.params;
3124 err = mlx5e_modify_tirs_lro(priv);
3128 err = mlx5e_open_channels(priv, &new_channels);
3132 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3134 mutex_unlock(&priv->state_lock);
3138 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
3140 struct mlx5e_priv *priv = netdev_priv(netdev);
3143 mlx5e_enable_vlan_filter(priv);
3145 mlx5e_disable_vlan_filter(priv);
3150 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3152 struct mlx5e_priv *priv = netdev_priv(netdev);
3154 if (!enable && mlx5e_tc_num_filters(priv)) {
3156 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3163 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3165 struct mlx5e_priv *priv = netdev_priv(netdev);
3166 struct mlx5_core_dev *mdev = priv->mdev;
3168 return mlx5_set_port_fcs(mdev, !enable);
3171 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3173 struct mlx5e_priv *priv = netdev_priv(netdev);
3176 mutex_lock(&priv->state_lock);
3178 priv->channels.params.scatter_fcs_en = enable;
3179 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3181 priv->channels.params.scatter_fcs_en = !enable;
3183 mutex_unlock(&priv->state_lock);
3188 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3190 struct mlx5e_priv *priv = netdev_priv(netdev);
3193 mutex_lock(&priv->state_lock);
3195 priv->channels.params.vlan_strip_disable = !enable;
3196 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3199 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3201 priv->channels.params.vlan_strip_disable = enable;
3204 mutex_unlock(&priv->state_lock);
3209 #ifdef CONFIG_RFS_ACCEL
3210 static int set_feature_arfs(struct net_device *netdev, bool enable)
3212 struct mlx5e_priv *priv = netdev_priv(netdev);
3216 err = mlx5e_arfs_enable(priv);
3218 err = mlx5e_arfs_disable(priv);
3224 static int mlx5e_handle_feature(struct net_device *netdev,
3225 netdev_features_t wanted_features,
3226 netdev_features_t feature,
3227 mlx5e_feature_handler feature_handler)
3229 netdev_features_t changes = wanted_features ^ netdev->features;
3230 bool enable = !!(wanted_features & feature);
3233 if (!(changes & feature))
3236 err = feature_handler(netdev, enable);
3238 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
3239 enable ? "Enable" : "Disable", feature, err);
3243 MLX5E_SET_FEATURE(netdev, feature, enable);
3247 static int mlx5e_set_features(struct net_device *netdev,
3248 netdev_features_t features)
3252 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3254 err |= mlx5e_handle_feature(netdev, features,
3255 NETIF_F_HW_VLAN_CTAG_FILTER,
3256 set_feature_vlan_filter);
3257 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3258 set_feature_tc_num_filters);
3259 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3260 set_feature_rx_all);
3261 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3262 set_feature_rx_fcs);
3263 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3264 set_feature_rx_vlan);
3265 #ifdef CONFIG_RFS_ACCEL
3266 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3270 return err ? -EINVAL : 0;
3273 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3275 struct mlx5e_priv *priv = netdev_priv(netdev);
3276 struct mlx5e_channels new_channels = {};
3281 mutex_lock(&priv->state_lock);
3283 reset = !priv->channels.params.lro_en &&
3284 (priv->channels.params.rq_wq_type !=
3285 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3287 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3289 curr_mtu = netdev->mtu;
3290 netdev->mtu = new_mtu;
3293 mlx5e_set_dev_port_mtu(priv);
3297 new_channels.params = priv->channels.params;
3298 err = mlx5e_open_channels(priv, &new_channels);
3300 netdev->mtu = curr_mtu;
3304 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
3307 mutex_unlock(&priv->state_lock);
3311 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3315 return mlx5e_hwstamp_set(dev, ifr);
3317 return mlx5e_hwstamp_get(dev, ifr);
3323 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3325 struct mlx5e_priv *priv = netdev_priv(dev);
3326 struct mlx5_core_dev *mdev = priv->mdev;
3328 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3331 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3334 struct mlx5e_priv *priv = netdev_priv(dev);
3335 struct mlx5_core_dev *mdev = priv->mdev;
3337 if (vlan_proto != htons(ETH_P_8021Q))
3338 return -EPROTONOSUPPORT;
3340 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3344 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3346 struct mlx5e_priv *priv = netdev_priv(dev);
3347 struct mlx5_core_dev *mdev = priv->mdev;
3349 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3352 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3354 struct mlx5e_priv *priv = netdev_priv(dev);
3355 struct mlx5_core_dev *mdev = priv->mdev;
3357 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3360 static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3363 struct mlx5e_priv *priv = netdev_priv(dev);
3364 struct mlx5_core_dev *mdev = priv->mdev;
3366 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3367 max_tx_rate, min_tx_rate);
3370 static int mlx5_vport_link2ifla(u8 esw_link)
3373 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3374 return IFLA_VF_LINK_STATE_DISABLE;
3375 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3376 return IFLA_VF_LINK_STATE_ENABLE;
3378 return IFLA_VF_LINK_STATE_AUTO;
3381 static int mlx5_ifla_link2vport(u8 ifla_link)
3383 switch (ifla_link) {
3384 case IFLA_VF_LINK_STATE_DISABLE:
3385 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3386 case IFLA_VF_LINK_STATE_ENABLE:
3387 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3389 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3392 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3395 struct mlx5e_priv *priv = netdev_priv(dev);
3396 struct mlx5_core_dev *mdev = priv->mdev;
3398 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3399 mlx5_ifla_link2vport(link_state));
3402 static int mlx5e_get_vf_config(struct net_device *dev,
3403 int vf, struct ifla_vf_info *ivi)
3405 struct mlx5e_priv *priv = netdev_priv(dev);
3406 struct mlx5_core_dev *mdev = priv->mdev;
3409 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3412 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3416 static int mlx5e_get_vf_stats(struct net_device *dev,
3417 int vf, struct ifla_vf_stats *vf_stats)
3419 struct mlx5e_priv *priv = netdev_priv(dev);
3420 struct mlx5_core_dev *mdev = priv->mdev;
3422 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3426 static void mlx5e_add_vxlan_port(struct net_device *netdev,
3427 struct udp_tunnel_info *ti)
3429 struct mlx5e_priv *priv = netdev_priv(netdev);
3431 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3434 if (!mlx5e_vxlan_allowed(priv->mdev))
3437 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3440 static void mlx5e_del_vxlan_port(struct net_device *netdev,
3441 struct udp_tunnel_info *ti)
3443 struct mlx5e_priv *priv = netdev_priv(netdev);
3445 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3448 if (!mlx5e_vxlan_allowed(priv->mdev))
3451 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3454 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3455 struct sk_buff *skb,
3456 netdev_features_t features)
3458 struct udphdr *udph;
3462 switch (vlan_get_protocol(skb)) {
3463 case htons(ETH_P_IP):
3464 proto = ip_hdr(skb)->protocol;
3466 case htons(ETH_P_IPV6):
3467 proto = ipv6_hdr(skb)->nexthdr;
3473 if (proto == IPPROTO_UDP) {
3474 udph = udp_hdr(skb);
3475 port = be16_to_cpu(udph->dest);
3478 /* Verify if UDP port is being offloaded by HW */
3479 if (port && mlx5e_vxlan_lookup_port(priv, port))
3483 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3484 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3487 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3488 struct net_device *netdev,
3489 netdev_features_t features)
3491 struct mlx5e_priv *priv = netdev_priv(netdev);
3493 features = vlan_features_check(skb, features);
3494 features = vxlan_features_check(skb, features);
3496 /* Validate if the tunneled packet is being offloaded by HW */
3497 if (skb->encapsulation &&
3498 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3499 return mlx5e_vxlan_features_check(priv, skb, features);
3504 static void mlx5e_tx_timeout(struct net_device *dev)
3506 struct mlx5e_priv *priv = netdev_priv(dev);
3507 bool sched_work = false;
3510 netdev_err(dev, "TX timeout detected\n");
3512 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
3513 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3515 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3518 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3519 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3520 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3523 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3524 schedule_work(&priv->tx_timeout_work);
3527 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3529 struct mlx5e_priv *priv = netdev_priv(netdev);
3530 struct bpf_prog *old_prog;
3532 bool reset, was_opened;
3535 mutex_lock(&priv->state_lock);
3537 if ((netdev->features & NETIF_F_LRO) && prog) {
3538 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3543 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3544 /* no need for full reset when exchanging programs */
3545 reset = (!priv->channels.params.xdp_prog || !prog);
3547 if (was_opened && reset)
3548 mlx5e_close_locked(netdev);
3549 if (was_opened && !reset) {
3550 /* num_channels is invariant here, so we can take the
3551 * batched reference right upfront.
3553 prog = bpf_prog_add(prog, priv->channels.num);
3555 err = PTR_ERR(prog);
3560 /* exchange programs, extra prog reference we got from caller
3561 * as long as we don't fail from this point onwards.
3563 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
3565 bpf_prog_put(old_prog);
3567 if (reset) /* change RQ type according to priv->xdp_prog */
3568 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
3570 if (was_opened && reset)
3571 mlx5e_open_locked(netdev);
3573 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3576 /* exchanging programs w/o reset, we update ref counts on behalf
3577 * of the channels RQs here.
3579 for (i = 0; i < priv->channels.num; i++) {
3580 struct mlx5e_channel *c = priv->channels.c[i];
3582 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3583 napi_synchronize(&c->napi);
3584 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3586 old_prog = xchg(&c->rq.xdp_prog, prog);
3588 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3589 /* napi_schedule in case we have missed anything */
3590 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3591 napi_schedule(&c->napi);
3594 bpf_prog_put(old_prog);
3598 mutex_unlock(&priv->state_lock);
3602 static bool mlx5e_xdp_attached(struct net_device *dev)
3604 struct mlx5e_priv *priv = netdev_priv(dev);
3606 return !!priv->channels.params.xdp_prog;
3609 static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3611 switch (xdp->command) {
3612 case XDP_SETUP_PROG:
3613 return mlx5e_xdp_set(dev, xdp->prog);
3614 case XDP_QUERY_PROG:
3615 xdp->prog_attached = mlx5e_xdp_attached(dev);
3622 #ifdef CONFIG_NET_POLL_CONTROLLER
3623 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3624 * reenabling interrupts.
3626 static void mlx5e_netpoll(struct net_device *dev)
3628 struct mlx5e_priv *priv = netdev_priv(dev);
3629 struct mlx5e_channels *chs = &priv->channels;
3633 for (i = 0; i < chs->num; i++)
3634 napi_schedule(&chs->c[i]->napi);
3638 static const struct net_device_ops mlx5e_netdev_ops_basic = {
3639 .ndo_open = mlx5e_open,
3640 .ndo_stop = mlx5e_close,
3641 .ndo_start_xmit = mlx5e_xmit,
3642 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3643 .ndo_select_queue = mlx5e_select_queue,
3644 .ndo_get_stats64 = mlx5e_get_stats,
3645 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3646 .ndo_set_mac_address = mlx5e_set_mac,
3647 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3648 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3649 .ndo_set_features = mlx5e_set_features,
3650 .ndo_change_mtu = mlx5e_change_mtu,
3651 .ndo_do_ioctl = mlx5e_ioctl,
3652 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3653 #ifdef CONFIG_RFS_ACCEL
3654 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3656 .ndo_tx_timeout = mlx5e_tx_timeout,
3657 .ndo_xdp = mlx5e_xdp,
3658 #ifdef CONFIG_NET_POLL_CONTROLLER
3659 .ndo_poll_controller = mlx5e_netpoll,
3663 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3664 .ndo_open = mlx5e_open,
3665 .ndo_stop = mlx5e_close,
3666 .ndo_start_xmit = mlx5e_xmit,
3667 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3668 .ndo_select_queue = mlx5e_select_queue,
3669 .ndo_get_stats64 = mlx5e_get_stats,
3670 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3671 .ndo_set_mac_address = mlx5e_set_mac,
3672 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3673 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3674 .ndo_set_features = mlx5e_set_features,
3675 .ndo_change_mtu = mlx5e_change_mtu,
3676 .ndo_do_ioctl = mlx5e_ioctl,
3677 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3678 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3679 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3680 .ndo_features_check = mlx5e_features_check,
3681 #ifdef CONFIG_RFS_ACCEL
3682 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3684 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3685 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
3686 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
3687 .ndo_set_vf_trust = mlx5e_set_vf_trust,
3688 .ndo_set_vf_rate = mlx5e_set_vf_rate,
3689 .ndo_get_vf_config = mlx5e_get_vf_config,
3690 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3691 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3692 .ndo_tx_timeout = mlx5e_tx_timeout,
3693 .ndo_xdp = mlx5e_xdp,
3694 #ifdef CONFIG_NET_POLL_CONTROLLER
3695 .ndo_poll_controller = mlx5e_netpoll,
3697 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3698 .ndo_get_offload_stats = mlx5e_get_offload_stats,
3701 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3703 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3705 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3706 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3707 !MLX5_CAP_ETH(mdev, csum_cap) ||
3708 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3709 !MLX5_CAP_ETH(mdev, vlan_cap) ||
3710 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3711 MLX5_CAP_FLOWTABLE(mdev,
3712 flow_table_properties_nic_receive.max_ft_level)
3714 mlx5_core_warn(mdev,
3715 "Not creating net device, some required device capabilities are missing\n");
3718 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3719 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
3720 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3721 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
3726 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3728 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3730 return bf_buf_size -
3731 sizeof(struct mlx5e_tx_wqe) +
3732 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3735 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3736 u32 *indirection_rqt, int len,
3739 int node = mdev->priv.numa_node;
3740 int node_num_of_cores;
3744 node = first_online_node;
3746 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3748 if (node_num_of_cores)
3749 num_channels = min_t(int, num_channels, node_num_of_cores);
3751 for (i = 0; i < len; i++)
3752 indirection_rqt[i] = i % num_channels;
3755 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3757 enum pcie_link_width width;
3758 enum pci_bus_speed speed;
3761 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3765 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3769 case PCIE_SPEED_2_5GT:
3770 *pci_bw = 2500 * width;
3772 case PCIE_SPEED_5_0GT:
3773 *pci_bw = 5000 * width;
3775 case PCIE_SPEED_8_0GT:
3776 *pci_bw = 8000 * width;
3785 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3787 return (link_speed && pci_bw &&
3788 (pci_bw < 40000) && (pci_bw < link_speed));
3791 static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
3793 return !(link_speed && pci_bw &&
3794 (pci_bw <= 16000) && (pci_bw < link_speed));
3797 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3799 params->rx_cq_period_mode = cq_period_mode;
3801 params->rx_cq_moderation.pkts =
3802 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3803 params->rx_cq_moderation.usec =
3804 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3806 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3807 params->rx_cq_moderation.usec =
3808 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3810 if (params->rx_am_enabled)
3811 params->rx_cq_moderation =
3812 mlx5e_am_get_def_profile(params->rx_cq_period_mode);
3814 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3815 params->rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3818 u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3822 /* The supported periods are organized in ascending order */
3823 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3824 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3827 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3830 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
3831 struct mlx5e_params *params,
3834 u8 cq_period_mode = 0;
3838 params->num_channels = max_channels;
3841 mlx5e_get_max_linkspeed(mdev, &link_speed);
3842 mlx5e_get_pci_bw(mdev, &pci_bw);
3843 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3844 link_speed, pci_bw);
3847 params->log_sq_size = is_kdump_kernel() ?
3848 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
3849 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3851 /* set CQE compression */
3852 params->rx_cqe_compress_def = false;
3853 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3854 MLX5_CAP_GEN(mdev, vport_group_manager))
3855 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
3857 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
3860 mlx5e_set_rq_params(mdev, params);
3863 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
3864 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
3865 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
3866 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3868 /* CQ moderation params */
3869 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3870 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3871 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3872 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3873 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
3875 params->tx_cq_moderation.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3876 params->tx_cq_moderation.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3879 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3880 mlx5_query_min_inline(mdev, ¶ms->tx_min_inline_mode);
3881 if (params->tx_min_inline_mode == MLX5_INLINE_MODE_NONE &&
3882 !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
3883 params->tx_min_inline_mode = MLX5_INLINE_MODE_L2;
3886 params->rss_hfunc = ETH_RSS_HASH_XOR;
3887 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
3888 mlx5e_build_default_indir_rqt(mdev, params->indirection_rqt,
3889 MLX5E_INDIR_RQT_SIZE, max_channels);
3892 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3893 struct net_device *netdev,
3894 const struct mlx5e_profile *profile,
3897 struct mlx5e_priv *priv = netdev_priv(netdev);
3900 priv->netdev = netdev;
3901 priv->profile = profile;
3902 priv->ppriv = ppriv;
3904 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
3906 mutex_init(&priv->state_lock);
3908 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3909 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3910 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3911 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3914 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3916 struct mlx5e_priv *priv = netdev_priv(netdev);
3918 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3919 if (is_zero_ether_addr(netdev->dev_addr) &&
3920 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3921 eth_hw_addr_random(netdev);
3922 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3926 static const struct switchdev_ops mlx5e_switchdev_ops = {
3927 .switchdev_port_attr_get = mlx5e_attr_get,
3930 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3932 struct mlx5e_priv *priv = netdev_priv(netdev);
3933 struct mlx5_core_dev *mdev = priv->mdev;
3937 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3939 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3940 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3941 #ifdef CONFIG_MLX5_CORE_EN_DCB
3942 if (MLX5_CAP_GEN(mdev, qos))
3943 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3946 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3949 netdev->watchdog_timeo = 15 * HZ;
3951 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3953 netdev->vlan_features |= NETIF_F_SG;
3954 netdev->vlan_features |= NETIF_F_IP_CSUM;
3955 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3956 netdev->vlan_features |= NETIF_F_GRO;
3957 netdev->vlan_features |= NETIF_F_TSO;
3958 netdev->vlan_features |= NETIF_F_TSO6;
3959 netdev->vlan_features |= NETIF_F_RXCSUM;
3960 netdev->vlan_features |= NETIF_F_RXHASH;
3962 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3963 netdev->vlan_features |= NETIF_F_LRO;
3965 netdev->hw_features = netdev->vlan_features;
3966 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
3967 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3968 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3970 if (mlx5e_vxlan_allowed(mdev)) {
3971 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3972 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3973 NETIF_F_GSO_PARTIAL;
3974 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3975 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3976 netdev->hw_enc_features |= NETIF_F_TSO;
3977 netdev->hw_enc_features |= NETIF_F_TSO6;
3978 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3979 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3980 NETIF_F_GSO_PARTIAL;
3981 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3984 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3987 netdev->hw_features |= NETIF_F_RXALL;
3989 if (MLX5_CAP_ETH(mdev, scatter_fcs))
3990 netdev->hw_features |= NETIF_F_RXFCS;
3992 netdev->features = netdev->hw_features;
3993 if (!priv->channels.params.lro_en)
3994 netdev->features &= ~NETIF_F_LRO;
3997 netdev->features &= ~NETIF_F_RXALL;
3999 if (!priv->channels.params.scatter_fcs_en)
4000 netdev->features &= ~NETIF_F_RXFCS;
4002 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4003 if (FT_CAP(flow_modify_en) &&
4004 FT_CAP(modify_root) &&
4005 FT_CAP(identified_miss_table_mode) &&
4006 FT_CAP(flow_table_modify)) {
4007 netdev->hw_features |= NETIF_F_HW_TC;
4008 #ifdef CONFIG_RFS_ACCEL
4009 netdev->hw_features |= NETIF_F_NTUPLE;
4013 netdev->features |= NETIF_F_HIGHDMA;
4015 netdev->priv_flags |= IFF_UNICAST_FLT;
4017 mlx5e_set_netdev_dev_addr(netdev);
4019 #ifdef CONFIG_NET_SWITCHDEV
4020 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4021 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4025 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4027 struct mlx5_core_dev *mdev = priv->mdev;
4030 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4032 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4033 priv->q_counter = 0;
4037 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4039 if (!priv->q_counter)
4042 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4045 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4046 struct net_device *netdev,
4047 const struct mlx5e_profile *profile,
4050 struct mlx5e_priv *priv = netdev_priv(netdev);
4052 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4053 mlx5e_build_nic_netdev(netdev);
4054 mlx5e_vxlan_init(priv);
4057 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4059 mlx5e_vxlan_cleanup(priv);
4061 if (priv->channels.params.xdp_prog)
4062 bpf_prog_put(priv->channels.params.xdp_prog);
4065 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4067 struct mlx5_core_dev *mdev = priv->mdev;
4070 err = mlx5e_create_indirect_rqt(priv);
4074 err = mlx5e_create_direct_rqts(priv);
4076 goto err_destroy_indirect_rqts;
4078 err = mlx5e_create_indirect_tirs(priv);
4080 goto err_destroy_direct_rqts;
4082 err = mlx5e_create_direct_tirs(priv);
4084 goto err_destroy_indirect_tirs;
4086 err = mlx5e_create_flow_steering(priv);
4088 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4089 goto err_destroy_direct_tirs;
4092 err = mlx5e_tc_init(priv);
4094 goto err_destroy_flow_steering;
4098 err_destroy_flow_steering:
4099 mlx5e_destroy_flow_steering(priv);
4100 err_destroy_direct_tirs:
4101 mlx5e_destroy_direct_tirs(priv);
4102 err_destroy_indirect_tirs:
4103 mlx5e_destroy_indirect_tirs(priv);
4104 err_destroy_direct_rqts:
4105 mlx5e_destroy_direct_rqts(priv);
4106 err_destroy_indirect_rqts:
4107 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4111 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4113 mlx5e_tc_cleanup(priv);
4114 mlx5e_destroy_flow_steering(priv);
4115 mlx5e_destroy_direct_tirs(priv);
4116 mlx5e_destroy_indirect_tirs(priv);
4117 mlx5e_destroy_direct_rqts(priv);
4118 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4121 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4125 err = mlx5e_create_tises(priv);
4127 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4131 #ifdef CONFIG_MLX5_CORE_EN_DCB
4132 mlx5e_dcbnl_initialize(priv);
4137 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4139 struct net_device *netdev = priv->netdev;
4140 struct mlx5_core_dev *mdev = priv->mdev;
4143 mlx5e_init_l2_addr(priv);
4145 /* MTU range: 68 - hw-specific max */
4146 netdev->min_mtu = ETH_MIN_MTU;
4147 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4148 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
4149 mlx5e_set_dev_port_mtu(priv);
4151 mlx5_lag_add(mdev, netdev);
4153 mlx5e_enable_async_events(priv);
4155 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4156 mlx5e_register_vport_reps(priv);
4158 if (netdev->reg_state != NETREG_REGISTERED)
4161 /* Device already registered: sync netdev system state */
4162 if (mlx5e_vxlan_allowed(mdev)) {
4164 udp_tunnel_get_rx_info(netdev);
4168 queue_work(priv->wq, &priv->set_rx_mode_work);
4171 if (netif_running(netdev))
4173 netif_device_attach(netdev);
4177 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4179 struct mlx5_core_dev *mdev = priv->mdev;
4182 if (netif_running(priv->netdev))
4183 mlx5e_close(priv->netdev);
4184 netif_device_detach(priv->netdev);
4187 queue_work(priv->wq, &priv->set_rx_mode_work);
4189 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4190 mlx5e_unregister_vport_reps(priv);
4192 mlx5e_disable_async_events(priv);
4193 mlx5_lag_remove(mdev);
4196 static const struct mlx5e_profile mlx5e_nic_profile = {
4197 .init = mlx5e_nic_init,
4198 .cleanup = mlx5e_nic_cleanup,
4199 .init_rx = mlx5e_init_nic_rx,
4200 .cleanup_rx = mlx5e_cleanup_nic_rx,
4201 .init_tx = mlx5e_init_nic_tx,
4202 .cleanup_tx = mlx5e_cleanup_nic_tx,
4203 .enable = mlx5e_nic_enable,
4204 .disable = mlx5e_nic_disable,
4205 .update_stats = mlx5e_update_stats,
4206 .max_nch = mlx5e_get_max_num_channels,
4207 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4208 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4209 .max_tc = MLX5E_MAX_NUM_TC,
4212 /* mlx5e generic netdev management API (move to en_common.c) */
4214 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4215 const struct mlx5e_profile *profile,
4218 int nch = profile->max_nch(mdev);
4219 struct net_device *netdev;
4220 struct mlx5e_priv *priv;
4222 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4223 nch * profile->max_tc,
4226 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4230 #ifdef CONFIG_RFS_ACCEL
4231 netdev->rx_cpu_rmap = mdev->rmap;
4234 profile->init(mdev, netdev, profile, ppriv);
4236 netif_carrier_off(netdev);
4238 priv = netdev_priv(netdev);
4240 priv->wq = create_singlethread_workqueue("mlx5e");
4242 goto err_cleanup_nic;
4247 profile->cleanup(priv);
4248 free_netdev(netdev);
4253 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4255 struct mlx5_core_dev *mdev = priv->mdev;
4256 const struct mlx5e_profile *profile;
4259 profile = priv->profile;
4260 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4262 err = profile->init_tx(priv);
4266 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
4268 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4269 goto err_cleanup_tx;
4272 err = profile->init_rx(priv);
4274 goto err_close_drop_rq;
4276 mlx5e_create_q_counter(priv);
4278 if (profile->enable)
4279 profile->enable(priv);
4284 mlx5e_close_drop_rq(&priv->drop_rq);
4287 profile->cleanup_tx(priv);
4293 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4295 const struct mlx5e_profile *profile = priv->profile;
4297 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4299 if (profile->disable)
4300 profile->disable(priv);
4301 flush_workqueue(priv->wq);
4303 mlx5e_destroy_q_counter(priv);
4304 profile->cleanup_rx(priv);
4305 mlx5e_close_drop_rq(&priv->drop_rq);
4306 profile->cleanup_tx(priv);
4307 cancel_delayed_work_sync(&priv->update_stats_work);
4310 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4312 const struct mlx5e_profile *profile = priv->profile;
4313 struct net_device *netdev = priv->netdev;
4315 destroy_workqueue(priv->wq);
4316 if (profile->cleanup)
4317 profile->cleanup(priv);
4318 free_netdev(netdev);
4321 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4322 * hardware contexts and to connect it to the current netdev.
4324 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4326 struct mlx5e_priv *priv = vpriv;
4327 struct net_device *netdev = priv->netdev;
4330 if (netif_device_present(netdev))
4333 err = mlx5e_create_mdev_resources(mdev);
4337 err = mlx5e_attach_netdev(priv);
4339 mlx5e_destroy_mdev_resources(mdev);
4346 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4348 struct mlx5e_priv *priv = vpriv;
4349 struct net_device *netdev = priv->netdev;
4351 if (!netif_device_present(netdev))
4354 mlx5e_detach_netdev(priv);
4355 mlx5e_destroy_mdev_resources(mdev);
4358 static void *mlx5e_add(struct mlx5_core_dev *mdev)
4360 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4361 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
4362 struct mlx5e_rep_priv *rpriv = NULL;
4366 struct net_device *netdev;
4368 err = mlx5e_check_required_hca_cap(mdev);
4372 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
4373 rpriv = kzalloc(sizeof(*rpriv), GFP_KERNEL);
4375 mlx5_core_warn(mdev,
4376 "Not creating net device, Failed to alloc rep priv data\n");
4379 rpriv->rep = &esw->offloads.vport_reps[0];
4382 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4384 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4385 goto err_unregister_reps;
4388 priv = netdev_priv(netdev);
4390 err = mlx5e_attach(mdev, priv);
4392 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4393 goto err_destroy_netdev;
4396 err = register_netdev(netdev);
4398 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4405 mlx5e_detach(mdev, priv);
4408 mlx5e_destroy_netdev(priv);
4410 err_unregister_reps:
4411 for (vport = 1; vport < total_vfs; vport++)
4412 mlx5_eswitch_unregister_vport_rep(esw, vport);
4418 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4420 struct mlx5e_priv *priv = vpriv;
4421 void *ppriv = priv->ppriv;
4423 unregister_netdev(priv->netdev);
4424 mlx5e_detach(mdev, vpriv);
4425 mlx5e_destroy_netdev(priv);
4429 static void *mlx5e_get_netdev(void *vpriv)
4431 struct mlx5e_priv *priv = vpriv;
4433 return priv->netdev;
4436 static struct mlx5_interface mlx5e_interface = {
4438 .remove = mlx5e_remove,
4439 .attach = mlx5e_attach,
4440 .detach = mlx5e_detach,
4441 .event = mlx5e_async_event,
4442 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4443 .get_dev = mlx5e_get_netdev,
4446 void mlx5e_init(void)
4448 mlx5e_build_ptys2ethtool_map();
4449 mlx5_register_interface(&mlx5e_interface);
4452 void mlx5e_cleanup(void)
4454 mlx5_unregister_interface(&mlx5e_interface);