drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include <net/geneve.h>
  38 #include <linux/bpf.h>
  39 #include <linux/if_bridge.h>
  40 #include <net/page_pool.h>
  41 #include "eswitch.h"
  42 #include "en.h"
  43 #include "en_tc.h"
  44 #include "en_rep.h"
  45 #include "en_accel/ipsec.h"
  46 #include "en_accel/ipsec_rxtx.h"
  47 #include "en_accel/en_accel.h"
  48 #include "en_accel/tls.h"
  49 #include "accel/ipsec.h"
  50 #include "accel/tls.h"
  51 #include "lib/vxlan.h"
  52 #include "lib/clock.h"
  53 #include "en/port.h"
  54 #include "en/xdp.h"
  55 #include "lib/eq.h"
  56 #include "en/monitor_stats.h"
  57 #include "en/reporter.h"
  58
  59 struct mlx5e_rq_param {
  60         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  61         struct mlx5_wq_param    wq;
  62         struct mlx5e_rq_frags_info frags_info;
  63 };
  64
  65 struct mlx5e_sq_param {
  66         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  67         struct mlx5_wq_param       wq;
  68         bool                       is_mpw;
  69 };
  70
  71 struct mlx5e_cq_param {
  72         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  73         struct mlx5_wq_param       wq;
  74         u16                        eq_ix;
  75         u8                         cq_period_mode;
  76 };
  77
  78 struct mlx5e_channel_param {
  79         struct mlx5e_rq_param      rq;
  80         struct mlx5e_sq_param      sq;
  81         struct mlx5e_sq_param      xdp_sq;
  82         struct mlx5e_sq_param      icosq;
  83         struct mlx5e_cq_param      rx_cq;
  84         struct mlx5e_cq_param      tx_cq;
  85         struct mlx5e_cq_param      icosq_cq;
  86 };
  87
  88 bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
  89 {
  90         bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
  91                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
  92                 MLX5_CAP_ETH(mdev, reg_umr_sq);
  93         u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
  94         bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
  95
  96         if (!striding_rq_umr)
  97                 return false;
  98         if (!inline_umr) {
  99                 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
 100                                (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
 101                 return false;
 102         }
 103         return true;
 104 }
 105
 106 static u32 mlx5e_rx_get_linear_frag_sz(struct mlx5e_params *params)
 107 {
 108         u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 109         u16 linear_rq_headroom = params->xdp_prog ?
 110                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 111         u32 frag_sz;
 112
 113         linear_rq_headroom += NET_IP_ALIGN;
 114
 115         frag_sz = MLX5_SKB_FRAG_SZ(linear_rq_headroom + hw_mtu);
 116
 117         if (params->xdp_prog && frag_sz < PAGE_SIZE)
 118                 frag_sz = PAGE_SIZE;
 119
 120         return frag_sz;
 121 }
 122
 123 static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
 124 {
 125         u32 linear_frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 126
 127         return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
 128 }
 129
 130 static bool mlx5e_rx_is_linear_skb(struct mlx5_core_dev *mdev,
 131                                    struct mlx5e_params *params)
 132 {
 133         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 134
 135         return !params->lro_en && frag_sz <= PAGE_SIZE;
 136 }
 137
 138 #define MLX5_MAX_MPWQE_LOG_WQE_STRIDE_SZ ((BIT(__mlx5_bit_sz(wq, log_wqe_stride_size)) - 1) + \
 139                                           MLX5_MPWQE_LOG_STRIDE_SZ_BASE)
 140 static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
 141                                          struct mlx5e_params *params)
 142 {
 143         u32 frag_sz = mlx5e_rx_get_linear_frag_sz(params);
 144         s8 signed_log_num_strides_param;
 145         u8 log_num_strides;
 146
 147         if (!mlx5e_rx_is_linear_skb(mdev, params))
 148                 return false;
 149
 150         if (order_base_2(frag_sz) > MLX5_MAX_MPWQE_LOG_WQE_STRIDE_SZ)
 151                 return false;
 152
 153         if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
 154                 return true;
 155
 156         log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
 157         signed_log_num_strides_param =
 158                 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
 159
 160         return signed_log_num_strides_param >= 0;
 161 }
 162
 163 static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
 164 {
 165         if (params->log_rq_mtu_frames <
 166             mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
 167                 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
 168
 169         return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
 170 }
 171
 172 static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
 173                                           struct mlx5e_params *params)
 174 {
 175         if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
 176                 return order_base_2(mlx5e_rx_get_linear_frag_sz(params));
 177
 178         return MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
 179 }
 180
 181 static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
 182                                           struct mlx5e_params *params)
 183 {
 184         return MLX5_MPWRQ_LOG_WQE_SZ -
 185                 mlx5e_mpwqe_get_log_stride_size(mdev, params);
 186 }
 187
 188 static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
 189                                  struct mlx5e_params *params)
 190 {
 191         u16 linear_rq_headroom = params->xdp_prog ?
 192                 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
 193         bool is_linear_skb;
 194
 195         linear_rq_headroom += NET_IP_ALIGN;
 196
 197         is_linear_skb = (params->rq_wq_type == MLX5_WQ_TYPE_CYCLIC) ?
 198                 mlx5e_rx_is_linear_skb(mdev, params) :
 199                 mlx5e_rx_mpwqe_is_linear_skb(mdev, params);
 200
 201         return is_linear_skb ? linear_rq_headroom : 0;
 202 }
 203
 204 void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
 205                                struct mlx5e_params *params)
 206 {
 207         params->log_rq_mtu_frames = is_kdump_kernel() ?
 208                 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
 209                 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
 210
 211         mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
 212                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
 213                        params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
 214                        BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
 215                        BIT(params->log_rq_mtu_frames),
 216                        BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
 217                        MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
 218 }
 219
 220 bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
 221                                 struct mlx5e_params *params)
 222 {
 223         return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
 224                 !MLX5_IPSEC_DEV(mdev) &&
 225                 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
 226 }
 227
 228 void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
 229 {
 230         params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
 231                 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
 232                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
 233                 MLX5_WQ_TYPE_CYCLIC;
 234 }
 235
 236 void mlx5e_update_carrier(struct mlx5e_priv *priv)
 237 {
 238         struct mlx5_core_dev *mdev = priv->mdev;
 239         u8 port_state;
 240
 241         port_state = mlx5_query_vport_state(mdev,
 242                                             MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT,
 243                                             0);
 244
 245         if (port_state == VPORT_STATE_UP) {
 246                 netdev_info(priv->netdev, "Link up\n");
 247                 netif_carrier_on(priv->netdev);
 248         } else {
 249                 netdev_info(priv->netdev, "Link down\n");
 250                 netif_carrier_off(priv->netdev);
 251         }
 252 }
 253
 254 static void mlx5e_update_carrier_work(struct work_struct *work)
 255 {
 256         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 257                                                update_carrier_work);
 258
 259         mutex_lock(&priv->state_lock);
 260         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 261                 if (priv->profile->update_carrier)
 262                         priv->profile->update_carrier(priv);
 263         mutex_unlock(&priv->state_lock);
 264 }
 265
 266 void mlx5e_update_stats(struct mlx5e_priv *priv)
 267 {
 268         int i;
 269
 270         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 271                 if (mlx5e_stats_grps[i].update_stats)
 272                         mlx5e_stats_grps[i].update_stats(priv);
 273 }
 274
 275 void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
 276 {
 277         int i;
 278
 279         for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
 280                 if (mlx5e_stats_grps[i].update_stats_mask &
 281                     MLX5E_NDO_UPDATE_STATS)
 282                         mlx5e_stats_grps[i].update_stats(priv);
 283 }
 284
 285 static void mlx5e_update_stats_work(struct work_struct *work)
 286 {
 287         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 288                                                update_stats_work);
 289
 290         mutex_lock(&priv->state_lock);
 291         priv->profile->update_stats(priv);
 292         mutex_unlock(&priv->state_lock);
 293 }
 294
 295 void mlx5e_queue_update_stats(struct mlx5e_priv *priv)
 296 {
 297         if (!priv->profile->update_stats)
 298                 return;
 299
 300         if (unlikely(test_bit(MLX5E_STATE_DESTROYING, &priv->state)))
 301                 return;
 302
 303         queue_work(priv->wq, &priv->update_stats_work);
 304 }
 305
 306 static int async_event(struct notifier_block *nb, unsigned long event, void *data)
 307 {
 308         struct mlx5e_priv *priv = container_of(nb, struct mlx5e_priv, events_nb);
 309         struct mlx5_eqe   *eqe = data;
 310
 311         if (event != MLX5_EVENT_TYPE_PORT_CHANGE)
 312                 return NOTIFY_DONE;
 313
 314         switch (eqe->sub_type) {
 315         case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
 316         case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
 317                 queue_work(priv->wq, &priv->update_carrier_work);
 318                 break;
 319         default:
 320                 return NOTIFY_DONE;
 321         }
 322
 323         return NOTIFY_OK;
 324 }
 325
 326 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 327 {
 328         priv->events_nb.notifier_call = async_event;
 329         mlx5_notifier_register(priv->mdev, &priv->events_nb);
 330 }
 331
 332 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 333 {
 334         mlx5_notifier_unregister(priv->mdev, &priv->events_nb);
 335 }
 336
 337 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
 338                                        struct mlx5e_icosq *sq,
 339                                        struct mlx5e_umr_wqe *wqe)
 340 {
 341         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 342         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 343         u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
 344
 345         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 346                                       ds_cnt);
 347         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 348         cseg->imm       = rq->mkey_be;
 349
 350         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
 351         ucseg->xlt_octowords =
 352                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 353         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 354 }
 355
 356 static u32 mlx5e_rqwq_get_size(struct mlx5e_rq *rq)
 357 {
 358         switch (rq->wq_type) {
 359         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 360                 return mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 361         default:
 362                 return mlx5_wq_cyc_get_size(&rq->wqe.wq);
 363         }
 364 }
 365
 366 static u32 mlx5e_rqwq_get_cur_sz(struct mlx5e_rq *rq)
 367 {
 368         switch (rq->wq_type) {
 369         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 370                 return rq->mpwqe.wq.cur_sz;
 371         default:
 372                 return rq->wqe.wq.cur_sz;
 373         }
 374 }
 375
 376 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 377                                      struct mlx5e_channel *c)
 378 {
 379         int wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 380
 381         rq->mpwqe.info = kvzalloc_node(array_size(wq_sz,
 382                                                   sizeof(*rq->mpwqe.info)),
 383                                        GFP_KERNEL, cpu_to_node(c->cpu));
 384         if (!rq->mpwqe.info)
 385                 return -ENOMEM;
 386
 387         mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
 388
 389         return 0;
 390 }
 391
 392 static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
 393                                  u64 npages, u8 page_shift,
 394                                  struct mlx5_core_mkey *umr_mkey)
 395 {
 396         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
 397         void *mkc;
 398         u32 *in;
 399         int err;
 400
 401         in = kvzalloc(inlen, GFP_KERNEL);
 402         if (!in)
 403                 return -ENOMEM;
 404
 405         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 406
 407         MLX5_SET(mkc, mkc, free, 1);
 408         MLX5_SET(mkc, mkc, umr_en, 1);
 409         MLX5_SET(mkc, mkc, lw, 1);
 410         MLX5_SET(mkc, mkc, lr, 1);
 411         MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 412
 413         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 414         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
 415         MLX5_SET64(mkc, mkc, len, npages << page_shift);
 416         MLX5_SET(mkc, mkc, translations_octword_size,
 417                  MLX5_MTT_OCTW(npages));
 418         MLX5_SET(mkc, mkc, log_page_size, page_shift);
 419
 420         err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
 421
 422         kvfree(in);
 423         return err;
 424 }
 425
 426 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
 427 {
 428         u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->mpwqe.wq));
 429
 430         return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
 431 }
 432
 433 static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
 434 {
 435         return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
 436 }
 437
 438 static void mlx5e_init_frags_partition(struct mlx5e_rq *rq)
 439 {
 440         struct mlx5e_wqe_frag_info next_frag, *prev;
 441         int i;
 442
 443         next_frag.di = &rq->wqe.di[0];
 444         next_frag.offset = 0;
 445         prev = NULL;
 446
 447         for (i = 0; i < mlx5_wq_cyc_get_size(&rq->wqe.wq); i++) {
 448                 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
 449                 struct mlx5e_wqe_frag_info *frag =
 450                         &rq->wqe.frags[i << rq->wqe.info.log_num_frags];
 451                 int f;
 452
 453                 for (f = 0; f < rq->wqe.info.num_frags; f++, frag++) {
 454                         if (next_frag.offset + frag_info[f].frag_stride > PAGE_SIZE) {
 455                                 next_frag.di++;
 456                                 next_frag.offset = 0;
 457                                 if (prev)
 458                                         prev->last_in_page = true;
 459                         }
 460                         *frag = next_frag;
 461
 462                         /* prepare next */
 463                         next_frag.offset += frag_info[f].frag_stride;
 464                         prev = frag;
 465                 }
 466         }
 467
 468         if (prev)
 469                 prev->last_in_page = true;
 470 }
 471
 472 static int mlx5e_init_di_list(struct mlx5e_rq *rq,
 473                               struct mlx5e_params *params,
 474                               int wq_sz, int cpu)
 475 {
 476         int len = wq_sz << rq->wqe.info.log_num_frags;
 477
 478         rq->wqe.di = kvzalloc_node(array_size(len, sizeof(*rq->wqe.di)),
 479                                    GFP_KERNEL, cpu_to_node(cpu));
 480         if (!rq->wqe.di)
 481                 return -ENOMEM;
 482
 483         mlx5e_init_frags_partition(rq);
 484
 485         return 0;
 486 }
 487
 488 static void mlx5e_free_di_list(struct mlx5e_rq *rq)
 489 {
 490         kvfree(rq->wqe.di);
 491 }
 492
 493 static int mlx5e_alloc_rq(struct mlx5e_channel *c,
 494                           struct mlx5e_params *params,
 495                           struct mlx5e_rq_param *rqp,
 496                           struct mlx5e_rq *rq)
 497 {
 498         struct page_pool_params pp_params = { 0 };
 499         struct mlx5_core_dev *mdev = c->mdev;
 500         void *rqc = rqp->rqc;
 501         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 502         u32 pool_size;
 503         int wq_sz;
 504         int err;
 505         int i;
 506
 507         rqp->wq.db_numa_node = cpu_to_node(c->cpu);
 508
 509         rq->wq_type = params->rq_wq_type;
 510         rq->pdev    = c->pdev;
 511         rq->netdev  = c->netdev;
 512         rq->tstamp  = c->tstamp;
 513         rq->clock   = &mdev->clock;
 514         rq->channel = c;
 515         rq->ix      = c->ix;
 516         rq->mdev    = mdev;
 517         rq->hw_mtu  = MLX5E_SW2HW_MTU(params, params->sw_mtu);
 518         rq->stats   = &c->priv->channel_stats[c->ix].rq;
 519
 520         rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
 521         if (IS_ERR(rq->xdp_prog)) {
 522                 err = PTR_ERR(rq->xdp_prog);
 523                 rq->xdp_prog = NULL;
 524                 goto err_rq_wq_destroy;
 525         }
 526
 527         err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
 528         if (err < 0)
 529                 goto err_rq_wq_destroy;
 530
 531         rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
 532         rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
 533         pool_size = 1 << params->log_rq_mtu_frames;
 534
 535         switch (rq->wq_type) {
 536         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 537                 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->mpwqe.wq,
 538                                         &rq->wq_ctrl);
 539                 if (err)
 540                         return err;
 541
 542                 rq->mpwqe.wq.db = &rq->mpwqe.wq.db[MLX5_RCV_DBR];
 543
 544                 wq_sz = mlx5_wq_ll_get_size(&rq->mpwqe.wq);
 545
 546                 pool_size = MLX5_MPWRQ_PAGES_PER_WQE << mlx5e_mpwqe_get_log_rq_size(params);
 547
 548                 rq->post_wqes = mlx5e_post_rx_mpwqes;
 549                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 550
 551                 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
 552 #ifdef CONFIG_MLX5_EN_IPSEC
 553                 if (MLX5_IPSEC_DEV(mdev)) {
 554                         err = -EINVAL;
 555                         netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
 556                         goto err_rq_wq_destroy;
 557                 }
 558 #endif
 559                 if (!rq->handle_rx_cqe) {
 560                         err = -EINVAL;
 561                         netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
 562                         goto err_rq_wq_destroy;
 563                 }
 564
 565                 rq->mpwqe.skb_from_cqe_mpwrq =
 566                         mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
 567                         mlx5e_skb_from_cqe_mpwrq_linear :
 568                         mlx5e_skb_from_cqe_mpwrq_nonlinear;
 569                 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
 570                 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
 571
 572                 err = mlx5e_create_rq_umr_mkey(mdev, rq);
 573                 if (err)
 574                         goto err_rq_wq_destroy;
 575                 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
 576
 577                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 578                 if (err)
 579                         goto err_free;
 580                 break;
 581         default: /* MLX5_WQ_TYPE_CYCLIC */
 582                 err = mlx5_wq_cyc_create(mdev, &rqp->wq, rqc_wq, &rq->wqe.wq,
 583                                          &rq->wq_ctrl);
 584                 if (err)
 585                         return err;
 586
 587                 rq->wqe.wq.db = &rq->wqe.wq.db[MLX5_RCV_DBR];
 588
 589                 wq_sz = mlx5_wq_cyc_get_size(&rq->wqe.wq);
 590
 591                 rq->wqe.info = rqp->frags_info;
 592                 rq->wqe.frags =
 593                         kvzalloc_node(array_size(sizeof(*rq->wqe.frags),
 594                                         (wq_sz << rq->wqe.info.log_num_frags)),
 595                                       GFP_KERNEL, cpu_to_node(c->cpu));
 596                 if (!rq->wqe.frags) {
 597                         err = -ENOMEM;
 598                         goto err_free;
 599                 }
 600
 601                 err = mlx5e_init_di_list(rq, params, wq_sz, c->cpu);
 602                 if (err)
 603                         goto err_free;
 604                 rq->post_wqes = mlx5e_post_rx_wqes;
 605                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 606
 607 #ifdef CONFIG_MLX5_EN_IPSEC
 608                 if (c->priv->ipsec)
 609                         rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
 610                 else
 611 #endif
 612                         rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
 613                 if (!rq->handle_rx_cqe) {
 614                         err = -EINVAL;
 615                         netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
 616                         goto err_free;
 617                 }
 618
 619                 rq->wqe.skb_from_cqe = mlx5e_rx_is_linear_skb(mdev, params) ?
 620                         mlx5e_skb_from_cqe_linear :
 621                         mlx5e_skb_from_cqe_nonlinear;
 622                 rq->mkey_be = c->mkey_be;
 623         }
 624
 625         /* Create a page_pool and register it with rxq */
 626         pp_params.order     = 0;
 627         pp_params.flags     = 0; /* No-internal DMA mapping in page_pool */
 628         pp_params.pool_size = pool_size;
 629         pp_params.nid       = cpu_to_node(c->cpu);
 630         pp_params.dev       = c->pdev;
 631         pp_params.dma_dir   = rq->buff.map_dir;
 632
 633         /* page_pool can be used even when there is no rq->xdp_prog,
 634          * given page_pool does not handle DMA mapping there is no
 635          * required state to clear. And page_pool gracefully handle
 636          * elevated refcnt.
 637          */
 638         rq->page_pool = page_pool_create(&pp_params);
 639         if (IS_ERR(rq->page_pool)) {
 640                 err = PTR_ERR(rq->page_pool);
 641                 rq->page_pool = NULL;
 642                 goto err_free;
 643         }
 644         err = xdp_rxq_info_reg_mem_model(&rq->xdp_rxq,
 645                                          MEM_TYPE_PAGE_POOL, rq->page_pool);
 646         if (err)
 647                 goto err_free;
 648
 649         for (i = 0; i < wq_sz; i++) {
 650                 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 651                         struct mlx5e_rx_wqe_ll *wqe =
 652                                 mlx5_wq_ll_get_wqe(&rq->mpwqe.wq, i);
 653                         u32 byte_count =
 654                                 rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
 655                         u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
 656
 657                         wqe->data[0].addr = cpu_to_be64(dma_offset + rq->buff.headroom);
 658                         wqe->data[0].byte_count = cpu_to_be32(byte_count);
 659                         wqe->data[0].lkey = rq->mkey_be;
 660                 } else {
 661                         struct mlx5e_rx_wqe_cyc *wqe =
 662                                 mlx5_wq_cyc_get_wqe(&rq->wqe.wq, i);
 663                         int f;
 664
 665                         for (f = 0; f < rq->wqe.info.num_frags; f++) {
 666                                 u32 frag_size = rq->wqe.info.arr[f].frag_size |
 667                                         MLX5_HW_START_PADDING;
 668
 669                                 wqe->data[f].byte_count = cpu_to_be32(frag_size);
 670                                 wqe->data[f].lkey = rq->mkey_be;
 671                         }
 672                         /* check if num_frags is not a pow of two */
 673                         if (rq->wqe.info.num_frags < (1 << rq->wqe.info.log_num_frags)) {
 674                                 wqe->data[f].byte_count = 0;
 675                                 wqe->data[f].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
 676                                 wqe->data[f].addr = 0;
 677                         }
 678                 }
 679         }
 680
 681         INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
 682
 683         switch (params->rx_cq_moderation.cq_period_mode) {
 684         case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 685                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 686                 break;
 687         case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 688         default:
 689                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 690         }
 691
 692         rq->page_cache.head = 0;
 693         rq->page_cache.tail = 0;
 694
 695         return 0;
 696
 697 err_free:
 698         switch (rq->wq_type) {
 699         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 700                 kvfree(rq->mpwqe.info);
 701                 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
 702                 break;
 703         default: /* MLX5_WQ_TYPE_CYCLIC */
 704                 kvfree(rq->wqe.frags);
 705                 mlx5e_free_di_list(rq);
 706         }
 707
 708 err_rq_wq_destroy:
 709         if (rq->xdp_prog)
 710                 bpf_prog_put(rq->xdp_prog);
 711         xdp_rxq_info_unreg(&rq->xdp_rxq);
 712         if (rq->page_pool)
 713                 page_pool_destroy(rq->page_pool);
 714         mlx5_wq_destroy(&rq->wq_ctrl);
 715
 716         return err;
 717 }
 718
 719 static void mlx5e_free_rq(struct mlx5e_rq *rq)
 720 {
 721         int i;
 722
 723         if (rq->xdp_prog)
 724                 bpf_prog_put(rq->xdp_prog);
 725
 726         xdp_rxq_info_unreg(&rq->xdp_rxq);
 727         if (rq->page_pool)
 728                 page_pool_destroy(rq->page_pool);
 729
 730         switch (rq->wq_type) {
 731         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 732                 kvfree(rq->mpwqe.info);
 733                 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
 734                 break;
 735         default: /* MLX5_WQ_TYPE_CYCLIC */
 736                 kvfree(rq->wqe.frags);
 737                 mlx5e_free_di_list(rq);
 738         }
 739
 740         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 741              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 742                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 743
 744                 mlx5e_page_release(rq, dma_info, false);
 745         }
 746         mlx5_wq_destroy(&rq->wq_ctrl);
 747 }
 748
 749 static int mlx5e_create_rq(struct mlx5e_rq *rq,
 750                            struct mlx5e_rq_param *param)
 751 {
 752         struct mlx5_core_dev *mdev = rq->mdev;
 753
 754         void *in;
 755         void *rqc;
 756         void *wq;
 757         int inlen;
 758         int err;
 759
 760         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 761                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 762         in = kvzalloc(inlen, GFP_KERNEL);
 763         if (!in)
 764                 return -ENOMEM;
 765
 766         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 767         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 768
 769         memcpy(rqc, param->rqc, sizeof(param->rqc));
 770
 771         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 772         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 773         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 774                                                 MLX5_ADAPTER_PAGE_SHIFT);
 775         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 776
 777         mlx5_fill_page_frag_array(&rq->wq_ctrl.buf,
 778                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 779
 780         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 781
 782         kvfree(in);
 783
 784         return err;
 785 }
 786
 787 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 788                                  int next_state)
 789 {
 790         struct mlx5_core_dev *mdev = rq->mdev;
 791
 792         void *in;
 793         void *rqc;
 794         int inlen;
 795         int err;
 796
 797         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 798         in = kvzalloc(inlen, GFP_KERNEL);
 799         if (!in)
 800                 return -ENOMEM;
 801
 802         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 803
 804         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 805         MLX5_SET(rqc, rqc, state, next_state);
 806
 807         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 808
 809         kvfree(in);
 810
 811         return err;
 812 }
 813
 814 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
 815 {
 816         struct mlx5e_channel *c = rq->channel;
 817         struct mlx5e_priv *priv = c->priv;
 818         struct mlx5_core_dev *mdev = priv->mdev;
 819
 820         void *in;
 821         void *rqc;
 822         int inlen;
 823         int err;
 824
 825         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 826         in = kvzalloc(inlen, GFP_KERNEL);
 827         if (!in)
 828                 return -ENOMEM;
 829
 830         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 831
 832         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 833         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 834                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
 835         MLX5_SET(rqc, rqc, scatter_fcs, enable);
 836         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 837
 838         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 839
 840         kvfree(in);
 841
 842         return err;
 843 }
 844
 845 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 846 {
 847         struct mlx5e_channel *c = rq->channel;
 848         struct mlx5_core_dev *mdev = c->mdev;
 849         void *in;
 850         void *rqc;
 851         int inlen;
 852         int err;
 853
 854         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 855         in = kvzalloc(inlen, GFP_KERNEL);
 856         if (!in)
 857                 return -ENOMEM;
 858
 859         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 860
 861         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 862         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 863                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 864         MLX5_SET(rqc, rqc, vsd, vsd);
 865         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 866
 867         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 868
 869         kvfree(in);
 870
 871         return err;
 872 }
 873
 874 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 875 {
 876         mlx5_core_destroy_rq(rq->mdev, rq->rqn);
 877 }
 878
 879 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time)
 880 {
 881         unsigned long exp_time = jiffies + msecs_to_jiffies(wait_time);
 882         struct mlx5e_channel *c = rq->channel;
 883
 884         u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5e_rqwq_get_size(rq));
 885
 886         do {
 887                 if (mlx5e_rqwq_get_cur_sz(rq) >= min_wqes)
 888                         return 0;
 889
 890                 msleep(20);
 891         } while (time_before(jiffies, exp_time));
 892
 893         netdev_warn(c->netdev, "Failed to get min RX wqes on Channel[%d] RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
 894                     c->ix, rq->rqn, mlx5e_rqwq_get_cur_sz(rq), min_wqes);
 895
 896         return -ETIMEDOUT;
 897 }
 898
 899 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 900 {
 901         __be16 wqe_ix_be;
 902         u16 wqe_ix;
 903
 904         if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
 905                 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
 906
 907                 /* UMR WQE (if in progress) is always at wq->head */
 908                 if (rq->mpwqe.umr_in_progress)
 909                         rq->dealloc_wqe(rq, wq->head);
 910
 911                 while (!mlx5_wq_ll_is_empty(wq)) {
 912                         struct mlx5e_rx_wqe_ll *wqe;
 913
 914                         wqe_ix_be = *wq->tail_next;
 915                         wqe_ix    = be16_to_cpu(wqe_ix_be);
 916                         wqe       = mlx5_wq_ll_get_wqe(wq, wqe_ix);
 917                         rq->dealloc_wqe(rq, wqe_ix);
 918                         mlx5_wq_ll_pop(wq, wqe_ix_be,
 919                                        &wqe->next.next_wqe_index);
 920                 }
 921         } else {
 922                 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
 923
 924                 while (!mlx5_wq_cyc_is_empty(wq)) {
 925                         wqe_ix = mlx5_wq_cyc_get_tail(wq);
 926                         rq->dealloc_wqe(rq, wqe_ix);
 927                         mlx5_wq_cyc_pop(wq);
 928                 }
 929         }
 930
 931 }
 932
 933 static int mlx5e_open_rq(struct mlx5e_channel *c,
 934                          struct mlx5e_params *params,
 935                          struct mlx5e_rq_param *param,
 936                          struct mlx5e_rq *rq)
 937 {
 938         int err;
 939
 940         err = mlx5e_alloc_rq(c, params, param, rq);
 941         if (err)
 942                 return err;
 943
 944         err = mlx5e_create_rq(rq, param);
 945         if (err)
 946                 goto err_free_rq;
 947
 948         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 949         if (err)
 950                 goto err_destroy_rq;
 951
 952         if (params->rx_dim_enabled)
 953                 __set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 954
 955         /* We disable csum_complete when XDP is enabled since
 956          * XDP programs might manipulate packets which will render
 957          * skb->checksum incorrect.
 958          */
 959         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE) || c->xdp)
 960                 __set_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &c->rq.state);
 961
 962         return 0;
 963
 964 err_destroy_rq:
 965         mlx5e_destroy_rq(rq);
 966 err_free_rq:
 967         mlx5e_free_rq(rq);
 968
 969         return err;
 970 }
 971
 972 static void mlx5e_activate_rq(struct mlx5e_rq *rq)
 973 {
 974         struct mlx5e_icosq *sq = &rq->channel->icosq;
 975         struct mlx5_wq_cyc *wq = &sq->wq;
 976         struct mlx5e_tx_wqe *nopwqe;
 977
 978         u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
 979
 980         set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 981         sq->db.ico_wqe[pi].opcode     = MLX5_OPCODE_NOP;
 982         nopwqe = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
 983         mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
 984 }
 985
 986 static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
 987 {
 988         clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
 989         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 990 }
 991
 992 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 993 {
 994         cancel_work_sync(&rq->dim.work);
 995         mlx5e_destroy_rq(rq);
 996         mlx5e_free_rx_descs(rq);
 997         mlx5e_free_rq(rq);
 998 }
 999
1000 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
1001 {
1002         kvfree(sq->db.xdpi_fifo.xi);
1003         kvfree(sq->db.wqe_info);
1004 }
1005
1006 static int mlx5e_alloc_xdpsq_fifo(struct mlx5e_xdpsq *sq, int numa)
1007 {
1008         struct mlx5e_xdp_info_fifo *xdpi_fifo = &sq->db.xdpi_fifo;
1009         int wq_sz        = mlx5_wq_cyc_get_size(&sq->wq);
1010         int dsegs_per_wq = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1011
1012         xdpi_fifo->xi = kvzalloc_node(sizeof(*xdpi_fifo->xi) * dsegs_per_wq,
1013                                       GFP_KERNEL, numa);
1014         if (!xdpi_fifo->xi)
1015                 return -ENOMEM;
1016
1017         xdpi_fifo->pc   = &sq->xdpi_fifo_pc;
1018         xdpi_fifo->cc   = &sq->xdpi_fifo_cc;
1019         xdpi_fifo->mask = dsegs_per_wq - 1;
1020
1021         return 0;
1022 }
1023
1024 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
1025 {
1026         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1027         int err;
1028
1029         sq->db.wqe_info = kvzalloc_node(sizeof(*sq->db.wqe_info) * wq_sz,
1030                                         GFP_KERNEL, numa);
1031         if (!sq->db.wqe_info)
1032                 return -ENOMEM;
1033
1034         err = mlx5e_alloc_xdpsq_fifo(sq, numa);
1035         if (err) {
1036                 mlx5e_free_xdpsq_db(sq);
1037                 return err;
1038         }
1039
1040         return 0;
1041 }
1042
1043 static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
1044                              struct mlx5e_params *params,
1045                              struct mlx5e_sq_param *param,
1046                              struct mlx5e_xdpsq *sq,
1047                              bool is_redirect)
1048 {
1049         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1050         struct mlx5_core_dev *mdev = c->mdev;
1051         struct mlx5_wq_cyc *wq = &sq->wq;
1052         int err;
1053
1054         sq->pdev      = c->pdev;
1055         sq->mkey_be   = c->mkey_be;
1056         sq->channel   = c;
1057         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1058         sq->min_inline_mode = params->tx_min_inline_mode;
1059         sq->hw_mtu    = MLX5E_SW2HW_MTU(params, params->sw_mtu);
1060         sq->stats     = is_redirect ?
1061                 &c->priv->channel_stats[c->ix].xdpsq :
1062                 &c->priv->channel_stats[c->ix].rq_xdpsq;
1063
1064         param->wq.db_numa_node = cpu_to_node(c->cpu);
1065         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1066         if (err)
1067                 return err;
1068         wq->db = &wq->db[MLX5_SND_DBR];
1069
1070         err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
1071         if (err)
1072                 goto err_sq_wq_destroy;
1073
1074         return 0;
1075
1076 err_sq_wq_destroy:
1077         mlx5_wq_destroy(&sq->wq_ctrl);
1078
1079         return err;
1080 }
1081
1082 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1083 {
1084         mlx5e_free_xdpsq_db(sq);
1085         mlx5_wq_destroy(&sq->wq_ctrl);
1086 }
1087
1088 static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
1089 {
1090         kvfree(sq->db.ico_wqe);
1091 }
1092
1093 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
1094 {
1095         u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1096
1097         sq->db.ico_wqe = kvzalloc_node(array_size(wq_sz,
1098                                                   sizeof(*sq->db.ico_wqe)),
1099                                        GFP_KERNEL, numa);
1100         if (!sq->db.ico_wqe)
1101                 return -ENOMEM;
1102
1103         return 0;
1104 }
1105
1106 static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
1107                              struct mlx5e_sq_param *param,
1108                              struct mlx5e_icosq *sq)
1109 {
1110         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1111         struct mlx5_core_dev *mdev = c->mdev;
1112         struct mlx5_wq_cyc *wq = &sq->wq;
1113         int err;
1114
1115         sq->channel   = c;
1116         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1117
1118         param->wq.db_numa_node = cpu_to_node(c->cpu);
1119         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1120         if (err)
1121                 return err;
1122         wq->db = &wq->db[MLX5_SND_DBR];
1123
1124         err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
1125         if (err)
1126                 goto err_sq_wq_destroy;
1127
1128         return 0;
1129
1130 err_sq_wq_destroy:
1131         mlx5_wq_destroy(&sq->wq_ctrl);
1132
1133         return err;
1134 }
1135
1136 static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
1137 {
1138         mlx5e_free_icosq_db(sq);
1139         mlx5_wq_destroy(&sq->wq_ctrl);
1140 }
1141
1142 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
1143 {
1144         kvfree(sq->db.wqe_info);
1145         kvfree(sq->db.dma_fifo);
1146 }
1147
1148 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
1149 {
1150         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1151         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1152
1153         sq->db.dma_fifo = kvzalloc_node(array_size(df_sz,
1154                                                    sizeof(*sq->db.dma_fifo)),
1155                                         GFP_KERNEL, numa);
1156         sq->db.wqe_info = kvzalloc_node(array_size(wq_sz,
1157                                                    sizeof(*sq->db.wqe_info)),
1158                                         GFP_KERNEL, numa);
1159         if (!sq->db.dma_fifo || !sq->db.wqe_info) {
1160                 mlx5e_free_txqsq_db(sq);
1161                 return -ENOMEM;
1162         }
1163
1164         sq->dma_fifo_mask = df_sz - 1;
1165
1166         return 0;
1167 }
1168
1169 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
1170 static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
1171                              int txq_ix,
1172                              struct mlx5e_params *params,
1173                              struct mlx5e_sq_param *param,
1174                              struct mlx5e_txqsq *sq,
1175                              int tc)
1176 {
1177         void *sqc_wq               = MLX5_ADDR_OF(sqc, param->sqc, wq);
1178         struct mlx5_core_dev *mdev = c->mdev;
1179         struct mlx5_wq_cyc *wq = &sq->wq;
1180         int err;
1181
1182         sq->pdev      = c->pdev;
1183         sq->tstamp    = c->tstamp;
1184         sq->clock     = &mdev->clock;
1185         sq->mkey_be   = c->mkey_be;
1186         sq->channel   = c;
1187         sq->txq_ix    = txq_ix;
1188         sq->uar_map   = mdev->mlx5e_res.bfreg.map;
1189         sq->min_inline_mode = params->tx_min_inline_mode;
1190         sq->stats     = &c->priv->channel_stats[c->ix].sq[tc];
1191         INIT_WORK(&sq->recover_work, mlx5e_tx_err_cqe_work);
1192         if (MLX5_IPSEC_DEV(c->priv->mdev))
1193                 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
1194         if (mlx5_accel_is_tls_device(c->priv->mdev))
1195                 set_bit(MLX5E_SQ_STATE_TLS, &sq->state);
1196
1197         param->wq.db_numa_node = cpu_to_node(c->cpu);
1198         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, wq, &sq->wq_ctrl);
1199         if (err)
1200                 return err;
1201         wq->db    = &wq->db[MLX5_SND_DBR];
1202
1203         err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
1204         if (err)
1205                 goto err_sq_wq_destroy;
1206
1207         INIT_WORK(&sq->dim.work, mlx5e_tx_dim_work);
1208         sq->dim.mode = params->tx_cq_moderation.cq_period_mode;
1209
1210         return 0;
1211
1212 err_sq_wq_destroy:
1213         mlx5_wq_destroy(&sq->wq_ctrl);
1214
1215         return err;
1216 }
1217
1218 static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1219 {
1220         mlx5e_free_txqsq_db(sq);
1221         mlx5_wq_destroy(&sq->wq_ctrl);
1222 }
1223
1224 struct mlx5e_create_sq_param {
1225         struct mlx5_wq_ctrl        *wq_ctrl;
1226         u32                         cqn;
1227         u32                         tisn;
1228         u8                          tis_lst_sz;
1229         u8                          min_inline_mode;
1230 };
1231
1232 static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1233                            struct mlx5e_sq_param *param,
1234                            struct mlx5e_create_sq_param *csp,
1235                            u32 *sqn)
1236 {
1237         void *in;
1238         void *sqc;
1239         void *wq;
1240         int inlen;
1241         int err;
1242
1243         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1244                 sizeof(u64) * csp->wq_ctrl->buf.npages;
1245         in = kvzalloc(inlen, GFP_KERNEL);
1246         if (!in)
1247                 return -ENOMEM;
1248
1249         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1250         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1251
1252         memcpy(sqc, param->sqc, sizeof(param->sqc));
1253         MLX5_SET(sqc,  sqc, tis_lst_sz, csp->tis_lst_sz);
1254         MLX5_SET(sqc,  sqc, tis_num_0, csp->tisn);
1255         MLX5_SET(sqc,  sqc, cqn, csp->cqn);
1256
1257         if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1258                 MLX5_SET(sqc,  sqc, min_wqe_inline_mode, csp->min_inline_mode);
1259
1260         MLX5_SET(sqc,  sqc, state, MLX5_SQC_STATE_RST);
1261         MLX5_SET(sqc,  sqc, flush_in_error_en, 1);
1262
1263         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
1264         MLX5_SET(wq,   wq, uar_page,      mdev->mlx5e_res.bfreg.index);
1265         MLX5_SET(wq,   wq, log_wq_pg_sz,  csp->wq_ctrl->buf.page_shift -
1266                                           MLX5_ADAPTER_PAGE_SHIFT);
1267         MLX5_SET64(wq, wq, dbr_addr,      csp->wq_ctrl->db.dma);
1268
1269         mlx5_fill_page_frag_array(&csp->wq_ctrl->buf,
1270                                   (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1271
1272         err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1273
1274         kvfree(in);
1275
1276         return err;
1277 }
1278
1279 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1280                     struct mlx5e_modify_sq_param *p)
1281 {
1282         void *in;
1283         void *sqc;
1284         int inlen;
1285         int err;
1286
1287         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1288         in = kvzalloc(inlen, GFP_KERNEL);
1289         if (!in)
1290                 return -ENOMEM;
1291
1292         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1293
1294         MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1295         MLX5_SET(sqc, sqc, state, p->next_state);
1296         if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1297                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1298                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, p->rl_index);
1299         }
1300
1301         err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1302
1303         kvfree(in);
1304
1305         return err;
1306 }
1307
1308 static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1309 {
1310         mlx5_core_destroy_sq(mdev, sqn);
1311 }
1312
1313 static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1314                                struct mlx5e_sq_param *param,
1315                                struct mlx5e_create_sq_param *csp,
1316                                u32 *sqn)
1317 {
1318         struct mlx5e_modify_sq_param msp = {0};
1319         int err;
1320
1321         err = mlx5e_create_sq(mdev, param, csp, sqn);
1322         if (err)
1323                 return err;
1324
1325         msp.curr_state = MLX5_SQC_STATE_RST;
1326         msp.next_state = MLX5_SQC_STATE_RDY;
1327         err = mlx5e_modify_sq(mdev, *sqn, &msp);
1328         if (err)
1329                 mlx5e_destroy_sq(mdev, *sqn);
1330
1331         return err;
1332 }
1333
1334 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1335                                 struct mlx5e_txqsq *sq, u32 rate);
1336
1337 static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1338                             u32 tisn,
1339                             int txq_ix,
1340                             struct mlx5e_params *params,
1341                             struct mlx5e_sq_param *param,
1342                             struct mlx5e_txqsq *sq,
1343                             int tc)
1344 {
1345         struct mlx5e_create_sq_param csp = {};
1346         u32 tx_rate;
1347         int err;
1348
1349         err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq, tc);
1350         if (err)
1351                 return err;
1352
1353         csp.tisn            = tisn;
1354         csp.tis_lst_sz      = 1;
1355         csp.cqn             = sq->cq.mcq.cqn;
1356         csp.wq_ctrl         = &sq->wq_ctrl;
1357         csp.min_inline_mode = sq->min_inline_mode;
1358         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1359         if (err)
1360                 goto err_free_txqsq;
1361
1362         tx_rate = c->priv->tx_rates[sq->txq_ix];
1363         if (tx_rate)
1364                 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1365
1366         if (params->tx_dim_enabled)
1367                 sq->state |= BIT(MLX5E_SQ_STATE_AM);
1368
1369         return 0;
1370
1371 err_free_txqsq:
1372         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1373         mlx5e_free_txqsq(sq);
1374
1375         return err;
1376 }
1377
1378 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1379 {
1380         sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1381         clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1382         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1383         netdev_tx_reset_queue(sq->txq);
1384         netif_tx_start_queue(sq->txq);
1385 }
1386
1387 void mlx5e_tx_disable_queue(struct netdev_queue *txq)
1388 {
1389         __netif_tx_lock_bh(txq);
1390         netif_tx_stop_queue(txq);
1391         __netif_tx_unlock_bh(txq);
1392 }
1393
1394 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1395 {
1396         struct mlx5e_channel *c = sq->channel;
1397         struct mlx5_wq_cyc *wq = &sq->wq;
1398
1399         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1400         /* prevent netif_tx_wake_queue */
1401         napi_synchronize(&c->napi);
1402
1403         mlx5e_tx_disable_queue(sq->txq);
1404
1405         /* last doorbell out, godspeed .. */
1406         if (mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1)) {
1407                 u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
1408                 struct mlx5e_tx_wqe *nop;
1409
1410                 sq->db.wqe_info[pi].skb = NULL;
1411                 nop = mlx5e_post_nop(wq, sq->sqn, &sq->pc);
1412                 mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &nop->ctrl);
1413         }
1414 }
1415
1416 static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1417 {
1418         struct mlx5e_channel *c = sq->channel;
1419         struct mlx5_core_dev *mdev = c->mdev;
1420         struct mlx5_rate_limit rl = {0};
1421
1422         cancel_work_sync(&sq->dim.work);
1423         cancel_work_sync(&sq->recover_work);
1424         mlx5e_destroy_sq(mdev, sq->sqn);
1425         if (sq->rate_limit) {
1426                 rl.rate = sq->rate_limit;
1427                 mlx5_rl_remove_rate(mdev, &rl);
1428         }
1429         mlx5e_free_txqsq_descs(sq);
1430         mlx5e_free_txqsq(sq);
1431 }
1432
1433 static void mlx5e_tx_err_cqe_work(struct work_struct *recover_work)
1434 {
1435         struct mlx5e_txqsq *sq = container_of(recover_work, struct mlx5e_txqsq,
1436                                               recover_work);
1437
1438         mlx5e_tx_reporter_err_cqe(sq);
1439 }
1440
1441 static int mlx5e_open_icosq(struct mlx5e_channel *c,
1442                             struct mlx5e_params *params,
1443                             struct mlx5e_sq_param *param,
1444                             struct mlx5e_icosq *sq)
1445 {
1446         struct mlx5e_create_sq_param csp = {};
1447         int err;
1448
1449         err = mlx5e_alloc_icosq(c, param, sq);
1450         if (err)
1451                 return err;
1452
1453         csp.cqn             = sq->cq.mcq.cqn;
1454         csp.wq_ctrl         = &sq->wq_ctrl;
1455         csp.min_inline_mode = params->tx_min_inline_mode;
1456         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1457         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1458         if (err)
1459                 goto err_free_icosq;
1460
1461         return 0;
1462
1463 err_free_icosq:
1464         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1465         mlx5e_free_icosq(sq);
1466
1467         return err;
1468 }
1469
1470 static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1471 {
1472         struct mlx5e_channel *c = sq->channel;
1473
1474         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1475         napi_synchronize(&c->napi);
1476
1477         mlx5e_destroy_sq(c->mdev, sq->sqn);
1478         mlx5e_free_icosq(sq);
1479 }
1480
1481 static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1482                             struct mlx5e_params *params,
1483                             struct mlx5e_sq_param *param,
1484                             struct mlx5e_xdpsq *sq,
1485                             bool is_redirect)
1486 {
1487         struct mlx5e_create_sq_param csp = {};
1488         int err;
1489
1490         err = mlx5e_alloc_xdpsq(c, params, param, sq, is_redirect);
1491         if (err)
1492                 return err;
1493
1494         csp.tis_lst_sz      = 1;
1495         csp.tisn            = c->priv->tisn[0]; /* tc = 0 */
1496         csp.cqn             = sq->cq.mcq.cqn;
1497         csp.wq_ctrl         = &sq->wq_ctrl;
1498         csp.min_inline_mode = sq->min_inline_mode;
1499         set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1500         err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1501         if (err)
1502                 goto err_free_xdpsq;
1503
1504         mlx5e_set_xmit_fp(sq, param->is_mpw);
1505
1506         if (!param->is_mpw) {
1507                 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1508                 unsigned int inline_hdr_sz = 0;
1509                 int i;
1510
1511                 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1512                         inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1513                         ds_cnt++;
1514                 }
1515
1516                 /* Pre initialize fixed WQE fields */
1517                 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1518                         struct mlx5e_xdp_wqe_info *wi  = &sq->db.wqe_info[i];
1519                         struct mlx5e_tx_wqe      *wqe  = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1520                         struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1521                         struct mlx5_wqe_eth_seg  *eseg = &wqe->eth;
1522                         struct mlx5_wqe_data_seg *dseg;
1523
1524                         cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1525                         eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1526
1527                         dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1528                         dseg->lkey = sq->mkey_be;
1529
1530                         wi->num_wqebbs = 1;
1531                         wi->num_ds     = 1;
1532                 }
1533         }
1534
1535         return 0;
1536
1537 err_free_xdpsq:
1538         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1539         mlx5e_free_xdpsq(sq);
1540
1541         return err;
1542 }
1543
1544 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq, struct mlx5e_rq *rq)
1545 {
1546         struct mlx5e_channel *c = sq->channel;
1547
1548         clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1549         napi_synchronize(&c->napi);
1550
1551         mlx5e_destroy_sq(c->mdev, sq->sqn);
1552         mlx5e_free_xdpsq_descs(sq, rq);
1553         mlx5e_free_xdpsq(sq);
1554 }
1555
1556 static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1557                                  struct mlx5e_cq_param *param,
1558                                  struct mlx5e_cq *cq)
1559 {
1560         struct mlx5_core_cq *mcq = &cq->mcq;
1561         int eqn_not_used;
1562         unsigned int irqn;
1563         int err;
1564         u32 i;
1565
1566         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1567         if (err)
1568                 return err;
1569
1570         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1571                                &cq->wq_ctrl);
1572         if (err)
1573                 return err;
1574
1575         mcq->cqe_sz     = 64;
1576         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1577         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1578         *mcq->set_ci_db = 0;
1579         *mcq->arm_db    = 0;
1580         mcq->vector     = param->eq_ix;
1581         mcq->comp       = mlx5e_completion_event;
1582         mcq->event      = mlx5e_cq_error_event;
1583         mcq->irqn       = irqn;
1584
1585         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1586                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1587
1588                 cqe->op_own = 0xf1;
1589         }
1590
1591         cq->mdev = mdev;
1592
1593         return 0;
1594 }
1595
1596 static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1597                           struct mlx5e_cq_param *param,
1598                           struct mlx5e_cq *cq)
1599 {
1600         struct mlx5_core_dev *mdev = c->priv->mdev;
1601         int err;
1602
1603         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1604         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1605         param->eq_ix   = c->ix;
1606
1607         err = mlx5e_alloc_cq_common(mdev, param, cq);
1608
1609         cq->napi    = &c->napi;
1610         cq->channel = c;
1611
1612         return err;
1613 }
1614
1615 static void mlx5e_free_cq(struct mlx5e_cq *cq)
1616 {
1617         mlx5_wq_destroy(&cq->wq_ctrl);
1618 }
1619
1620 static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1621 {
1622         struct mlx5_core_dev *mdev = cq->mdev;
1623         struct mlx5_core_cq *mcq = &cq->mcq;
1624
1625         void *in;
1626         void *cqc;
1627         int inlen;
1628         unsigned int irqn_not_used;
1629         int eqn;
1630         int err;
1631
1632         err = mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1633         if (err)
1634                 return err;
1635
1636         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1637                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1638         in = kvzalloc(inlen, GFP_KERNEL);
1639         if (!in)
1640                 return -ENOMEM;
1641
1642         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1643
1644         memcpy(cqc, param->cqc, sizeof(param->cqc));
1645
1646         mlx5_fill_page_frag_array(&cq->wq_ctrl.buf,
1647                                   (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1648
1649         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1650         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1651         MLX5_SET(cqc,   cqc, uar_page,      mdev->priv.uar->index);
1652         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1653                                             MLX5_ADAPTER_PAGE_SHIFT);
1654         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1655
1656         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1657
1658         kvfree(in);
1659
1660         if (err)
1661                 return err;
1662
1663         mlx5e_cq_arm(cq);
1664
1665         return 0;
1666 }
1667
1668 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1669 {
1670         mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1671 }
1672
1673 static int mlx5e_open_cq(struct mlx5e_channel *c,
1674                          struct net_dim_cq_moder moder,
1675                          struct mlx5e_cq_param *param,
1676                          struct mlx5e_cq *cq)
1677 {
1678         struct mlx5_core_dev *mdev = c->mdev;
1679         int err;
1680
1681         err = mlx5e_alloc_cq(c, param, cq);
1682         if (err)
1683                 return err;
1684
1685         err = mlx5e_create_cq(cq, param);
1686         if (err)
1687                 goto err_free_cq;
1688
1689         if (MLX5_CAP_GEN(mdev, cq_moderation))
1690                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1691         return 0;
1692
1693 err_free_cq:
1694         mlx5e_free_cq(cq);
1695
1696         return err;
1697 }
1698
1699 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1700 {
1701         mlx5e_destroy_cq(cq);
1702         mlx5e_free_cq(cq);
1703 }
1704
1705 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1706                              struct mlx5e_params *params,
1707                              struct mlx5e_channel_param *cparam)
1708 {
1709         int err;
1710         int tc;
1711
1712         for (tc = 0; tc < c->num_tc; tc++) {
1713                 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1714                                     &cparam->tx_cq, &c->sq[tc].cq);
1715                 if (err)
1716                         goto err_close_tx_cqs;
1717         }
1718
1719         return 0;
1720
1721 err_close_tx_cqs:
1722         for (tc--; tc >= 0; tc--)
1723                 mlx5e_close_cq(&c->sq[tc].cq);
1724
1725         return err;
1726 }
1727
1728 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1729 {
1730         int tc;
1731
1732         for (tc = 0; tc < c->num_tc; tc++)
1733                 mlx5e_close_cq(&c->sq[tc].cq);
1734 }
1735
1736 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1737                           struct mlx5e_params *params,
1738                           struct mlx5e_channel_param *cparam)
1739 {
1740         struct mlx5e_priv *priv = c->priv;
1741         int err, tc, max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
1742
1743         for (tc = 0; tc < params->num_tc; tc++) {
1744                 int txq_ix = c->ix + tc * max_nch;
1745
1746                 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1747                                        params, &cparam->sq, &c->sq[tc], tc);
1748                 if (err)
1749                         goto err_close_sqs;
1750         }
1751
1752         return 0;
1753
1754 err_close_sqs:
1755         for (tc--; tc >= 0; tc--)
1756                 mlx5e_close_txqsq(&c->sq[tc]);
1757
1758         return err;
1759 }
1760
1761 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1762 {
1763         int tc;
1764
1765         for (tc = 0; tc < c->num_tc; tc++)
1766                 mlx5e_close_txqsq(&c->sq[tc]);
1767 }
1768
1769 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1770                                 struct mlx5e_txqsq *sq, u32 rate)
1771 {
1772         struct mlx5e_priv *priv = netdev_priv(dev);
1773         struct mlx5_core_dev *mdev = priv->mdev;
1774         struct mlx5e_modify_sq_param msp = {0};
1775         struct mlx5_rate_limit rl = {0};
1776         u16 rl_index = 0;
1777         int err;
1778
1779         if (rate == sq->rate_limit)
1780                 /* nothing to do */
1781                 return 0;
1782
1783         if (sq->rate_limit) {
1784                 rl.rate = sq->rate_limit;
1785                 /* remove current rl index to free space to next ones */
1786                 mlx5_rl_remove_rate(mdev, &rl);
1787         }
1788
1789         sq->rate_limit = 0;
1790
1791         if (rate) {
1792                 rl.rate = rate;
1793                 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1794                 if (err) {
1795                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1796                                    rate, err);
1797                         return err;
1798                 }
1799         }
1800
1801         msp.curr_state = MLX5_SQC_STATE_RDY;
1802         msp.next_state = MLX5_SQC_STATE_RDY;
1803         msp.rl_index   = rl_index;
1804         msp.rl_update  = true;
1805         err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1806         if (err) {
1807                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1808                            rate, err);
1809                 /* remove the rate from the table */
1810                 if (rate)
1811                         mlx5_rl_remove_rate(mdev, &rl);
1812                 return err;
1813         }
1814
1815         sq->rate_limit = rate;
1816         return 0;
1817 }
1818
1819 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1820 {
1821         struct mlx5e_priv *priv = netdev_priv(dev);
1822         struct mlx5_core_dev *mdev = priv->mdev;
1823         struct mlx5e_txqsq *sq = priv->txq2sq[index];
1824         int err = 0;
1825
1826         if (!mlx5_rl_is_supported(mdev)) {
1827                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1828                 return -EINVAL;
1829         }
1830
1831         /* rate is given in Mb/sec, HW config is in Kb/sec */
1832         rate = rate << 10;
1833
1834         /* Check whether rate in valid range, 0 is always valid */
1835         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1836                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1837                 return -ERANGE;
1838         }
1839
1840         mutex_lock(&priv->state_lock);
1841         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1842                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1843         if (!err)
1844                 priv->tx_rates[index] = rate;
1845         mutex_unlock(&priv->state_lock);
1846
1847         return err;
1848 }
1849
1850 static int mlx5e_alloc_xps_cpumask(struct mlx5e_channel *c,
1851                                    struct mlx5e_params *params)
1852 {
1853         int num_comp_vectors = mlx5_comp_vectors_count(c->mdev);
1854         int irq;
1855
1856         if (!zalloc_cpumask_var(&c->xps_cpumask, GFP_KERNEL))
1857                 return -ENOMEM;
1858
1859         for (irq = c->ix; irq < num_comp_vectors; irq += params->num_channels) {
1860                 int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(c->mdev, irq));
1861
1862                 cpumask_set_cpu(cpu, c->xps_cpumask);
1863         }
1864
1865         return 0;
1866 }
1867
1868 static void mlx5e_free_xps_cpumask(struct mlx5e_channel *c)
1869 {
1870         free_cpumask_var(c->xps_cpumask);
1871 }
1872
1873 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1874                               struct mlx5e_params *params,
1875                               struct mlx5e_channel_param *cparam,
1876                               struct mlx5e_channel **cp)
1877 {
1878         int cpu = cpumask_first(mlx5_comp_irq_get_affinity_mask(priv->mdev, ix));
1879         struct net_dim_cq_moder icocq_moder = {0, 0};
1880         struct net_device *netdev = priv->netdev;
1881         struct mlx5e_channel *c;
1882         unsigned int irq;
1883         int err;
1884         int eqn;
1885
1886         err = mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1887         if (err)
1888                 return err;
1889
1890         c = kvzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1891         if (!c)
1892                 return -ENOMEM;
1893
1894         c->priv     = priv;
1895         c->mdev     = priv->mdev;
1896         c->tstamp   = &priv->tstamp;
1897         c->ix       = ix;
1898         c->cpu      = cpu;
1899         c->pdev     = &priv->mdev->pdev->dev;
1900         c->netdev   = priv->netdev;
1901         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1902         c->num_tc   = params->num_tc;
1903         c->xdp      = !!params->xdp_prog;
1904         c->stats    = &priv->channel_stats[ix].ch;
1905         c->irq_desc = irq_to_desc(irq);
1906
1907         err = mlx5e_alloc_xps_cpumask(c, params);
1908         if (err)
1909                 goto err_free_channel;
1910
1911         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1912
1913         err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1914         if (err)
1915                 goto err_napi_del;
1916
1917         err = mlx5e_open_tx_cqs(c, params, cparam);
1918         if (err)
1919                 goto err_close_icosq_cq;
1920
1921         err = mlx5e_open_cq(c, params->tx_cq_moderation, &cparam->tx_cq, &c->xdpsq.cq);
1922         if (err)
1923                 goto err_close_tx_cqs;
1924
1925         err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1926         if (err)
1927                 goto err_close_xdp_tx_cqs;
1928
1929         /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1930         err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1931                                      &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1932         if (err)
1933                 goto err_close_rx_cq;
1934
1935         napi_enable(&c->napi);
1936
1937         err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1938         if (err)
1939                 goto err_disable_napi;
1940
1941         err = mlx5e_open_sqs(c, params, cparam);
1942         if (err)
1943                 goto err_close_icosq;
1944
1945         err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq, false) : 0;
1946         if (err)
1947                 goto err_close_sqs;
1948
1949         err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1950         if (err)
1951                 goto err_close_xdp_sq;
1952
1953         err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->xdpsq, true);
1954         if (err)
1955                 goto err_close_rq;
1956
1957         *cp = c;
1958
1959         return 0;
1960
1961 err_close_rq:
1962         mlx5e_close_rq(&c->rq);
1963
1964 err_close_xdp_sq:
1965         if (c->xdp)
1966                 mlx5e_close_xdpsq(&c->rq.xdpsq, &c->rq);
1967
1968 err_close_sqs:
1969         mlx5e_close_sqs(c);
1970
1971 err_close_icosq:
1972         mlx5e_close_icosq(&c->icosq);
1973
1974 err_disable_napi:
1975         napi_disable(&c->napi);
1976         if (c->xdp)
1977                 mlx5e_close_cq(&c->rq.xdpsq.cq);
1978
1979 err_close_rx_cq:
1980         mlx5e_close_cq(&c->rq.cq);
1981
1982 err_close_xdp_tx_cqs:
1983         mlx5e_close_cq(&c->xdpsq.cq);
1984
1985 err_close_tx_cqs:
1986         mlx5e_close_tx_cqs(c);
1987
1988 err_close_icosq_cq:
1989         mlx5e_close_cq(&c->icosq.cq);
1990
1991 err_napi_del:
1992         netif_napi_del(&c->napi);
1993         mlx5e_free_xps_cpumask(c);
1994
1995 err_free_channel:
1996         kvfree(c);
1997
1998         return err;
1999 }
2000
2001 static void mlx5e_activate_channel(struct mlx5e_channel *c)
2002 {
2003         int tc;
2004
2005         for (tc = 0; tc < c->num_tc; tc++)
2006                 mlx5e_activate_txqsq(&c->sq[tc]);
2007         mlx5e_activate_rq(&c->rq);
2008         netif_set_xps_queue(c->netdev, c->xps_cpumask, c->ix);
2009 }
2010
2011 static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
2012 {
2013         int tc;
2014
2015         mlx5e_deactivate_rq(&c->rq);
2016         for (tc = 0; tc < c->num_tc; tc++)
2017                 mlx5e_deactivate_txqsq(&c->sq[tc]);
2018 }
2019
2020 static void mlx5e_close_channel(struct mlx5e_channel *c)
2021 {
2022         mlx5e_close_xdpsq(&c->xdpsq, NULL);
2023         mlx5e_close_rq(&c->rq);
2024         if (c->xdp)
2025                 mlx5e_close_xdpsq(&c->rq.xdpsq, &c->rq);
2026         mlx5e_close_sqs(c);
2027         mlx5e_close_icosq(&c->icosq);
2028         napi_disable(&c->napi);
2029         if (c->xdp)
2030                 mlx5e_close_cq(&c->rq.xdpsq.cq);
2031         mlx5e_close_cq(&c->rq.cq);
2032         mlx5e_close_cq(&c->xdpsq.cq);
2033         mlx5e_close_tx_cqs(c);
2034         mlx5e_close_cq(&c->icosq.cq);
2035         netif_napi_del(&c->napi);
2036         mlx5e_free_xps_cpumask(c);
2037
2038         kvfree(c);
2039 }
2040
2041 #define DEFAULT_FRAG_SIZE (2048)
2042
2043 static void mlx5e_build_rq_frags_info(struct mlx5_core_dev *mdev,
2044                                       struct mlx5e_params *params,
2045                                       struct mlx5e_rq_frags_info *info)
2046 {
2047         u32 byte_count = MLX5E_SW2HW_MTU(params, params->sw_mtu);
2048         int frag_size_max = DEFAULT_FRAG_SIZE;
2049         u32 buf_size = 0;
2050         int i;
2051
2052 #ifdef CONFIG_MLX5_EN_IPSEC
2053         if (MLX5_IPSEC_DEV(mdev))
2054                 byte_count += MLX5E_METADATA_ETHER_LEN;
2055 #endif
2056
2057         if (mlx5e_rx_is_linear_skb(mdev, params)) {
2058                 int frag_stride;
2059
2060                 frag_stride = mlx5e_rx_get_linear_frag_sz(params);
2061                 frag_stride = roundup_pow_of_two(frag_stride);
2062
2063                 info->arr[0].frag_size = byte_count;
2064                 info->arr[0].frag_stride = frag_stride;
2065                 info->num_frags = 1;
2066                 info->wqe_bulk = PAGE_SIZE / frag_stride;
2067                 goto out;
2068         }
2069
2070         if (byte_count > PAGE_SIZE +
2071             (MLX5E_MAX_RX_FRAGS - 1) * frag_size_max)
2072                 frag_size_max = PAGE_SIZE;
2073
2074         i = 0;
2075         while (buf_size < byte_count) {
2076                 int frag_size = byte_count - buf_size;
2077
2078                 if (i < MLX5E_MAX_RX_FRAGS - 1)
2079                         frag_size = min(frag_size, frag_size_max);
2080
2081                 info->arr[i].frag_size = frag_size;
2082                 info->arr[i].frag_stride = roundup_pow_of_two(frag_size);
2083
2084                 buf_size += frag_size;
2085                 i++;
2086         }
2087         info->num_frags = i;
2088         /* number of different wqes sharing a page */
2089         info->wqe_bulk = 1 + (info->num_frags % 2);
2090
2091 out:
2092         info->wqe_bulk = max_t(u8, info->wqe_bulk, 8);
2093         info->log_num_frags = order_base_2(info->num_frags);
2094 }
2095
2096 static inline u8 mlx5e_get_rqwq_log_stride(u8 wq_type, int ndsegs)
2097 {
2098         int sz = sizeof(struct mlx5_wqe_data_seg) * ndsegs;
2099
2100         switch (wq_type) {
2101         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2102                 sz += sizeof(struct mlx5e_rx_wqe_ll);
2103                 break;
2104         default: /* MLX5_WQ_TYPE_CYCLIC */
2105                 sz += sizeof(struct mlx5e_rx_wqe_cyc);
2106         }
2107
2108         return order_base_2(sz);
2109 }
2110
2111 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
2112                                  struct mlx5e_params *params,
2113                                  struct mlx5e_rq_param *param)
2114 {
2115         struct mlx5_core_dev *mdev = priv->mdev;
2116         void *rqc = param->rqc;
2117         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2118         int ndsegs = 1;
2119
2120         switch (params->rq_wq_type) {
2121         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2122                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
2123                          mlx5e_mpwqe_get_log_num_strides(mdev, params) -
2124                          MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
2125                 MLX5_SET(wq, wq, log_wqe_stride_size,
2126                          mlx5e_mpwqe_get_log_stride_size(mdev, params) -
2127                          MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
2128                 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
2129                 break;
2130         default: /* MLX5_WQ_TYPE_CYCLIC */
2131                 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
2132                 mlx5e_build_rq_frags_info(mdev, params, &param->frags_info);
2133                 ndsegs = param->frags_info.num_frags;
2134         }
2135
2136         MLX5_SET(wq, wq, wq_type,          params->rq_wq_type);
2137         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2138         MLX5_SET(wq, wq, log_wq_stride,
2139                  mlx5e_get_rqwq_log_stride(params->rq_wq_type, ndsegs));
2140         MLX5_SET(wq, wq, pd,               mdev->mlx5e_res.pdn);
2141         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
2142         MLX5_SET(rqc, rqc, vsd,            params->vlan_strip_disable);
2143         MLX5_SET(rqc, rqc, scatter_fcs,    params->scatter_fcs_en);
2144
2145         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2146 }
2147
2148 static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
2149                                       struct mlx5e_rq_param *param)
2150 {
2151         struct mlx5_core_dev *mdev = priv->mdev;
2152         void *rqc = param->rqc;
2153         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2154
2155         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
2156         MLX5_SET(wq, wq, log_wq_stride,
2157                  mlx5e_get_rqwq_log_stride(MLX5_WQ_TYPE_CYCLIC, 1));
2158         MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
2159
2160         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2161 }
2162
2163 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
2164                                         struct mlx5e_sq_param *param)
2165 {
2166         void *sqc = param->sqc;
2167         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2168
2169         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2170         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
2171
2172         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
2173 }
2174
2175 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
2176                                  struct mlx5e_params *params,
2177                                  struct mlx5e_sq_param *param)
2178 {
2179         void *sqc = param->sqc;
2180         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2181         bool allow_swp;
2182
2183         allow_swp = mlx5_geneve_tx_allowed(priv->mdev) ||
2184                     !!MLX5_IPSEC_DEV(priv->mdev);
2185         mlx5e_build_sq_param_common(priv, param);
2186         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2187         MLX5_SET(sqc, sqc, allow_swp, allow_swp);
2188 }
2189
2190 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2191                                         struct mlx5e_cq_param *param)
2192 {
2193         void *cqc = param->cqc;
2194
2195         MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
2196         if (MLX5_CAP_GEN(priv->mdev, cqe_128_always) && cache_line_size() >= 128)
2197                 MLX5_SET(cqc, cqc, cqe_sz, CQE_STRIDE_128_PAD);
2198 }
2199
2200 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2201                                     struct mlx5e_params *params,
2202                                     struct mlx5e_cq_param *param)
2203 {
2204         struct mlx5_core_dev *mdev = priv->mdev;
2205         void *cqc = param->cqc;
2206         u8 log_cq_size;
2207
2208         switch (params->rq_wq_type) {
2209         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2210                 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
2211                         mlx5e_mpwqe_get_log_num_strides(mdev, params);
2212                 break;
2213         default: /* MLX5_WQ_TYPE_CYCLIC */
2214                 log_cq_size = params->log_rq_mtu_frames;
2215         }
2216
2217         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
2218         if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
2219                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
2220                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
2221         }
2222
2223         mlx5e_build_common_cq_param(priv, param);
2224         param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
2225 }
2226
2227 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2228                                     struct mlx5e_params *params,
2229                                     struct mlx5e_cq_param *param)
2230 {
2231         void *cqc = param->cqc;
2232
2233         MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
2234
2235         mlx5e_build_common_cq_param(priv, param);
2236         param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
2237 }
2238
2239 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
2240                                      u8 log_wq_size,
2241                                      struct mlx5e_cq_param *param)
2242 {
2243         void *cqc = param->cqc;
2244
2245         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2246
2247         mlx5e_build_common_cq_param(priv, param);
2248
2249         param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2250 }
2251
2252 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2253                                     u8 log_wq_size,
2254                                     struct mlx5e_sq_param *param)
2255 {
2256         void *sqc = param->sqc;
2257         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2258
2259         mlx5e_build_sq_param_common(priv, param);
2260
2261         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2262         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2263 }
2264
2265 static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2266                                     struct mlx5e_params *params,
2267                                     struct mlx5e_sq_param *param)
2268 {
2269         void *sqc = param->sqc;
2270         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2271
2272         mlx5e_build_sq_param_common(priv, param);
2273         MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2274         param->is_mpw = MLX5E_GET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE);
2275 }
2276
2277 static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2278                                       struct mlx5e_params *params,
2279                                       struct mlx5e_channel_param *cparam)
2280 {
2281         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2282
2283         mlx5e_build_rq_param(priv, params, &cparam->rq);
2284         mlx5e_build_sq_param(priv, params, &cparam->sq);
2285         mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2286         mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2287         mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2288         mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2289         mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2290 }
2291
2292 int mlx5e_open_channels(struct mlx5e_priv *priv,
2293                         struct mlx5e_channels *chs)
2294 {
2295         struct mlx5e_channel_param *cparam;
2296         int err = -ENOMEM;
2297         int i;
2298
2299         chs->num = chs->params.num_channels;
2300
2301         chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2302         cparam = kvzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2303         if (!chs->c || !cparam)
2304                 goto err_free;
2305
2306         mlx5e_build_channel_param(priv, &chs->params, cparam);
2307         for (i = 0; i < chs->num; i++) {
2308                 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2309                 if (err)
2310                         goto err_close_channels;
2311         }
2312
2313         if (!IS_ERR_OR_NULL(priv->tx_reporter))
2314                 devlink_health_reporter_state_update(priv->tx_reporter,
2315                                                      DEVLINK_HEALTH_REPORTER_STATE_HEALTHY);
2316
2317         kvfree(cparam);
2318         return 0;
2319
2320 err_close_channels:
2321         for (i--; i >= 0; i--)
2322                 mlx5e_close_channel(chs->c[i]);
2323
2324 err_free:
2325         kfree(chs->c);
2326         kvfree(cparam);
2327         chs->num = 0;
2328         return err;
2329 }
2330
2331 static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2332 {
2333         int i;
2334
2335         for (i = 0; i < chs->num; i++)
2336                 mlx5e_activate_channel(chs->c[i]);
2337 }
2338
2339 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2340 {
2341         int err = 0;
2342         int i;
2343
2344         for (i = 0; i < chs->num; i++)
2345                 err |= mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq,
2346                                                   err ? 0 : 20000);
2347
2348         return err ? -ETIMEDOUT : 0;
2349 }
2350
2351 static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2352 {
2353         int i;
2354
2355         for (i = 0; i < chs->num; i++)
2356                 mlx5e_deactivate_channel(chs->c[i]);
2357 }
2358
2359 void mlx5e_close_channels(struct mlx5e_channels *chs)
2360 {
2361         int i;
2362
2363         for (i = 0; i < chs->num; i++)
2364                 mlx5e_close_channel(chs->c[i]);
2365
2366         kfree(chs->c);
2367         chs->num = 0;
2368 }
2369
2370 static int
2371 mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2372 {
2373         struct mlx5_core_dev *mdev = priv->mdev;
2374         void *rqtc;
2375         int inlen;
2376         int err;
2377         u32 *in;
2378         int i;
2379
2380         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2381         in = kvzalloc(inlen, GFP_KERNEL);
2382         if (!in)
2383                 return -ENOMEM;
2384
2385         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2386
2387         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2388         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2389
2390         for (i = 0; i < sz; i++)
2391                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2392
2393         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2394         if (!err)
2395                 rqt->enabled = true;
2396
2397         kvfree(in);
2398         return err;
2399 }
2400
2401 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2402 {
2403         rqt->enabled = false;
2404         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2405 }
2406
2407 int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2408 {
2409         struct mlx5e_rqt *rqt = &priv->indir_rqt;
2410         int err;
2411
2412         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2413         if (err)
2414                 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2415         return err;
2416 }
2417
2418 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2419 {
2420         struct mlx5e_rqt *rqt;
2421         int err;
2422         int ix;
2423
2424         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2425                 rqt = &priv->direct_tir[ix].rqt;
2426                 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
2427                 if (err)
2428                         goto err_destroy_rqts;
2429         }
2430
2431         return 0;
2432
2433 err_destroy_rqts:
2434         mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2435         for (ix--; ix >= 0; ix--)
2436                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2437
2438         return err;
2439 }
2440
2441 void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2442 {
2443         int i;
2444
2445         for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++)
2446                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2447 }
2448
2449 static int mlx5e_rx_hash_fn(int hfunc)
2450 {
2451         return (hfunc == ETH_RSS_HASH_TOP) ?
2452                MLX5_RX_HASH_FN_TOEPLITZ :
2453                MLX5_RX_HASH_FN_INVERTED_XOR8;
2454 }
2455
2456 int mlx5e_bits_invert(unsigned long a, int size)
2457 {
2458         int inv = 0;
2459         int i;
2460
2461         for (i = 0; i < size; i++)
2462                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2463
2464         return inv;
2465 }
2466
2467 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2468                                 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2469 {
2470         int i;
2471
2472         for (i = 0; i < sz; i++) {
2473                 u32 rqn;
2474
2475                 if (rrp.is_rss) {
2476                         int ix = i;
2477
2478                         if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2479                                 ix = mlx5e_bits_invert(i, ilog2(sz));
2480
2481                         ix = priv->rss_params.indirection_rqt[ix];
2482                         rqn = rrp.rss.channels->c[ix]->rq.rqn;
2483                 } else {
2484                         rqn = rrp.rqn;
2485                 }
2486                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2487         }
2488 }
2489
2490 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2491                        struct mlx5e_redirect_rqt_param rrp)
2492 {
2493         struct mlx5_core_dev *mdev = priv->mdev;
2494         void *rqtc;
2495         int inlen;
2496         u32 *in;
2497         int err;
2498
2499         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2500         in = kvzalloc(inlen, GFP_KERNEL);
2501         if (!in)
2502                 return -ENOMEM;
2503
2504         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2505
2506         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2507         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2508         mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2509         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2510
2511         kvfree(in);
2512         return err;
2513 }
2514
2515 static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2516                                 struct mlx5e_redirect_rqt_param rrp)
2517 {
2518         if (!rrp.is_rss)
2519                 return rrp.rqn;
2520
2521         if (ix >= rrp.rss.channels->num)
2522                 return priv->drop_rq.rqn;
2523
2524         return rrp.rss.channels->c[ix]->rq.rqn;
2525 }
2526
2527 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2528                                 struct mlx5e_redirect_rqt_param rrp)
2529 {
2530         u32 rqtn;
2531         int ix;
2532
2533         if (priv->indir_rqt.enabled) {
2534                 /* RSS RQ table */
2535                 rqtn = priv->indir_rqt.rqtn;
2536                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2537         }
2538
2539         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2540                 struct mlx5e_redirect_rqt_param direct_rrp = {
2541                         .is_rss = false,
2542                         {
2543                                 .rqn    = mlx5e_get_direct_rqn(priv, ix, rrp)
2544                         },
2545                 };
2546
2547                 /* Direct RQ Tables */
2548                 if (!priv->direct_tir[ix].rqt.enabled)
2549                         continue;
2550
2551                 rqtn = priv->direct_tir[ix].rqt.rqtn;
2552                 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2553         }
2554 }
2555
2556 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2557                                             struct mlx5e_channels *chs)
2558 {
2559         struct mlx5e_redirect_rqt_param rrp = {
2560                 .is_rss        = true,
2561                 {
2562                         .rss = {
2563                                 .channels  = chs,
2564                                 .hfunc     = priv->rss_params.hfunc,
2565                         }
2566                 },
2567         };
2568
2569         mlx5e_redirect_rqts(priv, rrp);
2570 }
2571
2572 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2573 {
2574         struct mlx5e_redirect_rqt_param drop_rrp = {
2575                 .is_rss = false,
2576                 {
2577                         .rqn = priv->drop_rq.rqn,
2578                 },
2579         };
2580
2581         mlx5e_redirect_rqts(priv, drop_rrp);
2582 }
2583
2584 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {
2585         [MLX5E_TT_IPV4_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2586                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2587                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2588         },
2589         [MLX5E_TT_IPV6_TCP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2590                                 .l4_prot_type = MLX5_L4_PROT_TYPE_TCP,
2591                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2592         },
2593         [MLX5E_TT_IPV4_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2594                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2595                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2596         },
2597         [MLX5E_TT_IPV6_UDP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2598                                 .l4_prot_type = MLX5_L4_PROT_TYPE_UDP,
2599                                 .rx_hash_fields = MLX5_HASH_IP_L4PORTS,
2600         },
2601         [MLX5E_TT_IPV4_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2602                                      .l4_prot_type = 0,
2603                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2604         },
2605         [MLX5E_TT_IPV6_IPSEC_AH] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2606                                      .l4_prot_type = 0,
2607                                      .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2608         },
2609         [MLX5E_TT_IPV4_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2610                                       .l4_prot_type = 0,
2611                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2612         },
2613         [MLX5E_TT_IPV6_IPSEC_ESP] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2614                                       .l4_prot_type = 0,
2615                                       .rx_hash_fields = MLX5_HASH_IP_IPSEC_SPI,
2616         },
2617         [MLX5E_TT_IPV4] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV4,
2618                             .l4_prot_type = 0,
2619                             .rx_hash_fields = MLX5_HASH_IP,
2620         },
2621         [MLX5E_TT_IPV6] = { .l3_prot_type = MLX5_L3_PROT_TYPE_IPV6,
2622                             .l4_prot_type = 0,
2623                             .rx_hash_fields = MLX5_HASH_IP,
2624         },
2625 };
2626
2627 struct mlx5e_tirc_config mlx5e_tirc_get_default_config(enum mlx5e_traffic_types tt)
2628 {
2629         return tirc_default_config[tt];
2630 }
2631
2632 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2633 {
2634         if (!params->lro_en)
2635                 return;
2636
2637 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2638
2639         MLX5_SET(tirc, tirc, lro_enable_mask,
2640                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2641                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2642         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2643                  (MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2644         MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2645 }
2646
2647 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_rss_params *rss_params,
2648                                     const struct mlx5e_tirc_config *ttconfig,
2649                                     void *tirc, bool inner)
2650 {
2651         void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2652                              MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2653
2654         MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(rss_params->hfunc));
2655         if (rss_params->hfunc == ETH_RSS_HASH_TOP) {
2656                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2657                                              rx_hash_toeplitz_key);
2658                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2659                                                rx_hash_toeplitz_key);
2660
2661                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2662                 memcpy(rss_key, rss_params->toeplitz_hash_key, len);
2663         }
2664         MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2665                  ttconfig->l3_prot_type);
2666         MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2667                  ttconfig->l4_prot_type);
2668         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2669                  ttconfig->rx_hash_fields);
2670 }
2671
2672 static void mlx5e_update_rx_hash_fields(struct mlx5e_tirc_config *ttconfig,
2673                                         enum mlx5e_traffic_types tt,
2674                                         u32 rx_hash_fields)
2675 {
2676         *ttconfig                = tirc_default_config[tt];
2677         ttconfig->rx_hash_fields = rx_hash_fields;
2678 }
2679
2680 void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
2681 {
2682         void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2683         struct mlx5e_rss_params *rss = &priv->rss_params;
2684         struct mlx5_core_dev *mdev = priv->mdev;
2685         int ctxlen = MLX5_ST_SZ_BYTES(tirc);
2686         struct mlx5e_tirc_config ttconfig;
2687         int tt;
2688
2689         MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
2690
2691         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2692                 memset(tirc, 0, ctxlen);
2693                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2694                                             rss->rx_hash_fields[tt]);
2695                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, false);
2696                 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
2697         }
2698
2699         if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2700                 return;
2701
2702         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2703                 memset(tirc, 0, ctxlen);
2704                 mlx5e_update_rx_hash_fields(&ttconfig, tt,
2705                                             rss->rx_hash_fields[tt]);
2706                 mlx5e_build_indir_tir_ctx_hash(rss, &ttconfig, tirc, true);
2707                 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in,
2708                                      inlen);
2709         }
2710 }
2711
2712 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2713 {
2714         struct mlx5_core_dev *mdev = priv->mdev;
2715
2716         void *in;
2717         void *tirc;
2718         int inlen;
2719         int err;
2720         int tt;
2721         int ix;
2722
2723         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2724         in = kvzalloc(inlen, GFP_KERNEL);
2725         if (!in)
2726                 return -ENOMEM;
2727
2728         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2729         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2730
2731         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2732
2733         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2734                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2735                                            inlen);
2736                 if (err)
2737                         goto free_in;
2738         }
2739
2740         for (ix = 0; ix < mlx5e_get_netdev_max_channels(priv->netdev); ix++) {
2741                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2742                                            in, inlen);
2743                 if (err)
2744                         goto free_in;
2745         }
2746
2747 free_in:
2748         kvfree(in);
2749
2750         return err;
2751 }
2752
2753 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2754                                             enum mlx5e_traffic_types tt,
2755                                             u32 *tirc)
2756 {
2757         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2758
2759         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2760
2761         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2762         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2763         MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2764
2765         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
2766                                        &tirc_default_config[tt], tirc, true);
2767 }
2768
2769 static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2770                          struct mlx5e_params *params, u16 mtu)
2771 {
2772         u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2773         int err;
2774
2775         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2776         if (err)
2777                 return err;
2778
2779         /* Update vport context MTU */
2780         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2781         return 0;
2782 }
2783
2784 static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2785                             struct mlx5e_params *params, u16 *mtu)
2786 {
2787         u16 hw_mtu = 0;
2788         int err;
2789
2790         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2791         if (err || !hw_mtu) /* fallback to port oper mtu */
2792                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2793
2794         *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2795 }
2796
2797 int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2798 {
2799         struct mlx5e_params *params = &priv->channels.params;
2800         struct net_device *netdev = priv->netdev;
2801         struct mlx5_core_dev *mdev = priv->mdev;
2802         u16 mtu;
2803         int err;
2804
2805         err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2806         if (err)
2807                 return err;
2808
2809         mlx5e_query_mtu(mdev, params, &mtu);
2810         if (mtu != params->sw_mtu)
2811                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2812                             __func__, mtu, params->sw_mtu);
2813
2814         params->sw_mtu = mtu;
2815         return 0;
2816 }
2817
2818 void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv)
2819 {
2820         struct mlx5e_params *params = &priv->channels.params;
2821         struct net_device *netdev   = priv->netdev;
2822         struct mlx5_core_dev *mdev  = priv->mdev;
2823         u16 max_mtu;
2824
2825         /* MTU range: 68 - hw-specific max */
2826         netdev->min_mtu = ETH_MIN_MTU;
2827
2828         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2829         netdev->max_mtu = min_t(unsigned int, MLX5E_HW2SW_MTU(params, max_mtu),
2830                                 ETH_MAX_MTU);
2831 }
2832
2833 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2834 {
2835         struct mlx5e_priv *priv = netdev_priv(netdev);
2836         int nch = priv->channels.params.num_channels;
2837         int ntc = priv->channels.params.num_tc;
2838         int tc;
2839
2840         netdev_reset_tc(netdev);
2841
2842         if (ntc == 1)
2843                 return;
2844
2845         netdev_set_num_tc(netdev, ntc);
2846
2847         /* Map netdev TCs to offset 0
2848          * We have our own UP to TXQ mapping for QoS
2849          */
2850         for (tc = 0; tc < ntc; tc++)
2851                 netdev_set_tc_queue(netdev, tc, nch, 0);
2852 }
2853
2854 static void mlx5e_build_tc2txq_maps(struct mlx5e_priv *priv)
2855 {
2856         int max_nch = mlx5e_get_netdev_max_channels(priv->netdev);
2857         int i, tc;
2858
2859         for (i = 0; i < max_nch; i++)
2860                 for (tc = 0; tc < priv->profile->max_tc; tc++)
2861                         priv->channel_tc2txq[i][tc] = i + tc * max_nch;
2862 }
2863
2864 static void mlx5e_build_tx2sq_maps(struct mlx5e_priv *priv)
2865 {
2866         struct mlx5e_channel *c;
2867         struct mlx5e_txqsq *sq;
2868         int i, tc;
2869
2870         for (i = 0; i < priv->channels.num; i++) {
2871                 c = priv->channels.c[i];
2872                 for (tc = 0; tc < c->num_tc; tc++) {
2873                         sq = &c->sq[tc];
2874                         priv->txq2sq[sq->txq_ix] = sq;
2875                 }
2876         }
2877 }
2878
2879 void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2880 {
2881         int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2882         struct net_device *netdev = priv->netdev;
2883
2884         mlx5e_netdev_set_tcs(netdev);
2885         netif_set_real_num_tx_queues(netdev, num_txqs);
2886         netif_set_real_num_rx_queues(netdev, priv->channels.num);
2887
2888         mlx5e_build_tx2sq_maps(priv);
2889         mlx5e_activate_channels(&priv->channels);
2890         mlx5e_xdp_tx_enable(priv);
2891         netif_tx_start_all_queues(priv->netdev);
2892
2893         if (mlx5e_is_vport_rep(priv))
2894                 mlx5e_add_sqs_fwd_rules(priv);
2895
2896         mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2897         mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2898 }
2899
2900 void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2901 {
2902         mlx5e_redirect_rqts_to_drop(priv);
2903
2904         if (mlx5e_is_vport_rep(priv))
2905                 mlx5e_remove_sqs_fwd_rules(priv);
2906
2907         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2908          * polling for inactive tx queues.
2909          */
2910         netif_tx_stop_all_queues(priv->netdev);
2911         netif_tx_disable(priv->netdev);
2912         mlx5e_xdp_tx_disable(priv);
2913         mlx5e_deactivate_channels(&priv->channels);
2914 }
2915
2916 static void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2917                                        struct mlx5e_channels *new_chs,
2918                                        mlx5e_fp_hw_modify hw_modify)
2919 {
2920         struct net_device *netdev = priv->netdev;
2921         int new_num_txqs;
2922         int carrier_ok;
2923
2924         new_num_txqs = new_chs->num * new_chs->params.num_tc;
2925
2926         carrier_ok = netif_carrier_ok(netdev);
2927         netif_carrier_off(netdev);
2928
2929         if (new_num_txqs < netdev->real_num_tx_queues)
2930                 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2931
2932         mlx5e_deactivate_priv_channels(priv);
2933         mlx5e_close_channels(&priv->channels);
2934
2935         priv->channels = *new_chs;
2936
2937         /* New channels are ready to roll, modify HW settings if needed */
2938         if (hw_modify)
2939                 hw_modify(priv);
2940
2941         mlx5e_refresh_tirs(priv, false);
2942         mlx5e_activate_priv_channels(priv);
2943
2944         /* return carrier back if needed */
2945         if (carrier_ok)
2946                 netif_carrier_on(netdev);
2947 }
2948
2949 int mlx5e_safe_switch_channels(struct mlx5e_priv *priv,
2950                                struct mlx5e_channels *new_chs,
2951                                mlx5e_fp_hw_modify hw_modify)
2952 {
2953         int err;
2954
2955         err = mlx5e_open_channels(priv, new_chs);
2956         if (err)
2957                 return err;
2958
2959         mlx5e_switch_priv_channels(priv, new_chs, hw_modify);
2960         return 0;
2961 }
2962
2963 int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv)
2964 {
2965         struct mlx5e_channels new_channels = {};
2966
2967         new_channels.params = priv->channels.params;
2968         return mlx5e_safe_switch_channels(priv, &new_channels, NULL);
2969 }
2970
2971 void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2972 {
2973         priv->tstamp.tx_type   = HWTSTAMP_TX_OFF;
2974         priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2975 }
2976
2977 int mlx5e_open_locked(struct net_device *netdev)
2978 {
2979         struct mlx5e_priv *priv = netdev_priv(netdev);
2980         int err;
2981
2982         set_bit(MLX5E_STATE_OPENED, &priv->state);
2983
2984         err = mlx5e_open_channels(priv, &priv->channels);
2985         if (err)
2986                 goto err_clear_state_opened_flag;
2987
2988         mlx5e_refresh_tirs(priv, false);
2989         mlx5e_activate_priv_channels(priv);
2990         if (priv->profile->update_carrier)
2991                 priv->profile->update_carrier(priv);
2992
2993         mlx5e_queue_update_stats(priv);
2994         return 0;
2995
2996 err_clear_state_opened_flag:
2997         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2998         return err;
2999 }
3000
3001 int mlx5e_open(struct net_device *netdev)
3002 {
3003         struct mlx5e_priv *priv = netdev_priv(netdev);
3004         int err;
3005
3006         mutex_lock(&priv->state_lock);
3007         err = mlx5e_open_locked(netdev);
3008         if (!err)
3009                 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
3010         mutex_unlock(&priv->state_lock);
3011
3012         if (mlx5_vxlan_allowed(priv->mdev->vxlan))
3013                 udp_tunnel_get_rx_info(netdev);
3014
3015         return err;
3016 }
3017
3018 int mlx5e_close_locked(struct net_device *netdev)
3019 {
3020         struct mlx5e_priv *priv = netdev_priv(netdev);
3021
3022         /* May already be CLOSED in case a previous configuration operation
3023          * (e.g RX/TX queue size change) that involves close&open failed.
3024          */
3025         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3026                 return 0;
3027
3028         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3029
3030         netif_carrier_off(priv->netdev);
3031         mlx5e_deactivate_priv_channels(priv);
3032         mlx5e_close_channels(&priv->channels);
3033
3034         return 0;
3035 }
3036
3037 int mlx5e_close(struct net_device *netdev)
3038 {
3039         struct mlx5e_priv *priv = netdev_priv(netdev);
3040         int err;
3041
3042         if (!netif_device_present(netdev))
3043                 return -ENODEV;
3044
3045         mutex_lock(&priv->state_lock);
3046         mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
3047         err = mlx5e_close_locked(netdev);
3048         mutex_unlock(&priv->state_lock);
3049
3050         return err;
3051 }
3052
3053 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3054                                struct mlx5e_rq *rq,
3055                                struct mlx5e_rq_param *param)
3056 {
3057         void *rqc = param->rqc;
3058         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
3059         int err;
3060
3061         param->wq.db_numa_node = param->wq.buf_numa_node;
3062
3063         err = mlx5_wq_cyc_create(mdev, &param->wq, rqc_wq, &rq->wqe.wq,
3064                                  &rq->wq_ctrl);
3065         if (err)
3066                 return err;
3067
3068         /* Mark as unused given "Drop-RQ" packets never reach XDP */
3069         xdp_rxq_info_unused(&rq->xdp_rxq);
3070
3071         rq->mdev = mdev;
3072
3073         return 0;
3074 }
3075
3076 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3077                                struct mlx5e_cq *cq,
3078                                struct mlx5e_cq_param *param)
3079 {
3080         param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
3081         param->wq.db_numa_node  = dev_to_node(&mdev->pdev->dev);
3082
3083         return mlx5e_alloc_cq_common(mdev, param, cq);
3084 }
3085
3086 int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
3087                        struct mlx5e_rq *drop_rq)
3088 {
3089         struct mlx5_core_dev *mdev = priv->mdev;
3090         struct mlx5e_cq_param cq_param = {};
3091         struct mlx5e_rq_param rq_param = {};
3092         struct mlx5e_cq *cq = &drop_rq->cq;
3093         int err;
3094
3095         mlx5e_build_drop_rq_param(priv, &rq_param);
3096
3097         err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
3098         if (err)
3099                 return err;
3100
3101         err = mlx5e_create_cq(cq, &cq_param);
3102         if (err)
3103                 goto err_free_cq;
3104
3105         err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
3106         if (err)
3107                 goto err_destroy_cq;
3108
3109         err = mlx5e_create_rq(drop_rq, &rq_param);
3110         if (err)
3111                 goto err_free_rq;
3112
3113         err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3114         if (err)
3115                 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
3116
3117         return 0;
3118
3119 err_free_rq:
3120         mlx5e_free_rq(drop_rq);
3121
3122 err_destroy_cq:
3123         mlx5e_destroy_cq(cq);
3124
3125 err_free_cq:
3126         mlx5e_free_cq(cq);
3127
3128         return err;
3129 }
3130
3131 void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
3132 {
3133         mlx5e_destroy_rq(drop_rq);
3134         mlx5e_free_rq(drop_rq);
3135         mlx5e_destroy_cq(&drop_rq->cq);
3136         mlx5e_free_cq(&drop_rq->cq);
3137 }
3138
3139 int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
3140                      u32 underlay_qpn, u32 *tisn)
3141 {
3142         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
3143         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
3144
3145         MLX5_SET(tisc, tisc, prio, tc << 1);
3146         MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
3147         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
3148
3149         if (mlx5_lag_is_lacp_owner(mdev))
3150                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
3151
3152         return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
3153 }
3154
3155 void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
3156 {
3157         mlx5_core_destroy_tis(mdev, tisn);
3158 }
3159
3160 int mlx5e_create_tises(struct mlx5e_priv *priv)
3161 {
3162         int err;
3163         int tc;
3164
3165         for (tc = 0; tc < priv->profile->max_tc; tc++) {
3166                 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
3167                 if (err)
3168                         goto err_close_tises;
3169         }
3170
3171         return 0;
3172
3173 err_close_tises:
3174         for (tc--; tc >= 0; tc--)
3175                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3176
3177         return err;
3178 }
3179
3180 static void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
3181 {
3182         int tc;
3183
3184         mlx5e_tx_reporter_destroy(priv);
3185         for (tc = 0; tc < priv->profile->max_tc; tc++)
3186                 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
3187 }
3188
3189 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
3190                                       enum mlx5e_traffic_types tt,
3191                                       u32 *tirc)
3192 {
3193         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3194
3195         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3196
3197         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3198         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
3199
3200         mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
3201                                        &tirc_default_config[tt], tirc, false);
3202 }
3203
3204 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
3205 {
3206         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3207
3208         mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
3209
3210         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
3211         MLX5_SET(tirc, tirc, indirect_table, rqtn);
3212         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
3213 }
3214
3215 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3216 {
3217         struct mlx5e_tir *tir;
3218         void *tirc;
3219         int inlen;
3220         int i = 0;
3221         int err;
3222         u32 *in;
3223         int tt;
3224
3225         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3226         in = kvzalloc(inlen, GFP_KERNEL);
3227         if (!in)
3228                 return -ENOMEM;
3229
3230         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
3231                 memset(in, 0, inlen);
3232                 tir = &priv->indir_tir[tt];
3233                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3234                 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
3235                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3236                 if (err) {
3237                         mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
3238                         goto err_destroy_inner_tirs;
3239                 }
3240         }
3241
3242         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3243                 goto out;
3244
3245         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
3246                 memset(in, 0, inlen);
3247                 tir = &priv->inner_indir_tir[i];
3248                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3249                 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
3250                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3251                 if (err) {
3252                         mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
3253                         goto err_destroy_inner_tirs;
3254                 }
3255         }
3256
3257 out:
3258         kvfree(in);
3259
3260         return 0;
3261
3262 err_destroy_inner_tirs:
3263         for (i--; i >= 0; i--)
3264                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3265
3266         for (tt--; tt >= 0; tt--)
3267                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
3268
3269         kvfree(in);
3270
3271         return err;
3272 }
3273
3274 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
3275 {
3276         int nch = mlx5e_get_netdev_max_channels(priv->netdev);
3277         struct mlx5e_tir *tir;
3278         void *tirc;
3279         int inlen;
3280         int err;
3281         u32 *in;
3282         int ix;
3283
3284         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
3285         in = kvzalloc(inlen, GFP_KERNEL);
3286         if (!in)
3287                 return -ENOMEM;
3288
3289         for (ix = 0; ix < nch; ix++) {
3290                 memset(in, 0, inlen);
3291                 tir = &priv->direct_tir[ix];
3292                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
3293                 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
3294                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
3295                 if (err)
3296                         goto err_destroy_ch_tirs;
3297         }
3298
3299         kvfree(in);
3300
3301         return 0;
3302
3303 err_destroy_ch_tirs:
3304         mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3305         for (ix--; ix >= 0; ix--)
3306                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3307
3308         kvfree(in);
3309
3310         return err;
3311 }
3312
3313 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
3314 {
3315         int i;
3316
3317         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3318                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3319
3320         if (!inner_ttc || !mlx5e_tunnel_inner_ft_supported(priv->mdev))
3321                 return;
3322
3323         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3324                 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3325 }
3326
3327 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3328 {
3329         int nch = mlx5e_get_netdev_max_channels(priv->netdev);
3330         int i;
3331
3332         for (i = 0; i < nch; i++)
3333                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3334 }
3335
3336 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3337 {
3338         int err = 0;
3339         int i;
3340
3341         for (i = 0; i < chs->num; i++) {
3342                 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3343                 if (err)
3344                         return err;
3345         }
3346
3347         return 0;
3348 }
3349
3350 static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3351 {
3352         int err = 0;
3353         int i;
3354
3355         for (i = 0; i < chs->num; i++) {
3356                 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3357                 if (err)
3358                         return err;
3359         }
3360
3361         return 0;
3362 }
3363
3364 static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3365                                  struct tc_mqprio_qopt *mqprio)
3366 {
3367         struct mlx5e_priv *priv = netdev_priv(netdev);
3368         struct mlx5e_channels new_channels = {};
3369         u8 tc = mqprio->num_tc;
3370         int err = 0;
3371
3372         mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3373
3374         if (tc && tc != MLX5E_MAX_NUM_TC)
3375                 return -EINVAL;
3376
3377         mutex_lock(&priv->state_lock);
3378
3379         new_channels.params = priv->channels.params;
3380         new_channels.params.num_tc = tc ? tc : 1;
3381
3382         if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3383                 priv->channels.params = new_channels.params;
3384                 goto out;
3385         }
3386
3387         err = mlx5e_safe_switch_channels(priv, &new_channels, NULL);
3388         if (err)
3389                 goto out;
3390
3391         priv->max_opened_tc = max_t(u8, priv->max_opened_tc,
3392                                     new_channels.params.num_tc);
3393 out:
3394         mutex_unlock(&priv->state_lock);
3395         return err;
3396 }
3397
3398 #ifdef CONFIG_MLX5_ESWITCH
3399 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3400                                      struct tc_cls_flower_offload *cls_flower,
3401                                      int flags)
3402 {
3403         switch (cls_flower->command) {
3404         case TC_CLSFLOWER_REPLACE:
3405                 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
3406                                               flags);
3407         case TC_CLSFLOWER_DESTROY:
3408                 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
3409                                            flags);
3410         case TC_CLSFLOWER_STATS:
3411                 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
3412                                           flags);
3413         default:
3414                 return -EOPNOTSUPP;
3415         }
3416 }
3417
3418 static int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3419                                    void *cb_priv)
3420 {
3421         struct mlx5e_priv *priv = cb_priv;
3422
3423         switch (type) {
3424         case TC_SETUP_CLSFLOWER:
3425                 return mlx5e_setup_tc_cls_flower(priv, type_data, MLX5E_TC_INGRESS |
3426                                                  MLX5E_TC_NIC_OFFLOAD);
3427         default:
3428                 return -EOPNOTSUPP;
3429         }
3430 }
3431
3432 static int mlx5e_setup_tc_block(struct net_device *dev,
3433                                 struct tc_block_offload *f)
3434 {
3435         struct mlx5e_priv *priv = netdev_priv(dev);
3436
3437         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3438                 return -EOPNOTSUPP;
3439
3440         switch (f->command) {
3441         case TC_BLOCK_BIND:
3442                 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3443                                              priv, priv, f->extack);
3444         case TC_BLOCK_UNBIND:
3445                 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3446                                         priv);
3447                 return 0;
3448         default:
3449                 return -EOPNOTSUPP;
3450         }
3451 }
3452 #endif
3453
3454 static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3455                           void *type_data)
3456 {
3457         switch (type) {
3458 #ifdef CONFIG_MLX5_ESWITCH
3459         case TC_SETUP_BLOCK:
3460                 return mlx5e_setup_tc_block(dev, type_data);
3461 #endif
3462         case TC_SETUP_QDISC_MQPRIO:
3463                 return mlx5e_setup_tc_mqprio(dev, type_data);
3464         default:
3465                 return -EOPNOTSUPP;
3466         }
3467 }
3468
3469 void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s)
3470 {
3471         int i;
3472
3473         for (i = 0; i < mlx5e_get_netdev_max_channels(priv->netdev); i++) {
3474                 struct mlx5e_channel_stats *channel_stats = &priv->channel_stats[i];
3475                 struct mlx5e_rq_stats *rq_stats = &channel_stats->rq;
3476                 int j;
3477
3478                 s->rx_packets   += rq_stats->packets;
3479                 s->rx_bytes     += rq_stats->bytes;
3480
3481                 for (j = 0; j < priv->max_opened_tc; j++) {
3482                         struct mlx5e_sq_stats *sq_stats = &channel_stats->sq[j];
3483
3484                         s->tx_packets    += sq_stats->packets;
3485                         s->tx_bytes      += sq_stats->bytes;
3486                         s->tx_dropped    += sq_stats->dropped;
3487                 }
3488         }
3489 }
3490
3491 void
3492 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3493 {
3494         struct mlx5e_priv *priv = netdev_priv(dev);
3495         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3496         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3497
3498         if (!mlx5e_monitor_counter_supported(priv)) {
3499                 /* update HW stats in background for next time */
3500                 mlx5e_queue_update_stats(priv);
3501         }
3502
3503         if (mlx5e_is_uplink_rep(priv)) {
3504                 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3505                 stats->rx_bytes   = PPORT_802_3_GET(pstats, a_octets_received_ok);
3506                 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3507                 stats->tx_bytes   = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3508         } else {
3509                 mlx5e_fold_sw_stats64(priv, stats);
3510         }
3511
3512         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3513
3514         stats->rx_length_errors =
3515                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3516                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3517                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3518         stats->rx_crc_errors =
3519                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3520         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3521         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3522         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3523                            stats->rx_frame_errors;
3524         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3525
3526         /* vport multicast also counts packets that are dropped due to steering
3527          * or rx out of buffer
3528          */
3529         stats->multicast =
3530                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3531 }
3532
3533 static void mlx5e_set_rx_mode(struct net_device *dev)
3534 {
3535         struct mlx5e_priv *priv = netdev_priv(dev);
3536
3537         queue_work(priv->wq, &priv->set_rx_mode_work);
3538 }
3539
3540 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3541 {
3542         struct mlx5e_priv *priv = netdev_priv(netdev);
3543         struct sockaddr *saddr = addr;
3544
3545         if (!is_valid_ether_addr(saddr->sa_data))
3546                 return -EADDRNOTAVAIL;
3547
3548         netif_addr_lock_bh(netdev);
3549         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3550         netif_addr_unlock_bh(netdev);
3551
3552         queue_work(priv->wq, &priv->set_rx_mode_work);
3553
3554         return 0;
3555 }
3556
3557 #define MLX5E_SET_FEATURE(features, feature, enable)    \
3558         do {                                            \
3559                 if (enable)                             \
3560                         *features |= feature;           \
3561                 else                                    \
3562                         *features &= ~feature;          \
3563         } while (0)
3564
3565 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3566
3567 static int set_feature_lro(struct net_device *netdev, bool enable)
3568 {
3569         struct mlx5e_priv *priv = netdev_priv(netdev);
3570         struct mlx5_core_dev *mdev = priv->mdev;
3571         struct mlx5e_channels new_channels = {};
3572         struct mlx5e_params *old_params;
3573         int err = 0;
3574         bool reset;
3575
3576         mutex_lock(&priv->state_lock);
3577
3578         old_params = &priv->channels.params;
3579         if (enable && !MLX5E_GET_PFLAG(old_params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3580                 netdev_warn(netdev, "can't set LRO with legacy RQ\n");
3581                 err = -EINVAL;
3582                 goto out;
3583         }
3584
3585         reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3586
3587         new_channels.params = *old_params;
3588         new_channels.params.lro_en = enable;
3589
3590         if (old_params->rq_wq_type != MLX5_WQ_TYPE_CYCLIC) {
3591                 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3592                     mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3593                         reset = false;
3594         }
3595
3596         if (!reset) {
3597                 *old_params = new_channels.params;
3598                 err = mlx5e_modify_tirs_lro(priv);
3599                 goto out;
3600         }
3601
3602         err = mlx5e_safe_switch_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3603 out:
3604         mutex_unlock(&priv->state_lock);
3605         return err;
3606 }
3607
3608 static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3609 {
3610         struct mlx5e_priv *priv = netdev_priv(netdev);
3611
3612         if (enable)
3613                 mlx5e_enable_cvlan_filter(priv);
3614         else
3615                 mlx5e_disable_cvlan_filter(priv);
3616
3617         return 0;
3618 }
3619
3620 #ifdef CONFIG_MLX5_ESWITCH
3621 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3622 {
3623         struct mlx5e_priv *priv = netdev_priv(netdev);
3624
3625         if (!enable && mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD)) {
3626                 netdev_err(netdev,
3627                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3628                 return -EINVAL;
3629         }
3630
3631         return 0;
3632 }
3633 #endif
3634
3635 static int set_feature_rx_all(struct net_device *netdev, bool enable)
3636 {
3637         struct mlx5e_priv *priv = netdev_priv(netdev);
3638         struct mlx5_core_dev *mdev = priv->mdev;
3639
3640         return mlx5_set_port_fcs(mdev, !enable);
3641 }
3642
3643 static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3644 {
3645         struct mlx5e_priv *priv = netdev_priv(netdev);
3646         int err;
3647
3648         mutex_lock(&priv->state_lock);
3649
3650         priv->channels.params.scatter_fcs_en = enable;
3651         err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3652         if (err)
3653                 priv->channels.params.scatter_fcs_en = !enable;
3654
3655         mutex_unlock(&priv->state_lock);
3656
3657         return err;
3658 }
3659
3660 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3661 {
3662         struct mlx5e_priv *priv = netdev_priv(netdev);
3663         int err = 0;
3664
3665         mutex_lock(&priv->state_lock);
3666
3667         priv->channels.params.vlan_strip_disable = !enable;
3668         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3669                 goto unlock;
3670
3671         err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3672         if (err)
3673                 priv->channels.params.vlan_strip_disable = enable;
3674
3675 unlock:
3676         mutex_unlock(&priv->state_lock);
3677
3678         return err;
3679 }
3680
3681 #ifdef CONFIG_MLX5_EN_ARFS
3682 static int set_feature_arfs(struct net_device *netdev, bool enable)
3683 {
3684         struct mlx5e_priv *priv = netdev_priv(netdev);
3685         int err;
3686
3687         if (enable)
3688                 err = mlx5e_arfs_enable(priv);
3689         else
3690                 err = mlx5e_arfs_disable(priv);
3691
3692         return err;
3693 }
3694 #endif
3695
3696 static int mlx5e_handle_feature(struct net_device *netdev,
3697                                 netdev_features_t *features,
3698                                 netdev_features_t wanted_features,
3699                                 netdev_features_t feature,
3700                                 mlx5e_feature_handler feature_handler)
3701 {
3702         netdev_features_t changes = wanted_features ^ netdev->features;
3703         bool enable = !!(wanted_features & feature);
3704         int err;
3705
3706         if (!(changes & feature))
3707                 return 0;
3708
3709         err = feature_handler(netdev, enable);
3710         if (err) {
3711                 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3712                            enable ? "Enable" : "Disable", &feature, err);
3713                 return err;
3714         }
3715
3716         MLX5E_SET_FEATURE(features, feature, enable);
3717         return 0;
3718 }
3719
3720 static int mlx5e_set_features(struct net_device *netdev,
3721                               netdev_features_t features)
3722 {
3723         netdev_features_t oper_features = netdev->features;
3724         int err = 0;
3725
3726 #define MLX5E_HANDLE_FEATURE(feature, handler) \
3727         mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3728
3729         err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3730         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3731                                     set_feature_cvlan_filter);
3732 #ifdef CONFIG_MLX5_ESWITCH
3733         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3734 #endif
3735         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3736         err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3737         err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3738 #ifdef CONFIG_MLX5_EN_ARFS
3739         err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3740 #endif
3741
3742         if (err) {
3743                 netdev->features = oper_features;
3744                 return -EINVAL;
3745         }
3746
3747         return 0;
3748 }
3749
3750 static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3751                                             netdev_features_t features)
3752 {
3753         struct mlx5e_priv *priv = netdev_priv(netdev);
3754         struct mlx5e_params *params;
3755
3756         mutex_lock(&priv->state_lock);
3757         params = &priv->channels.params;
3758         if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3759                 /* HW strips the outer C-tag header, this is a problem
3760                  * for S-tag traffic.
3761                  */
3762                 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3763                 if (!params->vlan_strip_disable)
3764                         netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3765         }
3766         if (!MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ)) {
3767                 features &= ~NETIF_F_LRO;
3768                 if (params->lro_en)
3769                         netdev_warn(netdev, "Disabling LRO, not supported in legacy RQ\n");
3770         }
3771
3772         mutex_unlock(&priv->state_lock);
3773
3774         return features;
3775 }
3776
3777 int mlx5e_change_mtu(struct net_device *netdev, int new_mtu,
3778                      change_hw_mtu_cb set_mtu_cb)
3779 {
3780         struct mlx5e_priv *priv = netdev_priv(netdev);
3781         struct mlx5e_channels new_channels = {};
3782         struct mlx5e_params *params;
3783         int err = 0;
3784         bool reset;
3785
3786         mutex_lock(&priv->state_lock);
3787
3788         params = &priv->channels.params;
3789
3790         reset = !params->lro_en;
3791         reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3792
3793         new_channels.params = *params;
3794         new_channels.params.sw_mtu = new_mtu;
3795
3796         if (params->xdp_prog &&
3797             !mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
3798                 netdev_err(netdev, "MTU(%d) > %d is not allowed while XDP enabled\n",
3799                            new_mtu, MLX5E_XDP_MAX_MTU);
3800                 err = -EINVAL;
3801                 goto out;
3802         }
3803
3804         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
3805                 bool is_linear = mlx5e_rx_mpwqe_is_linear_skb(priv->mdev, &new_channels.params);
3806                 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3807                 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3808
3809                 reset = reset && (is_linear || (ppw_old != ppw_new));
3810         }
3811
3812         if (!reset) {
3813                 params->sw_mtu = new_mtu;
3814                 if (set_mtu_cb)
3815                         set_mtu_cb(priv);
3816                 netdev->mtu = params->sw_mtu;
3817                 goto out;
3818         }
3819
3820         err = mlx5e_safe_switch_channels(priv, &new_channels, set_mtu_cb);
3821         if (err)
3822                 goto out;
3823
3824         netdev->mtu = new_channels.params.sw_mtu;
3825
3826 out:
3827         mutex_unlock(&priv->state_lock);
3828         return err;
3829 }
3830
3831 static int mlx5e_change_nic_mtu(struct net_device *netdev, int new_mtu)
3832 {
3833         return mlx5e_change_mtu(netdev, new_mtu, mlx5e_set_dev_port_mtu);
3834 }
3835
3836 int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3837 {
3838         struct hwtstamp_config config;
3839         int err;
3840
3841         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) ||
3842             (mlx5_clock_get_ptp_index(priv->mdev) == -1))
3843                 return -EOPNOTSUPP;
3844
3845         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3846                 return -EFAULT;
3847
3848         /* TX HW timestamp */
3849         switch (config.tx_type) {
3850         case HWTSTAMP_TX_OFF:
3851         case HWTSTAMP_TX_ON:
3852                 break;
3853         default:
3854                 return -ERANGE;
3855         }
3856
3857         mutex_lock(&priv->state_lock);
3858         /* RX HW timestamp */
3859         switch (config.rx_filter) {
3860         case HWTSTAMP_FILTER_NONE:
3861                 /* Reset CQE compression to Admin default */
3862                 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3863                 break;
3864         case HWTSTAMP_FILTER_ALL:
3865         case HWTSTAMP_FILTER_SOME:
3866         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3867         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3868         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3869         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3870         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3871         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3872         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3873         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3874         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3875         case HWTSTAMP_FILTER_PTP_V2_EVENT:
3876         case HWTSTAMP_FILTER_PTP_V2_SYNC:
3877         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3878         case HWTSTAMP_FILTER_NTP_ALL:
3879                 /* Disable CQE compression */
3880                 netdev_warn(priv->netdev, "Disabling cqe compression");
3881                 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3882                 if (err) {
3883                         netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3884                         mutex_unlock(&priv->state_lock);
3885                         return err;
3886                 }
3887                 config.rx_filter = HWTSTAMP_FILTER_ALL;
3888                 break;
3889         default:
3890                 mutex_unlock(&priv->state_lock);
3891                 return -ERANGE;
3892         }
3893
3894         memcpy(&priv->tstamp, &config, sizeof(config));
3895         mutex_unlock(&priv->state_lock);
3896
3897         return copy_to_user(ifr->ifr_data, &config,
3898                             sizeof(config)) ? -EFAULT : 0;
3899 }
3900
3901 int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3902 {
3903         struct hwtstamp_config *cfg = &priv->tstamp;
3904
3905         if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3906                 return -EOPNOTSUPP;
3907
3908         return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3909 }
3910
3911 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3912 {
3913         struct mlx5e_priv *priv = netdev_priv(dev);
3914
3915         switch (cmd) {
3916         case SIOCSHWTSTAMP:
3917                 return mlx5e_hwstamp_set(priv, ifr);
3918         case SIOCGHWTSTAMP:
3919                 return mlx5e_hwstamp_get(priv, ifr);
3920         default:
3921                 return -EOPNOTSUPP;
3922         }
3923 }
3924
3925 #ifdef CONFIG_MLX5_ESWITCH
3926 int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3927 {
3928         struct mlx5e_priv *priv = netdev_priv(dev);
3929         struct mlx5_core_dev *mdev = priv->mdev;
3930
3931         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3932 }
3933
3934 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3935                              __be16 vlan_proto)
3936 {
3937         struct mlx5e_priv *priv = netdev_priv(dev);
3938         struct mlx5_core_dev *mdev = priv->mdev;
3939
3940         if (vlan_proto != htons(ETH_P_8021Q))
3941                 return -EPROTONOSUPPORT;
3942
3943         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3944                                            vlan, qos);
3945 }
3946
3947 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3948 {
3949         struct mlx5e_priv *priv = netdev_priv(dev);
3950         struct mlx5_core_dev *mdev = priv->mdev;
3951
3952         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3953 }
3954
3955 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3956 {
3957         struct mlx5e_priv *priv = netdev_priv(dev);
3958         struct mlx5_core_dev *mdev = priv->mdev;
3959
3960         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3961 }
3962
3963 int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3964                       int max_tx_rate)
3965 {
3966         struct mlx5e_priv *priv = netdev_priv(dev);
3967         struct mlx5_core_dev *mdev = priv->mdev;
3968
3969         return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3970                                            max_tx_rate, min_tx_rate);
3971 }
3972
3973 static int mlx5_vport_link2ifla(u8 esw_link)
3974 {
3975         switch (esw_link) {
3976         case MLX5_VPORT_ADMIN_STATE_DOWN:
3977                 return IFLA_VF_LINK_STATE_DISABLE;
3978         case MLX5_VPORT_ADMIN_STATE_UP:
3979                 return IFLA_VF_LINK_STATE_ENABLE;
3980         }
3981         return IFLA_VF_LINK_STATE_AUTO;
3982 }
3983
3984 static int mlx5_ifla_link2vport(u8 ifla_link)
3985 {
3986         switch (ifla_link) {
3987         case IFLA_VF_LINK_STATE_DISABLE:
3988                 return MLX5_VPORT_ADMIN_STATE_DOWN;
3989         case IFLA_VF_LINK_STATE_ENABLE:
3990                 return MLX5_VPORT_ADMIN_STATE_UP;
3991         }
3992         return MLX5_VPORT_ADMIN_STATE_AUTO;
3993 }
3994
3995 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3996                                    int link_state)
3997 {
3998         struct mlx5e_priv *priv = netdev_priv(dev);
3999         struct mlx5_core_dev *mdev = priv->mdev;
4000
4001         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
4002                                             mlx5_ifla_link2vport(link_state));
4003 }
4004
4005 int mlx5e_get_vf_config(struct net_device *dev,
4006                         int vf, struct ifla_vf_info *ivi)
4007 {
4008         struct mlx5e_priv *priv = netdev_priv(dev);
4009         struct mlx5_core_dev *mdev = priv->mdev;
4010         int err;
4011
4012         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
4013         if (err)
4014                 return err;
4015         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
4016         return 0;
4017 }
4018
4019 int mlx5e_get_vf_stats(struct net_device *dev,
4020                        int vf, struct ifla_vf_stats *vf_stats)
4021 {
4022         struct mlx5e_priv *priv = netdev_priv(dev);
4023         struct mlx5_core_dev *mdev = priv->mdev;
4024
4025         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
4026                                             vf_stats);
4027 }
4028 #endif
4029
4030 struct mlx5e_vxlan_work {
4031         struct work_struct      work;
4032         struct mlx5e_priv       *priv;
4033         u16                     port;
4034 };
4035
4036 static void mlx5e_vxlan_add_work(struct work_struct *work)
4037 {
4038         struct mlx5e_vxlan_work *vxlan_work =
4039                 container_of(work, struct mlx5e_vxlan_work, work);
4040         struct mlx5e_priv *priv = vxlan_work->priv;
4041         u16 port = vxlan_work->port;
4042
4043         mutex_lock(&priv->state_lock);
4044         mlx5_vxlan_add_port(priv->mdev->vxlan, port);
4045         mutex_unlock(&priv->state_lock);
4046
4047         kfree(vxlan_work);
4048 }
4049
4050 static void mlx5e_vxlan_del_work(struct work_struct *work)
4051 {
4052         struct mlx5e_vxlan_work *vxlan_work =
4053                 container_of(work, struct mlx5e_vxlan_work, work);
4054         struct mlx5e_priv *priv         = vxlan_work->priv;
4055         u16 port = vxlan_work->port;
4056
4057         mutex_lock(&priv->state_lock);
4058         mlx5_vxlan_del_port(priv->mdev->vxlan, port);
4059         mutex_unlock(&priv->state_lock);
4060         kfree(vxlan_work);
4061 }
4062
4063 static void mlx5e_vxlan_queue_work(struct mlx5e_priv *priv, u16 port, int add)
4064 {
4065         struct mlx5e_vxlan_work *vxlan_work;
4066
4067         vxlan_work = kmalloc(sizeof(*vxlan_work), GFP_ATOMIC);
4068         if (!vxlan_work)
4069                 return;
4070
4071         if (add)
4072                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_add_work);
4073         else
4074                 INIT_WORK(&vxlan_work->work, mlx5e_vxlan_del_work);
4075
4076         vxlan_work->priv = priv;
4077         vxlan_work->port = port;
4078         queue_work(priv->wq, &vxlan_work->work);
4079 }
4080
4081 void mlx5e_add_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4082 {
4083         struct mlx5e_priv *priv = netdev_priv(netdev);
4084
4085         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4086                 return;
4087
4088         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4089                 return;
4090
4091         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 1);
4092 }
4093
4094 void mlx5e_del_vxlan_port(struct net_device *netdev, struct udp_tunnel_info *ti)
4095 {
4096         struct mlx5e_priv *priv = netdev_priv(netdev);
4097
4098         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
4099                 return;
4100
4101         if (!mlx5_vxlan_allowed(priv->mdev->vxlan))
4102                 return;
4103
4104         mlx5e_vxlan_queue_work(priv, be16_to_cpu(ti->port), 0);
4105 }
4106
4107 static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
4108                                                      struct sk_buff *skb,
4109                                                      netdev_features_t features)
4110 {
4111         unsigned int offset = 0;
4112         struct udphdr *udph;
4113         u8 proto;
4114         u16 port;
4115
4116         switch (vlan_get_protocol(skb)) {
4117         case htons(ETH_P_IP):
4118                 proto = ip_hdr(skb)->protocol;
4119                 break;
4120         case htons(ETH_P_IPV6):
4121                 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
4122                 break;
4123         default:
4124                 goto out;
4125         }
4126
4127         switch (proto) {
4128         case IPPROTO_GRE:
4129                 return features;
4130         case IPPROTO_UDP:
4131                 udph = udp_hdr(skb);
4132                 port = be16_to_cpu(udph->dest);
4133
4134                 /* Verify if UDP port is being offloaded by HW */
4135                 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, port))
4136                         return features;
4137
4138 #if IS_ENABLED(CONFIG_GENEVE)
4139                 /* Support Geneve offload for default UDP port */
4140                 if (port == GENEVE_UDP_PORT && mlx5_geneve_tx_allowed(priv->mdev))
4141                         return features;
4142 #endif
4143         }
4144
4145 out:
4146         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
4147         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
4148 }
4149
4150 netdev_features_t mlx5e_features_check(struct sk_buff *skb,
4151                                        struct net_device *netdev,
4152                                        netdev_features_t features)
4153 {
4154         struct mlx5e_priv *priv = netdev_priv(netdev);
4155
4156         features = vlan_features_check(skb, features);
4157         features = vxlan_features_check(skb, features);
4158
4159 #ifdef CONFIG_MLX5_EN_IPSEC
4160         if (mlx5e_ipsec_feature_check(skb, netdev, features))
4161                 return features;
4162 #endif
4163
4164         /* Validate if the tunneled packet is being offloaded by HW */
4165         if (skb->encapsulation &&
4166             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
4167                 return mlx5e_tunnel_features_check(priv, skb, features);
4168
4169         return features;
4170 }
4171
4172 static void mlx5e_tx_timeout_work(struct work_struct *work)
4173 {
4174         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
4175                                                tx_timeout_work);
4176         bool report_failed = false;
4177         int err;
4178         int i;
4179
4180         rtnl_lock();
4181         mutex_lock(&priv->state_lock);
4182
4183         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
4184                 goto unlock;
4185
4186         for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
4187                 struct netdev_queue *dev_queue =
4188                         netdev_get_tx_queue(priv->netdev, i);
4189                 struct mlx5e_txqsq *sq = priv->txq2sq[i];
4190
4191                 if (!netif_xmit_stopped(dev_queue))
4192                         continue;
4193
4194                 if (mlx5e_tx_reporter_timeout(sq))
4195                         report_failed = true;
4196         }
4197
4198         if (!report_failed)
4199                 goto unlock;
4200
4201         err = mlx5e_safe_reopen_channels(priv);
4202         if (err)
4203                 netdev_err(priv->netdev,
4204                            "mlx5e_safe_reopen_channels failed recovering from a tx_timeout, err(%d).\n",
4205                            err);
4206
4207 unlock:
4208         mutex_unlock(&priv->state_lock);
4209         rtnl_unlock();
4210 }
4211
4212 static void mlx5e_tx_timeout(struct net_device *dev)
4213 {
4214         struct mlx5e_priv *priv = netdev_priv(dev);
4215
4216         netdev_err(dev, "TX timeout detected\n");
4217         queue_work(priv->wq, &priv->tx_timeout_work);
4218 }
4219
4220 static int mlx5e_xdp_allowed(struct mlx5e_priv *priv, struct bpf_prog *prog)
4221 {
4222         struct net_device *netdev = priv->netdev;
4223         struct mlx5e_channels new_channels = {};
4224
4225         if (priv->channels.params.lro_en) {
4226                 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
4227                 return -EINVAL;
4228         }
4229
4230         if (MLX5_IPSEC_DEV(priv->mdev)) {
4231                 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
4232                 return -EINVAL;
4233         }
4234
4235         new_channels.params = priv->channels.params;
4236         new_channels.params.xdp_prog = prog;
4237
4238         if (!mlx5e_rx_is_linear_skb(priv->mdev, &new_channels.params)) {
4239                 netdev_warn(netdev, "XDP is not allowed with MTU(%d) > %d\n",
4240                             new_channels.params.sw_mtu, MLX5E_XDP_MAX_MTU);
4241                 return -EINVAL;
4242         }
4243
4244         return 0;
4245 }
4246
4247 static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
4248 {
4249         struct mlx5e_priv *priv = netdev_priv(netdev);
4250         struct bpf_prog *old_prog;
4251         bool reset, was_opened;
4252         int err = 0;
4253         int i;
4254
4255         mutex_lock(&priv->state_lock);
4256
4257         if (prog) {
4258                 err = mlx5e_xdp_allowed(priv, prog);
4259                 if (err)
4260                         goto unlock;
4261         }
4262
4263         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
4264         /* no need for full reset when exchanging programs */
4265         reset = (!priv->channels.params.xdp_prog || !prog);
4266
4267         if (was_opened && reset)
4268                 mlx5e_close_locked(netdev);
4269         if (was_opened && !reset) {
4270                 /* num_channels is invariant here, so we can take the
4271                  * batched reference right upfront.
4272                  */
4273                 prog = bpf_prog_add(prog, priv->channels.num);
4274                 if (IS_ERR(prog)) {
4275                         err = PTR_ERR(prog);
4276                         goto unlock;
4277                 }
4278         }
4279
4280         /* exchange programs, extra prog reference we got from caller
4281          * as long as we don't fail from this point onwards.
4282          */
4283         old_prog = xchg(&priv->channels.params.xdp_prog, prog);
4284         if (old_prog)
4285                 bpf_prog_put(old_prog);
4286
4287         if (reset) /* change RQ type according to priv->xdp_prog */
4288                 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
4289
4290         if (was_opened && reset)
4291                 mlx5e_open_locked(netdev);
4292
4293         if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
4294                 goto unlock;
4295
4296         /* exchanging programs w/o reset, we update ref counts on behalf
4297          * of the channels RQs here.
4298          */
4299         for (i = 0; i < priv->channels.num; i++) {
4300                 struct mlx5e_channel *c = priv->channels.c[i];
4301
4302                 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4303                 napi_synchronize(&c->napi);
4304                 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
4305
4306                 old_prog = xchg(&c->rq.xdp_prog, prog);
4307
4308                 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
4309                 /* napi_schedule in case we have missed anything */
4310                 napi_schedule(&c->napi);
4311
4312                 if (old_prog)
4313                         bpf_prog_put(old_prog);
4314         }
4315
4316 unlock:
4317         mutex_unlock(&priv->state_lock);
4318         return err;
4319 }
4320
4321 static u32 mlx5e_xdp_query(struct net_device *dev)
4322 {
4323         struct mlx5e_priv *priv = netdev_priv(dev);
4324         const struct bpf_prog *xdp_prog;
4325         u32 prog_id = 0;
4326
4327         mutex_lock(&priv->state_lock);
4328         xdp_prog = priv->channels.params.xdp_prog;
4329         if (xdp_prog)
4330                 prog_id = xdp_prog->aux->id;
4331         mutex_unlock(&priv->state_lock);
4332
4333         return prog_id;
4334 }
4335
4336 static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
4337 {
4338         switch (xdp->command) {
4339         case XDP_SETUP_PROG:
4340                 return mlx5e_xdp_set(dev, xdp->prog);
4341         case XDP_QUERY_PROG:
4342                 xdp->prog_id = mlx5e_xdp_query(dev);
4343                 return 0;
4344         default:
4345                 return -EINVAL;
4346         }
4347 }
4348
4349 #ifdef CONFIG_MLX5_ESWITCH
4350 static int mlx5e_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
4351                                 struct net_device *dev, u32 filter_mask,
4352                                 int nlflags)
4353 {
4354         struct mlx5e_priv *priv = netdev_priv(dev);
4355         struct mlx5_core_dev *mdev = priv->mdev;
4356         u8 mode, setting;
4357         int err;
4358
4359         err = mlx5_eswitch_get_vepa(mdev->priv.eswitch, &setting);
4360         if (err)
4361                 return err;
4362         mode = setting ? BRIDGE_MODE_VEPA : BRIDGE_MODE_VEB;
4363         return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
4364                                        mode,
4365                                        0, 0, nlflags, filter_mask, NULL);
4366 }
4367
4368 static int mlx5e_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
4369                                 u16 flags, struct netlink_ext_ack *extack)
4370 {
4371         struct mlx5e_priv *priv = netdev_priv(dev);
4372         struct mlx5_core_dev *mdev = priv->mdev;
4373         struct nlattr *attr, *br_spec;
4374         u16 mode = BRIDGE_MODE_UNDEF;
4375         u8 setting;
4376         int rem;
4377
4378         br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4379         if (!br_spec)
4380                 return -EINVAL;
4381
4382         nla_for_each_nested(attr, br_spec, rem) {
4383                 if (nla_type(attr) != IFLA_BRIDGE_MODE)
4384                         continue;
4385
4386                 if (nla_len(attr) < sizeof(mode))
4387                         return -EINVAL;
4388
4389                 mode = nla_get_u16(attr);
4390                 if (mode > BRIDGE_MODE_VEPA)
4391                         return -EINVAL;
4392
4393                 break;
4394         }
4395
4396         if (mode == BRIDGE_MODE_UNDEF)
4397                 return -EINVAL;
4398
4399         setting = (mode == BRIDGE_MODE_VEPA) ?  1 : 0;
4400         return mlx5_eswitch_set_vepa(mdev->priv.eswitch, setting);
4401 }
4402 #endif
4403
4404 const struct net_device_ops mlx5e_netdev_ops = {
4405         .ndo_open                = mlx5e_open,
4406         .ndo_stop                = mlx5e_close,
4407         .ndo_start_xmit          = mlx5e_xmit,
4408         .ndo_setup_tc            = mlx5e_setup_tc,
4409         .ndo_select_queue        = mlx5e_select_queue,
4410         .ndo_get_stats64         = mlx5e_get_stats,
4411         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
4412         .ndo_set_mac_address     = mlx5e_set_mac,
4413         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
4414         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
4415         .ndo_set_features        = mlx5e_set_features,
4416         .ndo_fix_features        = mlx5e_fix_features,
4417         .ndo_change_mtu          = mlx5e_change_nic_mtu,
4418         .ndo_do_ioctl            = mlx5e_ioctl,
4419         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
4420         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
4421         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
4422         .ndo_features_check      = mlx5e_features_check,
4423         .ndo_tx_timeout          = mlx5e_tx_timeout,
4424         .ndo_bpf                 = mlx5e_xdp,
4425         .ndo_xdp_xmit            = mlx5e_xdp_xmit,
4426 #ifdef CONFIG_MLX5_EN_ARFS
4427         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
4428 #endif
4429 #ifdef CONFIG_MLX5_ESWITCH
4430         .ndo_bridge_setlink      = mlx5e_bridge_setlink,
4431         .ndo_bridge_getlink      = mlx5e_bridge_getlink,
4432
4433         /* SRIOV E-Switch NDOs */
4434         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
4435         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
4436         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
4437         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
4438         .ndo_set_vf_rate         = mlx5e_set_vf_rate,
4439         .ndo_get_vf_config       = mlx5e_get_vf_config,
4440         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
4441         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
4442 #endif
4443 };
4444
4445 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4446 {
4447         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4448                 return -EOPNOTSUPP;
4449         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4450             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4451             !MLX5_CAP_ETH(mdev, csum_cap) ||
4452             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4453             !MLX5_CAP_ETH(mdev, vlan_cap) ||
4454             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4455             MLX5_CAP_FLOWTABLE(mdev,
4456                                flow_table_properties_nic_receive.max_ft_level)
4457                                < 3) {
4458                 mlx5_core_warn(mdev,
4459                                "Not creating net device, some required device capabilities are missing\n");
4460                 return -EOPNOTSUPP;
4461         }
4462         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4463                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4464         if (!MLX5_CAP_GEN(mdev, cq_moderation))
4465                 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4466
4467         return 0;
4468 }
4469
4470 void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4471                                    int num_channels)
4472 {
4473         int i;
4474
4475         for (i = 0; i < len; i++)
4476                 indirection_rqt[i] = i % num_channels;
4477 }
4478
4479 static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4480 {
4481         u32 link_speed = 0;
4482         u32 pci_bw = 0;
4483
4484         mlx5e_port_max_linkspeed(mdev, &link_speed);
4485         pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4486         mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4487                            link_speed, pci_bw);
4488
4489 #define MLX5E_SLOW_PCI_RATIO (2)
4490
4491         return link_speed && pci_bw &&
4492                 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4493 }
4494
4495 static struct net_dim_cq_moder mlx5e_get_def_tx_moderation(u8 cq_period_mode)
4496 {
4497         struct net_dim_cq_moder moder;
4498
4499         moder.cq_period_mode = cq_period_mode;
4500         moder.pkts = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4501         moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4502         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4503                 moder.usec = MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4504
4505         return moder;
4506 }
4507
4508 static struct net_dim_cq_moder mlx5e_get_def_rx_moderation(u8 cq_period_mode)
4509 {
4510         struct net_dim_cq_moder moder;
4511
4512         moder.cq_period_mode = cq_period_mode;
4513         moder.pkts = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4514         moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4515         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4516                 moder.usec = MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4517
4518         return moder;
4519 }
4520
4521 static u8 mlx5_to_net_dim_cq_period_mode(u8 cq_period_mode)
4522 {
4523         return cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE ?
4524                 NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE :
4525                 NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
4526 }
4527
4528 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4529 {
4530         if (params->tx_dim_enabled) {
4531                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4532
4533                 params->tx_cq_moderation = net_dim_get_def_tx_moderation(dim_period_mode);
4534         } else {
4535                 params->tx_cq_moderation = mlx5e_get_def_tx_moderation(cq_period_mode);
4536         }
4537
4538         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4539                         params->tx_cq_moderation.cq_period_mode ==
4540                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4541 }
4542
4543 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4544 {
4545         if (params->rx_dim_enabled) {
4546                 u8 dim_period_mode = mlx5_to_net_dim_cq_period_mode(cq_period_mode);
4547
4548                 params->rx_cq_moderation = net_dim_get_def_rx_moderation(dim_period_mode);
4549         } else {
4550                 params->rx_cq_moderation = mlx5e_get_def_rx_moderation(cq_period_mode);
4551         }
4552
4553         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4554                         params->rx_cq_moderation.cq_period_mode ==
4555                                 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4556 }
4557
4558 static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4559 {
4560         int i;
4561
4562         /* The supported periods are organized in ascending order */
4563         for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4564                 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4565                         break;
4566
4567         return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4568 }
4569
4570 void mlx5e_build_rq_params(struct mlx5_core_dev *mdev,
4571                            struct mlx5e_params *params)
4572 {
4573         /* Prefer Striding RQ, unless any of the following holds:
4574          * - Striding RQ configuration is not possible/supported.
4575          * - Slow PCI heuristic.
4576          * - Legacy RQ would use linear SKB while Striding RQ would use non-linear.
4577          */
4578         if (!slow_pci_heuristic(mdev) &&
4579             mlx5e_striding_rq_possible(mdev, params) &&
4580             (mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ||
4581              !mlx5e_rx_is_linear_skb(mdev, params)))
4582                 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ, true);
4583         mlx5e_set_rq_type(mdev, params);
4584         mlx5e_init_rq_type_params(mdev, params);
4585 }
4586
4587 void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params,
4588                             u16 num_channels)
4589 {
4590         enum mlx5e_traffic_types tt;
4591
4592         rss_params->hfunc = ETH_RSS_HASH_TOP;
4593         netdev_rss_key_fill(rss_params->toeplitz_hash_key,
4594                             sizeof(rss_params->toeplitz_hash_key));
4595         mlx5e_build_default_indir_rqt(rss_params->indirection_rqt,
4596                                       MLX5E_INDIR_RQT_SIZE, num_channels);
4597         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
4598                 rss_params->rx_hash_fields[tt] =
4599                         tirc_default_config[tt].rx_hash_fields;
4600 }
4601
4602 void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4603                             struct mlx5e_rss_params *rss_params,
4604                             struct mlx5e_params *params,
4605                             u16 max_channels, u16 mtu)
4606 {
4607         u8 rx_cq_period_mode;
4608
4609         params->sw_mtu = mtu;
4610         params->hard_mtu = MLX5E_ETH_HARD_MTU;
4611         params->num_channels = max_channels;
4612         params->num_tc       = 1;
4613
4614         /* SQ */
4615         params->log_sq_size = is_kdump_kernel() ?
4616                 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4617                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4618
4619         /* XDP SQ */
4620         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_XDP_TX_MPWQE,
4621                         MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe));
4622
4623         /* set CQE compression */
4624         params->rx_cqe_compress_def = false;
4625         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4626             MLX5_CAP_GEN(mdev, vport_group_manager))
4627                 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4628
4629         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4630         MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, false);
4631
4632         /* RQ */
4633         mlx5e_build_rq_params(mdev, params);
4634
4635         /* HW LRO */
4636
4637         /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4638         if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4639                 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4640                         params->lro_en = !slow_pci_heuristic(mdev);
4641         params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4642
4643         /* CQ moderation params */
4644         rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4645                         MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4646                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4647         params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4648         params->tx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4649         mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4650         mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4651
4652         /* TX inline */
4653         params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4654
4655         /* RSS */
4656         mlx5e_build_rss_params(rss_params, params->num_channels);
4657 }
4658
4659 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4660 {
4661         struct mlx5e_priv *priv = netdev_priv(netdev);
4662
4663         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4664         if (is_zero_ether_addr(netdev->dev_addr) &&
4665             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4666                 eth_hw_addr_random(netdev);
4667                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4668         }
4669 }
4670
4671 static void mlx5e_build_nic_netdev(struct net_device *netdev)
4672 {
4673         struct mlx5e_priv *priv = netdev_priv(netdev);
4674         struct mlx5_core_dev *mdev = priv->mdev;
4675         bool fcs_supported;
4676         bool fcs_enabled;
4677
4678         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4679
4680         netdev->netdev_ops = &mlx5e_netdev_ops;
4681
4682 #ifdef CONFIG_MLX5_CORE_EN_DCB
4683         if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4684                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4685 #endif
4686
4687         netdev->watchdog_timeo    = 15 * HZ;
4688
4689         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
4690
4691         netdev->vlan_features    |= NETIF_F_SG;
4692         netdev->vlan_features    |= NETIF_F_IP_CSUM;
4693         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
4694         netdev->vlan_features    |= NETIF_F_GRO;
4695         netdev->vlan_features    |= NETIF_F_TSO;
4696         netdev->vlan_features    |= NETIF_F_TSO6;
4697         netdev->vlan_features    |= NETIF_F_RXCSUM;
4698         netdev->vlan_features    |= NETIF_F_RXHASH;
4699
4700         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_TX;
4701         netdev->hw_enc_features  |= NETIF_F_HW_VLAN_CTAG_RX;
4702
4703         if (!!MLX5_CAP_ETH(mdev, lro_cap) &&
4704             mlx5e_check_fragmented_striding_rq_cap(mdev))
4705                 netdev->vlan_features    |= NETIF_F_LRO;
4706
4707         netdev->hw_features       = netdev->vlan_features;
4708         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
4709         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
4710         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
4711         netdev->hw_features      |= NETIF_F_HW_VLAN_STAG_TX;
4712
4713         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev) ||
4714             MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4715                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4716                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4717                 netdev->hw_enc_features |= NETIF_F_TSO;
4718                 netdev->hw_enc_features |= NETIF_F_TSO6;
4719                 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4720         }
4721
4722         if (mlx5_vxlan_allowed(mdev->vxlan) || mlx5_geneve_tx_allowed(mdev)) {
4723                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
4724                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4725                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4726                                            NETIF_F_GSO_UDP_TUNNEL_CSUM;
4727                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4728         }
4729
4730         if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4731                 netdev->hw_features     |= NETIF_F_GSO_GRE |
4732                                            NETIF_F_GSO_GRE_CSUM;
4733                 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4734                                            NETIF_F_GSO_GRE_CSUM;
4735                 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4736                                                 NETIF_F_GSO_GRE_CSUM;
4737         }
4738
4739         netdev->hw_features                      |= NETIF_F_GSO_PARTIAL;
4740         netdev->gso_partial_features             |= NETIF_F_GSO_UDP_L4;
4741         netdev->hw_features                      |= NETIF_F_GSO_UDP_L4;
4742         netdev->features                         |= NETIF_F_GSO_UDP_L4;
4743
4744         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4745
4746         if (fcs_supported)
4747                 netdev->hw_features |= NETIF_F_RXALL;
4748
4749         if (MLX5_CAP_ETH(mdev, scatter_fcs))
4750                 netdev->hw_features |= NETIF_F_RXFCS;
4751
4752         netdev->features          = netdev->hw_features;
4753         if (!priv->channels.params.lro_en)
4754                 netdev->features  &= ~NETIF_F_LRO;
4755
4756         if (fcs_enabled)
4757                 netdev->features  &= ~NETIF_F_RXALL;
4758
4759         if (!priv->channels.params.scatter_fcs_en)
4760                 netdev->features  &= ~NETIF_F_RXFCS;
4761
4762 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4763         if (FT_CAP(flow_modify_en) &&
4764             FT_CAP(modify_root) &&
4765             FT_CAP(identified_miss_table_mode) &&
4766             FT_CAP(flow_table_modify)) {
4767 #ifdef CONFIG_MLX5_ESWITCH
4768                 netdev->hw_features      |= NETIF_F_HW_TC;
4769 #endif
4770 #ifdef CONFIG_MLX5_EN_ARFS
4771                 netdev->hw_features      |= NETIF_F_NTUPLE;
4772 #endif
4773         }
4774
4775         netdev->features         |= NETIF_F_HIGHDMA;
4776         netdev->features         |= NETIF_F_HW_VLAN_STAG_FILTER;
4777
4778         netdev->priv_flags       |= IFF_UNICAST_FLT;
4779
4780         mlx5e_set_netdev_dev_addr(netdev);
4781         mlx5e_ipsec_build_netdev(priv);
4782         mlx5e_tls_build_netdev(priv);
4783 }
4784
4785 void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4786 {
4787         struct mlx5_core_dev *mdev = priv->mdev;
4788         int err;
4789
4790         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4791         if (err) {
4792                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4793                 priv->q_counter = 0;
4794         }
4795
4796         err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4797         if (err) {
4798                 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4799                 priv->drop_rq_q_counter = 0;
4800         }
4801 }
4802
4803 void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4804 {
4805         if (priv->q_counter)
4806                 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4807
4808         if (priv->drop_rq_q_counter)
4809                 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4810 }
4811
4812 static int mlx5e_nic_init(struct mlx5_core_dev *mdev,
4813                           struct net_device *netdev,
4814                           const struct mlx5e_profile *profile,
4815                           void *ppriv)
4816 {
4817         struct mlx5e_priv *priv = netdev_priv(netdev);
4818         struct mlx5e_rss_params *rss = &priv->rss_params;
4819         int err;
4820
4821         err = mlx5e_netdev_init(netdev, priv, mdev, profile, ppriv);
4822         if (err)
4823                 return err;
4824
4825         mlx5e_build_nic_params(mdev, rss, &priv->channels.params,
4826                                mlx5e_get_netdev_max_channels(netdev),
4827                                netdev->mtu);
4828
4829         mlx5e_timestamp_init(priv);
4830
4831         err = mlx5e_ipsec_init(priv);
4832         if (err)
4833                 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4834         err = mlx5e_tls_init(priv);
4835         if (err)
4836                 mlx5_core_err(mdev, "TLS initialization failed, %d\n", err);
4837         mlx5e_build_nic_netdev(netdev);
4838         mlx5e_build_tc2txq_maps(priv);
4839
4840         return 0;
4841 }
4842
4843 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4844 {
4845         mlx5e_tls_cleanup(priv);
4846         mlx5e_ipsec_cleanup(priv);
4847         mlx5e_netdev_cleanup(priv->netdev, priv);
4848 }
4849
4850 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4851 {
4852         struct mlx5_core_dev *mdev = priv->mdev;
4853         int err;
4854
4855         mlx5e_create_q_counters(priv);
4856
4857         err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4858         if (err) {
4859                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4860                 goto err_destroy_q_counters;
4861         }
4862
4863         err = mlx5e_create_indirect_rqt(priv);
4864         if (err)
4865                 goto err_close_drop_rq;
4866
4867         err = mlx5e_create_direct_rqts(priv);
4868         if (err)
4869                 goto err_destroy_indirect_rqts;
4870
4871         err = mlx5e_create_indirect_tirs(priv, true);
4872         if (err)
4873                 goto err_destroy_direct_rqts;
4874
4875         err = mlx5e_create_direct_tirs(priv);
4876         if (err)
4877                 goto err_destroy_indirect_tirs;
4878
4879         err = mlx5e_create_flow_steering(priv);
4880         if (err) {
4881                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4882                 goto err_destroy_direct_tirs;
4883         }
4884
4885         err = mlx5e_tc_nic_init(priv);
4886         if (err)
4887                 goto err_destroy_flow_steering;
4888
4889         return 0;
4890
4891 err_destroy_flow_steering:
4892         mlx5e_destroy_flow_steering(priv);
4893 err_destroy_direct_tirs:
4894         mlx5e_destroy_direct_tirs(priv);
4895 err_destroy_indirect_tirs:
4896         mlx5e_destroy_indirect_tirs(priv, true);
4897 err_destroy_direct_rqts:
4898         mlx5e_destroy_direct_rqts(priv);
4899 err_destroy_indirect_rqts:
4900         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4901 err_close_drop_rq:
4902         mlx5e_close_drop_rq(&priv->drop_rq);
4903 err_destroy_q_counters:
4904         mlx5e_destroy_q_counters(priv);
4905         return err;
4906 }
4907
4908 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4909 {
4910         mlx5e_tc_nic_cleanup(priv);
4911         mlx5e_destroy_flow_steering(priv);
4912         mlx5e_destroy_direct_tirs(priv);
4913         mlx5e_destroy_indirect_tirs(priv, true);
4914         mlx5e_destroy_direct_rqts(priv);
4915         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4916         mlx5e_close_drop_rq(&priv->drop_rq);
4917         mlx5e_destroy_q_counters(priv);
4918 }
4919
4920 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4921 {
4922         int err;
4923
4924         err = mlx5e_create_tises(priv);
4925         if (err) {
4926                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4927                 return err;
4928         }
4929
4930 #ifdef CONFIG_MLX5_CORE_EN_DCB
4931         mlx5e_dcbnl_initialize(priv);
4932 #endif
4933         mlx5e_tx_reporter_create(priv);
4934         return 0;
4935 }
4936
4937 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4938 {
4939         struct net_device *netdev = priv->netdev;
4940         struct mlx5_core_dev *mdev = priv->mdev;
4941
4942         mlx5e_init_l2_addr(priv);
4943
4944         /* Marking the link as currently not needed by the Driver */
4945         if (!netif_running(netdev))
4946                 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4947
4948         mlx5e_set_netdev_mtu_boundaries(priv);
4949         mlx5e_set_dev_port_mtu(priv);
4950
4951         mlx5_lag_add(mdev, netdev);
4952
4953         mlx5e_enable_async_events(priv);
4954         if (mlx5e_monitor_counter_supported(priv))
4955                 mlx5e_monitor_counter_init(priv);
4956
4957         if (netdev->reg_state != NETREG_REGISTERED)
4958                 return;
4959 #ifdef CONFIG_MLX5_CORE_EN_DCB
4960         mlx5e_dcbnl_init_app(priv);
4961 #endif
4962
4963         queue_work(priv->wq, &priv->set_rx_mode_work);
4964
4965         rtnl_lock();
4966         if (netif_running(netdev))
4967                 mlx5e_open(netdev);
4968         netif_device_attach(netdev);
4969         rtnl_unlock();
4970 }
4971
4972 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4973 {
4974         struct mlx5_core_dev *mdev = priv->mdev;
4975
4976 #ifdef CONFIG_MLX5_CORE_EN_DCB
4977         if (priv->netdev->reg_state == NETREG_REGISTERED)
4978                 mlx5e_dcbnl_delete_app(priv);
4979 #endif
4980
4981         rtnl_lock();
4982         if (netif_running(priv->netdev))
4983                 mlx5e_close(priv->netdev);
4984         netif_device_detach(priv->netdev);
4985         rtnl_unlock();
4986
4987         queue_work(priv->wq, &priv->set_rx_mode_work);
4988
4989         if (mlx5e_monitor_counter_supported(priv))
4990                 mlx5e_monitor_counter_cleanup(priv);
4991
4992         mlx5e_disable_async_events(priv);
4993         mlx5_lag_remove(mdev);
4994 }
4995
4996 static const struct mlx5e_profile mlx5e_nic_profile = {
4997         .init              = mlx5e_nic_init,
4998         .cleanup           = mlx5e_nic_cleanup,
4999         .init_rx           = mlx5e_init_nic_rx,
5000         .cleanup_rx        = mlx5e_cleanup_nic_rx,
5001         .init_tx           = mlx5e_init_nic_tx,
5002         .cleanup_tx        = mlx5e_cleanup_nic_tx,
5003         .enable            = mlx5e_nic_enable,
5004         .disable           = mlx5e_nic_disable,
5005         .update_stats      = mlx5e_update_ndo_stats,
5006         .update_carrier    = mlx5e_update_carrier,
5007         .rx_handlers.handle_rx_cqe       = mlx5e_handle_rx_cqe,
5008         .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
5009         .max_tc            = MLX5E_MAX_NUM_TC,
5010 };
5011
5012 /* mlx5e generic netdev management API (move to en_common.c) */
5013
5014 /* mlx5e_netdev_init/cleanup must be called from profile->init/cleanup callbacks */
5015 int mlx5e_netdev_init(struct net_device *netdev,
5016                       struct mlx5e_priv *priv,
5017                       struct mlx5_core_dev *mdev,
5018                       const struct mlx5e_profile *profile,
5019                       void *ppriv)
5020 {
5021         /* priv init */
5022         priv->mdev        = mdev;
5023         priv->netdev      = netdev;
5024         priv->profile     = profile;
5025         priv->ppriv       = ppriv;
5026         priv->msglevel    = MLX5E_MSG_LEVEL;
5027         priv->max_opened_tc = 1;
5028
5029         mutex_init(&priv->state_lock);
5030         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
5031         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
5032         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
5033         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
5034
5035         priv->wq = create_singlethread_workqueue("mlx5e");
5036         if (!priv->wq)
5037                 return -ENOMEM;
5038
5039         /* netdev init */
5040         netif_carrier_off(netdev);
5041
5042 #ifdef CONFIG_MLX5_EN_ARFS
5043         netdev->rx_cpu_rmap =  mlx5_eq_table_get_rmap(mdev);
5044 #endif
5045
5046         return 0;
5047 }
5048
5049 void mlx5e_netdev_cleanup(struct net_device *netdev, struct mlx5e_priv *priv)
5050 {
5051         destroy_workqueue(priv->wq);
5052 }
5053
5054 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
5055                                        const struct mlx5e_profile *profile,
5056                                        int nch,
5057                                        void *ppriv)
5058 {
5059         struct net_device *netdev;
5060         int err;
5061
5062         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
5063                                     nch * profile->max_tc,
5064                                     nch);
5065         if (!netdev) {
5066                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
5067                 return NULL;
5068         }
5069
5070         err = profile->init(mdev, netdev, profile, ppriv);
5071         if (err) {
5072                 mlx5_core_err(mdev, "failed to init mlx5e profile %d\n", err);
5073                 goto err_free_netdev;
5074         }
5075
5076         return netdev;
5077
5078 err_free_netdev:
5079         free_netdev(netdev);
5080
5081         return NULL;
5082 }
5083
5084 int mlx5e_attach_netdev(struct mlx5e_priv *priv)
5085 {
5086         const struct mlx5e_profile *profile;
5087         int max_nch;
5088         int err;
5089
5090         profile = priv->profile;
5091         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
5092
5093         /* max number of channels may have changed */
5094         max_nch = mlx5e_get_max_num_channels(priv->mdev);
5095         if (priv->channels.params.num_channels > max_nch) {
5096                 mlx5_core_warn(priv->mdev, "MLX5E: Reducing number of channels to %d\n", max_nch);
5097                 priv->channels.params.num_channels = max_nch;
5098                 mlx5e_build_default_indir_rqt(priv->rss_params.indirection_rqt,
5099                                               MLX5E_INDIR_RQT_SIZE, max_nch);
5100         }
5101
5102         err = profile->init_tx(priv);
5103         if (err)
5104                 goto out;
5105
5106         err = profile->init_rx(priv);
5107         if (err)
5108                 goto err_cleanup_tx;
5109
5110         if (profile->enable)
5111                 profile->enable(priv);
5112
5113         return 0;
5114
5115 err_cleanup_tx:
5116         profile->cleanup_tx(priv);
5117
5118 out:
5119         return err;
5120 }
5121
5122 void mlx5e_detach_netdev(struct mlx5e_priv *priv)
5123 {
5124         const struct mlx5e_profile *profile = priv->profile;
5125
5126         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
5127
5128         if (profile->disable)
5129                 profile->disable(priv);
5130         flush_workqueue(priv->wq);
5131
5132         profile->cleanup_rx(priv);
5133         profile->cleanup_tx(priv);
5134         cancel_work_sync(&priv->update_stats_work);
5135 }
5136
5137 void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
5138 {
5139         const struct mlx5e_profile *profile = priv->profile;
5140         struct net_device *netdev = priv->netdev;
5141
5142         if (profile->cleanup)
5143                 profile->cleanup(priv);
5144         free_netdev(netdev);
5145 }
5146
5147 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
5148  * hardware contexts and to connect it to the current netdev.
5149  */
5150 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
5151 {
5152         struct mlx5e_priv *priv = vpriv;
5153         struct net_device *netdev = priv->netdev;
5154         int err;
5155
5156         if (netif_device_present(netdev))
5157                 return 0;
5158
5159         err = mlx5e_create_mdev_resources(mdev);
5160         if (err)
5161                 return err;
5162
5163         err = mlx5e_attach_netdev(priv);
5164         if (err) {
5165                 mlx5e_destroy_mdev_resources(mdev);
5166                 return err;
5167         }
5168
5169         return 0;
5170 }
5171
5172 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
5173 {
5174         struct mlx5e_priv *priv = vpriv;
5175         struct net_device *netdev = priv->netdev;
5176
5177         if (!netif_device_present(netdev))
5178                 return;
5179
5180         mlx5e_detach_netdev(priv);
5181         mlx5e_destroy_mdev_resources(mdev);
5182 }
5183
5184 static void *mlx5e_add(struct mlx5_core_dev *mdev)
5185 {
5186         struct net_device *netdev;
5187         void *priv;
5188         int err;
5189         int nch;
5190
5191         err = mlx5e_check_required_hca_cap(mdev);
5192         if (err)
5193                 return NULL;
5194
5195 #ifdef CONFIG_MLX5_ESWITCH
5196         if (MLX5_ESWITCH_MANAGER(mdev) &&
5197             mlx5_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
5198                 mlx5e_rep_register_vport_reps(mdev);
5199                 return mdev;
5200         }
5201 #endif
5202
5203         nch = mlx5e_get_max_num_channels(mdev);
5204         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, nch, NULL);
5205         if (!netdev) {
5206                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
5207                 return NULL;
5208         }
5209
5210         priv = netdev_priv(netdev);
5211
5212         err = mlx5e_attach(mdev, priv);
5213         if (err) {
5214                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
5215                 goto err_destroy_netdev;
5216         }
5217
5218         err = register_netdev(netdev);
5219         if (err) {
5220                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
5221                 goto err_detach;
5222         }
5223
5224 #ifdef CONFIG_MLX5_CORE_EN_DCB
5225         mlx5e_dcbnl_init_app(priv);
5226 #endif
5227         return priv;
5228
5229 err_detach:
5230         mlx5e_detach(mdev, priv);
5231 err_destroy_netdev:
5232         mlx5e_destroy_netdev(priv);
5233         return NULL;
5234 }
5235
5236 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
5237 {
5238         struct mlx5e_priv *priv;
5239
5240 #ifdef CONFIG_MLX5_ESWITCH
5241         if (MLX5_ESWITCH_MANAGER(mdev) && vpriv == mdev) {
5242                 mlx5e_rep_unregister_vport_reps(mdev);
5243                 return;
5244         }
5245 #endif
5246         priv = vpriv;
5247 #ifdef CONFIG_MLX5_CORE_EN_DCB
5248         mlx5e_dcbnl_delete_app(priv);
5249 #endif
5250         unregister_netdev(priv->netdev);
5251         mlx5e_detach(mdev, vpriv);
5252         mlx5e_destroy_netdev(priv);
5253 }
5254
5255 static struct mlx5_interface mlx5e_interface = {
5256         .add       = mlx5e_add,
5257         .remove    = mlx5e_remove,
5258         .attach    = mlx5e_attach,
5259         .detach    = mlx5e_detach,
5260         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
5261 };
5262
5263 void mlx5e_init(void)
5264 {
5265         mlx5e_ipsec_build_inverse_table();
5266         mlx5e_build_ptys2ethtool_map();
5267         mlx5_register_interface(&mlx5e_interface);
5268 }
5269
5270 void mlx5e_cleanup(void)
5271 {
5272         mlx5_unregister_interface(&mlx5e_interface);
5273 }